Merge branch 'mpi-master' into wip-k-fmlpwip-k-fmlp

Conflicts:
	litmus/sched_cedf.c

1 files changed, 444 insertions, 79 deletions

diff --git a/drivers/usb/host/pci-quirks.c b/drivers/usb/host/pci-quirks.c
index 83b5f9cea85a..fd930618c28f 100644
--- a/drivers/usb/host/pci-quirks.c
+++ b/drivers/usb/host/pci-quirks.c
@@ -14,6 +14,7 @@
 #include <linux/init.h>
 #include <linux/delay.h>
 #include <linux/acpi.h>
+#include <linux/dmi.h>
 #include "pci-quirks.h"
 #include "xhci-ext-caps.h"
 
@@ -52,6 +53,298 @@
 #define EHCI_USBLEGCTLSTS       4               /* legacy control/status */
 #define EHCI_USBLEGCTLSTS_SOOE  (1 << 13)       /* SMI on ownership change */
 
+/* AMD quirk use */
+#define AB_REG_BAR_LOW          0xe0
+#define AB_REG_BAR_HIGH         0xe1
+#define AB_REG_BAR_SB700        0xf0
+#define AB_INDX(addr)           ((addr) + 0x00)
+#define AB_DATA(addr)           ((addr) + 0x04)
+#define AX_INDXC                0x30
+#define AX_DATAC                0x34
+
+#define NB_PCIE_INDX_ADDR       0xe0
+#define NB_PCIE_INDX_DATA       0xe4
+#define PCIE_P_CNTL             0x10040
+#define BIF_NB                  0x10002
+#define NB_PIF0_PWRDOWN_0       0x01100012
+#define NB_PIF0_PWRDOWN_1       0x01100013
+
+#define USB_INTEL_XUSB2PR      0xD0
+#define USB_INTEL_USB3_PSSEN   0xD8
+
+static struct amd_chipset_info {
+        struct pci_dev  *nb_dev;
+        struct pci_dev  *smbus_dev;
+        int nb_type;
+        int sb_type;
+        int isoc_reqs;
+        int probe_count;
+        int probe_result;
+} amd_chipset;
+
+static DEFINE_SPINLOCK(amd_lock);
+
+int usb_amd_find_chipset_info(void)
+{
+        u8 rev = 0;
+        unsigned long flags;
+        struct amd_chipset_info info;
+        int ret;
+
+        spin_lock_irqsave(&amd_lock, flags);
+
+        /* probe only once */
+        if (amd_chipset.probe_count > 0) {
+                amd_chipset.probe_count++;
+                spin_unlock_irqrestore(&amd_lock, flags);
+                return amd_chipset.probe_result;
+        }
+        memset(&info, 0, sizeof(info));
+        spin_unlock_irqrestore(&amd_lock, flags);
+
+        info.smbus_dev = pci_get_device(PCI_VENDOR_ID_ATI, 0x4385, NULL);
+        if (info.smbus_dev) {
+                rev = info.smbus_dev->revision;
+                if (rev >= 0x40)
+                        info.sb_type = 1;
+                else if (rev >= 0x30 && rev <= 0x3b)
+                        info.sb_type = 3;
+        } else {
+                info.smbus_dev = pci_get_device(PCI_VENDOR_ID_AMD,
+                                                0x780b, NULL);
+                if (!info.smbus_dev) {
+                        ret = 0;
+                        goto commit;
+                }
+
+                rev = info.smbus_dev->revision;
+                if (rev >= 0x11 && rev <= 0x18)
+                        info.sb_type = 2;
+        }
+
+        if (info.sb_type == 0) {
+                if (info.smbus_dev) {
+                        pci_dev_put(info.smbus_dev);
+                        info.smbus_dev = NULL;
+                }
+                ret = 0;
+                goto commit;
+        }
+
+        info.nb_dev = pci_get_device(PCI_VENDOR_ID_AMD, 0x9601, NULL);
+        if (info.nb_dev) {
+                info.nb_type = 1;
+        } else {
+                info.nb_dev = pci_get_device(PCI_VENDOR_ID_AMD, 0x1510, NULL);
+                if (info.nb_dev) {
+                        info.nb_type = 2;
+                } else {
+                        info.nb_dev = pci_get_device(PCI_VENDOR_ID_AMD,
+                                                     0x9600, NULL);
+                        if (info.nb_dev)
+                                info.nb_type = 3;
+                }
+        }
+
+        ret = info.probe_result = 1;
+        printk(KERN_DEBUG "QUIRK: Enable AMD PLL fix\n");
+
+commit:
+
+        spin_lock_irqsave(&amd_lock, flags);
+        if (amd_chipset.probe_count > 0) {
+                /* race - someone else was faster - drop devices */
+
+                /* Mark that we where here */
+                amd_chipset.probe_count++;
+                ret = amd_chipset.probe_result;
+
+                spin_unlock_irqrestore(&amd_lock, flags);
+
+                if (info.nb_dev)
+                        pci_dev_put(info.nb_dev);
+                if (info.smbus_dev)
+                        pci_dev_put(info.smbus_dev);
+
+        } else {
+                /* no race - commit the result */
+                info.probe_count++;
+                amd_chipset = info;
+                spin_unlock_irqrestore(&amd_lock, flags);
+        }
+
+        return ret;
+}
+EXPORT_SYMBOL_GPL(usb_amd_find_chipset_info);
+
+/*
+ * The hardware normally enables the A-link power management feature, which
+ * lets the system lower the power consumption in idle states.
+ *
+ * This USB quirk prevents the link going into that lower power state
+ * during isochronous transfers.
+ *
+ * Without this quirk, isochronous stream on OHCI/EHCI/xHCI controllers of
+ * some AMD platforms may stutter or have breaks occasionally.
+ */
+static void usb_amd_quirk_pll(int disable)
+{
+        u32 addr, addr_low, addr_high, val;
+        u32 bit = disable ? 0 : 1;
+        unsigned long flags;
+
+        spin_lock_irqsave(&amd_lock, flags);
+
+        if (disable) {
+                amd_chipset.isoc_reqs++;
+                if (amd_chipset.isoc_reqs > 1) {
+                        spin_unlock_irqrestore(&amd_lock, flags);
+                        return;
+                }
+        } else {
+                amd_chipset.isoc_reqs--;
+                if (amd_chipset.isoc_reqs > 0) {
+                        spin_unlock_irqrestore(&amd_lock, flags);
+                        return;
+                }
+        }
+
+        if (amd_chipset.sb_type == 1 || amd_chipset.sb_type == 2) {
+                outb_p(AB_REG_BAR_LOW, 0xcd6);
+                addr_low = inb_p(0xcd7);
+                outb_p(AB_REG_BAR_HIGH, 0xcd6);
+                addr_high = inb_p(0xcd7);
+                addr = addr_high << 8 | addr_low;
+
+                outl_p(0x30, AB_INDX(addr));
+                outl_p(0x40, AB_DATA(addr));
+                outl_p(0x34, AB_INDX(addr));
+                val = inl_p(AB_DATA(addr));
+        } else if (amd_chipset.sb_type == 3) {
+                pci_read_config_dword(amd_chipset.smbus_dev,
+                                        AB_REG_BAR_SB700, &addr);
+                outl(AX_INDXC, AB_INDX(addr));
+                outl(0x40, AB_DATA(addr));
+                outl(AX_DATAC, AB_INDX(addr));
+                val = inl(AB_DATA(addr));
+        } else {
+                spin_unlock_irqrestore(&amd_lock, flags);
+                return;
+        }
+
+        if (disable) {
+                val &= ~0x08;
+                val |= (1 << 4) | (1 << 9);
+        } else {
+                val |= 0x08;
+                val &= ~((1 << 4) | (1 << 9));
+        }
+        outl_p(val, AB_DATA(addr));
+
+        if (!amd_chipset.nb_dev) {
+                spin_unlock_irqrestore(&amd_lock, flags);
+                return;
+        }
+
+        if (amd_chipset.nb_type == 1 || amd_chipset.nb_type == 3) {
+                addr = PCIE_P_CNTL;
+                pci_write_config_dword(amd_chipset.nb_dev,
+                                        NB_PCIE_INDX_ADDR, addr);
+                pci_read_config_dword(amd_chipset.nb_dev,
+                                        NB_PCIE_INDX_DATA, &val);
+
+                val &= ~(1 | (1 << 3) | (1 << 4) | (1 << 9) | (1 << 12));
+                val |= bit | (bit << 3) | (bit << 12);
+                val |= ((!bit) << 4) | ((!bit) << 9);
+                pci_write_config_dword(amd_chipset.nb_dev,
+                                        NB_PCIE_INDX_DATA, val);
+
+                addr = BIF_NB;
+                pci_write_config_dword(amd_chipset.nb_dev,
+                                        NB_PCIE_INDX_ADDR, addr);
+                pci_read_config_dword(amd_chipset.nb_dev,
+                                        NB_PCIE_INDX_DATA, &val);
+                val &= ~(1 << 8);
+                val |= bit << 8;
+
+                pci_write_config_dword(amd_chipset.nb_dev,
+                                        NB_PCIE_INDX_DATA, val);
+        } else if (amd_chipset.nb_type == 2) {
+                addr = NB_PIF0_PWRDOWN_0;
+                pci_write_config_dword(amd_chipset.nb_dev,
+                                        NB_PCIE_INDX_ADDR, addr);
+                pci_read_config_dword(amd_chipset.nb_dev,
+                                        NB_PCIE_INDX_DATA, &val);
+                if (disable)
+                        val &= ~(0x3f << 7);
+                else
+                        val |= 0x3f << 7;
+
+                pci_write_config_dword(amd_chipset.nb_dev,
+                                        NB_PCIE_INDX_DATA, val);
+
+                addr = NB_PIF0_PWRDOWN_1;
+                pci_write_config_dword(amd_chipset.nb_dev,
+                                        NB_PCIE_INDX_ADDR, addr);
+                pci_read_config_dword(amd_chipset.nb_dev,
+                                        NB_PCIE_INDX_DATA, &val);
+                if (disable)
+                        val &= ~(0x3f << 7);
+                else
+                        val |= 0x3f << 7;
+
+                pci_write_config_dword(amd_chipset.nb_dev,
+                                        NB_PCIE_INDX_DATA, val);
+        }
+
+        spin_unlock_irqrestore(&amd_lock, flags);
+        return;
+}
+
+void usb_amd_quirk_pll_disable(void)
+{
+        usb_amd_quirk_pll(1);
+}
+EXPORT_SYMBOL_GPL(usb_amd_quirk_pll_disable);
+
+void usb_amd_quirk_pll_enable(void)
+{
+        usb_amd_quirk_pll(0);
+}
+EXPORT_SYMBOL_GPL(usb_amd_quirk_pll_enable);
+
+void usb_amd_dev_put(void)
+{
+        struct pci_dev *nb, *smbus;
+        unsigned long flags;
+
+        spin_lock_irqsave(&amd_lock, flags);
+
+        amd_chipset.probe_count--;
+        if (amd_chipset.probe_count > 0) {
+                spin_unlock_irqrestore(&amd_lock, flags);
+                return;
+        }
+
+        /* save them to pci_dev_put outside of spinlock */
+        nb    = amd_chipset.nb_dev;
+        smbus = amd_chipset.smbus_dev;
+
+        amd_chipset.nb_dev = NULL;
+        amd_chipset.smbus_dev = NULL;
+        amd_chipset.nb_type = 0;
+        amd_chipset.sb_type = 0;
+        amd_chipset.isoc_reqs = 0;
+        amd_chipset.probe_result = 0;
+
+        spin_unlock_irqrestore(&amd_lock, flags);
+
+        if (nb)
+                pci_dev_put(nb);
+        if (smbus)
+                pci_dev_put(smbus);
+}
+EXPORT_SYMBOL_GPL(usb_amd_dev_put);
 
 /*
  * Make sure the controller is completely inactive, unable to
@@ -169,6 +462,7 @@ static int __devinit mmio_resource_enabled(struct pci_dev *pdev, int idx)
 static void __devinit quirk_usb_handoff_ohci(struct pci_dev *pdev)
 {
         void __iomem *base;
+        u32 control;
 
         if (!mmio_resource_enabled(pdev, 0))
                 return;
@@ -177,10 +471,14 @@ static void __devinit quirk_usb_handoff_ohci(struct pci_dev *pdev)
         if (base == NULL)
                 return;
 
+        control = readl(base + OHCI_CONTROL);
+
 /* On PA-RISC, PDC can leave IR set incorrectly; ignore it there. */
-#ifndef __hppa__
-{
-        u32 control = readl(base + OHCI_CONTROL);
+#ifdef __hppa__
+#define OHCI_CTRL_MASK          (OHCI_CTRL_RWC | OHCI_CTRL_IR)
+#else
+#define OHCI_CTRL_MASK          OHCI_CTRL_RWC
+
         if (control & OHCI_CTRL_IR) {
                 int wait_time = 500; /* arbitrary; 5 seconds */
                 writel(OHCI_INTR_OC, base + OHCI_INTRENABLE);
@@ -194,13 +492,12 @@ static void __devinit quirk_usb_handoff_ohci(struct pci_dev *pdev)
                         dev_warn(&pdev->dev, "OHCI: BIOS handoff failed"
                                         " (BIOS bug?) %08x\n",
                                         readl(base + OHCI_CONTROL));
-
-                /* reset controller, preserving RWC */
-                writel(control & OHCI_CTRL_RWC, base + OHCI_CONTROL);
         }
-}
 #endif
 
+        /* reset controller, preserving RWC (and possibly IR) */
+        writel(control & OHCI_CTRL_MASK, base + OHCI_CONTROL);
+
         /*
          * disable interrupts
          */
@@ -210,14 +507,84 @@ static void __devinit quirk_usb_handoff_ohci(struct pci_dev *pdev)
         iounmap(base);
 }
 
+static void __devinit ehci_bios_handoff(struct pci_dev *pdev,
+                                        void __iomem *op_reg_base,
+                                        u32 cap, u8 offset)
+{
+        int try_handoff = 1, tried_handoff = 0;
+
+        /* The Pegatron Lucid (ExoPC) tablet sporadically waits for 90
+         * seconds trying the handoff on its unused controller.  Skip
+         * it. */
+        if (pdev->vendor == 0x8086 && pdev->device == 0x283a) {
+                const char *dmi_bn = dmi_get_system_info(DMI_BOARD_NAME);
+                const char *dmi_bv = dmi_get_system_info(DMI_BIOS_VERSION);
+                if (dmi_bn && !strcmp(dmi_bn, "EXOPG06411") &&
+                    dmi_bv && !strcmp(dmi_bv, "Lucid-CE-133"))
+                        try_handoff = 0;
+        }
+
+        if (try_handoff && (cap & EHCI_USBLEGSUP_BIOS)) {
+                dev_dbg(&pdev->dev, "EHCI: BIOS handoff\n");
+
+#if 0
+/* aleksey_gorelov@phoenix.com reports that some systems need SMI forced on,
+ * but that seems dubious in general (the BIOS left it off intentionally)
+ * and is known to prevent some systems from booting.  so we won't do this
+ * unless maybe we can determine when we're on a system that needs SMI forced.
+ */
+                /* BIOS workaround (?): be sure the pre-Linux code
+                 * receives the SMI
+                 */
+                pci_read_config_dword(pdev, offset + EHCI_USBLEGCTLSTS, &val);
+                pci_write_config_dword(pdev, offset + EHCI_USBLEGCTLSTS,
+                                       val | EHCI_USBLEGCTLSTS_SOOE);
+#endif
+
+                /* some systems get upset if this semaphore is
+                 * set for any other reason than forcing a BIOS
+                 * handoff..
+                 */
+                pci_write_config_byte(pdev, offset + 3, 1);
+        }
+
+        /* if boot firmware now owns EHCI, spin till it hands it over. */
+        if (try_handoff) {
+                int msec = 1000;
+                while ((cap & EHCI_USBLEGSUP_BIOS) && (msec > 0)) {
+                        tried_handoff = 1;
+                        msleep(10);
+                        msec -= 10;
+                        pci_read_config_dword(pdev, offset, &cap);
+                }
+        }
+
+        if (cap & EHCI_USBLEGSUP_BIOS) {
+                /* well, possibly buggy BIOS... try to shut it down,
+                 * and hope nothing goes too wrong
+                 */
+                if (try_handoff)
+                        dev_warn(&pdev->dev, "EHCI: BIOS handoff failed"
+                                 " (BIOS bug?) %08x\n", cap);
+                pci_write_config_byte(pdev, offset + 2, 0);
+        }
+
+        /* just in case, always disable EHCI SMIs */
+        pci_write_config_dword(pdev, offset + EHCI_USBLEGCTLSTS, 0);
+
+        /* If the BIOS ever owned the controller then we can't expect
+         * any power sessions to remain intact.
+         */
+        if (tried_handoff)
+                writel(0, op_reg_base + EHCI_CONFIGFLAG);
+}
+
 static void __devinit quirk_usb_disable_ehci(struct pci_dev *pdev)
 {
-        int wait_time, delta;
         void __iomem *base, *op_reg_base;
-        u32     hcc_params, val;
+        u32     hcc_params, cap, val;
         u8      offset, cap_length;
-        int     count = 256/4;
-        int     tried_handoff = 0;
+        int     wait_time, delta, count = 256/4;
 
         if (!mmio_resource_enabled(pdev, 0))
                 return;
@@ -236,77 +603,17 @@ static void __devinit quirk_usb_disable_ehci(struct pci_dev *pdev)
         hcc_params = readl(base + EHCI_HCC_PARAMS);
         offset = (hcc_params >> 8) & 0xff;
         while (offset && --count) {
-                u32             cap;
-                int             msec;
-
                 pci_read_config_dword(pdev, offset, &cap);
-                switch (cap & 0xff) {
-                case 1:                 /* BIOS/SMM/... handoff support */
-                        if ((cap & EHCI_USBLEGSUP_BIOS)) {
-                                dev_dbg(&pdev->dev, "EHCI: BIOS handoff\n");
 
-#if 0
-/* aleksey_gorelov@phoenix.com reports that some systems need SMI forced on,
- * but that seems dubious in general (the BIOS left it off intentionally)
- * and is known to prevent some systems from booting.  so we won't do this
- * unless maybe we can determine when we're on a system that needs SMI forced.
- */
-                                /* BIOS workaround (?): be sure the
-                                 * pre-Linux code receives the SMI
-                                 */
-                                pci_read_config_dword(pdev,
-                                                offset + EHCI_USBLEGCTLSTS,
-                                                &val);
-                                pci_write_config_dword(pdev,
-                                                offset + EHCI_USBLEGCTLSTS,
-                                                val | EHCI_USBLEGCTLSTS_SOOE);
-#endif
-
-                                /* some systems get upset if this semaphore is
-                                 * set for any other reason than forcing a BIOS
-                                 * handoff..
-                                 */
-                                pci_write_config_byte(pdev, offset + 3, 1);
-                        }
-
-                        /* if boot firmware now owns EHCI, spin till
-                         * it hands it over.
-                         */
-                        msec = 1000;
-                        while ((cap & EHCI_USBLEGSUP_BIOS) && (msec > 0)) {
-                                tried_handoff = 1;
-                                msleep(10);
-                                msec -= 10;
-                                pci_read_config_dword(pdev, offset, &cap);
-                        }
-
-                        if (cap & EHCI_USBLEGSUP_BIOS) {
-                                /* well, possibly buggy BIOS... try to shut
-                                 * it down, and hope nothing goes too wrong
-                                 */
-                                dev_warn(&pdev->dev, "EHCI: BIOS handoff failed"
-                                                " (BIOS bug?) %08x\n", cap);
-                                pci_write_config_byte(pdev, offset + 2, 0);
-                        }
-
-                        /* just in case, always disable EHCI SMIs */
-                        pci_write_config_dword(pdev,
-                                        offset + EHCI_USBLEGCTLSTS,
-                                        0);
-
-                        /* If the BIOS ever owned the controller then we
-                         * can't expect any power sessions to remain intact.
-                         */
-                        if (tried_handoff)
-                                writel(0, op_reg_base + EHCI_CONFIGFLAG);
+                switch (cap & 0xff) {
+                case 1:
+                        ehci_bios_handoff(pdev, op_reg_base, cap, offset);
                         break;
-                case 0:                 /* illegal reserved capability */
-                        cap = 0;
-                        /* FALLTHROUGH */
+                case 0: /* Illegal reserved cap, set cap=0 so we exit */
+                        cap = 0; /* then fallthrough... */
                 default:
                         dev_warn(&pdev->dev, "EHCI: unrecognized capability "
-                                        "%02x\n", cap & 0xff);
-                        break;
+                                 "%02x\n", cap & 0xff);
                 }
                 offset = (cap >> 8) & 0xff;
         }
@@ -338,8 +645,6 @@ static void __devinit quirk_usb_disable_ehci(struct pci_dev *pdev)
         writel(0x3f, op_reg_base + EHCI_USBSTS);
 
         iounmap(base);
-
-        return;
 }
 
 /*
@@ -371,6 +676,64 @@ static int handshake(void __iomem *ptr, u32 mask, u32 done,
         return -ETIMEDOUT;
 }
 
+bool usb_is_intel_switchable_xhci(struct pci_dev *pdev)
+{
+        return pdev->class == PCI_CLASS_SERIAL_USB_XHCI &&
+                pdev->vendor == PCI_VENDOR_ID_INTEL &&
+                pdev->device == PCI_DEVICE_ID_INTEL_PANTHERPOINT_XHCI;
+}
+EXPORT_SYMBOL_GPL(usb_is_intel_switchable_xhci);
+
+/*
+ * Intel's Panther Point chipset has two host controllers (EHCI and xHCI) that
+ * share some number of ports.  These ports can be switched between either
+ * controller.  Not all of the ports under the EHCI host controller may be
+ * switchable.
+ *
+ * The ports should be switched over to xHCI before PCI probes for any device
+ * start.  This avoids active devices under EHCI being disconnected during the
+ * port switchover, which could cause loss of data on USB storage devices, or
+ * failed boot when the root file system is on a USB mass storage device and is
+ * enumerated under EHCI first.
+ *
+ * We write into the xHC's PCI configuration space in some Intel-specific
+ * registers to switch the ports over.  The USB 3.0 terminations and the USB
+ * 2.0 data wires are switched separately.  We want to enable the SuperSpeed
+ * terminations before switching the USB 2.0 wires over, so that USB 3.0
+ * devices connect at SuperSpeed, rather than at USB 2.0 speeds.
+ */
+void usb_enable_xhci_ports(struct pci_dev *xhci_pdev)
+{
+        u32             ports_available;
+
+        ports_available = 0xffffffff;
+        /* Write USB3_PSSEN, the USB 3.0 Port SuperSpeed Enable
+         * Register, to turn on SuperSpeed terminations for all
+         * available ports.
+         */
+        pci_write_config_dword(xhci_pdev, USB_INTEL_USB3_PSSEN,
+                        cpu_to_le32(ports_available));
+
+        pci_read_config_dword(xhci_pdev, USB_INTEL_USB3_PSSEN,
+                        &ports_available);
+        dev_dbg(&xhci_pdev->dev, "USB 3.0 ports that are now enabled "
+                        "under xHCI: 0x%x\n", ports_available);
+
+        ports_available = 0xffffffff;
+        /* Write XUSB2PR, the xHC USB 2.0 Port Routing Register, to
+         * switch the USB 2.0 power and data lines over to the xHCI
+         * host.
+         */
+        pci_write_config_dword(xhci_pdev, USB_INTEL_XUSB2PR,
+                        cpu_to_le32(ports_available));
+
+        pci_read_config_dword(xhci_pdev, USB_INTEL_XUSB2PR,
+                        &ports_available);
+        dev_dbg(&xhci_pdev->dev, "USB 2.0 ports that are now switched over "
+                        "to xHCI: 0x%x\n", ports_available);
+}
+EXPORT_SYMBOL_GPL(usb_enable_xhci_ports);
+
 /**
  * PCI Quirks for xHCI.
  *
@@ -430,6 +793,8 @@ static void __devinit quirk_usb_handoff_xhci(struct pci_dev *pdev)
         writel(XHCI_LEGACY_DISABLE_SMI,
                         base + ext_cap_offset + XHCI_LEGACY_CONTROL_OFFSET);
 
+        if (usb_is_intel_switchable_xhci(pdev))
+                usb_enable_xhci_ports(pdev);
 hc_init:
         op_reg_base = base + XHCI_HC_LENGTH(readl(base));