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authorArvid Brodin <arvid.brodin@enea.com>2011-08-21 02:29:26 -0400
committerGreg Kroah-Hartman <gregkh@suse.de>2011-08-22 18:32:45 -0400
commit6d50c60e6d169b04b0cf0b267eb14ab0839f9540 (patch)
treed79f632ef413323a0bbec04cbe0f72863c89ca10 /drivers/usb/host/isp1760-hcd.h
parent0ba7905e030a409fd0bb92cb965e915c0cb01030 (diff)
usb/isp1760: Use polling instead of SOF interrupts to fix Errata 2
Errata 2 for the isp1760 explains that the chip sometimes does not issue interrupts when an ATL (bulk or control) transfer is completed. There are several issues with the current work-around (SOF interrupts) for this: 1) It seems the chip sometimes does not even set the done bit for a completed transfer, in which case SOF interrupts does not solve the problem since we still check the done map to find out which transfer descriptors to handle. 2) The above point seems to happen only when ATL and SOF interrupts are enabled at the same time. However, disabling ATL interrupts increases the latency between transfer completion and handling. This is very noticeable in the testusb suite, which take several minutes more to run with ATL interrupts disabled. This patch removes the code to switch on SOF interrupts, and instead use a kernel timer to periodically check for "old" descriptors that have their VALID and ACTIVE flags unset, indicating completion, thus avoiding the dependency on the chip's done map (and SOF interrupts) to find transfers affected by this HW bug. [bigeasy@linutronix: 80 lines limit] Signed-off-by: Arvid Brodin <arvid.brodin@enea.com> Signed-off-by: Sebastian Andrzej Siewior <bigeasy@linutronix.de> Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
Diffstat (limited to 'drivers/usb/host/isp1760-hcd.h')
-rw-r--r--drivers/usb/host/isp1760-hcd.h3
1 files changed, 2 insertions, 1 deletions
diff --git a/drivers/usb/host/isp1760-hcd.h b/drivers/usb/host/isp1760-hcd.h
index 014a7dfadf91..fda0f2d54e3d 100644
--- a/drivers/usb/host/isp1760-hcd.h
+++ b/drivers/usb/host/isp1760-hcd.h
@@ -73,7 +73,6 @@ void deinit_kmem_cache(void);
73#define HC_EOT_INT (1 << 3) 73#define HC_EOT_INT (1 << 3)
74#define HC_SOT_INT (1 << 1) 74#define HC_SOT_INT (1 << 1)
75#define INTERRUPT_ENABLE_MASK (HC_INTL_INT | HC_ATL_INT) 75#define INTERRUPT_ENABLE_MASK (HC_INTL_INT | HC_ATL_INT)
76#define INTERRUPT_ENABLE_SOT_MASK (HC_SOT_INT)
77 76
78#define HC_ISO_IRQ_MASK_OR_REG 0x318 77#define HC_ISO_IRQ_MASK_OR_REG 0x318
79#define HC_INT_IRQ_MASK_OR_REG 0x31C 78#define HC_INT_IRQ_MASK_OR_REG 0x31C
@@ -107,6 +106,7 @@ struct ptd {
107struct slotinfo { 106struct slotinfo {
108 struct isp1760_qh *qh; 107 struct isp1760_qh *qh;
109 struct isp1760_qtd *qtd; 108 struct isp1760_qtd *qtd;
109 unsigned long timestamp;
110}; 110};
111 111
112 112
@@ -188,6 +188,7 @@ struct memory_chunk {
188#define DW3_BABBLE_BIT (1 << 29) 188#define DW3_BABBLE_BIT (1 << 29)
189#define DW3_HALT_BIT (1 << 30) 189#define DW3_HALT_BIT (1 << 30)
190#define DW3_ACTIVE_BIT (1 << 31) 190#define DW3_ACTIVE_BIT (1 << 31)
191#define FROM_DW3_ACTIVE(x) (((x) >> 31) & 0x01)
191 192
192#define INT_UNDERRUN (1 << 2) 193#define INT_UNDERRUN (1 << 2)
193#define INT_BABBLE (1 << 1) 194#define INT_BABBLE (1 << 1)