aboutsummaryrefslogtreecommitdiffstats
path: root/drivers/usb/host/isp1760-hcd.h
diff options
context:
space:
mode:
authorGlenn Elliott <gelliott@cs.unc.edu>2012-03-04 19:47:13 -0500
committerGlenn Elliott <gelliott@cs.unc.edu>2012-03-04 19:47:13 -0500
commitc71c03bda1e86c9d5198c5d83f712e695c4f2a1e (patch)
treeecb166cb3e2b7e2adb3b5e292245fefd23381ac8 /drivers/usb/host/isp1760-hcd.h
parentea53c912f8a86a8567697115b6a0d8152beee5c8 (diff)
parent6a00f206debf8a5c8899055726ad127dbeeed098 (diff)
Merge branch 'mpi-master' into wip-k-fmlpwip-k-fmlp
Conflicts: litmus/sched_cedf.c
Diffstat (limited to 'drivers/usb/host/isp1760-hcd.h')
-rw-r--r--drivers/usb/host/isp1760-hcd.h132
1 files changed, 54 insertions, 78 deletions
diff --git a/drivers/usb/host/isp1760-hcd.h b/drivers/usb/host/isp1760-hcd.h
index 6931ef5c9650..014a7dfadf91 100644
--- a/drivers/usb/host/isp1760-hcd.h
+++ b/drivers/usb/host/isp1760-hcd.h
@@ -49,10 +49,9 @@ void deinit_kmem_cache(void);
49#define SW_RESET_RESET_ALL (1 << 0) 49#define SW_RESET_RESET_ALL (1 << 0)
50 50
51#define HC_BUFFER_STATUS_REG 0x334 51#define HC_BUFFER_STATUS_REG 0x334
52#define ATL_BUFFER 0x1 52#define ISO_BUF_FILL (1 << 2)
53#define INT_BUFFER 0x2 53#define INT_BUF_FILL (1 << 1)
54#define ISO_BUFFER 0x4 54#define ATL_BUF_FILL (1 << 0)
55#define BUFFER_MAP 0x7
56 55
57#define HC_MEMORY_REG 0x33c 56#define HC_MEMORY_REG 0x33c
58#define ISP_BANK(x) ((x) << 16) 57#define ISP_BANK(x) ((x) << 16)
@@ -68,13 +67,13 @@ void deinit_kmem_cache(void);
68#define HC_INTERRUPT_REG 0x310 67#define HC_INTERRUPT_REG 0x310
69 68
70#define HC_INTERRUPT_ENABLE 0x314 69#define HC_INTERRUPT_ENABLE 0x314
71#define INTERRUPT_ENABLE_MASK (HC_INTL_INT | HC_ATL_INT | HC_EOT_INT)
72
73#define HC_ISO_INT (1 << 9) 70#define HC_ISO_INT (1 << 9)
74#define HC_ATL_INT (1 << 8) 71#define HC_ATL_INT (1 << 8)
75#define HC_INTL_INT (1 << 7) 72#define HC_INTL_INT (1 << 7)
76#define HC_EOT_INT (1 << 3) 73#define HC_EOT_INT (1 << 3)
77#define HC_SOT_INT (1 << 1) 74#define HC_SOT_INT (1 << 1)
75#define INTERRUPT_ENABLE_MASK (HC_INTL_INT | HC_ATL_INT)
76#define INTERRUPT_ENABLE_SOT_MASK (HC_SOT_INT)
78 77
79#define HC_ISO_IRQ_MASK_OR_REG 0x318 78#define HC_ISO_IRQ_MASK_OR_REG 0x318
80#define HC_INT_IRQ_MASK_OR_REG 0x31C 79#define HC_INT_IRQ_MASK_OR_REG 0x31C
@@ -83,37 +82,29 @@ void deinit_kmem_cache(void);
83#define HC_INT_IRQ_MASK_AND_REG 0x328 82#define HC_INT_IRQ_MASK_AND_REG 0x328
84#define HC_ATL_IRQ_MASK_AND_REG 0x32C 83#define HC_ATL_IRQ_MASK_AND_REG 0x32C
85 84
86/* Register sets */
87#define HC_BEGIN_OF_ATL 0x0c00
88#define HC_BEGIN_OF_INT 0x0800
89#define HC_BEGIN_OF_ISO 0x0400
90#define HC_BEGIN_OF_PAYLOAD 0x1000
91
92/* urb state*/ 85/* urb state*/
93#define DELETE_URB (0x0008) 86#define DELETE_URB (0x0008)
94#define NO_TRANSFER_ACTIVE (0xffffffff) 87#define NO_TRANSFER_ACTIVE (0xffffffff)
95 88
96#define ATL_REGS_OFFSET (0xc00) 89/* Philips Proprietary Transfer Descriptor (PTD) */
97#define INT_REGS_OFFSET (0x800) 90typedef __u32 __bitwise __dw;
98
99/* Philips Transfer Descriptor (PTD) */
100struct ptd { 91struct ptd {
101 __le32 dw0; 92 __dw dw0;
102 __le32 dw1; 93 __dw dw1;
103 __le32 dw2; 94 __dw dw2;
104 __le32 dw3; 95 __dw dw3;
105 __le32 dw4; 96 __dw dw4;
106 __le32 dw5; 97 __dw dw5;
107 __le32 dw6; 98 __dw dw6;
108 __le32 dw7; 99 __dw dw7;
109}; 100};
101#define PTD_OFFSET 0x0400
102#define ISO_PTD_OFFSET 0x0400
103#define INT_PTD_OFFSET 0x0800
104#define ATL_PTD_OFFSET 0x0c00
105#define PAYLOAD_OFFSET 0x1000
110 106
111struct inter_packet_info { 107struct slotinfo {
112 void *data_buffer;
113 u32 payload;
114#define PTD_FIRE_NEXT (1 << 0)
115#define PTD_URB_FINISHED (1 << 1)
116 struct urb *urb;
117 struct isp1760_qh *qh; 108 struct isp1760_qh *qh;
118 struct isp1760_qtd *qtd; 109 struct isp1760_qtd *qtd;
119}; 110};
@@ -122,15 +113,6 @@ struct inter_packet_info {
122typedef void (packet_enqueue)(struct usb_hcd *hcd, struct isp1760_qh *qh, 113typedef void (packet_enqueue)(struct usb_hcd *hcd, struct isp1760_qh *qh,
123 struct isp1760_qtd *qtd); 114 struct isp1760_qtd *qtd);
124 115
125#define isp1760_dbg(priv, fmt, args...) \
126 dev_dbg(priv_to_hcd(priv)->self.controller, fmt, ##args)
127
128#define isp1760_info(priv, fmt, args...) \
129 dev_info(priv_to_hcd(priv)->self.controller, fmt, ##args)
130
131#define isp1760_err(priv, fmt, args...) \
132 dev_err(priv_to_hcd(priv)->self.controller, fmt, ##args)
133
134/* 116/*
135 * Device flags that can vary from board to board. All of these 117 * Device flags that can vary from board to board. All of these
136 * indicate the most "atypical" case, so that a devflags of 0 is 118 * indicate the most "atypical" case, so that a devflags of 0 is
@@ -167,63 +149,57 @@ struct memory_chunk {
167#define BLOCK_2_SIZE 1024 149#define BLOCK_2_SIZE 1024
168#define BLOCK_3_SIZE 8192 150#define BLOCK_3_SIZE 8192
169#define BLOCKS (BLOCK_1_NUM + BLOCK_2_NUM + BLOCK_3_NUM) 151#define BLOCKS (BLOCK_1_NUM + BLOCK_2_NUM + BLOCK_3_NUM)
170#define PAYLOAD_SIZE 0xf000 152#define MAX_PAYLOAD_SIZE BLOCK_3_SIZE
171 153#define PAYLOAD_AREA_SIZE 0xf000
172/* I saw if some reloads if the pointer was negative */
173#define ISP1760_NULL_POINTER (0x400)
174 154
175/* ATL */ 155/* ATL */
176/* DW0 */ 156/* DW0 */
177#define PTD_VALID 1 157#define DW0_VALID_BIT 1
178#define PTD_LENGTH(x) (((u32) x) << 3) 158#define FROM_DW0_VALID(x) ((x) & 0x01)
179#define PTD_MAXPACKET(x) (((u32) x) << 18) 159#define TO_DW0_LENGTH(x) (((u32) x) << 3)
180#define PTD_MULTI(x) (((u32) x) << 29) 160#define TO_DW0_MAXPACKET(x) (((u32) x) << 18)
181#define PTD_ENDPOINT(x) (((u32) x) << 31) 161#define TO_DW0_MULTI(x) (((u32) x) << 29)
162#define TO_DW0_ENDPOINT(x) (((u32) x) << 31)
182/* DW1 */ 163/* DW1 */
183#define PTD_DEVICE_ADDR(x) (((u32) x) << 3) 164#define TO_DW1_DEVICE_ADDR(x) (((u32) x) << 3)
184#define PTD_PID_TOKEN(x) (((u32) x) << 10) 165#define TO_DW1_PID_TOKEN(x) (((u32) x) << 10)
185#define PTD_TRANS_BULK ((u32) 2 << 12) 166#define DW1_TRANS_BULK ((u32) 2 << 12)
186#define PTD_TRANS_INT ((u32) 3 << 12) 167#define DW1_TRANS_INT ((u32) 3 << 12)
187#define PTD_TRANS_SPLIT ((u32) 1 << 14) 168#define DW1_TRANS_SPLIT ((u32) 1 << 14)
188#define PTD_SE_USB_LOSPEED ((u32) 2 << 16) 169#define DW1_SE_USB_LOSPEED ((u32) 2 << 16)
189#define PTD_PORT_NUM(x) (((u32) x) << 18) 170#define TO_DW1_PORT_NUM(x) (((u32) x) << 18)
190#define PTD_HUB_NUM(x) (((u32) x) << 25) 171#define TO_DW1_HUB_NUM(x) (((u32) x) << 25)
191#define PTD_PING(x) (((u32) x) << 26)
192/* DW2 */ 172/* DW2 */
193#define PTD_RL_CNT(x) (((u32) x) << 25) 173#define TO_DW2_DATA_START_ADDR(x) (((u32) x) << 8)
194#define PTD_DATA_START_ADDR(x) (((u32) x) << 8) 174#define TO_DW2_RL(x) ((x) << 25)
195#define BASE_ADDR 0x1000 175#define FROM_DW2_RL(x) (((x) >> 25) & 0xf)
196/* DW3 */ 176/* DW3 */
197#define PTD_CERR(x) (((u32) x) << 23) 177#define FROM_DW3_NRBYTESTRANSFERRED(x) ((x) & 0x7fff)
198#define PTD_NAC_CNT(x) (((u32) x) << 19) 178#define FROM_DW3_SCS_NRBYTESTRANSFERRED(x) ((x) & 0x07ff)
199#define PTD_ACTIVE ((u32) 1 << 31) 179#define TO_DW3_NAKCOUNT(x) ((x) << 19)
200#define PTD_DATA_TOGGLE(x) (((u32) x) << 25) 180#define FROM_DW3_NAKCOUNT(x) (((x) >> 19) & 0xf)
201 181#define TO_DW3_CERR(x) ((x) << 23)
202#define DW3_HALT_BIT (1 << 30) 182#define FROM_DW3_CERR(x) (((x) >> 23) & 0x3)
183#define TO_DW3_DATA_TOGGLE(x) ((x) << 25)
184#define FROM_DW3_DATA_TOGGLE(x) (((x) >> 25) & 0x1)
185#define TO_DW3_PING(x) ((x) << 26)
186#define FROM_DW3_PING(x) (((x) >> 26) & 0x1)
203#define DW3_ERROR_BIT (1 << 28) 187#define DW3_ERROR_BIT (1 << 28)
204#define DW3_QTD_ACTIVE (1 << 31) 188#define DW3_BABBLE_BIT (1 << 29)
189#define DW3_HALT_BIT (1 << 30)
190#define DW3_ACTIVE_BIT (1 << 31)
205 191
206#define INT_UNDERRUN (1 << 2) 192#define INT_UNDERRUN (1 << 2)
207#define INT_BABBLE (1 << 1) 193#define INT_BABBLE (1 << 1)
208#define INT_EXACT (1 << 0) 194#define INT_EXACT (1 << 0)
209 195
210#define DW1_GET_PID(x) (((x) >> 10) & 0x3)
211#define PTD_XFERRED_LENGTH(x) ((x) & 0x7fff)
212#define PTD_XFERRED_LENGTH_LO(x) ((x) & 0x7ff)
213
214#define SETUP_PID (2) 196#define SETUP_PID (2)
215#define IN_PID (1) 197#define IN_PID (1)
216#define OUT_PID (0) 198#define OUT_PID (0)
217#define GET_QTD_TOKEN_TYPE(x) ((x) & 0x3)
218
219#define DATA_TOGGLE (1 << 31)
220#define GET_DATA_TOGGLE(x) ((x) >> 31)
221 199
222/* Errata 1 */ 200/* Errata 1 */
223#define RL_COUNTER (0) 201#define RL_COUNTER (0)
224#define NAK_COUNTER (0) 202#define NAK_COUNTER (0)
225#define ERR_COUNTER (2) 203#define ERR_COUNTER (2)
226 204
227#define HC_ATL_PL_SIZE (8192) 205#endif /* _ISP1760_HCD_H_ */
228
229#endif