diff options
author | Glenn Elliott <gelliott@cs.unc.edu> | 2012-03-04 19:47:13 -0500 |
---|---|---|
committer | Glenn Elliott <gelliott@cs.unc.edu> | 2012-03-04 19:47:13 -0500 |
commit | c71c03bda1e86c9d5198c5d83f712e695c4f2a1e (patch) | |
tree | ecb166cb3e2b7e2adb3b5e292245fefd23381ac8 /drivers/usb/host/isp1760-hcd.c | |
parent | ea53c912f8a86a8567697115b6a0d8152beee5c8 (diff) | |
parent | 6a00f206debf8a5c8899055726ad127dbeeed098 (diff) |
Merge branch 'mpi-master' into wip-k-fmlpwip-k-fmlp
Conflicts:
litmus/sched_cedf.c
Diffstat (limited to 'drivers/usb/host/isp1760-hcd.c')
-rw-r--r-- | drivers/usb/host/isp1760-hcd.c | 2380 |
1 files changed, 1097 insertions, 1283 deletions
diff --git a/drivers/usb/host/isp1760-hcd.c b/drivers/usb/host/isp1760-hcd.c index bdba8c5d844a..55d3d5859ac5 100644 --- a/drivers/usb/host/isp1760-hcd.c +++ b/drivers/usb/host/isp1760-hcd.c | |||
@@ -8,6 +8,8 @@ | |||
8 | * | 8 | * |
9 | * (c) 2007 Sebastian Siewior <bigeasy@linutronix.de> | 9 | * (c) 2007 Sebastian Siewior <bigeasy@linutronix.de> |
10 | * | 10 | * |
11 | * (c) 2011 Arvid Brodin <arvid.brodin@enea.com> | ||
12 | * | ||
11 | */ | 13 | */ |
12 | #include <linux/module.h> | 14 | #include <linux/module.h> |
13 | #include <linux/kernel.h> | 15 | #include <linux/kernel.h> |
@@ -26,13 +28,18 @@ | |||
26 | 28 | ||
27 | static struct kmem_cache *qtd_cachep; | 29 | static struct kmem_cache *qtd_cachep; |
28 | static struct kmem_cache *qh_cachep; | 30 | static struct kmem_cache *qh_cachep; |
31 | static struct kmem_cache *urb_listitem_cachep; | ||
29 | 32 | ||
30 | struct isp1760_hcd { | 33 | struct isp1760_hcd { |
31 | u32 hcs_params; | 34 | u32 hcs_params; |
32 | spinlock_t lock; | 35 | spinlock_t lock; |
33 | struct inter_packet_info atl_ints[32]; | 36 | struct slotinfo atl_slots[32]; |
34 | struct inter_packet_info int_ints[32]; | 37 | int atl_done_map; |
38 | struct slotinfo int_slots[32]; | ||
39 | int int_done_map; | ||
35 | struct memory_chunk memory_pool[BLOCKS]; | 40 | struct memory_chunk memory_pool[BLOCKS]; |
41 | struct list_head controlqhs, bulkqhs, interruptqhs; | ||
42 | int active_ptds; | ||
36 | 43 | ||
37 | /* periodic schedule support */ | 44 | /* periodic schedule support */ |
38 | #define DEFAULT_I_TDPS 1024 | 45 | #define DEFAULT_I_TDPS 1024 |
@@ -47,10 +54,6 @@ static inline struct isp1760_hcd *hcd_to_priv(struct usb_hcd *hcd) | |||
47 | { | 54 | { |
48 | return (struct isp1760_hcd *) (hcd->hcd_priv); | 55 | return (struct isp1760_hcd *) (hcd->hcd_priv); |
49 | } | 56 | } |
50 | static inline struct usb_hcd *priv_to_hcd(struct isp1760_hcd *priv) | ||
51 | { | ||
52 | return container_of((void *) priv, struct usb_hcd, hcd_priv); | ||
53 | } | ||
54 | 57 | ||
55 | /* Section 2.2 Host Controller Capability Registers */ | 58 | /* Section 2.2 Host Controller Capability Registers */ |
56 | #define HC_LENGTH(p) (((p)>>00)&0x00ff) /* bits 7:0 */ | 59 | #define HC_LENGTH(p) (((p)>>00)&0x00ff) /* bits 7:0 */ |
@@ -80,217 +83,270 @@ static inline struct usb_hcd *priv_to_hcd(struct isp1760_hcd *priv) | |||
80 | #define PORT_RWC_BITS (PORT_CSC) | 83 | #define PORT_RWC_BITS (PORT_CSC) |
81 | 84 | ||
82 | struct isp1760_qtd { | 85 | struct isp1760_qtd { |
83 | struct isp1760_qtd *hw_next; | ||
84 | u8 packet_type; | 86 | u8 packet_type; |
85 | u8 toggle; | ||
86 | |||
87 | void *data_buffer; | 87 | void *data_buffer; |
88 | u32 payload_addr; | ||
89 | |||
88 | /* the rest is HCD-private */ | 90 | /* the rest is HCD-private */ |
89 | struct list_head qtd_list; | 91 | struct list_head qtd_list; |
90 | struct urb *urb; | 92 | struct urb *urb; |
91 | size_t length; | 93 | size_t length; |
92 | 94 | size_t actual_length; | |
93 | /* isp special*/ | 95 | |
96 | /* QTD_ENQUEUED: waiting for transfer (inactive) */ | ||
97 | /* QTD_PAYLOAD_ALLOC: chip mem has been allocated for payload */ | ||
98 | /* QTD_XFER_STARTED: valid ptd has been written to isp176x - only | ||
99 | interrupt handler may touch this qtd! */ | ||
100 | /* QTD_XFER_COMPLETE: payload has been transferred successfully */ | ||
101 | /* QTD_RETIRE: transfer error/abort qtd */ | ||
102 | #define QTD_ENQUEUED 0 | ||
103 | #define QTD_PAYLOAD_ALLOC 1 | ||
104 | #define QTD_XFER_STARTED 2 | ||
105 | #define QTD_XFER_COMPLETE 3 | ||
106 | #define QTD_RETIRE 4 | ||
94 | u32 status; | 107 | u32 status; |
95 | #define URB_COMPLETE_NOTIFY (1 << 0) | ||
96 | #define URB_ENQUEUED (1 << 1) | ||
97 | #define URB_TYPE_ATL (1 << 2) | ||
98 | #define URB_TYPE_INT (1 << 3) | ||
99 | }; | 108 | }; |
100 | 109 | ||
110 | /* Queue head, one for each active endpoint */ | ||
101 | struct isp1760_qh { | 111 | struct isp1760_qh { |
102 | /* first part defined by EHCI spec */ | 112 | struct list_head qh_list; |
103 | struct list_head qtd_list; | 113 | struct list_head qtd_list; |
104 | struct isp1760_hcd *priv; | ||
105 | |||
106 | /* periodic schedule info */ | ||
107 | unsigned short period; /* polling interval */ | ||
108 | struct usb_device *dev; | ||
109 | |||
110 | u32 toggle; | 114 | u32 toggle; |
111 | u32 ping; | 115 | u32 ping; |
116 | int slot; | ||
112 | }; | 117 | }; |
113 | 118 | ||
114 | #define ehci_port_speed(priv, portsc) USB_PORT_STAT_HIGH_SPEED | 119 | struct urb_listitem { |
120 | struct list_head urb_list; | ||
121 | struct urb *urb; | ||
122 | }; | ||
115 | 123 | ||
116 | static unsigned int isp1760_readl(__u32 __iomem *regs) | 124 | /* |
125 | * Access functions for isp176x registers (addresses 0..0x03FF). | ||
126 | */ | ||
127 | static u32 reg_read32(void __iomem *base, u32 reg) | ||
117 | { | 128 | { |
118 | return readl(regs); | 129 | return readl(base + reg); |
119 | } | 130 | } |
120 | 131 | ||
121 | static void isp1760_writel(const unsigned int val, __u32 __iomem *regs) | 132 | static void reg_write32(void __iomem *base, u32 reg, u32 val) |
122 | { | 133 | { |
123 | writel(val, regs); | 134 | writel(val, base + reg); |
124 | } | 135 | } |
125 | 136 | ||
126 | /* | 137 | /* |
127 | * The next two copy via MMIO data to/from the device. memcpy_{to|from}io() | 138 | * Access functions for isp176x memory (offset >= 0x0400). |
139 | * | ||
140 | * bank_reads8() reads memory locations prefetched by an earlier write to | ||
141 | * HC_MEMORY_REG (see isp176x datasheet). Unless you want to do fancy multi- | ||
142 | * bank optimizations, you should use the more generic mem_reads8() below. | ||
143 | * | ||
144 | * For access to ptd memory, use the specialized ptd_read() and ptd_write() | ||
145 | * below. | ||
146 | * | ||
147 | * These functions copy via MMIO data to/from the device. memcpy_{to|from}io() | ||
128 | * doesn't quite work because some people have to enforce 32-bit access | 148 | * doesn't quite work because some people have to enforce 32-bit access |
129 | */ | 149 | */ |
130 | static void priv_read_copy(struct isp1760_hcd *priv, u32 *src, | 150 | static void bank_reads8(void __iomem *src_base, u32 src_offset, u32 bank_addr, |
131 | __u32 __iomem *dst, u32 len) | 151 | __u32 *dst, u32 bytes) |
132 | { | 152 | { |
153 | __u32 __iomem *src; | ||
133 | u32 val; | 154 | u32 val; |
134 | u8 *buff8; | 155 | __u8 *src_byteptr; |
156 | __u8 *dst_byteptr; | ||
135 | 157 | ||
136 | if (!src) { | 158 | src = src_base + (bank_addr | src_offset); |
137 | printk(KERN_ERR "ERROR: buffer: %p len: %d\n", src, len); | ||
138 | return; | ||
139 | } | ||
140 | 159 | ||
141 | while (len >= 4) { | 160 | if (src_offset < PAYLOAD_OFFSET) { |
142 | *src = __raw_readl(dst); | 161 | while (bytes >= 4) { |
143 | len -= 4; | 162 | *dst = le32_to_cpu(__raw_readl(src)); |
144 | src++; | 163 | bytes -= 4; |
145 | dst++; | 164 | src++; |
165 | dst++; | ||
166 | } | ||
167 | } else { | ||
168 | while (bytes >= 4) { | ||
169 | *dst = __raw_readl(src); | ||
170 | bytes -= 4; | ||
171 | src++; | ||
172 | dst++; | ||
173 | } | ||
146 | } | 174 | } |
147 | 175 | ||
148 | if (!len) | 176 | if (!bytes) |
149 | return; | 177 | return; |
150 | 178 | ||
151 | /* in case we have 3, 2 or 1 by left. The dst buffer may not be fully | 179 | /* in case we have 3, 2 or 1 by left. The dst buffer may not be fully |
152 | * allocated. | 180 | * allocated. |
153 | */ | 181 | */ |
154 | val = isp1760_readl(dst); | 182 | if (src_offset < PAYLOAD_OFFSET) |
155 | 183 | val = le32_to_cpu(__raw_readl(src)); | |
156 | buff8 = (u8 *)src; | 184 | else |
157 | while (len) { | 185 | val = __raw_readl(src); |
158 | 186 | ||
159 | *buff8 = val; | 187 | dst_byteptr = (void *) dst; |
160 | val >>= 8; | 188 | src_byteptr = (void *) &val; |
161 | len--; | 189 | while (bytes > 0) { |
162 | buff8++; | 190 | *dst_byteptr = *src_byteptr; |
191 | dst_byteptr++; | ||
192 | src_byteptr++; | ||
193 | bytes--; | ||
163 | } | 194 | } |
164 | } | 195 | } |
165 | 196 | ||
166 | static void priv_write_copy(const struct isp1760_hcd *priv, const u32 *src, | 197 | static void mem_reads8(void __iomem *src_base, u32 src_offset, void *dst, |
167 | __u32 __iomem *dst, u32 len) | 198 | u32 bytes) |
168 | { | 199 | { |
169 | while (len >= 4) { | 200 | reg_write32(src_base, HC_MEMORY_REG, src_offset + ISP_BANK(0)); |
170 | __raw_writel(*src, dst); | 201 | ndelay(90); |
171 | len -= 4; | 202 | bank_reads8(src_base, src_offset, ISP_BANK(0), dst, bytes); |
172 | src++; | 203 | } |
173 | dst++; | 204 | |
205 | static void mem_writes8(void __iomem *dst_base, u32 dst_offset, | ||
206 | __u32 const *src, u32 bytes) | ||
207 | { | ||
208 | __u32 __iomem *dst; | ||
209 | |||
210 | dst = dst_base + dst_offset; | ||
211 | |||
212 | if (dst_offset < PAYLOAD_OFFSET) { | ||
213 | while (bytes >= 4) { | ||
214 | __raw_writel(cpu_to_le32(*src), dst); | ||
215 | bytes -= 4; | ||
216 | src++; | ||
217 | dst++; | ||
218 | } | ||
219 | } else { | ||
220 | while (bytes >= 4) { | ||
221 | __raw_writel(*src, dst); | ||
222 | bytes -= 4; | ||
223 | src++; | ||
224 | dst++; | ||
225 | } | ||
174 | } | 226 | } |
175 | 227 | ||
176 | if (!len) | 228 | if (!bytes) |
177 | return; | 229 | return; |
178 | /* in case we have 3, 2 or 1 by left. The buffer is allocated and the | 230 | /* in case we have 3, 2 or 1 bytes left. The buffer is allocated and the |
179 | * extra bytes should not be read by the HW | 231 | * extra bytes should not be read by the HW. |
180 | */ | 232 | */ |
181 | 233 | ||
182 | __raw_writel(*src, dst); | 234 | if (dst_offset < PAYLOAD_OFFSET) |
235 | __raw_writel(cpu_to_le32(*src), dst); | ||
236 | else | ||
237 | __raw_writel(*src, dst); | ||
183 | } | 238 | } |
184 | 239 | ||
240 | /* | ||
241 | * Read and write ptds. 'ptd_offset' should be one of ISO_PTD_OFFSET, | ||
242 | * INT_PTD_OFFSET, and ATL_PTD_OFFSET. 'slot' should be less than 32. | ||
243 | */ | ||
244 | static void ptd_read(void __iomem *base, u32 ptd_offset, u32 slot, | ||
245 | struct ptd *ptd) | ||
246 | { | ||
247 | reg_write32(base, HC_MEMORY_REG, | ||
248 | ISP_BANK(0) + ptd_offset + slot*sizeof(*ptd)); | ||
249 | ndelay(90); | ||
250 | bank_reads8(base, ptd_offset + slot*sizeof(*ptd), ISP_BANK(0), | ||
251 | (void *) ptd, sizeof(*ptd)); | ||
252 | } | ||
253 | |||
254 | static void ptd_write(void __iomem *base, u32 ptd_offset, u32 slot, | ||
255 | struct ptd *ptd) | ||
256 | { | ||
257 | mem_writes8(base, ptd_offset + slot*sizeof(*ptd) + sizeof(ptd->dw0), | ||
258 | &ptd->dw1, 7*sizeof(ptd->dw1)); | ||
259 | /* Make sure dw0 gets written last (after other dw's and after payload) | ||
260 | since it contains the enable bit */ | ||
261 | wmb(); | ||
262 | mem_writes8(base, ptd_offset + slot*sizeof(*ptd), &ptd->dw0, | ||
263 | sizeof(ptd->dw0)); | ||
264 | } | ||
265 | |||
266 | |||
185 | /* memory management of the 60kb on the chip from 0x1000 to 0xffff */ | 267 | /* memory management of the 60kb on the chip from 0x1000 to 0xffff */ |
186 | static void init_memory(struct isp1760_hcd *priv) | 268 | static void init_memory(struct isp1760_hcd *priv) |
187 | { | 269 | { |
188 | int i; | 270 | int i, curr; |
189 | u32 payload; | 271 | u32 payload_addr; |
190 | 272 | ||
191 | payload = 0x1000; | 273 | payload_addr = PAYLOAD_OFFSET; |
192 | for (i = 0; i < BLOCK_1_NUM; i++) { | 274 | for (i = 0; i < BLOCK_1_NUM; i++) { |
193 | priv->memory_pool[i].start = payload; | 275 | priv->memory_pool[i].start = payload_addr; |
194 | priv->memory_pool[i].size = BLOCK_1_SIZE; | 276 | priv->memory_pool[i].size = BLOCK_1_SIZE; |
195 | priv->memory_pool[i].free = 1; | 277 | priv->memory_pool[i].free = 1; |
196 | payload += priv->memory_pool[i].size; | 278 | payload_addr += priv->memory_pool[i].size; |
197 | } | 279 | } |
198 | 280 | ||
199 | 281 | curr = i; | |
200 | for (i = BLOCK_1_NUM; i < BLOCK_1_NUM + BLOCK_2_NUM; i++) { | 282 | for (i = 0; i < BLOCK_2_NUM; i++) { |
201 | priv->memory_pool[i].start = payload; | 283 | priv->memory_pool[curr + i].start = payload_addr; |
202 | priv->memory_pool[i].size = BLOCK_2_SIZE; | 284 | priv->memory_pool[curr + i].size = BLOCK_2_SIZE; |
203 | priv->memory_pool[i].free = 1; | 285 | priv->memory_pool[curr + i].free = 1; |
204 | payload += priv->memory_pool[i].size; | 286 | payload_addr += priv->memory_pool[curr + i].size; |
205 | } | 287 | } |
206 | 288 | ||
207 | 289 | curr = i; | |
208 | for (i = BLOCK_1_NUM + BLOCK_2_NUM; i < BLOCKS; i++) { | 290 | for (i = 0; i < BLOCK_3_NUM; i++) { |
209 | priv->memory_pool[i].start = payload; | 291 | priv->memory_pool[curr + i].start = payload_addr; |
210 | priv->memory_pool[i].size = BLOCK_3_SIZE; | 292 | priv->memory_pool[curr + i].size = BLOCK_3_SIZE; |
211 | priv->memory_pool[i].free = 1; | 293 | priv->memory_pool[curr + i].free = 1; |
212 | payload += priv->memory_pool[i].size; | 294 | payload_addr += priv->memory_pool[curr + i].size; |
213 | } | 295 | } |
214 | 296 | ||
215 | BUG_ON(payload - priv->memory_pool[i - 1].size > PAYLOAD_SIZE); | 297 | WARN_ON(payload_addr - priv->memory_pool[0].start > PAYLOAD_AREA_SIZE); |
216 | } | 298 | } |
217 | 299 | ||
218 | static u32 alloc_mem(struct isp1760_hcd *priv, u32 size) | 300 | static void alloc_mem(struct usb_hcd *hcd, struct isp1760_qtd *qtd) |
219 | { | 301 | { |
302 | struct isp1760_hcd *priv = hcd_to_priv(hcd); | ||
220 | int i; | 303 | int i; |
221 | 304 | ||
222 | if (!size) | 305 | WARN_ON(qtd->payload_addr); |
223 | return ISP1760_NULL_POINTER; | 306 | |
307 | if (!qtd->length) | ||
308 | return; | ||
224 | 309 | ||
225 | for (i = 0; i < BLOCKS; i++) { | 310 | for (i = 0; i < BLOCKS; i++) { |
226 | if (priv->memory_pool[i].size >= size && | 311 | if (priv->memory_pool[i].size >= qtd->length && |
227 | priv->memory_pool[i].free) { | 312 | priv->memory_pool[i].free) { |
228 | |||
229 | priv->memory_pool[i].free = 0; | 313 | priv->memory_pool[i].free = 0; |
230 | return priv->memory_pool[i].start; | 314 | qtd->payload_addr = priv->memory_pool[i].start; |
315 | return; | ||
231 | } | 316 | } |
232 | } | 317 | } |
233 | |||
234 | printk(KERN_ERR "ISP1760 MEM: can not allocate %d bytes of memory\n", | ||
235 | size); | ||
236 | printk(KERN_ERR "Current memory map:\n"); | ||
237 | for (i = 0; i < BLOCKS; i++) { | ||
238 | printk(KERN_ERR "Pool %2d size %4d status: %d\n", | ||
239 | i, priv->memory_pool[i].size, | ||
240 | priv->memory_pool[i].free); | ||
241 | } | ||
242 | /* XXX maybe -ENOMEM could be possible */ | ||
243 | BUG(); | ||
244 | return 0; | ||
245 | } | 318 | } |
246 | 319 | ||
247 | static void free_mem(struct isp1760_hcd *priv, u32 mem) | 320 | static void free_mem(struct usb_hcd *hcd, struct isp1760_qtd *qtd) |
248 | { | 321 | { |
322 | struct isp1760_hcd *priv = hcd_to_priv(hcd); | ||
249 | int i; | 323 | int i; |
250 | 324 | ||
251 | if (mem == ISP1760_NULL_POINTER) | 325 | if (!qtd->payload_addr) |
252 | return; | 326 | return; |
253 | 327 | ||
254 | for (i = 0; i < BLOCKS; i++) { | 328 | for (i = 0; i < BLOCKS; i++) { |
255 | if (priv->memory_pool[i].start == mem) { | 329 | if (priv->memory_pool[i].start == qtd->payload_addr) { |
256 | 330 | WARN_ON(priv->memory_pool[i].free); | |
257 | BUG_ON(priv->memory_pool[i].free); | ||
258 | |||
259 | priv->memory_pool[i].free = 1; | 331 | priv->memory_pool[i].free = 1; |
260 | return ; | 332 | qtd->payload_addr = 0; |
333 | return; | ||
261 | } | 334 | } |
262 | } | 335 | } |
263 | 336 | ||
264 | printk(KERN_ERR "Trying to free not-here-allocated memory :%08x\n", | 337 | dev_err(hcd->self.controller, "%s: Invalid pointer: %08x\n", |
265 | mem); | 338 | __func__, qtd->payload_addr); |
266 | BUG(); | 339 | WARN_ON(1); |
267 | } | 340 | qtd->payload_addr = 0; |
268 | |||
269 | static void isp1760_init_regs(struct usb_hcd *hcd) | ||
270 | { | ||
271 | isp1760_writel(0, hcd->regs + HC_BUFFER_STATUS_REG); | ||
272 | isp1760_writel(NO_TRANSFER_ACTIVE, hcd->regs + | ||
273 | HC_ATL_PTD_SKIPMAP_REG); | ||
274 | isp1760_writel(NO_TRANSFER_ACTIVE, hcd->regs + | ||
275 | HC_INT_PTD_SKIPMAP_REG); | ||
276 | isp1760_writel(NO_TRANSFER_ACTIVE, hcd->regs + | ||
277 | HC_ISO_PTD_SKIPMAP_REG); | ||
278 | |||
279 | isp1760_writel(~NO_TRANSFER_ACTIVE, hcd->regs + | ||
280 | HC_ATL_PTD_DONEMAP_REG); | ||
281 | isp1760_writel(~NO_TRANSFER_ACTIVE, hcd->regs + | ||
282 | HC_INT_PTD_DONEMAP_REG); | ||
283 | isp1760_writel(~NO_TRANSFER_ACTIVE, hcd->regs + | ||
284 | HC_ISO_PTD_DONEMAP_REG); | ||
285 | } | 341 | } |
286 | 342 | ||
287 | static int handshake(struct isp1760_hcd *priv, void __iomem *ptr, | 343 | static int handshake(struct usb_hcd *hcd, u32 reg, |
288 | u32 mask, u32 done, int usec) | 344 | u32 mask, u32 done, int usec) |
289 | { | 345 | { |
290 | u32 result; | 346 | u32 result; |
291 | 347 | ||
292 | do { | 348 | do { |
293 | result = isp1760_readl(ptr); | 349 | result = reg_read32(hcd->regs, reg); |
294 | if (result == ~0) | 350 | if (result == ~0) |
295 | return -ENODEV; | 351 | return -ENODEV; |
296 | result &= mask; | 352 | result &= mask; |
@@ -303,48 +359,43 @@ static int handshake(struct isp1760_hcd *priv, void __iomem *ptr, | |||
303 | } | 359 | } |
304 | 360 | ||
305 | /* reset a non-running (STS_HALT == 1) controller */ | 361 | /* reset a non-running (STS_HALT == 1) controller */ |
306 | static int ehci_reset(struct isp1760_hcd *priv) | 362 | static int ehci_reset(struct usb_hcd *hcd) |
307 | { | 363 | { |
308 | int retval; | 364 | int retval; |
309 | struct usb_hcd *hcd = priv_to_hcd(priv); | 365 | struct isp1760_hcd *priv = hcd_to_priv(hcd); |
310 | u32 command = isp1760_readl(hcd->regs + HC_USBCMD); | 366 | |
367 | u32 command = reg_read32(hcd->regs, HC_USBCMD); | ||
311 | 368 | ||
312 | command |= CMD_RESET; | 369 | command |= CMD_RESET; |
313 | isp1760_writel(command, hcd->regs + HC_USBCMD); | 370 | reg_write32(hcd->regs, HC_USBCMD, command); |
314 | hcd->state = HC_STATE_HALT; | 371 | hcd->state = HC_STATE_HALT; |
315 | priv->next_statechange = jiffies; | 372 | priv->next_statechange = jiffies; |
316 | retval = handshake(priv, hcd->regs + HC_USBCMD, | 373 | retval = handshake(hcd, HC_USBCMD, |
317 | CMD_RESET, 0, 250 * 1000); | 374 | CMD_RESET, 0, 250 * 1000); |
318 | return retval; | 375 | return retval; |
319 | } | 376 | } |
320 | 377 | ||
321 | static void qh_destroy(struct isp1760_qh *qh) | 378 | static struct isp1760_qh *qh_alloc(gfp_t flags) |
322 | { | ||
323 | BUG_ON(!list_empty(&qh->qtd_list)); | ||
324 | kmem_cache_free(qh_cachep, qh); | ||
325 | } | ||
326 | |||
327 | static struct isp1760_qh *isp1760_qh_alloc(struct isp1760_hcd *priv, | ||
328 | gfp_t flags) | ||
329 | { | 379 | { |
330 | struct isp1760_qh *qh; | 380 | struct isp1760_qh *qh; |
331 | 381 | ||
332 | qh = kmem_cache_zalloc(qh_cachep, flags); | 382 | qh = kmem_cache_zalloc(qh_cachep, flags); |
333 | if (!qh) | 383 | if (!qh) |
334 | return qh; | 384 | return NULL; |
335 | 385 | ||
386 | INIT_LIST_HEAD(&qh->qh_list); | ||
336 | INIT_LIST_HEAD(&qh->qtd_list); | 387 | INIT_LIST_HEAD(&qh->qtd_list); |
337 | qh->priv = priv; | 388 | qh->slot = -1; |
389 | |||
338 | return qh; | 390 | return qh; |
339 | } | 391 | } |
340 | 392 | ||
341 | /* magic numbers that can affect system performance */ | 393 | static void qh_free(struct isp1760_qh *qh) |
342 | #define EHCI_TUNE_CERR 3 /* 0-3 qtd retries; 0 == don't stop */ | 394 | { |
343 | #define EHCI_TUNE_RL_HS 4 /* nak throttle; see 4.9 */ | 395 | WARN_ON(!list_empty(&qh->qtd_list)); |
344 | #define EHCI_TUNE_RL_TT 0 | 396 | WARN_ON(qh->slot > -1); |
345 | #define EHCI_TUNE_MULT_HS 1 /* 1-3 transactions/uframe; 4.10.3 */ | 397 | kmem_cache_free(qh_cachep, qh); |
346 | #define EHCI_TUNE_MULT_TT 1 | 398 | } |
347 | #define EHCI_TUNE_FLS 2 /* (small) 256 frame schedule */ | ||
348 | 399 | ||
349 | /* one-time init, only for memory state */ | 400 | /* one-time init, only for memory state */ |
350 | static int priv_init(struct usb_hcd *hcd) | 401 | static int priv_init(struct usb_hcd *hcd) |
@@ -354,6 +405,10 @@ static int priv_init(struct usb_hcd *hcd) | |||
354 | 405 | ||
355 | spin_lock_init(&priv->lock); | 406 | spin_lock_init(&priv->lock); |
356 | 407 | ||
408 | INIT_LIST_HEAD(&priv->interruptqhs); | ||
409 | INIT_LIST_HEAD(&priv->controlqhs); | ||
410 | INIT_LIST_HEAD(&priv->bulkqhs); | ||
411 | |||
357 | /* | 412 | /* |
358 | * hw default: 1K periodic list heads, one per frame. | 413 | * hw default: 1K periodic list heads, one per frame. |
359 | * periodic_size can shrink by USBCMD update if hcc_params allows. | 414 | * periodic_size can shrink by USBCMD update if hcc_params allows. |
@@ -361,7 +416,7 @@ static int priv_init(struct usb_hcd *hcd) | |||
361 | priv->periodic_size = DEFAULT_I_TDPS; | 416 | priv->periodic_size = DEFAULT_I_TDPS; |
362 | 417 | ||
363 | /* controllers may cache some of the periodic schedule ... */ | 418 | /* controllers may cache some of the periodic schedule ... */ |
364 | hcc_params = isp1760_readl(hcd->regs + HC_HCCPARAMS); | 419 | hcc_params = reg_read32(hcd->regs, HC_HCCPARAMS); |
365 | /* full frame cache */ | 420 | /* full frame cache */ |
366 | if (HCC_ISOC_CACHE(hcc_params)) | 421 | if (HCC_ISOC_CACHE(hcc_params)) |
367 | priv->i_thresh = 8; | 422 | priv->i_thresh = 8; |
@@ -398,46 +453,52 @@ static int isp1760_hc_setup(struct usb_hcd *hcd) | |||
398 | * Write it twice to ensure correct upper bits if switching | 453 | * Write it twice to ensure correct upper bits if switching |
399 | * to 16-bit mode. | 454 | * to 16-bit mode. |
400 | */ | 455 | */ |
401 | isp1760_writel(hwmode, hcd->regs + HC_HW_MODE_CTRL); | 456 | reg_write32(hcd->regs, HC_HW_MODE_CTRL, hwmode); |
402 | isp1760_writel(hwmode, hcd->regs + HC_HW_MODE_CTRL); | 457 | reg_write32(hcd->regs, HC_HW_MODE_CTRL, hwmode); |
403 | 458 | ||
404 | isp1760_writel(0xdeadbabe, hcd->regs + HC_SCRATCH_REG); | 459 | reg_write32(hcd->regs, HC_SCRATCH_REG, 0xdeadbabe); |
405 | /* Change bus pattern */ | 460 | /* Change bus pattern */ |
406 | scratch = isp1760_readl(hcd->regs + HC_CHIP_ID_REG); | 461 | scratch = reg_read32(hcd->regs, HC_CHIP_ID_REG); |
407 | scratch = isp1760_readl(hcd->regs + HC_SCRATCH_REG); | 462 | scratch = reg_read32(hcd->regs, HC_SCRATCH_REG); |
408 | if (scratch != 0xdeadbabe) { | 463 | if (scratch != 0xdeadbabe) { |
409 | printk(KERN_ERR "ISP1760: Scratch test failed.\n"); | 464 | dev_err(hcd->self.controller, "Scratch test failed.\n"); |
410 | return -ENODEV; | 465 | return -ENODEV; |
411 | } | 466 | } |
412 | 467 | ||
413 | /* pre reset */ | 468 | /* pre reset */ |
414 | isp1760_init_regs(hcd); | 469 | reg_write32(hcd->regs, HC_BUFFER_STATUS_REG, 0); |
470 | reg_write32(hcd->regs, HC_ATL_PTD_SKIPMAP_REG, NO_TRANSFER_ACTIVE); | ||
471 | reg_write32(hcd->regs, HC_INT_PTD_SKIPMAP_REG, NO_TRANSFER_ACTIVE); | ||
472 | reg_write32(hcd->regs, HC_ISO_PTD_SKIPMAP_REG, NO_TRANSFER_ACTIVE); | ||
415 | 473 | ||
416 | /* reset */ | 474 | /* reset */ |
417 | isp1760_writel(SW_RESET_RESET_ALL, hcd->regs + HC_RESET_REG); | 475 | reg_write32(hcd->regs, HC_RESET_REG, SW_RESET_RESET_ALL); |
418 | mdelay(100); | 476 | mdelay(100); |
419 | 477 | ||
420 | isp1760_writel(SW_RESET_RESET_HC, hcd->regs + HC_RESET_REG); | 478 | reg_write32(hcd->regs, HC_RESET_REG, SW_RESET_RESET_HC); |
421 | mdelay(100); | 479 | mdelay(100); |
422 | 480 | ||
423 | result = ehci_reset(priv); | 481 | result = ehci_reset(hcd); |
424 | if (result) | 482 | if (result) |
425 | return result; | 483 | return result; |
426 | 484 | ||
427 | /* Step 11 passed */ | 485 | /* Step 11 passed */ |
428 | 486 | ||
429 | isp1760_info(priv, "bus width: %d, oc: %s\n", | 487 | dev_info(hcd->self.controller, "bus width: %d, oc: %s\n", |
430 | (priv->devflags & ISP1760_FLAG_BUS_WIDTH_16) ? | 488 | (priv->devflags & ISP1760_FLAG_BUS_WIDTH_16) ? |
431 | 16 : 32, (priv->devflags & ISP1760_FLAG_ANALOG_OC) ? | 489 | 16 : 32, (priv->devflags & ISP1760_FLAG_ANALOG_OC) ? |
432 | "analog" : "digital"); | 490 | "analog" : "digital"); |
433 | 491 | ||
492 | /* This is weird: at the first plug-in of a device there seems to be | ||
493 | one packet queued that never gets returned? */ | ||
494 | priv->active_ptds = -1; | ||
495 | |||
434 | /* ATL reset */ | 496 | /* ATL reset */ |
435 | isp1760_writel(hwmode | ALL_ATX_RESET, hcd->regs + HC_HW_MODE_CTRL); | 497 | reg_write32(hcd->regs, HC_HW_MODE_CTRL, hwmode | ALL_ATX_RESET); |
436 | mdelay(10); | 498 | mdelay(10); |
437 | isp1760_writel(hwmode, hcd->regs + HC_HW_MODE_CTRL); | 499 | reg_write32(hcd->regs, HC_HW_MODE_CTRL, hwmode); |
438 | 500 | ||
439 | isp1760_writel(INTERRUPT_ENABLE_MASK, hcd->regs + HC_INTERRUPT_REG); | 501 | reg_write32(hcd->regs, HC_INTERRUPT_ENABLE, INTERRUPT_ENABLE_MASK); |
440 | isp1760_writel(INTERRUPT_ENABLE_MASK, hcd->regs + HC_INTERRUPT_ENABLE); | ||
441 | 502 | ||
442 | /* | 503 | /* |
443 | * PORT 1 Control register of the ISP1760 is the OTG control | 504 | * PORT 1 Control register of the ISP1760 is the OTG control |
@@ -445,11 +506,10 @@ static int isp1760_hc_setup(struct usb_hcd *hcd) | |||
445 | * support in this driver, we use port 1 as a "normal" USB host port on | 506 | * support in this driver, we use port 1 as a "normal" USB host port on |
446 | * both chips. | 507 | * both chips. |
447 | */ | 508 | */ |
448 | isp1760_writel(PORT1_POWER | PORT1_INIT2, | 509 | reg_write32(hcd->regs, HC_PORT1_CTRL, PORT1_POWER | PORT1_INIT2); |
449 | hcd->regs + HC_PORT1_CTRL); | ||
450 | mdelay(10); | 510 | mdelay(10); |
451 | 511 | ||
452 | priv->hcs_params = isp1760_readl(hcd->regs + HC_HCSPARAMS); | 512 | priv->hcs_params = reg_read32(hcd->regs, HC_HCSPARAMS); |
453 | 513 | ||
454 | return priv_init(hcd); | 514 | return priv_init(hcd); |
455 | } | 515 | } |
@@ -457,25 +517,31 @@ static int isp1760_hc_setup(struct usb_hcd *hcd) | |||
457 | static void isp1760_init_maps(struct usb_hcd *hcd) | 517 | static void isp1760_init_maps(struct usb_hcd *hcd) |
458 | { | 518 | { |
459 | /*set last maps, for iso its only 1, else 32 tds bitmap*/ | 519 | /*set last maps, for iso its only 1, else 32 tds bitmap*/ |
460 | isp1760_writel(0x80000000, hcd->regs + HC_ATL_PTD_LASTPTD_REG); | 520 | reg_write32(hcd->regs, HC_ATL_PTD_LASTPTD_REG, 0x80000000); |
461 | isp1760_writel(0x80000000, hcd->regs + HC_INT_PTD_LASTPTD_REG); | 521 | reg_write32(hcd->regs, HC_INT_PTD_LASTPTD_REG, 0x80000000); |
462 | isp1760_writel(0x00000001, hcd->regs + HC_ISO_PTD_LASTPTD_REG); | 522 | reg_write32(hcd->regs, HC_ISO_PTD_LASTPTD_REG, 0x00000001); |
523 | |||
524 | reg_write32(hcd->regs, HC_ATL_PTD_SKIPMAP_REG, 0xffffffff); | ||
525 | reg_write32(hcd->regs, HC_INT_PTD_SKIPMAP_REG, 0xffffffff); | ||
526 | reg_write32(hcd->regs, HC_ISO_PTD_SKIPMAP_REG, 0xffffffff); | ||
527 | |||
528 | reg_write32(hcd->regs, HC_BUFFER_STATUS_REG, | ||
529 | ATL_BUF_FILL | INT_BUF_FILL); | ||
463 | } | 530 | } |
464 | 531 | ||
465 | static void isp1760_enable_interrupts(struct usb_hcd *hcd) | 532 | static void isp1760_enable_interrupts(struct usb_hcd *hcd) |
466 | { | 533 | { |
467 | isp1760_writel(0, hcd->regs + HC_ATL_IRQ_MASK_AND_REG); | 534 | reg_write32(hcd->regs, HC_ATL_IRQ_MASK_AND_REG, 0); |
468 | isp1760_writel(0, hcd->regs + HC_ATL_IRQ_MASK_OR_REG); | 535 | reg_write32(hcd->regs, HC_ATL_IRQ_MASK_OR_REG, 0xffffffff); |
469 | isp1760_writel(0, hcd->regs + HC_INT_IRQ_MASK_AND_REG); | 536 | reg_write32(hcd->regs, HC_INT_IRQ_MASK_AND_REG, 0); |
470 | isp1760_writel(0, hcd->regs + HC_INT_IRQ_MASK_OR_REG); | 537 | reg_write32(hcd->regs, HC_INT_IRQ_MASK_OR_REG, 0xffffffff); |
471 | isp1760_writel(0, hcd->regs + HC_ISO_IRQ_MASK_AND_REG); | 538 | reg_write32(hcd->regs, HC_ISO_IRQ_MASK_AND_REG, 0); |
472 | isp1760_writel(0xffffffff, hcd->regs + HC_ISO_IRQ_MASK_OR_REG); | 539 | reg_write32(hcd->regs, HC_ISO_IRQ_MASK_OR_REG, 0xffffffff); |
473 | /* step 23 passed */ | 540 | /* step 23 passed */ |
474 | } | 541 | } |
475 | 542 | ||
476 | static int isp1760_run(struct usb_hcd *hcd) | 543 | static int isp1760_run(struct usb_hcd *hcd) |
477 | { | 544 | { |
478 | struct isp1760_hcd *priv = hcd_to_priv(hcd); | ||
479 | int retval; | 545 | int retval; |
480 | u32 temp; | 546 | u32 temp; |
481 | u32 command; | 547 | u32 command; |
@@ -485,16 +551,15 @@ static int isp1760_run(struct usb_hcd *hcd) | |||
485 | 551 | ||
486 | hcd->state = HC_STATE_RUNNING; | 552 | hcd->state = HC_STATE_RUNNING; |
487 | isp1760_enable_interrupts(hcd); | 553 | isp1760_enable_interrupts(hcd); |
488 | temp = isp1760_readl(hcd->regs + HC_HW_MODE_CTRL); | 554 | temp = reg_read32(hcd->regs, HC_HW_MODE_CTRL); |
489 | isp1760_writel(temp | HW_GLOBAL_INTR_EN, hcd->regs + HC_HW_MODE_CTRL); | 555 | reg_write32(hcd->regs, HC_HW_MODE_CTRL, temp | HW_GLOBAL_INTR_EN); |
490 | 556 | ||
491 | command = isp1760_readl(hcd->regs + HC_USBCMD); | 557 | command = reg_read32(hcd->regs, HC_USBCMD); |
492 | command &= ~(CMD_LRESET|CMD_RESET); | 558 | command &= ~(CMD_LRESET|CMD_RESET); |
493 | command |= CMD_RUN; | 559 | command |= CMD_RUN; |
494 | isp1760_writel(command, hcd->regs + HC_USBCMD); | 560 | reg_write32(hcd->regs, HC_USBCMD, command); |
495 | 561 | ||
496 | retval = handshake(priv, hcd->regs + HC_USBCMD, CMD_RUN, CMD_RUN, | 562 | retval = handshake(hcd, HC_USBCMD, CMD_RUN, CMD_RUN, 250 * 1000); |
497 | 250 * 1000); | ||
498 | if (retval) | 563 | if (retval) |
499 | return retval; | 564 | return retval; |
500 | 565 | ||
@@ -504,17 +569,16 @@ static int isp1760_run(struct usb_hcd *hcd) | |||
504 | * the semaphore while doing so. | 569 | * the semaphore while doing so. |
505 | */ | 570 | */ |
506 | down_write(&ehci_cf_port_reset_rwsem); | 571 | down_write(&ehci_cf_port_reset_rwsem); |
507 | isp1760_writel(FLAG_CF, hcd->regs + HC_CONFIGFLAG); | 572 | reg_write32(hcd->regs, HC_CONFIGFLAG, FLAG_CF); |
508 | 573 | ||
509 | retval = handshake(priv, hcd->regs + HC_CONFIGFLAG, FLAG_CF, FLAG_CF, | 574 | retval = handshake(hcd, HC_CONFIGFLAG, FLAG_CF, FLAG_CF, 250 * 1000); |
510 | 250 * 1000); | ||
511 | up_write(&ehci_cf_port_reset_rwsem); | 575 | up_write(&ehci_cf_port_reset_rwsem); |
512 | if (retval) | 576 | if (retval) |
513 | return retval; | 577 | return retval; |
514 | 578 | ||
515 | chipid = isp1760_readl(hcd->regs + HC_CHIP_ID_REG); | 579 | chipid = reg_read32(hcd->regs, HC_CHIP_ID_REG); |
516 | isp1760_info(priv, "USB ISP %04x HW rev. %d started\n", chipid & 0xffff, | 580 | dev_info(hcd->self.controller, "USB ISP %04x HW rev. %d started\n", |
517 | chipid >> 16); | 581 | chipid & 0xffff, chipid >> 16); |
518 | 582 | ||
519 | /* PTD Register Init Part 2, Step 28 */ | 583 | /* PTD Register Init Part 2, Step 28 */ |
520 | /* enable INTs */ | 584 | /* enable INTs */ |
@@ -532,378 +596,169 @@ static u32 base_to_chip(u32 base) | |||
532 | return ((base - 0x400) >> 3); | 596 | return ((base - 0x400) >> 3); |
533 | } | 597 | } |
534 | 598 | ||
535 | static void transform_into_atl(struct isp1760_hcd *priv, struct isp1760_qh *qh, | 599 | static int last_qtd_of_urb(struct isp1760_qtd *qtd, struct isp1760_qh *qh) |
536 | struct isp1760_qtd *qtd, struct urb *urb, | 600 | { |
537 | u32 payload, struct ptd *ptd) | 601 | struct urb *urb; |
602 | |||
603 | if (list_is_last(&qtd->qtd_list, &qh->qtd_list)) | ||
604 | return 1; | ||
605 | |||
606 | urb = qtd->urb; | ||
607 | qtd = list_entry(qtd->qtd_list.next, typeof(*qtd), qtd_list); | ||
608 | return (qtd->urb != urb); | ||
609 | } | ||
610 | |||
611 | /* magic numbers that can affect system performance */ | ||
612 | #define EHCI_TUNE_CERR 3 /* 0-3 qtd retries; 0 == don't stop */ | ||
613 | #define EHCI_TUNE_RL_HS 4 /* nak throttle; see 4.9 */ | ||
614 | #define EHCI_TUNE_RL_TT 0 | ||
615 | #define EHCI_TUNE_MULT_HS 1 /* 1-3 transactions/uframe; 4.10.3 */ | ||
616 | #define EHCI_TUNE_MULT_TT 1 | ||
617 | #define EHCI_TUNE_FLS 2 /* (small) 256 frame schedule */ | ||
618 | |||
619 | static void create_ptd_atl(struct isp1760_qh *qh, | ||
620 | struct isp1760_qtd *qtd, struct ptd *ptd) | ||
538 | { | 621 | { |
539 | u32 dw0; | ||
540 | u32 dw1; | ||
541 | u32 dw2; | ||
542 | u32 dw3; | ||
543 | u32 maxpacket; | 622 | u32 maxpacket; |
544 | u32 multi; | 623 | u32 multi; |
545 | u32 pid_code; | ||
546 | u32 rl = RL_COUNTER; | 624 | u32 rl = RL_COUNTER; |
547 | u32 nak = NAK_COUNTER; | 625 | u32 nak = NAK_COUNTER; |
548 | 626 | ||
627 | memset(ptd, 0, sizeof(*ptd)); | ||
628 | |||
549 | /* according to 3.6.2, max packet len can not be > 0x400 */ | 629 | /* according to 3.6.2, max packet len can not be > 0x400 */ |
550 | maxpacket = usb_maxpacket(urb->dev, urb->pipe, usb_pipeout(urb->pipe)); | 630 | maxpacket = usb_maxpacket(qtd->urb->dev, qtd->urb->pipe, |
631 | usb_pipeout(qtd->urb->pipe)); | ||
551 | multi = 1 + ((maxpacket >> 11) & 0x3); | 632 | multi = 1 + ((maxpacket >> 11) & 0x3); |
552 | maxpacket &= 0x7ff; | 633 | maxpacket &= 0x7ff; |
553 | 634 | ||
554 | /* DW0 */ | 635 | /* DW0 */ |
555 | dw0 = PTD_VALID; | 636 | ptd->dw0 = DW0_VALID_BIT; |
556 | dw0 |= PTD_LENGTH(qtd->length); | 637 | ptd->dw0 |= TO_DW0_LENGTH(qtd->length); |
557 | dw0 |= PTD_MAXPACKET(maxpacket); | 638 | ptd->dw0 |= TO_DW0_MAXPACKET(maxpacket); |
558 | dw0 |= PTD_ENDPOINT(usb_pipeendpoint(urb->pipe)); | 639 | ptd->dw0 |= TO_DW0_ENDPOINT(usb_pipeendpoint(qtd->urb->pipe)); |
559 | dw1 = usb_pipeendpoint(urb->pipe) >> 1; | ||
560 | 640 | ||
561 | /* DW1 */ | 641 | /* DW1 */ |
562 | dw1 |= PTD_DEVICE_ADDR(usb_pipedevice(urb->pipe)); | 642 | ptd->dw1 = usb_pipeendpoint(qtd->urb->pipe) >> 1; |
643 | ptd->dw1 |= TO_DW1_DEVICE_ADDR(usb_pipedevice(qtd->urb->pipe)); | ||
644 | ptd->dw1 |= TO_DW1_PID_TOKEN(qtd->packet_type); | ||
563 | 645 | ||
564 | pid_code = qtd->packet_type; | 646 | if (usb_pipebulk(qtd->urb->pipe)) |
565 | dw1 |= PTD_PID_TOKEN(pid_code); | 647 | ptd->dw1 |= DW1_TRANS_BULK; |
648 | else if (usb_pipeint(qtd->urb->pipe)) | ||
649 | ptd->dw1 |= DW1_TRANS_INT; | ||
566 | 650 | ||
567 | if (usb_pipebulk(urb->pipe)) | 651 | if (qtd->urb->dev->speed != USB_SPEED_HIGH) { |
568 | dw1 |= PTD_TRANS_BULK; | ||
569 | else if (usb_pipeint(urb->pipe)) | ||
570 | dw1 |= PTD_TRANS_INT; | ||
571 | |||
572 | if (urb->dev->speed != USB_SPEED_HIGH) { | ||
573 | /* split transaction */ | 652 | /* split transaction */ |
574 | 653 | ||
575 | dw1 |= PTD_TRANS_SPLIT; | 654 | ptd->dw1 |= DW1_TRANS_SPLIT; |
576 | if (urb->dev->speed == USB_SPEED_LOW) | 655 | if (qtd->urb->dev->speed == USB_SPEED_LOW) |
577 | dw1 |= PTD_SE_USB_LOSPEED; | 656 | ptd->dw1 |= DW1_SE_USB_LOSPEED; |
578 | 657 | ||
579 | dw1 |= PTD_PORT_NUM(urb->dev->ttport); | 658 | ptd->dw1 |= TO_DW1_PORT_NUM(qtd->urb->dev->ttport); |
580 | dw1 |= PTD_HUB_NUM(urb->dev->tt->hub->devnum); | 659 | ptd->dw1 |= TO_DW1_HUB_NUM(qtd->urb->dev->tt->hub->devnum); |
581 | 660 | ||
582 | /* SE bit for Split INT transfers */ | 661 | /* SE bit for Split INT transfers */ |
583 | if (usb_pipeint(urb->pipe) && | 662 | if (usb_pipeint(qtd->urb->pipe) && |
584 | (urb->dev->speed == USB_SPEED_LOW)) | 663 | (qtd->urb->dev->speed == USB_SPEED_LOW)) |
585 | dw1 |= 2 << 16; | 664 | ptd->dw1 |= 2 << 16; |
586 | 665 | ||
587 | dw3 = 0; | ||
588 | rl = 0; | 666 | rl = 0; |
589 | nak = 0; | 667 | nak = 0; |
590 | } else { | 668 | } else { |
591 | dw0 |= PTD_MULTI(multi); | 669 | ptd->dw0 |= TO_DW0_MULTI(multi); |
592 | if (usb_pipecontrol(urb->pipe) || usb_pipebulk(urb->pipe)) | 670 | if (usb_pipecontrol(qtd->urb->pipe) || |
593 | dw3 = qh->ping; | 671 | usb_pipebulk(qtd->urb->pipe)) |
594 | else | 672 | ptd->dw3 |= TO_DW3_PING(qh->ping); |
595 | dw3 = 0; | ||
596 | } | 673 | } |
597 | /* DW2 */ | 674 | /* DW2 */ |
598 | dw2 = 0; | 675 | ptd->dw2 = 0; |
599 | dw2 |= PTD_DATA_START_ADDR(base_to_chip(payload)); | 676 | ptd->dw2 |= TO_DW2_DATA_START_ADDR(base_to_chip(qtd->payload_addr)); |
600 | dw2 |= PTD_RL_CNT(rl); | 677 | ptd->dw2 |= TO_DW2_RL(rl); |
601 | dw3 |= PTD_NAC_CNT(nak); | ||
602 | 678 | ||
603 | /* DW3 */ | 679 | /* DW3 */ |
604 | if (usb_pipecontrol(urb->pipe)) | 680 | ptd->dw3 |= TO_DW3_NAKCOUNT(nak); |
605 | dw3 |= PTD_DATA_TOGGLE(qtd->toggle); | 681 | ptd->dw3 |= TO_DW3_DATA_TOGGLE(qh->toggle); |
606 | else | 682 | if (usb_pipecontrol(qtd->urb->pipe)) { |
607 | dw3 |= qh->toggle; | 683 | if (qtd->data_buffer == qtd->urb->setup_packet) |
608 | 684 | ptd->dw3 &= ~TO_DW3_DATA_TOGGLE(1); | |
685 | else if (last_qtd_of_urb(qtd, qh)) | ||
686 | ptd->dw3 |= TO_DW3_DATA_TOGGLE(1); | ||
687 | } | ||
609 | 688 | ||
610 | dw3 |= PTD_ACTIVE; | 689 | ptd->dw3 |= DW3_ACTIVE_BIT; |
611 | /* Cerr */ | 690 | /* Cerr */ |
612 | dw3 |= PTD_CERR(ERR_COUNTER); | 691 | ptd->dw3 |= TO_DW3_CERR(ERR_COUNTER); |
613 | |||
614 | memset(ptd, 0, sizeof(*ptd)); | ||
615 | |||
616 | ptd->dw0 = cpu_to_le32(dw0); | ||
617 | ptd->dw1 = cpu_to_le32(dw1); | ||
618 | ptd->dw2 = cpu_to_le32(dw2); | ||
619 | ptd->dw3 = cpu_to_le32(dw3); | ||
620 | } | 692 | } |
621 | 693 | ||
622 | static void transform_add_int(struct isp1760_hcd *priv, struct isp1760_qh *qh, | 694 | static void transform_add_int(struct isp1760_qh *qh, |
623 | struct isp1760_qtd *qtd, struct urb *urb, | 695 | struct isp1760_qtd *qtd, struct ptd *ptd) |
624 | u32 payload, struct ptd *ptd) | ||
625 | { | 696 | { |
626 | u32 maxpacket; | 697 | u32 usof; |
627 | u32 multi; | ||
628 | u32 numberofusofs; | ||
629 | u32 i; | ||
630 | u32 usofmask, usof; | ||
631 | u32 period; | 698 | u32 period; |
632 | 699 | ||
633 | maxpacket = usb_maxpacket(urb->dev, urb->pipe, usb_pipeout(urb->pipe)); | 700 | /* |
634 | multi = 1 + ((maxpacket >> 11) & 0x3); | 701 | * Most of this is guessing. ISP1761 datasheet is quite unclear, and |
635 | maxpacket &= 0x7ff; | 702 | * the algorithm from the original Philips driver code, which was |
636 | /* length of the data per uframe */ | 703 | * pretty much used in this driver before as well, is quite horrendous |
637 | maxpacket = multi * maxpacket; | 704 | * and, i believe, incorrect. The code below follows the datasheet and |
638 | 705 | * USB2.0 spec as far as I can tell, and plug/unplug seems to be much | |
639 | numberofusofs = urb->transfer_buffer_length / maxpacket; | 706 | * more reliable this way (fingers crossed...). |
640 | if (urb->transfer_buffer_length % maxpacket) | 707 | */ |
641 | numberofusofs += 1; | ||
642 | |||
643 | usofmask = 1; | ||
644 | usof = 0; | ||
645 | for (i = 0; i < numberofusofs; i++) { | ||
646 | usof |= usofmask; | ||
647 | usofmask <<= 1; | ||
648 | } | ||
649 | |||
650 | if (urb->dev->speed != USB_SPEED_HIGH) { | ||
651 | /* split */ | ||
652 | ptd->dw5 = cpu_to_le32(0x1c); | ||
653 | 708 | ||
654 | if (qh->period >= 32) | 709 | if (qtd->urb->dev->speed == USB_SPEED_HIGH) { |
655 | period = qh->period / 2; | 710 | /* urb->interval is in units of microframes (1/8 ms) */ |
711 | period = qtd->urb->interval >> 3; | ||
712 | |||
713 | if (qtd->urb->interval > 4) | ||
714 | usof = 0x01; /* One bit set => | ||
715 | interval 1 ms * uFrame-match */ | ||
716 | else if (qtd->urb->interval > 2) | ||
717 | usof = 0x22; /* Two bits set => interval 1/2 ms */ | ||
718 | else if (qtd->urb->interval > 1) | ||
719 | usof = 0x55; /* Four bits set => interval 1/4 ms */ | ||
656 | else | 720 | else |
657 | period = qh->period; | 721 | usof = 0xff; /* All bits set => interval 1/8 ms */ |
658 | |||
659 | } else { | 722 | } else { |
723 | /* urb->interval is in units of frames (1 ms) */ | ||
724 | period = qtd->urb->interval; | ||
725 | usof = 0x0f; /* Execute Start Split on any of the | ||
726 | four first uFrames */ | ||
660 | 727 | ||
661 | if (qh->period >= 8) | 728 | /* |
662 | period = qh->period/8; | 729 | * First 8 bits in dw5 is uSCS and "specifies which uSOF the |
663 | else | 730 | * complete split needs to be sent. Valid only for IN." Also, |
664 | period = qh->period; | 731 | * "All bits can be set to one for every transfer." (p 82, |
665 | 732 | * ISP1761 data sheet.) 0x1c is from Philips driver. Where did | |
666 | if (period >= 32) | 733 | * that number come from? 0xff seems to work fine... |
667 | period = 16; | 734 | */ |
668 | 735 | /* ptd->dw5 = 0x1c; */ | |
669 | if (qh->period >= 8) { | 736 | ptd->dw5 = 0xff; /* Execute Complete Split on any uFrame */ |
670 | /* millisecond period */ | ||
671 | period = (period << 3); | ||
672 | } else { | ||
673 | /* usof based tranmsfers */ | ||
674 | /* minimum 4 usofs */ | ||
675 | usof = 0x11; | ||
676 | } | ||
677 | } | ||
678 | |||
679 | ptd->dw2 |= cpu_to_le32(period); | ||
680 | ptd->dw4 = cpu_to_le32(usof); | ||
681 | } | ||
682 | |||
683 | static void transform_into_int(struct isp1760_hcd *priv, struct isp1760_qh *qh, | ||
684 | struct isp1760_qtd *qtd, struct urb *urb, | ||
685 | u32 payload, struct ptd *ptd) | ||
686 | { | ||
687 | transform_into_atl(priv, qh, qtd, urb, payload, ptd); | ||
688 | transform_add_int(priv, qh, qtd, urb, payload, ptd); | ||
689 | } | ||
690 | |||
691 | static int qtd_fill(struct isp1760_qtd *qtd, void *databuffer, size_t len, | ||
692 | u32 token) | ||
693 | { | ||
694 | int count; | ||
695 | |||
696 | qtd->data_buffer = databuffer; | ||
697 | qtd->packet_type = GET_QTD_TOKEN_TYPE(token); | ||
698 | qtd->toggle = GET_DATA_TOGGLE(token); | ||
699 | |||
700 | if (len > HC_ATL_PL_SIZE) | ||
701 | count = HC_ATL_PL_SIZE; | ||
702 | else | ||
703 | count = len; | ||
704 | |||
705 | qtd->length = count; | ||
706 | return count; | ||
707 | } | ||
708 | |||
709 | static int check_error(struct ptd *ptd) | ||
710 | { | ||
711 | int error = 0; | ||
712 | u32 dw3; | ||
713 | |||
714 | dw3 = le32_to_cpu(ptd->dw3); | ||
715 | if (dw3 & DW3_HALT_BIT) { | ||
716 | error = -EPIPE; | ||
717 | |||
718 | if (dw3 & DW3_ERROR_BIT) | ||
719 | pr_err("error bit is set in DW3\n"); | ||
720 | } | ||
721 | |||
722 | if (dw3 & DW3_QTD_ACTIVE) { | ||
723 | printk(KERN_ERR "transfer active bit is set DW3\n"); | ||
724 | printk(KERN_ERR "nak counter: %d, rl: %d\n", (dw3 >> 19) & 0xf, | ||
725 | (le32_to_cpu(ptd->dw2) >> 25) & 0xf); | ||
726 | } | ||
727 | |||
728 | return error; | ||
729 | } | ||
730 | |||
731 | static void check_int_err_status(u32 dw4) | ||
732 | { | ||
733 | u32 i; | ||
734 | |||
735 | dw4 >>= 8; | ||
736 | |||
737 | for (i = 0; i < 8; i++) { | ||
738 | switch (dw4 & 0x7) { | ||
739 | case INT_UNDERRUN: | ||
740 | printk(KERN_ERR "ERROR: under run , %d\n", i); | ||
741 | break; | ||
742 | |||
743 | case INT_EXACT: | ||
744 | printk(KERN_ERR "ERROR: transaction error, %d\n", i); | ||
745 | break; | ||
746 | |||
747 | case INT_BABBLE: | ||
748 | printk(KERN_ERR "ERROR: babble error, %d\n", i); | ||
749 | break; | ||
750 | } | ||
751 | dw4 >>= 3; | ||
752 | } | ||
753 | } | ||
754 | |||
755 | static void enqueue_one_qtd(struct isp1760_qtd *qtd, struct isp1760_hcd *priv, | ||
756 | u32 payload) | ||
757 | { | ||
758 | u32 token; | ||
759 | struct usb_hcd *hcd = priv_to_hcd(priv); | ||
760 | |||
761 | token = qtd->packet_type; | ||
762 | |||
763 | if (qtd->length && (qtd->length <= HC_ATL_PL_SIZE)) { | ||
764 | switch (token) { | ||
765 | case IN_PID: | ||
766 | break; | ||
767 | case OUT_PID: | ||
768 | case SETUP_PID: | ||
769 | priv_write_copy(priv, qtd->data_buffer, | ||
770 | hcd->regs + payload, | ||
771 | qtd->length); | ||
772 | } | ||
773 | } | 737 | } |
774 | } | ||
775 | |||
776 | static void enqueue_one_atl_qtd(u32 atl_regs, u32 payload, | ||
777 | struct isp1760_hcd *priv, struct isp1760_qh *qh, | ||
778 | struct urb *urb, u32 slot, struct isp1760_qtd *qtd) | ||
779 | { | ||
780 | struct ptd ptd; | ||
781 | struct usb_hcd *hcd = priv_to_hcd(priv); | ||
782 | |||
783 | transform_into_atl(priv, qh, qtd, urb, payload, &ptd); | ||
784 | priv_write_copy(priv, (u32 *)&ptd, hcd->regs + atl_regs, sizeof(ptd)); | ||
785 | enqueue_one_qtd(qtd, priv, payload); | ||
786 | |||
787 | priv->atl_ints[slot].urb = urb; | ||
788 | priv->atl_ints[slot].qh = qh; | ||
789 | priv->atl_ints[slot].qtd = qtd; | ||
790 | priv->atl_ints[slot].data_buffer = qtd->data_buffer; | ||
791 | priv->atl_ints[slot].payload = payload; | ||
792 | qtd->status |= URB_ENQUEUED | URB_TYPE_ATL; | ||
793 | qtd->status |= slot << 16; | ||
794 | } | ||
795 | |||
796 | static void enqueue_one_int_qtd(u32 int_regs, u32 payload, | ||
797 | struct isp1760_hcd *priv, struct isp1760_qh *qh, | ||
798 | struct urb *urb, u32 slot, struct isp1760_qtd *qtd) | ||
799 | { | ||
800 | struct ptd ptd; | ||
801 | struct usb_hcd *hcd = priv_to_hcd(priv); | ||
802 | |||
803 | transform_into_int(priv, qh, qtd, urb, payload, &ptd); | ||
804 | priv_write_copy(priv, (u32 *)&ptd, hcd->regs + int_regs, sizeof(ptd)); | ||
805 | enqueue_one_qtd(qtd, priv, payload); | ||
806 | |||
807 | priv->int_ints[slot].urb = urb; | ||
808 | priv->int_ints[slot].qh = qh; | ||
809 | priv->int_ints[slot].qtd = qtd; | ||
810 | priv->int_ints[slot].data_buffer = qtd->data_buffer; | ||
811 | priv->int_ints[slot].payload = payload; | ||
812 | qtd->status |= URB_ENQUEUED | URB_TYPE_INT; | ||
813 | qtd->status |= slot << 16; | ||
814 | } | ||
815 | |||
816 | static void enqueue_an_ATL_packet(struct usb_hcd *hcd, struct isp1760_qh *qh, | ||
817 | struct isp1760_qtd *qtd) | ||
818 | { | ||
819 | struct isp1760_hcd *priv = hcd_to_priv(hcd); | ||
820 | u32 skip_map, or_map; | ||
821 | u32 queue_entry; | ||
822 | u32 slot; | ||
823 | u32 atl_regs, payload; | ||
824 | u32 buffstatus; | ||
825 | |||
826 | /* | ||
827 | * When this function is called from the interrupt handler to enqueue | ||
828 | * a follow-up packet, the SKIP register gets written and read back | ||
829 | * almost immediately. With ISP1761, this register requires a delay of | ||
830 | * 195ns between a write and subsequent read (see section 15.1.1.3). | ||
831 | */ | ||
832 | mmiowb(); | ||
833 | ndelay(195); | ||
834 | skip_map = isp1760_readl(hcd->regs + HC_ATL_PTD_SKIPMAP_REG); | ||
835 | |||
836 | BUG_ON(!skip_map); | ||
837 | slot = __ffs(skip_map); | ||
838 | queue_entry = 1 << slot; | ||
839 | |||
840 | atl_regs = ATL_REGS_OFFSET + slot * sizeof(struct ptd); | ||
841 | 738 | ||
842 | payload = alloc_mem(priv, qtd->length); | 739 | period = period >> 1;/* Ensure equal or shorter period than requested */ |
740 | period &= 0xf8; /* Mask off too large values and lowest unused 3 bits */ | ||
843 | 741 | ||
844 | enqueue_one_atl_qtd(atl_regs, payload, priv, qh, qtd->urb, slot, qtd); | 742 | ptd->dw2 |= period; |
845 | 743 | ptd->dw4 = usof; | |
846 | or_map = isp1760_readl(hcd->regs + HC_ATL_IRQ_MASK_OR_REG); | ||
847 | or_map |= queue_entry; | ||
848 | isp1760_writel(or_map, hcd->regs + HC_ATL_IRQ_MASK_OR_REG); | ||
849 | |||
850 | skip_map &= ~queue_entry; | ||
851 | isp1760_writel(skip_map, hcd->regs + HC_ATL_PTD_SKIPMAP_REG); | ||
852 | |||
853 | buffstatus = isp1760_readl(hcd->regs + HC_BUFFER_STATUS_REG); | ||
854 | buffstatus |= ATL_BUFFER; | ||
855 | isp1760_writel(buffstatus, hcd->regs + HC_BUFFER_STATUS_REG); | ||
856 | } | 744 | } |
857 | 745 | ||
858 | static void enqueue_an_INT_packet(struct usb_hcd *hcd, struct isp1760_qh *qh, | 746 | static void create_ptd_int(struct isp1760_qh *qh, |
859 | struct isp1760_qtd *qtd) | 747 | struct isp1760_qtd *qtd, struct ptd *ptd) |
860 | { | 748 | { |
861 | struct isp1760_hcd *priv = hcd_to_priv(hcd); | 749 | create_ptd_atl(qh, qtd, ptd); |
862 | u32 skip_map, or_map; | 750 | transform_add_int(qh, qtd, ptd); |
863 | u32 queue_entry; | ||
864 | u32 slot; | ||
865 | u32 int_regs, payload; | ||
866 | u32 buffstatus; | ||
867 | |||
868 | /* | ||
869 | * When this function is called from the interrupt handler to enqueue | ||
870 | * a follow-up packet, the SKIP register gets written and read back | ||
871 | * almost immediately. With ISP1761, this register requires a delay of | ||
872 | * 195ns between a write and subsequent read (see section 15.1.1.3). | ||
873 | */ | ||
874 | mmiowb(); | ||
875 | ndelay(195); | ||
876 | skip_map = isp1760_readl(hcd->regs + HC_INT_PTD_SKIPMAP_REG); | ||
877 | |||
878 | BUG_ON(!skip_map); | ||
879 | slot = __ffs(skip_map); | ||
880 | queue_entry = 1 << slot; | ||
881 | |||
882 | int_regs = INT_REGS_OFFSET + slot * sizeof(struct ptd); | ||
883 | |||
884 | payload = alloc_mem(priv, qtd->length); | ||
885 | |||
886 | enqueue_one_int_qtd(int_regs, payload, priv, qh, qtd->urb, slot, qtd); | ||
887 | |||
888 | or_map = isp1760_readl(hcd->regs + HC_INT_IRQ_MASK_OR_REG); | ||
889 | or_map |= queue_entry; | ||
890 | isp1760_writel(or_map, hcd->regs + HC_INT_IRQ_MASK_OR_REG); | ||
891 | |||
892 | skip_map &= ~queue_entry; | ||
893 | isp1760_writel(skip_map, hcd->regs + HC_INT_PTD_SKIPMAP_REG); | ||
894 | |||
895 | buffstatus = isp1760_readl(hcd->regs + HC_BUFFER_STATUS_REG); | ||
896 | buffstatus |= INT_BUFFER; | ||
897 | isp1760_writel(buffstatus, hcd->regs + HC_BUFFER_STATUS_REG); | ||
898 | } | 751 | } |
899 | 752 | ||
900 | static void isp1760_urb_done(struct isp1760_hcd *priv, struct urb *urb, int status) | 753 | static void isp1760_urb_done(struct usb_hcd *hcd, struct urb *urb) |
901 | __releases(priv->lock) | 754 | __releases(priv->lock) |
902 | __acquires(priv->lock) | 755 | __acquires(priv->lock) |
903 | { | 756 | { |
757 | struct isp1760_hcd *priv = hcd_to_priv(hcd); | ||
758 | |||
904 | if (!urb->unlinked) { | 759 | if (!urb->unlinked) { |
905 | if (status == -EINPROGRESS) | 760 | if (urb->status == -EINPROGRESS) |
906 | status = 0; | 761 | urb->status = 0; |
907 | } | 762 | } |
908 | 763 | ||
909 | if (usb_pipein(urb->pipe) && usb_pipetype(urb->pipe) != PIPE_CONTROL) { | 764 | if (usb_pipein(urb->pipe) && usb_pipetype(urb->pipe) != PIPE_CONTROL) { |
@@ -915,679 +770,660 @@ __acquires(priv->lock) | |||
915 | } | 770 | } |
916 | 771 | ||
917 | /* complete() can reenter this HCD */ | 772 | /* complete() can reenter this HCD */ |
918 | usb_hcd_unlink_urb_from_ep(priv_to_hcd(priv), urb); | 773 | usb_hcd_unlink_urb_from_ep(hcd, urb); |
919 | spin_unlock(&priv->lock); | 774 | spin_unlock(&priv->lock); |
920 | usb_hcd_giveback_urb(priv_to_hcd(priv), urb, status); | 775 | usb_hcd_giveback_urb(hcd, urb, urb->status); |
921 | spin_lock(&priv->lock); | 776 | spin_lock(&priv->lock); |
922 | } | 777 | } |
923 | 778 | ||
924 | static void isp1760_qtd_free(struct isp1760_qtd *qtd) | 779 | static struct isp1760_qtd *qtd_alloc(gfp_t flags, struct urb *urb, |
780 | u8 packet_type) | ||
925 | { | 781 | { |
926 | kmem_cache_free(qtd_cachep, qtd); | 782 | struct isp1760_qtd *qtd; |
927 | } | ||
928 | |||
929 | static struct isp1760_qtd *clean_this_qtd(struct isp1760_qtd *qtd) | ||
930 | { | ||
931 | struct isp1760_qtd *tmp_qtd; | ||
932 | |||
933 | tmp_qtd = qtd->hw_next; | ||
934 | list_del(&qtd->qtd_list); | ||
935 | isp1760_qtd_free(qtd); | ||
936 | return tmp_qtd; | ||
937 | } | ||
938 | 783 | ||
939 | /* | 784 | qtd = kmem_cache_zalloc(qtd_cachep, flags); |
940 | * Remove this QTD from the QH list and free its memory. If this QTD | 785 | if (!qtd) |
941 | * isn't the last one than remove also his successor(s). | 786 | return NULL; |
942 | * Returns the QTD which is part of an new URB and should be enqueued. | ||
943 | */ | ||
944 | static struct isp1760_qtd *clean_up_qtdlist(struct isp1760_qtd *qtd) | ||
945 | { | ||
946 | struct isp1760_qtd *tmp_qtd; | ||
947 | int last_one; | ||
948 | 787 | ||
949 | do { | 788 | INIT_LIST_HEAD(&qtd->qtd_list); |
950 | tmp_qtd = qtd->hw_next; | 789 | qtd->urb = urb; |
951 | last_one = qtd->status & URB_COMPLETE_NOTIFY; | 790 | qtd->packet_type = packet_type; |
952 | list_del(&qtd->qtd_list); | 791 | qtd->status = QTD_ENQUEUED; |
953 | isp1760_qtd_free(qtd); | 792 | qtd->actual_length = 0; |
954 | qtd = tmp_qtd; | ||
955 | } while (!last_one && qtd); | ||
956 | 793 | ||
957 | return qtd; | 794 | return qtd; |
958 | } | 795 | } |
959 | 796 | ||
960 | static void do_atl_int(struct usb_hcd *usb_hcd) | 797 | static void qtd_free(struct isp1760_qtd *qtd) |
961 | { | 798 | { |
962 | struct isp1760_hcd *priv = hcd_to_priv(usb_hcd); | 799 | WARN_ON(qtd->payload_addr); |
963 | u32 done_map, skip_map; | 800 | kmem_cache_free(qtd_cachep, qtd); |
964 | struct ptd ptd; | 801 | } |
965 | struct urb *urb = NULL; | ||
966 | u32 atl_regs_base; | ||
967 | u32 atl_regs; | ||
968 | u32 queue_entry; | ||
969 | u32 payload; | ||
970 | u32 length; | ||
971 | u32 or_map; | ||
972 | u32 status = -EINVAL; | ||
973 | int error; | ||
974 | struct isp1760_qtd *qtd; | ||
975 | struct isp1760_qh *qh; | ||
976 | u32 rl; | ||
977 | u32 nakcount; | ||
978 | |||
979 | done_map = isp1760_readl(usb_hcd->regs + | ||
980 | HC_ATL_PTD_DONEMAP_REG); | ||
981 | skip_map = isp1760_readl(usb_hcd->regs + | ||
982 | HC_ATL_PTD_SKIPMAP_REG); | ||
983 | |||
984 | or_map = isp1760_readl(usb_hcd->regs + HC_ATL_IRQ_MASK_OR_REG); | ||
985 | or_map &= ~done_map; | ||
986 | isp1760_writel(or_map, usb_hcd->regs + HC_ATL_IRQ_MASK_OR_REG); | ||
987 | |||
988 | atl_regs_base = ATL_REGS_OFFSET; | ||
989 | while (done_map) { | ||
990 | u32 dw1; | ||
991 | u32 dw2; | ||
992 | u32 dw3; | ||
993 | |||
994 | status = 0; | ||
995 | |||
996 | queue_entry = __ffs(done_map); | ||
997 | done_map &= ~(1 << queue_entry); | ||
998 | skip_map |= 1 << queue_entry; | ||
999 | |||
1000 | atl_regs = atl_regs_base + queue_entry * sizeof(struct ptd); | ||
1001 | |||
1002 | urb = priv->atl_ints[queue_entry].urb; | ||
1003 | qtd = priv->atl_ints[queue_entry].qtd; | ||
1004 | qh = priv->atl_ints[queue_entry].qh; | ||
1005 | payload = priv->atl_ints[queue_entry].payload; | ||
1006 | |||
1007 | if (!qh) { | ||
1008 | printk(KERN_ERR "qh is 0\n"); | ||
1009 | continue; | ||
1010 | } | ||
1011 | isp1760_writel(atl_regs + ISP_BANK(0), usb_hcd->regs + | ||
1012 | HC_MEMORY_REG); | ||
1013 | isp1760_writel(payload + ISP_BANK(1), usb_hcd->regs + | ||
1014 | HC_MEMORY_REG); | ||
1015 | /* | ||
1016 | * write bank1 address twice to ensure the 90ns delay (time | ||
1017 | * between BANK0 write and the priv_read_copy() call is at | ||
1018 | * least 3*t_WHWL + 2*t_w11 = 3*25ns + 2*17ns = 109ns) | ||
1019 | */ | ||
1020 | isp1760_writel(payload + ISP_BANK(1), usb_hcd->regs + | ||
1021 | HC_MEMORY_REG); | ||
1022 | |||
1023 | priv_read_copy(priv, (u32 *)&ptd, usb_hcd->regs + atl_regs + | ||
1024 | ISP_BANK(0), sizeof(ptd)); | ||
1025 | 802 | ||
1026 | dw1 = le32_to_cpu(ptd.dw1); | 803 | static void start_bus_transfer(struct usb_hcd *hcd, u32 ptd_offset, int slot, |
1027 | dw2 = le32_to_cpu(ptd.dw2); | 804 | struct slotinfo *slots, struct isp1760_qtd *qtd, |
1028 | dw3 = le32_to_cpu(ptd.dw3); | 805 | struct isp1760_qh *qh, struct ptd *ptd) |
1029 | rl = (dw2 >> 25) & 0x0f; | 806 | { |
1030 | nakcount = (dw3 >> 19) & 0xf; | 807 | struct isp1760_hcd *priv = hcd_to_priv(hcd); |
808 | int skip_map; | ||
809 | |||
810 | WARN_ON((slot < 0) || (slot > 31)); | ||
811 | WARN_ON(qtd->length && !qtd->payload_addr); | ||
812 | WARN_ON(slots[slot].qtd); | ||
813 | WARN_ON(slots[slot].qh); | ||
814 | WARN_ON(qtd->status != QTD_PAYLOAD_ALLOC); | ||
815 | |||
816 | slots[slot].qtd = qtd; | ||
817 | slots[slot].qh = qh; | ||
818 | qh->slot = slot; | ||
819 | qtd->status = QTD_XFER_STARTED; /* Set this before writing ptd, since | ||
820 | interrupt routine may preempt and expects this value. */ | ||
821 | ptd_write(hcd->regs, ptd_offset, slot, ptd); | ||
822 | priv->active_ptds++; | ||
823 | |||
824 | /* Make sure done map has not triggered from some unlinked transfer */ | ||
825 | if (ptd_offset == ATL_PTD_OFFSET) { | ||
826 | priv->atl_done_map |= reg_read32(hcd->regs, | ||
827 | HC_ATL_PTD_DONEMAP_REG); | ||
828 | priv->atl_done_map &= ~(1 << qh->slot); | ||
829 | |||
830 | skip_map = reg_read32(hcd->regs, HC_ATL_PTD_SKIPMAP_REG); | ||
831 | skip_map &= ~(1 << qh->slot); | ||
832 | reg_write32(hcd->regs, HC_ATL_PTD_SKIPMAP_REG, skip_map); | ||
833 | } else { | ||
834 | priv->int_done_map |= reg_read32(hcd->regs, | ||
835 | HC_INT_PTD_DONEMAP_REG); | ||
836 | priv->int_done_map &= ~(1 << qh->slot); | ||
1031 | 837 | ||
1032 | /* Transfer Error, *but* active and no HALT -> reload */ | 838 | skip_map = reg_read32(hcd->regs, HC_INT_PTD_SKIPMAP_REG); |
1033 | if ((dw3 & DW3_ERROR_BIT) && (dw3 & DW3_QTD_ACTIVE) && | 839 | skip_map &= ~(1 << qh->slot); |
1034 | !(dw3 & DW3_HALT_BIT)) { | 840 | reg_write32(hcd->regs, HC_INT_PTD_SKIPMAP_REG, skip_map); |
1035 | 841 | } | |
1036 | /* according to ppriv code, we have to | 842 | } |
1037 | * reload this one if trasfered bytes != requested bytes | ||
1038 | * else act like everything went smooth.. | ||
1039 | * XXX This just doesn't feel right and hasn't | ||
1040 | * triggered so far. | ||
1041 | */ | ||
1042 | 843 | ||
1043 | length = PTD_XFERRED_LENGTH(dw3); | 844 | static int is_short_bulk(struct isp1760_qtd *qtd) |
1044 | printk(KERN_ERR "Should reload now.... transfered %d " | 845 | { |
1045 | "of %zu\n", length, qtd->length); | 846 | return (usb_pipebulk(qtd->urb->pipe) && |
1046 | BUG(); | 847 | (qtd->actual_length < qtd->length)); |
1047 | } | 848 | } |
1048 | 849 | ||
1049 | if (!nakcount && (dw3 & DW3_QTD_ACTIVE)) { | 850 | static void collect_qtds(struct usb_hcd *hcd, struct isp1760_qh *qh, |
1050 | u32 buffstatus; | 851 | struct list_head *urb_list) |
852 | { | ||
853 | int last_qtd; | ||
854 | struct isp1760_qtd *qtd, *qtd_next; | ||
855 | struct urb_listitem *urb_listitem; | ||
1051 | 856 | ||
1052 | /* | 857 | list_for_each_entry_safe(qtd, qtd_next, &qh->qtd_list, qtd_list) { |
1053 | * NAKs are handled in HW by the chip. Usually if the | 858 | if (qtd->status < QTD_XFER_COMPLETE) |
1054 | * device is not able to send data fast enough. | 859 | break; |
1055 | * This happens mostly on slower hardware. | ||
1056 | */ | ||
1057 | printk(KERN_NOTICE "Reloading ptd %p/%p... qh %p read: " | ||
1058 | "%d of %zu done: %08x cur: %08x\n", qtd, | ||
1059 | urb, qh, PTD_XFERRED_LENGTH(dw3), | ||
1060 | qtd->length, done_map, | ||
1061 | (1 << queue_entry)); | ||
1062 | 860 | ||
1063 | /* RL counter = ERR counter */ | 861 | if (list_is_last(&qtd->qtd_list, &qh->qtd_list)) |
1064 | dw3 &= ~(0xf << 19); | 862 | last_qtd = 1; |
1065 | dw3 |= rl << 19; | 863 | else |
1066 | dw3 &= ~(3 << (55 - 32)); | 864 | last_qtd = qtd->urb != qtd_next->urb; |
1067 | dw3 |= ERR_COUNTER << (55 - 32); | 865 | |
1068 | 866 | if ((!last_qtd) && (qtd->status == QTD_RETIRE)) | |
1069 | /* | 867 | qtd_next->status = QTD_RETIRE; |
1070 | * It is not needed to write skip map back because it | 868 | |
1071 | * is unchanged. Just make sure that this entry is | 869 | if (qtd->status == QTD_XFER_COMPLETE) { |
1072 | * unskipped once it gets written to the HW. | 870 | if (qtd->actual_length) { |
1073 | */ | 871 | switch (qtd->packet_type) { |
1074 | skip_map &= ~(1 << queue_entry); | 872 | case IN_PID: |
1075 | or_map = isp1760_readl(usb_hcd->regs + | 873 | mem_reads8(hcd->regs, qtd->payload_addr, |
1076 | HC_ATL_IRQ_MASK_OR_REG); | 874 | qtd->data_buffer, |
1077 | or_map |= 1 << queue_entry; | 875 | qtd->actual_length); |
1078 | isp1760_writel(or_map, usb_hcd->regs + | 876 | /* Fall through (?) */ |
1079 | HC_ATL_IRQ_MASK_OR_REG); | 877 | case OUT_PID: |
1080 | 878 | qtd->urb->actual_length += | |
1081 | ptd.dw3 = cpu_to_le32(dw3); | 879 | qtd->actual_length; |
1082 | priv_write_copy(priv, (u32 *)&ptd, usb_hcd->regs + | 880 | /* Fall through ... */ |
1083 | atl_regs, sizeof(ptd)); | 881 | case SETUP_PID: |
1084 | 882 | break; | |
1085 | ptd.dw0 |= cpu_to_le32(PTD_VALID); | 883 | } |
1086 | priv_write_copy(priv, (u32 *)&ptd, usb_hcd->regs + | 884 | } |
1087 | atl_regs, sizeof(ptd)); | ||
1088 | |||
1089 | buffstatus = isp1760_readl(usb_hcd->regs + | ||
1090 | HC_BUFFER_STATUS_REG); | ||
1091 | buffstatus |= ATL_BUFFER; | ||
1092 | isp1760_writel(buffstatus, usb_hcd->regs + | ||
1093 | HC_BUFFER_STATUS_REG); | ||
1094 | continue; | ||
1095 | } | ||
1096 | 885 | ||
1097 | error = check_error(&ptd); | 886 | if (is_short_bulk(qtd)) { |
1098 | if (error) { | 887 | if (qtd->urb->transfer_flags & URB_SHORT_NOT_OK) |
1099 | status = error; | 888 | qtd->urb->status = -EREMOTEIO; |
1100 | priv->atl_ints[queue_entry].qh->toggle = 0; | 889 | if (!last_qtd) |
1101 | priv->atl_ints[queue_entry].qh->ping = 0; | 890 | qtd_next->status = QTD_RETIRE; |
1102 | urb->status = -EPIPE; | ||
1103 | |||
1104 | #if 0 | ||
1105 | printk(KERN_ERR "Error in %s().\n", __func__); | ||
1106 | printk(KERN_ERR "IN dw0: %08x dw1: %08x dw2: %08x " | ||
1107 | "dw3: %08x dw4: %08x dw5: %08x dw6: " | ||
1108 | "%08x dw7: %08x\n", | ||
1109 | ptd.dw0, ptd.dw1, ptd.dw2, ptd.dw3, | ||
1110 | ptd.dw4, ptd.dw5, ptd.dw6, ptd.dw7); | ||
1111 | #endif | ||
1112 | } else { | ||
1113 | if (usb_pipetype(urb->pipe) == PIPE_BULK) { | ||
1114 | priv->atl_ints[queue_entry].qh->toggle = dw3 & | ||
1115 | (1 << 25); | ||
1116 | priv->atl_ints[queue_entry].qh->ping = dw3 & | ||
1117 | (1 << 26); | ||
1118 | } | 891 | } |
1119 | } | 892 | } |
1120 | 893 | ||
1121 | length = PTD_XFERRED_LENGTH(dw3); | 894 | if (qtd->payload_addr) |
1122 | if (length) { | 895 | free_mem(hcd, qtd); |
1123 | switch (DW1_GET_PID(dw1)) { | 896 | |
1124 | case IN_PID: | 897 | if (last_qtd) { |
1125 | priv_read_copy(priv, | 898 | if ((qtd->status == QTD_RETIRE) && |
1126 | priv->atl_ints[queue_entry].data_buffer, | 899 | (qtd->urb->status == -EINPROGRESS)) |
1127 | usb_hcd->regs + payload + ISP_BANK(1), | 900 | qtd->urb->status = -EPIPE; |
1128 | length); | 901 | /* Defer calling of urb_done() since it releases lock */ |
1129 | 902 | urb_listitem = kmem_cache_zalloc(urb_listitem_cachep, | |
1130 | case OUT_PID: | 903 | GFP_ATOMIC); |
1131 | 904 | if (unlikely(!urb_listitem)) | |
1132 | urb->actual_length += length; | ||
1133 | |||
1134 | case SETUP_PID: | ||
1135 | break; | 905 | break; |
1136 | } | 906 | urb_listitem->urb = qtd->urb; |
907 | list_add_tail(&urb_listitem->urb_list, urb_list); | ||
1137 | } | 908 | } |
1138 | 909 | ||
1139 | priv->atl_ints[queue_entry].data_buffer = NULL; | 910 | list_del(&qtd->qtd_list); |
1140 | priv->atl_ints[queue_entry].urb = NULL; | 911 | qtd_free(qtd); |
1141 | priv->atl_ints[queue_entry].qtd = NULL; | 912 | } |
1142 | priv->atl_ints[queue_entry].qh = NULL; | 913 | } |
1143 | 914 | ||
1144 | free_mem(priv, payload); | 915 | #define ENQUEUE_DEPTH 2 |
916 | static void enqueue_qtds(struct usb_hcd *hcd, struct isp1760_qh *qh) | ||
917 | { | ||
918 | struct isp1760_hcd *priv = hcd_to_priv(hcd); | ||
919 | int ptd_offset; | ||
920 | struct slotinfo *slots; | ||
921 | int curr_slot, free_slot; | ||
922 | int n; | ||
923 | struct ptd ptd; | ||
924 | struct isp1760_qtd *qtd; | ||
1145 | 925 | ||
1146 | isp1760_writel(skip_map, usb_hcd->regs + | 926 | if (unlikely(list_empty(&qh->qtd_list))) { |
1147 | HC_ATL_PTD_SKIPMAP_REG); | 927 | WARN_ON(1); |
928 | return; | ||
929 | } | ||
1148 | 930 | ||
1149 | if (urb->status == -EPIPE) { | 931 | if (usb_pipeint(list_entry(qh->qtd_list.next, struct isp1760_qtd, |
1150 | /* HALT was received */ | 932 | qtd_list)->urb->pipe)) { |
933 | ptd_offset = INT_PTD_OFFSET; | ||
934 | slots = priv->int_slots; | ||
935 | } else { | ||
936 | ptd_offset = ATL_PTD_OFFSET; | ||
937 | slots = priv->atl_slots; | ||
938 | } | ||
1151 | 939 | ||
1152 | qtd = clean_up_qtdlist(qtd); | 940 | free_slot = -1; |
1153 | isp1760_urb_done(priv, urb, urb->status); | 941 | for (curr_slot = 0; curr_slot < 32; curr_slot++) { |
942 | if ((free_slot == -1) && (slots[curr_slot].qtd == NULL)) | ||
943 | free_slot = curr_slot; | ||
944 | if (slots[curr_slot].qh == qh) | ||
945 | break; | ||
946 | } | ||
1154 | 947 | ||
1155 | } else if (usb_pipebulk(urb->pipe) && (length < qtd->length)) { | 948 | n = 0; |
1156 | /* short BULK received */ | 949 | list_for_each_entry(qtd, &qh->qtd_list, qtd_list) { |
950 | if (qtd->status == QTD_ENQUEUED) { | ||
951 | WARN_ON(qtd->payload_addr); | ||
952 | alloc_mem(hcd, qtd); | ||
953 | if ((qtd->length) && (!qtd->payload_addr)) | ||
954 | break; | ||
1157 | 955 | ||
1158 | if (urb->transfer_flags & URB_SHORT_NOT_OK) { | 956 | if ((qtd->length) && |
1159 | urb->status = -EREMOTEIO; | 957 | ((qtd->packet_type == SETUP_PID) || |
1160 | isp1760_dbg(priv, "short bulk, %d instead %zu " | 958 | (qtd->packet_type == OUT_PID))) { |
1161 | "with URB_SHORT_NOT_OK flag.\n", | 959 | mem_writes8(hcd->regs, qtd->payload_addr, |
1162 | length, qtd->length); | 960 | qtd->data_buffer, qtd->length); |
1163 | } | 961 | } |
1164 | 962 | ||
1165 | if (urb->status == -EINPROGRESS) | 963 | qtd->status = QTD_PAYLOAD_ALLOC; |
1166 | urb->status = 0; | ||
1167 | |||
1168 | qtd = clean_up_qtdlist(qtd); | ||
1169 | |||
1170 | isp1760_urb_done(priv, urb, urb->status); | ||
1171 | |||
1172 | } else if (qtd->status & URB_COMPLETE_NOTIFY) { | ||
1173 | /* that was the last qtd of that URB */ | ||
1174 | |||
1175 | if (urb->status == -EINPROGRESS) | ||
1176 | urb->status = 0; | ||
1177 | |||
1178 | qtd = clean_this_qtd(qtd); | ||
1179 | isp1760_urb_done(priv, urb, urb->status); | ||
1180 | |||
1181 | } else { | ||
1182 | /* next QTD of this URB */ | ||
1183 | |||
1184 | qtd = clean_this_qtd(qtd); | ||
1185 | BUG_ON(!qtd); | ||
1186 | } | 964 | } |
1187 | 965 | ||
1188 | if (qtd) | 966 | if (qtd->status == QTD_PAYLOAD_ALLOC) { |
1189 | enqueue_an_ATL_packet(usb_hcd, qh, qtd); | 967 | /* |
968 | if ((curr_slot > 31) && (free_slot == -1)) | ||
969 | dev_dbg(hcd->self.controller, "%s: No slot " | ||
970 | "available for transfer\n", __func__); | ||
971 | */ | ||
972 | /* Start xfer for this endpoint if not already done */ | ||
973 | if ((curr_slot > 31) && (free_slot > -1)) { | ||
974 | if (usb_pipeint(qtd->urb->pipe)) | ||
975 | create_ptd_int(qh, qtd, &ptd); | ||
976 | else | ||
977 | create_ptd_atl(qh, qtd, &ptd); | ||
978 | |||
979 | start_bus_transfer(hcd, ptd_offset, free_slot, | ||
980 | slots, qtd, qh, &ptd); | ||
981 | curr_slot = free_slot; | ||
982 | } | ||
1190 | 983 | ||
1191 | skip_map = isp1760_readl(usb_hcd->regs + | 984 | n++; |
1192 | HC_ATL_PTD_SKIPMAP_REG); | 985 | if (n >= ENQUEUE_DEPTH) |
986 | break; | ||
987 | } | ||
1193 | } | 988 | } |
1194 | } | 989 | } |
1195 | 990 | ||
1196 | static void do_intl_int(struct usb_hcd *usb_hcd) | 991 | void schedule_ptds(struct usb_hcd *hcd) |
1197 | { | 992 | { |
1198 | struct isp1760_hcd *priv = hcd_to_priv(usb_hcd); | 993 | struct isp1760_hcd *priv; |
1199 | u32 done_map, skip_map; | 994 | struct isp1760_qh *qh, *qh_next; |
1200 | struct ptd ptd; | 995 | struct list_head *ep_queue; |
1201 | struct urb *urb = NULL; | 996 | struct usb_host_endpoint *ep; |
1202 | u32 int_regs; | 997 | LIST_HEAD(urb_list); |
1203 | u32 int_regs_base; | 998 | struct urb_listitem *urb_listitem, *urb_listitem_next; |
1204 | u32 payload; | 999 | |
1205 | u32 length; | 1000 | if (!hcd) { |
1206 | u32 or_map; | 1001 | WARN_ON(1); |
1207 | int error; | 1002 | return; |
1208 | u32 queue_entry; | 1003 | } |
1209 | struct isp1760_qtd *qtd; | ||
1210 | struct isp1760_qh *qh; | ||
1211 | |||
1212 | done_map = isp1760_readl(usb_hcd->regs + | ||
1213 | HC_INT_PTD_DONEMAP_REG); | ||
1214 | skip_map = isp1760_readl(usb_hcd->regs + | ||
1215 | HC_INT_PTD_SKIPMAP_REG); | ||
1216 | 1004 | ||
1217 | or_map = isp1760_readl(usb_hcd->regs + HC_INT_IRQ_MASK_OR_REG); | 1005 | priv = hcd_to_priv(hcd); |
1218 | or_map &= ~done_map; | ||
1219 | isp1760_writel(or_map, usb_hcd->regs + HC_INT_IRQ_MASK_OR_REG); | ||
1220 | 1006 | ||
1221 | int_regs_base = INT_REGS_OFFSET; | 1007 | /* |
1008 | * check finished/retired xfers, transfer payloads, call urb_done() | ||
1009 | */ | ||
1010 | ep_queue = &priv->interruptqhs; | ||
1011 | while (ep_queue) { | ||
1012 | list_for_each_entry_safe(qh, qh_next, ep_queue, qh_list) { | ||
1013 | ep = list_entry(qh->qtd_list.next, struct isp1760_qtd, | ||
1014 | qtd_list)->urb->ep; | ||
1015 | collect_qtds(hcd, qh, &urb_list); | ||
1016 | if (list_empty(&qh->qtd_list)) { | ||
1017 | list_del(&qh->qh_list); | ||
1018 | if (ep->hcpriv == NULL) { | ||
1019 | /* Endpoint has been disabled, so we | ||
1020 | can free the associated queue head. */ | ||
1021 | qh_free(qh); | ||
1022 | } | ||
1023 | } | ||
1024 | } | ||
1222 | 1025 | ||
1223 | while (done_map) { | 1026 | if (ep_queue == &priv->interruptqhs) |
1224 | u32 dw1; | 1027 | ep_queue = &priv->controlqhs; |
1225 | u32 dw3; | 1028 | else if (ep_queue == &priv->controlqhs) |
1029 | ep_queue = &priv->bulkqhs; | ||
1030 | else | ||
1031 | ep_queue = NULL; | ||
1032 | } | ||
1226 | 1033 | ||
1227 | queue_entry = __ffs(done_map); | 1034 | list_for_each_entry_safe(urb_listitem, urb_listitem_next, &urb_list, |
1228 | done_map &= ~(1 << queue_entry); | 1035 | urb_list) { |
1229 | skip_map |= 1 << queue_entry; | 1036 | isp1760_urb_done(hcd, urb_listitem->urb); |
1037 | kmem_cache_free(urb_listitem_cachep, urb_listitem); | ||
1038 | } | ||
1230 | 1039 | ||
1231 | int_regs = int_regs_base + queue_entry * sizeof(struct ptd); | 1040 | /* |
1232 | urb = priv->int_ints[queue_entry].urb; | 1041 | * Schedule packets for transfer. |
1233 | qtd = priv->int_ints[queue_entry].qtd; | 1042 | * |
1234 | qh = priv->int_ints[queue_entry].qh; | 1043 | * According to USB2.0 specification: |
1235 | payload = priv->int_ints[queue_entry].payload; | 1044 | * |
1045 | * 1st prio: interrupt xfers, up to 80 % of bandwidth | ||
1046 | * 2nd prio: control xfers | ||
1047 | * 3rd prio: bulk xfers | ||
1048 | * | ||
1049 | * ... but let's use a simpler scheme here (mostly because ISP1761 doc | ||
1050 | * is very unclear on how to prioritize traffic): | ||
1051 | * | ||
1052 | * 1) Enqueue any queued control transfers, as long as payload chip mem | ||
1053 | * and PTD ATL slots are available. | ||
1054 | * 2) Enqueue any queued INT transfers, as long as payload chip mem | ||
1055 | * and PTD INT slots are available. | ||
1056 | * 3) Enqueue any queued bulk transfers, as long as payload chip mem | ||
1057 | * and PTD ATL slots are available. | ||
1058 | * | ||
1059 | * Use double buffering (ENQUEUE_DEPTH==2) as a compromise between | ||
1060 | * conservation of chip mem and performance. | ||
1061 | * | ||
1062 | * I'm sure this scheme could be improved upon! | ||
1063 | */ | ||
1064 | ep_queue = &priv->controlqhs; | ||
1065 | while (ep_queue) { | ||
1066 | list_for_each_entry_safe(qh, qh_next, ep_queue, qh_list) | ||
1067 | enqueue_qtds(hcd, qh); | ||
1068 | |||
1069 | if (ep_queue == &priv->controlqhs) | ||
1070 | ep_queue = &priv->interruptqhs; | ||
1071 | else if (ep_queue == &priv->interruptqhs) | ||
1072 | ep_queue = &priv->bulkqhs; | ||
1073 | else | ||
1074 | ep_queue = NULL; | ||
1075 | } | ||
1076 | } | ||
1236 | 1077 | ||
1237 | if (!qh) { | 1078 | #define PTD_STATE_QTD_DONE 1 |
1238 | printk(KERN_ERR "(INT) qh is 0\n"); | 1079 | #define PTD_STATE_QTD_RELOAD 2 |
1239 | continue; | 1080 | #define PTD_STATE_URB_RETIRE 3 |
1240 | } | ||
1241 | 1081 | ||
1242 | isp1760_writel(int_regs + ISP_BANK(0), usb_hcd->regs + | 1082 | static int check_int_transfer(struct usb_hcd *hcd, struct ptd *ptd, |
1243 | HC_MEMORY_REG); | 1083 | struct urb *urb) |
1244 | isp1760_writel(payload + ISP_BANK(1), usb_hcd->regs + | 1084 | { |
1245 | HC_MEMORY_REG); | 1085 | __dw dw4; |
1246 | /* | 1086 | int i; |
1247 | * write bank1 address twice to ensure the 90ns delay (time | ||
1248 | * between BANK0 write and the priv_read_copy() call is at | ||
1249 | * least 3*t_WHWL + 2*t_w11 = 3*25ns + 2*17ns = 92ns) | ||
1250 | */ | ||
1251 | isp1760_writel(payload + ISP_BANK(1), usb_hcd->regs + | ||
1252 | HC_MEMORY_REG); | ||
1253 | |||
1254 | priv_read_copy(priv, (u32 *)&ptd, usb_hcd->regs + int_regs + | ||
1255 | ISP_BANK(0), sizeof(ptd)); | ||
1256 | dw1 = le32_to_cpu(ptd.dw1); | ||
1257 | dw3 = le32_to_cpu(ptd.dw3); | ||
1258 | check_int_err_status(le32_to_cpu(ptd.dw4)); | ||
1259 | |||
1260 | error = check_error(&ptd); | ||
1261 | if (error) { | ||
1262 | #if 0 | ||
1263 | printk(KERN_ERR "Error in %s().\n", __func__); | ||
1264 | printk(KERN_ERR "IN dw0: %08x dw1: %08x dw2: %08x " | ||
1265 | "dw3: %08x dw4: %08x dw5: %08x dw6: " | ||
1266 | "%08x dw7: %08x\n", | ||
1267 | ptd.dw0, ptd.dw1, ptd.dw2, ptd.dw3, | ||
1268 | ptd.dw4, ptd.dw5, ptd.dw6, ptd.dw7); | ||
1269 | #endif | ||
1270 | urb->status = -EPIPE; | ||
1271 | priv->int_ints[queue_entry].qh->toggle = 0; | ||
1272 | priv->int_ints[queue_entry].qh->ping = 0; | ||
1273 | 1087 | ||
1274 | } else { | 1088 | dw4 = ptd->dw4; |
1275 | priv->int_ints[queue_entry].qh->toggle = | 1089 | dw4 >>= 8; |
1276 | dw3 & (1 << 25); | ||
1277 | priv->int_ints[queue_entry].qh->ping = dw3 & (1 << 26); | ||
1278 | } | ||
1279 | 1090 | ||
1280 | if (urb->dev->speed != USB_SPEED_HIGH) | 1091 | /* FIXME: ISP1761 datasheet does not say what to do with these. Do we |
1281 | length = PTD_XFERRED_LENGTH_LO(dw3); | 1092 | need to handle these errors? Is it done in hardware? */ |
1282 | else | ||
1283 | length = PTD_XFERRED_LENGTH(dw3); | ||
1284 | 1093 | ||
1285 | if (length) { | 1094 | if (ptd->dw3 & DW3_HALT_BIT) { |
1286 | switch (DW1_GET_PID(dw1)) { | ||
1287 | case IN_PID: | ||
1288 | priv_read_copy(priv, | ||
1289 | priv->int_ints[queue_entry].data_buffer, | ||
1290 | usb_hcd->regs + payload + ISP_BANK(1), | ||
1291 | length); | ||
1292 | case OUT_PID: | ||
1293 | 1095 | ||
1294 | urb->actual_length += length; | 1096 | urb->status = -EPROTO; /* Default unknown error */ |
1295 | 1097 | ||
1296 | case SETUP_PID: | 1098 | for (i = 0; i < 8; i++) { |
1099 | switch (dw4 & 0x7) { | ||
1100 | case INT_UNDERRUN: | ||
1101 | dev_dbg(hcd->self.controller, "%s: underrun " | ||
1102 | "during uFrame %d\n", | ||
1103 | __func__, i); | ||
1104 | urb->status = -ECOMM; /* Could not write data */ | ||
1105 | break; | ||
1106 | case INT_EXACT: | ||
1107 | dev_dbg(hcd->self.controller, "%s: transaction " | ||
1108 | "error during uFrame %d\n", | ||
1109 | __func__, i); | ||
1110 | urb->status = -EPROTO; /* timeout, bad CRC, PID | ||
1111 | error etc. */ | ||
1112 | break; | ||
1113 | case INT_BABBLE: | ||
1114 | dev_dbg(hcd->self.controller, "%s: babble " | ||
1115 | "error during uFrame %d\n", | ||
1116 | __func__, i); | ||
1117 | urb->status = -EOVERFLOW; | ||
1297 | break; | 1118 | break; |
1298 | } | 1119 | } |
1120 | dw4 >>= 3; | ||
1299 | } | 1121 | } |
1300 | 1122 | ||
1301 | priv->int_ints[queue_entry].data_buffer = NULL; | 1123 | return PTD_STATE_URB_RETIRE; |
1302 | priv->int_ints[queue_entry].urb = NULL; | 1124 | } |
1303 | priv->int_ints[queue_entry].qtd = NULL; | ||
1304 | priv->int_ints[queue_entry].qh = NULL; | ||
1305 | |||
1306 | isp1760_writel(skip_map, usb_hcd->regs + | ||
1307 | HC_INT_PTD_SKIPMAP_REG); | ||
1308 | free_mem(priv, payload); | ||
1309 | |||
1310 | if (urb->status == -EPIPE) { | ||
1311 | /* HALT received */ | ||
1312 | |||
1313 | qtd = clean_up_qtdlist(qtd); | ||
1314 | isp1760_urb_done(priv, urb, urb->status); | ||
1315 | |||
1316 | } else if (qtd->status & URB_COMPLETE_NOTIFY) { | ||
1317 | |||
1318 | if (urb->status == -EINPROGRESS) | ||
1319 | urb->status = 0; | ||
1320 | |||
1321 | qtd = clean_this_qtd(qtd); | ||
1322 | isp1760_urb_done(priv, urb, urb->status); | ||
1323 | 1125 | ||
1324 | } else { | 1126 | return PTD_STATE_QTD_DONE; |
1325 | /* next QTD of this URB */ | 1127 | } |
1326 | 1128 | ||
1327 | qtd = clean_this_qtd(qtd); | 1129 | static int check_atl_transfer(struct usb_hcd *hcd, struct ptd *ptd, |
1328 | BUG_ON(!qtd); | 1130 | struct urb *urb) |
1329 | } | 1131 | { |
1132 | WARN_ON(!ptd); | ||
1133 | if (ptd->dw3 & DW3_HALT_BIT) { | ||
1134 | if (ptd->dw3 & DW3_BABBLE_BIT) | ||
1135 | urb->status = -EOVERFLOW; | ||
1136 | else if (FROM_DW3_CERR(ptd->dw3)) | ||
1137 | urb->status = -EPIPE; /* Stall */ | ||
1138 | else if (ptd->dw3 & DW3_ERROR_BIT) | ||
1139 | urb->status = -EPROTO; /* XactErr */ | ||
1140 | else | ||
1141 | urb->status = -EPROTO; /* Unknown */ | ||
1142 | /* | ||
1143 | dev_dbg(hcd->self.controller, "%s: ptd error:\n" | ||
1144 | " dw0: %08x dw1: %08x dw2: %08x dw3: %08x\n" | ||
1145 | " dw4: %08x dw5: %08x dw6: %08x dw7: %08x\n", | ||
1146 | __func__, | ||
1147 | ptd->dw0, ptd->dw1, ptd->dw2, ptd->dw3, | ||
1148 | ptd->dw4, ptd->dw5, ptd->dw6, ptd->dw7); | ||
1149 | */ | ||
1150 | return PTD_STATE_URB_RETIRE; | ||
1151 | } | ||
1330 | 1152 | ||
1331 | if (qtd) | 1153 | if ((ptd->dw3 & DW3_ERROR_BIT) && (ptd->dw3 & DW3_ACTIVE_BIT)) { |
1332 | enqueue_an_INT_packet(usb_hcd, qh, qtd); | 1154 | /* Transfer Error, *but* active and no HALT -> reload */ |
1155 | dev_dbg(hcd->self.controller, "PID error; reloading ptd\n"); | ||
1156 | return PTD_STATE_QTD_RELOAD; | ||
1157 | } | ||
1333 | 1158 | ||
1334 | skip_map = isp1760_readl(usb_hcd->regs + | 1159 | if (!FROM_DW3_NAKCOUNT(ptd->dw3) && (ptd->dw3 & DW3_ACTIVE_BIT)) { |
1335 | HC_INT_PTD_SKIPMAP_REG); | 1160 | /* |
1161 | * NAKs are handled in HW by the chip. Usually if the | ||
1162 | * device is not able to send data fast enough. | ||
1163 | * This happens mostly on slower hardware. | ||
1164 | */ | ||
1165 | return PTD_STATE_QTD_RELOAD; | ||
1336 | } | 1166 | } |
1167 | |||
1168 | return PTD_STATE_QTD_DONE; | ||
1337 | } | 1169 | } |
1338 | 1170 | ||
1339 | #define max_packet(wMaxPacketSize) ((wMaxPacketSize) & 0x07ff) | 1171 | static irqreturn_t isp1760_irq(struct usb_hcd *hcd) |
1340 | static struct isp1760_qh *qh_make(struct isp1760_hcd *priv, struct urb *urb, | ||
1341 | gfp_t flags) | ||
1342 | { | 1172 | { |
1173 | struct isp1760_hcd *priv = hcd_to_priv(hcd); | ||
1174 | u32 imask; | ||
1175 | irqreturn_t irqret = IRQ_NONE; | ||
1176 | struct ptd ptd; | ||
1343 | struct isp1760_qh *qh; | 1177 | struct isp1760_qh *qh; |
1344 | int is_input, type; | 1178 | int slot; |
1345 | 1179 | int state; | |
1346 | qh = isp1760_qh_alloc(priv, flags); | 1180 | struct slotinfo *slots; |
1347 | if (!qh) | 1181 | u32 ptd_offset; |
1348 | return qh; | 1182 | struct isp1760_qtd *qtd; |
1349 | 1183 | int modified; | |
1350 | /* | 1184 | static int last_active_ptds; |
1351 | * init endpoint/device data for this QH | 1185 | int int_skip_map, atl_skip_map; |
1352 | */ | ||
1353 | is_input = usb_pipein(urb->pipe); | ||
1354 | type = usb_pipetype(urb->pipe); | ||
1355 | 1186 | ||
1356 | if (type == PIPE_INTERRUPT) { | 1187 | spin_lock(&priv->lock); |
1357 | 1188 | ||
1358 | if (urb->dev->speed == USB_SPEED_HIGH) { | 1189 | if (!(hcd->state & HC_STATE_RUNNING)) |
1190 | goto leave; | ||
1359 | 1191 | ||
1360 | qh->period = urb->interval >> 3; | 1192 | imask = reg_read32(hcd->regs, HC_INTERRUPT_REG); |
1361 | if (qh->period == 0 && urb->interval != 1) { | 1193 | if (unlikely(!imask)) |
1362 | /* NOTE interval 2 or 4 uframes could work. | 1194 | goto leave; |
1363 | * But interval 1 scheduling is simpler, and | 1195 | reg_write32(hcd->regs, HC_INTERRUPT_REG, imask); /* Clear */ |
1364 | * includes high bandwidth. | 1196 | |
1365 | */ | 1197 | int_skip_map = reg_read32(hcd->regs, HC_INT_PTD_SKIPMAP_REG); |
1366 | printk(KERN_ERR "intr period %d uframes, NYET!", | 1198 | atl_skip_map = reg_read32(hcd->regs, HC_ATL_PTD_SKIPMAP_REG); |
1367 | urb->interval); | 1199 | priv->int_done_map |= reg_read32(hcd->regs, HC_INT_PTD_DONEMAP_REG); |
1368 | qh_destroy(qh); | 1200 | priv->atl_done_map |= reg_read32(hcd->regs, HC_ATL_PTD_DONEMAP_REG); |
1369 | return NULL; | 1201 | priv->int_done_map &= ~int_skip_map; |
1202 | priv->atl_done_map &= ~atl_skip_map; | ||
1203 | |||
1204 | modified = priv->int_done_map | priv->atl_done_map; | ||
1205 | |||
1206 | while (priv->int_done_map || priv->atl_done_map) { | ||
1207 | if (priv->int_done_map) { | ||
1208 | /* INT ptd */ | ||
1209 | slot = __ffs(priv->int_done_map); | ||
1210 | priv->int_done_map &= ~(1 << slot); | ||
1211 | slots = priv->int_slots; | ||
1212 | /* This should not trigger, and could be removed if | ||
1213 | noone have any problems with it triggering: */ | ||
1214 | if (!slots[slot].qh) { | ||
1215 | WARN_ON(1); | ||
1216 | continue; | ||
1370 | } | 1217 | } |
1218 | ptd_offset = INT_PTD_OFFSET; | ||
1219 | ptd_read(hcd->regs, INT_PTD_OFFSET, slot, &ptd); | ||
1220 | state = check_int_transfer(hcd, &ptd, | ||
1221 | slots[slot].qtd->urb); | ||
1371 | } else { | 1222 | } else { |
1372 | qh->period = urb->interval; | 1223 | /* ATL ptd */ |
1224 | slot = __ffs(priv->atl_done_map); | ||
1225 | priv->atl_done_map &= ~(1 << slot); | ||
1226 | slots = priv->atl_slots; | ||
1227 | /* This should not trigger, and could be removed if | ||
1228 | noone have any problems with it triggering: */ | ||
1229 | if (!slots[slot].qh) { | ||
1230 | WARN_ON(1); | ||
1231 | continue; | ||
1232 | } | ||
1233 | ptd_offset = ATL_PTD_OFFSET; | ||
1234 | ptd_read(hcd->regs, ATL_PTD_OFFSET, slot, &ptd); | ||
1235 | state = check_atl_transfer(hcd, &ptd, | ||
1236 | slots[slot].qtd->urb); | ||
1373 | } | 1237 | } |
1374 | } | ||
1375 | 1238 | ||
1376 | /* support for tt scheduling, and access to toggles */ | 1239 | qtd = slots[slot].qtd; |
1377 | qh->dev = urb->dev; | 1240 | slots[slot].qtd = NULL; |
1241 | qh = slots[slot].qh; | ||
1242 | slots[slot].qh = NULL; | ||
1243 | priv->active_ptds--; | ||
1244 | qh->slot = -1; | ||
1245 | |||
1246 | WARN_ON(qtd->status != QTD_XFER_STARTED); | ||
1247 | |||
1248 | switch (state) { | ||
1249 | case PTD_STATE_QTD_DONE: | ||
1250 | if ((usb_pipeint(qtd->urb->pipe)) && | ||
1251 | (qtd->urb->dev->speed != USB_SPEED_HIGH)) | ||
1252 | qtd->actual_length = | ||
1253 | FROM_DW3_SCS_NRBYTESTRANSFERRED(ptd.dw3); | ||
1254 | else | ||
1255 | qtd->actual_length = | ||
1256 | FROM_DW3_NRBYTESTRANSFERRED(ptd.dw3); | ||
1257 | |||
1258 | qtd->status = QTD_XFER_COMPLETE; | ||
1259 | if (list_is_last(&qtd->qtd_list, &qh->qtd_list) || | ||
1260 | is_short_bulk(qtd)) | ||
1261 | qtd = NULL; | ||
1262 | else | ||
1263 | qtd = list_entry(qtd->qtd_list.next, | ||
1264 | typeof(*qtd), qtd_list); | ||
1265 | |||
1266 | qh->toggle = FROM_DW3_DATA_TOGGLE(ptd.dw3); | ||
1267 | qh->ping = FROM_DW3_PING(ptd.dw3); | ||
1268 | break; | ||
1378 | 1269 | ||
1379 | if (!usb_pipecontrol(urb->pipe)) | 1270 | case PTD_STATE_QTD_RELOAD: /* QTD_RETRY, for atls only */ |
1380 | usb_settoggle(urb->dev, usb_pipeendpoint(urb->pipe), !is_input, | 1271 | qtd->status = QTD_PAYLOAD_ALLOC; |
1381 | 1); | 1272 | ptd.dw0 |= DW0_VALID_BIT; |
1382 | return qh; | 1273 | /* RL counter = ERR counter */ |
1383 | } | 1274 | ptd.dw3 &= ~TO_DW3_NAKCOUNT(0xf); |
1275 | ptd.dw3 |= TO_DW3_NAKCOUNT(FROM_DW2_RL(ptd.dw2)); | ||
1276 | ptd.dw3 &= ~TO_DW3_CERR(3); | ||
1277 | ptd.dw3 |= TO_DW3_CERR(ERR_COUNTER); | ||
1278 | qh->toggle = FROM_DW3_DATA_TOGGLE(ptd.dw3); | ||
1279 | qh->ping = FROM_DW3_PING(ptd.dw3); | ||
1280 | break; | ||
1384 | 1281 | ||
1385 | /* | 1282 | case PTD_STATE_URB_RETIRE: |
1386 | * For control/bulk/interrupt, return QH with these TDs appended. | 1283 | qtd->status = QTD_RETIRE; |
1387 | * Allocates and initializes the QH if necessary. | 1284 | qtd = NULL; |
1388 | * Returns null if it can't allocate a QH it needs to. | 1285 | qh->toggle = 0; |
1389 | * If the QH has TDs (urbs) already, that's great. | 1286 | qh->ping = 0; |
1390 | */ | 1287 | break; |
1391 | static struct isp1760_qh *qh_append_tds(struct isp1760_hcd *priv, | ||
1392 | struct urb *urb, struct list_head *qtd_list, int epnum, | ||
1393 | void **ptr) | ||
1394 | { | ||
1395 | struct isp1760_qh *qh; | ||
1396 | struct isp1760_qtd *qtd; | ||
1397 | struct isp1760_qtd *prev_qtd; | ||
1398 | 1288 | ||
1399 | qh = (struct isp1760_qh *)*ptr; | 1289 | default: |
1400 | if (!qh) { | 1290 | WARN_ON(1); |
1401 | /* can't sleep here, we have priv->lock... */ | 1291 | continue; |
1402 | qh = qh_make(priv, urb, GFP_ATOMIC); | 1292 | } |
1403 | if (!qh) | ||
1404 | return qh; | ||
1405 | *ptr = qh; | ||
1406 | } | ||
1407 | 1293 | ||
1408 | qtd = list_entry(qtd_list->next, struct isp1760_qtd, | 1294 | if (qtd && (qtd->status == QTD_PAYLOAD_ALLOC)) { |
1409 | qtd_list); | 1295 | if (slots == priv->int_slots) { |
1410 | if (!list_empty(&qh->qtd_list)) | 1296 | if (state == PTD_STATE_QTD_RELOAD) |
1411 | prev_qtd = list_entry(qh->qtd_list.prev, | 1297 | dev_err(hcd->self.controller, |
1412 | struct isp1760_qtd, qtd_list); | 1298 | "%s: PTD_STATE_QTD_RELOAD on " |
1413 | else | 1299 | "interrupt packet\n", __func__); |
1414 | prev_qtd = NULL; | 1300 | if (state != PTD_STATE_QTD_RELOAD) |
1301 | create_ptd_int(qh, qtd, &ptd); | ||
1302 | } else { | ||
1303 | if (state != PTD_STATE_QTD_RELOAD) | ||
1304 | create_ptd_atl(qh, qtd, &ptd); | ||
1305 | } | ||
1415 | 1306 | ||
1416 | list_splice(qtd_list, qh->qtd_list.prev); | 1307 | start_bus_transfer(hcd, ptd_offset, slot, slots, qtd, |
1417 | if (prev_qtd) { | 1308 | qh, &ptd); |
1418 | BUG_ON(prev_qtd->hw_next); | 1309 | } |
1419 | prev_qtd->hw_next = qtd; | ||
1420 | } | 1310 | } |
1421 | 1311 | ||
1422 | urb->hcpriv = qh; | 1312 | if (modified) |
1423 | return qh; | 1313 | schedule_ptds(hcd); |
1424 | } | ||
1425 | |||
1426 | static void qtd_list_free(struct isp1760_hcd *priv, struct urb *urb, | ||
1427 | struct list_head *qtd_list) | ||
1428 | { | ||
1429 | struct list_head *entry, *temp; | ||
1430 | 1314 | ||
1431 | list_for_each_safe(entry, temp, qtd_list) { | 1315 | /* ISP1760 Errata 2 explains that interrupts may be missed (or not |
1432 | struct isp1760_qtd *qtd; | 1316 | happen?) if two USB devices are running simultaneously. Perhaps |
1317 | this happens when a PTD is finished during interrupt handling; | ||
1318 | enable SOF interrupts if PTDs are still scheduled when exiting this | ||
1319 | interrupt handler, just to be safe. */ | ||
1433 | 1320 | ||
1434 | qtd = list_entry(entry, struct isp1760_qtd, qtd_list); | 1321 | if (priv->active_ptds != last_active_ptds) { |
1435 | list_del(&qtd->qtd_list); | 1322 | if (priv->active_ptds > 0) |
1436 | isp1760_qtd_free(qtd); | 1323 | reg_write32(hcd->regs, HC_INTERRUPT_ENABLE, |
1324 | INTERRUPT_ENABLE_SOT_MASK); | ||
1325 | else | ||
1326 | reg_write32(hcd->regs, HC_INTERRUPT_ENABLE, | ||
1327 | INTERRUPT_ENABLE_MASK); | ||
1328 | last_active_ptds = priv->active_ptds; | ||
1437 | } | 1329 | } |
1438 | } | ||
1439 | |||
1440 | static int isp1760_prepare_enqueue(struct isp1760_hcd *priv, struct urb *urb, | ||
1441 | struct list_head *qtd_list, gfp_t mem_flags, packet_enqueue *p) | ||
1442 | { | ||
1443 | struct isp1760_qtd *qtd; | ||
1444 | int epnum; | ||
1445 | unsigned long flags; | ||
1446 | struct isp1760_qh *qh = NULL; | ||
1447 | int rc; | ||
1448 | int qh_busy; | ||
1449 | |||
1450 | qtd = list_entry(qtd_list->next, struct isp1760_qtd, qtd_list); | ||
1451 | epnum = urb->ep->desc.bEndpointAddress; | ||
1452 | 1330 | ||
1453 | spin_lock_irqsave(&priv->lock, flags); | 1331 | irqret = IRQ_HANDLED; |
1454 | if (!HCD_HW_ACCESSIBLE(priv_to_hcd(priv))) { | 1332 | leave: |
1455 | rc = -ESHUTDOWN; | 1333 | spin_unlock(&priv->lock); |
1456 | goto done; | ||
1457 | } | ||
1458 | rc = usb_hcd_link_urb_to_ep(priv_to_hcd(priv), urb); | ||
1459 | if (rc) | ||
1460 | goto done; | ||
1461 | 1334 | ||
1462 | qh = urb->ep->hcpriv; | 1335 | return irqret; |
1463 | if (qh) | 1336 | } |
1464 | qh_busy = !list_empty(&qh->qtd_list); | ||
1465 | else | ||
1466 | qh_busy = 0; | ||
1467 | 1337 | ||
1468 | qh = qh_append_tds(priv, urb, qtd_list, epnum, &urb->ep->hcpriv); | 1338 | static int qtd_fill(struct isp1760_qtd *qtd, void *databuffer, size_t len) |
1469 | if (!qh) { | 1339 | { |
1470 | usb_hcd_unlink_urb_from_ep(priv_to_hcd(priv), urb); | 1340 | qtd->data_buffer = databuffer; |
1471 | rc = -ENOMEM; | ||
1472 | goto done; | ||
1473 | } | ||
1474 | 1341 | ||
1475 | if (!qh_busy) | 1342 | if (len > MAX_PAYLOAD_SIZE) |
1476 | p(priv_to_hcd(priv), qh, qtd); | 1343 | len = MAX_PAYLOAD_SIZE; |
1344 | qtd->length = len; | ||
1477 | 1345 | ||
1478 | done: | 1346 | return qtd->length; |
1479 | spin_unlock_irqrestore(&priv->lock, flags); | ||
1480 | if (!qh) | ||
1481 | qtd_list_free(priv, urb, qtd_list); | ||
1482 | return rc; | ||
1483 | } | 1347 | } |
1484 | 1348 | ||
1485 | static struct isp1760_qtd *isp1760_qtd_alloc(struct isp1760_hcd *priv, | 1349 | static void qtd_list_free(struct list_head *qtd_list) |
1486 | gfp_t flags) | ||
1487 | { | 1350 | { |
1488 | struct isp1760_qtd *qtd; | 1351 | struct isp1760_qtd *qtd, *qtd_next; |
1489 | 1352 | ||
1490 | qtd = kmem_cache_zalloc(qtd_cachep, flags); | 1353 | list_for_each_entry_safe(qtd, qtd_next, qtd_list, qtd_list) { |
1491 | if (qtd) | 1354 | list_del(&qtd->qtd_list); |
1492 | INIT_LIST_HEAD(&qtd->qtd_list); | 1355 | qtd_free(qtd); |
1493 | 1356 | } | |
1494 | return qtd; | ||
1495 | } | 1357 | } |
1496 | 1358 | ||
1497 | /* | 1359 | /* |
1498 | * create a list of filled qtds for this URB; won't link into qh. | 1360 | * Packetize urb->transfer_buffer into list of packets of size wMaxPacketSize. |
1361 | * Also calculate the PID type (SETUP/IN/OUT) for each packet. | ||
1499 | */ | 1362 | */ |
1500 | static struct list_head *qh_urb_transaction(struct isp1760_hcd *priv, | 1363 | #define max_packet(wMaxPacketSize) ((wMaxPacketSize) & 0x07ff) |
1364 | static void packetize_urb(struct usb_hcd *hcd, | ||
1501 | struct urb *urb, struct list_head *head, gfp_t flags) | 1365 | struct urb *urb, struct list_head *head, gfp_t flags) |
1502 | { | 1366 | { |
1503 | struct isp1760_qtd *qtd, *qtd_prev; | 1367 | struct isp1760_qtd *qtd; |
1504 | void *buf; | 1368 | void *buf; |
1505 | int len, maxpacket; | 1369 | int len, maxpacketsize; |
1506 | int is_input; | 1370 | u8 packet_type; |
1507 | u32 token; | ||
1508 | 1371 | ||
1509 | /* | 1372 | /* |
1510 | * URBs map to sequences of QTDs: one logical transaction | 1373 | * URBs map to sequences of QTDs: one logical transaction |
1511 | */ | 1374 | */ |
1512 | qtd = isp1760_qtd_alloc(priv, flags); | ||
1513 | if (!qtd) | ||
1514 | return NULL; | ||
1515 | 1375 | ||
1516 | list_add_tail(&qtd->qtd_list, head); | 1376 | if (!urb->transfer_buffer && urb->transfer_buffer_length) { |
1517 | qtd->urb = urb; | 1377 | /* XXX This looks like usb storage / SCSI bug */ |
1518 | urb->status = -EINPROGRESS; | 1378 | dev_err(hcd->self.controller, |
1379 | "buf is null, dma is %08lx len is %d\n", | ||
1380 | (long unsigned)urb->transfer_dma, | ||
1381 | urb->transfer_buffer_length); | ||
1382 | WARN_ON(1); | ||
1383 | } | ||
1519 | 1384 | ||
1520 | token = 0; | 1385 | if (usb_pipein(urb->pipe)) |
1521 | /* for split transactions, SplitXState initialized to zero */ | 1386 | packet_type = IN_PID; |
1387 | else | ||
1388 | packet_type = OUT_PID; | ||
1522 | 1389 | ||
1523 | len = urb->transfer_buffer_length; | ||
1524 | is_input = usb_pipein(urb->pipe); | ||
1525 | if (usb_pipecontrol(urb->pipe)) { | 1390 | if (usb_pipecontrol(urb->pipe)) { |
1526 | /* SETUP pid */ | 1391 | qtd = qtd_alloc(flags, urb, SETUP_PID); |
1527 | qtd_fill(qtd, urb->setup_packet, | ||
1528 | sizeof(struct usb_ctrlrequest), | ||
1529 | token | SETUP_PID); | ||
1530 | |||
1531 | /* ... and always at least one more pid */ | ||
1532 | token ^= DATA_TOGGLE; | ||
1533 | qtd_prev = qtd; | ||
1534 | qtd = isp1760_qtd_alloc(priv, flags); | ||
1535 | if (!qtd) | 1392 | if (!qtd) |
1536 | goto cleanup; | 1393 | goto cleanup; |
1537 | qtd->urb = urb; | 1394 | qtd_fill(qtd, urb->setup_packet, sizeof(struct usb_ctrlrequest)); |
1538 | qtd_prev->hw_next = qtd; | ||
1539 | list_add_tail(&qtd->qtd_list, head); | 1395 | list_add_tail(&qtd->qtd_list, head); |
1540 | 1396 | ||
1541 | /* for zero length DATA stages, STATUS is always IN */ | 1397 | /* for zero length DATA stages, STATUS is always IN */ |
1542 | if (len == 0) | 1398 | if (urb->transfer_buffer_length == 0) |
1543 | token |= IN_PID; | 1399 | packet_type = IN_PID; |
1544 | } | 1400 | } |
1545 | 1401 | ||
1546 | /* | 1402 | maxpacketsize = max_packet(usb_maxpacket(urb->dev, urb->pipe, |
1547 | * data transfer stage: buffer setup | 1403 | usb_pipeout(urb->pipe))); |
1548 | */ | ||
1549 | buf = urb->transfer_buffer; | ||
1550 | |||
1551 | if (is_input) | ||
1552 | token |= IN_PID; | ||
1553 | else | ||
1554 | token |= OUT_PID; | ||
1555 | |||
1556 | maxpacket = max_packet(usb_maxpacket(urb->dev, urb->pipe, !is_input)); | ||
1557 | 1404 | ||
1558 | /* | 1405 | /* |
1559 | * buffer gets wrapped in one or more qtds; | 1406 | * buffer gets wrapped in one or more qtds; |
1560 | * last one may be "short" (including zero len) | 1407 | * last one may be "short" (including zero len) |
1561 | * and may serve as a control status ack | 1408 | * and may serve as a control status ack |
1562 | */ | 1409 | */ |
1410 | buf = urb->transfer_buffer; | ||
1411 | len = urb->transfer_buffer_length; | ||
1412 | |||
1563 | for (;;) { | 1413 | for (;;) { |
1564 | int this_qtd_len; | 1414 | int this_qtd_len; |
1565 | 1415 | ||
1566 | if (!buf && len) { | 1416 | qtd = qtd_alloc(flags, urb, packet_type); |
1567 | /* XXX This looks like usb storage / SCSI bug */ | 1417 | if (!qtd) |
1568 | printk(KERN_ERR "buf is null, dma is %08lx len is %d\n", | 1418 | goto cleanup; |
1569 | (long unsigned)urb->transfer_dma, len); | 1419 | this_qtd_len = qtd_fill(qtd, buf, len); |
1570 | WARN_ON(1); | 1420 | list_add_tail(&qtd->qtd_list, head); |
1571 | } | ||
1572 | 1421 | ||
1573 | this_qtd_len = qtd_fill(qtd, buf, len, token); | ||
1574 | len -= this_qtd_len; | 1422 | len -= this_qtd_len; |
1575 | buf += this_qtd_len; | 1423 | buf += this_qtd_len; |
1576 | 1424 | ||
1577 | /* qh makes control packets use qtd toggle; maybe switch it */ | ||
1578 | if ((maxpacket & (this_qtd_len + (maxpacket - 1))) == 0) | ||
1579 | token ^= DATA_TOGGLE; | ||
1580 | |||
1581 | if (len <= 0) | 1425 | if (len <= 0) |
1582 | break; | 1426 | break; |
1583 | |||
1584 | qtd_prev = qtd; | ||
1585 | qtd = isp1760_qtd_alloc(priv, flags); | ||
1586 | if (!qtd) | ||
1587 | goto cleanup; | ||
1588 | qtd->urb = urb; | ||
1589 | qtd_prev->hw_next = qtd; | ||
1590 | list_add_tail(&qtd->qtd_list, head); | ||
1591 | } | 1427 | } |
1592 | 1428 | ||
1593 | /* | 1429 | /* |
@@ -1599,187 +1435,204 @@ static struct list_head *qh_urb_transaction(struct isp1760_hcd *priv, | |||
1599 | 1435 | ||
1600 | if (usb_pipecontrol(urb->pipe)) { | 1436 | if (usb_pipecontrol(urb->pipe)) { |
1601 | one_more = 1; | 1437 | one_more = 1; |
1602 | /* "in" <--> "out" */ | 1438 | if (packet_type == IN_PID) |
1603 | token ^= IN_PID; | 1439 | packet_type = OUT_PID; |
1604 | /* force DATA1 */ | 1440 | else |
1605 | token |= DATA_TOGGLE; | 1441 | packet_type = IN_PID; |
1606 | } else if (usb_pipebulk(urb->pipe) | 1442 | } else if (usb_pipebulk(urb->pipe) |
1607 | && (urb->transfer_flags & URB_ZERO_PACKET) | 1443 | && (urb->transfer_flags & URB_ZERO_PACKET) |
1608 | && !(urb->transfer_buffer_length % maxpacket)) { | 1444 | && !(urb->transfer_buffer_length % |
1445 | maxpacketsize)) { | ||
1609 | one_more = 1; | 1446 | one_more = 1; |
1610 | } | 1447 | } |
1611 | if (one_more) { | 1448 | if (one_more) { |
1612 | qtd_prev = qtd; | 1449 | qtd = qtd_alloc(flags, urb, packet_type); |
1613 | qtd = isp1760_qtd_alloc(priv, flags); | ||
1614 | if (!qtd) | 1450 | if (!qtd) |
1615 | goto cleanup; | 1451 | goto cleanup; |
1616 | qtd->urb = urb; | ||
1617 | qtd_prev->hw_next = qtd; | ||
1618 | list_add_tail(&qtd->qtd_list, head); | ||
1619 | 1452 | ||
1620 | /* never any data in such packets */ | 1453 | /* never any data in such packets */ |
1621 | qtd_fill(qtd, NULL, 0, token); | 1454 | qtd_fill(qtd, NULL, 0); |
1455 | list_add_tail(&qtd->qtd_list, head); | ||
1622 | } | 1456 | } |
1623 | } | 1457 | } |
1624 | 1458 | ||
1625 | qtd->status = URB_COMPLETE_NOTIFY; | 1459 | return; |
1626 | return head; | ||
1627 | 1460 | ||
1628 | cleanup: | 1461 | cleanup: |
1629 | qtd_list_free(priv, urb, head); | 1462 | qtd_list_free(head); |
1630 | return NULL; | ||
1631 | } | 1463 | } |
1632 | 1464 | ||
1633 | static int isp1760_urb_enqueue(struct usb_hcd *hcd, struct urb *urb, | 1465 | static int isp1760_urb_enqueue(struct usb_hcd *hcd, struct urb *urb, |
1634 | gfp_t mem_flags) | 1466 | gfp_t mem_flags) |
1635 | { | 1467 | { |
1636 | struct isp1760_hcd *priv = hcd_to_priv(hcd); | 1468 | struct isp1760_hcd *priv = hcd_to_priv(hcd); |
1637 | struct list_head qtd_list; | 1469 | struct list_head *ep_queue; |
1638 | packet_enqueue *pe; | 1470 | struct isp1760_qh *qh, *qhit; |
1639 | 1471 | unsigned long spinflags; | |
1640 | INIT_LIST_HEAD(&qtd_list); | 1472 | LIST_HEAD(new_qtds); |
1473 | int retval; | ||
1474 | int qh_in_queue; | ||
1641 | 1475 | ||
1642 | switch (usb_pipetype(urb->pipe)) { | 1476 | switch (usb_pipetype(urb->pipe)) { |
1643 | case PIPE_CONTROL: | 1477 | case PIPE_CONTROL: |
1478 | ep_queue = &priv->controlqhs; | ||
1479 | break; | ||
1644 | case PIPE_BULK: | 1480 | case PIPE_BULK: |
1645 | 1481 | ep_queue = &priv->bulkqhs; | |
1646 | if (!qh_urb_transaction(priv, urb, &qtd_list, mem_flags)) | ||
1647 | return -ENOMEM; | ||
1648 | pe = enqueue_an_ATL_packet; | ||
1649 | break; | 1482 | break; |
1650 | |||
1651 | case PIPE_INTERRUPT: | 1483 | case PIPE_INTERRUPT: |
1652 | if (!qh_urb_transaction(priv, urb, &qtd_list, mem_flags)) | 1484 | if (urb->interval < 0) |
1653 | return -ENOMEM; | 1485 | return -EINVAL; |
1654 | pe = enqueue_an_INT_packet; | 1486 | /* FIXME: Check bandwidth */ |
1487 | ep_queue = &priv->interruptqhs; | ||
1655 | break; | 1488 | break; |
1656 | |||
1657 | case PIPE_ISOCHRONOUS: | 1489 | case PIPE_ISOCHRONOUS: |
1658 | printk(KERN_ERR "PIPE_ISOCHRONOUS ain't supported\n"); | 1490 | dev_err(hcd->self.controller, "%s: isochronous USB packets " |
1491 | "not yet supported\n", | ||
1492 | __func__); | ||
1493 | return -EPIPE; | ||
1659 | default: | 1494 | default: |
1495 | dev_err(hcd->self.controller, "%s: unknown pipe type\n", | ||
1496 | __func__); | ||
1660 | return -EPIPE; | 1497 | return -EPIPE; |
1661 | } | 1498 | } |
1662 | 1499 | ||
1663 | return isp1760_prepare_enqueue(priv, urb, &qtd_list, mem_flags, pe); | 1500 | if (usb_pipein(urb->pipe)) |
1501 | urb->actual_length = 0; | ||
1502 | |||
1503 | packetize_urb(hcd, urb, &new_qtds, mem_flags); | ||
1504 | if (list_empty(&new_qtds)) | ||
1505 | return -ENOMEM; | ||
1506 | urb->hcpriv = NULL; /* Used to signal unlink to interrupt handler */ | ||
1507 | |||
1508 | retval = 0; | ||
1509 | spin_lock_irqsave(&priv->lock, spinflags); | ||
1510 | |||
1511 | if (!test_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags)) { | ||
1512 | retval = -ESHUTDOWN; | ||
1513 | goto out; | ||
1514 | } | ||
1515 | retval = usb_hcd_link_urb_to_ep(hcd, urb); | ||
1516 | if (retval) | ||
1517 | goto out; | ||
1518 | |||
1519 | qh = urb->ep->hcpriv; | ||
1520 | if (qh) { | ||
1521 | qh_in_queue = 0; | ||
1522 | list_for_each_entry(qhit, ep_queue, qh_list) { | ||
1523 | if (qhit == qh) { | ||
1524 | qh_in_queue = 1; | ||
1525 | break; | ||
1526 | } | ||
1527 | } | ||
1528 | if (!qh_in_queue) | ||
1529 | list_add_tail(&qh->qh_list, ep_queue); | ||
1530 | } else { | ||
1531 | qh = qh_alloc(GFP_ATOMIC); | ||
1532 | if (!qh) { | ||
1533 | retval = -ENOMEM; | ||
1534 | goto out; | ||
1535 | } | ||
1536 | list_add_tail(&qh->qh_list, ep_queue); | ||
1537 | urb->ep->hcpriv = qh; | ||
1538 | } | ||
1539 | |||
1540 | list_splice_tail(&new_qtds, &qh->qtd_list); | ||
1541 | schedule_ptds(hcd); | ||
1542 | |||
1543 | out: | ||
1544 | spin_unlock_irqrestore(&priv->lock, spinflags); | ||
1545 | return retval; | ||
1546 | } | ||
1547 | |||
1548 | static void kill_transfer(struct usb_hcd *hcd, struct urb *urb, | ||
1549 | struct isp1760_qh *qh) | ||
1550 | { | ||
1551 | struct isp1760_hcd *priv = hcd_to_priv(hcd); | ||
1552 | int skip_map; | ||
1553 | |||
1554 | WARN_ON(qh->slot == -1); | ||
1555 | |||
1556 | /* We need to forcefully reclaim the slot since some transfers never | ||
1557 | return, e.g. interrupt transfers and NAKed bulk transfers. */ | ||
1558 | if (usb_pipecontrol(urb->pipe) || usb_pipebulk(urb->pipe)) { | ||
1559 | skip_map = reg_read32(hcd->regs, HC_ATL_PTD_SKIPMAP_REG); | ||
1560 | skip_map |= (1 << qh->slot); | ||
1561 | reg_write32(hcd->regs, HC_ATL_PTD_SKIPMAP_REG, skip_map); | ||
1562 | priv->atl_slots[qh->slot].qh = NULL; | ||
1563 | priv->atl_slots[qh->slot].qtd = NULL; | ||
1564 | } else { | ||
1565 | skip_map = reg_read32(hcd->regs, HC_INT_PTD_SKIPMAP_REG); | ||
1566 | skip_map |= (1 << qh->slot); | ||
1567 | reg_write32(hcd->regs, HC_INT_PTD_SKIPMAP_REG, skip_map); | ||
1568 | priv->int_slots[qh->slot].qh = NULL; | ||
1569 | priv->int_slots[qh->slot].qtd = NULL; | ||
1570 | } | ||
1571 | |||
1572 | qh->slot = -1; | ||
1573 | priv->active_ptds--; | ||
1664 | } | 1574 | } |
1665 | 1575 | ||
1666 | static int isp1760_urb_dequeue(struct usb_hcd *hcd, struct urb *urb, | 1576 | static int isp1760_urb_dequeue(struct usb_hcd *hcd, struct urb *urb, |
1667 | int status) | 1577 | int status) |
1668 | { | 1578 | { |
1669 | struct isp1760_hcd *priv = hcd_to_priv(hcd); | 1579 | struct isp1760_hcd *priv = hcd_to_priv(hcd); |
1670 | struct inter_packet_info *ints; | 1580 | unsigned long spinflags; |
1671 | u32 i; | 1581 | struct isp1760_qh *qh; |
1672 | u32 reg_base, or_reg, skip_reg; | 1582 | struct isp1760_qtd *qtd; |
1673 | unsigned long flags; | 1583 | int retval = 0; |
1674 | struct ptd ptd; | ||
1675 | packet_enqueue *pe; | ||
1676 | |||
1677 | switch (usb_pipetype(urb->pipe)) { | ||
1678 | case PIPE_ISOCHRONOUS: | ||
1679 | return -EPIPE; | ||
1680 | break; | ||
1681 | 1584 | ||
1682 | case PIPE_INTERRUPT: | 1585 | spin_lock_irqsave(&priv->lock, spinflags); |
1683 | ints = priv->int_ints; | ||
1684 | reg_base = INT_REGS_OFFSET; | ||
1685 | or_reg = HC_INT_IRQ_MASK_OR_REG; | ||
1686 | skip_reg = HC_INT_PTD_SKIPMAP_REG; | ||
1687 | pe = enqueue_an_INT_packet; | ||
1688 | break; | ||
1689 | 1586 | ||
1690 | default: | 1587 | qh = urb->ep->hcpriv; |
1691 | ints = priv->atl_ints; | 1588 | if (!qh) { |
1692 | reg_base = ATL_REGS_OFFSET; | 1589 | retval = -EINVAL; |
1693 | or_reg = HC_ATL_IRQ_MASK_OR_REG; | 1590 | goto out; |
1694 | skip_reg = HC_ATL_PTD_SKIPMAP_REG; | ||
1695 | pe = enqueue_an_ATL_packet; | ||
1696 | break; | ||
1697 | } | 1591 | } |
1698 | 1592 | ||
1699 | memset(&ptd, 0, sizeof(ptd)); | 1593 | list_for_each_entry(qtd, &qh->qtd_list, qtd_list) |
1700 | spin_lock_irqsave(&priv->lock, flags); | 1594 | if (qtd->urb == urb) { |
1701 | 1595 | if (qtd->status == QTD_XFER_STARTED) | |
1702 | for (i = 0; i < 32; i++) { | 1596 | kill_transfer(hcd, urb, qh); |
1703 | if (ints->urb == urb) { | 1597 | qtd->status = QTD_RETIRE; |
1704 | u32 skip_map; | ||
1705 | u32 or_map; | ||
1706 | struct isp1760_qtd *qtd; | ||
1707 | struct isp1760_qh *qh = ints->qh; | ||
1708 | |||
1709 | skip_map = isp1760_readl(hcd->regs + skip_reg); | ||
1710 | skip_map |= 1 << i; | ||
1711 | isp1760_writel(skip_map, hcd->regs + skip_reg); | ||
1712 | |||
1713 | or_map = isp1760_readl(hcd->regs + or_reg); | ||
1714 | or_map &= ~(1 << i); | ||
1715 | isp1760_writel(or_map, hcd->regs + or_reg); | ||
1716 | |||
1717 | priv_write_copy(priv, (u32 *)&ptd, hcd->regs + reg_base | ||
1718 | + i * sizeof(ptd), sizeof(ptd)); | ||
1719 | qtd = ints->qtd; | ||
1720 | qtd = clean_up_qtdlist(qtd); | ||
1721 | |||
1722 | free_mem(priv, ints->payload); | ||
1723 | |||
1724 | ints->urb = NULL; | ||
1725 | ints->qh = NULL; | ||
1726 | ints->qtd = NULL; | ||
1727 | ints->data_buffer = NULL; | ||
1728 | ints->payload = 0; | ||
1729 | |||
1730 | isp1760_urb_done(priv, urb, status); | ||
1731 | if (qtd) | ||
1732 | pe(hcd, qh, qtd); | ||
1733 | break; | ||
1734 | |||
1735 | } else if (ints->qtd) { | ||
1736 | struct isp1760_qtd *qtd, *prev_qtd = ints->qtd; | ||
1737 | |||
1738 | for (qtd = ints->qtd->hw_next; qtd; qtd = qtd->hw_next) { | ||
1739 | if (qtd->urb == urb) { | ||
1740 | prev_qtd->hw_next = clean_up_qtdlist(qtd); | ||
1741 | isp1760_urb_done(priv, urb, status); | ||
1742 | break; | ||
1743 | } | ||
1744 | prev_qtd = qtd; | ||
1745 | } | ||
1746 | /* we found the urb before the end of the list */ | ||
1747 | if (qtd) | ||
1748 | break; | ||
1749 | } | 1598 | } |
1750 | ints++; | ||
1751 | } | ||
1752 | 1599 | ||
1753 | spin_unlock_irqrestore(&priv->lock, flags); | 1600 | urb->status = status; |
1754 | return 0; | 1601 | schedule_ptds(hcd); |
1602 | |||
1603 | out: | ||
1604 | spin_unlock_irqrestore(&priv->lock, spinflags); | ||
1605 | return retval; | ||
1755 | } | 1606 | } |
1756 | 1607 | ||
1757 | static irqreturn_t isp1760_irq(struct usb_hcd *usb_hcd) | 1608 | static void isp1760_endpoint_disable(struct usb_hcd *hcd, |
1609 | struct usb_host_endpoint *ep) | ||
1758 | { | 1610 | { |
1759 | struct isp1760_hcd *priv = hcd_to_priv(usb_hcd); | 1611 | struct isp1760_hcd *priv = hcd_to_priv(hcd); |
1760 | u32 imask; | 1612 | unsigned long spinflags; |
1761 | irqreturn_t irqret = IRQ_NONE; | 1613 | struct isp1760_qh *qh; |
1614 | struct isp1760_qtd *qtd; | ||
1762 | 1615 | ||
1763 | spin_lock(&priv->lock); | 1616 | spin_lock_irqsave(&priv->lock, spinflags); |
1764 | 1617 | ||
1765 | if (!(usb_hcd->state & HC_STATE_RUNNING)) | 1618 | qh = ep->hcpriv; |
1766 | goto leave; | 1619 | if (!qh) |
1620 | goto out; | ||
1767 | 1621 | ||
1768 | imask = isp1760_readl(usb_hcd->regs + HC_INTERRUPT_REG); | 1622 | list_for_each_entry(qtd, &qh->qtd_list, qtd_list) { |
1769 | if (unlikely(!imask)) | 1623 | if (qtd->status == QTD_XFER_STARTED) |
1770 | goto leave; | 1624 | kill_transfer(hcd, qtd->urb, qh); |
1625 | qtd->status = QTD_RETIRE; | ||
1626 | qtd->urb->status = -ECONNRESET; | ||
1627 | } | ||
1771 | 1628 | ||
1772 | isp1760_writel(imask, usb_hcd->regs + HC_INTERRUPT_REG); | 1629 | ep->hcpriv = NULL; |
1773 | if (imask & HC_ATL_INT) | 1630 | /* Cannot free qh here since it will be parsed by schedule_ptds() */ |
1774 | do_atl_int(usb_hcd); | ||
1775 | 1631 | ||
1776 | if (imask & HC_INTL_INT) | 1632 | schedule_ptds(hcd); |
1777 | do_intl_int(usb_hcd); | ||
1778 | 1633 | ||
1779 | irqret = IRQ_HANDLED; | 1634 | out: |
1780 | leave: | 1635 | spin_unlock_irqrestore(&priv->lock, spinflags); |
1781 | spin_unlock(&priv->lock); | ||
1782 | return irqret; | ||
1783 | } | 1636 | } |
1784 | 1637 | ||
1785 | static int isp1760_hub_status_data(struct usb_hcd *hcd, char *buf) | 1638 | static int isp1760_hub_status_data(struct usb_hcd *hcd, char *buf) |
@@ -1799,12 +1652,12 @@ static int isp1760_hub_status_data(struct usb_hcd *hcd, char *buf) | |||
1799 | mask = PORT_CSC; | 1652 | mask = PORT_CSC; |
1800 | 1653 | ||
1801 | spin_lock_irqsave(&priv->lock, flags); | 1654 | spin_lock_irqsave(&priv->lock, flags); |
1802 | temp = isp1760_readl(hcd->regs + HC_PORTSC1); | 1655 | temp = reg_read32(hcd->regs, HC_PORTSC1); |
1803 | 1656 | ||
1804 | if (temp & PORT_OWNER) { | 1657 | if (temp & PORT_OWNER) { |
1805 | if (temp & PORT_CSC) { | 1658 | if (temp & PORT_CSC) { |
1806 | temp &= ~PORT_CSC; | 1659 | temp &= ~PORT_CSC; |
1807 | isp1760_writel(temp, hcd->regs + HC_PORTSC1); | 1660 | reg_write32(hcd->regs, HC_PORTSC1, temp); |
1808 | goto done; | 1661 | goto done; |
1809 | } | 1662 | } |
1810 | } | 1663 | } |
@@ -1844,9 +1697,9 @@ static void isp1760_hub_descriptor(struct isp1760_hcd *priv, | |||
1844 | temp = 1 + (ports / 8); | 1697 | temp = 1 + (ports / 8); |
1845 | desc->bDescLength = 7 + 2 * temp; | 1698 | desc->bDescLength = 7 + 2 * temp; |
1846 | 1699 | ||
1847 | /* two bitmaps: ports removable, and usb 1.0 legacy PortPwrCtrlMask */ | 1700 | /* ports removable, and usb 1.0 legacy PortPwrCtrlMask */ |
1848 | memset(&desc->bitmap[0], 0, temp); | 1701 | memset(&desc->u.hs.DeviceRemovable[0], 0, temp); |
1849 | memset(&desc->bitmap[temp], 0xff, temp); | 1702 | memset(&desc->u.hs.DeviceRemovable[temp], 0xff, temp); |
1850 | 1703 | ||
1851 | /* per-port overcurrent reporting */ | 1704 | /* per-port overcurrent reporting */ |
1852 | temp = 0x0008; | 1705 | temp = 0x0008; |
@@ -1861,8 +1714,8 @@ static void isp1760_hub_descriptor(struct isp1760_hcd *priv, | |||
1861 | 1714 | ||
1862 | #define PORT_WAKE_BITS (PORT_WKOC_E|PORT_WKDISC_E|PORT_WKCONN_E) | 1715 | #define PORT_WAKE_BITS (PORT_WKOC_E|PORT_WKDISC_E|PORT_WKCONN_E) |
1863 | 1716 | ||
1864 | static int check_reset_complete(struct isp1760_hcd *priv, int index, | 1717 | static int check_reset_complete(struct usb_hcd *hcd, int index, |
1865 | u32 __iomem *status_reg, int port_status) | 1718 | int port_status) |
1866 | { | 1719 | { |
1867 | if (!(port_status & PORT_CONNECT)) | 1720 | if (!(port_status & PORT_CONNECT)) |
1868 | return port_status; | 1721 | return port_status; |
@@ -1870,15 +1723,17 @@ static int check_reset_complete(struct isp1760_hcd *priv, int index, | |||
1870 | /* if reset finished and it's still not enabled -- handoff */ | 1723 | /* if reset finished and it's still not enabled -- handoff */ |
1871 | if (!(port_status & PORT_PE)) { | 1724 | if (!(port_status & PORT_PE)) { |
1872 | 1725 | ||
1873 | printk(KERN_ERR "port %d full speed --> companion\n", | 1726 | dev_info(hcd->self.controller, |
1874 | index + 1); | 1727 | "port %d full speed --> companion\n", |
1728 | index + 1); | ||
1875 | 1729 | ||
1876 | port_status |= PORT_OWNER; | 1730 | port_status |= PORT_OWNER; |
1877 | port_status &= ~PORT_RWC_BITS; | 1731 | port_status &= ~PORT_RWC_BITS; |
1878 | isp1760_writel(port_status, status_reg); | 1732 | reg_write32(hcd->regs, HC_PORTSC1, port_status); |
1879 | 1733 | ||
1880 | } else | 1734 | } else |
1881 | printk(KERN_ERR "port %d high speed\n", index + 1); | 1735 | dev_info(hcd->self.controller, "port %d high speed\n", |
1736 | index + 1); | ||
1882 | 1737 | ||
1883 | return port_status; | 1738 | return port_status; |
1884 | } | 1739 | } |
@@ -1888,7 +1743,6 @@ static int isp1760_hub_control(struct usb_hcd *hcd, u16 typeReq, | |||
1888 | { | 1743 | { |
1889 | struct isp1760_hcd *priv = hcd_to_priv(hcd); | 1744 | struct isp1760_hcd *priv = hcd_to_priv(hcd); |
1890 | int ports = HCS_N_PORTS(priv->hcs_params); | 1745 | int ports = HCS_N_PORTS(priv->hcs_params); |
1891 | u32 __iomem *status_reg = hcd->regs + HC_PORTSC1; | ||
1892 | u32 temp, status; | 1746 | u32 temp, status; |
1893 | unsigned long flags; | 1747 | unsigned long flags; |
1894 | int retval = 0; | 1748 | int retval = 0; |
@@ -1917,7 +1771,7 @@ static int isp1760_hub_control(struct usb_hcd *hcd, u16 typeReq, | |||
1917 | if (!wIndex || wIndex > ports) | 1771 | if (!wIndex || wIndex > ports) |
1918 | goto error; | 1772 | goto error; |
1919 | wIndex--; | 1773 | wIndex--; |
1920 | temp = isp1760_readl(status_reg); | 1774 | temp = reg_read32(hcd->regs, HC_PORTSC1); |
1921 | 1775 | ||
1922 | /* | 1776 | /* |
1923 | * Even if OWNER is set, so the port is owned by the | 1777 | * Even if OWNER is set, so the port is owned by the |
@@ -1928,7 +1782,7 @@ static int isp1760_hub_control(struct usb_hcd *hcd, u16 typeReq, | |||
1928 | 1782 | ||
1929 | switch (wValue) { | 1783 | switch (wValue) { |
1930 | case USB_PORT_FEAT_ENABLE: | 1784 | case USB_PORT_FEAT_ENABLE: |
1931 | isp1760_writel(temp & ~PORT_PE, status_reg); | 1785 | reg_write32(hcd->regs, HC_PORTSC1, temp & ~PORT_PE); |
1932 | break; | 1786 | break; |
1933 | case USB_PORT_FEAT_C_ENABLE: | 1787 | case USB_PORT_FEAT_C_ENABLE: |
1934 | /* XXX error? */ | 1788 | /* XXX error? */ |
@@ -1942,8 +1796,8 @@ static int isp1760_hub_control(struct usb_hcd *hcd, u16 typeReq, | |||
1942 | goto error; | 1796 | goto error; |
1943 | /* resume signaling for 20 msec */ | 1797 | /* resume signaling for 20 msec */ |
1944 | temp &= ~(PORT_RWC_BITS); | 1798 | temp &= ~(PORT_RWC_BITS); |
1945 | isp1760_writel(temp | PORT_RESUME, | 1799 | reg_write32(hcd->regs, HC_PORTSC1, |
1946 | status_reg); | 1800 | temp | PORT_RESUME); |
1947 | priv->reset_done = jiffies + | 1801 | priv->reset_done = jiffies + |
1948 | msecs_to_jiffies(20); | 1802 | msecs_to_jiffies(20); |
1949 | } | 1803 | } |
@@ -1953,11 +1807,11 @@ static int isp1760_hub_control(struct usb_hcd *hcd, u16 typeReq, | |||
1953 | break; | 1807 | break; |
1954 | case USB_PORT_FEAT_POWER: | 1808 | case USB_PORT_FEAT_POWER: |
1955 | if (HCS_PPC(priv->hcs_params)) | 1809 | if (HCS_PPC(priv->hcs_params)) |
1956 | isp1760_writel(temp & ~PORT_POWER, status_reg); | 1810 | reg_write32(hcd->regs, HC_PORTSC1, |
1811 | temp & ~PORT_POWER); | ||
1957 | break; | 1812 | break; |
1958 | case USB_PORT_FEAT_C_CONNECTION: | 1813 | case USB_PORT_FEAT_C_CONNECTION: |
1959 | isp1760_writel(temp | PORT_CSC, | 1814 | reg_write32(hcd->regs, HC_PORTSC1, temp | PORT_CSC); |
1960 | status_reg); | ||
1961 | break; | 1815 | break; |
1962 | case USB_PORT_FEAT_C_OVER_CURRENT: | 1816 | case USB_PORT_FEAT_C_OVER_CURRENT: |
1963 | /* XXX error ?*/ | 1817 | /* XXX error ?*/ |
@@ -1968,7 +1822,7 @@ static int isp1760_hub_control(struct usb_hcd *hcd, u16 typeReq, | |||
1968 | default: | 1822 | default: |
1969 | goto error; | 1823 | goto error; |
1970 | } | 1824 | } |
1971 | isp1760_readl(hcd->regs + HC_USBCMD); | 1825 | reg_read32(hcd->regs, HC_USBCMD); |
1972 | break; | 1826 | break; |
1973 | case GetHubDescriptor: | 1827 | case GetHubDescriptor: |
1974 | isp1760_hub_descriptor(priv, (struct usb_hub_descriptor *) | 1828 | isp1760_hub_descriptor(priv, (struct usb_hub_descriptor *) |
@@ -1983,7 +1837,7 @@ static int isp1760_hub_control(struct usb_hcd *hcd, u16 typeReq, | |||
1983 | goto error; | 1837 | goto error; |
1984 | wIndex--; | 1838 | wIndex--; |
1985 | status = 0; | 1839 | status = 0; |
1986 | temp = isp1760_readl(status_reg); | 1840 | temp = reg_read32(hcd->regs, HC_PORTSC1); |
1987 | 1841 | ||
1988 | /* wPortChange bits */ | 1842 | /* wPortChange bits */ |
1989 | if (temp & PORT_CSC) | 1843 | if (temp & PORT_CSC) |
@@ -1992,7 +1846,7 @@ static int isp1760_hub_control(struct usb_hcd *hcd, u16 typeReq, | |||
1992 | 1846 | ||
1993 | /* whoever resumes must GetPortStatus to complete it!! */ | 1847 | /* whoever resumes must GetPortStatus to complete it!! */ |
1994 | if (temp & PORT_RESUME) { | 1848 | if (temp & PORT_RESUME) { |
1995 | printk(KERN_ERR "Port resume should be skipped.\n"); | 1849 | dev_err(hcd->self.controller, "Port resume should be skipped.\n"); |
1996 | 1850 | ||
1997 | /* Remote Wakeup received? */ | 1851 | /* Remote Wakeup received? */ |
1998 | if (!priv->reset_done) { | 1852 | if (!priv->reset_done) { |
@@ -2000,8 +1854,7 @@ static int isp1760_hub_control(struct usb_hcd *hcd, u16 typeReq, | |||
2000 | priv->reset_done = jiffies | 1854 | priv->reset_done = jiffies |
2001 | + msecs_to_jiffies(20); | 1855 | + msecs_to_jiffies(20); |
2002 | /* check the port again */ | 1856 | /* check the port again */ |
2003 | mod_timer(&priv_to_hcd(priv)->rh_timer, | 1857 | mod_timer(&hcd->rh_timer, priv->reset_done); |
2004 | priv->reset_done); | ||
2005 | } | 1858 | } |
2006 | 1859 | ||
2007 | /* resume completed? */ | 1860 | /* resume completed? */ |
@@ -2011,14 +1864,13 @@ static int isp1760_hub_control(struct usb_hcd *hcd, u16 typeReq, | |||
2011 | priv->reset_done = 0; | 1864 | priv->reset_done = 0; |
2012 | 1865 | ||
2013 | /* stop resume signaling */ | 1866 | /* stop resume signaling */ |
2014 | temp = isp1760_readl(status_reg); | 1867 | temp = reg_read32(hcd->regs, HC_PORTSC1); |
2015 | isp1760_writel( | 1868 | reg_write32(hcd->regs, HC_PORTSC1, |
2016 | temp & ~(PORT_RWC_BITS | PORT_RESUME), | 1869 | temp & ~(PORT_RWC_BITS | PORT_RESUME)); |
2017 | status_reg); | 1870 | retval = handshake(hcd, HC_PORTSC1, |
2018 | retval = handshake(priv, status_reg, | ||
2019 | PORT_RESUME, 0, 2000 /* 2msec */); | 1871 | PORT_RESUME, 0, 2000 /* 2msec */); |
2020 | if (retval != 0) { | 1872 | if (retval != 0) { |
2021 | isp1760_err(priv, | 1873 | dev_err(hcd->self.controller, |
2022 | "port %d resume error %d\n", | 1874 | "port %d resume error %d\n", |
2023 | wIndex + 1, retval); | 1875 | wIndex + 1, retval); |
2024 | goto error; | 1876 | goto error; |
@@ -2035,22 +1887,21 @@ static int isp1760_hub_control(struct usb_hcd *hcd, u16 typeReq, | |||
2035 | priv->reset_done = 0; | 1887 | priv->reset_done = 0; |
2036 | 1888 | ||
2037 | /* force reset to complete */ | 1889 | /* force reset to complete */ |
2038 | isp1760_writel(temp & ~PORT_RESET, | 1890 | reg_write32(hcd->regs, HC_PORTSC1, temp & ~PORT_RESET); |
2039 | status_reg); | ||
2040 | /* REVISIT: some hardware needs 550+ usec to clear | 1891 | /* REVISIT: some hardware needs 550+ usec to clear |
2041 | * this bit; seems too long to spin routinely... | 1892 | * this bit; seems too long to spin routinely... |
2042 | */ | 1893 | */ |
2043 | retval = handshake(priv, status_reg, | 1894 | retval = handshake(hcd, HC_PORTSC1, |
2044 | PORT_RESET, 0, 750); | 1895 | PORT_RESET, 0, 750); |
2045 | if (retval != 0) { | 1896 | if (retval != 0) { |
2046 | isp1760_err(priv, "port %d reset error %d\n", | 1897 | dev_err(hcd->self.controller, "port %d reset error %d\n", |
2047 | wIndex + 1, retval); | 1898 | wIndex + 1, retval); |
2048 | goto error; | 1899 | goto error; |
2049 | } | 1900 | } |
2050 | 1901 | ||
2051 | /* see what we found out */ | 1902 | /* see what we found out */ |
2052 | temp = check_reset_complete(priv, wIndex, status_reg, | 1903 | temp = check_reset_complete(hcd, wIndex, |
2053 | isp1760_readl(status_reg)); | 1904 | reg_read32(hcd->regs, HC_PORTSC1)); |
2054 | } | 1905 | } |
2055 | /* | 1906 | /* |
2056 | * Even if OWNER is set, there's no harm letting khubd | 1907 | * Even if OWNER is set, there's no harm letting khubd |
@@ -2059,12 +1910,12 @@ static int isp1760_hub_control(struct usb_hcd *hcd, u16 typeReq, | |||
2059 | */ | 1910 | */ |
2060 | 1911 | ||
2061 | if (temp & PORT_OWNER) | 1912 | if (temp & PORT_OWNER) |
2062 | printk(KERN_ERR "Warning: PORT_OWNER is set\n"); | 1913 | dev_err(hcd->self.controller, "PORT_OWNER is set\n"); |
2063 | 1914 | ||
2064 | if (temp & PORT_CONNECT) { | 1915 | if (temp & PORT_CONNECT) { |
2065 | status |= USB_PORT_STAT_CONNECTION; | 1916 | status |= USB_PORT_STAT_CONNECTION; |
2066 | /* status may be from integrated TT */ | 1917 | /* status may be from integrated TT */ |
2067 | status |= ehci_port_speed(priv, temp); | 1918 | status |= USB_PORT_STAT_HIGH_SPEED; |
2068 | } | 1919 | } |
2069 | if (temp & PORT_PE) | 1920 | if (temp & PORT_PE) |
2070 | status |= USB_PORT_STAT_ENABLE; | 1921 | status |= USB_PORT_STAT_ENABLE; |
@@ -2093,14 +1944,14 @@ static int isp1760_hub_control(struct usb_hcd *hcd, u16 typeReq, | |||
2093 | if (!wIndex || wIndex > ports) | 1944 | if (!wIndex || wIndex > ports) |
2094 | goto error; | 1945 | goto error; |
2095 | wIndex--; | 1946 | wIndex--; |
2096 | temp = isp1760_readl(status_reg); | 1947 | temp = reg_read32(hcd->regs, HC_PORTSC1); |
2097 | if (temp & PORT_OWNER) | 1948 | if (temp & PORT_OWNER) |
2098 | break; | 1949 | break; |
2099 | 1950 | ||
2100 | /* temp &= ~PORT_RWC_BITS; */ | 1951 | /* temp &= ~PORT_RWC_BITS; */ |
2101 | switch (wValue) { | 1952 | switch (wValue) { |
2102 | case USB_PORT_FEAT_ENABLE: | 1953 | case USB_PORT_FEAT_ENABLE: |
2103 | isp1760_writel(temp | PORT_PE, status_reg); | 1954 | reg_write32(hcd->regs, HC_PORTSC1, temp | PORT_PE); |
2104 | break; | 1955 | break; |
2105 | 1956 | ||
2106 | case USB_PORT_FEAT_SUSPEND: | 1957 | case USB_PORT_FEAT_SUSPEND: |
@@ -2108,12 +1959,12 @@ static int isp1760_hub_control(struct usb_hcd *hcd, u16 typeReq, | |||
2108 | || (temp & PORT_RESET) != 0) | 1959 | || (temp & PORT_RESET) != 0) |
2109 | goto error; | 1960 | goto error; |
2110 | 1961 | ||
2111 | isp1760_writel(temp | PORT_SUSPEND, status_reg); | 1962 | reg_write32(hcd->regs, HC_PORTSC1, temp | PORT_SUSPEND); |
2112 | break; | 1963 | break; |
2113 | case USB_PORT_FEAT_POWER: | 1964 | case USB_PORT_FEAT_POWER: |
2114 | if (HCS_PPC(priv->hcs_params)) | 1965 | if (HCS_PPC(priv->hcs_params)) |
2115 | isp1760_writel(temp | PORT_POWER, | 1966 | reg_write32(hcd->regs, HC_PORTSC1, |
2116 | status_reg); | 1967 | temp | PORT_POWER); |
2117 | break; | 1968 | break; |
2118 | case USB_PORT_FEAT_RESET: | 1969 | case USB_PORT_FEAT_RESET: |
2119 | if (temp & PORT_RESUME) | 1970 | if (temp & PORT_RESUME) |
@@ -2136,12 +1987,12 @@ static int isp1760_hub_control(struct usb_hcd *hcd, u16 typeReq, | |||
2136 | priv->reset_done = jiffies + | 1987 | priv->reset_done = jiffies + |
2137 | msecs_to_jiffies(50); | 1988 | msecs_to_jiffies(50); |
2138 | } | 1989 | } |
2139 | isp1760_writel(temp, status_reg); | 1990 | reg_write32(hcd->regs, HC_PORTSC1, temp); |
2140 | break; | 1991 | break; |
2141 | default: | 1992 | default: |
2142 | goto error; | 1993 | goto error; |
2143 | } | 1994 | } |
2144 | isp1760_readl(hcd->regs + HC_USBCMD); | 1995 | reg_read32(hcd->regs, HC_USBCMD); |
2145 | break; | 1996 | break; |
2146 | 1997 | ||
2147 | default: | 1998 | default: |
@@ -2153,57 +2004,12 @@ error: | |||
2153 | return retval; | 2004 | return retval; |
2154 | } | 2005 | } |
2155 | 2006 | ||
2156 | static void isp1760_endpoint_disable(struct usb_hcd *usb_hcd, | ||
2157 | struct usb_host_endpoint *ep) | ||
2158 | { | ||
2159 | struct isp1760_hcd *priv = hcd_to_priv(usb_hcd); | ||
2160 | struct isp1760_qh *qh; | ||
2161 | struct isp1760_qtd *qtd; | ||
2162 | unsigned long flags; | ||
2163 | |||
2164 | spin_lock_irqsave(&priv->lock, flags); | ||
2165 | qh = ep->hcpriv; | ||
2166 | if (!qh) | ||
2167 | goto out; | ||
2168 | |||
2169 | ep->hcpriv = NULL; | ||
2170 | do { | ||
2171 | /* more than entry might get removed */ | ||
2172 | if (list_empty(&qh->qtd_list)) | ||
2173 | break; | ||
2174 | |||
2175 | qtd = list_first_entry(&qh->qtd_list, struct isp1760_qtd, | ||
2176 | qtd_list); | ||
2177 | |||
2178 | if (qtd->status & URB_ENQUEUED) { | ||
2179 | |||
2180 | spin_unlock_irqrestore(&priv->lock, flags); | ||
2181 | isp1760_urb_dequeue(usb_hcd, qtd->urb, -ECONNRESET); | ||
2182 | spin_lock_irqsave(&priv->lock, flags); | ||
2183 | } else { | ||
2184 | struct urb *urb; | ||
2185 | |||
2186 | urb = qtd->urb; | ||
2187 | clean_up_qtdlist(qtd); | ||
2188 | isp1760_urb_done(priv, urb, -ECONNRESET); | ||
2189 | } | ||
2190 | } while (1); | ||
2191 | |||
2192 | qh_destroy(qh); | ||
2193 | /* remove requests and leak them. | ||
2194 | * ATL are pretty fast done, INT could take a while... | ||
2195 | * The latter shoule be removed | ||
2196 | */ | ||
2197 | out: | ||
2198 | spin_unlock_irqrestore(&priv->lock, flags); | ||
2199 | } | ||
2200 | |||
2201 | static int isp1760_get_frame(struct usb_hcd *hcd) | 2007 | static int isp1760_get_frame(struct usb_hcd *hcd) |
2202 | { | 2008 | { |
2203 | struct isp1760_hcd *priv = hcd_to_priv(hcd); | 2009 | struct isp1760_hcd *priv = hcd_to_priv(hcd); |
2204 | u32 fr; | 2010 | u32 fr; |
2205 | 2011 | ||
2206 | fr = isp1760_readl(hcd->regs + HC_FRINDEX); | 2012 | fr = reg_read32(hcd->regs, HC_FRINDEX); |
2207 | return (fr >> 3) % priv->periodic_size; | 2013 | return (fr >> 3) % priv->periodic_size; |
2208 | } | 2014 | } |
2209 | 2015 | ||
@@ -2217,13 +2023,13 @@ static void isp1760_stop(struct usb_hcd *hcd) | |||
2217 | mdelay(20); | 2023 | mdelay(20); |
2218 | 2024 | ||
2219 | spin_lock_irq(&priv->lock); | 2025 | spin_lock_irq(&priv->lock); |
2220 | ehci_reset(priv); | 2026 | ehci_reset(hcd); |
2221 | /* Disable IRQ */ | 2027 | /* Disable IRQ */ |
2222 | temp = isp1760_readl(hcd->regs + HC_HW_MODE_CTRL); | 2028 | temp = reg_read32(hcd->regs, HC_HW_MODE_CTRL); |
2223 | isp1760_writel(temp &= ~HW_GLOBAL_INTR_EN, hcd->regs + HC_HW_MODE_CTRL); | 2029 | reg_write32(hcd->regs, HC_HW_MODE_CTRL, temp &= ~HW_GLOBAL_INTR_EN); |
2224 | spin_unlock_irq(&priv->lock); | 2030 | spin_unlock_irq(&priv->lock); |
2225 | 2031 | ||
2226 | isp1760_writel(0, hcd->regs + HC_CONFIGFLAG); | 2032 | reg_write32(hcd->regs, HC_CONFIGFLAG, 0); |
2227 | } | 2033 | } |
2228 | 2034 | ||
2229 | static void isp1760_shutdown(struct usb_hcd *hcd) | 2035 | static void isp1760_shutdown(struct usb_hcd *hcd) |
@@ -2231,12 +2037,12 @@ static void isp1760_shutdown(struct usb_hcd *hcd) | |||
2231 | u32 command, temp; | 2037 | u32 command, temp; |
2232 | 2038 | ||
2233 | isp1760_stop(hcd); | 2039 | isp1760_stop(hcd); |
2234 | temp = isp1760_readl(hcd->regs + HC_HW_MODE_CTRL); | 2040 | temp = reg_read32(hcd->regs, HC_HW_MODE_CTRL); |
2235 | isp1760_writel(temp &= ~HW_GLOBAL_INTR_EN, hcd->regs + HC_HW_MODE_CTRL); | 2041 | reg_write32(hcd->regs, HC_HW_MODE_CTRL, temp &= ~HW_GLOBAL_INTR_EN); |
2236 | 2042 | ||
2237 | command = isp1760_readl(hcd->regs + HC_USBCMD); | 2043 | command = reg_read32(hcd->regs, HC_USBCMD); |
2238 | command &= ~CMD_RUN; | 2044 | command &= ~CMD_RUN; |
2239 | isp1760_writel(command, hcd->regs + HC_USBCMD); | 2045 | reg_write32(hcd->regs, HC_USBCMD, command); |
2240 | } | 2046 | } |
2241 | 2047 | ||
2242 | static const struct hc_driver isp1760_hc_driver = { | 2048 | static const struct hc_driver isp1760_hc_driver = { |
@@ -2259,6 +2065,13 @@ static const struct hc_driver isp1760_hc_driver = { | |||
2259 | 2065 | ||
2260 | int __init init_kmem_once(void) | 2066 | int __init init_kmem_once(void) |
2261 | { | 2067 | { |
2068 | urb_listitem_cachep = kmem_cache_create("isp1760 urb_listitem", | ||
2069 | sizeof(struct urb_listitem), 0, SLAB_TEMPORARY | | ||
2070 | SLAB_MEM_SPREAD, NULL); | ||
2071 | |||
2072 | if (!urb_listitem_cachep) | ||
2073 | return -ENOMEM; | ||
2074 | |||
2262 | qtd_cachep = kmem_cache_create("isp1760_qtd", | 2075 | qtd_cachep = kmem_cache_create("isp1760_qtd", |
2263 | sizeof(struct isp1760_qtd), 0, SLAB_TEMPORARY | | 2076 | sizeof(struct isp1760_qtd), 0, SLAB_TEMPORARY | |
2264 | SLAB_MEM_SPREAD, NULL); | 2077 | SLAB_MEM_SPREAD, NULL); |
@@ -2281,6 +2094,7 @@ void deinit_kmem_cache(void) | |||
2281 | { | 2094 | { |
2282 | kmem_cache_destroy(qtd_cachep); | 2095 | kmem_cache_destroy(qtd_cachep); |
2283 | kmem_cache_destroy(qh_cachep); | 2096 | kmem_cache_destroy(qh_cachep); |
2097 | kmem_cache_destroy(urb_listitem_cachep); | ||
2284 | } | 2098 | } |
2285 | 2099 | ||
2286 | struct usb_hcd *isp1760_register(phys_addr_t res_start, resource_size_t res_len, | 2100 | struct usb_hcd *isp1760_register(phys_addr_t res_start, resource_size_t res_len, |