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authorGreg Kroah-Hartman <gregkh@linuxfoundation.org>2013-07-24 19:10:58 -0400
committerGreg Kroah-Hartman <gregkh@linuxfoundation.org>2013-07-24 19:10:58 -0400
commit5447e0a652ba8907a0f4d88821acf7d37ef81af1 (patch)
treeb22a33022fad11706a62a926c0a462e2ea59265f /drivers/usb/host/fotg210.h
parent1dd3d123239179fad5de5dc00a6e0014a1918fde (diff)
Revert "usb: host: Faraday fotg210-hcd driver"
This reverts commit 1dd3d123239179fad5de5dc00a6e0014a1918fde. The email address for the developer now bounces, which means they have moved on, so remove the driver until someone else from the company steps up to maintain it. Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Diffstat (limited to 'drivers/usb/host/fotg210.h')
-rw-r--r--drivers/usb/host/fotg210.h750
1 files changed, 0 insertions, 750 deletions
diff --git a/drivers/usb/host/fotg210.h b/drivers/usb/host/fotg210.h
deleted file mode 100644
index 8920f9d32564..000000000000
--- a/drivers/usb/host/fotg210.h
+++ /dev/null
@@ -1,750 +0,0 @@
1#ifndef __LINUX_FOTG210_H
2#define __LINUX_FOTG210_H
3
4/* definitions used for the EHCI driver */
5
6/*
7 * __hc32 and __hc16 are "Host Controller" types, they may be equivalent to
8 * __leXX (normally) or __beXX (given FOTG210_BIG_ENDIAN_DESC), depending on
9 * the host controller implementation.
10 *
11 * To facilitate the strongest possible byte-order checking from "sparse"
12 * and so on, we use __leXX unless that's not practical.
13 */
14#define __hc32 __le32
15#define __hc16 __le16
16
17/* statistics can be kept for tuning/monitoring */
18struct fotg210_stats {
19 /* irq usage */
20 unsigned long normal;
21 unsigned long error;
22 unsigned long iaa;
23 unsigned long lost_iaa;
24
25 /* termination of urbs from core */
26 unsigned long complete;
27 unsigned long unlink;
28};
29
30/* fotg210_hcd->lock guards shared data against other CPUs:
31 * fotg210_hcd: async, unlink, periodic (and shadow), ...
32 * usb_host_endpoint: hcpriv
33 * fotg210_qh: qh_next, qtd_list
34 * fotg210_qtd: qtd_list
35 *
36 * Also, hold this lock when talking to HC registers or
37 * when updating hw_* fields in shared qh/qtd/... structures.
38 */
39
40#define FOTG210_MAX_ROOT_PORTS 1 /* see HCS_N_PORTS */
41
42/*
43 * fotg210_rh_state values of FOTG210_RH_RUNNING or above mean that the
44 * controller may be doing DMA. Lower values mean there's no DMA.
45 */
46enum fotg210_rh_state {
47 FOTG210_RH_HALTED,
48 FOTG210_RH_SUSPENDED,
49 FOTG210_RH_RUNNING,
50 FOTG210_RH_STOPPING
51};
52
53/*
54 * Timer events, ordered by increasing delay length.
55 * Always update event_delays_ns[] and event_handlers[] (defined in
56 * ehci-timer.c) in parallel with this list.
57 */
58enum fotg210_hrtimer_event {
59 FOTG210_HRTIMER_POLL_ASS, /* Poll for async schedule off */
60 FOTG210_HRTIMER_POLL_PSS, /* Poll for periodic schedule off */
61 FOTG210_HRTIMER_POLL_DEAD, /* Wait for dead controller to stop */
62 FOTG210_HRTIMER_UNLINK_INTR, /* Wait for interrupt QH unlink */
63 FOTG210_HRTIMER_FREE_ITDS, /* Wait for unused iTDs and siTDs */
64 FOTG210_HRTIMER_ASYNC_UNLINKS, /* Unlink empty async QHs */
65 FOTG210_HRTIMER_IAA_WATCHDOG, /* Handle lost IAA interrupts */
66 FOTG210_HRTIMER_DISABLE_PERIODIC, /* Wait to disable periodic sched */
67 FOTG210_HRTIMER_DISABLE_ASYNC, /* Wait to disable async sched */
68 FOTG210_HRTIMER_IO_WATCHDOG, /* Check for missing IRQs */
69 FOTG210_HRTIMER_NUM_EVENTS /* Must come last */
70};
71#define FOTG210_HRTIMER_NO_EVENT 99
72
73struct fotg210_hcd { /* one per controller */
74 /* timing support */
75 enum fotg210_hrtimer_event next_hrtimer_event;
76 unsigned enabled_hrtimer_events;
77 ktime_t hr_timeouts[FOTG210_HRTIMER_NUM_EVENTS];
78 struct hrtimer hrtimer;
79
80 int PSS_poll_count;
81 int ASS_poll_count;
82 int died_poll_count;
83
84 /* glue to PCI and HCD framework */
85 struct fotg210_caps __iomem *caps;
86 struct fotg210_regs __iomem *regs;
87 struct fotg210_dbg_port __iomem *debug;
88
89 __u32 hcs_params; /* cached register copy */
90 spinlock_t lock;
91 enum fotg210_rh_state rh_state;
92
93 /* general schedule support */
94 bool scanning:1;
95 bool need_rescan:1;
96 bool intr_unlinking:1;
97 bool async_unlinking:1;
98 bool shutdown:1;
99 struct fotg210_qh *qh_scan_next;
100
101 /* async schedule support */
102 struct fotg210_qh *async;
103 struct fotg210_qh *dummy; /* For AMD quirk use */
104 struct fotg210_qh *async_unlink;
105 struct fotg210_qh *async_unlink_last;
106 struct fotg210_qh *async_iaa;
107 unsigned async_unlink_cycle;
108 unsigned async_count; /* async activity count */
109
110 /* periodic schedule support */
111#define DEFAULT_I_TDPS 1024 /* some HCs can do less */
112 unsigned periodic_size;
113 __hc32 *periodic; /* hw periodic table */
114 dma_addr_t periodic_dma;
115 struct list_head intr_qh_list;
116 unsigned i_thresh; /* uframes HC might cache */
117
118 union fotg210_shadow *pshadow; /* mirror hw periodic table */
119 struct fotg210_qh *intr_unlink;
120 struct fotg210_qh *intr_unlink_last;
121 unsigned intr_unlink_cycle;
122 unsigned now_frame; /* frame from HC hardware */
123 unsigned next_frame; /* scan periodic, start here */
124 unsigned intr_count; /* intr activity count */
125 unsigned isoc_count; /* isoc activity count */
126 unsigned periodic_count; /* periodic activity count */
127 /* max periodic time per uframe */
128 unsigned uframe_periodic_max;
129
130
131 /* list of itds completed while now_frame was still active */
132 struct list_head cached_itd_list;
133 struct fotg210_itd *last_itd_to_free;
134
135 /* per root hub port */
136 unsigned long reset_done[FOTG210_MAX_ROOT_PORTS];
137
138 /* bit vectors (one bit per port) */
139 unsigned long bus_suspended; /* which ports were
140 already suspended at the start of a bus suspend */
141 unsigned long companion_ports; /* which ports are
142 dedicated to the companion controller */
143 unsigned long owned_ports; /* which ports are
144 owned by the companion during a bus suspend */
145 unsigned long port_c_suspend; /* which ports have
146 the change-suspend feature turned on */
147 unsigned long suspended_ports; /* which ports are
148 suspended */
149 unsigned long resuming_ports; /* which ports have
150 started to resume */
151
152 /* per-HC memory pools (could be per-bus, but ...) */
153 struct dma_pool *qh_pool; /* qh per active urb */
154 struct dma_pool *qtd_pool; /* one or more per qh */
155 struct dma_pool *itd_pool; /* itd per iso urb */
156
157 unsigned random_frame;
158 unsigned long next_statechange;
159 ktime_t last_periodic_enable;
160 u32 command;
161
162 /* SILICON QUIRKS */
163 unsigned need_io_watchdog:1;
164 unsigned fs_i_thresh:1; /* Intel iso scheduling */
165
166 u8 sbrn; /* packed release number */
167
168 /* irq statistics */
169#ifdef FOTG210_STATS
170 struct fotg210_stats stats;
171# define COUNT(x) ((x)++)
172#else
173# define COUNT(x)
174#endif
175
176 /* debug files */
177#ifdef DEBUG
178 struct dentry *debug_dir;
179#endif
180};
181
182/* convert between an HCD pointer and the corresponding FOTG210_HCD */
183static inline struct fotg210_hcd *hcd_to_fotg210(struct usb_hcd *hcd)
184{
185 return (struct fotg210_hcd *)(hcd->hcd_priv);
186}
187static inline struct usb_hcd *fotg210_to_hcd(struct fotg210_hcd *fotg210)
188{
189 return container_of((void *) fotg210, struct usb_hcd, hcd_priv);
190}
191
192/*-------------------------------------------------------------------------*/
193
194/* EHCI register interface, corresponds to EHCI Revision 0.95 specification */
195
196/* Section 2.2 Host Controller Capability Registers */
197struct fotg210_caps {
198 /* these fields are specified as 8 and 16 bit registers,
199 * but some hosts can't perform 8 or 16 bit PCI accesses.
200 * some hosts treat caplength and hciversion as parts of a 32-bit
201 * register, others treat them as two separate registers, this
202 * affects the memory map for big endian controllers.
203 */
204 u32 hc_capbase;
205#define HC_LENGTH(fotg210, p) (0x00ff&((p) >> /* bits 7:0 / offset 00h */ \
206 (fotg210_big_endian_capbase(fotg210) ? 24 : 0)))
207#define HC_VERSION(fotg210, p) (0xffff&((p) >> /* bits 31:16 / offset 02h */ \
208 (fotg210_big_endian_capbase(fotg210) ? 0 : 16)))
209 u32 hcs_params; /* HCSPARAMS - offset 0x4 */
210#define HCS_N_PORTS(p) (((p)>>0)&0xf) /* bits 3:0, ports on HC */
211
212 u32 hcc_params; /* HCCPARAMS - offset 0x8 */
213#define HCC_CANPARK(p) ((p)&(1 << 2)) /* true: can park on async qh */
214#define HCC_PGM_FRAMELISTLEN(p) ((p)&(1 << 1)) /* true: periodic_size changes*/
215 u8 portroute[8]; /* nibbles for routing - offset 0xC */
216};
217
218
219/* Section 2.3 Host Controller Operational Registers */
220struct fotg210_regs {
221
222 /* USBCMD: offset 0x00 */
223 u32 command;
224
225/* EHCI 1.1 addendum */
226/* 23:16 is r/w intr rate, in microframes; default "8" == 1/msec */
227#define CMD_PARK (1<<11) /* enable "park" on async qh */
228#define CMD_PARK_CNT(c) (((c)>>8)&3) /* how many transfers to park for */
229#define CMD_IAAD (1<<6) /* "doorbell" interrupt async advance */
230#define CMD_ASE (1<<5) /* async schedule enable */
231#define CMD_PSE (1<<4) /* periodic schedule enable */
232/* 3:2 is periodic frame list size */
233#define CMD_RESET (1<<1) /* reset HC not bus */
234#define CMD_RUN (1<<0) /* start/stop HC */
235
236 /* USBSTS: offset 0x04 */
237 u32 status;
238#define STS_ASS (1<<15) /* Async Schedule Status */
239#define STS_PSS (1<<14) /* Periodic Schedule Status */
240#define STS_RECL (1<<13) /* Reclamation */
241#define STS_HALT (1<<12) /* Not running (any reason) */
242/* some bits reserved */
243 /* these STS_* flags are also intr_enable bits (USBINTR) */
244#define STS_IAA (1<<5) /* Interrupted on async advance */
245#define STS_FATAL (1<<4) /* such as some PCI access errors */
246#define STS_FLR (1<<3) /* frame list rolled over */
247#define STS_PCD (1<<2) /* port change detect */
248#define STS_ERR (1<<1) /* "error" completion (overflow, ...) */
249#define STS_INT (1<<0) /* "normal" completion (short, ...) */
250
251 /* USBINTR: offset 0x08 */
252 u32 intr_enable;
253
254 /* FRINDEX: offset 0x0C */
255 u32 frame_index; /* current microframe number */
256 /* CTRLDSSEGMENT: offset 0x10 */
257 u32 segment; /* address bits 63:32 if needed */
258 /* PERIODICLISTBASE: offset 0x14 */
259 u32 frame_list; /* points to periodic list */
260 /* ASYNCLISTADDR: offset 0x18 */
261 u32 async_next; /* address of next async queue head */
262
263 u32 reserved1;
264 /* PORTSC: offset 0x20 */
265 u32 port_status;
266/* 31:23 reserved */
267#define PORT_USB11(x) (((x)&(3<<10)) == (1<<10)) /* USB 1.1 device */
268#define PORT_RESET (1<<8) /* reset port */
269#define PORT_SUSPEND (1<<7) /* suspend port */
270#define PORT_RESUME (1<<6) /* resume it */
271#define PORT_PEC (1<<3) /* port enable change */
272#define PORT_PE (1<<2) /* port enable */
273#define PORT_CSC (1<<1) /* connect status change */
274#define PORT_CONNECT (1<<0) /* device connected */
275#define PORT_RWC_BITS (PORT_CSC | PORT_PEC)
276 u32 reserved2[19];
277
278 /* OTGCSR: offet 0x70 */
279 u32 otgcsr;
280#define OTGCSR_HOST_SPD_TYP (3 << 22)
281#define OTGCSR_A_BUS_DROP (1 << 5)
282#define OTGCSR_A_BUS_REQ (1 << 4)
283
284 /* OTGISR: offset 0x74 */
285 u32 otgisr;
286#define OTGISR_OVC (1 << 10)
287
288 u32 reserved3[15];
289
290 /* GMIR: offset 0xB4 */
291 u32 gmir;
292#define GMIR_INT_POLARITY (1 << 3) /*Active High*/
293#define GMIR_MHC_INT (1 << 2)
294#define GMIR_MOTG_INT (1 << 1)
295#define GMIR_MDEV_INT (1 << 0)
296};
297
298/* Appendix C, Debug port ... intended for use with special "debug devices"
299 * that can help if there's no serial console. (nonstandard enumeration.)
300 */
301struct fotg210_dbg_port {
302 u32 control;
303#define DBGP_OWNER (1<<30)
304#define DBGP_ENABLED (1<<28)
305#define DBGP_DONE (1<<16)
306#define DBGP_INUSE (1<<10)
307#define DBGP_ERRCODE(x) (((x)>>7)&0x07)
308# define DBGP_ERR_BAD 1
309# define DBGP_ERR_SIGNAL 2
310#define DBGP_ERROR (1<<6)
311#define DBGP_GO (1<<5)
312#define DBGP_OUT (1<<4)
313#define DBGP_LEN(x) (((x)>>0)&0x0f)
314 u32 pids;
315#define DBGP_PID_GET(x) (((x)>>16)&0xff)
316#define DBGP_PID_SET(data, tok) (((data)<<8)|(tok))
317 u32 data03;
318 u32 data47;
319 u32 address;
320#define DBGP_EPADDR(dev, ep) (((dev)<<8)|(ep))
321};
322
323#ifdef CONFIG_EARLY_PRINTK_DBGP
324#include <linux/init.h>
325extern int __init early_dbgp_init(char *s);
326extern struct console early_dbgp_console;
327#endif /* CONFIG_EARLY_PRINTK_DBGP */
328
329struct usb_hcd;
330
331static inline int xen_dbgp_reset_prep(struct usb_hcd *hcd)
332{
333 return 1; /* Shouldn't this be 0? */
334}
335
336static inline int xen_dbgp_external_startup(struct usb_hcd *hcd)
337{
338 return -1;
339}
340
341#ifdef CONFIG_EARLY_PRINTK_DBGP
342/* Call backs from fotg210 host driver to fotg210 debug driver */
343extern int dbgp_external_startup(struct usb_hcd *);
344extern int dbgp_reset_prep(struct usb_hcd *hcd);
345#else
346static inline int dbgp_reset_prep(struct usb_hcd *hcd)
347{
348 return xen_dbgp_reset_prep(hcd);
349}
350static inline int dbgp_external_startup(struct usb_hcd *hcd)
351{
352 return xen_dbgp_external_startup(hcd);
353}
354#endif
355
356/*-------------------------------------------------------------------------*/
357
358#define QTD_NEXT(fotg210, dma) cpu_to_hc32(fotg210, (u32)dma)
359
360/*
361 * EHCI Specification 0.95 Section 3.5
362 * QTD: describe data transfer components (buffer, direction, ...)
363 * See Fig 3-6 "Queue Element Transfer Descriptor Block Diagram".
364 *
365 * These are associated only with "QH" (Queue Head) structures,
366 * used with control, bulk, and interrupt transfers.
367 */
368struct fotg210_qtd {
369 /* first part defined by EHCI spec */
370 __hc32 hw_next; /* see EHCI 3.5.1 */
371 __hc32 hw_alt_next; /* see EHCI 3.5.2 */
372 __hc32 hw_token; /* see EHCI 3.5.3 */
373#define QTD_TOGGLE (1 << 31) /* data toggle */
374#define QTD_LENGTH(tok) (((tok)>>16) & 0x7fff)
375#define QTD_IOC (1 << 15) /* interrupt on complete */
376#define QTD_CERR(tok) (((tok)>>10) & 0x3)
377#define QTD_PID(tok) (((tok)>>8) & 0x3)
378#define QTD_STS_ACTIVE (1 << 7) /* HC may execute this */
379#define QTD_STS_HALT (1 << 6) /* halted on error */
380#define QTD_STS_DBE (1 << 5) /* data buffer error (in HC) */
381#define QTD_STS_BABBLE (1 << 4) /* device was babbling (qtd halted) */
382#define QTD_STS_XACT (1 << 3) /* device gave illegal response */
383#define QTD_STS_MMF (1 << 2) /* incomplete split transaction */
384#define QTD_STS_STS (1 << 1) /* split transaction state */
385#define QTD_STS_PING (1 << 0) /* issue PING? */
386
387#define ACTIVE_BIT(fotg210) cpu_to_hc32(fotg210, QTD_STS_ACTIVE)
388#define HALT_BIT(fotg210) cpu_to_hc32(fotg210, QTD_STS_HALT)
389#define STATUS_BIT(fotg210) cpu_to_hc32(fotg210, QTD_STS_STS)
390
391 __hc32 hw_buf[5]; /* see EHCI 3.5.4 */
392 __hc32 hw_buf_hi[5]; /* Appendix B */
393
394 /* the rest is HCD-private */
395 dma_addr_t qtd_dma; /* qtd address */
396 struct list_head qtd_list; /* sw qtd list */
397 struct urb *urb; /* qtd's urb */
398 size_t length; /* length of buffer */
399} __aligned(32);
400
401/* mask NakCnt+T in qh->hw_alt_next */
402#define QTD_MASK(fotg210) cpu_to_hc32(fotg210, ~0x1f)
403
404#define IS_SHORT_READ(token) (QTD_LENGTH(token) != 0 && QTD_PID(token) == 1)
405
406/*-------------------------------------------------------------------------*/
407
408/* type tag from {qh,itd,fstn}->hw_next */
409#define Q_NEXT_TYPE(fotg210, dma) ((dma) & cpu_to_hc32(fotg210, 3 << 1))
410
411/*
412 * Now the following defines are not converted using the
413 * cpu_to_le32() macro anymore, since we have to support
414 * "dynamic" switching between be and le support, so that the driver
415 * can be used on one system with SoC EHCI controller using big-endian
416 * descriptors as well as a normal little-endian PCI EHCI controller.
417 */
418/* values for that type tag */
419#define Q_TYPE_ITD (0 << 1)
420#define Q_TYPE_QH (1 << 1)
421#define Q_TYPE_SITD (2 << 1)
422#define Q_TYPE_FSTN (3 << 1)
423
424/* next async queue entry, or pointer to interrupt/periodic QH */
425#define QH_NEXT(fotg210, dma) \
426 (cpu_to_hc32(fotg210, (((u32)dma)&~0x01f)|Q_TYPE_QH))
427
428/* for periodic/async schedules and qtd lists, mark end of list */
429#define FOTG210_LIST_END(fotg210) \
430 cpu_to_hc32(fotg210, 1) /* "null pointer" to hw */
431
432/*
433 * Entries in periodic shadow table are pointers to one of four kinds
434 * of data structure. That's dictated by the hardware; a type tag is
435 * encoded in the low bits of the hardware's periodic schedule. Use
436 * Q_NEXT_TYPE to get the tag.
437 *
438 * For entries in the async schedule, the type tag always says "qh".
439 */
440union fotg210_shadow {
441 struct fotg210_qh *qh; /* Q_TYPE_QH */
442 struct fotg210_itd *itd; /* Q_TYPE_ITD */
443 struct fotg210_fstn *fstn; /* Q_TYPE_FSTN */
444 __hc32 *hw_next; /* (all types) */
445 void *ptr;
446};
447
448/*-------------------------------------------------------------------------*/
449
450/*
451 * EHCI Specification 0.95 Section 3.6
452 * QH: describes control/bulk/interrupt endpoints
453 * See Fig 3-7 "Queue Head Structure Layout".
454 *
455 * These appear in both the async and (for interrupt) periodic schedules.
456 */
457
458/* first part defined by EHCI spec */
459struct fotg210_qh_hw {
460 __hc32 hw_next; /* see EHCI 3.6.1 */
461 __hc32 hw_info1; /* see EHCI 3.6.2 */
462#define QH_CONTROL_EP (1 << 27) /* FS/LS control endpoint */
463#define QH_HEAD (1 << 15) /* Head of async reclamation list */
464#define QH_TOGGLE_CTL (1 << 14) /* Data toggle control */
465#define QH_HIGH_SPEED (2 << 12) /* Endpoint speed */
466#define QH_LOW_SPEED (1 << 12)
467#define QH_FULL_SPEED (0 << 12)
468#define QH_INACTIVATE (1 << 7) /* Inactivate on next transaction */
469 __hc32 hw_info2; /* see EHCI 3.6.2 */
470#define QH_SMASK 0x000000ff
471#define QH_CMASK 0x0000ff00
472#define QH_HUBADDR 0x007f0000
473#define QH_HUBPORT 0x3f800000
474#define QH_MULT 0xc0000000
475 __hc32 hw_current; /* qtd list - see EHCI 3.6.4 */
476
477 /* qtd overlay (hardware parts of a struct fotg210_qtd) */
478 __hc32 hw_qtd_next;
479 __hc32 hw_alt_next;
480 __hc32 hw_token;
481 __hc32 hw_buf[5];
482 __hc32 hw_buf_hi[5];
483} __aligned(32);
484
485struct fotg210_qh {
486 struct fotg210_qh_hw *hw; /* Must come first */
487 /* the rest is HCD-private */
488 dma_addr_t qh_dma; /* address of qh */
489 union fotg210_shadow qh_next; /* ptr to qh; or periodic */
490 struct list_head qtd_list; /* sw qtd list */
491 struct list_head intr_node; /* list of intr QHs */
492 struct fotg210_qtd *dummy;
493 struct fotg210_qh *unlink_next; /* next on unlink list */
494
495 unsigned unlink_cycle;
496
497 u8 needs_rescan; /* Dequeue during giveback */
498 u8 qh_state;
499#define QH_STATE_LINKED 1 /* HC sees this */
500#define QH_STATE_UNLINK 2 /* HC may still see this */
501#define QH_STATE_IDLE 3 /* HC doesn't see this */
502#define QH_STATE_UNLINK_WAIT 4 /* LINKED and on unlink q */
503#define QH_STATE_COMPLETING 5 /* don't touch token.HALT */
504
505 u8 xacterrs; /* XactErr retry counter */
506#define QH_XACTERR_MAX 32 /* XactErr retry limit */
507
508 /* periodic schedule info */
509 u8 usecs; /* intr bandwidth */
510 u8 gap_uf; /* uframes split/csplit gap */
511 u8 c_usecs; /* ... split completion bw */
512 u16 tt_usecs; /* tt downstream bandwidth */
513 unsigned short period; /* polling interval */
514 unsigned short start; /* where polling starts */
515#define NO_FRAME ((unsigned short)~0) /* pick new start */
516
517 struct usb_device *dev; /* access to TT */
518 unsigned is_out:1; /* bulk or intr OUT */
519 unsigned clearing_tt:1; /* Clear-TT-Buf in progress */
520};
521
522/*-------------------------------------------------------------------------*/
523
524/* description of one iso transaction (up to 3 KB data if highspeed) */
525struct fotg210_iso_packet {
526 /* These will be copied to iTD when scheduling */
527 u64 bufp; /* itd->hw_bufp{,_hi}[pg] |= */
528 __hc32 transaction; /* itd->hw_transaction[i] |= */
529 u8 cross; /* buf crosses pages */
530 /* for full speed OUT splits */
531 u32 buf1;
532};
533
534/* temporary schedule data for packets from iso urbs (both speeds)
535 * each packet is one logical usb transaction to the device (not TT),
536 * beginning at stream->next_uframe
537 */
538struct fotg210_iso_sched {
539 struct list_head td_list;
540 unsigned span;
541 struct fotg210_iso_packet packet[0];
542};
543
544/*
545 * fotg210_iso_stream - groups all (s)itds for this endpoint.
546 * acts like a qh would, if EHCI had them for ISO.
547 */
548struct fotg210_iso_stream {
549 /* first field matches fotg210_hq, but is NULL */
550 struct fotg210_qh_hw *hw;
551
552 u8 bEndpointAddress;
553 u8 highspeed;
554 struct list_head td_list; /* queued itds */
555 struct list_head free_list; /* list of unused itds */
556 struct usb_device *udev;
557 struct usb_host_endpoint *ep;
558
559 /* output of (re)scheduling */
560 int next_uframe;
561 __hc32 splits;
562
563 /* the rest is derived from the endpoint descriptor,
564 * trusting urb->interval == f(epdesc->bInterval) and
565 * including the extra info for hw_bufp[0..2]
566 */
567 u8 usecs, c_usecs;
568 u16 interval;
569 u16 tt_usecs;
570 u16 maxp;
571 u16 raw_mask;
572 unsigned bandwidth;
573
574 /* This is used to initialize iTD's hw_bufp fields */
575 __hc32 buf0;
576 __hc32 buf1;
577 __hc32 buf2;
578
579 /* this is used to initialize sITD's tt info */
580 __hc32 address;
581};
582
583/*-------------------------------------------------------------------------*/
584
585/*
586 * EHCI Specification 0.95 Section 3.3
587 * Fig 3-4 "Isochronous Transaction Descriptor (iTD)"
588 *
589 * Schedule records for high speed iso xfers
590 */
591struct fotg210_itd {
592 /* first part defined by EHCI spec */
593 __hc32 hw_next; /* see EHCI 3.3.1 */
594 __hc32 hw_transaction[8]; /* see EHCI 3.3.2 */
595#define FOTG210_ISOC_ACTIVE (1<<31) /* activate transfer this slot */
596#define FOTG210_ISOC_BUF_ERR (1<<30) /* Data buffer error */
597#define FOTG210_ISOC_BABBLE (1<<29) /* babble detected */
598#define FOTG210_ISOC_XACTERR (1<<28) /* XactErr - transaction error */
599#define FOTG210_ITD_LENGTH(tok) (((tok)>>16) & 0x0fff)
600#define FOTG210_ITD_IOC (1 << 15) /* interrupt on complete */
601
602#define ITD_ACTIVE(fotg210) cpu_to_hc32(fotg210, FOTG210_ISOC_ACTIVE)
603
604 __hc32 hw_bufp[7]; /* see EHCI 3.3.3 */
605 __hc32 hw_bufp_hi[7]; /* Appendix B */
606
607 /* the rest is HCD-private */
608 dma_addr_t itd_dma; /* for this itd */
609 union fotg210_shadow itd_next; /* ptr to periodic q entry */
610
611 struct urb *urb;
612 struct fotg210_iso_stream *stream; /* endpoint's queue */
613 struct list_head itd_list; /* list of stream's itds */
614
615 /* any/all hw_transactions here may be used by that urb */
616 unsigned frame; /* where scheduled */
617 unsigned pg;
618 unsigned index[8]; /* in urb->iso_frame_desc */
619} __aligned(32);
620
621/*-------------------------------------------------------------------------*/
622
623/*
624 * EHCI Specification 0.96 Section 3.7
625 * Periodic Frame Span Traversal Node (FSTN)
626 *
627 * Manages split interrupt transactions (using TT) that span frame boundaries
628 * into uframes 0/1; see 4.12.2.2. In those uframes, a "save place" FSTN
629 * makes the HC jump (back) to a QH to scan for fs/ls QH completions until
630 * it hits a "restore" FSTN; then it returns to finish other uframe 0/1 work.
631 */
632struct fotg210_fstn {
633 __hc32 hw_next; /* any periodic q entry */
634 __hc32 hw_prev; /* qh or FOTG210_LIST_END */
635
636 /* the rest is HCD-private */
637 dma_addr_t fstn_dma;
638 union fotg210_shadow fstn_next; /* ptr to periodic q entry */
639} __aligned(32);
640
641/*-------------------------------------------------------------------------*/
642
643/* Prepare the PORTSC wakeup flags during controller suspend/resume */
644
645#define fotg210_prepare_ports_for_controller_suspend(fotg210, do_wakeup) \
646 fotg210_adjust_port_wakeup_flags(fotg210, true, do_wakeup);
647
648#define fotg210_prepare_ports_for_controller_resume(fotg210) \
649 fotg210_adjust_port_wakeup_flags(fotg210, false, false);
650
651/*-------------------------------------------------------------------------*/
652
653/*
654 * Some EHCI controllers have a Transaction Translator built into the
655 * root hub. This is a non-standard feature. Each controller will need
656 * to add code to the following inline functions, and call them as
657 * needed (mostly in root hub code).
658 */
659
660static inline unsigned int
661fotg210_get_speed(struct fotg210_hcd *fotg210, unsigned int portsc)
662{
663 return (readl(&fotg210->regs->otgcsr)
664 & OTGCSR_HOST_SPD_TYP) >> 22;
665}
666
667/* Returns the speed of a device attached to a port on the root hub. */
668static inline unsigned int
669fotg210_port_speed(struct fotg210_hcd *fotg210, unsigned int portsc)
670{
671 switch (fotg210_get_speed(fotg210, portsc)) {
672 case 0:
673 return 0;
674 case 1:
675 return USB_PORT_STAT_LOW_SPEED;
676 case 2:
677 default:
678 return USB_PORT_STAT_HIGH_SPEED;
679 }
680}
681
682/*-------------------------------------------------------------------------*/
683
684#define fotg210_has_fsl_portno_bug(e) (0)
685
686/*
687 * While most USB host controllers implement their registers in
688 * little-endian format, a minority (celleb companion chip) implement
689 * them in big endian format.
690 *
691 * This attempts to support either format at compile time without a
692 * runtime penalty, or both formats with the additional overhead
693 * of checking a flag bit.
694 *
695 */
696
697#define fotg210_big_endian_mmio(e) 0
698#define fotg210_big_endian_capbase(e) 0
699
700static inline unsigned int fotg210_readl(const struct fotg210_hcd *fotg210,
701 __u32 __iomem *regs)
702{
703 return readl(regs);
704}
705
706static inline void fotg210_writel(const struct fotg210_hcd *fotg210,
707 const unsigned int val, __u32 __iomem *regs)
708{
709 writel(val, regs);
710}
711
712/* cpu to fotg210 */
713static inline __hc32 cpu_to_hc32(const struct fotg210_hcd *fotg210, const u32 x)
714{
715 return cpu_to_le32(x);
716}
717
718/* fotg210 to cpu */
719static inline u32 hc32_to_cpu(const struct fotg210_hcd *fotg210, const __hc32 x)
720{
721 return le32_to_cpu(x);
722}
723
724static inline u32 hc32_to_cpup(const struct fotg210_hcd *fotg210,
725 const __hc32 *x)
726{
727 return le32_to_cpup(x);
728}
729
730/*-------------------------------------------------------------------------*/
731
732static inline unsigned fotg210_read_frame_index(struct fotg210_hcd *fotg210)
733{
734 return fotg210_readl(fotg210, &fotg210->regs->frame_index);
735}
736
737#define fotg210_itdlen(urb, desc, t) ({ \
738 usb_pipein((urb)->pipe) ? \
739 (desc)->length - FOTG210_ITD_LENGTH(t) : \
740 FOTG210_ITD_LENGTH(t); \
741})
742/*-------------------------------------------------------------------------*/
743
744#ifndef DEBUG
745#define STUB_DEBUG_FILES
746#endif /* DEBUG */
747
748/*-------------------------------------------------------------------------*/
749
750#endif /* __LINUX_FOTG210_H */
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-27 02:54:49 -0500