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authorAlan Stern <stern@rowland.harvard.edu>2011-10-12 10:39:14 -0400
committerGreg Kroah-Hartman <gregkh@suse.de>2011-10-18 16:49:33 -0400
commit68aa95d5d4de31c9348c1628ffa85c805305ebc5 (patch)
tree7782dad26b9672be03b78a70cae1105f395dafe2 /drivers/usb/host/ehci-pci.c
parent91960c2ef095c4b0744349e80a933921cbdcfd6e (diff)
EHCI: workaround for MosChip controller bug
This patch (as1489) works around a hardware bug in MosChip EHCI controllers. Evidently when one of these controllers increments the frame-index register, it changes the three low-order bits (the microframe counter) before changing the higher order bits (the frame counter). If the register is read at just the wrong time, the value obtained is too low by 8. When the appropriate quirk flag is set, we work around this problem by reading the frame-index register a second time if the first value's three low-order bits are all 0. This gives the hardware a chance to finish updating the register, yielding the correct value. Signed-off-by: Alan Stern <stern@rowland.harvard.edu> Tested-by: Jason N Pitt <jpitt@fhcrc.org> CC: stable <stable@vger.kernel.org> Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
Diffstat (limited to 'drivers/usb/host/ehci-pci.c')
-rw-r--r--drivers/usb/host/ehci-pci.c5
1 files changed, 5 insertions, 0 deletions
diff --git a/drivers/usb/host/ehci-pci.c b/drivers/usb/host/ehci-pci.c
index 8311de7c0a75..f4b627d343ac 100644
--- a/drivers/usb/host/ehci-pci.c
+++ b/drivers/usb/host/ehci-pci.c
@@ -224,6 +224,11 @@ static int ehci_pci_setup(struct usb_hcd *hcd)
224 pci_dev_put(p_smbus); 224 pci_dev_put(p_smbus);
225 } 225 }
226 break; 226 break;
227 case PCI_VENDOR_ID_NETMOS:
228 /* MosChip frame-index-register bug */
229 ehci_info(ehci, "applying MosChip frame-index workaround\n");
230 ehci->frame_index_bug = 1;
231 break;
227 } 232 }
228 233
229 /* optional debug port, normally in the first BAR */ 234 /* optional debug port, normally in the first BAR */