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authorPeter Tyser <ptyser@xes-inc.com>2011-01-10 18:34:14 -0500
committerGreg Kroah-Hartman <gregkh@suse.de>2011-01-22 21:38:58 -0500
commitcc604ddd118cf4a699c12bc41a5fa2d2f225f702 (patch)
tree6efdd3c28567a7cbdb030a08f1a27b95f88364ce /drivers/usb/host/ehci-fsl.h
parentad84e4a9efb7c8ed322bafb6ebdb9c3a49a3d3a8 (diff)
USB: ehci-fsl: Fix 'have_sysif_regs' detection
Previously a check was done on an ID register at the base of a CPU's internal USB registers to determine if system interface regsiters were present. The check looked for an ID register that had the format ID[0:5] == ~ID[8:13] as described in the MPC5121 User's Manual to determine if a MPC5121 or MPC83xx/85xx was being used. There are two issues with this method: - The ID register is not defined on the MPC83xx/85xx CPUs, so its unclear what is being checked on them. - Newer CPUs such as the P4080 also don't document the ID register, but do share the same format as the MPC5121. Thus the previous code did not set 'have_sysif_regs' properly which results in the P4080 not properly initializing its USB ports. Using the device tree 'compatible' node is a cleaner way to determine if 'have_sysif_regs' should be set and resolves the USB initialization issue seen on the P4080. Tested on a P4080-based system and compile tested on mpc512x_defconfig with Freescale EHCI driver enabled. Cc: Anatolij Gustschin <agust@denx.de> Cc: David Brownell <dbrownell@users.sourceforge.net> Cc: Kumar Gala <galak@kernel.crashing.org> Cc: linuxppc-dev@lists.ozlabs.org Signed-off-by: Peter Tyser <ptyser@xes-inc.com> Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
Diffstat (limited to 'drivers/usb/host/ehci-fsl.h')
-rw-r--r--drivers/usb/host/ehci-fsl.h3
1 files changed, 0 insertions, 3 deletions
diff --git a/drivers/usb/host/ehci-fsl.h b/drivers/usb/host/ehci-fsl.h
index 2c8353795226..3fabed33d940 100644
--- a/drivers/usb/host/ehci-fsl.h
+++ b/drivers/usb/host/ehci-fsl.h
@@ -19,9 +19,6 @@
19#define _EHCI_FSL_H 19#define _EHCI_FSL_H
20 20
21/* offsets for the non-ehci registers in the FSL SOC USB controller */ 21/* offsets for the non-ehci registers in the FSL SOC USB controller */
22#define FSL_SOC_USB_ID 0x0
23#define ID_MSK 0x3f
24#define NID_MSK 0x3f00
25#define FSL_SOC_USB_ULPIVP 0x170 22#define FSL_SOC_USB_ULPIVP 0x170
26#define FSL_SOC_USB_PORTSC1 0x184 23#define FSL_SOC_USB_PORTSC1 0x184
27#define PORT_PTS_MSK (3<<30) 24#define PORT_PTS_MSK (3<<30)