diff options
author | Fabio Estevam <fabio.estevam@freescale.com> | 2014-05-14 14:55:03 -0400 |
---|---|---|
committer | Greg Kroah-Hartman <gregkh@linuxfoundation.org> | 2014-05-28 15:36:21 -0400 |
commit | b38cb7d2571197b56cefae8967f9db15c9361113 (patch) | |
tree | 5a5ea6abcfa86082753b9f2272a4dfe990ae1493 /drivers/tty | |
parent | 81bd1eb7af751666ace2f1dadb0b0101401807cd (diff) |
serial: imx: Disable new features of autobaud detection
Bit 7 of UCR3 is described in the i.MX reference manuals (with the exception
of i.MX1) as follows:
ADNIMP: Autobaud Detection Not Improved-. Disables new features of
autobaud detection (See Baud Rate Automatic Detection
Protocol, for more details).
0 Autobaud detection new features selected
1 Keep old autobaud detection mechanism
The "new features" mechanism occasionally cause the receiver to get out of sync
and continuously produce received characters of '\xff'.
In order to reproduce the problem:
$ stty -F /dev/ttymxc0 19200
- Change the terminal baudrate to 19200
- Type in the console and it should look good
- Change the terminal baudrate back to 115200
- Type 'b' in the console, then a stream of garbage characters is seen.
Also rename the bit definition as per the reference manual.
Tested on mx6q, mx6dl, mx6solo and mx53.
Based on a patch from Eric Nelson for U-boot.
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Tested-by: Eric Nelson <eric.nelson@boundarydevices.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Diffstat (limited to 'drivers/tty')
-rw-r--r-- | drivers/tty/serial/imx.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/drivers/tty/serial/imx.c b/drivers/tty/serial/imx.c index 3b6c1a2e25de..392154d13614 100644 --- a/drivers/tty/serial/imx.c +++ b/drivers/tty/serial/imx.c | |||
@@ -116,7 +116,7 @@ | |||
116 | #define UCR3_DSR (1<<10) /* Data set ready */ | 116 | #define UCR3_DSR (1<<10) /* Data set ready */ |
117 | #define UCR3_DCD (1<<9) /* Data carrier detect */ | 117 | #define UCR3_DCD (1<<9) /* Data carrier detect */ |
118 | #define UCR3_RI (1<<8) /* Ring indicator */ | 118 | #define UCR3_RI (1<<8) /* Ring indicator */ |
119 | #define UCR3_TIMEOUTEN (1<<7) /* Timeout interrupt enable */ | 119 | #define UCR3_ADNIMP (1<<7) /* Autobaud Detection Not Improved */ |
120 | #define UCR3_RXDSEN (1<<6) /* Receive status interrupt enable */ | 120 | #define UCR3_RXDSEN (1<<6) /* Receive status interrupt enable */ |
121 | #define UCR3_AIRINTEN (1<<5) /* Async IR wake interrupt enable */ | 121 | #define UCR3_AIRINTEN (1<<5) /* Async IR wake interrupt enable */ |
122 | #define UCR3_AWAKEN (1<<4) /* Async wake interrupt enable */ | 122 | #define UCR3_AWAKEN (1<<4) /* Async wake interrupt enable */ |
@@ -1174,7 +1174,7 @@ static int imx_startup(struct uart_port *port) | |||
1174 | 1174 | ||
1175 | if (!is_imx1_uart(sport)) { | 1175 | if (!is_imx1_uart(sport)) { |
1176 | temp = readl(sport->port.membase + UCR3); | 1176 | temp = readl(sport->port.membase + UCR3); |
1177 | temp |= IMX21_UCR3_RXDMUXSEL; | 1177 | temp |= IMX21_UCR3_RXDMUXSEL | UCR3_ADNIMP; |
1178 | writel(temp, sport->port.membase + UCR3); | 1178 | writel(temp, sport->port.membase + UCR3); |
1179 | } | 1179 | } |
1180 | 1180 | ||