aboutsummaryrefslogtreecommitdiffstats
path: root/drivers/tty
diff options
context:
space:
mode:
authorRob Herring <robh@kernel.org>2014-05-20 15:22:54 -0400
committerRob Herring <robh@kernel.org>2014-05-20 15:22:54 -0400
commit6e87b7030e3ef2c7ad01fcaa1b46d3ebe6c261e7 (patch)
treee01eaf5fcfed6767da9fcfd8f5120ef667c81bb8 /drivers/tty
parenteafd370dfe487facfdef499057f4eac9aa0b4bf5 (diff)
parente26f1db9b8d74617519e50b41749900d0a257406 (diff)
Merge branch 'tty-next' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/tty into for-next
Conflicts: arch/arm64/kernel/early_printk.c
Diffstat (limited to 'drivers/tty')
-rw-r--r--drivers/tty/serial/8250/8250_core.c5
-rw-r--r--drivers/tty/serial/8250/8250_dw.c81
-rw-r--r--drivers/tty/serial/8250/8250_early.c138
-rw-r--r--drivers/tty/serial/8250/Kconfig6
-rw-r--r--drivers/tty/serial/Kconfig47
-rw-r--r--drivers/tty/serial/Makefile5
-rw-r--r--drivers/tty/serial/amba-pl011.c30
-rw-r--r--drivers/tty/serial/earlycon-arm-semihost.c61
-rw-r--r--drivers/tty/serial/earlycon.c144
-rw-r--r--drivers/tty/serial/men_z135_uart.c866
-rw-r--r--drivers/tty/serial/mux.c4
-rw-r--r--drivers/tty/serial/omap-serial.c94
-rw-r--r--drivers/tty/serial/pch_uart.c13
-rw-r--r--drivers/tty/serial/pxa.c5
-rw-r--r--drivers/tty/serial/sc16is7xx.c1280
-rw-r--r--drivers/tty/serial/serial_core.c3
-rw-r--r--drivers/tty/serial/serial_txx9.c5
-rw-r--r--drivers/tty/serial/xilinx_uartps.c1129
18 files changed, 3097 insertions, 819 deletions
diff --git a/drivers/tty/serial/8250/8250_core.c b/drivers/tty/serial/8250/8250_core.c
index 2d4bd3929e50..053c2007b054 100644
--- a/drivers/tty/serial/8250/8250_core.c
+++ b/drivers/tty/serial/8250/8250_core.c
@@ -1926,13 +1926,8 @@ static void serial8250_put_poll_char(struct uart_port *port,
1926 wait_for_xmitr(up, BOTH_EMPTY); 1926 wait_for_xmitr(up, BOTH_EMPTY);
1927 /* 1927 /*
1928 * Send the character out. 1928 * Send the character out.
1929 * If a LF, also do CR...
1930 */ 1929 */
1931 serial_port_out(port, UART_TX, c); 1930 serial_port_out(port, UART_TX, c);
1932 if (c == 10) {
1933 wait_for_xmitr(up, BOTH_EMPTY);
1934 serial_port_out(port, UART_TX, 13);
1935 }
1936 1931
1937 /* 1932 /*
1938 * Finally, wait for transmitter to become empty 1933 * Finally, wait for transmitter to become empty
diff --git a/drivers/tty/serial/8250/8250_dw.c b/drivers/tty/serial/8250/8250_dw.c
index ed3113576740..51b307aab75e 100644
--- a/drivers/tty/serial/8250/8250_dw.c
+++ b/drivers/tty/serial/8250/8250_dw.c
@@ -62,6 +62,70 @@ struct dw8250_data {
62 struct uart_8250_dma dma; 62 struct uart_8250_dma dma;
63}; 63};
64 64
65struct dw8250_acpi_desc {
66 void (*set_termios)(struct uart_port *p, struct ktermios *termios,
67 struct ktermios *old);
68};
69
70#define BYT_PRV_CLK 0x800
71#define BYT_PRV_CLK_EN (1 << 0)
72#define BYT_PRV_CLK_M_VAL_SHIFT 1
73#define BYT_PRV_CLK_N_VAL_SHIFT 16
74#define BYT_PRV_CLK_UPDATE (1 << 31)
75
76static void byt_set_termios(struct uart_port *p, struct ktermios *termios,
77 struct ktermios *old)
78{
79 unsigned int baud = tty_termios_baud_rate(termios);
80 unsigned int m, n;
81 u32 reg;
82
83 /*
84 * For baud rates 0.5M, 1M, 1.5M, 2M, 2.5M, 3M, 3.5M and 4M the
85 * dividers must be adjusted.
86 *
87 * uartclk = (m / n) * 100 MHz, where m <= n
88 */
89 switch (baud) {
90 case 500000:
91 case 1000000:
92 case 2000000:
93 case 4000000:
94 m = 64;
95 n = 100;
96 p->uartclk = 64000000;
97 break;
98 case 3500000:
99 m = 56;
100 n = 100;
101 p->uartclk = 56000000;
102 break;
103 case 1500000:
104 case 3000000:
105 m = 48;
106 n = 100;
107 p->uartclk = 48000000;
108 break;
109 case 2500000:
110 m = 40;
111 n = 100;
112 p->uartclk = 40000000;
113 break;
114 default:
115 m = 2304;
116 n = 3125;
117 p->uartclk = 73728000;
118 }
119
120 /* Reset the clock */
121 reg = (m << BYT_PRV_CLK_M_VAL_SHIFT) | (n << BYT_PRV_CLK_N_VAL_SHIFT);
122 writel(reg, p->membase + BYT_PRV_CLK);
123 reg |= BYT_PRV_CLK_EN | BYT_PRV_CLK_UPDATE;
124 writel(reg, p->membase + BYT_PRV_CLK);
125
126 serial8250_do_set_termios(p, termios, old);
127}
128
65static inline int dw8250_modify_msr(struct uart_port *p, int offset, int value) 129static inline int dw8250_modify_msr(struct uart_port *p, int offset, int value)
66{ 130{
67 struct dw8250_data *d = p->private_data; 131 struct dw8250_data *d = p->private_data;
@@ -278,6 +342,7 @@ static int dw8250_probe_acpi(struct uart_8250_port *up,
278{ 342{
279 const struct acpi_device_id *id; 343 const struct acpi_device_id *id;
280 struct uart_port *p = &up->port; 344 struct uart_port *p = &up->port;
345 struct dw8250_acpi_desc *acpi_desc;
281 346
282 dw8250_setup_port(up); 347 dw8250_setup_port(up);
283 348
@@ -290,14 +355,18 @@ static int dw8250_probe_acpi(struct uart_8250_port *up,
290 p->serial_out = dw8250_serial_out32; 355 p->serial_out = dw8250_serial_out32;
291 p->regshift = 2; 356 p->regshift = 2;
292 357
293 if (!p->uartclk)
294 p->uartclk = (unsigned int)id->driver_data;
295
296 up->dma = &data->dma; 358 up->dma = &data->dma;
297 359
298 up->dma->rxconf.src_maxburst = p->fifosize / 4; 360 up->dma->rxconf.src_maxburst = p->fifosize / 4;
299 up->dma->txconf.dst_maxburst = p->fifosize / 4; 361 up->dma->txconf.dst_maxburst = p->fifosize / 4;
300 362
363 acpi_desc = (struct dw8250_acpi_desc *)id->driver_data;
364 if (!acpi_desc)
365 return 0;
366
367 if (acpi_desc->set_termios)
368 p->set_termios = acpi_desc->set_termios;
369
301 return 0; 370 return 0;
302} 371}
303 372
@@ -445,12 +514,16 @@ static const struct of_device_id dw8250_of_match[] = {
445}; 514};
446MODULE_DEVICE_TABLE(of, dw8250_of_match); 515MODULE_DEVICE_TABLE(of, dw8250_of_match);
447 516
517static struct dw8250_acpi_desc byt_8250_desc = {
518 .set_termios = byt_set_termios,
519};
520
448static const struct acpi_device_id dw8250_acpi_match[] = { 521static const struct acpi_device_id dw8250_acpi_match[] = {
449 { "INT33C4", 0 }, 522 { "INT33C4", 0 },
450 { "INT33C5", 0 }, 523 { "INT33C5", 0 },
451 { "INT3434", 0 }, 524 { "INT3434", 0 },
452 { "INT3435", 0 }, 525 { "INT3435", 0 },
453 { "80860F0A", 0 }, 526 { "80860F0A", (kernel_ulong_t)&byt_8250_desc},
454 { }, 527 { },
455}; 528};
456MODULE_DEVICE_TABLE(acpi, dw8250_acpi_match); 529MODULE_DEVICE_TABLE(acpi, dw8250_acpi_match);
diff --git a/drivers/tty/serial/8250/8250_early.c b/drivers/tty/serial/8250/8250_early.c
index c100d6343d50..cfef801a49d4 100644
--- a/drivers/tty/serial/8250/8250_early.c
+++ b/drivers/tty/serial/8250/8250_early.c
@@ -35,18 +35,8 @@
35#include <linux/serial_8250.h> 35#include <linux/serial_8250.h>
36#include <asm/io.h> 36#include <asm/io.h>
37#include <asm/serial.h> 37#include <asm/serial.h>
38#ifdef CONFIG_FIX_EARLYCON_MEM
39#include <asm/pgtable.h>
40#include <asm/fixmap.h>
41#endif
42 38
43struct early_serial8250_device { 39static struct earlycon_device *early_device;
44 struct uart_port port;
45 char options[16]; /* e.g., 115200n8 */
46 unsigned int baud;
47};
48
49static struct early_serial8250_device early_device;
50 40
51unsigned int __weak __init serial8250_early_in(struct uart_port *port, int offset) 41unsigned int __weak __init serial8250_early_in(struct uart_port *port, int offset)
52{ 42{
@@ -100,7 +90,7 @@ static void __init serial_putc(struct uart_port *port, int c)
100static void __init early_serial8250_write(struct console *console, 90static void __init early_serial8250_write(struct console *console,
101 const char *s, unsigned int count) 91 const char *s, unsigned int count)
102{ 92{
103 struct uart_port *port = &early_device.port; 93 struct uart_port *port = &early_device->port;
104 unsigned int ier; 94 unsigned int ier;
105 95
106 /* Save the IER and disable interrupts */ 96 /* Save the IER and disable interrupts */
@@ -129,7 +119,7 @@ static unsigned int __init probe_baud(struct uart_port *port)
129 return (port->uartclk / 16) / quot; 119 return (port->uartclk / 16) / quot;
130} 120}
131 121
132static void __init init_port(struct early_serial8250_device *device) 122static void __init init_port(struct earlycon_device *device)
133{ 123{
134 struct uart_port *port = &device->port; 124 struct uart_port *port = &device->port;
135 unsigned int divisor; 125 unsigned int divisor;
@@ -148,128 +138,42 @@ static void __init init_port(struct early_serial8250_device *device)
148 serial8250_early_out(port, UART_LCR, c & ~UART_LCR_DLAB); 138 serial8250_early_out(port, UART_LCR, c & ~UART_LCR_DLAB);
149} 139}
150 140
151static int __init parse_options(struct early_serial8250_device *device, 141static int __init early_serial8250_setup(struct earlycon_device *device,
152 char *options) 142 const char *options)
153{ 143{
154 struct uart_port *port = &device->port; 144 if (!(device->port.membase || device->port.iobase))
155 int mmio, mmio32, length;
156
157 if (!options)
158 return -ENODEV;
159
160 port->uartclk = BASE_BAUD * 16;
161
162 mmio = !strncmp(options, "mmio,", 5);
163 mmio32 = !strncmp(options, "mmio32,", 7);
164 if (mmio || mmio32) {
165 port->iotype = (mmio ? UPIO_MEM : UPIO_MEM32);
166 port->mapbase = simple_strtoul(options + (mmio ? 5 : 7),
167 &options, 0);
168 if (mmio32)
169 port->regshift = 2;
170#ifdef CONFIG_FIX_EARLYCON_MEM
171 set_fixmap_nocache(FIX_EARLYCON_MEM_BASE,
172 port->mapbase & PAGE_MASK);
173 port->membase =
174 (void __iomem *)__fix_to_virt(FIX_EARLYCON_MEM_BASE);
175 port->membase += port->mapbase & ~PAGE_MASK;
176#else
177 port->membase = ioremap_nocache(port->mapbase, 64);
178 if (!port->membase) {
179 printk(KERN_ERR "%s: Couldn't ioremap 0x%llx\n",
180 __func__,
181 (unsigned long long) port->mapbase);
182 return -ENOMEM;
183 }
184#endif
185 } else if (!strncmp(options, "io,", 3)) {
186 port->iotype = UPIO_PORT;
187 port->iobase = simple_strtoul(options + 3, &options, 0);
188 mmio = 0;
189 } else
190 return -EINVAL;
191
192 options = strchr(options, ',');
193 if (options) {
194 options++;
195 device->baud = simple_strtoul(options, NULL, 0);
196 length = min(strcspn(options, " ") + 1,
197 (size_t)(sizeof(device->options)));
198 strlcpy(device->options, options, length);
199 } else {
200 device->baud = probe_baud(port);
201 snprintf(device->options, sizeof(device->options), "%u",
202 device->baud);
203 }
204
205 if (mmio || mmio32)
206 printk(KERN_INFO
207 "Early serial console at MMIO%s 0x%llx (options '%s')\n",
208 mmio32 ? "32" : "",
209 (unsigned long long)port->mapbase,
210 device->options);
211 else
212 printk(KERN_INFO
213 "Early serial console at I/O port 0x%lx (options '%s')\n",
214 port->iobase,
215 device->options);
216
217 return 0;
218}
219
220static struct console early_serial8250_console __initdata = {
221 .name = "uart",
222 .write = early_serial8250_write,
223 .flags = CON_PRINTBUFFER | CON_BOOT,
224 .index = -1,
225};
226
227static int __init early_serial8250_setup(char *options)
228{
229 struct early_serial8250_device *device = &early_device;
230 int err;
231
232 if (device->port.membase || device->port.iobase)
233 return 0; 145 return 0;
234 146
235 err = parse_options(device, options); 147 if (!device->baud)
236 if (err < 0) 148 device->baud = probe_baud(&device->port);
237 return err;
238 149
239 init_port(device); 150 init_port(device);
151
152 early_device = device;
153 device->con->write = early_serial8250_write;
240 return 0; 154 return 0;
241} 155}
156EARLYCON_DECLARE(uart8250, early_serial8250_setup);
157EARLYCON_DECLARE(uart, early_serial8250_setup);
242 158
243int __init setup_early_serial8250_console(char *cmdline) 159int __init setup_early_serial8250_console(char *cmdline)
244{ 160{
245 char *options; 161 char match[] = "uart8250";
246 int err;
247 162
248 options = strstr(cmdline, "uart8250,"); 163 if (cmdline && cmdline[4] == ',')
249 if (!options) { 164 match[4] = '\0';
250 options = strstr(cmdline, "uart,");
251 if (!options)
252 return 0;
253 }
254 165
255 options = strchr(cmdline, ',') + 1; 166 return setup_earlycon(cmdline, match, early_serial8250_setup);
256 err = early_serial8250_setup(options);
257 if (err < 0)
258 return err;
259
260 register_console(&early_serial8250_console);
261
262 return 0;
263} 167}
264 168
265int serial8250_find_port_for_earlycon(void) 169int serial8250_find_port_for_earlycon(void)
266{ 170{
267 struct early_serial8250_device *device = &early_device; 171 struct earlycon_device *device = early_device;
268 struct uart_port *port = &device->port; 172 struct uart_port *port = device ? &device->port : NULL;
269 int line; 173 int line;
270 int ret; 174 int ret;
271 175
272 if (!device->port.membase && !device->port.iobase) 176 if (!port || (!port->membase && !port->iobase))
273 return -ENODEV; 177 return -ENODEV;
274 178
275 line = serial8250_find_port(port); 179 line = serial8250_find_port(port);
@@ -284,5 +188,3 @@ int serial8250_find_port_for_earlycon(void)
284 188
285 return ret; 189 return ret;
286} 190}
287
288early_param("earlycon", setup_early_serial8250_console);
diff --git a/drivers/tty/serial/8250/Kconfig b/drivers/tty/serial/8250/Kconfig
index 23329918f229..349ee598b34c 100644
--- a/drivers/tty/serial/8250/Kconfig
+++ b/drivers/tty/serial/8250/Kconfig
@@ -61,6 +61,7 @@ config SERIAL_8250_CONSOLE
61 bool "Console on 8250/16550 and compatible serial port" 61 bool "Console on 8250/16550 and compatible serial port"
62 depends on SERIAL_8250=y 62 depends on SERIAL_8250=y
63 select SERIAL_CORE_CONSOLE 63 select SERIAL_CORE_CONSOLE
64 select SERIAL_EARLYCON
64 ---help--- 65 ---help---
65 If you say Y here, it will be possible to use a serial port as the 66 If you say Y here, it will be possible to use a serial port as the
66 system console (the system console is the device which receives all 67 system console (the system console is the device which receives all
@@ -90,11 +91,6 @@ config SERIAL_8250_CONSOLE
90 91
91 If unsure, say N. 92 If unsure, say N.
92 93
93config FIX_EARLYCON_MEM
94 bool
95 depends on X86
96 default y
97
98config SERIAL_8250_GSC 94config SERIAL_8250_GSC
99 tristate 95 tristate
100 depends on SERIAL_8250 && GSC 96 depends on SERIAL_8250 && GSC
diff --git a/drivers/tty/serial/Kconfig b/drivers/tty/serial/Kconfig
index 5d9b01aa54f4..64c565945ac3 100644
--- a/drivers/tty/serial/Kconfig
+++ b/drivers/tty/serial/Kconfig
@@ -7,6 +7,13 @@ if TTY
7menu "Serial drivers" 7menu "Serial drivers"
8 depends on HAS_IOMEM 8 depends on HAS_IOMEM
9 9
10config SERIAL_EARLYCON
11 bool
12 help
13 Support for early consoles with the earlycon parameter. This enables
14 the console before standard serial driver is probed. The console is
15 enabled when early_param is processed.
16
10source "drivers/tty/serial/8250/Kconfig" 17source "drivers/tty/serial/8250/Kconfig"
11 18
12comment "Non-8250 serial port support" 19comment "Non-8250 serial port support"
@@ -53,6 +60,7 @@ config SERIAL_AMBA_PL011_CONSOLE
53 bool "Support for console on AMBA serial port" 60 bool "Support for console on AMBA serial port"
54 depends on SERIAL_AMBA_PL011=y 61 depends on SERIAL_AMBA_PL011=y
55 select SERIAL_CORE_CONSOLE 62 select SERIAL_CORE_CONSOLE
63 select SERIAL_EARLYCON
56 ---help--- 64 ---help---
57 Say Y here if you wish to use an AMBA PrimeCell UART as the system 65 Say Y here if you wish to use an AMBA PrimeCell UART as the system
58 console (the system console is the device which receives all kernel 66 console (the system console is the device which receives all kernel
@@ -65,6 +73,16 @@ config SERIAL_AMBA_PL011_CONSOLE
65 your boot loader (lilo or loadlin) about how to pass options to the 73 your boot loader (lilo or loadlin) about how to pass options to the
66 kernel at boot time.) 74 kernel at boot time.)
67 75
76config SERIAL_EARLYCON_ARM_SEMIHOST
77 bool "Early console using ARM semihosting"
78 depends on ARM64 || ARM
79 select SERIAL_EARLYCON
80 help
81 Support for early debug console using ARM semihosting. This enables
82 the console before standard serial driver is probed. This is enabled
83 with "earlycon=smh" on the kernel command line. The console is
84 enabled when early_param is processed.
85
68config SERIAL_SB1250_DUART 86config SERIAL_SB1250_DUART
69 tristate "BCM1xxx on-chip DUART serial support" 87 tristate "BCM1xxx on-chip DUART serial support"
70 depends on SIBYTE_SB1xxx_SOC=y 88 depends on SIBYTE_SB1xxx_SOC=y
@@ -1160,6 +1178,16 @@ config SERIAL_SCCNXP_CONSOLE
1160 help 1178 help
1161 Support for console on SCCNXP serial ports. 1179 Support for console on SCCNXP serial ports.
1162 1180
1181config SERIAL_SC16IS7XX
1182 tristate "SC16IS7xx serial support"
1183 depends on I2C
1184 select SERIAL_CORE
1185 select REGMAP_I2C if I2C
1186 help
1187 This selects support for SC16IS7xx serial ports.
1188 Supported ICs are SC16IS740, SC16IS741, SC16IS750, SC16IS752,
1189 SC16IS760 and SC16IS762.
1190
1163config SERIAL_BFIN_SPORT 1191config SERIAL_BFIN_SPORT
1164 tristate "Blackfin SPORT emulate UART" 1192 tristate "Blackfin SPORT emulate UART"
1165 depends on BLACKFIN 1193 depends on BLACKFIN
@@ -1369,18 +1397,19 @@ config SERIAL_MXS_AUART_CONSOLE
1369 Enable a MXS AUART port to be the system console. 1397 Enable a MXS AUART port to be the system console.
1370 1398
1371config SERIAL_XILINX_PS_UART 1399config SERIAL_XILINX_PS_UART
1372 tristate "Xilinx PS UART support" 1400 tristate "Cadence (Xilinx Zynq) UART support"
1373 depends on OF 1401 depends on OF
1374 select SERIAL_CORE 1402 select SERIAL_CORE
1375 help 1403 help
1376 This driver supports the Xilinx PS UART port. 1404 This driver supports the Cadence UART. It is found e.g. in Xilinx
1405 Zynq.
1377 1406
1378config SERIAL_XILINX_PS_UART_CONSOLE 1407config SERIAL_XILINX_PS_UART_CONSOLE
1379 bool "Xilinx PS UART console support" 1408 bool "Cadence UART console support"
1380 depends on SERIAL_XILINX_PS_UART=y 1409 depends on SERIAL_XILINX_PS_UART=y
1381 select SERIAL_CORE_CONSOLE 1410 select SERIAL_CORE_CONSOLE
1382 help 1411 help
1383 Enable a Xilinx PS UART port to be the system console. 1412 Enable a Cadence UART port to be the system console.
1384 1413
1385config SERIAL_AR933X 1414config SERIAL_AR933X
1386 tristate "AR933X serial port support" 1415 tristate "AR933X serial port support"
@@ -1508,6 +1537,16 @@ config SERIAL_ST_ASC_CONSOLE
1508 depends on SERIAL_ST_ASC=y 1537 depends on SERIAL_ST_ASC=y
1509 select SERIAL_CORE_CONSOLE 1538 select SERIAL_CORE_CONSOLE
1510 1539
1540config SERIAL_MEN_Z135
1541 tristate "MEN 16z135 Support"
1542 depends on MCB
1543 help
1544 Say yes here to enable support for the MEN 16z135 High Speed UART IP-Core
1545 on a MCB carrier.
1546
1547 This driver can also be build as a module. If so, the module will be called
1548 men_z135_uart.ko
1549
1511endmenu 1550endmenu
1512 1551
1513endif # TTY 1552endif # TTY
diff --git a/drivers/tty/serial/Makefile b/drivers/tty/serial/Makefile
index 3680854fef41..712732b43917 100644
--- a/drivers/tty/serial/Makefile
+++ b/drivers/tty/serial/Makefile
@@ -5,6 +5,9 @@
5obj-$(CONFIG_SERIAL_CORE) += serial_core.o 5obj-$(CONFIG_SERIAL_CORE) += serial_core.o
6obj-$(CONFIG_SERIAL_21285) += 21285.o 6obj-$(CONFIG_SERIAL_21285) += 21285.o
7 7
8obj-$(CONFIG_SERIAL_EARLYCON) += earlycon.o
9obj-$(CONFIG_SERIAL_EARLYCON_ARM_SEMIHOST) += earlycon-arm-semihost.o
10
8# These Sparc drivers have to appear before others such as 8250 11# These Sparc drivers have to appear before others such as 8250
9# which share ttySx minor node space. Otherwise console device 12# which share ttySx minor node space. Otherwise console device
10# names change and other unplesantries. 13# names change and other unplesantries.
@@ -48,6 +51,7 @@ obj-$(CONFIG_SERIAL_MPSC) += mpsc.o
48obj-$(CONFIG_SERIAL_SB1250_DUART) += sb1250-duart.o 51obj-$(CONFIG_SERIAL_SB1250_DUART) += sb1250-duart.o
49obj-$(CONFIG_ETRAX_SERIAL) += crisv10.o 52obj-$(CONFIG_ETRAX_SERIAL) += crisv10.o
50obj-$(CONFIG_SERIAL_SCCNXP) += sccnxp.o 53obj-$(CONFIG_SERIAL_SCCNXP) += sccnxp.o
54obj-$(CONFIG_SERIAL_SC16IS7XX) += sc16is7xx.o
51obj-$(CONFIG_SERIAL_JSM) += jsm/ 55obj-$(CONFIG_SERIAL_JSM) += jsm/
52obj-$(CONFIG_SERIAL_TXX9) += serial_txx9.o 56obj-$(CONFIG_SERIAL_TXX9) += serial_txx9.o
53obj-$(CONFIG_SERIAL_VR41XX) += vr41xx_siu.o 57obj-$(CONFIG_SERIAL_VR41XX) += vr41xx_siu.o
@@ -87,3 +91,4 @@ obj-$(CONFIG_SERIAL_EFM32_UART) += efm32-uart.o
87obj-$(CONFIG_SERIAL_ARC) += arc_uart.o 91obj-$(CONFIG_SERIAL_ARC) += arc_uart.o
88obj-$(CONFIG_SERIAL_RP2) += rp2.o 92obj-$(CONFIG_SERIAL_RP2) += rp2.o
89obj-$(CONFIG_SERIAL_FSL_LPUART) += fsl_lpuart.o 93obj-$(CONFIG_SERIAL_FSL_LPUART) += fsl_lpuart.o
94obj-$(CONFIG_SERIAL_MEN_Z135) += men_z135_uart.o
diff --git a/drivers/tty/serial/amba-pl011.c b/drivers/tty/serial/amba-pl011.c
index dacf0a09ab24..ee3d80346780 100644
--- a/drivers/tty/serial/amba-pl011.c
+++ b/drivers/tty/serial/amba-pl011.c
@@ -303,7 +303,7 @@ static void pl011_dma_probe_initcall(struct device *dev, struct uart_amba_port *
303 303
304 /* Optionally make use of an RX channel as well */ 304 /* Optionally make use of an RX channel as well */
305 chan = dma_request_slave_channel(dev, "rx"); 305 chan = dma_request_slave_channel(dev, "rx");
306 306
307 if (!chan && plat->dma_rx_param) { 307 if (!chan && plat->dma_rx_param) {
308 chan = dma_request_channel(mask, plat->dma_filter, plat->dma_rx_param); 308 chan = dma_request_channel(mask, plat->dma_filter, plat->dma_rx_param);
309 309
@@ -2045,6 +2045,34 @@ static struct console amba_console = {
2045}; 2045};
2046 2046
2047#define AMBA_CONSOLE (&amba_console) 2047#define AMBA_CONSOLE (&amba_console)
2048
2049static void pl011_putc(struct uart_port *port, int c)
2050{
2051 while (readl(port->membase + UART01x_FR) & UART01x_FR_TXFF)
2052 ;
2053 writeb(c, port->membase + UART01x_DR);
2054 while (readl(port->membase + UART01x_FR) & UART01x_FR_BUSY)
2055 ;
2056}
2057
2058static void pl011_early_write(struct console *con, const char *s, unsigned n)
2059{
2060 struct earlycon_device *dev = con->data;
2061
2062 uart_console_write(&dev->port, s, n, pl011_putc);
2063}
2064
2065static int __init pl011_early_console_setup(struct earlycon_device *device,
2066 const char *opt)
2067{
2068 if (!device->port.membase)
2069 return -ENODEV;
2070
2071 device->con->write = pl011_early_write;
2072 return 0;
2073}
2074EARLYCON_DECLARE(pl011, pl011_early_console_setup);
2075
2048#else 2076#else
2049#define AMBA_CONSOLE NULL 2077#define AMBA_CONSOLE NULL
2050#endif 2078#endif
diff --git a/drivers/tty/serial/earlycon-arm-semihost.c b/drivers/tty/serial/earlycon-arm-semihost.c
new file mode 100644
index 000000000000..383db10fbb49
--- /dev/null
+++ b/drivers/tty/serial/earlycon-arm-semihost.c
@@ -0,0 +1,61 @@
1/*
2 * Copyright (C) 2012 ARM Ltd.
3 * Author: Marc Zyngier <marc.zyngier@arm.com>
4 *
5 * Adapted for ARM and earlycon:
6 * Copyright (C) 2014 Linaro Ltd.
7 * Author: Rob Herring <robh@kernel.org>
8 *
9 * This program is free software: you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program. If not, see <http://www.gnu.org/licenses/>.
20 */
21#include <linux/kernel.h>
22#include <linux/console.h>
23#include <linux/init.h>
24#include <linux/serial_core.h>
25
26#ifdef CONFIG_THUMB2_KERNEL
27#define SEMIHOST_SWI "0xab"
28#else
29#define SEMIHOST_SWI "0x123456"
30#endif
31
32/*
33 * Semihosting-based debug console
34 */
35static void smh_putc(struct uart_port *port, int c)
36{
37#ifdef CONFIG_ARM64
38 asm volatile("mov x1, %0\n"
39 "mov x0, #3\n"
40 "hlt 0xf000\n"
41 : : "r" (&c) : "x0", "x1", "memory");
42#else
43 asm volatile("mov r1, %0\n"
44 "mov r0, #3\n"
45 "svc " SEMIHOST_SWI "\n"
46 : : "r" (&c) : "r0", "r1", "memory");
47#endif
48}
49
50static void smh_write(struct console *con, const char *s, unsigned n)
51{
52 struct earlycon_device *dev = con->data;
53 uart_console_write(&dev->port, s, n, smh_putc);
54}
55
56int __init early_smh_setup(struct earlycon_device *device, const char *opt)
57{
58 device->con->write = smh_write;
59 return 0;
60}
61EARLYCON_DECLARE(smh, early_smh_setup);
diff --git a/drivers/tty/serial/earlycon.c b/drivers/tty/serial/earlycon.c
new file mode 100644
index 000000000000..c92e83088adb
--- /dev/null
+++ b/drivers/tty/serial/earlycon.c
@@ -0,0 +1,144 @@
1/*
2 * Copyright (C) 2014 Linaro Ltd.
3 * Author: Rob Herring <robh@kernel.org>
4 *
5 * Based on 8250 earlycon:
6 * (c) Copyright 2004 Hewlett-Packard Development Company, L.P.
7 * Bjorn Helgaas <bjorn.helgaas@hp.com>
8 *
9 * This program is free software: you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12 */
13#include <linux/console.h>
14#include <linux/kernel.h>
15#include <linux/init.h>
16#include <linux/io.h>
17#include <linux/serial_core.h>
18
19#ifdef CONFIG_FIX_EARLYCON_MEM
20#include <asm/fixmap.h>
21#endif
22
23#include <asm/serial.h>
24
25static struct console early_con = {
26 .name = "earlycon",
27 .flags = CON_PRINTBUFFER | CON_BOOT,
28 .index = -1,
29};
30
31static struct earlycon_device early_console_dev = {
32 .con = &early_con,
33};
34
35static void __iomem * __init earlycon_map(unsigned long paddr, size_t size)
36{
37 void __iomem *base;
38#ifdef CONFIG_FIX_EARLYCON_MEM
39 set_fixmap_io(FIX_EARLYCON_MEM_BASE, paddr & PAGE_MASK);
40 base = (void __iomem *)__fix_to_virt(FIX_EARLYCON_MEM_BASE);
41 base += paddr & ~PAGE_MASK;
42#else
43 base = ioremap(paddr, size);
44#endif
45 if (!base)
46 pr_err("%s: Couldn't map 0x%llx\n", __func__,
47 (unsigned long long)paddr);
48
49 return base;
50}
51
52static int __init parse_options(struct earlycon_device *device,
53 char *options)
54{
55 struct uart_port *port = &device->port;
56 int mmio, mmio32, length;
57 unsigned long addr;
58
59 if (!options)
60 return -ENODEV;
61
62 mmio = !strncmp(options, "mmio,", 5);
63 mmio32 = !strncmp(options, "mmio32,", 7);
64 if (mmio || mmio32) {
65 port->iotype = (mmio ? UPIO_MEM : UPIO_MEM32);
66 options += mmio ? 5 : 7;
67 addr = simple_strtoul(options, NULL, 0);
68 port->mapbase = addr;
69 if (mmio32)
70 port->regshift = 2;
71 } else if (!strncmp(options, "io,", 3)) {
72 port->iotype = UPIO_PORT;
73 options += 3;
74 addr = simple_strtoul(options, NULL, 0);
75 port->iobase = addr;
76 mmio = 0;
77 } else if (!strncmp(options, "0x", 2)) {
78 port->iotype = UPIO_MEM;
79 addr = simple_strtoul(options, NULL, 0);
80 port->mapbase = addr;
81 } else {
82 return -EINVAL;
83 }
84
85 port->uartclk = BASE_BAUD * 16;
86
87 options = strchr(options, ',');
88 if (options) {
89 options++;
90 device->baud = simple_strtoul(options, NULL, 0);
91 length = min(strcspn(options, " ") + 1,
92 (size_t)(sizeof(device->options)));
93 strlcpy(device->options, options, length);
94 }
95
96 if (mmio || mmio32)
97 pr_info("Early serial console at MMIO%s 0x%llx (options '%s')\n",
98 mmio32 ? "32" : "",
99 (unsigned long long)port->mapbase,
100 device->options);
101 else
102 pr_info("Early serial console at I/O port 0x%lx (options '%s')\n",
103 port->iobase,
104 device->options);
105
106 return 0;
107}
108
109int __init setup_earlycon(char *buf, const char *match,
110 int (*setup)(struct earlycon_device *, const char *))
111{
112 int err;
113 size_t len;
114 struct uart_port *port = &early_console_dev.port;
115
116 if (!buf || !match || !setup)
117 return 0;
118
119 len = strlen(match);
120 if (strncmp(buf, match, len))
121 return 0;
122 if (buf[len] && (buf[len] != ','))
123 return 0;
124
125 buf += len + 1;
126
127 err = parse_options(&early_console_dev, buf);
128 /* On parsing error, pass the options buf to the setup function */
129 if (!err)
130 buf = NULL;
131
132 if (port->mapbase)
133 port->membase = earlycon_map(port->mapbase, 64);
134
135 early_console_dev.con->data = &early_console_dev;
136 err = setup(&early_console_dev, buf);
137 if (err < 0)
138 return err;
139 if (!early_console_dev.con->write)
140 return -ENODEV;
141
142 register_console(early_console_dev.con);
143 return 0;
144}
diff --git a/drivers/tty/serial/men_z135_uart.c b/drivers/tty/serial/men_z135_uart.c
new file mode 100644
index 000000000000..d08eb5d8330d
--- /dev/null
+++ b/drivers/tty/serial/men_z135_uart.c
@@ -0,0 +1,866 @@
1/*
2 * MEN 16z135 High Speed UART
3 *
4 * Copyright (C) 2014 MEN Mikroelektronik GmbH (www.men.de)
5 * Author: Johannes Thumshirn <johannes.thumshirn@men.de>
6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License as published by the Free
9 * Software Foundation; version 2 of the License.
10 */
11#define pr_fmt(fmt) KBUILD_MODNAME ":" fmt
12
13#include <linux/kernel.h>
14#include <linux/module.h>
15#include <linux/interrupt.h>
16#include <linux/serial_core.h>
17#include <linux/ioport.h>
18#include <linux/io.h>
19#include <linux/tty_flip.h>
20#include <linux/bitops.h>
21#include <linux/mcb.h>
22
23#define MEN_Z135_MAX_PORTS 12
24#define MEN_Z135_BASECLK 29491200
25#define MEN_Z135_FIFO_SIZE 1024
26#define MEN_Z135_NUM_MSI_VECTORS 2
27#define MEN_Z135_FIFO_WATERMARK 1020
28
29#define MEN_Z135_STAT_REG 0x0
30#define MEN_Z135_RX_RAM 0x4
31#define MEN_Z135_TX_RAM 0x400
32#define MEN_Z135_RX_CTRL 0x800
33#define MEN_Z135_TX_CTRL 0x804
34#define MEN_Z135_CONF_REG 0x808
35#define MEN_Z135_UART_FREQ 0x80c
36#define MEN_Z135_BAUD_REG 0x810
37#define MENZ135_TIMEOUT 0x814
38
39#define MEN_Z135_MEM_SIZE 0x818
40
41#define IS_IRQ(x) ((x) & 1)
42#define IRQ_ID(x) (((x) >> 1) & 7)
43
44#define MEN_Z135_IER_RXCIEN BIT(0) /* TX Space IRQ */
45#define MEN_Z135_IER_TXCIEN BIT(1) /* RX Space IRQ */
46#define MEN_Z135_IER_RLSIEN BIT(2) /* Receiver Line Status IRQ */
47#define MEN_Z135_IER_MSIEN BIT(3) /* Modem Status IRQ */
48#define MEN_Z135_ALL_IRQS (MEN_Z135_IER_RXCIEN \
49 | MEN_Z135_IER_RLSIEN \
50 | MEN_Z135_IER_MSIEN \
51 | MEN_Z135_IER_TXCIEN)
52
53#define MEN_Z135_MCR_DTR BIT(24)
54#define MEN_Z135_MCR_RTS BIT(25)
55#define MEN_Z135_MCR_OUT1 BIT(26)
56#define MEN_Z135_MCR_OUT2 BIT(27)
57#define MEN_Z135_MCR_LOOP BIT(28)
58#define MEN_Z135_MCR_RCFC BIT(29)
59
60#define MEN_Z135_MSR_DCTS BIT(0)
61#define MEN_Z135_MSR_DDSR BIT(1)
62#define MEN_Z135_MSR_DRI BIT(2)
63#define MEN_Z135_MSR_DDCD BIT(3)
64#define MEN_Z135_MSR_CTS BIT(4)
65#define MEN_Z135_MSR_DSR BIT(5)
66#define MEN_Z135_MSR_RI BIT(6)
67#define MEN_Z135_MSR_DCD BIT(7)
68
69#define MEN_Z135_LCR_SHIFT 8 /* LCR shift mask */
70
71#define MEN_Z135_WL5 0 /* CS5 */
72#define MEN_Z135_WL6 1 /* CS6 */
73#define MEN_Z135_WL7 2 /* CS7 */
74#define MEN_Z135_WL8 3 /* CS8 */
75
76#define MEN_Z135_STB_SHIFT 2 /* Stopbits */
77#define MEN_Z135_NSTB1 0
78#define MEN_Z135_NSTB2 1
79
80#define MEN_Z135_PEN_SHIFT 3 /* Parity enable */
81#define MEN_Z135_PAR_DIS 0
82#define MEN_Z135_PAR_ENA 1
83
84#define MEN_Z135_PTY_SHIFT 4 /* Parity type */
85#define MEN_Z135_PTY_ODD 0
86#define MEN_Z135_PTY_EVN 1
87
88#define MEN_Z135_LSR_DR BIT(0)
89#define MEN_Z135_LSR_OE BIT(1)
90#define MEN_Z135_LSR_PE BIT(2)
91#define MEN_Z135_LSR_FE BIT(3)
92#define MEN_Z135_LSR_BI BIT(4)
93#define MEN_Z135_LSR_THEP BIT(5)
94#define MEN_Z135_LSR_TEXP BIT(6)
95#define MEN_Z135_LSR_RXFIFOERR BIT(7)
96
97#define MEN_Z135_IRQ_ID_MST 0
98#define MEN_Z135_IRQ_ID_TSA 1
99#define MEN_Z135_IRQ_ID_RDA 2
100#define MEN_Z135_IRQ_ID_RLS 3
101#define MEN_Z135_IRQ_ID_CTI 6
102
103#define LCR(x) (((x) >> MEN_Z135_LCR_SHIFT) & 0xff)
104
105#define BYTES_TO_ALIGN(x) ((x) & 0x3)
106
107static int line;
108
109static int txlvl = 5;
110module_param(txlvl, int, S_IRUGO);
111MODULE_PARM_DESC(txlvl, "TX IRQ trigger level 0-7, default 5 (128 byte)");
112
113static int rxlvl = 6;
114module_param(rxlvl, int, S_IRUGO);
115MODULE_PARM_DESC(rxlvl, "RX IRQ trigger level 0-7, default 6 (256 byte)");
116
117static int align;
118module_param(align, int, S_IRUGO);
119MODULE_PARM_DESC(align, "Keep hardware FIFO write pointer aligned, default 0");
120
121struct men_z135_port {
122 struct uart_port port;
123 struct mcb_device *mdev;
124 unsigned char *rxbuf;
125 u32 stat_reg;
126 spinlock_t lock;
127};
128#define to_men_z135(port) container_of((port), struct men_z135_port, port)
129
130/**
131 * men_z135_reg_set() - Set value in register
132 * @uart: The UART port
133 * @addr: Register address
134 * @val: value to set
135 */
136static inline void men_z135_reg_set(struct men_z135_port *uart,
137 u32 addr, u32 val)
138{
139 struct uart_port *port = &uart->port;
140 unsigned long flags;
141 u32 reg;
142
143 spin_lock_irqsave(&uart->lock, flags);
144
145 reg = ioread32(port->membase + addr);
146 reg |= val;
147 iowrite32(reg, port->membase + addr);
148
149 spin_unlock_irqrestore(&uart->lock, flags);
150}
151
152/**
153 * men_z135_reg_clr() - Unset value in register
154 * @uart: The UART port
155 * @addr: Register address
156 * @val: value to clear
157 */
158static inline void men_z135_reg_clr(struct men_z135_port *uart,
159 u32 addr, u32 val)
160{
161 struct uart_port *port = &uart->port;
162 unsigned long flags;
163 u32 reg;
164
165 spin_lock_irqsave(&uart->lock, flags);
166
167 reg = ioread32(port->membase + addr);
168 reg &= ~val;
169 iowrite32(reg, port->membase + addr);
170
171 spin_unlock_irqrestore(&uart->lock, flags);
172}
173
174/**
175 * men_z135_handle_modem_status() - Handle change of modem status
176 * @port: The UART port
177 *
178 * Handle change of modem status register. This is done by reading the "delta"
179 * versions of DCD (Data Carrier Detect) and CTS (Clear To Send).
180 */
181static void men_z135_handle_modem_status(struct men_z135_port *uart)
182{
183 if (uart->stat_reg & MEN_Z135_MSR_DDCD)
184 uart_handle_dcd_change(&uart->port,
185 uart->stat_reg & ~MEN_Z135_MSR_DCD);
186 if (uart->stat_reg & MEN_Z135_MSR_DCTS)
187 uart_handle_cts_change(&uart->port,
188 uart->stat_reg & ~MEN_Z135_MSR_CTS);
189}
190
191static void men_z135_handle_lsr(struct men_z135_port *uart)
192{
193 struct uart_port *port = &uart->port;
194 u8 lsr;
195
196 lsr = (uart->stat_reg >> 16) & 0xff;
197
198 if (lsr & MEN_Z135_LSR_OE)
199 port->icount.overrun++;
200 if (lsr & MEN_Z135_LSR_PE)
201 port->icount.parity++;
202 if (lsr & MEN_Z135_LSR_FE)
203 port->icount.frame++;
204 if (lsr & MEN_Z135_LSR_BI) {
205 port->icount.brk++;
206 uart_handle_break(port);
207 }
208}
209
210/**
211 * get_rx_fifo_content() - Get the number of bytes in RX FIFO
212 * @uart: The UART port
213 *
214 * Read RXC register from hardware and return current FIFO fill size.
215 */
216static u16 get_rx_fifo_content(struct men_z135_port *uart)
217{
218 struct uart_port *port = &uart->port;
219 u32 stat_reg;
220 u16 rxc;
221 u8 rxc_lo;
222 u8 rxc_hi;
223
224 stat_reg = ioread32(port->membase + MEN_Z135_STAT_REG);
225 rxc_lo = stat_reg >> 24;
226 rxc_hi = (stat_reg & 0xC0) >> 6;
227
228 rxc = rxc_lo | (rxc_hi << 8);
229
230 return rxc;
231}
232
233/**
234 * men_z135_handle_rx() - RX tasklet routine
235 * @arg: Pointer to struct men_z135_port
236 *
237 * Copy from RX FIFO and acknowledge number of bytes copied.
238 */
239static void men_z135_handle_rx(struct men_z135_port *uart)
240{
241 struct uart_port *port = &uart->port;
242 struct tty_port *tport = &port->state->port;
243 int copied;
244 u16 size;
245 int room;
246
247 size = get_rx_fifo_content(uart);
248
249 if (size == 0)
250 return;
251
252 /* Avoid accidently accessing TX FIFO instead of RX FIFO. Last
253 * longword in RX FIFO cannot be read.(0x004-0x3FF)
254 */
255 if (size > MEN_Z135_FIFO_WATERMARK)
256 size = MEN_Z135_FIFO_WATERMARK;
257
258 room = tty_buffer_request_room(tport, size);
259 if (room != size)
260 dev_warn(&uart->mdev->dev,
261 "Not enough room in flip buffer, truncating to %d\n",
262 room);
263
264 if (room == 0)
265 return;
266
267 memcpy_fromio(uart->rxbuf, port->membase + MEN_Z135_RX_RAM, room);
268 /* Be sure to first copy all data and then acknowledge it */
269 mb();
270 iowrite32(room, port->membase + MEN_Z135_RX_CTRL);
271
272 copied = tty_insert_flip_string(tport, uart->rxbuf, room);
273 if (copied != room)
274 dev_warn(&uart->mdev->dev,
275 "Only copied %d instead of %d bytes\n",
276 copied, room);
277
278 port->icount.rx += copied;
279
280 tty_flip_buffer_push(tport);
281
282}
283
284/**
285 * men_z135_handle_tx() - TX tasklet routine
286 * @arg: Pointer to struct men_z135_port
287 *
288 */
289static void men_z135_handle_tx(struct men_z135_port *uart)
290{
291 struct uart_port *port = &uart->port;
292 struct circ_buf *xmit = &port->state->xmit;
293 u32 txc;
294 u32 wptr;
295 int qlen;
296 int n;
297 int txfree;
298 int head;
299 int tail;
300 int s;
301
302 if (uart_circ_empty(xmit))
303 goto out;
304
305 if (uart_tx_stopped(port))
306 goto out;
307
308 if (port->x_char)
309 goto out;
310
311 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
312 uart_write_wakeup(port);
313
314 /* calculate bytes to copy */
315 qlen = uart_circ_chars_pending(xmit);
316 if (qlen <= 0)
317 goto out;
318
319 wptr = ioread32(port->membase + MEN_Z135_TX_CTRL);
320 txc = (wptr >> 16) & 0x3ff;
321 wptr &= 0x3ff;
322
323 if (txc > MEN_Z135_FIFO_WATERMARK)
324 txc = MEN_Z135_FIFO_WATERMARK;
325
326 txfree = MEN_Z135_FIFO_WATERMARK - txc;
327 if (txfree <= 0) {
328 pr_err("Not enough room in TX FIFO have %d, need %d\n",
329 txfree, qlen);
330 goto irq_en;
331 }
332
333 /* if we're not aligned, it's better to copy only 1 or 2 bytes and
334 * then the rest.
335 */
336 if (align && qlen >= 3 && BYTES_TO_ALIGN(wptr))
337 n = 4 - BYTES_TO_ALIGN(wptr);
338 else if (qlen > txfree)
339 n = txfree;
340 else
341 n = qlen;
342
343 if (n <= 0)
344 goto irq_en;
345
346 head = xmit->head & (UART_XMIT_SIZE - 1);
347 tail = xmit->tail & (UART_XMIT_SIZE - 1);
348
349 s = ((head >= tail) ? head : UART_XMIT_SIZE) - tail;
350 n = min(n, s);
351
352 memcpy_toio(port->membase + MEN_Z135_TX_RAM, &xmit->buf[xmit->tail], n);
353 xmit->tail = (xmit->tail + n) & (UART_XMIT_SIZE - 1);
354 mmiowb();
355
356 iowrite32(n & 0x3ff, port->membase + MEN_Z135_TX_CTRL);
357
358 port->icount.tx += n;
359
360irq_en:
361 if (!uart_circ_empty(xmit))
362 men_z135_reg_set(uart, MEN_Z135_CONF_REG, MEN_Z135_IER_TXCIEN);
363 else
364 men_z135_reg_clr(uart, MEN_Z135_CONF_REG, MEN_Z135_IER_TXCIEN);
365
366out:
367 return;
368
369}
370
371/**
372 * men_z135_intr() - Handle legacy IRQs
373 * @irq: The IRQ number
374 * @data: Pointer to UART port
375 *
376 * Check IIR register to see which tasklet to start.
377 */
378static irqreturn_t men_z135_intr(int irq, void *data)
379{
380 struct men_z135_port *uart = (struct men_z135_port *)data;
381 struct uart_port *port = &uart->port;
382 int irq_id;
383
384 uart->stat_reg = ioread32(port->membase + MEN_Z135_STAT_REG);
385 /* IRQ pending is low active */
386 if (IS_IRQ(uart->stat_reg))
387 return IRQ_NONE;
388
389 irq_id = IRQ_ID(uart->stat_reg);
390 switch (irq_id) {
391 case MEN_Z135_IRQ_ID_MST:
392 men_z135_handle_modem_status(uart);
393 break;
394 case MEN_Z135_IRQ_ID_TSA:
395 men_z135_handle_tx(uart);
396 break;
397 case MEN_Z135_IRQ_ID_CTI:
398 dev_dbg(&uart->mdev->dev, "Character Timeout Indication\n");
399 /* Fallthrough */
400 case MEN_Z135_IRQ_ID_RDA:
401 /* Reading data clears RX IRQ */
402 men_z135_handle_rx(uart);
403 break;
404 case MEN_Z135_IRQ_ID_RLS:
405 men_z135_handle_lsr(uart);
406 break;
407 default:
408 dev_warn(&uart->mdev->dev, "Unknown IRQ id %d\n", irq_id);
409 return IRQ_NONE;
410 }
411
412 return IRQ_HANDLED;
413}
414
415/**
416 * men_z135_request_irq() - Request IRQ for 16z135 core
417 * @uart: z135 private uart port structure
418 *
419 * Request an IRQ for 16z135 to use. First try using MSI, if it fails
420 * fall back to using legacy interrupts.
421 */
422static int men_z135_request_irq(struct men_z135_port *uart)
423{
424 struct device *dev = &uart->mdev->dev;
425 struct uart_port *port = &uart->port;
426 int err = 0;
427
428 err = request_irq(port->irq, men_z135_intr, IRQF_SHARED,
429 "men_z135_intr", uart);
430 if (err)
431 dev_err(dev, "Error %d getting interrupt\n", err);
432
433 return err;
434}
435
436/**
437 * men_z135_tx_empty() - Handle tx_empty call
438 * @port: The UART port
439 *
440 * This function tests whether the TX FIFO and shifter for the port
441 * described by @port is empty.
442 */
443static unsigned int men_z135_tx_empty(struct uart_port *port)
444{
445 u32 wptr;
446 u16 txc;
447
448 wptr = ioread32(port->membase + MEN_Z135_TX_CTRL);
449 txc = (wptr >> 16) & 0x3ff;
450
451 if (txc == 0)
452 return TIOCSER_TEMT;
453 else
454 return 0;
455}
456
457/**
458 * men_z135_set_mctrl() - Set modem control lines
459 * @port: The UART port
460 * @mctrl: The modem control lines
461 *
462 * This function sets the modem control lines for a port described by @port
463 * to the state described by @mctrl
464 */
465static void men_z135_set_mctrl(struct uart_port *port, unsigned int mctrl)
466{
467 struct men_z135_port *uart = to_men_z135(port);
468 u32 conf_reg = 0;
469
470 if (mctrl & TIOCM_RTS)
471 conf_reg |= MEN_Z135_MCR_RTS;
472 if (mctrl & TIOCM_DTR)
473 conf_reg |= MEN_Z135_MCR_DTR;
474 if (mctrl & TIOCM_OUT1)
475 conf_reg |= MEN_Z135_MCR_OUT1;
476 if (mctrl & TIOCM_OUT2)
477 conf_reg |= MEN_Z135_MCR_OUT2;
478 if (mctrl & TIOCM_LOOP)
479 conf_reg |= MEN_Z135_MCR_LOOP;
480
481 men_z135_reg_set(uart, MEN_Z135_CONF_REG, conf_reg);
482}
483
484/**
485 * men_z135_get_mctrl() - Get modem control lines
486 * @port: The UART port
487 *
488 * Retruns the current state of modem control inputs.
489 */
490static unsigned int men_z135_get_mctrl(struct uart_port *port)
491{
492 unsigned int mctrl = 0;
493 u32 stat_reg;
494 u8 msr;
495
496 stat_reg = ioread32(port->membase + MEN_Z135_STAT_REG);
497
498 msr = ~((stat_reg >> 8) & 0xff);
499
500 if (msr & MEN_Z135_MSR_CTS)
501 mctrl |= TIOCM_CTS;
502 if (msr & MEN_Z135_MSR_DSR)
503 mctrl |= TIOCM_DSR;
504 if (msr & MEN_Z135_MSR_RI)
505 mctrl |= TIOCM_RI;
506 if (msr & MEN_Z135_MSR_DCD)
507 mctrl |= TIOCM_CAR;
508
509 return mctrl;
510}
511
512/**
513 * men_z135_stop_tx() - Stop transmitting characters
514 * @port: The UART port
515 *
516 * Stop transmitting characters. This might be due to CTS line becomming
517 * inactive or the tty layer indicating we want to stop transmission due to
518 * an XOFF character.
519 */
520static void men_z135_stop_tx(struct uart_port *port)
521{
522 struct men_z135_port *uart = to_men_z135(port);
523
524 men_z135_reg_clr(uart, MEN_Z135_CONF_REG, MEN_Z135_IER_TXCIEN);
525}
526
527/**
528 * men_z135_start_tx() - Start transmitting characters
529 * @port: The UART port
530 *
531 * Start transmitting character. This actually doesn't transmit anything, but
532 * fires off the TX tasklet.
533 */
534static void men_z135_start_tx(struct uart_port *port)
535{
536 struct men_z135_port *uart = to_men_z135(port);
537
538 men_z135_handle_tx(uart);
539}
540
541/**
542 * men_z135_stop_rx() - Stop receiving characters
543 * @port: The UART port
544 *
545 * Stop receiving characters; the port is in the process of being closed.
546 */
547static void men_z135_stop_rx(struct uart_port *port)
548{
549 struct men_z135_port *uart = to_men_z135(port);
550
551 men_z135_reg_clr(uart, MEN_Z135_CONF_REG, MEN_Z135_IER_RXCIEN);
552}
553
554/**
555 * men_z135_enable_ms() - Enable Modem Status
556 * port:
557 *
558 * Enable Modem Status IRQ.
559 */
560static void men_z135_enable_ms(struct uart_port *port)
561{
562 struct men_z135_port *uart = to_men_z135(port);
563
564 men_z135_reg_set(uart, MEN_Z135_CONF_REG, MEN_Z135_IER_MSIEN);
565}
566
567static int men_z135_startup(struct uart_port *port)
568{
569 struct men_z135_port *uart = to_men_z135(port);
570 int err;
571 u32 conf_reg = 0;
572
573 err = men_z135_request_irq(uart);
574 if (err)
575 return -ENODEV;
576
577 conf_reg = ioread32(port->membase + MEN_Z135_CONF_REG);
578
579 conf_reg |= MEN_Z135_ALL_IRQS;
580 conf_reg &= ~(0xff << 16);
581 conf_reg |= (txlvl << 16);
582 conf_reg |= (rxlvl << 20);
583
584 iowrite32(conf_reg, port->membase + MEN_Z135_CONF_REG);
585
586 return 0;
587}
588
589static void men_z135_shutdown(struct uart_port *port)
590{
591 struct men_z135_port *uart = to_men_z135(port);
592 u32 conf_reg = 0;
593
594 conf_reg |= MEN_Z135_ALL_IRQS;
595
596 men_z135_reg_clr(uart, MEN_Z135_CONF_REG, conf_reg);
597
598 free_irq(uart->port.irq, uart);
599}
600
601static void men_z135_set_termios(struct uart_port *port,
602 struct ktermios *termios,
603 struct ktermios *old)
604{
605 unsigned int baud;
606 u32 conf_reg;
607 u32 bd_reg;
608 u32 uart_freq;
609 u8 lcr;
610
611 conf_reg = ioread32(port->membase + MEN_Z135_CONF_REG);
612 lcr = LCR(conf_reg);
613
614 /* byte size */
615 switch (termios->c_cflag & CSIZE) {
616 case CS5:
617 lcr |= MEN_Z135_WL5;
618 break;
619 case CS6:
620 lcr |= MEN_Z135_WL6;
621 break;
622 case CS7:
623 lcr |= MEN_Z135_WL7;
624 break;
625 case CS8:
626 lcr |= MEN_Z135_WL8;
627 break;
628 }
629
630 /* stop bits */
631 if (termios->c_cflag & CSTOPB)
632 lcr |= MEN_Z135_NSTB2 << MEN_Z135_STB_SHIFT;
633
634 /* parity */
635 if (termios->c_cflag & PARENB) {
636 lcr |= MEN_Z135_PAR_ENA << MEN_Z135_PEN_SHIFT;
637
638 if (termios->c_cflag & PARODD)
639 lcr |= MEN_Z135_PTY_ODD << MEN_Z135_PTY_SHIFT;
640 else
641 lcr |= MEN_Z135_PTY_EVN << MEN_Z135_PTY_SHIFT;
642 } else
643 lcr |= MEN_Z135_PAR_DIS << MEN_Z135_PEN_SHIFT;
644
645 termios->c_cflag &= ~CMSPAR; /* Mark/Space parity is not supported */
646
647 conf_reg |= lcr << MEN_Z135_LCR_SHIFT;
648 iowrite32(conf_reg, port->membase + MEN_Z135_CONF_REG);
649
650 uart_freq = ioread32(port->membase + MEN_Z135_UART_FREQ);
651 if (uart_freq == 0)
652 uart_freq = MEN_Z135_BASECLK;
653
654 baud = uart_get_baud_rate(port, termios, old, 0, uart_freq / 16);
655
656 spin_lock(&port->lock);
657 if (tty_termios_baud_rate(termios))
658 tty_termios_encode_baud_rate(termios, baud, baud);
659
660 bd_reg = uart_freq / (4 * baud);
661 iowrite32(bd_reg, port->membase + MEN_Z135_BAUD_REG);
662
663 uart_update_timeout(port, termios->c_cflag, baud);
664 spin_unlock(&port->lock);
665}
666
667static const char *men_z135_type(struct uart_port *port)
668{
669 return KBUILD_MODNAME;
670}
671
672static void men_z135_release_port(struct uart_port *port)
673{
674 iounmap(port->membase);
675 port->membase = NULL;
676
677 release_mem_region(port->mapbase, MEN_Z135_MEM_SIZE);
678}
679
680static int men_z135_request_port(struct uart_port *port)
681{
682 int size = MEN_Z135_MEM_SIZE;
683
684 if (!request_mem_region(port->mapbase, size, "men_z135_port"))
685 return -EBUSY;
686
687 port->membase = ioremap(port->mapbase, MEN_Z135_MEM_SIZE);
688 if (port->membase == NULL) {
689 release_mem_region(port->mapbase, MEN_Z135_MEM_SIZE);
690 return -ENOMEM;
691 }
692
693 return 0;
694}
695
696static void men_z135_config_port(struct uart_port *port, int type)
697{
698 port->type = PORT_MEN_Z135;
699 men_z135_request_port(port);
700}
701
702static int men_z135_verify_port(struct uart_port *port,
703 struct serial_struct *serinfo)
704{
705 return -EINVAL;
706}
707
708static struct uart_ops men_z135_ops = {
709 .tx_empty = men_z135_tx_empty,
710 .set_mctrl = men_z135_set_mctrl,
711 .get_mctrl = men_z135_get_mctrl,
712 .stop_tx = men_z135_stop_tx,
713 .start_tx = men_z135_start_tx,
714 .stop_rx = men_z135_stop_rx,
715 .enable_ms = men_z135_enable_ms,
716 .startup = men_z135_startup,
717 .shutdown = men_z135_shutdown,
718 .set_termios = men_z135_set_termios,
719 .type = men_z135_type,
720 .release_port = men_z135_release_port,
721 .request_port = men_z135_request_port,
722 .config_port = men_z135_config_port,
723 .verify_port = men_z135_verify_port,
724};
725
726static struct uart_driver men_z135_driver = {
727 .owner = THIS_MODULE,
728 .driver_name = KBUILD_MODNAME,
729 .dev_name = "ttyHSU",
730 .major = 0,
731 .minor = 0,
732 .nr = MEN_Z135_MAX_PORTS,
733};
734
735/**
736 * men_z135_probe() - Probe a z135 instance
737 * @mdev: The MCB device
738 * @id: The MCB device ID
739 *
740 * men_z135_probe does the basic setup of hardware resources and registers the
741 * new uart port to the tty layer.
742 */
743static int men_z135_probe(struct mcb_device *mdev,
744 const struct mcb_device_id *id)
745{
746 struct men_z135_port *uart;
747 struct resource *mem;
748 struct device *dev;
749 int err;
750
751 dev = &mdev->dev;
752
753 uart = devm_kzalloc(dev, sizeof(struct men_z135_port), GFP_KERNEL);
754 if (!uart)
755 return -ENOMEM;
756
757 uart->rxbuf = (unsigned char *)__get_free_page(GFP_KERNEL);
758 if (!uart->rxbuf)
759 return -ENOMEM;
760
761 mem = &mdev->mem;
762
763 mcb_set_drvdata(mdev, uart);
764
765 uart->port.uartclk = MEN_Z135_BASECLK * 16;
766 uart->port.fifosize = MEN_Z135_FIFO_SIZE;
767 uart->port.iotype = UPIO_MEM;
768 uart->port.ops = &men_z135_ops;
769 uart->port.irq = mcb_get_irq(mdev);
770 uart->port.iotype = UPIO_MEM;
771 uart->port.flags = UPF_BOOT_AUTOCONF | UPF_IOREMAP;
772 uart->port.line = line++;
773 uart->port.dev = dev;
774 uart->port.type = PORT_MEN_Z135;
775 uart->port.mapbase = mem->start;
776 uart->port.membase = NULL;
777 uart->mdev = mdev;
778
779 spin_lock_init(&uart->port.lock);
780 spin_lock_init(&uart->lock);
781
782 err = uart_add_one_port(&men_z135_driver, &uart->port);
783 if (err)
784 goto err;
785
786 return 0;
787
788err:
789 free_page((unsigned long) uart->rxbuf);
790 dev_err(dev, "Failed to add UART: %d\n", err);
791
792 return err;
793}
794
795/**
796 * men_z135_remove() - Remove a z135 instance from the system
797 *
798 * @mdev: The MCB device
799 */
800static void men_z135_remove(struct mcb_device *mdev)
801{
802 struct men_z135_port *uart = mcb_get_drvdata(mdev);
803
804 line--;
805 uart_remove_one_port(&men_z135_driver, &uart->port);
806 free_page((unsigned long) uart->rxbuf);
807}
808
809static const struct mcb_device_id men_z135_ids[] = {
810 { .device = 0x87 },
811};
812MODULE_DEVICE_TABLE(mcb, men_z135_ids);
813
814static struct mcb_driver mcb_driver = {
815 .driver = {
816 .name = "z135-uart",
817 .owner = THIS_MODULE,
818 },
819 .probe = men_z135_probe,
820 .remove = men_z135_remove,
821 .id_table = men_z135_ids,
822};
823
824/**
825 * men_z135_init() - Driver Registration Routine
826 *
827 * men_z135_init is the first routine called when the driver is loaded. All it
828 * does is register with the legacy MEN Chameleon subsystem.
829 */
830static int __init men_z135_init(void)
831{
832 int err;
833
834 err = uart_register_driver(&men_z135_driver);
835 if (err) {
836 pr_err("Failed to register UART: %d\n", err);
837 return err;
838 }
839
840 err = mcb_register_driver(&mcb_driver);
841 if (err) {
842 pr_err("Failed to register MCB driver: %d\n", err);
843 uart_unregister_driver(&men_z135_driver);
844 return err;
845 }
846
847 return 0;
848}
849module_init(men_z135_init);
850
851/**
852 * men_z135_exit() - Driver Exit Routine
853 *
854 * men_z135_exit is called just before the driver is removed from memory.
855 */
856static void __exit men_z135_exit(void)
857{
858 mcb_unregister_driver(&mcb_driver);
859 uart_unregister_driver(&men_z135_driver);
860}
861module_exit(men_z135_exit);
862
863MODULE_AUTHOR("Johannes Thumshirn <johannes.thumshirn@men.de>");
864MODULE_LICENSE("GPL v2");
865MODULE_DESCRIPTION("MEN 16z135 High Speed UART");
866MODULE_ALIAS("mcb:16z135");
diff --git a/drivers/tty/serial/mux.c b/drivers/tty/serial/mux.c
index 7fd6aaaacd8e..be127d0da32c 100644
--- a/drivers/tty/serial/mux.c
+++ b/drivers/tty/serial/mux.c
@@ -29,7 +29,7 @@
29#include <asm/irq.h> 29#include <asm/irq.h>
30#include <asm/parisc-device.h> 30#include <asm/parisc-device.h>
31 31
32#ifdef CONFIG_MAGIC_SYSRQ 32#if defined(CONFIG_SERIAL_MUX_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
33#include <linux/sysrq.h> 33#include <linux/sysrq.h>
34#define SUPPORT_SYSRQ 34#define SUPPORT_SYSRQ
35#endif 35#endif
@@ -613,7 +613,7 @@ static void __exit mux_exit(void)
613{ 613{
614 /* Delete the Mux timer. */ 614 /* Delete the Mux timer. */
615 if(port_cnt > 0) { 615 if(port_cnt > 0) {
616 del_timer(&mux_timer); 616 del_timer_sync(&mux_timer);
617#ifdef CONFIG_SERIAL_MUX_CONSOLE 617#ifdef CONFIG_SERIAL_MUX_CONSOLE
618 unregister_console(&mux_console); 618 unregister_console(&mux_console);
619#endif 619#endif
diff --git a/drivers/tty/serial/omap-serial.c b/drivers/tty/serial/omap-serial.c
index 08b6b9419f0d..d017cec8a34a 100644
--- a/drivers/tty/serial/omap-serial.c
+++ b/drivers/tty/serial/omap-serial.c
@@ -163,10 +163,6 @@ struct uart_omap_port {
163 u8 wakeups_enabled; 163 u8 wakeups_enabled;
164 u32 features; 164 u32 features;
165 165
166 int DTR_gpio;
167 int DTR_inverted;
168 int DTR_active;
169
170 struct serial_rs485 rs485; 166 struct serial_rs485 rs485;
171 int rts_gpio; 167 int rts_gpio;
172 168
@@ -184,8 +180,6 @@ static struct uart_omap_port *ui[OMAP_MAX_HSUART_PORTS];
184/* Forward declaration of functions */ 180/* Forward declaration of functions */
185static void serial_omap_mdr1_errataset(struct uart_omap_port *up, u8 mdr1); 181static void serial_omap_mdr1_errataset(struct uart_omap_port *up, u8 mdr1);
186 182
187static struct workqueue_struct *serial_omap_uart_wq;
188
189static inline unsigned int serial_in(struct uart_omap_port *up, int offset) 183static inline unsigned int serial_in(struct uart_omap_port *up, int offset)
190{ 184{
191 offset <<= up->port.regshift; 185 offset <<= up->port.regshift;
@@ -398,11 +392,8 @@ static void transmit_chars(struct uart_omap_port *up, unsigned int lsr)
398 break; 392 break;
399 } while (--count > 0); 393 } while (--count > 0);
400 394
401 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) { 395 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
402 spin_unlock(&up->port.lock);
403 uart_write_wakeup(&up->port); 396 uart_write_wakeup(&up->port);
404 spin_lock(&up->port.lock);
405 }
406 397
407 if (uart_circ_empty(xmit)) 398 if (uart_circ_empty(xmit))
408 serial_omap_stop_tx(&up->port); 399 serial_omap_stop_tx(&up->port);
@@ -697,16 +688,6 @@ static void serial_omap_set_mctrl(struct uart_port *port, unsigned int mctrl)
697 serial_out(up, UART_MCR, up->mcr); 688 serial_out(up, UART_MCR, up->mcr);
698 pm_runtime_mark_last_busy(up->dev); 689 pm_runtime_mark_last_busy(up->dev);
699 pm_runtime_put_autosuspend(up->dev); 690 pm_runtime_put_autosuspend(up->dev);
700
701 if (gpio_is_valid(up->DTR_gpio) &&
702 !!(mctrl & TIOCM_DTR) != up->DTR_active) {
703 up->DTR_active = !up->DTR_active;
704 if (gpio_cansleep(up->DTR_gpio))
705 schedule_work(&up->qos_work);
706 else
707 gpio_set_value(up->DTR_gpio,
708 up->DTR_active != up->DTR_inverted);
709 }
710} 691}
711 692
712static void serial_omap_break_ctl(struct uart_port *port, int break_state) 693static void serial_omap_break_ctl(struct uart_port *port, int break_state)
@@ -850,9 +831,6 @@ static void serial_omap_uart_qos_work(struct work_struct *work)
850 qos_work); 831 qos_work);
851 832
852 pm_qos_update_request(&up->pm_qos_request, up->latency); 833 pm_qos_update_request(&up->pm_qos_request, up->latency);
853 if (gpio_is_valid(up->DTR_gpio))
854 gpio_set_value_cansleep(up->DTR_gpio,
855 up->DTR_active != up->DTR_inverted);
856} 834}
857 835
858static void 836static void
@@ -1420,7 +1398,7 @@ serial_omap_ioctl(struct uart_port *port, unsigned int cmd, unsigned long arg)
1420 1398
1421 switch (cmd) { 1399 switch (cmd) {
1422 case TIOCSRS485: 1400 case TIOCSRS485:
1423 if (copy_from_user(&rs485conf, (struct serial_rs485 *) arg, 1401 if (copy_from_user(&rs485conf, (void __user *) arg,
1424 sizeof(rs485conf))) 1402 sizeof(rs485conf)))
1425 return -EFAULT; 1403 return -EFAULT;
1426 1404
@@ -1428,7 +1406,7 @@ serial_omap_ioctl(struct uart_port *port, unsigned int cmd, unsigned long arg)
1428 break; 1406 break;
1429 1407
1430 case TIOCGRS485: 1408 case TIOCGRS485:
1431 if (copy_to_user((struct serial_rs485 *) arg, 1409 if (copy_to_user((void __user *) arg,
1432 &(to_uart_omap_port(port)->rs485), 1410 &(to_uart_omap_port(port)->rs485),
1433 sizeof(rs485conf))) 1411 sizeof(rs485conf)))
1434 return -EFAULT; 1412 return -EFAULT;
@@ -1614,7 +1592,7 @@ static int serial_omap_probe_rs485(struct uart_omap_port *up,
1614 /* check for tx enable gpio */ 1592 /* check for tx enable gpio */
1615 up->rts_gpio = of_get_named_gpio_flags(np, "rts-gpio", 0, &flags); 1593 up->rts_gpio = of_get_named_gpio_flags(np, "rts-gpio", 0, &flags);
1616 if (gpio_is_valid(up->rts_gpio)) { 1594 if (gpio_is_valid(up->rts_gpio)) {
1617 ret = gpio_request(up->rts_gpio, "omap-serial"); 1595 ret = devm_gpio_request(up->dev, up->rts_gpio, "omap-serial");
1618 if (ret < 0) 1596 if (ret < 0)
1619 return ret; 1597 return ret;
1620 ret = gpio_direction_output(up->rts_gpio, 1598 ret = gpio_direction_output(up->rts_gpio,
@@ -1644,10 +1622,13 @@ static int serial_omap_probe_rs485(struct uart_omap_port *up,
1644 1622
1645static int serial_omap_probe(struct platform_device *pdev) 1623static int serial_omap_probe(struct platform_device *pdev)
1646{ 1624{
1647 struct uart_omap_port *up;
1648 struct resource *mem, *irq;
1649 struct omap_uart_port_info *omap_up_info = dev_get_platdata(&pdev->dev); 1625 struct omap_uart_port_info *omap_up_info = dev_get_platdata(&pdev->dev);
1650 int ret, uartirq = 0, wakeirq = 0; 1626 struct uart_omap_port *up;
1627 struct resource *mem;
1628 void __iomem *base;
1629 int uartirq = 0;
1630 int wakeirq = 0;
1631 int ret;
1651 1632
1652 /* The optional wakeirq may be specified in the board dts file */ 1633 /* The optional wakeirq may be specified in the board dts file */
1653 if (pdev->dev.of_node) { 1634 if (pdev->dev.of_node) {
@@ -1658,48 +1639,19 @@ static int serial_omap_probe(struct platform_device *pdev)
1658 omap_up_info = of_get_uart_port_info(&pdev->dev); 1639 omap_up_info = of_get_uart_port_info(&pdev->dev);
1659 pdev->dev.platform_data = omap_up_info; 1640 pdev->dev.platform_data = omap_up_info;
1660 } else { 1641 } else {
1661 irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0); 1642 uartirq = platform_get_irq(pdev, 0);
1662 if (!irq) { 1643 if (uartirq < 0)
1663 dev_err(&pdev->dev, "no irq resource?\n"); 1644 return -EPROBE_DEFER;
1664 return -ENODEV;
1665 }
1666 uartirq = irq->start;
1667 }
1668
1669 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1670 if (!mem) {
1671 dev_err(&pdev->dev, "no mem resource?\n");
1672 return -ENODEV;
1673 }
1674
1675 if (!devm_request_mem_region(&pdev->dev, mem->start, resource_size(mem),
1676 pdev->dev.driver->name)) {
1677 dev_err(&pdev->dev, "memory region already claimed\n");
1678 return -EBUSY;
1679 }
1680
1681 if (gpio_is_valid(omap_up_info->DTR_gpio) &&
1682 omap_up_info->DTR_present) {
1683 ret = gpio_request(omap_up_info->DTR_gpio, "omap-serial");
1684 if (ret < 0)
1685 return ret;
1686 ret = gpio_direction_output(omap_up_info->DTR_gpio,
1687 omap_up_info->DTR_inverted);
1688 if (ret < 0)
1689 return ret;
1690 } 1645 }
1691 1646
1692 up = devm_kzalloc(&pdev->dev, sizeof(*up), GFP_KERNEL); 1647 up = devm_kzalloc(&pdev->dev, sizeof(*up), GFP_KERNEL);
1693 if (!up) 1648 if (!up)
1694 return -ENOMEM; 1649 return -ENOMEM;
1695 1650
1696 if (gpio_is_valid(omap_up_info->DTR_gpio) && 1651 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1697 omap_up_info->DTR_present) { 1652 base = devm_ioremap_resource(&pdev->dev, mem);
1698 up->DTR_gpio = omap_up_info->DTR_gpio; 1653 if (IS_ERR(base))
1699 up->DTR_inverted = omap_up_info->DTR_inverted; 1654 return PTR_ERR(base);
1700 } else
1701 up->DTR_gpio = -EINVAL;
1702 up->DTR_active = 0;
1703 1655
1704 up->dev = &pdev->dev; 1656 up->dev = &pdev->dev;
1705 up->port.dev = &pdev->dev; 1657 up->port.dev = &pdev->dev;
@@ -1733,14 +1685,7 @@ static int serial_omap_probe(struct platform_device *pdev)
1733 1685
1734 sprintf(up->name, "OMAP UART%d", up->port.line); 1686 sprintf(up->name, "OMAP UART%d", up->port.line);
1735 up->port.mapbase = mem->start; 1687 up->port.mapbase = mem->start;
1736 up->port.membase = devm_ioremap(&pdev->dev, mem->start, 1688 up->port.membase = base;
1737 resource_size(mem));
1738 if (!up->port.membase) {
1739 dev_err(&pdev->dev, "can't ioremap UART\n");
1740 ret = -ENOMEM;
1741 goto err_ioremap;
1742 }
1743
1744 up->port.flags = omap_up_info->flags; 1689 up->port.flags = omap_up_info->flags;
1745 up->port.uartclk = omap_up_info->uartclk; 1690 up->port.uartclk = omap_up_info->uartclk;
1746 if (!up->port.uartclk) { 1691 if (!up->port.uartclk) {
@@ -1754,12 +1699,12 @@ static int serial_omap_probe(struct platform_device *pdev)
1754 up->calc_latency = PM_QOS_CPU_DMA_LAT_DEFAULT_VALUE; 1699 up->calc_latency = PM_QOS_CPU_DMA_LAT_DEFAULT_VALUE;
1755 pm_qos_add_request(&up->pm_qos_request, 1700 pm_qos_add_request(&up->pm_qos_request,
1756 PM_QOS_CPU_DMA_LATENCY, up->latency); 1701 PM_QOS_CPU_DMA_LATENCY, up->latency);
1757 serial_omap_uart_wq = create_singlethread_workqueue(up->name);
1758 INIT_WORK(&up->qos_work, serial_omap_uart_qos_work); 1702 INIT_WORK(&up->qos_work, serial_omap_uart_qos_work);
1759 1703
1760 platform_set_drvdata(pdev, up); 1704 platform_set_drvdata(pdev, up);
1761 if (omap_up_info->autosuspend_timeout == 0) 1705 if (omap_up_info->autosuspend_timeout == 0)
1762 omap_up_info->autosuspend_timeout = -1; 1706 omap_up_info->autosuspend_timeout = -1;
1707
1763 device_init_wakeup(up->dev, true); 1708 device_init_wakeup(up->dev, true);
1764 pm_runtime_use_autosuspend(&pdev->dev); 1709 pm_runtime_use_autosuspend(&pdev->dev);
1765 pm_runtime_set_autosuspend_delay(&pdev->dev, 1710 pm_runtime_set_autosuspend_delay(&pdev->dev,
@@ -1786,7 +1731,6 @@ static int serial_omap_probe(struct platform_device *pdev)
1786err_add_port: 1731err_add_port:
1787 pm_runtime_put(&pdev->dev); 1732 pm_runtime_put(&pdev->dev);
1788 pm_runtime_disable(&pdev->dev); 1733 pm_runtime_disable(&pdev->dev);
1789err_ioremap:
1790err_rs485: 1734err_rs485:
1791err_port_line: 1735err_port_line:
1792 dev_err(&pdev->dev, "[UART%d]: failure [%s]: %d\n", 1736 dev_err(&pdev->dev, "[UART%d]: failure [%s]: %d\n",
diff --git a/drivers/tty/serial/pch_uart.c b/drivers/tty/serial/pch_uart.c
index 0931b3fe9edf..0cb6a8e52bd0 100644
--- a/drivers/tty/serial/pch_uart.c
+++ b/drivers/tty/serial/pch_uart.c
@@ -257,6 +257,8 @@ struct eg20t_port {
257 dma_addr_t rx_buf_dma; 257 dma_addr_t rx_buf_dma;
258 258
259 struct dentry *debugfs; 259 struct dentry *debugfs;
260#define IRQ_NAME_SIZE 17
261 char irq_name[IRQ_NAME_SIZE];
260 262
261 /* protect the eg20t_port private structure and io access to membase */ 263 /* protect the eg20t_port private structure and io access to membase */
262 spinlock_t lock; 264 spinlock_t lock;
@@ -1343,7 +1345,7 @@ static int pch_uart_startup(struct uart_port *port)
1343 return ret; 1345 return ret;
1344 1346
1345 ret = request_irq(priv->port.irq, pch_uart_interrupt, IRQF_SHARED, 1347 ret = request_irq(priv->port.irq, pch_uart_interrupt, IRQF_SHARED,
1346 KBUILD_MODNAME, priv); 1348 priv->irq_name, priv);
1347 if (ret < 0) 1349 if (ret < 0)
1348 return ret; 1350 return ret;
1349 1351
@@ -1588,13 +1590,8 @@ static void pch_uart_put_poll_char(struct uart_port *port,
1588 wait_for_xmitr(priv, UART_LSR_THRE); 1590 wait_for_xmitr(priv, UART_LSR_THRE);
1589 /* 1591 /*
1590 * Send the character out. 1592 * Send the character out.
1591 * If a LF, also do CR...
1592 */ 1593 */
1593 iowrite8(c, priv->membase + PCH_UART_THR); 1594 iowrite8(c, priv->membase + PCH_UART_THR);
1594 if (c == 10) {
1595 wait_for_xmitr(priv, UART_LSR_THRE);
1596 iowrite8(13, priv->membase + PCH_UART_THR);
1597 }
1598 1595
1599 /* 1596 /*
1600 * Finally, wait for transmitter to become empty 1597 * Finally, wait for transmitter to become empty
@@ -1818,6 +1815,10 @@ static struct eg20t_port *pch_uart_init_port(struct pci_dev *pdev,
1818 priv->port.line = board->line_no; 1815 priv->port.line = board->line_no;
1819 priv->trigger = PCH_UART_HAL_TRIGGER_M; 1816 priv->trigger = PCH_UART_HAL_TRIGGER_M;
1820 1817
1818 snprintf(priv->irq_name, IRQ_NAME_SIZE,
1819 KBUILD_MODNAME ":" PCH_UART_DRIVER_DEVICE "%d",
1820 priv->port.line);
1821
1821 spin_lock_init(&priv->port.lock); 1822 spin_lock_init(&priv->port.lock);
1822 1823
1823 pci_set_drvdata(pdev, priv); 1824 pci_set_drvdata(pdev, priv);
diff --git a/drivers/tty/serial/pxa.c b/drivers/tty/serial/pxa.c
index f9f20f383760..9e7ee39f8b2a 100644
--- a/drivers/tty/serial/pxa.c
+++ b/drivers/tty/serial/pxa.c
@@ -711,13 +711,8 @@ static void serial_pxa_put_poll_char(struct uart_port *port,
711 wait_for_xmitr(up); 711 wait_for_xmitr(up);
712 /* 712 /*
713 * Send the character out. 713 * Send the character out.
714 * If a LF, also do CR...
715 */ 714 */
716 serial_out(up, UART_TX, c); 715 serial_out(up, UART_TX, c);
717 if (c == 10) {
718 wait_for_xmitr(up);
719 serial_out(up, UART_TX, 13);
720 }
721 716
722 /* 717 /*
723 * Finally, wait for transmitter to become empty 718 * Finally, wait for transmitter to become empty
diff --git a/drivers/tty/serial/sc16is7xx.c b/drivers/tty/serial/sc16is7xx.c
new file mode 100644
index 000000000000..7206a64f3ff7
--- /dev/null
+++ b/drivers/tty/serial/sc16is7xx.c
@@ -0,0 +1,1280 @@
1/*
2 * SC16IS7xx tty serial driver - Copyright (C) 2014 GridPoint
3 * Author: Jon Ringle <jringle@gridpoint.com>
4 *
5 * Based on max310x.c, by Alexander Shiyan <shc_work@mail.ru>
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 */
13
14#include <linux/bitops.h>
15#include <linux/clk.h>
16#include <linux/delay.h>
17#include <linux/device.h>
18#include <linux/gpio.h>
19#include <linux/i2c.h>
20#include <linux/module.h>
21#include <linux/of.h>
22#include <linux/of_device.h>
23#include <linux/regmap.h>
24#include <linux/serial_core.h>
25#include <linux/serial.h>
26#include <linux/tty.h>
27#include <linux/tty_flip.h>
28#include <linux/uaccess.h>
29
30#define SC16IS7XX_NAME "sc16is7xx"
31
32/* SC16IS7XX register definitions */
33#define SC16IS7XX_RHR_REG (0x00) /* RX FIFO */
34#define SC16IS7XX_THR_REG (0x00) /* TX FIFO */
35#define SC16IS7XX_IER_REG (0x01) /* Interrupt enable */
36#define SC16IS7XX_IIR_REG (0x02) /* Interrupt Identification */
37#define SC16IS7XX_FCR_REG (0x02) /* FIFO control */
38#define SC16IS7XX_LCR_REG (0x03) /* Line Control */
39#define SC16IS7XX_MCR_REG (0x04) /* Modem Control */
40#define SC16IS7XX_LSR_REG (0x05) /* Line Status */
41#define SC16IS7XX_MSR_REG (0x06) /* Modem Status */
42#define SC16IS7XX_SPR_REG (0x07) /* Scratch Pad */
43#define SC16IS7XX_TXLVL_REG (0x08) /* TX FIFO level */
44#define SC16IS7XX_RXLVL_REG (0x09) /* RX FIFO level */
45#define SC16IS7XX_IODIR_REG (0x0a) /* I/O Direction
46 * - only on 75x/76x
47 */
48#define SC16IS7XX_IOSTATE_REG (0x0b) /* I/O State
49 * - only on 75x/76x
50 */
51#define SC16IS7XX_IOINTENA_REG (0x0c) /* I/O Interrupt Enable
52 * - only on 75x/76x
53 */
54#define SC16IS7XX_IOCONTROL_REG (0x0e) /* I/O Control
55 * - only on 75x/76x
56 */
57#define SC16IS7XX_EFCR_REG (0x0f) /* Extra Features Control */
58
59/* TCR/TLR Register set: Only if ((MCR[2] == 1) && (EFR[4] == 1)) */
60#define SC16IS7XX_TCR_REG (0x06) /* Transmit control */
61#define SC16IS7XX_TLR_REG (0x07) /* Trigger level */
62
63/* Special Register set: Only if ((LCR[7] == 1) && (LCR != 0xBF)) */
64#define SC16IS7XX_DLL_REG (0x00) /* Divisor Latch Low */
65#define SC16IS7XX_DLH_REG (0x01) /* Divisor Latch High */
66
67/* Enhanced Register set: Only if (LCR == 0xBF) */
68#define SC16IS7XX_EFR_REG (0x02) /* Enhanced Features */
69#define SC16IS7XX_XON1_REG (0x04) /* Xon1 word */
70#define SC16IS7XX_XON2_REG (0x05) /* Xon2 word */
71#define SC16IS7XX_XOFF1_REG (0x06) /* Xoff1 word */
72#define SC16IS7XX_XOFF2_REG (0x07) /* Xoff2 word */
73
74/* IER register bits */
75#define SC16IS7XX_IER_RDI_BIT (1 << 0) /* Enable RX data interrupt */
76#define SC16IS7XX_IER_THRI_BIT (1 << 1) /* Enable TX holding register
77 * interrupt */
78#define SC16IS7XX_IER_RLSI_BIT (1 << 2) /* Enable RX line status
79 * interrupt */
80#define SC16IS7XX_IER_MSI_BIT (1 << 3) /* Enable Modem status
81 * interrupt */
82
83/* IER register bits - write only if (EFR[4] == 1) */
84#define SC16IS7XX_IER_SLEEP_BIT (1 << 4) /* Enable Sleep mode */
85#define SC16IS7XX_IER_XOFFI_BIT (1 << 5) /* Enable Xoff interrupt */
86#define SC16IS7XX_IER_RTSI_BIT (1 << 6) /* Enable nRTS interrupt */
87#define SC16IS7XX_IER_CTSI_BIT (1 << 7) /* Enable nCTS interrupt */
88
89/* FCR register bits */
90#define SC16IS7XX_FCR_FIFO_BIT (1 << 0) /* Enable FIFO */
91#define SC16IS7XX_FCR_RXRESET_BIT (1 << 1) /* Reset RX FIFO */
92#define SC16IS7XX_FCR_TXRESET_BIT (1 << 2) /* Reset TX FIFO */
93#define SC16IS7XX_FCR_RXLVLL_BIT (1 << 6) /* RX Trigger level LSB */
94#define SC16IS7XX_FCR_RXLVLH_BIT (1 << 7) /* RX Trigger level MSB */
95
96/* FCR register bits - write only if (EFR[4] == 1) */
97#define SC16IS7XX_FCR_TXLVLL_BIT (1 << 4) /* TX Trigger level LSB */
98#define SC16IS7XX_FCR_TXLVLH_BIT (1 << 5) /* TX Trigger level MSB */
99
100/* IIR register bits */
101#define SC16IS7XX_IIR_NO_INT_BIT (1 << 0) /* No interrupts pending */
102#define SC16IS7XX_IIR_ID_MASK 0x3e /* Mask for the interrupt ID */
103#define SC16IS7XX_IIR_THRI_SRC 0x02 /* TX holding register empty */
104#define SC16IS7XX_IIR_RDI_SRC 0x04 /* RX data interrupt */
105#define SC16IS7XX_IIR_RLSE_SRC 0x06 /* RX line status error */
106#define SC16IS7XX_IIR_RTOI_SRC 0x0c /* RX time-out interrupt */
107#define SC16IS7XX_IIR_MSI_SRC 0x00 /* Modem status interrupt
108 * - only on 75x/76x
109 */
110#define SC16IS7XX_IIR_INPIN_SRC 0x30 /* Input pin change of state
111 * - only on 75x/76x
112 */
113#define SC16IS7XX_IIR_XOFFI_SRC 0x10 /* Received Xoff */
114#define SC16IS7XX_IIR_CTSRTS_SRC 0x20 /* nCTS,nRTS change of state
115 * from active (LOW)
116 * to inactive (HIGH)
117 */
118/* LCR register bits */
119#define SC16IS7XX_LCR_LENGTH0_BIT (1 << 0) /* Word length bit 0 */
120#define SC16IS7XX_LCR_LENGTH1_BIT (1 << 1) /* Word length bit 1
121 *
122 * Word length bits table:
123 * 00 -> 5 bit words
124 * 01 -> 6 bit words
125 * 10 -> 7 bit words
126 * 11 -> 8 bit words
127 */
128#define SC16IS7XX_LCR_STOPLEN_BIT (1 << 2) /* STOP length bit
129 *
130 * STOP length bit table:
131 * 0 -> 1 stop bit
132 * 1 -> 1-1.5 stop bits if
133 * word length is 5,
134 * 2 stop bits otherwise
135 */
136#define SC16IS7XX_LCR_PARITY_BIT (1 << 3) /* Parity bit enable */
137#define SC16IS7XX_LCR_EVENPARITY_BIT (1 << 4) /* Even parity bit enable */
138#define SC16IS7XX_LCR_FORCEPARITY_BIT (1 << 5) /* 9-bit multidrop parity */
139#define SC16IS7XX_LCR_TXBREAK_BIT (1 << 6) /* TX break enable */
140#define SC16IS7XX_LCR_DLAB_BIT (1 << 7) /* Divisor Latch enable */
141#define SC16IS7XX_LCR_WORD_LEN_5 (0x00)
142#define SC16IS7XX_LCR_WORD_LEN_6 (0x01)
143#define SC16IS7XX_LCR_WORD_LEN_7 (0x02)
144#define SC16IS7XX_LCR_WORD_LEN_8 (0x03)
145#define SC16IS7XX_LCR_CONF_MODE_A SC16IS7XX_LCR_DLAB_BIT /* Special
146 * reg set */
147#define SC16IS7XX_LCR_CONF_MODE_B 0xBF /* Enhanced
148 * reg set */
149
150/* MCR register bits */
151#define SC16IS7XX_MCR_DTR_BIT (1 << 0) /* DTR complement
152 * - only on 75x/76x
153 */
154#define SC16IS7XX_MCR_RTS_BIT (1 << 1) /* RTS complement */
155#define SC16IS7XX_MCR_TCRTLR_BIT (1 << 2) /* TCR/TLR register enable */
156#define SC16IS7XX_MCR_LOOP_BIT (1 << 4) /* Enable loopback test mode */
157#define SC16IS7XX_MCR_XONANY_BIT (1 << 5) /* Enable Xon Any
158 * - write enabled
159 * if (EFR[4] == 1)
160 */
161#define SC16IS7XX_MCR_IRDA_BIT (1 << 6) /* Enable IrDA mode
162 * - write enabled
163 * if (EFR[4] == 1)
164 */
165#define SC16IS7XX_MCR_CLKSEL_BIT (1 << 7) /* Divide clock by 4
166 * - write enabled
167 * if (EFR[4] == 1)
168 */
169
170/* LSR register bits */
171#define SC16IS7XX_LSR_DR_BIT (1 << 0) /* Receiver data ready */
172#define SC16IS7XX_LSR_OE_BIT (1 << 1) /* Overrun Error */
173#define SC16IS7XX_LSR_PE_BIT (1 << 2) /* Parity Error */
174#define SC16IS7XX_LSR_FE_BIT (1 << 3) /* Frame Error */
175#define SC16IS7XX_LSR_BI_BIT (1 << 4) /* Break Interrupt */
176#define SC16IS7XX_LSR_BRK_ERROR_MASK 0x1E /* BI, FE, PE, OE bits */
177#define SC16IS7XX_LSR_THRE_BIT (1 << 5) /* TX holding register empty */
178#define SC16IS7XX_LSR_TEMT_BIT (1 << 6) /* Transmitter empty */
179#define SC16IS7XX_LSR_FIFOE_BIT (1 << 7) /* Fifo Error */
180
181/* MSR register bits */
182#define SC16IS7XX_MSR_DCTS_BIT (1 << 0) /* Delta CTS Clear To Send */
183#define SC16IS7XX_MSR_DDSR_BIT (1 << 1) /* Delta DSR Data Set Ready
184 * or (IO4)
185 * - only on 75x/76x
186 */
187#define SC16IS7XX_MSR_DRI_BIT (1 << 2) /* Delta RI Ring Indicator
188 * or (IO7)
189 * - only on 75x/76x
190 */
191#define SC16IS7XX_MSR_DCD_BIT (1 << 3) /* Delta CD Carrier Detect
192 * or (IO6)
193 * - only on 75x/76x
194 */
195#define SC16IS7XX_MSR_CTS_BIT (1 << 0) /* CTS */
196#define SC16IS7XX_MSR_DSR_BIT (1 << 1) /* DSR (IO4)
197 * - only on 75x/76x
198 */
199#define SC16IS7XX_MSR_RI_BIT (1 << 2) /* RI (IO7)
200 * - only on 75x/76x
201 */
202#define SC16IS7XX_MSR_CD_BIT (1 << 3) /* CD (IO6)
203 * - only on 75x/76x
204 */
205#define SC16IS7XX_MSR_DELTA_MASK 0x0F /* Any of the delta bits! */
206
207/*
208 * TCR register bits
209 * TCR trigger levels are available from 0 to 60 characters with a granularity
210 * of four.
211 * The programmer must program the TCR such that TCR[3:0] > TCR[7:4]. There is
212 * no built-in hardware check to make sure this condition is met. Also, the TCR
213 * must be programmed with this condition before auto RTS or software flow
214 * control is enabled to avoid spurious operation of the device.
215 */
216#define SC16IS7XX_TCR_RX_HALT(words) ((((words) / 4) & 0x0f) << 0)
217#define SC16IS7XX_TCR_RX_RESUME(words) ((((words) / 4) & 0x0f) << 4)
218
219/*
220 * TLR register bits
221 * If TLR[3:0] or TLR[7:4] are logical 0, the selectable trigger levels via the
222 * FIFO Control Register (FCR) are used for the transmit and receive FIFO
223 * trigger levels. Trigger levels from 4 characters to 60 characters are
224 * available with a granularity of four.
225 *
226 * When the trigger level setting in TLR is zero, the SC16IS740/750/760 uses the
227 * trigger level setting defined in FCR. If TLR has non-zero trigger level value
228 * the trigger level defined in FCR is discarded. This applies to both transmit
229 * FIFO and receive FIFO trigger level setting.
230 *
231 * When TLR is used for RX trigger level control, FCR[7:6] should be left at the
232 * default state, that is, '00'.
233 */
234#define SC16IS7XX_TLR_TX_TRIGGER(words) ((((words) / 4) & 0x0f) << 0)
235#define SC16IS7XX_TLR_RX_TRIGGER(words) ((((words) / 4) & 0x0f) << 4)
236
237/* IOControl register bits (Only 750/760) */
238#define SC16IS7XX_IOCONTROL_LATCH_BIT (1 << 0) /* Enable input latching */
239#define SC16IS7XX_IOCONTROL_GPIO_BIT (1 << 1) /* Enable GPIO[7:4] */
240#define SC16IS7XX_IOCONTROL_SRESET_BIT (1 << 3) /* Software Reset */
241
242/* EFCR register bits */
243#define SC16IS7XX_EFCR_9BIT_MODE_BIT (1 << 0) /* Enable 9-bit or Multidrop
244 * mode (RS485) */
245#define SC16IS7XX_EFCR_RXDISABLE_BIT (1 << 1) /* Disable receiver */
246#define SC16IS7XX_EFCR_TXDISABLE_BIT (1 << 2) /* Disable transmitter */
247#define SC16IS7XX_EFCR_AUTO_RS485_BIT (1 << 4) /* Auto RS485 RTS direction */
248#define SC16IS7XX_EFCR_RTS_INVERT_BIT (1 << 5) /* RTS output inversion */
249#define SC16IS7XX_EFCR_IRDA_MODE_BIT (1 << 7) /* IrDA mode
250 * 0 = rate upto 115.2 kbit/s
251 * - Only 750/760
252 * 1 = rate upto 1.152 Mbit/s
253 * - Only 760
254 */
255
256/* EFR register bits */
257#define SC16IS7XX_EFR_AUTORTS_BIT (1 << 6) /* Auto RTS flow ctrl enable */
258#define SC16IS7XX_EFR_AUTOCTS_BIT (1 << 7) /* Auto CTS flow ctrl enable */
259#define SC16IS7XX_EFR_XOFF2_DETECT_BIT (1 << 5) /* Enable Xoff2 detection */
260#define SC16IS7XX_EFR_ENABLE_BIT (1 << 4) /* Enable enhanced functions
261 * and writing to IER[7:4],
262 * FCR[5:4], MCR[7:5]
263 */
264#define SC16IS7XX_EFR_SWFLOW3_BIT (1 << 3) /* SWFLOW bit 3 */
265#define SC16IS7XX_EFR_SWFLOW2_BIT (1 << 2) /* SWFLOW bit 2
266 *
267 * SWFLOW bits 3 & 2 table:
268 * 00 -> no transmitter flow
269 * control
270 * 01 -> transmitter generates
271 * XON2 and XOFF2
272 * 10 -> transmitter generates
273 * XON1 and XOFF1
274 * 11 -> transmitter generates
275 * XON1, XON2, XOFF1 and
276 * XOFF2
277 */
278#define SC16IS7XX_EFR_SWFLOW1_BIT (1 << 1) /* SWFLOW bit 2 */
279#define SC16IS7XX_EFR_SWFLOW0_BIT (1 << 0) /* SWFLOW bit 3
280 *
281 * SWFLOW bits 3 & 2 table:
282 * 00 -> no received flow
283 * control
284 * 01 -> receiver compares
285 * XON2 and XOFF2
286 * 10 -> receiver compares
287 * XON1 and XOFF1
288 * 11 -> receiver compares
289 * XON1, XON2, XOFF1 and
290 * XOFF2
291 */
292
293/* Misc definitions */
294#define SC16IS7XX_FIFO_SIZE (64)
295#define SC16IS7XX_REG_SHIFT 2
296
297struct sc16is7xx_devtype {
298 char name[10];
299 int nr_gpio;
300 int nr_uart;
301};
302
303struct sc16is7xx_one {
304 struct uart_port port;
305 struct work_struct tx_work;
306 struct work_struct md_work;
307
308 struct serial_rs485 rs485;
309};
310
311struct sc16is7xx_port {
312 struct uart_driver uart;
313 struct sc16is7xx_devtype *devtype;
314 struct regmap *regmap;
315 struct mutex mutex;
316 struct clk *clk;
317#ifdef CONFIG_GPIOLIB
318 struct gpio_chip gpio;
319#endif
320 struct sc16is7xx_one p[0];
321};
322
323#define to_sc16is7xx_one(p,e) ((container_of((p), struct sc16is7xx_one, e)))
324
325static u8 sc16is7xx_port_read(struct uart_port *port, u8 reg)
326{
327 struct sc16is7xx_port *s = dev_get_drvdata(port->dev);
328 unsigned int val = 0;
329
330 regmap_read(s->regmap,
331 (reg << SC16IS7XX_REG_SHIFT) | port->line, &val);
332
333 return val;
334}
335
336static void sc16is7xx_port_write(struct uart_port *port, u8 reg, u8 val)
337{
338 struct sc16is7xx_port *s = dev_get_drvdata(port->dev);
339
340 regmap_write(s->regmap,
341 (reg << SC16IS7XX_REG_SHIFT) | port->line, val);
342}
343
344static void sc16is7xx_port_update(struct uart_port *port, u8 reg,
345 u8 mask, u8 val)
346{
347 struct sc16is7xx_port *s = dev_get_drvdata(port->dev);
348
349 regmap_update_bits(s->regmap,
350 (reg << SC16IS7XX_REG_SHIFT) | port->line,
351 mask, val);
352}
353
354
355static void sc16is7xx_power(struct uart_port *port, int on)
356{
357 sc16is7xx_port_update(port, SC16IS7XX_IER_REG,
358 SC16IS7XX_IER_SLEEP_BIT,
359 on ? 0 : SC16IS7XX_IER_SLEEP_BIT);
360}
361
362static const struct sc16is7xx_devtype sc16is74x_devtype = {
363 .name = "SC16IS74X",
364 .nr_gpio = 0,
365 .nr_uart = 1,
366};
367
368static const struct sc16is7xx_devtype sc16is750_devtype = {
369 .name = "SC16IS750",
370 .nr_gpio = 8,
371 .nr_uart = 1,
372};
373
374static const struct sc16is7xx_devtype sc16is752_devtype = {
375 .name = "SC16IS752",
376 .nr_gpio = 8,
377 .nr_uart = 2,
378};
379
380static const struct sc16is7xx_devtype sc16is760_devtype = {
381 .name = "SC16IS760",
382 .nr_gpio = 8,
383 .nr_uart = 1,
384};
385
386static const struct sc16is7xx_devtype sc16is762_devtype = {
387 .name = "SC16IS762",
388 .nr_gpio = 8,
389 .nr_uart = 2,
390};
391
392static bool sc16is7xx_regmap_volatile(struct device *dev, unsigned int reg)
393{
394 switch (reg >> SC16IS7XX_REG_SHIFT) {
395 case SC16IS7XX_RHR_REG:
396 case SC16IS7XX_IIR_REG:
397 case SC16IS7XX_LSR_REG:
398 case SC16IS7XX_MSR_REG:
399 case SC16IS7XX_TXLVL_REG:
400 case SC16IS7XX_RXLVL_REG:
401 case SC16IS7XX_IOSTATE_REG:
402 return true;
403 default:
404 break;
405 }
406
407 return false;
408}
409
410static bool sc16is7xx_regmap_precious(struct device *dev, unsigned int reg)
411{
412 switch (reg >> SC16IS7XX_REG_SHIFT) {
413 case SC16IS7XX_RHR_REG:
414 return true;
415 default:
416 break;
417 }
418
419 return false;
420}
421
422static int sc16is7xx_set_baud(struct uart_port *port, int baud)
423{
424 struct sc16is7xx_port *s = dev_get_drvdata(port->dev);
425 u8 lcr;
426 u8 prescaler = 0;
427 unsigned long clk = port->uartclk, div = clk / 16 / baud;
428
429 if (div > 0xffff) {
430 prescaler = SC16IS7XX_MCR_CLKSEL_BIT;
431 div /= 4;
432 }
433
434 lcr = sc16is7xx_port_read(port, SC16IS7XX_LCR_REG);
435
436 /* Open the LCR divisors for configuration */
437 sc16is7xx_port_write(port, SC16IS7XX_LCR_REG,
438 SC16IS7XX_LCR_CONF_MODE_B);
439
440 /* Enable enhanced features */
441 regcache_cache_bypass(s->regmap, true);
442 sc16is7xx_port_write(port, SC16IS7XX_EFR_REG,
443 SC16IS7XX_EFR_ENABLE_BIT);
444 regcache_cache_bypass(s->regmap, false);
445
446 /* Put LCR back to the normal mode */
447 sc16is7xx_port_write(port, SC16IS7XX_LCR_REG, lcr);
448
449 sc16is7xx_port_update(port, SC16IS7XX_MCR_REG,
450 SC16IS7XX_MCR_CLKSEL_BIT,
451 prescaler);
452
453 /* Open the LCR divisors for configuration */
454 sc16is7xx_port_write(port, SC16IS7XX_LCR_REG,
455 SC16IS7XX_LCR_CONF_MODE_A);
456
457 /* Write the new divisor */
458 regcache_cache_bypass(s->regmap, true);
459 sc16is7xx_port_write(port, SC16IS7XX_DLH_REG, div / 256);
460 sc16is7xx_port_write(port, SC16IS7XX_DLL_REG, div % 256);
461 regcache_cache_bypass(s->regmap, false);
462
463 /* Put LCR back to the normal mode */
464 sc16is7xx_port_write(port, SC16IS7XX_LCR_REG, lcr);
465
466 return DIV_ROUND_CLOSEST(clk / 16, div);
467}
468
469static void sc16is7xx_handle_rx(struct uart_port *port, unsigned int rxlen,
470 unsigned int iir)
471{
472 struct sc16is7xx_port *s = dev_get_drvdata(port->dev);
473 unsigned int lsr = 0, ch, flag, bytes_read, i;
474 u8 buf[port->fifosize];
475 bool read_lsr = (iir == SC16IS7XX_IIR_RLSE_SRC) ? true : false;
476
477 if (unlikely(rxlen >= port->fifosize)) {
478 dev_warn_ratelimited(port->dev,
479 "Port %i: Possible RX FIFO overrun: %d\n",
480 port->line, rxlen);
481 port->icount.buf_overrun++;
482 /* Ensure sanity of RX level */
483 rxlen = port->fifosize;
484 }
485
486 while (rxlen) {
487 /* Only read lsr if there are possible errors in FIFO */
488 if (read_lsr) {
489 lsr = sc16is7xx_port_read(port, SC16IS7XX_LSR_REG);
490 if (!(lsr & SC16IS7XX_LSR_FIFOE_BIT))
491 read_lsr = false; /* No errors left in FIFO */
492 } else
493 lsr = 0;
494
495 if (read_lsr) {
496 buf[0] = sc16is7xx_port_read(port, SC16IS7XX_RHR_REG);
497 bytes_read = 1;
498 } else {
499 regcache_cache_bypass(s->regmap, true);
500 regmap_raw_read(s->regmap, SC16IS7XX_RHR_REG,
501 buf, rxlen);
502 regcache_cache_bypass(s->regmap, false);
503 bytes_read = rxlen;
504 }
505
506 lsr &= SC16IS7XX_LSR_BRK_ERROR_MASK;
507
508 port->icount.rx++;
509 flag = TTY_NORMAL;
510
511 if (unlikely(lsr)) {
512 if (lsr & SC16IS7XX_LSR_BI_BIT) {
513 port->icount.brk++;
514 if (uart_handle_break(port))
515 continue;
516 } else if (lsr & SC16IS7XX_LSR_PE_BIT)
517 port->icount.parity++;
518 else if (lsr & SC16IS7XX_LSR_FE_BIT)
519 port->icount.frame++;
520 else if (lsr & SC16IS7XX_LSR_OE_BIT)
521 port->icount.overrun++;
522
523 lsr &= port->read_status_mask;
524 if (lsr & SC16IS7XX_LSR_BI_BIT)
525 flag = TTY_BREAK;
526 else if (lsr & SC16IS7XX_LSR_PE_BIT)
527 flag = TTY_PARITY;
528 else if (lsr & SC16IS7XX_LSR_FE_BIT)
529 flag = TTY_FRAME;
530 else if (lsr & SC16IS7XX_LSR_OE_BIT)
531 flag = TTY_OVERRUN;
532 }
533
534 for (i = 0; i < bytes_read; ++i) {
535 ch = buf[i];
536 if (uart_handle_sysrq_char(port, ch))
537 continue;
538
539 if (lsr & port->ignore_status_mask)
540 continue;
541
542 uart_insert_char(port, lsr, SC16IS7XX_LSR_OE_BIT, ch,
543 flag);
544 }
545 rxlen -= bytes_read;
546 }
547
548 tty_flip_buffer_push(&port->state->port);
549}
550
551static void sc16is7xx_handle_tx(struct uart_port *port)
552{
553 struct sc16is7xx_port *s = dev_get_drvdata(port->dev);
554 struct circ_buf *xmit = &port->state->xmit;
555 unsigned int txlen, to_send, i;
556 u8 buf[port->fifosize];
557
558 if (unlikely(port->x_char)) {
559 sc16is7xx_port_write(port, SC16IS7XX_THR_REG, port->x_char);
560 port->icount.tx++;
561 port->x_char = 0;
562 return;
563 }
564
565 if (uart_circ_empty(xmit) || uart_tx_stopped(port))
566 return;
567
568 /* Get length of data pending in circular buffer */
569 to_send = uart_circ_chars_pending(xmit);
570 if (likely(to_send)) {
571 /* Limit to size of TX FIFO */
572 txlen = sc16is7xx_port_read(port, SC16IS7XX_TXLVL_REG);
573 to_send = (to_send > txlen) ? txlen : to_send;
574
575 /* Add data to send */
576 port->icount.tx += to_send;
577
578 /* Convert to linear buffer */
579 for (i = 0; i < to_send; ++i) {
580 buf[i] = xmit->buf[xmit->tail];
581 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
582 }
583 regcache_cache_bypass(s->regmap, true);
584 regmap_raw_write(s->regmap, SC16IS7XX_THR_REG, buf, to_send);
585 regcache_cache_bypass(s->regmap, false);
586 }
587
588 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
589 uart_write_wakeup(port);
590}
591
592static void sc16is7xx_port_irq(struct sc16is7xx_port *s, int portno)
593{
594 struct uart_port *port = &s->p[portno].port;
595
596 do {
597 unsigned int iir, msr, rxlen;
598
599 iir = sc16is7xx_port_read(port, SC16IS7XX_IIR_REG);
600 if (iir & SC16IS7XX_IIR_NO_INT_BIT)
601 break;
602
603 iir &= SC16IS7XX_IIR_ID_MASK;
604
605 switch (iir) {
606 case SC16IS7XX_IIR_RDI_SRC:
607 case SC16IS7XX_IIR_RLSE_SRC:
608 case SC16IS7XX_IIR_RTOI_SRC:
609 case SC16IS7XX_IIR_XOFFI_SRC:
610 rxlen = sc16is7xx_port_read(port, SC16IS7XX_RXLVL_REG);
611 if (rxlen)
612 sc16is7xx_handle_rx(port, rxlen, iir);
613 break;
614
615 case SC16IS7XX_IIR_CTSRTS_SRC:
616 msr = sc16is7xx_port_read(port, SC16IS7XX_MSR_REG);
617 uart_handle_cts_change(port,
618 !!(msr & SC16IS7XX_MSR_CTS_BIT));
619 break;
620 case SC16IS7XX_IIR_THRI_SRC:
621 mutex_lock(&s->mutex);
622 sc16is7xx_handle_tx(port);
623 mutex_unlock(&s->mutex);
624 break;
625 default:
626 dev_err_ratelimited(port->dev,
627 "Port %i: Unexpected interrupt: %x",
628 port->line, iir);
629 break;
630 }
631 } while (1);
632}
633
634static irqreturn_t sc16is7xx_ist(int irq, void *dev_id)
635{
636 struct sc16is7xx_port *s = (struct sc16is7xx_port *)dev_id;
637 int i;
638
639 for (i = 0; i < s->uart.nr; ++i)
640 sc16is7xx_port_irq(s, i);
641
642 return IRQ_HANDLED;
643}
644
645static void sc16is7xx_wq_proc(struct work_struct *ws)
646{
647 struct sc16is7xx_one *one = to_sc16is7xx_one(ws, tx_work);
648 struct sc16is7xx_port *s = dev_get_drvdata(one->port.dev);
649
650 mutex_lock(&s->mutex);
651 sc16is7xx_handle_tx(&one->port);
652 mutex_unlock(&s->mutex);
653}
654
655static void sc16is7xx_stop_tx(struct uart_port* port)
656{
657 struct sc16is7xx_one *one = to_sc16is7xx_one(port, port);
658 struct circ_buf *xmit = &one->port.state->xmit;
659
660 /* handle rs485 */
661 if (one->rs485.flags & SER_RS485_ENABLED) {
662 /* do nothing if current tx not yet completed */
663 int lsr = sc16is7xx_port_read(port, SC16IS7XX_LSR_REG);
664 if (!(lsr & SC16IS7XX_LSR_TEMT_BIT))
665 return;
666
667 if (uart_circ_empty(xmit) &&
668 (one->rs485.delay_rts_after_send > 0))
669 mdelay(one->rs485.delay_rts_after_send);
670 }
671
672 sc16is7xx_port_update(port, SC16IS7XX_IER_REG,
673 SC16IS7XX_IER_THRI_BIT,
674 0);
675}
676
677static void sc16is7xx_stop_rx(struct uart_port* port)
678{
679 struct sc16is7xx_one *one = to_sc16is7xx_one(port, port);
680
681 one->port.read_status_mask &= ~SC16IS7XX_LSR_DR_BIT;
682 sc16is7xx_port_update(port, SC16IS7XX_IER_REG,
683 SC16IS7XX_LSR_DR_BIT,
684 0);
685}
686
687static void sc16is7xx_start_tx(struct uart_port *port)
688{
689 struct sc16is7xx_one *one = to_sc16is7xx_one(port, port);
690
691 /* handle rs485 */
692 if ((one->rs485.flags & SER_RS485_ENABLED) &&
693 (one->rs485.delay_rts_before_send > 0)) {
694 mdelay(one->rs485.delay_rts_before_send);
695 }
696
697 if (!work_pending(&one->tx_work))
698 schedule_work(&one->tx_work);
699}
700
701static unsigned int sc16is7xx_tx_empty(struct uart_port *port)
702{
703 unsigned int lvl, lsr;
704
705 lvl = sc16is7xx_port_read(port, SC16IS7XX_TXLVL_REG);
706 lsr = sc16is7xx_port_read(port, SC16IS7XX_LSR_REG);
707
708 return ((lsr & SC16IS7XX_LSR_THRE_BIT) && !lvl) ? TIOCSER_TEMT : 0;
709}
710
711static unsigned int sc16is7xx_get_mctrl(struct uart_port *port)
712{
713 /* DCD and DSR are not wired and CTS/RTS is handled automatically
714 * so just indicate DSR and CAR asserted
715 */
716 return TIOCM_DSR | TIOCM_CAR;
717}
718
719static void sc16is7xx_md_proc(struct work_struct *ws)
720{
721 struct sc16is7xx_one *one = to_sc16is7xx_one(ws, md_work);
722
723 sc16is7xx_port_update(&one->port, SC16IS7XX_MCR_REG,
724 SC16IS7XX_MCR_LOOP_BIT,
725 (one->port.mctrl & TIOCM_LOOP) ?
726 SC16IS7XX_MCR_LOOP_BIT : 0);
727}
728
729static void sc16is7xx_set_mctrl(struct uart_port *port, unsigned int mctrl)
730{
731 struct sc16is7xx_one *one = to_sc16is7xx_one(port, port);
732
733 schedule_work(&one->md_work);
734}
735
736static void sc16is7xx_break_ctl(struct uart_port *port, int break_state)
737{
738 sc16is7xx_port_update(port, SC16IS7XX_LCR_REG,
739 SC16IS7XX_LCR_TXBREAK_BIT,
740 break_state ? SC16IS7XX_LCR_TXBREAK_BIT : 0);
741}
742
743static void sc16is7xx_set_termios(struct uart_port *port,
744 struct ktermios *termios,
745 struct ktermios *old)
746{
747 struct sc16is7xx_port *s = dev_get_drvdata(port->dev);
748 unsigned int lcr, flow = 0;
749 int baud;
750
751 /* Mask termios capabilities we don't support */
752 termios->c_cflag &= ~CMSPAR;
753
754 /* Word size */
755 switch (termios->c_cflag & CSIZE) {
756 case CS5:
757 lcr = SC16IS7XX_LCR_WORD_LEN_5;
758 break;
759 case CS6:
760 lcr = SC16IS7XX_LCR_WORD_LEN_6;
761 break;
762 case CS7:
763 lcr = SC16IS7XX_LCR_WORD_LEN_7;
764 break;
765 case CS8:
766 lcr = SC16IS7XX_LCR_WORD_LEN_8;
767 break;
768 default:
769 lcr = SC16IS7XX_LCR_WORD_LEN_8;
770 termios->c_cflag &= ~CSIZE;
771 termios->c_cflag |= CS8;
772 break;
773 }
774
775 /* Parity */
776 if (termios->c_cflag & PARENB) {
777 lcr |= SC16IS7XX_LCR_PARITY_BIT;
778 if (!(termios->c_cflag & PARODD))
779 lcr |= SC16IS7XX_LCR_EVENPARITY_BIT;
780 }
781
782 /* Stop bits */
783 if (termios->c_cflag & CSTOPB)
784 lcr |= SC16IS7XX_LCR_STOPLEN_BIT; /* 2 stops */
785
786 /* Set read status mask */
787 port->read_status_mask = SC16IS7XX_LSR_OE_BIT;
788 if (termios->c_iflag & INPCK)
789 port->read_status_mask |= SC16IS7XX_LSR_PE_BIT |
790 SC16IS7XX_LSR_FE_BIT;
791 if (termios->c_iflag & (BRKINT | PARMRK))
792 port->read_status_mask |= SC16IS7XX_LSR_BI_BIT;
793
794 /* Set status ignore mask */
795 port->ignore_status_mask = 0;
796 if (termios->c_iflag & IGNBRK)
797 port->ignore_status_mask |= SC16IS7XX_LSR_BI_BIT;
798 if (!(termios->c_cflag & CREAD))
799 port->ignore_status_mask |= SC16IS7XX_LSR_BRK_ERROR_MASK;
800
801 sc16is7xx_port_write(port, SC16IS7XX_LCR_REG,
802 SC16IS7XX_LCR_CONF_MODE_B);
803
804 /* Configure flow control */
805 regcache_cache_bypass(s->regmap, true);
806 sc16is7xx_port_write(port, SC16IS7XX_XON1_REG, termios->c_cc[VSTART]);
807 sc16is7xx_port_write(port, SC16IS7XX_XOFF1_REG, termios->c_cc[VSTOP]);
808 if (termios->c_cflag & CRTSCTS)
809 flow |= SC16IS7XX_EFR_AUTOCTS_BIT |
810 SC16IS7XX_EFR_AUTORTS_BIT;
811 if (termios->c_iflag & IXON)
812 flow |= SC16IS7XX_EFR_SWFLOW3_BIT;
813 if (termios->c_iflag & IXOFF)
814 flow |= SC16IS7XX_EFR_SWFLOW1_BIT;
815
816 sc16is7xx_port_write(port, SC16IS7XX_EFR_REG, flow);
817 regcache_cache_bypass(s->regmap, false);
818
819 /* Update LCR register */
820 sc16is7xx_port_write(port, SC16IS7XX_LCR_REG, lcr);
821
822 /* Get baud rate generator configuration */
823 baud = uart_get_baud_rate(port, termios, old,
824 port->uartclk / 16 / 4 / 0xffff,
825 port->uartclk / 16);
826
827 /* Setup baudrate generator */
828 baud = sc16is7xx_set_baud(port, baud);
829
830 /* Update timeout according to new baud rate */
831 uart_update_timeout(port, termios->c_cflag, baud);
832}
833
834#if defined(TIOCSRS485) && defined(TIOCGRS485)
835static void sc16is7xx_config_rs485(struct uart_port *port,
836 struct serial_rs485 *rs485)
837{
838 struct sc16is7xx_one *one = to_sc16is7xx_one(port, port);
839
840 one->rs485 = *rs485;
841
842 if (one->rs485.flags & SER_RS485_ENABLED) {
843 sc16is7xx_port_update(port, SC16IS7XX_EFCR_REG,
844 SC16IS7XX_EFCR_AUTO_RS485_BIT,
845 SC16IS7XX_EFCR_AUTO_RS485_BIT);
846 } else {
847 sc16is7xx_port_update(port, SC16IS7XX_EFCR_REG,
848 SC16IS7XX_EFCR_AUTO_RS485_BIT,
849 0);
850 }
851}
852#endif
853
854static int sc16is7xx_ioctl(struct uart_port *port, unsigned int cmd,
855 unsigned long arg)
856{
857#if defined(TIOCSRS485) && defined(TIOCGRS485)
858 struct serial_rs485 rs485;
859
860 switch (cmd) {
861 case TIOCSRS485:
862 if (copy_from_user(&rs485, (void __user *)arg, sizeof(rs485)))
863 return -EFAULT;
864
865 sc16is7xx_config_rs485(port, &rs485);
866 return 0;
867 case TIOCGRS485:
868 if (copy_to_user((void __user *)arg,
869 &(to_sc16is7xx_one(port, port)->rs485),
870 sizeof(rs485)))
871 return -EFAULT;
872 return 0;
873 default:
874 break;
875 }
876#endif
877
878 return -ENOIOCTLCMD;
879}
880
881static int sc16is7xx_startup(struct uart_port *port)
882{
883 struct sc16is7xx_port *s = dev_get_drvdata(port->dev);
884 unsigned int val;
885
886 sc16is7xx_power(port, 1);
887
888 /* Reset FIFOs*/
889 val = SC16IS7XX_FCR_RXRESET_BIT | SC16IS7XX_FCR_TXRESET_BIT;
890 sc16is7xx_port_write(port, SC16IS7XX_FCR_REG, val);
891 udelay(5);
892 sc16is7xx_port_write(port, SC16IS7XX_FCR_REG,
893 SC16IS7XX_FCR_FIFO_BIT);
894
895 /* Enable EFR */
896 sc16is7xx_port_write(port, SC16IS7XX_LCR_REG,
897 SC16IS7XX_LCR_CONF_MODE_B);
898
899 regcache_cache_bypass(s->regmap, true);
900
901 /* Enable write access to enhanced features and internal clock div */
902 sc16is7xx_port_write(port, SC16IS7XX_EFR_REG,
903 SC16IS7XX_EFR_ENABLE_BIT);
904
905 /* Enable TCR/TLR */
906 sc16is7xx_port_update(port, SC16IS7XX_MCR_REG,
907 SC16IS7XX_MCR_TCRTLR_BIT,
908 SC16IS7XX_MCR_TCRTLR_BIT);
909
910 /* Configure flow control levels */
911 /* Flow control halt level 48, resume level 24 */
912 sc16is7xx_port_write(port, SC16IS7XX_TCR_REG,
913 SC16IS7XX_TCR_RX_RESUME(24) |
914 SC16IS7XX_TCR_RX_HALT(48));
915
916 regcache_cache_bypass(s->regmap, false);
917
918 /* Now, initialize the UART */
919 sc16is7xx_port_write(port, SC16IS7XX_LCR_REG, SC16IS7XX_LCR_WORD_LEN_8);
920
921 /* Enable the Rx and Tx FIFO */
922 sc16is7xx_port_update(port, SC16IS7XX_EFCR_REG,
923 SC16IS7XX_EFCR_RXDISABLE_BIT |
924 SC16IS7XX_EFCR_TXDISABLE_BIT,
925 0);
926
927 /* Enable RX, TX, CTS change interrupts */
928 val = SC16IS7XX_IER_RDI_BIT | SC16IS7XX_IER_THRI_BIT |
929 SC16IS7XX_IER_CTSI_BIT;
930 sc16is7xx_port_write(port, SC16IS7XX_IER_REG, val);
931
932 return 0;
933}
934
935static void sc16is7xx_shutdown(struct uart_port *port)
936{
937 /* Disable all interrupts */
938 sc16is7xx_port_write(port, SC16IS7XX_IER_REG, 0);
939 /* Disable TX/RX */
940 sc16is7xx_port_write(port, SC16IS7XX_EFCR_REG,
941 SC16IS7XX_EFCR_RXDISABLE_BIT |
942 SC16IS7XX_EFCR_TXDISABLE_BIT);
943
944 sc16is7xx_power(port, 0);
945}
946
947static const char *sc16is7xx_type(struct uart_port *port)
948{
949 struct sc16is7xx_port *s = dev_get_drvdata(port->dev);
950
951 return (port->type == PORT_SC16IS7XX) ? s->devtype->name : NULL;
952}
953
954static int sc16is7xx_request_port(struct uart_port *port)
955{
956 /* Do nothing */
957 return 0;
958}
959
960static void sc16is7xx_config_port(struct uart_port *port, int flags)
961{
962 if (flags & UART_CONFIG_TYPE)
963 port->type = PORT_SC16IS7XX;
964}
965
966static int sc16is7xx_verify_port(struct uart_port *port,
967 struct serial_struct *s)
968{
969 if ((s->type != PORT_UNKNOWN) && (s->type != PORT_SC16IS7XX))
970 return -EINVAL;
971 if (s->irq != port->irq)
972 return -EINVAL;
973
974 return 0;
975}
976
977static void sc16is7xx_pm(struct uart_port *port, unsigned int state,
978 unsigned int oldstate)
979{
980 sc16is7xx_power(port, (state == UART_PM_STATE_ON) ? 1 : 0);
981}
982
983static void sc16is7xx_null_void(struct uart_port *port)
984{
985 /* Do nothing */
986}
987
988static const struct uart_ops sc16is7xx_ops = {
989 .tx_empty = sc16is7xx_tx_empty,
990 .set_mctrl = sc16is7xx_set_mctrl,
991 .get_mctrl = sc16is7xx_get_mctrl,
992 .stop_tx = sc16is7xx_stop_tx,
993 .start_tx = sc16is7xx_start_tx,
994 .stop_rx = sc16is7xx_stop_rx,
995 .enable_ms = sc16is7xx_null_void,
996 .break_ctl = sc16is7xx_break_ctl,
997 .startup = sc16is7xx_startup,
998 .shutdown = sc16is7xx_shutdown,
999 .set_termios = sc16is7xx_set_termios,
1000 .type = sc16is7xx_type,
1001 .request_port = sc16is7xx_request_port,
1002 .release_port = sc16is7xx_null_void,
1003 .config_port = sc16is7xx_config_port,
1004 .verify_port = sc16is7xx_verify_port,
1005 .ioctl = sc16is7xx_ioctl,
1006 .pm = sc16is7xx_pm,
1007};
1008
1009#ifdef CONFIG_GPIOLIB
1010static int sc16is7xx_gpio_get(struct gpio_chip *chip, unsigned offset)
1011{
1012 unsigned int val;
1013 struct sc16is7xx_port *s = container_of(chip, struct sc16is7xx_port,
1014 gpio);
1015 struct uart_port *port = &s->p[0].port;
1016
1017 val = sc16is7xx_port_read(port, SC16IS7XX_IOSTATE_REG);
1018
1019 return !!(val & BIT(offset));
1020}
1021
1022static void sc16is7xx_gpio_set(struct gpio_chip *chip, unsigned offset, int val)
1023{
1024 struct sc16is7xx_port *s = container_of(chip, struct sc16is7xx_port,
1025 gpio);
1026 struct uart_port *port = &s->p[0].port;
1027
1028 sc16is7xx_port_update(port, SC16IS7XX_IOSTATE_REG, BIT(offset),
1029 val ? BIT(offset) : 0);
1030}
1031
1032static int sc16is7xx_gpio_direction_input(struct gpio_chip *chip,
1033 unsigned offset)
1034{
1035 struct sc16is7xx_port *s = container_of(chip, struct sc16is7xx_port,
1036 gpio);
1037 struct uart_port *port = &s->p[0].port;
1038
1039 sc16is7xx_port_update(port, SC16IS7XX_IODIR_REG, BIT(offset), 0);
1040
1041 return 0;
1042}
1043
1044static int sc16is7xx_gpio_direction_output(struct gpio_chip *chip,
1045 unsigned offset, int val)
1046{
1047 struct sc16is7xx_port *s = container_of(chip, struct sc16is7xx_port,
1048 gpio);
1049 struct uart_port *port = &s->p[0].port;
1050
1051 sc16is7xx_port_update(port, SC16IS7XX_IOSTATE_REG, BIT(offset),
1052 val ? BIT(offset) : 0);
1053 sc16is7xx_port_update(port, SC16IS7XX_IODIR_REG, BIT(offset),
1054 BIT(offset));
1055
1056 return 0;
1057}
1058#endif
1059
1060static int sc16is7xx_probe(struct device *dev,
1061 struct sc16is7xx_devtype *devtype,
1062 struct regmap *regmap, int irq, unsigned long flags)
1063{
1064 unsigned long freq, *pfreq = dev_get_platdata(dev);
1065 struct clk *clk;
1066 int i, ret;
1067 struct sc16is7xx_port *s;
1068
1069 if (IS_ERR(regmap))
1070 return PTR_ERR(regmap);
1071
1072 /* Alloc port structure */
1073 s = devm_kzalloc(dev, sizeof(*s) +
1074 sizeof(struct sc16is7xx_one) * devtype->nr_uart,
1075 GFP_KERNEL);
1076 if (!s) {
1077 dev_err(dev, "Error allocating port structure\n");
1078 return -ENOMEM;
1079 }
1080
1081 clk = devm_clk_get(dev, NULL);
1082 if (IS_ERR(clk)) {
1083 if (pfreq)
1084 freq = *pfreq;
1085 else
1086 return PTR_ERR(clk);
1087 } else {
1088 freq = clk_get_rate(clk);
1089 }
1090
1091 s->regmap = regmap;
1092 s->devtype = devtype;
1093 dev_set_drvdata(dev, s);
1094
1095 /* Register UART driver */
1096 s->uart.owner = THIS_MODULE;
1097 s->uart.dev_name = "ttySC";
1098 s->uart.nr = devtype->nr_uart;
1099 ret = uart_register_driver(&s->uart);
1100 if (ret) {
1101 dev_err(dev, "Registering UART driver failed\n");
1102 goto out_clk;
1103 }
1104
1105#ifdef CONFIG_GPIOLIB
1106 if (devtype->nr_gpio) {
1107 /* Setup GPIO cotroller */
1108 s->gpio.owner = THIS_MODULE;
1109 s->gpio.dev = dev;
1110 s->gpio.label = dev_name(dev);
1111 s->gpio.direction_input = sc16is7xx_gpio_direction_input;
1112 s->gpio.get = sc16is7xx_gpio_get;
1113 s->gpio.direction_output = sc16is7xx_gpio_direction_output;
1114 s->gpio.set = sc16is7xx_gpio_set;
1115 s->gpio.base = -1;
1116 s->gpio.ngpio = devtype->nr_gpio;
1117 s->gpio.can_sleep = 1;
1118 ret = gpiochip_add(&s->gpio);
1119 if (ret)
1120 goto out_uart;
1121 }
1122#endif
1123
1124 mutex_init(&s->mutex);
1125
1126 for (i = 0; i < devtype->nr_uart; ++i) {
1127 /* Initialize port data */
1128 s->p[i].port.line = i;
1129 s->p[i].port.dev = dev;
1130 s->p[i].port.irq = irq;
1131 s->p[i].port.type = PORT_SC16IS7XX;
1132 s->p[i].port.fifosize = SC16IS7XX_FIFO_SIZE;
1133 s->p[i].port.flags = UPF_FIXED_TYPE | UPF_LOW_LATENCY;
1134 s->p[i].port.iotype = UPIO_PORT;
1135 s->p[i].port.uartclk = freq;
1136 s->p[i].port.ops = &sc16is7xx_ops;
1137 /* Disable all interrupts */
1138 sc16is7xx_port_write(&s->p[i].port, SC16IS7XX_IER_REG, 0);
1139 /* Disable TX/RX */
1140 sc16is7xx_port_write(&s->p[i].port, SC16IS7XX_EFCR_REG,
1141 SC16IS7XX_EFCR_RXDISABLE_BIT |
1142 SC16IS7XX_EFCR_TXDISABLE_BIT);
1143 /* Initialize queue for start TX */
1144 INIT_WORK(&s->p[i].tx_work, sc16is7xx_wq_proc);
1145 /* Initialize queue for changing mode */
1146 INIT_WORK(&s->p[i].md_work, sc16is7xx_md_proc);
1147 /* Register port */
1148 uart_add_one_port(&s->uart, &s->p[i].port);
1149 /* Go to suspend mode */
1150 sc16is7xx_power(&s->p[i].port, 0);
1151 }
1152
1153 /* Setup interrupt */
1154 ret = devm_request_threaded_irq(dev, irq, NULL, sc16is7xx_ist,
1155 IRQF_ONESHOT | flags, dev_name(dev), s);
1156 if (!ret)
1157 return 0;
1158
1159 mutex_destroy(&s->mutex);
1160
1161#ifdef CONFIG_GPIOLIB
1162 if (devtype->nr_gpio)
1163 WARN_ON(gpiochip_remove(&s->gpio));
1164
1165out_uart:
1166#endif
1167 uart_unregister_driver(&s->uart);
1168
1169out_clk:
1170 if (!IS_ERR(s->clk))
1171 clk_disable_unprepare(s->clk);
1172
1173 return ret;
1174}
1175
1176static int sc16is7xx_remove(struct device *dev)
1177{
1178 struct sc16is7xx_port *s = dev_get_drvdata(dev);
1179 int i, ret = 0;
1180
1181#ifdef CONFIG_GPIOLIB
1182 if (s->devtype->nr_gpio) {
1183 ret = gpiochip_remove(&s->gpio);
1184 if (ret)
1185 return ret;
1186 }
1187#endif
1188
1189 for (i = 0; i < s->uart.nr; i++) {
1190 cancel_work_sync(&s->p[i].tx_work);
1191 cancel_work_sync(&s->p[i].md_work);
1192 uart_remove_one_port(&s->uart, &s->p[i].port);
1193 sc16is7xx_power(&s->p[i].port, 0);
1194 }
1195
1196 mutex_destroy(&s->mutex);
1197 uart_unregister_driver(&s->uart);
1198 if (!IS_ERR(s->clk))
1199 clk_disable_unprepare(s->clk);
1200
1201 return ret;
1202}
1203
1204static const struct of_device_id __maybe_unused sc16is7xx_dt_ids[] = {
1205 { .compatible = "nxp,sc16is740", .data = &sc16is74x_devtype, },
1206 { .compatible = "nxp,sc16is741", .data = &sc16is74x_devtype, },
1207 { .compatible = "nxp,sc16is750", .data = &sc16is750_devtype, },
1208 { .compatible = "nxp,sc16is752", .data = &sc16is752_devtype, },
1209 { .compatible = "nxp,sc16is760", .data = &sc16is760_devtype, },
1210 { .compatible = "nxp,sc16is762", .data = &sc16is762_devtype, },
1211 { }
1212};
1213MODULE_DEVICE_TABLE(of, sc16is7xx_dt_ids);
1214
1215static struct regmap_config regcfg = {
1216 .reg_bits = 7,
1217 .pad_bits = 1,
1218 .val_bits = 8,
1219 .cache_type = REGCACHE_RBTREE,
1220 .volatile_reg = sc16is7xx_regmap_volatile,
1221 .precious_reg = sc16is7xx_regmap_precious,
1222};
1223
1224#ifdef CONFIG_REGMAP_I2C
1225static int sc16is7xx_i2c_probe(struct i2c_client *i2c,
1226 const struct i2c_device_id *id)
1227{
1228 struct sc16is7xx_devtype *devtype;
1229 unsigned long flags = 0;
1230 struct regmap *regmap;
1231
1232 if (i2c->dev.of_node) {
1233 const struct of_device_id *of_id =
1234 of_match_device(sc16is7xx_dt_ids, &i2c->dev);
1235
1236 devtype = (struct sc16is7xx_devtype *)of_id->data;
1237 } else {
1238 devtype = (struct sc16is7xx_devtype *)id->driver_data;
1239 flags = IRQF_TRIGGER_FALLING;
1240 }
1241
1242 regcfg.max_register = (0xf << SC16IS7XX_REG_SHIFT) |
1243 (devtype->nr_uart - 1);
1244 regmap = devm_regmap_init_i2c(i2c, &regcfg);
1245
1246 return sc16is7xx_probe(&i2c->dev, devtype, regmap, i2c->irq, flags);
1247}
1248
1249static int sc16is7xx_i2c_remove(struct i2c_client *client)
1250{
1251 return sc16is7xx_remove(&client->dev);
1252}
1253
1254static const struct i2c_device_id sc16is7xx_i2c_id_table[] = {
1255 { "sc16is74x", (kernel_ulong_t)&sc16is74x_devtype, },
1256 { "sc16is750", (kernel_ulong_t)&sc16is750_devtype, },
1257 { "sc16is752", (kernel_ulong_t)&sc16is752_devtype, },
1258 { "sc16is760", (kernel_ulong_t)&sc16is760_devtype, },
1259 { "sc16is762", (kernel_ulong_t)&sc16is762_devtype, },
1260 { }
1261};
1262MODULE_DEVICE_TABLE(i2c, sc16is7xx_i2c_id_table);
1263
1264static struct i2c_driver sc16is7xx_i2c_uart_driver = {
1265 .driver = {
1266 .name = SC16IS7XX_NAME,
1267 .owner = THIS_MODULE,
1268 .of_match_table = of_match_ptr(sc16is7xx_dt_ids),
1269 },
1270 .probe = sc16is7xx_i2c_probe,
1271 .remove = sc16is7xx_i2c_remove,
1272 .id_table = sc16is7xx_i2c_id_table,
1273};
1274module_i2c_driver(sc16is7xx_i2c_uart_driver);
1275MODULE_ALIAS("i2c:sc16is7xx");
1276#endif
1277
1278MODULE_LICENSE("GPL");
1279MODULE_AUTHOR("Jon Ringle <jringle@gridpoint.com>");
1280MODULE_DESCRIPTION("SC16IS7XX serial driver");
diff --git a/drivers/tty/serial/serial_core.c b/drivers/tty/serial/serial_core.c
index b68550d95a40..9a01ee4dda6d 100644
--- a/drivers/tty/serial/serial_core.c
+++ b/drivers/tty/serial/serial_core.c
@@ -2239,6 +2239,9 @@ static void uart_poll_put_char(struct tty_driver *driver, int line, char ch)
2239 return; 2239 return;
2240 2240
2241 port = state->uart_port; 2241 port = state->uart_port;
2242
2243 if (ch == '\n')
2244 port->ops->poll_put_char(port, '\r');
2242 port->ops->poll_put_char(port, ch); 2245 port->ops->poll_put_char(port, ch);
2243} 2246}
2244#endif 2247#endif
diff --git a/drivers/tty/serial/serial_txx9.c b/drivers/tty/serial/serial_txx9.c
index 90a080b1f9ee..60f49b9d7e39 100644
--- a/drivers/tty/serial/serial_txx9.c
+++ b/drivers/tty/serial/serial_txx9.c
@@ -535,13 +535,8 @@ static void serial_txx9_put_poll_char(struct uart_port *port, unsigned char c)
535 wait_for_xmitr(up); 535 wait_for_xmitr(up);
536 /* 536 /*
537 * Send the character out. 537 * Send the character out.
538 * If a LF, also do CR...
539 */ 538 */
540 sio_out(up, TXX9_SITFIFO, c); 539 sio_out(up, TXX9_SITFIFO, c);
541 if (c == 10) {
542 wait_for_xmitr(up);
543 sio_out(up, TXX9_SITFIFO, 13);
544 }
545 540
546 /* 541 /*
547 * Finally, wait for transmitter to become empty 542 * Finally, wait for transmitter to become empty
diff --git a/drivers/tty/serial/xilinx_uartps.c b/drivers/tty/serial/xilinx_uartps.c
index f619ad5b5eae..8809775e2ba3 100644
--- a/drivers/tty/serial/xilinx_uartps.c
+++ b/drivers/tty/serial/xilinx_uartps.c
@@ -1,7 +1,7 @@
1/* 1/*
2 * Xilinx PS UART driver 2 * Cadence UART driver (found in Xilinx Zynq)
3 * 3 *
4 * 2011 - 2013 (C) Xilinx Inc. 4 * 2011 - 2014 (C) Xilinx Inc.
5 * 5 *
6 * This program is free software; you can redistribute it 6 * This program is free software; you can redistribute it
7 * and/or modify it under the terms of the GNU General Public 7 * and/or modify it under the terms of the GNU General Public
@@ -9,6 +9,9 @@
9 * either version 2 of the License, or (at your option) any 9 * either version 2 of the License, or (at your option) any
10 * later version. 10 * later version.
11 * 11 *
12 * This driver has originally been pushed by Xilinx using a Zynq-branding. This
13 * still shows in the naming of this file, the kconfig symbols and some symbols
14 * in the code.
12 */ 15 */
13 16
14#if defined(CONFIG_SERIAL_XILINX_PS_UART_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ) 17#if defined(CONFIG_SERIAL_XILINX_PS_UART_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
@@ -28,16 +31,16 @@
28#include <linux/of.h> 31#include <linux/of.h>
29#include <linux/module.h> 32#include <linux/module.h>
30 33
31#define XUARTPS_TTY_NAME "ttyPS" 34#define CDNS_UART_TTY_NAME "ttyPS"
32#define XUARTPS_NAME "xuartps" 35#define CDNS_UART_NAME "xuartps"
33#define XUARTPS_MAJOR 0 /* use dynamic node allocation */ 36#define CDNS_UART_MAJOR 0 /* use dynamic node allocation */
34#define XUARTPS_MINOR 0 /* works best with devtmpfs */ 37#define CDNS_UART_MINOR 0 /* works best with devtmpfs */
35#define XUARTPS_NR_PORTS 2 38#define CDNS_UART_NR_PORTS 2
36#define XUARTPS_FIFO_SIZE 64 /* FIFO size */ 39#define CDNS_UART_FIFO_SIZE 64 /* FIFO size */
37#define XUARTPS_REGISTER_SPACE 0xFFF 40#define CDNS_UART_REGISTER_SPACE 0xFFF
38 41
39#define xuartps_readl(offset) ioread32(port->membase + offset) 42#define cdns_uart_readl(offset) ioread32(port->membase + offset)
40#define xuartps_writel(val, offset) iowrite32(val, port->membase + offset) 43#define cdns_uart_writel(val, offset) iowrite32(val, port->membase + offset)
41 44
42/* Rx Trigger level */ 45/* Rx Trigger level */
43static int rx_trigger_level = 56; 46static int rx_trigger_level = 56;
@@ -49,77 +52,62 @@ static int rx_timeout = 10;
49module_param(rx_timeout, uint, S_IRUGO); 52module_param(rx_timeout, uint, S_IRUGO);
50MODULE_PARM_DESC(rx_timeout, "Rx timeout, 1-255"); 53MODULE_PARM_DESC(rx_timeout, "Rx timeout, 1-255");
51 54
52/********************************Register Map********************************/ 55/* Register offsets for the UART. */
53/** UART 56#define CDNS_UART_CR_OFFSET 0x00 /* Control Register */
54 * 57#define CDNS_UART_MR_OFFSET 0x04 /* Mode Register */
55 * Register offsets for the UART. 58#define CDNS_UART_IER_OFFSET 0x08 /* Interrupt Enable */
56 * 59#define CDNS_UART_IDR_OFFSET 0x0C /* Interrupt Disable */
57 */ 60#define CDNS_UART_IMR_OFFSET 0x10 /* Interrupt Mask */
58#define XUARTPS_CR_OFFSET 0x00 /* Control Register [8:0] */ 61#define CDNS_UART_ISR_OFFSET 0x14 /* Interrupt Status */
59#define XUARTPS_MR_OFFSET 0x04 /* Mode Register [10:0] */ 62#define CDNS_UART_BAUDGEN_OFFSET 0x18 /* Baud Rate Generator */
60#define XUARTPS_IER_OFFSET 0x08 /* Interrupt Enable [10:0] */ 63#define CDNS_UART_RXTOUT_OFFSET 0x1C /* RX Timeout */
61#define XUARTPS_IDR_OFFSET 0x0C /* Interrupt Disable [10:0] */ 64#define CDNS_UART_RXWM_OFFSET 0x20 /* RX FIFO Trigger Level */
62#define XUARTPS_IMR_OFFSET 0x10 /* Interrupt Mask [10:0] */ 65#define CDNS_UART_MODEMCR_OFFSET 0x24 /* Modem Control */
63#define XUARTPS_ISR_OFFSET 0x14 /* Interrupt Status [10:0]*/ 66#define CDNS_UART_MODEMSR_OFFSET 0x28 /* Modem Status */
64#define XUARTPS_BAUDGEN_OFFSET 0x18 /* Baud Rate Generator [15:0] */ 67#define CDNS_UART_SR_OFFSET 0x2C /* Channel Status */
65#define XUARTPS_RXTOUT_OFFSET 0x1C /* RX Timeout [7:0] */ 68#define CDNS_UART_FIFO_OFFSET 0x30 /* FIFO */
66#define XUARTPS_RXWM_OFFSET 0x20 /* RX FIFO Trigger Level [5:0] */ 69#define CDNS_UART_BAUDDIV_OFFSET 0x34 /* Baud Rate Divider */
67#define XUARTPS_MODEMCR_OFFSET 0x24 /* Modem Control [5:0] */ 70#define CDNS_UART_FLOWDEL_OFFSET 0x38 /* Flow Delay */
68#define XUARTPS_MODEMSR_OFFSET 0x28 /* Modem Status [8:0] */ 71#define CDNS_UART_IRRX_PWIDTH_OFFSET 0x3C /* IR Min Received Pulse Width */
69#define XUARTPS_SR_OFFSET 0x2C /* Channel Status [11:0] */ 72#define CDNS_UART_IRTX_PWIDTH_OFFSET 0x40 /* IR Transmitted pulse Width */
70#define XUARTPS_FIFO_OFFSET 0x30 /* FIFO [15:0] or [7:0] */ 73#define CDNS_UART_TXWM_OFFSET 0x44 /* TX FIFO Trigger Level */
71#define XUARTPS_BAUDDIV_OFFSET 0x34 /* Baud Rate Divider [7:0] */ 74
72#define XUARTPS_FLOWDEL_OFFSET 0x38 /* Flow Delay [15:0] */ 75/* Control Register Bit Definitions */
73#define XUARTPS_IRRX_PWIDTH_OFFSET 0x3C /* IR Minimum Received Pulse 76#define CDNS_UART_CR_STOPBRK 0x00000100 /* Stop TX break */
74 Width [15:0] */ 77#define CDNS_UART_CR_STARTBRK 0x00000080 /* Set TX break */
75#define XUARTPS_IRTX_PWIDTH_OFFSET 0x40 /* IR Transmitted pulse 78#define CDNS_UART_CR_TX_DIS 0x00000020 /* TX disabled. */
76 Width [7:0] */ 79#define CDNS_UART_CR_TX_EN 0x00000010 /* TX enabled */
77#define XUARTPS_TXWM_OFFSET 0x44 /* TX FIFO Trigger Level [5:0] */ 80#define CDNS_UART_CR_RX_DIS 0x00000008 /* RX disabled. */
78 81#define CDNS_UART_CR_RX_EN 0x00000004 /* RX enabled */
79/** Control Register 82#define CDNS_UART_CR_TXRST 0x00000002 /* TX logic reset */
80 * 83#define CDNS_UART_CR_RXRST 0x00000001 /* RX logic reset */
81 * The Control register (CR) controls the major functions of the device. 84#define CDNS_UART_CR_RST_TO 0x00000040 /* Restart Timeout Counter */
82 * 85
83 * Control Register Bit Definitions 86/*
84 */ 87 * Mode Register:
85#define XUARTPS_CR_STOPBRK 0x00000100 /* Stop TX break */
86#define XUARTPS_CR_STARTBRK 0x00000080 /* Set TX break */
87#define XUARTPS_CR_TX_DIS 0x00000020 /* TX disabled. */
88#define XUARTPS_CR_TX_EN 0x00000010 /* TX enabled */
89#define XUARTPS_CR_RX_DIS 0x00000008 /* RX disabled. */
90#define XUARTPS_CR_RX_EN 0x00000004 /* RX enabled */
91#define XUARTPS_CR_TXRST 0x00000002 /* TX logic reset */
92#define XUARTPS_CR_RXRST 0x00000001 /* RX logic reset */
93#define XUARTPS_CR_RST_TO 0x00000040 /* Restart Timeout Counter */
94
95/** Mode Register
96 *
97 * The mode register (MR) defines the mode of transfer as well as the data 88 * The mode register (MR) defines the mode of transfer as well as the data
98 * format. If this register is modified during transmission or reception, 89 * format. If this register is modified during transmission or reception,
99 * data validity cannot be guaranteed. 90 * data validity cannot be guaranteed.
100 *
101 * Mode Register Bit Definitions
102 *
103 */ 91 */
104#define XUARTPS_MR_CLKSEL 0x00000001 /* Pre-scalar selection */ 92#define CDNS_UART_MR_CLKSEL 0x00000001 /* Pre-scalar selection */
105#define XUARTPS_MR_CHMODE_L_LOOP 0x00000200 /* Local loop back mode */ 93#define CDNS_UART_MR_CHMODE_L_LOOP 0x00000200 /* Local loop back mode */
106#define XUARTPS_MR_CHMODE_NORM 0x00000000 /* Normal mode */ 94#define CDNS_UART_MR_CHMODE_NORM 0x00000000 /* Normal mode */
107 95
108#define XUARTPS_MR_STOPMODE_2_BIT 0x00000080 /* 2 stop bits */ 96#define CDNS_UART_MR_STOPMODE_2_BIT 0x00000080 /* 2 stop bits */
109#define XUARTPS_MR_STOPMODE_1_BIT 0x00000000 /* 1 stop bit */ 97#define CDNS_UART_MR_STOPMODE_1_BIT 0x00000000 /* 1 stop bit */
110 98
111#define XUARTPS_MR_PARITY_NONE 0x00000020 /* No parity mode */ 99#define CDNS_UART_MR_PARITY_NONE 0x00000020 /* No parity mode */
112#define XUARTPS_MR_PARITY_MARK 0x00000018 /* Mark parity mode */ 100#define CDNS_UART_MR_PARITY_MARK 0x00000018 /* Mark parity mode */
113#define XUARTPS_MR_PARITY_SPACE 0x00000010 /* Space parity mode */ 101#define CDNS_UART_MR_PARITY_SPACE 0x00000010 /* Space parity mode */
114#define XUARTPS_MR_PARITY_ODD 0x00000008 /* Odd parity mode */ 102#define CDNS_UART_MR_PARITY_ODD 0x00000008 /* Odd parity mode */
115#define XUARTPS_MR_PARITY_EVEN 0x00000000 /* Even parity mode */ 103#define CDNS_UART_MR_PARITY_EVEN 0x00000000 /* Even parity mode */
116 104
117#define XUARTPS_MR_CHARLEN_6_BIT 0x00000006 /* 6 bits data */ 105#define CDNS_UART_MR_CHARLEN_6_BIT 0x00000006 /* 6 bits data */
118#define XUARTPS_MR_CHARLEN_7_BIT 0x00000004 /* 7 bits data */ 106#define CDNS_UART_MR_CHARLEN_7_BIT 0x00000004 /* 7 bits data */
119#define XUARTPS_MR_CHARLEN_8_BIT 0x00000000 /* 8 bits data */ 107#define CDNS_UART_MR_CHARLEN_8_BIT 0x00000000 /* 8 bits data */
120 108
121/** Interrupt Registers 109/*
122 * 110 * Interrupt Registers:
123 * Interrupt control logic uses the interrupt enable register (IER) and the 111 * Interrupt control logic uses the interrupt enable register (IER) and the
124 * interrupt disable register (IDR) to set the value of the bits in the 112 * interrupt disable register (IDR) to set the value of the bits in the
125 * interrupt mask register (IMR). The IMR determines whether to pass an 113 * interrupt mask register (IMR). The IMR determines whether to pass an
@@ -127,65 +115,65 @@ MODULE_PARM_DESC(rx_timeout, "Rx timeout, 1-255");
127 * Writing a 1 to IER Enables an interrupt, writing a 1 to IDR disables an 115 * Writing a 1 to IER Enables an interrupt, writing a 1 to IDR disables an
128 * interrupt. IMR and ISR are read only, and IER and IDR are write only. 116 * interrupt. IMR and ISR are read only, and IER and IDR are write only.
129 * Reading either IER or IDR returns 0x00. 117 * Reading either IER or IDR returns 0x00.
130 *
131 * All four registers have the same bit definitions. 118 * All four registers have the same bit definitions.
132 */ 119 */
133#define XUARTPS_IXR_TOUT 0x00000100 /* RX Timeout error interrupt */ 120#define CDNS_UART_IXR_TOUT 0x00000100 /* RX Timeout error interrupt */
134#define XUARTPS_IXR_PARITY 0x00000080 /* Parity error interrupt */ 121#define CDNS_UART_IXR_PARITY 0x00000080 /* Parity error interrupt */
135#define XUARTPS_IXR_FRAMING 0x00000040 /* Framing error interrupt */ 122#define CDNS_UART_IXR_FRAMING 0x00000040 /* Framing error interrupt */
136#define XUARTPS_IXR_OVERRUN 0x00000020 /* Overrun error interrupt */ 123#define CDNS_UART_IXR_OVERRUN 0x00000020 /* Overrun error interrupt */
137#define XUARTPS_IXR_TXFULL 0x00000010 /* TX FIFO Full interrupt */ 124#define CDNS_UART_IXR_TXFULL 0x00000010 /* TX FIFO Full interrupt */
138#define XUARTPS_IXR_TXEMPTY 0x00000008 /* TX FIFO empty interrupt */ 125#define CDNS_UART_IXR_TXEMPTY 0x00000008 /* TX FIFO empty interrupt */
139#define XUARTPS_ISR_RXEMPTY 0x00000002 /* RX FIFO empty interrupt */ 126#define CDNS_UART_ISR_RXEMPTY 0x00000002 /* RX FIFO empty interrupt */
140#define XUARTPS_IXR_RXTRIG 0x00000001 /* RX FIFO trigger interrupt */ 127#define CDNS_UART_IXR_RXTRIG 0x00000001 /* RX FIFO trigger interrupt */
141#define XUARTPS_IXR_RXFULL 0x00000004 /* RX FIFO full interrupt. */ 128#define CDNS_UART_IXR_RXFULL 0x00000004 /* RX FIFO full interrupt. */
142#define XUARTPS_IXR_RXEMPTY 0x00000002 /* RX FIFO empty interrupt. */ 129#define CDNS_UART_IXR_RXEMPTY 0x00000002 /* RX FIFO empty interrupt. */
143#define XUARTPS_IXR_MASK 0x00001FFF /* Valid bit mask */ 130#define CDNS_UART_IXR_MASK 0x00001FFF /* Valid bit mask */
144 131
145/* Goes in read_status_mask for break detection as the HW doesn't do it*/ 132/* Goes in read_status_mask for break detection as the HW doesn't do it*/
146#define XUARTPS_IXR_BRK 0x80000000 133#define CDNS_UART_IXR_BRK 0x80000000
147 134
148/** Channel Status Register 135/*
149 * 136 * Channel Status Register:
150 * The channel status register (CSR) is provided to enable the control logic 137 * The channel status register (CSR) is provided to enable the control logic
151 * to monitor the status of bits in the channel interrupt status register, 138 * to monitor the status of bits in the channel interrupt status register,
152 * even if these are masked out by the interrupt mask register. 139 * even if these are masked out by the interrupt mask register.
153 */ 140 */
154#define XUARTPS_SR_RXEMPTY 0x00000002 /* RX FIFO empty */ 141#define CDNS_UART_SR_RXEMPTY 0x00000002 /* RX FIFO empty */
155#define XUARTPS_SR_TXEMPTY 0x00000008 /* TX FIFO empty */ 142#define CDNS_UART_SR_TXEMPTY 0x00000008 /* TX FIFO empty */
156#define XUARTPS_SR_TXFULL 0x00000010 /* TX FIFO full */ 143#define CDNS_UART_SR_TXFULL 0x00000010 /* TX FIFO full */
157#define XUARTPS_SR_RXTRIG 0x00000001 /* Rx Trigger */ 144#define CDNS_UART_SR_RXTRIG 0x00000001 /* Rx Trigger */
158 145
159/* baud dividers min/max values */ 146/* baud dividers min/max values */
160#define XUARTPS_BDIV_MIN 4 147#define CDNS_UART_BDIV_MIN 4
161#define XUARTPS_BDIV_MAX 255 148#define CDNS_UART_BDIV_MAX 255
162#define XUARTPS_CD_MAX 65535 149#define CDNS_UART_CD_MAX 65535
163 150
164/** 151/**
165 * struct xuartps - device data 152 * struct cdns_uart - device data
166 * @port Pointer to the UART port 153 * @port: Pointer to the UART port
167 * @refclk Reference clock 154 * @uartclk: Reference clock
168 * @aperclk APB clock 155 * @pclk: APB clock
169 * @baud Current baud rate 156 * @baud: Current baud rate
170 * @clk_rate_change_nb Notifier block for clock changes 157 * @clk_rate_change_nb: Notifier block for clock changes
171 */ 158 */
172struct xuartps { 159struct cdns_uart {
173 struct uart_port *port; 160 struct uart_port *port;
174 struct clk *refclk; 161 struct clk *uartclk;
175 struct clk *aperclk; 162 struct clk *pclk;
176 unsigned int baud; 163 unsigned int baud;
177 struct notifier_block clk_rate_change_nb; 164 struct notifier_block clk_rate_change_nb;
178}; 165};
179#define to_xuartps(_nb) container_of(_nb, struct xuartps, clk_rate_change_nb); 166#define to_cdns_uart(_nb) container_of(_nb, struct cdns_uart, \
167 clk_rate_change_nb);
180 168
181/** 169/**
182 * xuartps_isr - Interrupt handler 170 * cdns_uart_isr - Interrupt handler
183 * @irq: Irq number 171 * @irq: Irq number
184 * @dev_id: Id of the port 172 * @dev_id: Id of the port
185 * 173 *
186 * Returns IRQHANDLED 174 * Return: IRQHANDLED
187 **/ 175 */
188static irqreturn_t xuartps_isr(int irq, void *dev_id) 176static irqreturn_t cdns_uart_isr(int irq, void *dev_id)
189{ 177{
190 struct uart_port *port = (struct uart_port *)dev_id; 178 struct uart_port *port = (struct uart_port *)dev_id;
191 unsigned long flags; 179 unsigned long flags;
@@ -198,43 +186,42 @@ static irqreturn_t xuartps_isr(int irq, void *dev_id)
198 /* Read the interrupt status register to determine which 186 /* Read the interrupt status register to determine which
199 * interrupt(s) is/are active. 187 * interrupt(s) is/are active.
200 */ 188 */
201 isrstatus = xuartps_readl(XUARTPS_ISR_OFFSET); 189 isrstatus = cdns_uart_readl(CDNS_UART_ISR_OFFSET);
202 190
203 /* 191 /*
204 * There is no hardware break detection, so we interpret framing 192 * There is no hardware break detection, so we interpret framing
205 * error with all-zeros data as a break sequence. Most of the time, 193 * error with all-zeros data as a break sequence. Most of the time,
206 * there's another non-zero byte at the end of the sequence. 194 * there's another non-zero byte at the end of the sequence.
207 */ 195 */
208 196 if (isrstatus & CDNS_UART_IXR_FRAMING) {
209 if (isrstatus & XUARTPS_IXR_FRAMING) { 197 while (!(cdns_uart_readl(CDNS_UART_SR_OFFSET) &
210 while (!(xuartps_readl(XUARTPS_SR_OFFSET) & 198 CDNS_UART_SR_RXEMPTY)) {
211 XUARTPS_SR_RXEMPTY)) { 199 if (!cdns_uart_readl(CDNS_UART_FIFO_OFFSET)) {
212 if (!xuartps_readl(XUARTPS_FIFO_OFFSET)) { 200 port->read_status_mask |= CDNS_UART_IXR_BRK;
213 port->read_status_mask |= XUARTPS_IXR_BRK; 201 isrstatus &= ~CDNS_UART_IXR_FRAMING;
214 isrstatus &= ~XUARTPS_IXR_FRAMING;
215 } 202 }
216 } 203 }
217 xuartps_writel(XUARTPS_IXR_FRAMING, XUARTPS_ISR_OFFSET); 204 cdns_uart_writel(CDNS_UART_IXR_FRAMING, CDNS_UART_ISR_OFFSET);
218 } 205 }
219 206
220 /* drop byte with parity error if IGNPAR specified */ 207 /* drop byte with parity error if IGNPAR specified */
221 if (isrstatus & port->ignore_status_mask & XUARTPS_IXR_PARITY) 208 if (isrstatus & port->ignore_status_mask & CDNS_UART_IXR_PARITY)
222 isrstatus &= ~(XUARTPS_IXR_RXTRIG | XUARTPS_IXR_TOUT); 209 isrstatus &= ~(CDNS_UART_IXR_RXTRIG | CDNS_UART_IXR_TOUT);
223 210
224 isrstatus &= port->read_status_mask; 211 isrstatus &= port->read_status_mask;
225 isrstatus &= ~port->ignore_status_mask; 212 isrstatus &= ~port->ignore_status_mask;
226 213
227 if ((isrstatus & XUARTPS_IXR_TOUT) || 214 if ((isrstatus & CDNS_UART_IXR_TOUT) ||
228 (isrstatus & XUARTPS_IXR_RXTRIG)) { 215 (isrstatus & CDNS_UART_IXR_RXTRIG)) {
229 /* Receive Timeout Interrupt */ 216 /* Receive Timeout Interrupt */
230 while ((xuartps_readl(XUARTPS_SR_OFFSET) & 217 while ((cdns_uart_readl(CDNS_UART_SR_OFFSET) &
231 XUARTPS_SR_RXEMPTY) != XUARTPS_SR_RXEMPTY) { 218 CDNS_UART_SR_RXEMPTY) != CDNS_UART_SR_RXEMPTY) {
232 data = xuartps_readl(XUARTPS_FIFO_OFFSET); 219 data = cdns_uart_readl(CDNS_UART_FIFO_OFFSET);
233 220
234 /* Non-NULL byte after BREAK is garbage (99%) */ 221 /* Non-NULL byte after BREAK is garbage (99%) */
235 if (data && (port->read_status_mask & 222 if (data && (port->read_status_mask &
236 XUARTPS_IXR_BRK)) { 223 CDNS_UART_IXR_BRK)) {
237 port->read_status_mask &= ~XUARTPS_IXR_BRK; 224 port->read_status_mask &= ~CDNS_UART_IXR_BRK;
238 port->icount.brk++; 225 port->icount.brk++;
239 if (uart_handle_break(port)) 226 if (uart_handle_break(port))
240 continue; 227 continue;
@@ -258,16 +245,17 @@ static irqreturn_t xuartps_isr(int irq, void *dev_id)
258 245
259 port->icount.rx++; 246 port->icount.rx++;
260 247
261 if (isrstatus & XUARTPS_IXR_PARITY) { 248 if (isrstatus & CDNS_UART_IXR_PARITY) {
262 port->icount.parity++; 249 port->icount.parity++;
263 status = TTY_PARITY; 250 status = TTY_PARITY;
264 } else if (isrstatus & XUARTPS_IXR_FRAMING) { 251 } else if (isrstatus & CDNS_UART_IXR_FRAMING) {
265 port->icount.frame++; 252 port->icount.frame++;
266 status = TTY_FRAME; 253 status = TTY_FRAME;
267 } else if (isrstatus & XUARTPS_IXR_OVERRUN) 254 } else if (isrstatus & CDNS_UART_IXR_OVERRUN) {
268 port->icount.overrun++; 255 port->icount.overrun++;
256 }
269 257
270 uart_insert_char(port, isrstatus, XUARTPS_IXR_OVERRUN, 258 uart_insert_char(port, isrstatus, CDNS_UART_IXR_OVERRUN,
271 data, status); 259 data, status);
272 } 260 }
273 spin_unlock(&port->lock); 261 spin_unlock(&port->lock);
@@ -276,10 +264,10 @@ static irqreturn_t xuartps_isr(int irq, void *dev_id)
276 } 264 }
277 265
278 /* Dispatch an appropriate handler */ 266 /* Dispatch an appropriate handler */
279 if ((isrstatus & XUARTPS_IXR_TXEMPTY) == XUARTPS_IXR_TXEMPTY) { 267 if ((isrstatus & CDNS_UART_IXR_TXEMPTY) == CDNS_UART_IXR_TXEMPTY) {
280 if (uart_circ_empty(&port->state->xmit)) { 268 if (uart_circ_empty(&port->state->xmit)) {
281 xuartps_writel(XUARTPS_IXR_TXEMPTY, 269 cdns_uart_writel(CDNS_UART_IXR_TXEMPTY,
282 XUARTPS_IDR_OFFSET); 270 CDNS_UART_IDR_OFFSET);
283 } else { 271 } else {
284 numbytes = port->fifosize; 272 numbytes = port->fifosize;
285 /* Break if no more data available in the UART buffer */ 273 /* Break if no more data available in the UART buffer */
@@ -287,12 +275,12 @@ static irqreturn_t xuartps_isr(int irq, void *dev_id)
287 if (uart_circ_empty(&port->state->xmit)) 275 if (uart_circ_empty(&port->state->xmit))
288 break; 276 break;
289 /* Get the data from the UART circular buffer 277 /* Get the data from the UART circular buffer
290 * and write it to the xuartps's TX_FIFO 278 * and write it to the cdns_uart's TX_FIFO
291 * register. 279 * register.
292 */ 280 */
293 xuartps_writel( 281 cdns_uart_writel(
294 port->state->xmit.buf[port->state->xmit. 282 port->state->xmit.buf[port->state->xmit.
295 tail], XUARTPS_FIFO_OFFSET); 283 tail], CDNS_UART_FIFO_OFFSET);
296 284
297 port->icount.tx++; 285 port->icount.tx++;
298 286
@@ -300,7 +288,7 @@ static irqreturn_t xuartps_isr(int irq, void *dev_id)
300 * the buffer if it reaches limit. 288 * the buffer if it reaches limit.
301 */ 289 */
302 port->state->xmit.tail = 290 port->state->xmit.tail =
303 (port->state->xmit.tail + 1) & \ 291 (port->state->xmit.tail + 1) &
304 (UART_XMIT_SIZE - 1); 292 (UART_XMIT_SIZE - 1);
305 } 293 }
306 294
@@ -310,7 +298,7 @@ static irqreturn_t xuartps_isr(int irq, void *dev_id)
310 } 298 }
311 } 299 }
312 300
313 xuartps_writel(isrstatus, XUARTPS_ISR_OFFSET); 301 cdns_uart_writel(isrstatus, CDNS_UART_ISR_OFFSET);
314 302
315 /* be sure to release the lock and tty before leaving */ 303 /* be sure to release the lock and tty before leaving */
316 spin_unlock_irqrestore(&port->lock, flags); 304 spin_unlock_irqrestore(&port->lock, flags);
@@ -319,13 +307,13 @@ static irqreturn_t xuartps_isr(int irq, void *dev_id)
319} 307}
320 308
321/** 309/**
322 * xuartps_calc_baud_divs - Calculate baud rate divisors 310 * cdns_uart_calc_baud_divs - Calculate baud rate divisors
323 * @clk: UART module input clock 311 * @clk: UART module input clock
324 * @baud: Desired baud rate 312 * @baud: Desired baud rate
325 * @rbdiv: BDIV value (return value) 313 * @rbdiv: BDIV value (return value)
326 * @rcd: CD value (return value) 314 * @rcd: CD value (return value)
327 * @div8: Value for clk_sel bit in mod (return value) 315 * @div8: Value for clk_sel bit in mod (return value)
328 * Returns baud rate, requested baud when possible, or actual baud when there 316 * Return: baud rate, requested baud when possible, or actual baud when there
329 * was too much error, zero if no valid divisors are found. 317 * was too much error, zero if no valid divisors are found.
330 * 318 *
331 * Formula to obtain baud rate is 319 * Formula to obtain baud rate is
@@ -338,8 +326,8 @@ static irqreturn_t xuartps_isr(int irq, void *dev_id)
338 * baud rate generate register 326 * baud rate generate register
339 * baud rate clock divisor register 327 * baud rate clock divisor register
340 */ 328 */
341static unsigned int xuartps_calc_baud_divs(unsigned int clk, unsigned int baud, 329static unsigned int cdns_uart_calc_baud_divs(unsigned int clk,
342 u32 *rbdiv, u32 *rcd, int *div8) 330 unsigned int baud, u32 *rbdiv, u32 *rcd, int *div8)
343{ 331{
344 u32 cd, bdiv; 332 u32 cd, bdiv;
345 unsigned int calc_baud; 333 unsigned int calc_baud;
@@ -347,16 +335,16 @@ static unsigned int xuartps_calc_baud_divs(unsigned int clk, unsigned int baud,
347 unsigned int bauderror; 335 unsigned int bauderror;
348 unsigned int besterror = ~0; 336 unsigned int besterror = ~0;
349 337
350 if (baud < clk / ((XUARTPS_BDIV_MAX + 1) * XUARTPS_CD_MAX)) { 338 if (baud < clk / ((CDNS_UART_BDIV_MAX + 1) * CDNS_UART_CD_MAX)) {
351 *div8 = 1; 339 *div8 = 1;
352 clk /= 8; 340 clk /= 8;
353 } else { 341 } else {
354 *div8 = 0; 342 *div8 = 0;
355 } 343 }
356 344
357 for (bdiv = XUARTPS_BDIV_MIN; bdiv <= XUARTPS_BDIV_MAX; bdiv++) { 345 for (bdiv = CDNS_UART_BDIV_MIN; bdiv <= CDNS_UART_BDIV_MAX; bdiv++) {
358 cd = DIV_ROUND_CLOSEST(clk, baud * (bdiv + 1)); 346 cd = DIV_ROUND_CLOSEST(clk, baud * (bdiv + 1));
359 if (cd < 1 || cd > XUARTPS_CD_MAX) 347 if (cd < 1 || cd > CDNS_UART_CD_MAX)
360 continue; 348 continue;
361 349
362 calc_baud = clk / (cd * (bdiv + 1)); 350 calc_baud = clk / (cd * (bdiv + 1));
@@ -381,47 +369,47 @@ static unsigned int xuartps_calc_baud_divs(unsigned int clk, unsigned int baud,
381} 369}
382 370
383/** 371/**
384 * xuartps_set_baud_rate - Calculate and set the baud rate 372 * cdns_uart_set_baud_rate - Calculate and set the baud rate
385 * @port: Handle to the uart port structure 373 * @port: Handle to the uart port structure
386 * @baud: Baud rate to set 374 * @baud: Baud rate to set
387 * Returns baud rate, requested baud when possible, or actual baud when there 375 * Return: baud rate, requested baud when possible, or actual baud when there
388 * was too much error, zero if no valid divisors are found. 376 * was too much error, zero if no valid divisors are found.
389 */ 377 */
390static unsigned int xuartps_set_baud_rate(struct uart_port *port, 378static unsigned int cdns_uart_set_baud_rate(struct uart_port *port,
391 unsigned int baud) 379 unsigned int baud)
392{ 380{
393 unsigned int calc_baud; 381 unsigned int calc_baud;
394 u32 cd = 0, bdiv = 0; 382 u32 cd = 0, bdiv = 0;
395 u32 mreg; 383 u32 mreg;
396 int div8; 384 int div8;
397 struct xuartps *xuartps = port->private_data; 385 struct cdns_uart *cdns_uart = port->private_data;
398 386
399 calc_baud = xuartps_calc_baud_divs(port->uartclk, baud, &bdiv, &cd, 387 calc_baud = cdns_uart_calc_baud_divs(port->uartclk, baud, &bdiv, &cd,
400 &div8); 388 &div8);
401 389
402 /* Write new divisors to hardware */ 390 /* Write new divisors to hardware */
403 mreg = xuartps_readl(XUARTPS_MR_OFFSET); 391 mreg = cdns_uart_readl(CDNS_UART_MR_OFFSET);
404 if (div8) 392 if (div8)
405 mreg |= XUARTPS_MR_CLKSEL; 393 mreg |= CDNS_UART_MR_CLKSEL;
406 else 394 else
407 mreg &= ~XUARTPS_MR_CLKSEL; 395 mreg &= ~CDNS_UART_MR_CLKSEL;
408 xuartps_writel(mreg, XUARTPS_MR_OFFSET); 396 cdns_uart_writel(mreg, CDNS_UART_MR_OFFSET);
409 xuartps_writel(cd, XUARTPS_BAUDGEN_OFFSET); 397 cdns_uart_writel(cd, CDNS_UART_BAUDGEN_OFFSET);
410 xuartps_writel(bdiv, XUARTPS_BAUDDIV_OFFSET); 398 cdns_uart_writel(bdiv, CDNS_UART_BAUDDIV_OFFSET);
411 xuartps->baud = baud; 399 cdns_uart->baud = baud;
412 400
413 return calc_baud; 401 return calc_baud;
414} 402}
415 403
416#ifdef CONFIG_COMMON_CLK 404#ifdef CONFIG_COMMON_CLK
417/** 405/**
418 * xuartps_clk_notitifer_cb - Clock notifier callback 406 * cdns_uart_clk_notitifer_cb - Clock notifier callback
419 * @nb: Notifier block 407 * @nb: Notifier block
420 * @event: Notify event 408 * @event: Notify event
421 * @data: Notifier data 409 * @data: Notifier data
422 * Returns NOTIFY_OK on success, NOTIFY_BAD on error. 410 * Return: NOTIFY_OK or NOTIFY_DONE on success, NOTIFY_BAD on error.
423 */ 411 */
424static int xuartps_clk_notifier_cb(struct notifier_block *nb, 412static int cdns_uart_clk_notifier_cb(struct notifier_block *nb,
425 unsigned long event, void *data) 413 unsigned long event, void *data)
426{ 414{
427 u32 ctrl_reg; 415 u32 ctrl_reg;
@@ -429,35 +417,36 @@ static int xuartps_clk_notifier_cb(struct notifier_block *nb,
429 int locked = 0; 417 int locked = 0;
430 struct clk_notifier_data *ndata = data; 418 struct clk_notifier_data *ndata = data;
431 unsigned long flags = 0; 419 unsigned long flags = 0;
432 struct xuartps *xuartps = to_xuartps(nb); 420 struct cdns_uart *cdns_uart = to_cdns_uart(nb);
433 421
434 port = xuartps->port; 422 port = cdns_uart->port;
435 if (port->suspended) 423 if (port->suspended)
436 return NOTIFY_OK; 424 return NOTIFY_OK;
437 425
438 switch (event) { 426 switch (event) {
439 case PRE_RATE_CHANGE: 427 case PRE_RATE_CHANGE:
440 { 428 {
441 u32 bdiv; 429 u32 bdiv, cd;
442 u32 cd;
443 int div8; 430 int div8;
444 431
445 /* 432 /*
446 * Find out if current baud-rate can be achieved with new clock 433 * Find out if current baud-rate can be achieved with new clock
447 * frequency. 434 * frequency.
448 */ 435 */
449 if (!xuartps_calc_baud_divs(ndata->new_rate, xuartps->baud, 436 if (!cdns_uart_calc_baud_divs(ndata->new_rate, cdns_uart->baud,
450 &bdiv, &cd, &div8)) 437 &bdiv, &cd, &div8)) {
438 dev_warn(port->dev, "clock rate change rejected\n");
451 return NOTIFY_BAD; 439 return NOTIFY_BAD;
440 }
452 441
453 spin_lock_irqsave(&xuartps->port->lock, flags); 442 spin_lock_irqsave(&cdns_uart->port->lock, flags);
454 443
455 /* Disable the TX and RX to set baud rate */ 444 /* Disable the TX and RX to set baud rate */
456 xuartps_writel(xuartps_readl(XUARTPS_CR_OFFSET) | 445 ctrl_reg = cdns_uart_readl(CDNS_UART_CR_OFFSET);
457 (XUARTPS_CR_TX_DIS | XUARTPS_CR_RX_DIS), 446 ctrl_reg |= CDNS_UART_CR_TX_DIS | CDNS_UART_CR_RX_DIS;
458 XUARTPS_CR_OFFSET); 447 cdns_uart_writel(ctrl_reg, CDNS_UART_CR_OFFSET);
459 448
460 spin_unlock_irqrestore(&xuartps->port->lock, flags); 449 spin_unlock_irqrestore(&cdns_uart->port->lock, flags);
461 450
462 return NOTIFY_OK; 451 return NOTIFY_OK;
463 } 452 }
@@ -467,25 +456,25 @@ static int xuartps_clk_notifier_cb(struct notifier_block *nb,
467 * frequency. 456 * frequency.
468 */ 457 */
469 458
470 spin_lock_irqsave(&xuartps->port->lock, flags); 459 spin_lock_irqsave(&cdns_uart->port->lock, flags);
471 460
472 locked = 1; 461 locked = 1;
473 port->uartclk = ndata->new_rate; 462 port->uartclk = ndata->new_rate;
474 463
475 xuartps->baud = xuartps_set_baud_rate(xuartps->port, 464 cdns_uart->baud = cdns_uart_set_baud_rate(cdns_uart->port,
476 xuartps->baud); 465 cdns_uart->baud);
477 /* fall through */ 466 /* fall through */
478 case ABORT_RATE_CHANGE: 467 case ABORT_RATE_CHANGE:
479 if (!locked) 468 if (!locked)
480 spin_lock_irqsave(&xuartps->port->lock, flags); 469 spin_lock_irqsave(&cdns_uart->port->lock, flags);
481 470
482 /* Set TX/RX Reset */ 471 /* Set TX/RX Reset */
483 xuartps_writel(xuartps_readl(XUARTPS_CR_OFFSET) | 472 ctrl_reg = cdns_uart_readl(CDNS_UART_CR_OFFSET);
484 (XUARTPS_CR_TXRST | XUARTPS_CR_RXRST), 473 ctrl_reg |= CDNS_UART_CR_TXRST | CDNS_UART_CR_RXRST;
485 XUARTPS_CR_OFFSET); 474 cdns_uart_writel(ctrl_reg, CDNS_UART_CR_OFFSET);
486 475
487 while (xuartps_readl(XUARTPS_CR_OFFSET) & 476 while (cdns_uart_readl(CDNS_UART_CR_OFFSET) &
488 (XUARTPS_CR_TXRST | XUARTPS_CR_RXRST)) 477 (CDNS_UART_CR_TXRST | CDNS_UART_CR_RXRST))
489 cpu_relax(); 478 cpu_relax();
490 479
491 /* 480 /*
@@ -493,14 +482,13 @@ static int xuartps_clk_notifier_cb(struct notifier_block *nb,
493 * enable bit and RX enable bit to enable the transmitter and 482 * enable bit and RX enable bit to enable the transmitter and
494 * receiver. 483 * receiver.
495 */ 484 */
496 xuartps_writel(rx_timeout, XUARTPS_RXTOUT_OFFSET); 485 cdns_uart_writel(rx_timeout, CDNS_UART_RXTOUT_OFFSET);
497 ctrl_reg = xuartps_readl(XUARTPS_CR_OFFSET); 486 ctrl_reg = cdns_uart_readl(CDNS_UART_CR_OFFSET);
498 xuartps_writel( 487 ctrl_reg &= ~(CDNS_UART_CR_TX_DIS | CDNS_UART_CR_RX_DIS);
499 (ctrl_reg & ~(XUARTPS_CR_TX_DIS | XUARTPS_CR_RX_DIS)) | 488 ctrl_reg |= CDNS_UART_CR_TX_EN | CDNS_UART_CR_RX_EN;
500 (XUARTPS_CR_TX_EN | XUARTPS_CR_RX_EN), 489 cdns_uart_writel(ctrl_reg, CDNS_UART_CR_OFFSET);
501 XUARTPS_CR_OFFSET);
502 490
503 spin_unlock_irqrestore(&xuartps->port->lock, flags); 491 spin_unlock_irqrestore(&cdns_uart->port->lock, flags);
504 492
505 return NOTIFY_OK; 493 return NOTIFY_OK;
506 default: 494 default:
@@ -509,40 +497,36 @@ static int xuartps_clk_notifier_cb(struct notifier_block *nb,
509} 497}
510#endif 498#endif
511 499
512/*----------------------Uart Operations---------------------------*/
513
514/** 500/**
515 * xuartps_start_tx - Start transmitting bytes 501 * cdns_uart_start_tx - Start transmitting bytes
516 * @port: Handle to the uart port structure 502 * @port: Handle to the uart port structure
517 * 503 */
518 **/ 504static void cdns_uart_start_tx(struct uart_port *port)
519static void xuartps_start_tx(struct uart_port *port)
520{ 505{
521 unsigned int status, numbytes = port->fifosize; 506 unsigned int status, numbytes = port->fifosize;
522 507
523 if (uart_circ_empty(&port->state->xmit) || uart_tx_stopped(port)) 508 if (uart_circ_empty(&port->state->xmit) || uart_tx_stopped(port))
524 return; 509 return;
525 510
526 status = xuartps_readl(XUARTPS_CR_OFFSET); 511 status = cdns_uart_readl(CDNS_UART_CR_OFFSET);
527 /* Set the TX enable bit and clear the TX disable bit to enable the 512 /* Set the TX enable bit and clear the TX disable bit to enable the
528 * transmitter. 513 * transmitter.
529 */ 514 */
530 xuartps_writel((status & ~XUARTPS_CR_TX_DIS) | XUARTPS_CR_TX_EN, 515 cdns_uart_writel((status & ~CDNS_UART_CR_TX_DIS) | CDNS_UART_CR_TX_EN,
531 XUARTPS_CR_OFFSET); 516 CDNS_UART_CR_OFFSET);
532
533 while (numbytes-- && ((xuartps_readl(XUARTPS_SR_OFFSET)
534 & XUARTPS_SR_TXFULL)) != XUARTPS_SR_TXFULL) {
535 517
518 while (numbytes-- && ((cdns_uart_readl(CDNS_UART_SR_OFFSET) &
519 CDNS_UART_SR_TXFULL)) != CDNS_UART_SR_TXFULL) {
536 /* Break if no more data available in the UART buffer */ 520 /* Break if no more data available in the UART buffer */
537 if (uart_circ_empty(&port->state->xmit)) 521 if (uart_circ_empty(&port->state->xmit))
538 break; 522 break;
539 523
540 /* Get the data from the UART circular buffer and 524 /* Get the data from the UART circular buffer and
541 * write it to the xuartps's TX_FIFO register. 525 * write it to the cdns_uart's TX_FIFO register.
542 */ 526 */
543 xuartps_writel( 527 cdns_uart_writel(
544 port->state->xmit.buf[port->state->xmit.tail], 528 port->state->xmit.buf[port->state->xmit.tail],
545 XUARTPS_FIFO_OFFSET); 529 CDNS_UART_FIFO_OFFSET);
546 port->icount.tx++; 530 port->icount.tx++;
547 531
548 /* Adjust the tail of the UART buffer and wrap 532 /* Adjust the tail of the UART buffer and wrap
@@ -551,94 +535,90 @@ static void xuartps_start_tx(struct uart_port *port)
551 port->state->xmit.tail = (port->state->xmit.tail + 1) & 535 port->state->xmit.tail = (port->state->xmit.tail + 1) &
552 (UART_XMIT_SIZE - 1); 536 (UART_XMIT_SIZE - 1);
553 } 537 }
554 xuartps_writel(XUARTPS_IXR_TXEMPTY, XUARTPS_ISR_OFFSET); 538 cdns_uart_writel(CDNS_UART_IXR_TXEMPTY, CDNS_UART_ISR_OFFSET);
555 /* Enable the TX Empty interrupt */ 539 /* Enable the TX Empty interrupt */
556 xuartps_writel(XUARTPS_IXR_TXEMPTY, XUARTPS_IER_OFFSET); 540 cdns_uart_writel(CDNS_UART_IXR_TXEMPTY, CDNS_UART_IER_OFFSET);
557 541
558 if (uart_circ_chars_pending(&port->state->xmit) < WAKEUP_CHARS) 542 if (uart_circ_chars_pending(&port->state->xmit) < WAKEUP_CHARS)
559 uart_write_wakeup(port); 543 uart_write_wakeup(port);
560} 544}
561 545
562/** 546/**
563 * xuartps_stop_tx - Stop TX 547 * cdns_uart_stop_tx - Stop TX
564 * @port: Handle to the uart port structure 548 * @port: Handle to the uart port structure
565 * 549 */
566 **/ 550static void cdns_uart_stop_tx(struct uart_port *port)
567static void xuartps_stop_tx(struct uart_port *port)
568{ 551{
569 unsigned int regval; 552 unsigned int regval;
570 553
571 regval = xuartps_readl(XUARTPS_CR_OFFSET); 554 regval = cdns_uart_readl(CDNS_UART_CR_OFFSET);
572 regval |= XUARTPS_CR_TX_DIS; 555 regval |= CDNS_UART_CR_TX_DIS;
573 /* Disable the transmitter */ 556 /* Disable the transmitter */
574 xuartps_writel(regval, XUARTPS_CR_OFFSET); 557 cdns_uart_writel(regval, CDNS_UART_CR_OFFSET);
575} 558}
576 559
577/** 560/**
578 * xuartps_stop_rx - Stop RX 561 * cdns_uart_stop_rx - Stop RX
579 * @port: Handle to the uart port structure 562 * @port: Handle to the uart port structure
580 * 563 */
581 **/ 564static void cdns_uart_stop_rx(struct uart_port *port)
582static void xuartps_stop_rx(struct uart_port *port)
583{ 565{
584 unsigned int regval; 566 unsigned int regval;
585 567
586 regval = xuartps_readl(XUARTPS_CR_OFFSET); 568 regval = cdns_uart_readl(CDNS_UART_CR_OFFSET);
587 regval |= XUARTPS_CR_RX_DIS; 569 regval |= CDNS_UART_CR_RX_DIS;
588 /* Disable the receiver */ 570 /* Disable the receiver */
589 xuartps_writel(regval, XUARTPS_CR_OFFSET); 571 cdns_uart_writel(regval, CDNS_UART_CR_OFFSET);
590} 572}
591 573
592/** 574/**
593 * xuartps_tx_empty - Check whether TX is empty 575 * cdns_uart_tx_empty - Check whether TX is empty
594 * @port: Handle to the uart port structure 576 * @port: Handle to the uart port structure
595 * 577 *
596 * Returns TIOCSER_TEMT on success, 0 otherwise 578 * Return: TIOCSER_TEMT on success, 0 otherwise
597 **/ 579 */
598static unsigned int xuartps_tx_empty(struct uart_port *port) 580static unsigned int cdns_uart_tx_empty(struct uart_port *port)
599{ 581{
600 unsigned int status; 582 unsigned int status;
601 583
602 status = xuartps_readl(XUARTPS_ISR_OFFSET) & XUARTPS_IXR_TXEMPTY; 584 status = cdns_uart_readl(CDNS_UART_ISR_OFFSET) & CDNS_UART_IXR_TXEMPTY;
603 return status ? TIOCSER_TEMT : 0; 585 return status ? TIOCSER_TEMT : 0;
604} 586}
605 587
606/** 588/**
607 * xuartps_break_ctl - Based on the input ctl we have to start or stop 589 * cdns_uart_break_ctl - Based on the input ctl we have to start or stop
608 * transmitting char breaks 590 * transmitting char breaks
609 * @port: Handle to the uart port structure 591 * @port: Handle to the uart port structure
610 * @ctl: Value based on which start or stop decision is taken 592 * @ctl: Value based on which start or stop decision is taken
611 * 593 */
612 **/ 594static void cdns_uart_break_ctl(struct uart_port *port, int ctl)
613static void xuartps_break_ctl(struct uart_port *port, int ctl)
614{ 595{
615 unsigned int status; 596 unsigned int status;
616 unsigned long flags; 597 unsigned long flags;
617 598
618 spin_lock_irqsave(&port->lock, flags); 599 spin_lock_irqsave(&port->lock, flags);
619 600
620 status = xuartps_readl(XUARTPS_CR_OFFSET); 601 status = cdns_uart_readl(CDNS_UART_CR_OFFSET);
621 602
622 if (ctl == -1) 603 if (ctl == -1)
623 xuartps_writel(XUARTPS_CR_STARTBRK | status, 604 cdns_uart_writel(CDNS_UART_CR_STARTBRK | status,
624 XUARTPS_CR_OFFSET); 605 CDNS_UART_CR_OFFSET);
625 else { 606 else {
626 if ((status & XUARTPS_CR_STOPBRK) == 0) 607 if ((status & CDNS_UART_CR_STOPBRK) == 0)
627 xuartps_writel(XUARTPS_CR_STOPBRK | status, 608 cdns_uart_writel(CDNS_UART_CR_STOPBRK | status,
628 XUARTPS_CR_OFFSET); 609 CDNS_UART_CR_OFFSET);
629 } 610 }
630 spin_unlock_irqrestore(&port->lock, flags); 611 spin_unlock_irqrestore(&port->lock, flags);
631} 612}
632 613
633/** 614/**
634 * xuartps_set_termios - termios operations, handling data length, parity, 615 * cdns_uart_set_termios - termios operations, handling data length, parity,
635 * stop bits, flow control, baud rate 616 * stop bits, flow control, baud rate
636 * @port: Handle to the uart port structure 617 * @port: Handle to the uart port structure
637 * @termios: Handle to the input termios structure 618 * @termios: Handle to the input termios structure
638 * @old: Values of the previously saved termios structure 619 * @old: Values of the previously saved termios structure
639 * 620 */
640 **/ 621static void cdns_uart_set_termios(struct uart_port *port,
641static void xuartps_set_termios(struct uart_port *port,
642 struct ktermios *termios, struct ktermios *old) 622 struct ktermios *termios, struct ktermios *old)
643{ 623{
644 unsigned int cval = 0; 624 unsigned int cval = 0;
@@ -649,81 +629,79 @@ static void xuartps_set_termios(struct uart_port *port,
649 spin_lock_irqsave(&port->lock, flags); 629 spin_lock_irqsave(&port->lock, flags);
650 630
651 /* Empty the receive FIFO 1st before making changes */ 631 /* Empty the receive FIFO 1st before making changes */
652 while ((xuartps_readl(XUARTPS_SR_OFFSET) & 632 while ((cdns_uart_readl(CDNS_UART_SR_OFFSET) &
653 XUARTPS_SR_RXEMPTY) != XUARTPS_SR_RXEMPTY) { 633 CDNS_UART_SR_RXEMPTY) != CDNS_UART_SR_RXEMPTY) {
654 xuartps_readl(XUARTPS_FIFO_OFFSET); 634 cdns_uart_readl(CDNS_UART_FIFO_OFFSET);
655 } 635 }
656 636
657 /* Disable the TX and RX to set baud rate */ 637 /* Disable the TX and RX to set baud rate */
658 xuartps_writel(xuartps_readl(XUARTPS_CR_OFFSET) | 638 ctrl_reg = cdns_uart_readl(CDNS_UART_CR_OFFSET);
659 (XUARTPS_CR_TX_DIS | XUARTPS_CR_RX_DIS), 639 ctrl_reg |= CDNS_UART_CR_TX_DIS | CDNS_UART_CR_RX_DIS;
660 XUARTPS_CR_OFFSET); 640 cdns_uart_writel(ctrl_reg, CDNS_UART_CR_OFFSET);
661 641
662 /* 642 /*
663 * Min baud rate = 6bps and Max Baud Rate is 10Mbps for 100Mhz clk 643 * Min baud rate = 6bps and Max Baud Rate is 10Mbps for 100Mhz clk
664 * min and max baud should be calculated here based on port->uartclk. 644 * min and max baud should be calculated here based on port->uartclk.
665 * this way we get a valid baud and can safely call set_baud() 645 * this way we get a valid baud and can safely call set_baud()
666 */ 646 */
667 minbaud = port->uartclk / ((XUARTPS_BDIV_MAX + 1) * XUARTPS_CD_MAX * 8); 647 minbaud = port->uartclk /
668 maxbaud = port->uartclk / (XUARTPS_BDIV_MIN + 1); 648 ((CDNS_UART_BDIV_MAX + 1) * CDNS_UART_CD_MAX * 8);
649 maxbaud = port->uartclk / (CDNS_UART_BDIV_MIN + 1);
669 baud = uart_get_baud_rate(port, termios, old, minbaud, maxbaud); 650 baud = uart_get_baud_rate(port, termios, old, minbaud, maxbaud);
670 baud = xuartps_set_baud_rate(port, baud); 651 baud = cdns_uart_set_baud_rate(port, baud);
671 if (tty_termios_baud_rate(termios)) 652 if (tty_termios_baud_rate(termios))
672 tty_termios_encode_baud_rate(termios, baud, baud); 653 tty_termios_encode_baud_rate(termios, baud, baud);
673 654
674 /* 655 /* Update the per-port timeout. */
675 * Update the per-port timeout.
676 */
677 uart_update_timeout(port, termios->c_cflag, baud); 656 uart_update_timeout(port, termios->c_cflag, baud);
678 657
679 /* Set TX/RX Reset */ 658 /* Set TX/RX Reset */
680 xuartps_writel(xuartps_readl(XUARTPS_CR_OFFSET) | 659 ctrl_reg = cdns_uart_readl(CDNS_UART_CR_OFFSET);
681 (XUARTPS_CR_TXRST | XUARTPS_CR_RXRST), 660 ctrl_reg |= CDNS_UART_CR_TXRST | CDNS_UART_CR_RXRST;
682 XUARTPS_CR_OFFSET); 661 cdns_uart_writel(ctrl_reg, CDNS_UART_CR_OFFSET);
683 662
684 ctrl_reg = xuartps_readl(XUARTPS_CR_OFFSET); 663 /*
685 664 * Clear the RX disable and TX disable bits and then set the TX enable
686 /* Clear the RX disable and TX disable bits and then set the TX enable
687 * bit and RX enable bit to enable the transmitter and receiver. 665 * bit and RX enable bit to enable the transmitter and receiver.
688 */ 666 */
689 xuartps_writel( 667 ctrl_reg = cdns_uart_readl(CDNS_UART_CR_OFFSET);
690 (ctrl_reg & ~(XUARTPS_CR_TX_DIS | XUARTPS_CR_RX_DIS)) 668 ctrl_reg &= ~(CDNS_UART_CR_TX_DIS | CDNS_UART_CR_RX_DIS);
691 | (XUARTPS_CR_TX_EN | XUARTPS_CR_RX_EN), 669 ctrl_reg |= CDNS_UART_CR_TX_EN | CDNS_UART_CR_RX_EN;
692 XUARTPS_CR_OFFSET); 670 cdns_uart_writel(ctrl_reg, CDNS_UART_CR_OFFSET);
693 671
694 xuartps_writel(rx_timeout, XUARTPS_RXTOUT_OFFSET); 672 cdns_uart_writel(rx_timeout, CDNS_UART_RXTOUT_OFFSET);
695 673
696 port->read_status_mask = XUARTPS_IXR_TXEMPTY | XUARTPS_IXR_RXTRIG | 674 port->read_status_mask = CDNS_UART_IXR_TXEMPTY | CDNS_UART_IXR_RXTRIG |
697 XUARTPS_IXR_OVERRUN | XUARTPS_IXR_TOUT; 675 CDNS_UART_IXR_OVERRUN | CDNS_UART_IXR_TOUT;
698 port->ignore_status_mask = 0; 676 port->ignore_status_mask = 0;
699 677
700 if (termios->c_iflag & INPCK) 678 if (termios->c_iflag & INPCK)
701 port->read_status_mask |= XUARTPS_IXR_PARITY | 679 port->read_status_mask |= CDNS_UART_IXR_PARITY |
702 XUARTPS_IXR_FRAMING; 680 CDNS_UART_IXR_FRAMING;
703 681
704 if (termios->c_iflag & IGNPAR) 682 if (termios->c_iflag & IGNPAR)
705 port->ignore_status_mask |= XUARTPS_IXR_PARITY | 683 port->ignore_status_mask |= CDNS_UART_IXR_PARITY |
706 XUARTPS_IXR_FRAMING | XUARTPS_IXR_OVERRUN; 684 CDNS_UART_IXR_FRAMING | CDNS_UART_IXR_OVERRUN;
707 685
708 /* ignore all characters if CREAD is not set */ 686 /* ignore all characters if CREAD is not set */
709 if ((termios->c_cflag & CREAD) == 0) 687 if ((termios->c_cflag & CREAD) == 0)
710 port->ignore_status_mask |= XUARTPS_IXR_RXTRIG | 688 port->ignore_status_mask |= CDNS_UART_IXR_RXTRIG |
711 XUARTPS_IXR_TOUT | XUARTPS_IXR_PARITY | 689 CDNS_UART_IXR_TOUT | CDNS_UART_IXR_PARITY |
712 XUARTPS_IXR_FRAMING | XUARTPS_IXR_OVERRUN; 690 CDNS_UART_IXR_FRAMING | CDNS_UART_IXR_OVERRUN;
713 691
714 mode_reg = xuartps_readl(XUARTPS_MR_OFFSET); 692 mode_reg = cdns_uart_readl(CDNS_UART_MR_OFFSET);
715 693
716 /* Handling Data Size */ 694 /* Handling Data Size */
717 switch (termios->c_cflag & CSIZE) { 695 switch (termios->c_cflag & CSIZE) {
718 case CS6: 696 case CS6:
719 cval |= XUARTPS_MR_CHARLEN_6_BIT; 697 cval |= CDNS_UART_MR_CHARLEN_6_BIT;
720 break; 698 break;
721 case CS7: 699 case CS7:
722 cval |= XUARTPS_MR_CHARLEN_7_BIT; 700 cval |= CDNS_UART_MR_CHARLEN_7_BIT;
723 break; 701 break;
724 default: 702 default:
725 case CS8: 703 case CS8:
726 cval |= XUARTPS_MR_CHARLEN_8_BIT; 704 cval |= CDNS_UART_MR_CHARLEN_8_BIT;
727 termios->c_cflag &= ~CSIZE; 705 termios->c_cflag &= ~CSIZE;
728 termios->c_cflag |= CS8; 706 termios->c_cflag |= CS8;
729 break; 707 break;
@@ -731,134 +709,135 @@ static void xuartps_set_termios(struct uart_port *port,
731 709
732 /* Handling Parity and Stop Bits length */ 710 /* Handling Parity and Stop Bits length */
733 if (termios->c_cflag & CSTOPB) 711 if (termios->c_cflag & CSTOPB)
734 cval |= XUARTPS_MR_STOPMODE_2_BIT; /* 2 STOP bits */ 712 cval |= CDNS_UART_MR_STOPMODE_2_BIT; /* 2 STOP bits */
735 else 713 else
736 cval |= XUARTPS_MR_STOPMODE_1_BIT; /* 1 STOP bit */ 714 cval |= CDNS_UART_MR_STOPMODE_1_BIT; /* 1 STOP bit */
737 715
738 if (termios->c_cflag & PARENB) { 716 if (termios->c_cflag & PARENB) {
739 /* Mark or Space parity */ 717 /* Mark or Space parity */
740 if (termios->c_cflag & CMSPAR) { 718 if (termios->c_cflag & CMSPAR) {
741 if (termios->c_cflag & PARODD) 719 if (termios->c_cflag & PARODD)
742 cval |= XUARTPS_MR_PARITY_MARK; 720 cval |= CDNS_UART_MR_PARITY_MARK;
743 else 721 else
744 cval |= XUARTPS_MR_PARITY_SPACE; 722 cval |= CDNS_UART_MR_PARITY_SPACE;
745 } else { 723 } else {
746 if (termios->c_cflag & PARODD) 724 if (termios->c_cflag & PARODD)
747 cval |= XUARTPS_MR_PARITY_ODD; 725 cval |= CDNS_UART_MR_PARITY_ODD;
748 else 726 else
749 cval |= XUARTPS_MR_PARITY_EVEN; 727 cval |= CDNS_UART_MR_PARITY_EVEN;
750 } 728 }
751 } else { 729 } else {
752 cval |= XUARTPS_MR_PARITY_NONE; 730 cval |= CDNS_UART_MR_PARITY_NONE;
753 } 731 }
754 cval |= mode_reg & 1; 732 cval |= mode_reg & 1;
755 xuartps_writel(cval, XUARTPS_MR_OFFSET); 733 cdns_uart_writel(cval, CDNS_UART_MR_OFFSET);
756 734
757 spin_unlock_irqrestore(&port->lock, flags); 735 spin_unlock_irqrestore(&port->lock, flags);
758} 736}
759 737
760/** 738/**
761 * xuartps_startup - Called when an application opens a xuartps port 739 * cdns_uart_startup - Called when an application opens a cdns_uart port
762 * @port: Handle to the uart port structure 740 * @port: Handle to the uart port structure
763 * 741 *
764 * Returns 0 on success, negative error otherwise 742 * Return: 0 on success, negative errno otherwise
765 **/ 743 */
766static int xuartps_startup(struct uart_port *port) 744static int cdns_uart_startup(struct uart_port *port)
767{ 745{
768 unsigned int retval = 0, status = 0; 746 unsigned int retval = 0, status = 0;
769 747
770 retval = request_irq(port->irq, xuartps_isr, 0, XUARTPS_NAME, 748 retval = request_irq(port->irq, cdns_uart_isr, 0, CDNS_UART_NAME,
771 (void *)port); 749 (void *)port);
772 if (retval) 750 if (retval)
773 return retval; 751 return retval;
774 752
775 /* Disable the TX and RX */ 753 /* Disable the TX and RX */
776 xuartps_writel(XUARTPS_CR_TX_DIS | XUARTPS_CR_RX_DIS, 754 cdns_uart_writel(CDNS_UART_CR_TX_DIS | CDNS_UART_CR_RX_DIS,
777 XUARTPS_CR_OFFSET); 755 CDNS_UART_CR_OFFSET);
778 756
779 /* Set the Control Register with TX/RX Enable, TX/RX Reset, 757 /* Set the Control Register with TX/RX Enable, TX/RX Reset,
780 * no break chars. 758 * no break chars.
781 */ 759 */
782 xuartps_writel(XUARTPS_CR_TXRST | XUARTPS_CR_RXRST, 760 cdns_uart_writel(CDNS_UART_CR_TXRST | CDNS_UART_CR_RXRST,
783 XUARTPS_CR_OFFSET); 761 CDNS_UART_CR_OFFSET);
784 762
785 status = xuartps_readl(XUARTPS_CR_OFFSET); 763 status = cdns_uart_readl(CDNS_UART_CR_OFFSET);
786 764
787 /* Clear the RX disable and TX disable bits and then set the TX enable 765 /* Clear the RX disable and TX disable bits and then set the TX enable
788 * bit and RX enable bit to enable the transmitter and receiver. 766 * bit and RX enable bit to enable the transmitter and receiver.
789 */ 767 */
790 xuartps_writel((status & ~(XUARTPS_CR_TX_DIS | XUARTPS_CR_RX_DIS)) 768 cdns_uart_writel((status & ~(CDNS_UART_CR_TX_DIS | CDNS_UART_CR_RX_DIS))
791 | (XUARTPS_CR_TX_EN | XUARTPS_CR_RX_EN | 769 | (CDNS_UART_CR_TX_EN | CDNS_UART_CR_RX_EN |
792 XUARTPS_CR_STOPBRK), XUARTPS_CR_OFFSET); 770 CDNS_UART_CR_STOPBRK), CDNS_UART_CR_OFFSET);
793 771
794 /* Set the Mode Register with normal mode,8 data bits,1 stop bit, 772 /* Set the Mode Register with normal mode,8 data bits,1 stop bit,
795 * no parity. 773 * no parity.
796 */ 774 */
797 xuartps_writel(XUARTPS_MR_CHMODE_NORM | XUARTPS_MR_STOPMODE_1_BIT 775 cdns_uart_writel(CDNS_UART_MR_CHMODE_NORM | CDNS_UART_MR_STOPMODE_1_BIT
798 | XUARTPS_MR_PARITY_NONE | XUARTPS_MR_CHARLEN_8_BIT, 776 | CDNS_UART_MR_PARITY_NONE | CDNS_UART_MR_CHARLEN_8_BIT,
799 XUARTPS_MR_OFFSET); 777 CDNS_UART_MR_OFFSET);
800 778
801 /* 779 /*
802 * Set the RX FIFO Trigger level to use most of the FIFO, but it 780 * Set the RX FIFO Trigger level to use most of the FIFO, but it
803 * can be tuned with a module parameter 781 * can be tuned with a module parameter
804 */ 782 */
805 xuartps_writel(rx_trigger_level, XUARTPS_RXWM_OFFSET); 783 cdns_uart_writel(rx_trigger_level, CDNS_UART_RXWM_OFFSET);
806 784
807 /* 785 /*
808 * Receive Timeout register is enabled but it 786 * Receive Timeout register is enabled but it
809 * can be tuned with a module parameter 787 * can be tuned with a module parameter
810 */ 788 */
811 xuartps_writel(rx_timeout, XUARTPS_RXTOUT_OFFSET); 789 cdns_uart_writel(rx_timeout, CDNS_UART_RXTOUT_OFFSET);
812 790
813 /* Clear out any pending interrupts before enabling them */ 791 /* Clear out any pending interrupts before enabling them */
814 xuartps_writel(xuartps_readl(XUARTPS_ISR_OFFSET), XUARTPS_ISR_OFFSET); 792 cdns_uart_writel(cdns_uart_readl(CDNS_UART_ISR_OFFSET),
793 CDNS_UART_ISR_OFFSET);
815 794
816 /* Set the Interrupt Registers with desired interrupts */ 795 /* Set the Interrupt Registers with desired interrupts */
817 xuartps_writel(XUARTPS_IXR_TXEMPTY | XUARTPS_IXR_PARITY | 796 cdns_uart_writel(CDNS_UART_IXR_TXEMPTY | CDNS_UART_IXR_PARITY |
818 XUARTPS_IXR_FRAMING | XUARTPS_IXR_OVERRUN | 797 CDNS_UART_IXR_FRAMING | CDNS_UART_IXR_OVERRUN |
819 XUARTPS_IXR_RXTRIG | XUARTPS_IXR_TOUT, XUARTPS_IER_OFFSET); 798 CDNS_UART_IXR_RXTRIG | CDNS_UART_IXR_TOUT,
799 CDNS_UART_IER_OFFSET);
820 800
821 return retval; 801 return retval;
822} 802}
823 803
824/** 804/**
825 * xuartps_shutdown - Called when an application closes a xuartps port 805 * cdns_uart_shutdown - Called when an application closes a cdns_uart port
826 * @port: Handle to the uart port structure 806 * @port: Handle to the uart port structure
827 * 807 */
828 **/ 808static void cdns_uart_shutdown(struct uart_port *port)
829static void xuartps_shutdown(struct uart_port *port)
830{ 809{
831 int status; 810 int status;
832 811
833 /* Disable interrupts */ 812 /* Disable interrupts */
834 status = xuartps_readl(XUARTPS_IMR_OFFSET); 813 status = cdns_uart_readl(CDNS_UART_IMR_OFFSET);
835 xuartps_writel(status, XUARTPS_IDR_OFFSET); 814 cdns_uart_writel(status, CDNS_UART_IDR_OFFSET);
836 815
837 /* Disable the TX and RX */ 816 /* Disable the TX and RX */
838 xuartps_writel(XUARTPS_CR_TX_DIS | XUARTPS_CR_RX_DIS, 817 cdns_uart_writel(CDNS_UART_CR_TX_DIS | CDNS_UART_CR_RX_DIS,
839 XUARTPS_CR_OFFSET); 818 CDNS_UART_CR_OFFSET);
840 free_irq(port->irq, port); 819 free_irq(port->irq, port);
841} 820}
842 821
843/** 822/**
844 * xuartps_type - Set UART type to xuartps port 823 * cdns_uart_type - Set UART type to cdns_uart port
845 * @port: Handle to the uart port structure 824 * @port: Handle to the uart port structure
846 * 825 *
847 * Returns string on success, NULL otherwise 826 * Return: string on success, NULL otherwise
848 **/ 827 */
849static const char *xuartps_type(struct uart_port *port) 828static const char *cdns_uart_type(struct uart_port *port)
850{ 829{
851 return port->type == PORT_XUARTPS ? XUARTPS_NAME : NULL; 830 return port->type == PORT_XUARTPS ? CDNS_UART_NAME : NULL;
852} 831}
853 832
854/** 833/**
855 * xuartps_verify_port - Verify the port params 834 * cdns_uart_verify_port - Verify the port params
856 * @port: Handle to the uart port structure 835 * @port: Handle to the uart port structure
857 * @ser: Handle to the structure whose members are compared 836 * @ser: Handle to the structure whose members are compared
858 * 837 *
859 * Returns 0 if success otherwise -EINVAL 838 * Return: 0 on success, negative errno otherwise.
860 **/ 839 */
861static int xuartps_verify_port(struct uart_port *port, 840static int cdns_uart_verify_port(struct uart_port *port,
862 struct serial_struct *ser) 841 struct serial_struct *ser)
863{ 842{
864 if (ser->type != PORT_UNKNOWN && ser->type != PORT_XUARTPS) 843 if (ser->type != PORT_UNKNOWN && ser->type != PORT_XUARTPS)
@@ -875,187 +854,170 @@ static int xuartps_verify_port(struct uart_port *port,
875} 854}
876 855
877/** 856/**
878 * xuartps_request_port - Claim the memory region attached to xuartps port, 857 * cdns_uart_request_port - Claim the memory region attached to cdns_uart port,
879 * called when the driver adds a xuartps port via 858 * called when the driver adds a cdns_uart port via
880 * uart_add_one_port() 859 * uart_add_one_port()
881 * @port: Handle to the uart port structure 860 * @port: Handle to the uart port structure
882 * 861 *
883 * Returns 0, -ENOMEM if request fails 862 * Return: 0 on success, negative errno otherwise.
884 **/ 863 */
885static int xuartps_request_port(struct uart_port *port) 864static int cdns_uart_request_port(struct uart_port *port)
886{ 865{
887 if (!request_mem_region(port->mapbase, XUARTPS_REGISTER_SPACE, 866 if (!request_mem_region(port->mapbase, CDNS_UART_REGISTER_SPACE,
888 XUARTPS_NAME)) { 867 CDNS_UART_NAME)) {
889 return -ENOMEM; 868 return -ENOMEM;
890 } 869 }
891 870
892 port->membase = ioremap(port->mapbase, XUARTPS_REGISTER_SPACE); 871 port->membase = ioremap(port->mapbase, CDNS_UART_REGISTER_SPACE);
893 if (!port->membase) { 872 if (!port->membase) {
894 dev_err(port->dev, "Unable to map registers\n"); 873 dev_err(port->dev, "Unable to map registers\n");
895 release_mem_region(port->mapbase, XUARTPS_REGISTER_SPACE); 874 release_mem_region(port->mapbase, CDNS_UART_REGISTER_SPACE);
896 return -ENOMEM; 875 return -ENOMEM;
897 } 876 }
898 return 0; 877 return 0;
899} 878}
900 879
901/** 880/**
902 * xuartps_release_port - Release the memory region attached to a xuartps 881 * cdns_uart_release_port - Release UART port
903 * port, called when the driver removes a xuartps
904 * port via uart_remove_one_port().
905 * @port: Handle to the uart port structure 882 * @port: Handle to the uart port structure
906 * 883 *
907 **/ 884 * Release the memory region attached to a cdns_uart port. Called when the
908static void xuartps_release_port(struct uart_port *port) 885 * driver removes a cdns_uart port via uart_remove_one_port().
886 */
887static void cdns_uart_release_port(struct uart_port *port)
909{ 888{
910 release_mem_region(port->mapbase, XUARTPS_REGISTER_SPACE); 889 release_mem_region(port->mapbase, CDNS_UART_REGISTER_SPACE);
911 iounmap(port->membase); 890 iounmap(port->membase);
912 port->membase = NULL; 891 port->membase = NULL;
913} 892}
914 893
915/** 894/**
916 * xuartps_config_port - Configure xuartps, called when the driver adds a 895 * cdns_uart_config_port - Configure UART port
917 * xuartps port
918 * @port: Handle to the uart port structure 896 * @port: Handle to the uart port structure
919 * @flags: If any 897 * @flags: If any
920 * 898 */
921 **/ 899static void cdns_uart_config_port(struct uart_port *port, int flags)
922static void xuartps_config_port(struct uart_port *port, int flags)
923{ 900{
924 if (flags & UART_CONFIG_TYPE && xuartps_request_port(port) == 0) 901 if (flags & UART_CONFIG_TYPE && cdns_uart_request_port(port) == 0)
925 port->type = PORT_XUARTPS; 902 port->type = PORT_XUARTPS;
926} 903}
927 904
928/** 905/**
929 * xuartps_get_mctrl - Get the modem control state 906 * cdns_uart_get_mctrl - Get the modem control state
930 *
931 * @port: Handle to the uart port structure 907 * @port: Handle to the uart port structure
932 * 908 *
933 * Returns the modem control state 909 * Return: the modem control state
934 * 910 */
935 **/ 911static unsigned int cdns_uart_get_mctrl(struct uart_port *port)
936static unsigned int xuartps_get_mctrl(struct uart_port *port)
937{ 912{
938 return TIOCM_CTS | TIOCM_DSR | TIOCM_CAR; 913 return TIOCM_CTS | TIOCM_DSR | TIOCM_CAR;
939} 914}
940 915
941static void xuartps_set_mctrl(struct uart_port *port, unsigned int mctrl) 916static void cdns_uart_set_mctrl(struct uart_port *port, unsigned int mctrl)
942{ 917{
943 /* N/A */ 918 /* N/A */
944} 919}
945 920
946static void xuartps_enable_ms(struct uart_port *port) 921static void cdns_uart_enable_ms(struct uart_port *port)
947{ 922{
948 /* N/A */ 923 /* N/A */
949} 924}
950 925
951#ifdef CONFIG_CONSOLE_POLL 926#ifdef CONFIG_CONSOLE_POLL
952static int xuartps_poll_get_char(struct uart_port *port) 927static int cdns_uart_poll_get_char(struct uart_port *port)
953{ 928{
954 u32 imr; 929 u32 imr;
955 int c; 930 int c;
956 931
957 /* Disable all interrupts */ 932 /* Disable all interrupts */
958 imr = xuartps_readl(XUARTPS_IMR_OFFSET); 933 imr = cdns_uart_readl(CDNS_UART_IMR_OFFSET);
959 xuartps_writel(imr, XUARTPS_IDR_OFFSET); 934 cdns_uart_writel(imr, CDNS_UART_IDR_OFFSET);
960 935
961 /* Check if FIFO is empty */ 936 /* Check if FIFO is empty */
962 if (xuartps_readl(XUARTPS_SR_OFFSET) & XUARTPS_SR_RXEMPTY) 937 if (cdns_uart_readl(CDNS_UART_SR_OFFSET) & CDNS_UART_SR_RXEMPTY)
963 c = NO_POLL_CHAR; 938 c = NO_POLL_CHAR;
964 else /* Read a character */ 939 else /* Read a character */
965 c = (unsigned char) xuartps_readl(XUARTPS_FIFO_OFFSET); 940 c = (unsigned char) cdns_uart_readl(CDNS_UART_FIFO_OFFSET);
966 941
967 /* Enable interrupts */ 942 /* Enable interrupts */
968 xuartps_writel(imr, XUARTPS_IER_OFFSET); 943 cdns_uart_writel(imr, CDNS_UART_IER_OFFSET);
969 944
970 return c; 945 return c;
971} 946}
972 947
973static void xuartps_poll_put_char(struct uart_port *port, unsigned char c) 948static void cdns_uart_poll_put_char(struct uart_port *port, unsigned char c)
974{ 949{
975 u32 imr; 950 u32 imr;
976 951
977 /* Disable all interrupts */ 952 /* Disable all interrupts */
978 imr = xuartps_readl(XUARTPS_IMR_OFFSET); 953 imr = cdns_uart_readl(CDNS_UART_IMR_OFFSET);
979 xuartps_writel(imr, XUARTPS_IDR_OFFSET); 954 cdns_uart_writel(imr, CDNS_UART_IDR_OFFSET);
980 955
981 /* Wait until FIFO is empty */ 956 /* Wait until FIFO is empty */
982 while (!(xuartps_readl(XUARTPS_SR_OFFSET) & XUARTPS_SR_TXEMPTY)) 957 while (!(cdns_uart_readl(CDNS_UART_SR_OFFSET) & CDNS_UART_SR_TXEMPTY))
983 cpu_relax(); 958 cpu_relax();
984 959
985 /* Write a character */ 960 /* Write a character */
986 xuartps_writel(c, XUARTPS_FIFO_OFFSET); 961 cdns_uart_writel(c, CDNS_UART_FIFO_OFFSET);
987 962
988 /* Wait until FIFO is empty */ 963 /* Wait until FIFO is empty */
989 while (!(xuartps_readl(XUARTPS_SR_OFFSET) & XUARTPS_SR_TXEMPTY)) 964 while (!(cdns_uart_readl(CDNS_UART_SR_OFFSET) & CDNS_UART_SR_TXEMPTY))
990 cpu_relax(); 965 cpu_relax();
991 966
992 /* Enable interrupts */ 967 /* Enable interrupts */
993 xuartps_writel(imr, XUARTPS_IER_OFFSET); 968 cdns_uart_writel(imr, CDNS_UART_IER_OFFSET);
994 969
995 return; 970 return;
996} 971}
997#endif 972#endif
998 973
999/** The UART operations structure 974static struct uart_ops cdns_uart_ops = {
1000 */ 975 .set_mctrl = cdns_uart_set_mctrl,
1001static struct uart_ops xuartps_ops = { 976 .get_mctrl = cdns_uart_get_mctrl,
1002 .set_mctrl = xuartps_set_mctrl, 977 .enable_ms = cdns_uart_enable_ms,
1003 .get_mctrl = xuartps_get_mctrl, 978 .start_tx = cdns_uart_start_tx,
1004 .enable_ms = xuartps_enable_ms, 979 .stop_tx = cdns_uart_stop_tx,
1005 980 .stop_rx = cdns_uart_stop_rx,
1006 .start_tx = xuartps_start_tx, /* Start transmitting */ 981 .tx_empty = cdns_uart_tx_empty,
1007 .stop_tx = xuartps_stop_tx, /* Stop transmission */ 982 .break_ctl = cdns_uart_break_ctl,
1008 .stop_rx = xuartps_stop_rx, /* Stop reception */ 983 .set_termios = cdns_uart_set_termios,
1009 .tx_empty = xuartps_tx_empty, /* Transmitter busy? */ 984 .startup = cdns_uart_startup,
1010 .break_ctl = xuartps_break_ctl, /* Start/stop 985 .shutdown = cdns_uart_shutdown,
1011 * transmitting break 986 .type = cdns_uart_type,
1012 */ 987 .verify_port = cdns_uart_verify_port,
1013 .set_termios = xuartps_set_termios, /* Set termios */ 988 .request_port = cdns_uart_request_port,
1014 .startup = xuartps_startup, /* App opens xuartps */ 989 .release_port = cdns_uart_release_port,
1015 .shutdown = xuartps_shutdown, /* App closes xuartps */ 990 .config_port = cdns_uart_config_port,
1016 .type = xuartps_type, /* Set UART type */
1017 .verify_port = xuartps_verify_port, /* Verification of port
1018 * params
1019 */
1020 .request_port = xuartps_request_port, /* Claim resources
1021 * associated with a
1022 * xuartps port
1023 */
1024 .release_port = xuartps_release_port, /* Release resources
1025 * associated with a
1026 * xuartps port
1027 */
1028 .config_port = xuartps_config_port, /* Configure when driver
1029 * adds a xuartps port
1030 */
1031#ifdef CONFIG_CONSOLE_POLL 991#ifdef CONFIG_CONSOLE_POLL
1032 .poll_get_char = xuartps_poll_get_char, 992 .poll_get_char = cdns_uart_poll_get_char,
1033 .poll_put_char = xuartps_poll_put_char, 993 .poll_put_char = cdns_uart_poll_put_char,
1034#endif 994#endif
1035}; 995};
1036 996
1037static struct uart_port xuartps_port[2]; 997static struct uart_port cdns_uart_port[2];
1038 998
1039/** 999/**
1040 * xuartps_get_port - Configure the port from the platform device resource 1000 * cdns_uart_get_port - Configure the port from platform device resource info
1041 * info 1001 * @id: Port id
1042 * 1002 *
1043 * Returns a pointer to a uart_port or NULL for failure 1003 * Return: a pointer to a uart_port or NULL for failure
1044 **/ 1004 */
1045static struct uart_port *xuartps_get_port(void) 1005static struct uart_port *cdns_uart_get_port(int id)
1046{ 1006{
1047 struct uart_port *port; 1007 struct uart_port *port;
1048 int id;
1049 1008
1050 /* Find the next unused port */ 1009 /* Try the given port id if failed use default method */
1051 for (id = 0; id < XUARTPS_NR_PORTS; id++) 1010 if (cdns_uart_port[id].mapbase != 0) {
1052 if (xuartps_port[id].mapbase == 0) 1011 /* Find the next unused port */
1053 break; 1012 for (id = 0; id < CDNS_UART_NR_PORTS; id++)
1013 if (cdns_uart_port[id].mapbase == 0)
1014 break;
1015 }
1054 1016
1055 if (id >= XUARTPS_NR_PORTS) 1017 if (id >= CDNS_UART_NR_PORTS)
1056 return NULL; 1018 return NULL;
1057 1019
1058 port = &xuartps_port[id]; 1020 port = &cdns_uart_port[id];
1059 1021
1060 /* At this point, we've got an empty uart_port struct, initialize it */ 1022 /* At this point, we've got an empty uart_port struct, initialize it */
1061 spin_lock_init(&port->lock); 1023 spin_lock_init(&port->lock);
@@ -1065,50 +1027,46 @@ static struct uart_port *xuartps_get_port(void)
1065 port->type = PORT_UNKNOWN; 1027 port->type = PORT_UNKNOWN;
1066 port->iotype = UPIO_MEM32; 1028 port->iotype = UPIO_MEM32;
1067 port->flags = UPF_BOOT_AUTOCONF; 1029 port->flags = UPF_BOOT_AUTOCONF;
1068 port->ops = &xuartps_ops; 1030 port->ops = &cdns_uart_ops;
1069 port->fifosize = XUARTPS_FIFO_SIZE; 1031 port->fifosize = CDNS_UART_FIFO_SIZE;
1070 port->line = id; 1032 port->line = id;
1071 port->dev = NULL; 1033 port->dev = NULL;
1072 return port; 1034 return port;
1073} 1035}
1074 1036
1075/*-----------------------Console driver operations--------------------------*/
1076
1077#ifdef CONFIG_SERIAL_XILINX_PS_UART_CONSOLE 1037#ifdef CONFIG_SERIAL_XILINX_PS_UART_CONSOLE
1078/** 1038/**
1079 * xuartps_console_wait_tx - Wait for the TX to be full 1039 * cdns_uart_console_wait_tx - Wait for the TX to be full
1080 * @port: Handle to the uart port structure 1040 * @port: Handle to the uart port structure
1081 * 1041 */
1082 **/ 1042static void cdns_uart_console_wait_tx(struct uart_port *port)
1083static void xuartps_console_wait_tx(struct uart_port *port)
1084{ 1043{
1085 while ((xuartps_readl(XUARTPS_SR_OFFSET) & XUARTPS_SR_TXEMPTY) 1044 while ((cdns_uart_readl(CDNS_UART_SR_OFFSET) & CDNS_UART_SR_TXEMPTY)
1086 != XUARTPS_SR_TXEMPTY) 1045 != CDNS_UART_SR_TXEMPTY)
1087 barrier(); 1046 barrier();
1088} 1047}
1089 1048
1090/** 1049/**
1091 * xuartps_console_putchar - write the character to the FIFO buffer 1050 * cdns_uart_console_putchar - write the character to the FIFO buffer
1092 * @port: Handle to the uart port structure 1051 * @port: Handle to the uart port structure
1093 * @ch: Character to be written 1052 * @ch: Character to be written
1094 * 1053 */
1095 **/ 1054static void cdns_uart_console_putchar(struct uart_port *port, int ch)
1096static void xuartps_console_putchar(struct uart_port *port, int ch)
1097{ 1055{
1098 xuartps_console_wait_tx(port); 1056 cdns_uart_console_wait_tx(port);
1099 xuartps_writel(ch, XUARTPS_FIFO_OFFSET); 1057 cdns_uart_writel(ch, CDNS_UART_FIFO_OFFSET);
1100} 1058}
1101 1059
1102/** 1060/**
1103 * xuartps_console_write - perform write operation 1061 * cdns_uart_console_write - perform write operation
1104 * @port: Handle to the uart port structure 1062 * @co: Console handle
1105 * @s: Pointer to character array 1063 * @s: Pointer to character array
1106 * @count: No of characters 1064 * @count: No of characters
1107 **/ 1065 */
1108static void xuartps_console_write(struct console *co, const char *s, 1066static void cdns_uart_console_write(struct console *co, const char *s,
1109 unsigned int count) 1067 unsigned int count)
1110{ 1068{
1111 struct uart_port *port = &xuartps_port[co->index]; 1069 struct uart_port *port = &cdns_uart_port[co->index];
1112 unsigned long flags; 1070 unsigned long flags;
1113 unsigned int imr, ctrl; 1071 unsigned int imr, ctrl;
1114 int locked = 1; 1072 int locked = 1;
@@ -1119,49 +1077,45 @@ static void xuartps_console_write(struct console *co, const char *s,
1119 spin_lock_irqsave(&port->lock, flags); 1077 spin_lock_irqsave(&port->lock, flags);
1120 1078
1121 /* save and disable interrupt */ 1079 /* save and disable interrupt */
1122 imr = xuartps_readl(XUARTPS_IMR_OFFSET); 1080 imr = cdns_uart_readl(CDNS_UART_IMR_OFFSET);
1123 xuartps_writel(imr, XUARTPS_IDR_OFFSET); 1081 cdns_uart_writel(imr, CDNS_UART_IDR_OFFSET);
1124 1082
1125 /* 1083 /*
1126 * Make sure that the tx part is enabled. Set the TX enable bit and 1084 * Make sure that the tx part is enabled. Set the TX enable bit and
1127 * clear the TX disable bit to enable the transmitter. 1085 * clear the TX disable bit to enable the transmitter.
1128 */ 1086 */
1129 ctrl = xuartps_readl(XUARTPS_CR_OFFSET); 1087 ctrl = cdns_uart_readl(CDNS_UART_CR_OFFSET);
1130 xuartps_writel((ctrl & ~XUARTPS_CR_TX_DIS) | XUARTPS_CR_TX_EN, 1088 cdns_uart_writel((ctrl & ~CDNS_UART_CR_TX_DIS) | CDNS_UART_CR_TX_EN,
1131 XUARTPS_CR_OFFSET); 1089 CDNS_UART_CR_OFFSET);
1132 1090
1133 uart_console_write(port, s, count, xuartps_console_putchar); 1091 uart_console_write(port, s, count, cdns_uart_console_putchar);
1134 xuartps_console_wait_tx(port); 1092 cdns_uart_console_wait_tx(port);
1135 1093
1136 xuartps_writel(ctrl, XUARTPS_CR_OFFSET); 1094 cdns_uart_writel(ctrl, CDNS_UART_CR_OFFSET);
1137 1095
1138 /* restore interrupt state, it seems like there may be a h/w bug 1096 /* restore interrupt state */
1139 * in that the interrupt enable register should not need to be 1097 cdns_uart_writel(imr, CDNS_UART_IER_OFFSET);
1140 * written based on the data sheet
1141 */
1142 xuartps_writel(~imr, XUARTPS_IDR_OFFSET);
1143 xuartps_writel(imr, XUARTPS_IER_OFFSET);
1144 1098
1145 if (locked) 1099 if (locked)
1146 spin_unlock_irqrestore(&port->lock, flags); 1100 spin_unlock_irqrestore(&port->lock, flags);
1147} 1101}
1148 1102
1149/** 1103/**
1150 * xuartps_console_setup - Initialize the uart to default config 1104 * cdns_uart_console_setup - Initialize the uart to default config
1151 * @co: Console handle 1105 * @co: Console handle
1152 * @options: Initial settings of uart 1106 * @options: Initial settings of uart
1153 * 1107 *
1154 * Returns 0, -ENODEV if no device 1108 * Return: 0 on success, negative errno otherwise.
1155 **/ 1109 */
1156static int __init xuartps_console_setup(struct console *co, char *options) 1110static int __init cdns_uart_console_setup(struct console *co, char *options)
1157{ 1111{
1158 struct uart_port *port = &xuartps_port[co->index]; 1112 struct uart_port *port = &cdns_uart_port[co->index];
1159 int baud = 9600; 1113 int baud = 9600;
1160 int bits = 8; 1114 int bits = 8;
1161 int parity = 'n'; 1115 int parity = 'n';
1162 int flow = 'n'; 1116 int flow = 'n';
1163 1117
1164 if (co->index < 0 || co->index >= XUARTPS_NR_PORTS) 1118 if (co->index < 0 || co->index >= CDNS_UART_NR_PORTS)
1165 return -EINVAL; 1119 return -EINVAL;
1166 1120
1167 if (!port->mapbase) { 1121 if (!port->mapbase) {
@@ -1175,55 +1129,53 @@ static int __init xuartps_console_setup(struct console *co, char *options)
1175 return uart_set_options(port, co, baud, parity, bits, flow); 1129 return uart_set_options(port, co, baud, parity, bits, flow);
1176} 1130}
1177 1131
1178static struct uart_driver xuartps_uart_driver; 1132static struct uart_driver cdns_uart_uart_driver;
1179 1133
1180static struct console xuartps_console = { 1134static struct console cdns_uart_console = {
1181 .name = XUARTPS_TTY_NAME, 1135 .name = CDNS_UART_TTY_NAME,
1182 .write = xuartps_console_write, 1136 .write = cdns_uart_console_write,
1183 .device = uart_console_device, 1137 .device = uart_console_device,
1184 .setup = xuartps_console_setup, 1138 .setup = cdns_uart_console_setup,
1185 .flags = CON_PRINTBUFFER, 1139 .flags = CON_PRINTBUFFER,
1186 .index = -1, /* Specified on the cmdline (e.g. console=ttyPS ) */ 1140 .index = -1, /* Specified on the cmdline (e.g. console=ttyPS ) */
1187 .data = &xuartps_uart_driver, 1141 .data = &cdns_uart_uart_driver,
1188}; 1142};
1189 1143
1190/** 1144/**
1191 * xuartps_console_init - Initialization call 1145 * cdns_uart_console_init - Initialization call
1192 * 1146 *
1193 * Returns 0 on success, negative error otherwise 1147 * Return: 0 on success, negative errno otherwise
1194 **/ 1148 */
1195static int __init xuartps_console_init(void) 1149static int __init cdns_uart_console_init(void)
1196{ 1150{
1197 register_console(&xuartps_console); 1151 register_console(&cdns_uart_console);
1198 return 0; 1152 return 0;
1199} 1153}
1200 1154
1201console_initcall(xuartps_console_init); 1155console_initcall(cdns_uart_console_init);
1202 1156
1203#endif /* CONFIG_SERIAL_XILINX_PS_UART_CONSOLE */ 1157#endif /* CONFIG_SERIAL_XILINX_PS_UART_CONSOLE */
1204 1158
1205/** Structure Definitions 1159static struct uart_driver cdns_uart_uart_driver = {
1206 */ 1160 .owner = THIS_MODULE,
1207static struct uart_driver xuartps_uart_driver = { 1161 .driver_name = CDNS_UART_NAME,
1208 .owner = THIS_MODULE, /* Owner */ 1162 .dev_name = CDNS_UART_TTY_NAME,
1209 .driver_name = XUARTPS_NAME, /* Driver name */ 1163 .major = CDNS_UART_MAJOR,
1210 .dev_name = XUARTPS_TTY_NAME, /* Node name */ 1164 .minor = CDNS_UART_MINOR,
1211 .major = XUARTPS_MAJOR, /* Major number */ 1165 .nr = CDNS_UART_NR_PORTS,
1212 .minor = XUARTPS_MINOR, /* Minor number */
1213 .nr = XUARTPS_NR_PORTS, /* Number of UART ports */
1214#ifdef CONFIG_SERIAL_XILINX_PS_UART_CONSOLE 1166#ifdef CONFIG_SERIAL_XILINX_PS_UART_CONSOLE
1215 .cons = &xuartps_console, /* Console */ 1167 .cons = &cdns_uart_console,
1216#endif 1168#endif
1217}; 1169};
1218 1170
1219#ifdef CONFIG_PM_SLEEP 1171#ifdef CONFIG_PM_SLEEP
1220/** 1172/**
1221 * xuartps_suspend - suspend event 1173 * cdns_uart_suspend - suspend event
1222 * @device: Pointer to the device structure 1174 * @device: Pointer to the device structure
1223 * 1175 *
1224 * Returns 0 1176 * Return: 0
1225 */ 1177 */
1226static int xuartps_suspend(struct device *device) 1178static int cdns_uart_suspend(struct device *device)
1227{ 1179{
1228 struct uart_port *port = dev_get_drvdata(device); 1180 struct uart_port *port = dev_get_drvdata(device);
1229 struct tty_struct *tty; 1181 struct tty_struct *tty;
@@ -1242,23 +1194,24 @@ static int xuartps_suspend(struct device *device)
1242 * Call the API provided in serial_core.c file which handles 1194 * Call the API provided in serial_core.c file which handles
1243 * the suspend. 1195 * the suspend.
1244 */ 1196 */
1245 uart_suspend_port(&xuartps_uart_driver, port); 1197 uart_suspend_port(&cdns_uart_uart_driver, port);
1246 if (console_suspend_enabled && !may_wake) { 1198 if (console_suspend_enabled && !may_wake) {
1247 struct xuartps *xuartps = port->private_data; 1199 struct cdns_uart *cdns_uart = port->private_data;
1248 1200
1249 clk_disable(xuartps->refclk); 1201 clk_disable(cdns_uart->uartclk);
1250 clk_disable(xuartps->aperclk); 1202 clk_disable(cdns_uart->pclk);
1251 } else { 1203 } else {
1252 unsigned long flags = 0; 1204 unsigned long flags = 0;
1253 1205
1254 spin_lock_irqsave(&port->lock, flags); 1206 spin_lock_irqsave(&port->lock, flags);
1255 /* Empty the receive FIFO 1st before making changes */ 1207 /* Empty the receive FIFO 1st before making changes */
1256 while (!(xuartps_readl(XUARTPS_SR_OFFSET) & XUARTPS_SR_RXEMPTY)) 1208 while (!(cdns_uart_readl(CDNS_UART_SR_OFFSET) &
1257 xuartps_readl(XUARTPS_FIFO_OFFSET); 1209 CDNS_UART_SR_RXEMPTY))
1210 cdns_uart_readl(CDNS_UART_FIFO_OFFSET);
1258 /* set RX trigger level to 1 */ 1211 /* set RX trigger level to 1 */
1259 xuartps_writel(1, XUARTPS_RXWM_OFFSET); 1212 cdns_uart_writel(1, CDNS_UART_RXWM_OFFSET);
1260 /* disable RX timeout interrups */ 1213 /* disable RX timeout interrups */
1261 xuartps_writel(XUARTPS_IXR_TOUT, XUARTPS_IDR_OFFSET); 1214 cdns_uart_writel(CDNS_UART_IXR_TOUT, CDNS_UART_IDR_OFFSET);
1262 spin_unlock_irqrestore(&port->lock, flags); 1215 spin_unlock_irqrestore(&port->lock, flags);
1263 } 1216 }
1264 1217
@@ -1266,12 +1219,12 @@ static int xuartps_suspend(struct device *device)
1266} 1219}
1267 1220
1268/** 1221/**
1269 * xuartps_resume - Resume after a previous suspend 1222 * cdns_uart_resume - Resume after a previous suspend
1270 * @device: Pointer to the device structure 1223 * @device: Pointer to the device structure
1271 * 1224 *
1272 * Returns 0 1225 * Return: 0
1273 */ 1226 */
1274static int xuartps_resume(struct device *device) 1227static int cdns_uart_resume(struct device *device)
1275{ 1228{
1276 struct uart_port *port = dev_get_drvdata(device); 1229 struct uart_port *port = dev_get_drvdata(device);
1277 unsigned long flags = 0; 1230 unsigned long flags = 0;
@@ -1289,87 +1242,95 @@ static int xuartps_resume(struct device *device)
1289 } 1242 }
1290 1243
1291 if (console_suspend_enabled && !may_wake) { 1244 if (console_suspend_enabled && !may_wake) {
1292 struct xuartps *xuartps = port->private_data; 1245 struct cdns_uart *cdns_uart = port->private_data;
1293 1246
1294 clk_enable(xuartps->aperclk); 1247 clk_enable(cdns_uart->pclk);
1295 clk_enable(xuartps->refclk); 1248 clk_enable(cdns_uart->uartclk);
1296 1249
1297 spin_lock_irqsave(&port->lock, flags); 1250 spin_lock_irqsave(&port->lock, flags);
1298 1251
1299 /* Set TX/RX Reset */ 1252 /* Set TX/RX Reset */
1300 xuartps_writel(xuartps_readl(XUARTPS_CR_OFFSET) | 1253 ctrl_reg = cdns_uart_readl(CDNS_UART_CR_OFFSET);
1301 (XUARTPS_CR_TXRST | XUARTPS_CR_RXRST), 1254 ctrl_reg |= CDNS_UART_CR_TXRST | CDNS_UART_CR_RXRST;
1302 XUARTPS_CR_OFFSET); 1255 cdns_uart_writel(ctrl_reg, CDNS_UART_CR_OFFSET);
1303 while (xuartps_readl(XUARTPS_CR_OFFSET) & 1256 while (cdns_uart_readl(CDNS_UART_CR_OFFSET) &
1304 (XUARTPS_CR_TXRST | XUARTPS_CR_RXRST)) 1257 (CDNS_UART_CR_TXRST | CDNS_UART_CR_RXRST))
1305 cpu_relax(); 1258 cpu_relax();
1306 1259
1307 /* restore rx timeout value */ 1260 /* restore rx timeout value */
1308 xuartps_writel(rx_timeout, XUARTPS_RXTOUT_OFFSET); 1261 cdns_uart_writel(rx_timeout, CDNS_UART_RXTOUT_OFFSET);
1309 /* Enable Tx/Rx */ 1262 /* Enable Tx/Rx */
1310 ctrl_reg = xuartps_readl(XUARTPS_CR_OFFSET); 1263 ctrl_reg = cdns_uart_readl(CDNS_UART_CR_OFFSET);
1311 xuartps_writel( 1264 ctrl_reg &= ~(CDNS_UART_CR_TX_DIS | CDNS_UART_CR_RX_DIS);
1312 (ctrl_reg & ~(XUARTPS_CR_TX_DIS | XUARTPS_CR_RX_DIS)) | 1265 ctrl_reg |= CDNS_UART_CR_TX_EN | CDNS_UART_CR_RX_EN;
1313 (XUARTPS_CR_TX_EN | XUARTPS_CR_RX_EN), 1266 cdns_uart_writel(ctrl_reg, CDNS_UART_CR_OFFSET);
1314 XUARTPS_CR_OFFSET);
1315 1267
1316 spin_unlock_irqrestore(&port->lock, flags); 1268 spin_unlock_irqrestore(&port->lock, flags);
1317 } else { 1269 } else {
1318 spin_lock_irqsave(&port->lock, flags); 1270 spin_lock_irqsave(&port->lock, flags);
1319 /* restore original rx trigger level */ 1271 /* restore original rx trigger level */
1320 xuartps_writel(rx_trigger_level, XUARTPS_RXWM_OFFSET); 1272 cdns_uart_writel(rx_trigger_level, CDNS_UART_RXWM_OFFSET);
1321 /* enable RX timeout interrupt */ 1273 /* enable RX timeout interrupt */
1322 xuartps_writel(XUARTPS_IXR_TOUT, XUARTPS_IER_OFFSET); 1274 cdns_uart_writel(CDNS_UART_IXR_TOUT, CDNS_UART_IER_OFFSET);
1323 spin_unlock_irqrestore(&port->lock, flags); 1275 spin_unlock_irqrestore(&port->lock, flags);
1324 } 1276 }
1325 1277
1326 return uart_resume_port(&xuartps_uart_driver, port); 1278 return uart_resume_port(&cdns_uart_uart_driver, port);
1327} 1279}
1328#endif /* ! CONFIG_PM_SLEEP */ 1280#endif /* ! CONFIG_PM_SLEEP */
1329 1281
1330static SIMPLE_DEV_PM_OPS(xuartps_dev_pm_ops, xuartps_suspend, xuartps_resume); 1282static SIMPLE_DEV_PM_OPS(cdns_uart_dev_pm_ops, cdns_uart_suspend,
1283 cdns_uart_resume);
1331 1284
1332/* ---------------------------------------------------------------------
1333 * Platform bus binding
1334 */
1335/** 1285/**
1336 * xuartps_probe - Platform driver probe 1286 * cdns_uart_probe - Platform driver probe
1337 * @pdev: Pointer to the platform device structure 1287 * @pdev: Pointer to the platform device structure
1338 * 1288 *
1339 * Returns 0 on success, negative error otherwise 1289 * Return: 0 on success, negative errno otherwise
1340 **/ 1290 */
1341static int xuartps_probe(struct platform_device *pdev) 1291static int cdns_uart_probe(struct platform_device *pdev)
1342{ 1292{
1343 int rc; 1293 int rc, id;
1344 struct uart_port *port; 1294 struct uart_port *port;
1345 struct resource *res, *res2; 1295 struct resource *res, *res2;
1346 struct xuartps *xuartps_data; 1296 struct cdns_uart *cdns_uart_data;
1347 1297
1348 xuartps_data = devm_kzalloc(&pdev->dev, sizeof(*xuartps_data), 1298 cdns_uart_data = devm_kzalloc(&pdev->dev, sizeof(*cdns_uart_data),
1349 GFP_KERNEL); 1299 GFP_KERNEL);
1350 if (!xuartps_data) 1300 if (!cdns_uart_data)
1351 return -ENOMEM; 1301 return -ENOMEM;
1352 1302
1353 xuartps_data->aperclk = devm_clk_get(&pdev->dev, "aper_clk"); 1303 cdns_uart_data->pclk = devm_clk_get(&pdev->dev, "pclk");
1354 if (IS_ERR(xuartps_data->aperclk)) { 1304 if (IS_ERR(cdns_uart_data->pclk)) {
1355 dev_err(&pdev->dev, "aper_clk clock not found.\n"); 1305 cdns_uart_data->pclk = devm_clk_get(&pdev->dev, "aper_clk");
1356 return PTR_ERR(xuartps_data->aperclk); 1306 if (!IS_ERR(cdns_uart_data->pclk))
1307 dev_err(&pdev->dev, "clock name 'aper_clk' is deprecated.\n");
1357 } 1308 }
1358 xuartps_data->refclk = devm_clk_get(&pdev->dev, "ref_clk"); 1309 if (IS_ERR(cdns_uart_data->pclk)) {
1359 if (IS_ERR(xuartps_data->refclk)) { 1310 dev_err(&pdev->dev, "pclk clock not found.\n");
1360 dev_err(&pdev->dev, "ref_clk clock not found.\n"); 1311 return PTR_ERR(cdns_uart_data->pclk);
1361 return PTR_ERR(xuartps_data->refclk);
1362 } 1312 }
1363 1313
1364 rc = clk_prepare_enable(xuartps_data->aperclk); 1314 cdns_uart_data->uartclk = devm_clk_get(&pdev->dev, "uart_clk");
1315 if (IS_ERR(cdns_uart_data->uartclk)) {
1316 cdns_uart_data->uartclk = devm_clk_get(&pdev->dev, "ref_clk");
1317 if (!IS_ERR(cdns_uart_data->uartclk))
1318 dev_err(&pdev->dev, "clock name 'ref_clk' is deprecated.\n");
1319 }
1320 if (IS_ERR(cdns_uart_data->uartclk)) {
1321 dev_err(&pdev->dev, "uart_clk clock not found.\n");
1322 return PTR_ERR(cdns_uart_data->uartclk);
1323 }
1324
1325 rc = clk_prepare_enable(cdns_uart_data->pclk);
1365 if (rc) { 1326 if (rc) {
1366 dev_err(&pdev->dev, "Unable to enable APER clock.\n"); 1327 dev_err(&pdev->dev, "Unable to enable pclk clock.\n");
1367 return rc; 1328 return rc;
1368 } 1329 }
1369 rc = clk_prepare_enable(xuartps_data->refclk); 1330 rc = clk_prepare_enable(cdns_uart_data->uartclk);
1370 if (rc) { 1331 if (rc) {
1371 dev_err(&pdev->dev, "Unable to enable device clock.\n"); 1332 dev_err(&pdev->dev, "Unable to enable device clock.\n");
1372 goto err_out_clk_dis_aper; 1333 goto err_out_clk_dis_pclk;
1373 } 1334 }
1374 1335
1375 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1336 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
@@ -1385,15 +1346,19 @@ static int xuartps_probe(struct platform_device *pdev)
1385 } 1346 }
1386 1347
1387#ifdef CONFIG_COMMON_CLK 1348#ifdef CONFIG_COMMON_CLK
1388 xuartps_data->clk_rate_change_nb.notifier_call = 1349 cdns_uart_data->clk_rate_change_nb.notifier_call =
1389 xuartps_clk_notifier_cb; 1350 cdns_uart_clk_notifier_cb;
1390 if (clk_notifier_register(xuartps_data->refclk, 1351 if (clk_notifier_register(cdns_uart_data->uartclk,
1391 &xuartps_data->clk_rate_change_nb)) 1352 &cdns_uart_data->clk_rate_change_nb))
1392 dev_warn(&pdev->dev, "Unable to register clock notifier.\n"); 1353 dev_warn(&pdev->dev, "Unable to register clock notifier.\n");
1393#endif 1354#endif
1355 /* Look for a serialN alias */
1356 id = of_alias_get_id(pdev->dev.of_node, "serial");
1357 if (id < 0)
1358 id = 0;
1394 1359
1395 /* Initialize the port structure */ 1360 /* Initialize the port structure */
1396 port = xuartps_get_port(); 1361 port = cdns_uart_get_port(id);
1397 1362
1398 if (!port) { 1363 if (!port) {
1399 dev_err(&pdev->dev, "Cannot get uart_port structure\n"); 1364 dev_err(&pdev->dev, "Cannot get uart_port structure\n");
@@ -1407,11 +1372,11 @@ static int xuartps_probe(struct platform_device *pdev)
1407 port->mapbase = res->start; 1372 port->mapbase = res->start;
1408 port->irq = res2->start; 1373 port->irq = res2->start;
1409 port->dev = &pdev->dev; 1374 port->dev = &pdev->dev;
1410 port->uartclk = clk_get_rate(xuartps_data->refclk); 1375 port->uartclk = clk_get_rate(cdns_uart_data->uartclk);
1411 port->private_data = xuartps_data; 1376 port->private_data = cdns_uart_data;
1412 xuartps_data->port = port; 1377 cdns_uart_data->port = port;
1413 platform_set_drvdata(pdev, port); 1378 platform_set_drvdata(pdev, port);
1414 rc = uart_add_one_port(&xuartps_uart_driver, port); 1379 rc = uart_add_one_port(&cdns_uart_uart_driver, port);
1415 if (rc) { 1380 if (rc) {
1416 dev_err(&pdev->dev, 1381 dev_err(&pdev->dev,
1417 "uart_add_one_port() failed; err=%i\n", rc); 1382 "uart_add_one_port() failed; err=%i\n", rc);
@@ -1422,103 +1387,89 @@ static int xuartps_probe(struct platform_device *pdev)
1422 1387
1423err_out_notif_unreg: 1388err_out_notif_unreg:
1424#ifdef CONFIG_COMMON_CLK 1389#ifdef CONFIG_COMMON_CLK
1425 clk_notifier_unregister(xuartps_data->refclk, 1390 clk_notifier_unregister(cdns_uart_data->uartclk,
1426 &xuartps_data->clk_rate_change_nb); 1391 &cdns_uart_data->clk_rate_change_nb);
1427#endif 1392#endif
1428err_out_clk_disable: 1393err_out_clk_disable:
1429 clk_disable_unprepare(xuartps_data->refclk); 1394 clk_disable_unprepare(cdns_uart_data->uartclk);
1430err_out_clk_dis_aper: 1395err_out_clk_dis_pclk:
1431 clk_disable_unprepare(xuartps_data->aperclk); 1396 clk_disable_unprepare(cdns_uart_data->pclk);
1432 1397
1433 return rc; 1398 return rc;
1434} 1399}
1435 1400
1436/** 1401/**
1437 * xuartps_remove - called when the platform driver is unregistered 1402 * cdns_uart_remove - called when the platform driver is unregistered
1438 * @pdev: Pointer to the platform device structure 1403 * @pdev: Pointer to the platform device structure
1439 * 1404 *
1440 * Returns 0 on success, negative error otherwise 1405 * Return: 0 on success, negative errno otherwise
1441 **/ 1406 */
1442static int xuartps_remove(struct platform_device *pdev) 1407static int cdns_uart_remove(struct platform_device *pdev)
1443{ 1408{
1444 struct uart_port *port = platform_get_drvdata(pdev); 1409 struct uart_port *port = platform_get_drvdata(pdev);
1445 struct xuartps *xuartps_data = port->private_data; 1410 struct cdns_uart *cdns_uart_data = port->private_data;
1446 int rc; 1411 int rc;
1447 1412
1448 /* Remove the xuartps port from the serial core */ 1413 /* Remove the cdns_uart port from the serial core */
1449#ifdef CONFIG_COMMON_CLK 1414#ifdef CONFIG_COMMON_CLK
1450 clk_notifier_unregister(xuartps_data->refclk, 1415 clk_notifier_unregister(cdns_uart_data->uartclk,
1451 &xuartps_data->clk_rate_change_nb); 1416 &cdns_uart_data->clk_rate_change_nb);
1452#endif 1417#endif
1453 rc = uart_remove_one_port(&xuartps_uart_driver, port); 1418 rc = uart_remove_one_port(&cdns_uart_uart_driver, port);
1454 port->mapbase = 0; 1419 port->mapbase = 0;
1455 clk_disable_unprepare(xuartps_data->refclk); 1420 clk_disable_unprepare(cdns_uart_data->uartclk);
1456 clk_disable_unprepare(xuartps_data->aperclk); 1421 clk_disable_unprepare(cdns_uart_data->pclk);
1457 return rc; 1422 return rc;
1458} 1423}
1459 1424
1460/* Match table for of_platform binding */ 1425/* Match table for of_platform binding */
1461static struct of_device_id xuartps_of_match[] = { 1426static struct of_device_id cdns_uart_of_match[] = {
1462 { .compatible = "xlnx,xuartps", }, 1427 { .compatible = "xlnx,xuartps", },
1428 { .compatible = "cdns,uart-r1p8", },
1463 {} 1429 {}
1464}; 1430};
1465MODULE_DEVICE_TABLE(of, xuartps_of_match); 1431MODULE_DEVICE_TABLE(of, cdns_uart_of_match);
1466 1432
1467static struct platform_driver xuartps_platform_driver = { 1433static struct platform_driver cdns_uart_platform_driver = {
1468 .probe = xuartps_probe, /* Probe method */ 1434 .probe = cdns_uart_probe,
1469 .remove = xuartps_remove, /* Detach method */ 1435 .remove = cdns_uart_remove,
1470 .driver = { 1436 .driver = {
1471 .owner = THIS_MODULE, 1437 .owner = THIS_MODULE,
1472 .name = XUARTPS_NAME, /* Driver name */ 1438 .name = CDNS_UART_NAME,
1473 .of_match_table = xuartps_of_match, 1439 .of_match_table = cdns_uart_of_match,
1474 .pm = &xuartps_dev_pm_ops, 1440 .pm = &cdns_uart_dev_pm_ops,
1475 }, 1441 },
1476}; 1442};
1477 1443
1478/* --------------------------------------------------------------------- 1444static int __init cdns_uart_init(void)
1479 * Module Init and Exit
1480 */
1481/**
1482 * xuartps_init - Initial driver registration call
1483 *
1484 * Returns whether the registration was successful or not
1485 **/
1486static int __init xuartps_init(void)
1487{ 1445{
1488 int retval = 0; 1446 int retval = 0;
1489 1447
1490 /* Register the xuartps driver with the serial core */ 1448 /* Register the cdns_uart driver with the serial core */
1491 retval = uart_register_driver(&xuartps_uart_driver); 1449 retval = uart_register_driver(&cdns_uart_uart_driver);
1492 if (retval) 1450 if (retval)
1493 return retval; 1451 return retval;
1494 1452
1495 /* Register the platform driver */ 1453 /* Register the platform driver */
1496 retval = platform_driver_register(&xuartps_platform_driver); 1454 retval = platform_driver_register(&cdns_uart_platform_driver);
1497 if (retval) 1455 if (retval)
1498 uart_unregister_driver(&xuartps_uart_driver); 1456 uart_unregister_driver(&cdns_uart_uart_driver);
1499 1457
1500 return retval; 1458 return retval;
1501} 1459}
1502 1460
1503/** 1461static void __exit cdns_uart_exit(void)
1504 * xuartps_exit - Driver unregistration call
1505 **/
1506static void __exit xuartps_exit(void)
1507{ 1462{
1508 /* The order of unregistration is important. Unregister the
1509 * UART driver before the platform driver crashes the system.
1510 */
1511
1512 /* Unregister the platform driver */ 1463 /* Unregister the platform driver */
1513 platform_driver_unregister(&xuartps_platform_driver); 1464 platform_driver_unregister(&cdns_uart_platform_driver);
1514 1465
1515 /* Unregister the xuartps driver */ 1466 /* Unregister the cdns_uart driver */
1516 uart_unregister_driver(&xuartps_uart_driver); 1467 uart_unregister_driver(&cdns_uart_uart_driver);
1517} 1468}
1518 1469
1519module_init(xuartps_init); 1470module_init(cdns_uart_init);
1520module_exit(xuartps_exit); 1471module_exit(cdns_uart_exit);
1521 1472
1522MODULE_DESCRIPTION("Driver for PS UART"); 1473MODULE_DESCRIPTION("Driver for Cadence UART");
1523MODULE_AUTHOR("Xilinx Inc."); 1474MODULE_AUTHOR("Xilinx Inc.");
1524MODULE_LICENSE("GPL"); 1475MODULE_LICENSE("GPL");
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-11 18:16:06 -0500