diff options
| author | Heikki Krogerus <heikki.krogerus@linux.intel.com> | 2015-03-18 06:55:13 -0400 |
|---|---|---|
| committer | Greg Kroah-Hartman <gregkh@linuxfoundation.org> | 2015-03-26 18:04:42 -0400 |
| commit | 23f5b3fdd04e89b4c67fd9ffa60a193d239acf0f (patch) | |
| tree | a04625a6cd8f9a6cf8f10737a6ff2e323882f938 /drivers/tty | |
| parent | 9001c07995fdd1f3657408c71bca7d6c5fb87fd3 (diff) | |
serial: 8250_dw: only get the clock rate in one place
The clock rate is requested from a property called
"clock-frequency" in both dw8250_probe_of and
dw8250_probe_acpi. Moving the requests to dw8250_probe.
Signed-off-by: Heikki Krogerus <heikki.krogerus@linux.intel.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Diffstat (limited to 'drivers/tty')
| -rw-r--r-- | drivers/tty/serial/8250/8250_dw.c | 30 |
1 files changed, 13 insertions, 17 deletions
diff --git a/drivers/tty/serial/8250/8250_dw.c b/drivers/tty/serial/8250/8250_dw.c index cc943fe3fd68..176f18f2e3ab 100644 --- a/drivers/tty/serial/8250/8250_dw.c +++ b/drivers/tty/serial/8250/8250_dw.c | |||
| @@ -374,17 +374,6 @@ static int dw8250_probe_of(struct uart_port *p, | |||
| 374 | data->msr_mask_off |= UART_MSR_TERI; | 374 | data->msr_mask_off |= UART_MSR_TERI; |
| 375 | } | 375 | } |
| 376 | 376 | ||
| 377 | /* clock got configured through clk api, all done */ | ||
| 378 | if (p->uartclk) | ||
| 379 | return 0; | ||
| 380 | |||
| 381 | /* try to find out clock frequency from DT as fallback */ | ||
| 382 | if (of_property_read_u32(np, "clock-frequency", &val)) { | ||
| 383 | dev_err(p->dev, "clk or clock-frequency not defined\n"); | ||
| 384 | return -EINVAL; | ||
| 385 | } | ||
| 386 | p->uartclk = val; | ||
| 387 | |||
| 388 | return 0; | 377 | return 0; |
| 389 | } | 378 | } |
| 390 | 379 | ||
| @@ -395,11 +384,6 @@ static int dw8250_probe_acpi(struct uart_8250_port *up, | |||
| 395 | 384 | ||
| 396 | dw8250_setup_port(up); | 385 | dw8250_setup_port(up); |
| 397 | 386 | ||
| 398 | if (!p->uartclk) | ||
| 399 | if (device_property_read_u32(p->dev, "clock-frequency", | ||
| 400 | &p->uartclk)) | ||
| 401 | return -EINVAL; | ||
| 402 | |||
| 403 | p->iotype = UPIO_MEM32; | 387 | p->iotype = UPIO_MEM32; |
| 404 | p->serial_in = dw8250_serial_in32; | 388 | p->serial_in = dw8250_serial_in32; |
| 405 | p->serial_out = dw8250_serial_out32; | 389 | p->serial_out = dw8250_serial_out32; |
| @@ -453,12 +437,18 @@ static int dw8250_probe(struct platform_device *pdev) | |||
| 453 | return -ENOMEM; | 437 | return -ENOMEM; |
| 454 | 438 | ||
| 455 | data->usr_reg = DW_UART_USR; | 439 | data->usr_reg = DW_UART_USR; |
| 440 | |||
| 441 | /* Always ask for fixed clock rate from a property. */ | ||
| 442 | device_property_read_u32(&pdev->dev, "clock-frequency", | ||
| 443 | &uart.port.uartclk); | ||
| 444 | |||
| 445 | /* If there is separate baudclk, get the rate from it. */ | ||
| 456 | data->clk = devm_clk_get(&pdev->dev, "baudclk"); | 446 | data->clk = devm_clk_get(&pdev->dev, "baudclk"); |
| 457 | if (IS_ERR(data->clk) && PTR_ERR(data->clk) != -EPROBE_DEFER) | 447 | if (IS_ERR(data->clk) && PTR_ERR(data->clk) != -EPROBE_DEFER) |
| 458 | data->clk = devm_clk_get(&pdev->dev, NULL); | 448 | data->clk = devm_clk_get(&pdev->dev, NULL); |
| 459 | if (IS_ERR(data->clk) && PTR_ERR(data->clk) == -EPROBE_DEFER) | 449 | if (IS_ERR(data->clk) && PTR_ERR(data->clk) == -EPROBE_DEFER) |
| 460 | return -EPROBE_DEFER; | 450 | return -EPROBE_DEFER; |
| 461 | if (!IS_ERR(data->clk)) { | 451 | if (!IS_ERR_OR_NULL(data->clk)) { |
| 462 | err = clk_prepare_enable(data->clk); | 452 | err = clk_prepare_enable(data->clk); |
| 463 | if (err) | 453 | if (err) |
| 464 | dev_warn(&pdev->dev, "could not enable optional baudclk: %d\n", | 454 | dev_warn(&pdev->dev, "could not enable optional baudclk: %d\n", |
| @@ -467,6 +457,12 @@ static int dw8250_probe(struct platform_device *pdev) | |||
| 467 | uart.port.uartclk = clk_get_rate(data->clk); | 457 | uart.port.uartclk = clk_get_rate(data->clk); |
| 468 | } | 458 | } |
| 469 | 459 | ||
| 460 | /* If no clock rate is defined, fail. */ | ||
| 461 | if (!uart.port.uartclk) { | ||
| 462 | dev_err(&pdev->dev, "clock rate not defined\n"); | ||
| 463 | return -EINVAL; | ||
| 464 | } | ||
| 465 | |||
| 470 | data->pclk = devm_clk_get(&pdev->dev, "apb_pclk"); | 466 | data->pclk = devm_clk_get(&pdev->dev, "apb_pclk"); |
| 471 | if (IS_ERR(data->clk) && PTR_ERR(data->clk) == -EPROBE_DEFER) { | 467 | if (IS_ERR(data->clk) && PTR_ERR(data->clk) == -EPROBE_DEFER) { |
| 472 | err = -EPROBE_DEFER; | 468 | err = -EPROBE_DEFER; |
