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authorPaul Mundt <lethal@linux-sh.org>2011-06-13 23:40:19 -0400
committerPaul Mundt <lethal@linux-sh.org>2011-06-13 23:40:19 -0400
commit61a6976bf19a6cf5dfcf37c3536665b316f22d49 (patch)
tree969831bb2a782454960a82a77d2802f62cc7ed91 /drivers/tty/serial/sh-sci.h
parente13198894bf6308c097e5678ee315e12b2e1b7a8 (diff)
serial: sh-sci: Abstract register maps.
This takes a bit of a sledgehammer to the horribly CPU subtype ifdef-ridden header and abstracts all of the different register layouts in to distinct types which in turn can be overriden on a per-port basis, or permitted to default to the map matching the port type at probe time. In the process this ultimately fixes up inumerable bugs with mismatches on various CPU types (particularly the legacy ones that were obviously broken years ago and no one noticed) and provides a more tightly coupled and consolidated platform for extending and implementing generic features. Signed-off-by: Paul Mundt <lethal@linux-sh.org>
Diffstat (limited to 'drivers/tty/serial/sh-sci.h')
-rw-r--r--drivers/tty/serial/sh-sci.h222
1 files changed, 0 insertions, 222 deletions
diff --git a/drivers/tty/serial/sh-sci.h b/drivers/tty/serial/sh-sci.h
index 5834f33d20ff..26de640a9d01 100644
--- a/drivers/tty/serial/sh-sci.h
+++ b/drivers/tty/serial/sh-sci.h
@@ -3,69 +3,6 @@
3#include <linux/gpio.h> 3#include <linux/gpio.h>
4 4
5#if defined(CONFIG_CPU_SUBTYPE_SH7705) || \ 5#if defined(CONFIG_CPU_SUBTYPE_SH7705) || \
6 defined(CONFIG_CPU_SUBTYPE_SH7706) || \
7 defined(CONFIG_CPU_SUBTYPE_SH7707) || \
8 defined(CONFIG_CPU_SUBTYPE_SH7708) || \
9 defined(CONFIG_CPU_SUBTYPE_SH7709)
10# define SCPCR 0xA4000116 /* 16 bit SCI and SCIF */
11# define SCPDR 0xA4000136 /* 8 bit SCI and SCIF */
12#elif defined(CONFIG_CPU_SUBTYPE_SH7720) || \
13 defined(CONFIG_CPU_SUBTYPE_SH7721) || \
14 defined(CONFIG_ARCH_SH73A0) || \
15 defined(CONFIG_ARCH_SH7367) || \
16 defined(CONFIG_ARCH_SH7377) || \
17 defined(CONFIG_ARCH_SH7372)
18# define PORT_PTCR 0xA405011EUL
19# define PORT_PVCR 0xA4050122UL
20#elif defined(CONFIG_CPU_SUBTYPE_SH7750) || \
21 defined(CONFIG_CPU_SUBTYPE_SH7750R) || \
22 defined(CONFIG_CPU_SUBTYPE_SH7750S) || \
23 defined(CONFIG_CPU_SUBTYPE_SH7091) || \
24 defined(CONFIG_CPU_SUBTYPE_SH7751) || \
25 defined(CONFIG_CPU_SUBTYPE_SH7751R) || \
26 defined(CONFIG_CPU_SUBTYPE_SH4_202)
27# define SCSPTR2 0xFFE80020 /* 16 bit SCIF */
28#elif defined(CONFIG_CPU_SUBTYPE_SH7760)
29# define SCSPTR0 0xfe600024 /* 16 bit SCIF */
30# define SCSPTR2 0xfe620024 /* 16 bit SCIF */
31#elif defined(CONFIG_CPU_SUBTYPE_SH7710) || defined(CONFIG_CPU_SUBTYPE_SH7712)
32# define SCSPTR0 0xA4400000 /* 16 bit SCIF */
33# define PACR 0xa4050100
34# define PBCR 0xa4050102
35#elif defined(CONFIG_CPU_SUBTYPE_SH7343)
36# define SCSPTR0 0xffe00010 /* 16 bit SCIF */
37#elif defined(CONFIG_CPU_SUBTYPE_SH7722)
38# define PWDR 0xA4050166
39# define PSCR 0xA405011E
40#elif defined(CONFIG_CPU_SUBTYPE_SH7366)
41# define SCPDR0 0xA405013E /* 16 bit SCIF0 PSDR */
42# define SCSPTR0 SCPDR0
43#elif defined(CONFIG_CPU_SUBTYPE_SH7723)
44# define SCSPTR0 0xa4050160
45#elif defined(CONFIG_CPU_SUBTYPE_SH7757)
46# define SCSPTR0 0xfe4b0020
47#elif defined(CONFIG_CPU_SUBTYPE_SH7763) || \
48 defined(CONFIG_CPU_SUBTYPE_SH7780)
49# define SCSPTR0 0xffe00024 /* 16 bit SCIF */
50#elif defined(CONFIG_CPU_SUBTYPE_SH7770)
51# define SCSPTR0 0xff923020 /* 16 bit SCIF */
52#elif defined(CONFIG_CPU_SUBTYPE_SH7785) || \
53 defined(CONFIG_CPU_SUBTYPE_SH7786)
54# define SCSPTR0 0xffea0024 /* 16 bit SCIF */
55#elif defined(CONFIG_CPU_SUBTYPE_SH7201) || \
56 defined(CONFIG_CPU_SUBTYPE_SH7203) || \
57 defined(CONFIG_CPU_SUBTYPE_SH7206) || \
58 defined(CONFIG_CPU_SUBTYPE_SH7263)
59# define SCSPTR0 0xfffe8020 /* 16 bit SCIF */
60#elif defined(CONFIG_CPU_SUBTYPE_SH7619)
61# define SCSPTR0 0xf8400020 /* 16 bit SCIF */
62#elif defined(CONFIG_CPU_SUBTYPE_SHX3)
63# define SCSPTR0 0xffc30020 /* 16 bit SCIF */
64#else
65# error CPU subtype not defined
66#endif
67
68#if defined(CONFIG_CPU_SUBTYPE_SH7705) || \
69 defined(CONFIG_CPU_SUBTYPE_SH7720) || \ 6 defined(CONFIG_CPU_SUBTYPE_SH7720) || \
70 defined(CONFIG_CPU_SUBTYPE_SH7721) || \ 7 defined(CONFIG_CPU_SUBTYPE_SH7721) || \
71 defined(CONFIG_ARCH_SH73A0) || \ 8 defined(CONFIG_ARCH_SH73A0) || \
@@ -119,162 +56,3 @@
119 56
120#define SCI_MAJOR 204 57#define SCI_MAJOR 204
121#define SCI_MINOR_START 8 58#define SCI_MINOR_START 8
122
123#define SCI_IN(size, offset) \
124 ioread##size(port->membase + (offset))
125
126#define SCI_OUT(size, offset, value) \
127 iowrite##size(value, port->membase + (offset))
128
129#define CPU_SCIx_FNS(name, sci_offset, sci_size, scif_offset, scif_size)\
130 static inline unsigned int sci_##name##_in(struct uart_port *port) \
131 { \
132 if (port->type == PORT_SCIF || port->type == PORT_SCIFB) { \
133 return SCI_IN(scif_size, scif_offset); \
134 } else { /* PORT_SCI or PORT_SCIFA */ \
135 return SCI_IN(sci_size, sci_offset); \
136 } \
137 } \
138 static inline void sci_##name##_out(struct uart_port *port, unsigned int value) \
139 { \
140 if (port->type == PORT_SCIF || port->type == PORT_SCIFB) { \
141 SCI_OUT(scif_size, scif_offset, value); \
142 } else { /* PORT_SCI or PORT_SCIFA */ \
143 SCI_OUT(sci_size, sci_offset, value); \
144 } \
145 }
146
147#define CPU_SCIF_FNS(name, scif_offset, scif_size) \
148 static inline unsigned int sci_##name##_in(struct uart_port *port) \
149 { \
150 return SCI_IN(scif_size, scif_offset); \
151 } \
152 static inline void sci_##name##_out(struct uart_port *port, unsigned int value) \
153 { \
154 SCI_OUT(scif_size, scif_offset, value); \
155 }
156
157#if defined(CONFIG_CPU_SH3) || \
158 defined(CONFIG_ARCH_SH73A0) || \
159 defined(CONFIG_ARCH_SH7367) || \
160 defined(CONFIG_ARCH_SH7377) || \
161 defined(CONFIG_ARCH_SH7372)
162#if defined(CONFIG_CPU_SUBTYPE_SH7710) || defined(CONFIG_CPU_SUBTYPE_SH7712)
163#define SCIx_FNS(name, sh3_sci_offset, sh3_sci_size, sh4_sci_offset, sh4_sci_size, \
164 sh3_scif_offset, sh3_scif_size, sh4_scif_offset, sh4_scif_size) \
165 CPU_SCIx_FNS(name, sh4_sci_offset, sh4_sci_size, sh4_scif_offset, sh4_scif_size)
166#define SCIF_FNS(name, sh3_scif_offset, sh3_scif_size, sh4_scif_offset, sh4_scif_size) \
167 CPU_SCIF_FNS(name, sh4_scif_offset, sh4_scif_size)
168#elif defined(CONFIG_CPU_SUBTYPE_SH7705) || \
169 defined(CONFIG_CPU_SUBTYPE_SH7720) || \
170 defined(CONFIG_CPU_SUBTYPE_SH7721) || \
171 defined(CONFIG_ARCH_SH7367)
172#define SCIF_FNS(name, scif_offset, scif_size) \
173 CPU_SCIF_FNS(name, scif_offset, scif_size)
174#elif defined(CONFIG_ARCH_SH7377) || \
175 defined(CONFIG_ARCH_SH7372) || \
176 defined(CONFIG_ARCH_SH73A0)
177#define SCIx_FNS(name, sh4_scifa_offset, sh4_scifa_size, sh4_scifb_offset, sh4_scifb_size) \
178 CPU_SCIx_FNS(name, sh4_scifa_offset, sh4_scifa_size, sh4_scifb_offset, sh4_scifb_size)
179#define SCIF_FNS(name, scif_offset, scif_size) \
180 CPU_SCIF_FNS(name, scif_offset, scif_size)
181#else
182#define SCIx_FNS(name, sh3_sci_offset, sh3_sci_size, sh4_sci_offset, sh4_sci_size, \
183 sh3_scif_offset, sh3_scif_size, sh4_scif_offset, sh4_scif_size) \
184 CPU_SCIx_FNS(name, sh3_sci_offset, sh3_sci_size, sh3_scif_offset, sh3_scif_size)
185#define SCIF_FNS(name, sh3_scif_offset, sh3_scif_size, sh4_scif_offset, sh4_scif_size) \
186 CPU_SCIF_FNS(name, sh3_scif_offset, sh3_scif_size)
187#endif
188#elif defined(CONFIG_CPU_SUBTYPE_SH7723) ||\
189 defined(CONFIG_CPU_SUBTYPE_SH7724)
190 #define SCIx_FNS(name, sh4_scifa_offset, sh4_scifa_size, sh4_scif_offset, sh4_scif_size) \
191 CPU_SCIx_FNS(name, sh4_scifa_offset, sh4_scifa_size, sh4_scif_offset, sh4_scif_size)
192 #define SCIF_FNS(name, sh4_scif_offset, sh4_scif_size) \
193 CPU_SCIF_FNS(name, sh4_scif_offset, sh4_scif_size)
194#else
195#define SCIx_FNS(name, sh3_sci_offset, sh3_sci_size, sh4_sci_offset, sh4_sci_size, \
196 sh3_scif_offset, sh3_scif_size, sh4_scif_offset, sh4_scif_size) \
197 CPU_SCIx_FNS(name, sh4_sci_offset, sh4_sci_size, sh4_scif_offset, sh4_scif_size)
198#define SCIF_FNS(name, sh3_scif_offset, sh3_scif_size, sh4_scif_offset, sh4_scif_size) \
199 CPU_SCIF_FNS(name, sh4_scif_offset, sh4_scif_size)
200#endif
201
202#if defined(CONFIG_CPU_SUBTYPE_SH7705) || \
203 defined(CONFIG_CPU_SUBTYPE_SH7720) || \
204 defined(CONFIG_CPU_SUBTYPE_SH7721) || \
205 defined(CONFIG_ARCH_SH7367)
206
207SCIF_FNS(SCSMR, 0x00, 16)
208SCIF_FNS(SCBRR, 0x04, 8)
209SCIF_FNS(SCSCR, 0x08, 16)
210SCIF_FNS(SCxSR, 0x14, 16)
211SCIF_FNS(SCFCR, 0x18, 16)
212SCIF_FNS(SCFDR, 0x1c, 16)
213SCIF_FNS(SCxTDR, 0x20, 8)
214SCIF_FNS(SCxRDR, 0x24, 8)
215SCIF_FNS(SCLSR, 0x00, 0)
216#elif defined(CONFIG_ARCH_SH7377) || \
217 defined(CONFIG_ARCH_SH7372) || \
218 defined(CONFIG_ARCH_SH73A0)
219SCIF_FNS(SCSMR, 0x00, 16)
220SCIF_FNS(SCBRR, 0x04, 8)
221SCIF_FNS(SCSCR, 0x08, 16)
222SCIF_FNS(SCTDSR, 0x0c, 16)
223SCIF_FNS(SCFER, 0x10, 16)
224SCIF_FNS(SCxSR, 0x14, 16)
225SCIF_FNS(SCFCR, 0x18, 16)
226SCIF_FNS(SCFDR, 0x1c, 16)
227SCIF_FNS(SCTFDR, 0x38, 16)
228SCIF_FNS(SCRFDR, 0x3c, 16)
229SCIx_FNS(SCxTDR, 0x20, 8, 0x40, 8)
230SCIx_FNS(SCxRDR, 0x24, 8, 0x60, 8)
231SCIF_FNS(SCLSR, 0x00, 0)
232#elif defined(CONFIG_CPU_SUBTYPE_SH7723) ||\
233 defined(CONFIG_CPU_SUBTYPE_SH7724)
234SCIx_FNS(SCSMR, 0x00, 16, 0x00, 16)
235SCIx_FNS(SCBRR, 0x04, 8, 0x04, 8)
236SCIx_FNS(SCSCR, 0x08, 16, 0x08, 16)
237SCIx_FNS(SCxTDR, 0x20, 8, 0x0c, 8)
238SCIx_FNS(SCxSR, 0x14, 16, 0x10, 16)
239SCIx_FNS(SCxRDR, 0x24, 8, 0x14, 8)
240SCIx_FNS(SCSPTR, 0, 0, 0, 0)
241SCIF_FNS(SCFCR, 0x18, 16)
242SCIF_FNS(SCFDR, 0x1c, 16)
243SCIF_FNS(SCLSR, 0x24, 16)
244#else
245/* reg SCI/SH3 SCI/SH4 SCIF/SH3 SCIF/SH4 */
246/* name off sz off sz off sz off sz */
247SCIx_FNS(SCSMR, 0x00, 8, 0x00, 8, 0x00, 8, 0x00, 16)
248SCIx_FNS(SCBRR, 0x02, 8, 0x04, 8, 0x02, 8, 0x04, 8)
249SCIx_FNS(SCSCR, 0x04, 8, 0x08, 8, 0x04, 8, 0x08, 16)
250SCIx_FNS(SCxTDR, 0x06, 8, 0x0c, 8, 0x06, 8, 0x0C, 8)
251SCIx_FNS(SCxSR, 0x08, 8, 0x10, 8, 0x08, 16, 0x10, 16)
252SCIx_FNS(SCxRDR, 0x0a, 8, 0x14, 8, 0x0A, 8, 0x14, 8)
253SCIF_FNS(SCFCR, 0x0c, 8, 0x18, 16)
254#if defined(CONFIG_CPU_SUBTYPE_SH7760) || \
255 defined(CONFIG_CPU_SUBTYPE_SH7780) || \
256 defined(CONFIG_CPU_SUBTYPE_SH7785) || \
257 defined(CONFIG_CPU_SUBTYPE_SH7786)
258SCIF_FNS(SCFDR, 0x0e, 16, 0x1C, 16)
259SCIF_FNS(SCTFDR, 0x0e, 16, 0x1C, 16)
260SCIF_FNS(SCRFDR, 0x0e, 16, 0x20, 16)
261SCIF_FNS(SCSPTR, 0, 0, 0x24, 16)
262SCIF_FNS(SCLSR, 0, 0, 0x28, 16)
263#elif defined(CONFIG_CPU_SUBTYPE_SH7763)
264SCIF_FNS(SCFDR, 0, 0, 0x1C, 16)
265SCIF_FNS(SCTFDR, 0x0e, 16, 0x1C, 16)
266SCIF_FNS(SCRFDR, 0x0e, 16, 0x20, 16)
267SCIF_FNS(SCSPTR, 0, 0, 0x24, 16)
268SCIF_FNS(SCLSR, 0, 0, 0x28, 16)
269#else
270SCIF_FNS(SCFDR, 0x0e, 16, 0x1C, 16)
271#if defined(CONFIG_CPU_SUBTYPE_SH7722)
272SCIF_FNS(SCSPTR, 0, 0, 0, 0)
273#else
274SCIF_FNS(SCSPTR, 0, 0, 0x20, 16)
275#endif
276SCIF_FNS(SCLSR, 0, 0, 0x24, 16)
277#endif
278#endif
279#define sci_in(port, reg) sci_##reg##_in(port)
280#define sci_out(port, reg, value) sci_##reg##_out(port, value)
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