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authorRussell King <rmk+kernel@arm.linux.org.uk>2012-10-06 05:50:58 -0400
committerRussell King <rmk+kernel@arm.linux.org.uk>2012-11-04 07:14:20 -0500
commitf91b55ab72a913a8a61e377a7766772a20f0d96b (patch)
treea572b4b120875fad21b0c1543efb10e3cd06e8aa /drivers/tty/serial/omap-serial.c
parent4073a53b36ff993f7c4d158d1cf30d93c7d12add (diff)
SERIAL: omap: move driver private definitions and structures to driver
struct uart_omap_port and struct uart_omap_dma, and associated definitions are private to the driver, so there's no point them sitting in an include file under arch/arm. Move them into the driver itself. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Diffstat (limited to 'drivers/tty/serial/omap-serial.c')
-rw-r--r--drivers/tty/serial/omap-serial.c52
1 files changed, 52 insertions, 0 deletions
diff --git a/drivers/tty/serial/omap-serial.c b/drivers/tty/serial/omap-serial.c
index da46be3d57b1..17babde8febf 100644
--- a/drivers/tty/serial/omap-serial.c
+++ b/drivers/tty/serial/omap-serial.c
@@ -44,6 +44,8 @@
44 44
45#include <plat/omap-serial.h> 45#include <plat/omap-serial.h>
46 46
47#define OMAP_MAX_HSUART_PORTS 6
48
47#define UART_BUILD_REVISION(x, y) (((x) << 8) | (y)) 49#define UART_BUILD_REVISION(x, y) (((x) << 8) | (y))
48 50
49#define OMAP_UART_REV_42 0x0402 51#define OMAP_UART_REV_42 0x0402
@@ -51,10 +53,14 @@
51#define OMAP_UART_REV_52 0x0502 53#define OMAP_UART_REV_52 0x0502
52#define OMAP_UART_REV_63 0x0603 54#define OMAP_UART_REV_63 0x0603
53 55
56#define UART_ERRATA_i202_MDR1_ACCESS BIT(0)
57#define UART_ERRATA_i291_DMA_FORCEIDLE BIT(1)
58
54#define DEFAULT_CLK_SPEED 48000000 /* 48Mhz*/ 59#define DEFAULT_CLK_SPEED 48000000 /* 48Mhz*/
55 60
56/* SCR register bitmasks */ 61/* SCR register bitmasks */
57#define OMAP_UART_SCR_RX_TRIG_GRANU1_MASK (1 << 7) 62#define OMAP_UART_SCR_RX_TRIG_GRANU1_MASK (1 << 7)
63#define OMAP_UART_SCR_TX_EMPTY (1 << 3)
58 64
59/* FCR register bitmasks */ 65/* FCR register bitmasks */
60#define OMAP_UART_FCR_RX_FIFO_TRIG_MASK (0x3 << 6) 66#define OMAP_UART_FCR_RX_FIFO_TRIG_MASK (0x3 << 6)
@@ -71,6 +77,52 @@
71#define OMAP_UART_MVR_MAJ_SHIFT 8 77#define OMAP_UART_MVR_MAJ_SHIFT 8
72#define OMAP_UART_MVR_MIN_MASK 0x3f 78#define OMAP_UART_MVR_MIN_MASK 0x3f
73 79
80#define OMAP_UART_DMA_CH_FREE -1
81
82#define MSR_SAVE_FLAGS UART_MSR_ANY_DELTA
83#define OMAP_MODE13X_SPEED 230400
84
85/* WER = 0x7F
86 * Enable module level wakeup in WER reg
87 */
88#define OMAP_UART_WER_MOD_WKUP 0X7F
89
90/* Enable XON/XOFF flow control on output */
91#define OMAP_UART_SW_TX 0x4
92
93/* Enable XON/XOFF flow control on input */
94#define OMAP_UART_SW_RX 0x4
95
96#define OMAP_UART_SW_CLR 0xF0
97
98#define OMAP_UART_TCR_TRIG 0x0F
99
100struct uart_omap_dma {
101 u8 uart_dma_tx;
102 u8 uart_dma_rx;
103 int rx_dma_channel;
104 int tx_dma_channel;
105 dma_addr_t rx_buf_dma_phys;
106 dma_addr_t tx_buf_dma_phys;
107 unsigned int uart_base;
108 /*
109 * Buffer for rx dma.It is not required for tx because the buffer
110 * comes from port structure.
111 */
112 unsigned char *rx_buf;
113 unsigned int prev_rx_dma_pos;
114 int tx_buf_size;
115 int tx_dma_used;
116 int rx_dma_used;
117 spinlock_t tx_lock;
118 spinlock_t rx_lock;
119 /* timer to poll activity on rx dma */
120 struct timer_list rx_timer;
121 unsigned int rx_buf_size;
122 unsigned int rx_poll_rate;
123 unsigned int rx_timeout;
124};
125
74struct uart_omap_port { 126struct uart_omap_port {
75 struct uart_port port; 127 struct uart_port port;
76 struct uart_omap_dma uart_dma; 128 struct uart_omap_dma uart_dma;