serial: of: add a PORT_RT2880 definition

The Ralink RT2880 SoC and its successors have an internal 8250 core. This core
needs the same quirks applied as the AMD AU1xxx uart. In addition to these
quirks, the ports memory region is only 0x100 unlike the AU1xxx which has a
size of 0x1000.

Signed-off-by: John Crispin <blogic@openwrt.org>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>

1 files changed, 9 insertions, 1 deletions

diff --git a/drivers/tty/serial/of_serial.c b/drivers/tty/serial/of_serial.c
index 9c64ad2ac1a8..8749fb849803 100644
--- a/drivers/tty/serial/of_serial.c
+++ b/drivers/tty/serial/of_serial.c
@@ -130,8 +130,15 @@ static int of_platform_serial_setup(struct platform_device *ofdev,
 
         port->dev = &ofdev->dev;
 
-        if (type == PORT_TEGRA)
+        switch (type) {
+        case PORT_TEGRA:
                 port->handle_break = tegra_serial_handle_break;
+                break;
+
+        case PORT_RT2880:
+                port->iotype = UPIO_AU;
+                break;
+        }
 
         return 0;
 out:
@@ -317,6 +324,7 @@ static struct of_device_id of_platform_serial_table[] = {
         { .compatible = "ns16850",  .data = (void *)PORT_16850, },
         { .compatible = "nvidia,tegra20-uart", .data = (void *)PORT_TEGRA, },
         { .compatible = "nxp,lpc3220-uart", .data = (void *)PORT_LPC3220, },
+        { .compatible = "ralink,rt2880-uart", .data = (void *)PORT_RT2880, },
         { .compatible = "altr,16550-FIFO32",
                 .data = (void *)PORT_ALTR_16550_F32, },
         { .compatible = "altr,16550-FIFO64",