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authorFeng Tang <feng.tang@intel.com>2011-02-22 02:28:10 -0500
committerGreg Kroah-Hartman <gregkh@suse.de>2011-02-22 18:49:00 -0500
commit085a4f758f0cf95e1865b63892bf4304a149f0ca (patch)
treee2649fbbf7ccc74b506f9415f740730d503e97d2 /drivers/tty/serial/mfd.c
parent10e82f6ce76351425644bccc56f8e2c2ad596ce6 (diff)
serial: mfd: remove the TX full-empty interrupts workaround
In A0 stepping, TX half-empty interrupt is not working, so have to use the full-empty interrupts whose performance will be 15% lower. Now re-enable the half-empty interrrupt after it is enabled in silicon. Signed-off-by: Feng Tang <feng.tang@intel.com> Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
Diffstat (limited to 'drivers/tty/serial/mfd.c')
-rw-r--r--drivers/tty/serial/mfd.c26
1 files changed, 5 insertions, 21 deletions
diff --git a/drivers/tty/serial/mfd.c b/drivers/tty/serial/mfd.c
index 776777462937..53ff6af16273 100644
--- a/drivers/tty/serial/mfd.c
+++ b/drivers/tty/serial/mfd.c
@@ -16,9 +16,7 @@
16 * 2/3 chan to port 1, 4/5 chan to port 3. Even number chans 16 * 2/3 chan to port 1, 4/5 chan to port 3. Even number chans
17 * are used for RX, odd chans for TX 17 * are used for RX, odd chans for TX
18 * 18 *
19 * 2. In A0 stepping, UART will not support TX half empty flag 19 * 2. The RI/DSR/DCD/DTR are not pinned out, DCD & DSR are always
20 *
21 * 3. The RI/DSR/DCD/DTR are not pinned out, DCD & DSR are always
22 * asserted, only when the HW is reset the DDCD and DDSR will 20 * asserted, only when the HW is reset the DDCD and DDSR will
23 * be triggered 21 * be triggered
24 */ 22 */
@@ -41,8 +39,6 @@
41#include <linux/io.h> 39#include <linux/io.h>
42#include <linux/debugfs.h> 40#include <linux/debugfs.h>
43 41
44#define MFD_HSU_A0_STEPPING 1
45
46#define HSU_DMA_BUF_SIZE 2048 42#define HSU_DMA_BUF_SIZE 2048
47 43
48#define chan_readl(chan, offset) readl(chan->reg + offset) 44#define chan_readl(chan, offset) readl(chan->reg + offset)
@@ -543,16 +539,9 @@ static void transmit_chars(struct uart_hsu_port *up)
543 return; 539 return;
544 } 540 }
545 541
546#ifndef MFD_HSU_A0_STEPPING 542 /* The IRQ is for TX FIFO half-empty */
547 count = up->port.fifosize / 2; 543 count = up->port.fifosize / 2;
548#else 544
549 /*
550 * A0 only supports fully empty IRQ, and the first char written
551 * into it won't clear the EMPT bit, so we may need be cautious
552 * by useing a shorter buffer
553 */
554 count = up->port.fifosize - 4;
555#endif
556 do { 545 do {
557 serial_out(up, UART_TX, xmit->buf[xmit->tail]); 546 serial_out(up, UART_TX, xmit->buf[xmit->tail]);
558 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1); 547 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
@@ -761,9 +750,8 @@ static void serial_hsu_break_ctl(struct uart_port *port, int break_state)
761/* 750/*
762 * What special to do: 751 * What special to do:
763 * 1. chose the 64B fifo mode 752 * 1. chose the 64B fifo mode
764 * 2. make sure not to select half empty mode for A0 stepping 753 * 2. start dma or pio depends on configuration
765 * 3. start dma or pio depends on configuration 754 * 3. we only allocate dma memory when needed
766 * 4. we only allocate dma memory when needed
767 */ 755 */
768static int serial_hsu_startup(struct uart_port *port) 756static int serial_hsu_startup(struct uart_port *port)
769{ 757{
@@ -967,10 +955,6 @@ serial_hsu_set_termios(struct uart_port *port, struct ktermios *termios,
967 fcr = UART_FCR_ENABLE_FIFO | UART_FCR_HSU_64_32B; 955 fcr = UART_FCR_ENABLE_FIFO | UART_FCR_HSU_64_32B;
968 956
969 fcr |= UART_FCR_HSU_64B_FIFO; 957 fcr |= UART_FCR_HSU_64B_FIFO;
970#ifdef MFD_HSU_A0_STEPPING
971 /* A0 doesn't support half empty IRQ */
972 fcr |= UART_FCR_FULL_EMPT_TXI;
973#endif
974 958
975 /* 959 /*
976 * Ok, we're now changing the port state. Do it with 960 * Ok, we're now changing the port state. Do it with