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authorGreg Kroah-Hartman <gregkh@suse.de>2011-01-13 15:10:18 -0500
committerGreg Kroah-Hartman <gregkh@suse.de>2011-01-13 15:10:18 -0500
commitab4382d27412e7e3e7c936e8d50d8888dfac3df8 (patch)
tree51d96dea2431140358784b6b426715f37f74fd53 /drivers/tty/serial/8250_pci.c
parent728674a7e466628df2aeec6d11a2ae1ef968fb67 (diff)
tty: move drivers/serial/ to drivers/tty/serial/
The serial drivers are really just tty drivers, so move them to drivers/tty/ to make things a bit neater overall. This is part of the tty/serial driver movement proceedure as proposed by Arnd Bergmann and approved by everyone involved a number of months ago. Cc: Arnd Bergmann <arnd@arndb.de> Cc: Alan Cox <alan@lxorguk.ukuu.org.uk> Cc: Geert Uytterhoeven <geert@linux-m68k.org> Cc: Rogier Wolff <R.E.Wolff@bitwizard.nl> Cc: Michael H. Warfield <mhw@wittsend.com> Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
Diffstat (limited to 'drivers/tty/serial/8250_pci.c')
-rw-r--r--drivers/tty/serial/8250_pci.c3850
1 files changed, 3850 insertions, 0 deletions
diff --git a/drivers/tty/serial/8250_pci.c b/drivers/tty/serial/8250_pci.c
new file mode 100644
index 000000000000..8b8930f700b5
--- /dev/null
+++ b/drivers/tty/serial/8250_pci.c
@@ -0,0 +1,3850 @@
1/*
2 * linux/drivers/char/8250_pci.c
3 *
4 * Probe module for 8250/16550-type PCI serial ports.
5 *
6 * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
7 *
8 * Copyright (C) 2001 Russell King, All Rights Reserved.
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License.
13 */
14#include <linux/module.h>
15#include <linux/init.h>
16#include <linux/pci.h>
17#include <linux/string.h>
18#include <linux/kernel.h>
19#include <linux/slab.h>
20#include <linux/delay.h>
21#include <linux/tty.h>
22#include <linux/serial_core.h>
23#include <linux/8250_pci.h>
24#include <linux/bitops.h>
25
26#include <asm/byteorder.h>
27#include <asm/io.h>
28
29#include "8250.h"
30
31#undef SERIAL_DEBUG_PCI
32
33/*
34 * init function returns:
35 * > 0 - number of ports
36 * = 0 - use board->num_ports
37 * < 0 - error
38 */
39struct pci_serial_quirk {
40 u32 vendor;
41 u32 device;
42 u32 subvendor;
43 u32 subdevice;
44 int (*init)(struct pci_dev *dev);
45 int (*setup)(struct serial_private *,
46 const struct pciserial_board *,
47 struct uart_port *, int);
48 void (*exit)(struct pci_dev *dev);
49};
50
51#define PCI_NUM_BAR_RESOURCES 6
52
53struct serial_private {
54 struct pci_dev *dev;
55 unsigned int nr;
56 void __iomem *remapped_bar[PCI_NUM_BAR_RESOURCES];
57 struct pci_serial_quirk *quirk;
58 int line[0];
59};
60
61static void moan_device(const char *str, struct pci_dev *dev)
62{
63 printk(KERN_WARNING
64 "%s: %s\n"
65 "Please send the output of lspci -vv, this\n"
66 "message (0x%04x,0x%04x,0x%04x,0x%04x), the\n"
67 "manufacturer and name of serial board or\n"
68 "modem board to rmk+serial@arm.linux.org.uk.\n",
69 pci_name(dev), str, dev->vendor, dev->device,
70 dev->subsystem_vendor, dev->subsystem_device);
71}
72
73static int
74setup_port(struct serial_private *priv, struct uart_port *port,
75 int bar, int offset, int regshift)
76{
77 struct pci_dev *dev = priv->dev;
78 unsigned long base, len;
79
80 if (bar >= PCI_NUM_BAR_RESOURCES)
81 return -EINVAL;
82
83 base = pci_resource_start(dev, bar);
84
85 if (pci_resource_flags(dev, bar) & IORESOURCE_MEM) {
86 len = pci_resource_len(dev, bar);
87
88 if (!priv->remapped_bar[bar])
89 priv->remapped_bar[bar] = ioremap_nocache(base, len);
90 if (!priv->remapped_bar[bar])
91 return -ENOMEM;
92
93 port->iotype = UPIO_MEM;
94 port->iobase = 0;
95 port->mapbase = base + offset;
96 port->membase = priv->remapped_bar[bar] + offset;
97 port->regshift = regshift;
98 } else {
99 port->iotype = UPIO_PORT;
100 port->iobase = base + offset;
101 port->mapbase = 0;
102 port->membase = NULL;
103 port->regshift = 0;
104 }
105 return 0;
106}
107
108/*
109 * ADDI-DATA GmbH communication cards <info@addi-data.com>
110 */
111static int addidata_apci7800_setup(struct serial_private *priv,
112 const struct pciserial_board *board,
113 struct uart_port *port, int idx)
114{
115 unsigned int bar = 0, offset = board->first_offset;
116 bar = FL_GET_BASE(board->flags);
117
118 if (idx < 2) {
119 offset += idx * board->uart_offset;
120 } else if ((idx >= 2) && (idx < 4)) {
121 bar += 1;
122 offset += ((idx - 2) * board->uart_offset);
123 } else if ((idx >= 4) && (idx < 6)) {
124 bar += 2;
125 offset += ((idx - 4) * board->uart_offset);
126 } else if (idx >= 6) {
127 bar += 3;
128 offset += ((idx - 6) * board->uart_offset);
129 }
130
131 return setup_port(priv, port, bar, offset, board->reg_shift);
132}
133
134/*
135 * AFAVLAB uses a different mixture of BARs and offsets
136 * Not that ugly ;) -- HW
137 */
138static int
139afavlab_setup(struct serial_private *priv, const struct pciserial_board *board,
140 struct uart_port *port, int idx)
141{
142 unsigned int bar, offset = board->first_offset;
143
144 bar = FL_GET_BASE(board->flags);
145 if (idx < 4)
146 bar += idx;
147 else {
148 bar = 4;
149 offset += (idx - 4) * board->uart_offset;
150 }
151
152 return setup_port(priv, port, bar, offset, board->reg_shift);
153}
154
155/*
156 * HP's Remote Management Console. The Diva chip came in several
157 * different versions. N-class, L2000 and A500 have two Diva chips, each
158 * with 3 UARTs (the third UART on the second chip is unused). Superdome
159 * and Keystone have one Diva chip with 3 UARTs. Some later machines have
160 * one Diva chip, but it has been expanded to 5 UARTs.
161 */
162static int pci_hp_diva_init(struct pci_dev *dev)
163{
164 int rc = 0;
165
166 switch (dev->subsystem_device) {
167 case PCI_DEVICE_ID_HP_DIVA_TOSCA1:
168 case PCI_DEVICE_ID_HP_DIVA_HALFDOME:
169 case PCI_DEVICE_ID_HP_DIVA_KEYSTONE:
170 case PCI_DEVICE_ID_HP_DIVA_EVEREST:
171 rc = 3;
172 break;
173 case PCI_DEVICE_ID_HP_DIVA_TOSCA2:
174 rc = 2;
175 break;
176 case PCI_DEVICE_ID_HP_DIVA_MAESTRO:
177 rc = 4;
178 break;
179 case PCI_DEVICE_ID_HP_DIVA_POWERBAR:
180 case PCI_DEVICE_ID_HP_DIVA_HURRICANE:
181 rc = 1;
182 break;
183 }
184
185 return rc;
186}
187
188/*
189 * HP's Diva chip puts the 4th/5th serial port further out, and
190 * some serial ports are supposed to be hidden on certain models.
191 */
192static int
193pci_hp_diva_setup(struct serial_private *priv,
194 const struct pciserial_board *board,
195 struct uart_port *port, int idx)
196{
197 unsigned int offset = board->first_offset;
198 unsigned int bar = FL_GET_BASE(board->flags);
199
200 switch (priv->dev->subsystem_device) {
201 case PCI_DEVICE_ID_HP_DIVA_MAESTRO:
202 if (idx == 3)
203 idx++;
204 break;
205 case PCI_DEVICE_ID_HP_DIVA_EVEREST:
206 if (idx > 0)
207 idx++;
208 if (idx > 2)
209 idx++;
210 break;
211 }
212 if (idx > 2)
213 offset = 0x18;
214
215 offset += idx * board->uart_offset;
216
217 return setup_port(priv, port, bar, offset, board->reg_shift);
218}
219
220/*
221 * Added for EKF Intel i960 serial boards
222 */
223static int pci_inteli960ni_init(struct pci_dev *dev)
224{
225 unsigned long oldval;
226
227 if (!(dev->subsystem_device & 0x1000))
228 return -ENODEV;
229
230 /* is firmware started? */
231 pci_read_config_dword(dev, 0x44, (void *)&oldval);
232 if (oldval == 0x00001000L) { /* RESET value */
233 printk(KERN_DEBUG "Local i960 firmware missing");
234 return -ENODEV;
235 }
236 return 0;
237}
238
239/*
240 * Some PCI serial cards using the PLX 9050 PCI interface chip require
241 * that the card interrupt be explicitly enabled or disabled. This
242 * seems to be mainly needed on card using the PLX which also use I/O
243 * mapped memory.
244 */
245static int pci_plx9050_init(struct pci_dev *dev)
246{
247 u8 irq_config;
248 void __iomem *p;
249
250 if ((pci_resource_flags(dev, 0) & IORESOURCE_MEM) == 0) {
251 moan_device("no memory in bar 0", dev);
252 return 0;
253 }
254
255 irq_config = 0x41;
256 if (dev->vendor == PCI_VENDOR_ID_PANACOM ||
257 dev->subsystem_vendor == PCI_SUBVENDOR_ID_EXSYS)
258 irq_config = 0x43;
259
260 if ((dev->vendor == PCI_VENDOR_ID_PLX) &&
261 (dev->device == PCI_DEVICE_ID_PLX_ROMULUS))
262 /*
263 * As the megawolf cards have the int pins active
264 * high, and have 2 UART chips, both ints must be
265 * enabled on the 9050. Also, the UARTS are set in
266 * 16450 mode by default, so we have to enable the
267 * 16C950 'enhanced' mode so that we can use the
268 * deep FIFOs
269 */
270 irq_config = 0x5b;
271 /*
272 * enable/disable interrupts
273 */
274 p = ioremap_nocache(pci_resource_start(dev, 0), 0x80);
275 if (p == NULL)
276 return -ENOMEM;
277 writel(irq_config, p + 0x4c);
278
279 /*
280 * Read the register back to ensure that it took effect.
281 */
282 readl(p + 0x4c);
283 iounmap(p);
284
285 return 0;
286}
287
288static void __devexit pci_plx9050_exit(struct pci_dev *dev)
289{
290 u8 __iomem *p;
291
292 if ((pci_resource_flags(dev, 0) & IORESOURCE_MEM) == 0)
293 return;
294
295 /*
296 * disable interrupts
297 */
298 p = ioremap_nocache(pci_resource_start(dev, 0), 0x80);
299 if (p != NULL) {
300 writel(0, p + 0x4c);
301
302 /*
303 * Read the register back to ensure that it took effect.
304 */
305 readl(p + 0x4c);
306 iounmap(p);
307 }
308}
309
310#define NI8420_INT_ENABLE_REG 0x38
311#define NI8420_INT_ENABLE_BIT 0x2000
312
313static void __devexit pci_ni8420_exit(struct pci_dev *dev)
314{
315 void __iomem *p;
316 unsigned long base, len;
317 unsigned int bar = 0;
318
319 if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) {
320 moan_device("no memory in bar", dev);
321 return;
322 }
323
324 base = pci_resource_start(dev, bar);
325 len = pci_resource_len(dev, bar);
326 p = ioremap_nocache(base, len);
327 if (p == NULL)
328 return;
329
330 /* Disable the CPU Interrupt */
331 writel(readl(p + NI8420_INT_ENABLE_REG) & ~(NI8420_INT_ENABLE_BIT),
332 p + NI8420_INT_ENABLE_REG);
333 iounmap(p);
334}
335
336
337/* MITE registers */
338#define MITE_IOWBSR1 0xc4
339#define MITE_IOWCR1 0xf4
340#define MITE_LCIMR1 0x08
341#define MITE_LCIMR2 0x10
342
343#define MITE_LCIMR2_CLR_CPU_IE (1 << 30)
344
345static void __devexit pci_ni8430_exit(struct pci_dev *dev)
346{
347 void __iomem *p;
348 unsigned long base, len;
349 unsigned int bar = 0;
350
351 if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) {
352 moan_device("no memory in bar", dev);
353 return;
354 }
355
356 base = pci_resource_start(dev, bar);
357 len = pci_resource_len(dev, bar);
358 p = ioremap_nocache(base, len);
359 if (p == NULL)
360 return;
361
362 /* Disable the CPU Interrupt */
363 writel(MITE_LCIMR2_CLR_CPU_IE, p + MITE_LCIMR2);
364 iounmap(p);
365}
366
367/* SBS Technologies Inc. PMC-OCTPRO and P-OCTAL cards */
368static int
369sbs_setup(struct serial_private *priv, const struct pciserial_board *board,
370 struct uart_port *port, int idx)
371{
372 unsigned int bar, offset = board->first_offset;
373
374 bar = 0;
375
376 if (idx < 4) {
377 /* first four channels map to 0, 0x100, 0x200, 0x300 */
378 offset += idx * board->uart_offset;
379 } else if (idx < 8) {
380 /* last four channels map to 0x1000, 0x1100, 0x1200, 0x1300 */
381 offset += idx * board->uart_offset + 0xC00;
382 } else /* we have only 8 ports on PMC-OCTALPRO */
383 return 1;
384
385 return setup_port(priv, port, bar, offset, board->reg_shift);
386}
387
388/*
389* This does initialization for PMC OCTALPRO cards:
390* maps the device memory, resets the UARTs (needed, bc
391* if the module is removed and inserted again, the card
392* is in the sleep mode) and enables global interrupt.
393*/
394
395/* global control register offset for SBS PMC-OctalPro */
396#define OCT_REG_CR_OFF 0x500
397
398static int sbs_init(struct pci_dev *dev)
399{
400 u8 __iomem *p;
401
402 p = pci_ioremap_bar(dev, 0);
403
404 if (p == NULL)
405 return -ENOMEM;
406 /* Set bit-4 Control Register (UART RESET) in to reset the uarts */
407 writeb(0x10, p + OCT_REG_CR_OFF);
408 udelay(50);
409 writeb(0x0, p + OCT_REG_CR_OFF);
410
411 /* Set bit-2 (INTENABLE) of Control Register */
412 writeb(0x4, p + OCT_REG_CR_OFF);
413 iounmap(p);
414
415 return 0;
416}
417
418/*
419 * Disables the global interrupt of PMC-OctalPro
420 */
421
422static void __devexit sbs_exit(struct pci_dev *dev)
423{
424 u8 __iomem *p;
425
426 p = pci_ioremap_bar(dev, 0);
427 /* FIXME: What if resource_len < OCT_REG_CR_OFF */
428 if (p != NULL)
429 writeb(0, p + OCT_REG_CR_OFF);
430 iounmap(p);
431}
432
433/*
434 * SIIG serial cards have an PCI interface chip which also controls
435 * the UART clocking frequency. Each UART can be clocked independently
436 * (except cards equiped with 4 UARTs) and initial clocking settings
437 * are stored in the EEPROM chip. It can cause problems because this
438 * version of serial driver doesn't support differently clocked UART's
439 * on single PCI card. To prevent this, initialization functions set
440 * high frequency clocking for all UART's on given card. It is safe (I
441 * hope) because it doesn't touch EEPROM settings to prevent conflicts
442 * with other OSes (like M$ DOS).
443 *
444 * SIIG support added by Andrey Panin <pazke@donpac.ru>, 10/1999
445 *
446 * There is two family of SIIG serial cards with different PCI
447 * interface chip and different configuration methods:
448 * - 10x cards have control registers in IO and/or memory space;
449 * - 20x cards have control registers in standard PCI configuration space.
450 *
451 * Note: all 10x cards have PCI device ids 0x10..
452 * all 20x cards have PCI device ids 0x20..
453 *
454 * There are also Quartet Serial cards which use Oxford Semiconductor
455 * 16954 quad UART PCI chip clocked by 18.432 MHz quartz.
456 *
457 * Note: some SIIG cards are probed by the parport_serial object.
458 */
459
460#define PCI_DEVICE_ID_SIIG_1S_10x (PCI_DEVICE_ID_SIIG_1S_10x_550 & 0xfffc)
461#define PCI_DEVICE_ID_SIIG_2S_10x (PCI_DEVICE_ID_SIIG_2S_10x_550 & 0xfff8)
462
463static int pci_siig10x_init(struct pci_dev *dev)
464{
465 u16 data;
466 void __iomem *p;
467
468 switch (dev->device & 0xfff8) {
469 case PCI_DEVICE_ID_SIIG_1S_10x: /* 1S */
470 data = 0xffdf;
471 break;
472 case PCI_DEVICE_ID_SIIG_2S_10x: /* 2S, 2S1P */
473 data = 0xf7ff;
474 break;
475 default: /* 1S1P, 4S */
476 data = 0xfffb;
477 break;
478 }
479
480 p = ioremap_nocache(pci_resource_start(dev, 0), 0x80);
481 if (p == NULL)
482 return -ENOMEM;
483
484 writew(readw(p + 0x28) & data, p + 0x28);
485 readw(p + 0x28);
486 iounmap(p);
487 return 0;
488}
489
490#define PCI_DEVICE_ID_SIIG_2S_20x (PCI_DEVICE_ID_SIIG_2S_20x_550 & 0xfffc)
491#define PCI_DEVICE_ID_SIIG_2S1P_20x (PCI_DEVICE_ID_SIIG_2S1P_20x_550 & 0xfffc)
492
493static int pci_siig20x_init(struct pci_dev *dev)
494{
495 u8 data;
496
497 /* Change clock frequency for the first UART. */
498 pci_read_config_byte(dev, 0x6f, &data);
499 pci_write_config_byte(dev, 0x6f, data & 0xef);
500
501 /* If this card has 2 UART, we have to do the same with second UART. */
502 if (((dev->device & 0xfffc) == PCI_DEVICE_ID_SIIG_2S_20x) ||
503 ((dev->device & 0xfffc) == PCI_DEVICE_ID_SIIG_2S1P_20x)) {
504 pci_read_config_byte(dev, 0x73, &data);
505 pci_write_config_byte(dev, 0x73, data & 0xef);
506 }
507 return 0;
508}
509
510static int pci_siig_init(struct pci_dev *dev)
511{
512 unsigned int type = dev->device & 0xff00;
513
514 if (type == 0x1000)
515 return pci_siig10x_init(dev);
516 else if (type == 0x2000)
517 return pci_siig20x_init(dev);
518
519 moan_device("Unknown SIIG card", dev);
520 return -ENODEV;
521}
522
523static int pci_siig_setup(struct serial_private *priv,
524 const struct pciserial_board *board,
525 struct uart_port *port, int idx)
526{
527 unsigned int bar = FL_GET_BASE(board->flags) + idx, offset = 0;
528
529 if (idx > 3) {
530 bar = 4;
531 offset = (idx - 4) * 8;
532 }
533
534 return setup_port(priv, port, bar, offset, 0);
535}
536
537/*
538 * Timedia has an explosion of boards, and to avoid the PCI table from
539 * growing *huge*, we use this function to collapse some 70 entries
540 * in the PCI table into one, for sanity's and compactness's sake.
541 */
542static const unsigned short timedia_single_port[] = {
543 0x4025, 0x4027, 0x4028, 0x5025, 0x5027, 0
544};
545
546static const unsigned short timedia_dual_port[] = {
547 0x0002, 0x4036, 0x4037, 0x4038, 0x4078, 0x4079, 0x4085,
548 0x4088, 0x4089, 0x5037, 0x5078, 0x5079, 0x5085, 0x6079,
549 0x7079, 0x8079, 0x8137, 0x8138, 0x8237, 0x8238, 0x9079,
550 0x9137, 0x9138, 0x9237, 0x9238, 0xA079, 0xB079, 0xC079,
551 0xD079, 0
552};
553
554static const unsigned short timedia_quad_port[] = {
555 0x4055, 0x4056, 0x4095, 0x4096, 0x5056, 0x8156, 0x8157,
556 0x8256, 0x8257, 0x9056, 0x9156, 0x9157, 0x9158, 0x9159,
557 0x9256, 0x9257, 0xA056, 0xA157, 0xA158, 0xA159, 0xB056,
558 0xB157, 0
559};
560
561static const unsigned short timedia_eight_port[] = {
562 0x4065, 0x4066, 0x5065, 0x5066, 0x8166, 0x9066, 0x9166,
563 0x9167, 0x9168, 0xA066, 0xA167, 0xA168, 0
564};
565
566static const struct timedia_struct {
567 int num;
568 const unsigned short *ids;
569} timedia_data[] = {
570 { 1, timedia_single_port },
571 { 2, timedia_dual_port },
572 { 4, timedia_quad_port },
573 { 8, timedia_eight_port }
574};
575
576static int pci_timedia_init(struct pci_dev *dev)
577{
578 const unsigned short *ids;
579 int i, j;
580
581 for (i = 0; i < ARRAY_SIZE(timedia_data); i++) {
582 ids = timedia_data[i].ids;
583 for (j = 0; ids[j]; j++)
584 if (dev->subsystem_device == ids[j])
585 return timedia_data[i].num;
586 }
587 return 0;
588}
589
590/*
591 * Timedia/SUNIX uses a mixture of BARs and offsets
592 * Ugh, this is ugly as all hell --- TYT
593 */
594static int
595pci_timedia_setup(struct serial_private *priv,
596 const struct pciserial_board *board,
597 struct uart_port *port, int idx)
598{
599 unsigned int bar = 0, offset = board->first_offset;
600
601 switch (idx) {
602 case 0:
603 bar = 0;
604 break;
605 case 1:
606 offset = board->uart_offset;
607 bar = 0;
608 break;
609 case 2:
610 bar = 1;
611 break;
612 case 3:
613 offset = board->uart_offset;
614 /* FALLTHROUGH */
615 case 4: /* BAR 2 */
616 case 5: /* BAR 3 */
617 case 6: /* BAR 4 */
618 case 7: /* BAR 5 */
619 bar = idx - 2;
620 }
621
622 return setup_port(priv, port, bar, offset, board->reg_shift);
623}
624
625/*
626 * Some Titan cards are also a little weird
627 */
628static int
629titan_400l_800l_setup(struct serial_private *priv,
630 const struct pciserial_board *board,
631 struct uart_port *port, int idx)
632{
633 unsigned int bar, offset = board->first_offset;
634
635 switch (idx) {
636 case 0:
637 bar = 1;
638 break;
639 case 1:
640 bar = 2;
641 break;
642 default:
643 bar = 4;
644 offset = (idx - 2) * board->uart_offset;
645 }
646
647 return setup_port(priv, port, bar, offset, board->reg_shift);
648}
649
650static int pci_xircom_init(struct pci_dev *dev)
651{
652 msleep(100);
653 return 0;
654}
655
656static int pci_ni8420_init(struct pci_dev *dev)
657{
658 void __iomem *p;
659 unsigned long base, len;
660 unsigned int bar = 0;
661
662 if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) {
663 moan_device("no memory in bar", dev);
664 return 0;
665 }
666
667 base = pci_resource_start(dev, bar);
668 len = pci_resource_len(dev, bar);
669 p = ioremap_nocache(base, len);
670 if (p == NULL)
671 return -ENOMEM;
672
673 /* Enable CPU Interrupt */
674 writel(readl(p + NI8420_INT_ENABLE_REG) | NI8420_INT_ENABLE_BIT,
675 p + NI8420_INT_ENABLE_REG);
676
677 iounmap(p);
678 return 0;
679}
680
681#define MITE_IOWBSR1_WSIZE 0xa
682#define MITE_IOWBSR1_WIN_OFFSET 0x800
683#define MITE_IOWBSR1_WENAB (1 << 7)
684#define MITE_LCIMR1_IO_IE_0 (1 << 24)
685#define MITE_LCIMR2_SET_CPU_IE (1 << 31)
686#define MITE_IOWCR1_RAMSEL_MASK 0xfffffffe
687
688static int pci_ni8430_init(struct pci_dev *dev)
689{
690 void __iomem *p;
691 unsigned long base, len;
692 u32 device_window;
693 unsigned int bar = 0;
694
695 if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) {
696 moan_device("no memory in bar", dev);
697 return 0;
698 }
699
700 base = pci_resource_start(dev, bar);
701 len = pci_resource_len(dev, bar);
702 p = ioremap_nocache(base, len);
703 if (p == NULL)
704 return -ENOMEM;
705
706 /* Set device window address and size in BAR0 */
707 device_window = ((base + MITE_IOWBSR1_WIN_OFFSET) & 0xffffff00)
708 | MITE_IOWBSR1_WENAB | MITE_IOWBSR1_WSIZE;
709 writel(device_window, p + MITE_IOWBSR1);
710
711 /* Set window access to go to RAMSEL IO address space */
712 writel((readl(p + MITE_IOWCR1) & MITE_IOWCR1_RAMSEL_MASK),
713 p + MITE_IOWCR1);
714
715 /* Enable IO Bus Interrupt 0 */
716 writel(MITE_LCIMR1_IO_IE_0, p + MITE_LCIMR1);
717
718 /* Enable CPU Interrupt */
719 writel(MITE_LCIMR2_SET_CPU_IE, p + MITE_LCIMR2);
720
721 iounmap(p);
722 return 0;
723}
724
725/* UART Port Control Register */
726#define NI8430_PORTCON 0x0f
727#define NI8430_PORTCON_TXVR_ENABLE (1 << 3)
728
729static int
730pci_ni8430_setup(struct serial_private *priv,
731 const struct pciserial_board *board,
732 struct uart_port *port, int idx)
733{
734 void __iomem *p;
735 unsigned long base, len;
736 unsigned int bar, offset = board->first_offset;
737
738 if (idx >= board->num_ports)
739 return 1;
740
741 bar = FL_GET_BASE(board->flags);
742 offset += idx * board->uart_offset;
743
744 base = pci_resource_start(priv->dev, bar);
745 len = pci_resource_len(priv->dev, bar);
746 p = ioremap_nocache(base, len);
747
748 /* enable the transciever */
749 writeb(readb(p + offset + NI8430_PORTCON) | NI8430_PORTCON_TXVR_ENABLE,
750 p + offset + NI8430_PORTCON);
751
752 iounmap(p);
753
754 return setup_port(priv, port, bar, offset, board->reg_shift);
755}
756
757
758static int pci_netmos_init(struct pci_dev *dev)
759{
760 /* subdevice 0x00PS means <P> parallel, <S> serial */
761 unsigned int num_serial = dev->subsystem_device & 0xf;
762
763 if ((dev->device == PCI_DEVICE_ID_NETMOS_9901) ||
764 (dev->device == PCI_DEVICE_ID_NETMOS_9865))
765 return 0;
766 if (dev->subsystem_vendor == PCI_VENDOR_ID_IBM &&
767 dev->subsystem_device == 0x0299)
768 return 0;
769
770 if (num_serial == 0)
771 return -ENODEV;
772 return num_serial;
773}
774
775/*
776 * These chips are available with optionally one parallel port and up to
777 * two serial ports. Unfortunately they all have the same product id.
778 *
779 * Basic configuration is done over a region of 32 I/O ports. The base
780 * ioport is called INTA or INTC, depending on docs/other drivers.
781 *
782 * The region of the 32 I/O ports is configured in POSIO0R...
783 */
784
785/* registers */
786#define ITE_887x_MISCR 0x9c
787#define ITE_887x_INTCBAR 0x78
788#define ITE_887x_UARTBAR 0x7c
789#define ITE_887x_PS0BAR 0x10
790#define ITE_887x_POSIO0 0x60
791
792/* I/O space size */
793#define ITE_887x_IOSIZE 32
794/* I/O space size (bits 26-24; 8 bytes = 011b) */
795#define ITE_887x_POSIO_IOSIZE_8 (3 << 24)
796/* I/O space size (bits 26-24; 32 bytes = 101b) */
797#define ITE_887x_POSIO_IOSIZE_32 (5 << 24)
798/* Decoding speed (1 = slow, 2 = medium, 3 = fast) */
799#define ITE_887x_POSIO_SPEED (3 << 29)
800/* enable IO_Space bit */
801#define ITE_887x_POSIO_ENABLE (1 << 31)
802
803static int pci_ite887x_init(struct pci_dev *dev)
804{
805 /* inta_addr are the configuration addresses of the ITE */
806 static const short inta_addr[] = { 0x2a0, 0x2c0, 0x220, 0x240, 0x1e0,
807 0x200, 0x280, 0 };
808 int ret, i, type;
809 struct resource *iobase = NULL;
810 u32 miscr, uartbar, ioport;
811
812 /* search for the base-ioport */
813 i = 0;
814 while (inta_addr[i] && iobase == NULL) {
815 iobase = request_region(inta_addr[i], ITE_887x_IOSIZE,
816 "ite887x");
817 if (iobase != NULL) {
818 /* write POSIO0R - speed | size | ioport */
819 pci_write_config_dword(dev, ITE_887x_POSIO0,
820 ITE_887x_POSIO_ENABLE | ITE_887x_POSIO_SPEED |
821 ITE_887x_POSIO_IOSIZE_32 | inta_addr[i]);
822 /* write INTCBAR - ioport */
823 pci_write_config_dword(dev, ITE_887x_INTCBAR,
824 inta_addr[i]);
825 ret = inb(inta_addr[i]);
826 if (ret != 0xff) {
827 /* ioport connected */
828 break;
829 }
830 release_region(iobase->start, ITE_887x_IOSIZE);
831 iobase = NULL;
832 }
833 i++;
834 }
835
836 if (!inta_addr[i]) {
837 printk(KERN_ERR "ite887x: could not find iobase\n");
838 return -ENODEV;
839 }
840
841 /* start of undocumented type checking (see parport_pc.c) */
842 type = inb(iobase->start + 0x18) & 0x0f;
843
844 switch (type) {
845 case 0x2: /* ITE8871 (1P) */
846 case 0xa: /* ITE8875 (1P) */
847 ret = 0;
848 break;
849 case 0xe: /* ITE8872 (2S1P) */
850 ret = 2;
851 break;
852 case 0x6: /* ITE8873 (1S) */
853 ret = 1;
854 break;
855 case 0x8: /* ITE8874 (2S) */
856 ret = 2;
857 break;
858 default:
859 moan_device("Unknown ITE887x", dev);
860 ret = -ENODEV;
861 }
862
863 /* configure all serial ports */
864 for (i = 0; i < ret; i++) {
865 /* read the I/O port from the device */
866 pci_read_config_dword(dev, ITE_887x_PS0BAR + (0x4 * (i + 1)),
867 &ioport);
868 ioport &= 0x0000FF00; /* the actual base address */
869 pci_write_config_dword(dev, ITE_887x_POSIO0 + (0x4 * (i + 1)),
870 ITE_887x_POSIO_ENABLE | ITE_887x_POSIO_SPEED |
871 ITE_887x_POSIO_IOSIZE_8 | ioport);
872
873 /* write the ioport to the UARTBAR */
874 pci_read_config_dword(dev, ITE_887x_UARTBAR, &uartbar);
875 uartbar &= ~(0xffff << (16 * i)); /* clear half the reg */
876 uartbar |= (ioport << (16 * i)); /* set the ioport */
877 pci_write_config_dword(dev, ITE_887x_UARTBAR, uartbar);
878
879 /* get current config */
880 pci_read_config_dword(dev, ITE_887x_MISCR, &miscr);
881 /* disable interrupts (UARTx_Routing[3:0]) */
882 miscr &= ~(0xf << (12 - 4 * i));
883 /* activate the UART (UARTx_En) */
884 miscr |= 1 << (23 - i);
885 /* write new config with activated UART */
886 pci_write_config_dword(dev, ITE_887x_MISCR, miscr);
887 }
888
889 if (ret <= 0) {
890 /* the device has no UARTs if we get here */
891 release_region(iobase->start, ITE_887x_IOSIZE);
892 }
893
894 return ret;
895}
896
897static void __devexit pci_ite887x_exit(struct pci_dev *dev)
898{
899 u32 ioport;
900 /* the ioport is bit 0-15 in POSIO0R */
901 pci_read_config_dword(dev, ITE_887x_POSIO0, &ioport);
902 ioport &= 0xffff;
903 release_region(ioport, ITE_887x_IOSIZE);
904}
905
906/*
907 * Oxford Semiconductor Inc.
908 * Check that device is part of the Tornado range of devices, then determine
909 * the number of ports available on the device.
910 */
911static int pci_oxsemi_tornado_init(struct pci_dev *dev)
912{
913 u8 __iomem *p;
914 unsigned long deviceID;
915 unsigned int number_uarts = 0;
916
917 /* OxSemi Tornado devices are all 0xCxxx */
918 if (dev->vendor == PCI_VENDOR_ID_OXSEMI &&
919 (dev->device & 0xF000) != 0xC000)
920 return 0;
921
922 p = pci_iomap(dev, 0, 5);
923 if (p == NULL)
924 return -ENOMEM;
925
926 deviceID = ioread32(p);
927 /* Tornado device */
928 if (deviceID == 0x07000200) {
929 number_uarts = ioread8(p + 4);
930 printk(KERN_DEBUG
931 "%d ports detected on Oxford PCI Express device\n",
932 number_uarts);
933 }
934 pci_iounmap(dev, p);
935 return number_uarts;
936}
937
938static int
939pci_default_setup(struct serial_private *priv,
940 const struct pciserial_board *board,
941 struct uart_port *port, int idx)
942{
943 unsigned int bar, offset = board->first_offset, maxnr;
944
945 bar = FL_GET_BASE(board->flags);
946 if (board->flags & FL_BASE_BARS)
947 bar += idx;
948 else
949 offset += idx * board->uart_offset;
950
951 maxnr = (pci_resource_len(priv->dev, bar) - board->first_offset) >>
952 (board->reg_shift + 3);
953
954 if (board->flags & FL_REGION_SZ_CAP && idx >= maxnr)
955 return 1;
956
957 return setup_port(priv, port, bar, offset, board->reg_shift);
958}
959
960static int
961ce4100_serial_setup(struct serial_private *priv,
962 const struct pciserial_board *board,
963 struct uart_port *port, int idx)
964{
965 int ret;
966
967 ret = setup_port(priv, port, 0, 0, board->reg_shift);
968 port->iotype = UPIO_MEM32;
969 port->type = PORT_XSCALE;
970 port->flags = (port->flags | UPF_FIXED_PORT | UPF_FIXED_TYPE);
971 port->regshift = 2;
972
973 return ret;
974}
975
976static int skip_tx_en_setup(struct serial_private *priv,
977 const struct pciserial_board *board,
978 struct uart_port *port, int idx)
979{
980 port->flags |= UPF_NO_TXEN_TEST;
981 printk(KERN_DEBUG "serial8250: skipping TxEn test for device "
982 "[%04x:%04x] subsystem [%04x:%04x]\n",
983 priv->dev->vendor,
984 priv->dev->device,
985 priv->dev->subsystem_vendor,
986 priv->dev->subsystem_device);
987
988 return pci_default_setup(priv, board, port, idx);
989}
990
991/* This should be in linux/pci_ids.h */
992#define PCI_VENDOR_ID_SBSMODULARIO 0x124B
993#define PCI_SUBVENDOR_ID_SBSMODULARIO 0x124B
994#define PCI_DEVICE_ID_OCTPRO 0x0001
995#define PCI_SUBDEVICE_ID_OCTPRO232 0x0108
996#define PCI_SUBDEVICE_ID_OCTPRO422 0x0208
997#define PCI_SUBDEVICE_ID_POCTAL232 0x0308
998#define PCI_SUBDEVICE_ID_POCTAL422 0x0408
999#define PCI_VENDOR_ID_ADVANTECH 0x13fe
1000#define PCI_DEVICE_ID_INTEL_CE4100_UART 0x2e66
1001#define PCI_DEVICE_ID_ADVANTECH_PCI3620 0x3620
1002#define PCI_DEVICE_ID_TITAN_200I 0x8028
1003#define PCI_DEVICE_ID_TITAN_400I 0x8048
1004#define PCI_DEVICE_ID_TITAN_800I 0x8088
1005#define PCI_DEVICE_ID_TITAN_800EH 0xA007
1006#define PCI_DEVICE_ID_TITAN_800EHB 0xA008
1007#define PCI_DEVICE_ID_TITAN_400EH 0xA009
1008#define PCI_DEVICE_ID_TITAN_100E 0xA010
1009#define PCI_DEVICE_ID_TITAN_200E 0xA012
1010#define PCI_DEVICE_ID_TITAN_400E 0xA013
1011#define PCI_DEVICE_ID_TITAN_800E 0xA014
1012#define PCI_DEVICE_ID_TITAN_200EI 0xA016
1013#define PCI_DEVICE_ID_TITAN_200EISI 0xA017
1014#define PCI_DEVICE_ID_OXSEMI_16PCI958 0x9538
1015
1016/* Unknown vendors/cards - this should not be in linux/pci_ids.h */
1017#define PCI_SUBDEVICE_ID_UNKNOWN_0x1584 0x1584
1018
1019/*
1020 * Master list of serial port init/setup/exit quirks.
1021 * This does not describe the general nature of the port.
1022 * (ie, baud base, number and location of ports, etc)
1023 *
1024 * This list is ordered alphabetically by vendor then device.
1025 * Specific entries must come before more generic entries.
1026 */
1027static struct pci_serial_quirk pci_serial_quirks[] __refdata = {
1028 /*
1029 * ADDI-DATA GmbH communication cards <info@addi-data.com>
1030 */
1031 {
1032 .vendor = PCI_VENDOR_ID_ADDIDATA_OLD,
1033 .device = PCI_DEVICE_ID_ADDIDATA_APCI7800,
1034 .subvendor = PCI_ANY_ID,
1035 .subdevice = PCI_ANY_ID,
1036 .setup = addidata_apci7800_setup,
1037 },
1038 /*
1039 * AFAVLAB cards - these may be called via parport_serial
1040 * It is not clear whether this applies to all products.
1041 */
1042 {
1043 .vendor = PCI_VENDOR_ID_AFAVLAB,
1044 .device = PCI_ANY_ID,
1045 .subvendor = PCI_ANY_ID,
1046 .subdevice = PCI_ANY_ID,
1047 .setup = afavlab_setup,
1048 },
1049 /*
1050 * HP Diva
1051 */
1052 {
1053 .vendor = PCI_VENDOR_ID_HP,
1054 .device = PCI_DEVICE_ID_HP_DIVA,
1055 .subvendor = PCI_ANY_ID,
1056 .subdevice = PCI_ANY_ID,
1057 .init = pci_hp_diva_init,
1058 .setup = pci_hp_diva_setup,
1059 },
1060 /*
1061 * Intel
1062 */
1063 {
1064 .vendor = PCI_VENDOR_ID_INTEL,
1065 .device = PCI_DEVICE_ID_INTEL_80960_RP,
1066 .subvendor = 0xe4bf,
1067 .subdevice = PCI_ANY_ID,
1068 .init = pci_inteli960ni_init,
1069 .setup = pci_default_setup,
1070 },
1071 {
1072 .vendor = PCI_VENDOR_ID_INTEL,
1073 .device = PCI_DEVICE_ID_INTEL_8257X_SOL,
1074 .subvendor = PCI_ANY_ID,
1075 .subdevice = PCI_ANY_ID,
1076 .setup = skip_tx_en_setup,
1077 },
1078 {
1079 .vendor = PCI_VENDOR_ID_INTEL,
1080 .device = PCI_DEVICE_ID_INTEL_82573L_SOL,
1081 .subvendor = PCI_ANY_ID,
1082 .subdevice = PCI_ANY_ID,
1083 .setup = skip_tx_en_setup,
1084 },
1085 {
1086 .vendor = PCI_VENDOR_ID_INTEL,
1087 .device = PCI_DEVICE_ID_INTEL_82573E_SOL,
1088 .subvendor = PCI_ANY_ID,
1089 .subdevice = PCI_ANY_ID,
1090 .setup = skip_tx_en_setup,
1091 },
1092 {
1093 .vendor = PCI_VENDOR_ID_INTEL,
1094 .device = PCI_DEVICE_ID_INTEL_CE4100_UART,
1095 .subvendor = PCI_ANY_ID,
1096 .subdevice = PCI_ANY_ID,
1097 .setup = ce4100_serial_setup,
1098 },
1099 /*
1100 * ITE
1101 */
1102 {
1103 .vendor = PCI_VENDOR_ID_ITE,
1104 .device = PCI_DEVICE_ID_ITE_8872,
1105 .subvendor = PCI_ANY_ID,
1106 .subdevice = PCI_ANY_ID,
1107 .init = pci_ite887x_init,
1108 .setup = pci_default_setup,
1109 .exit = __devexit_p(pci_ite887x_exit),
1110 },
1111 /*
1112 * National Instruments
1113 */
1114 {
1115 .vendor = PCI_VENDOR_ID_NI,
1116 .device = PCI_DEVICE_ID_NI_PCI23216,
1117 .subvendor = PCI_ANY_ID,
1118 .subdevice = PCI_ANY_ID,
1119 .init = pci_ni8420_init,
1120 .setup = pci_default_setup,
1121 .exit = __devexit_p(pci_ni8420_exit),
1122 },
1123 {
1124 .vendor = PCI_VENDOR_ID_NI,
1125 .device = PCI_DEVICE_ID_NI_PCI2328,
1126 .subvendor = PCI_ANY_ID,
1127 .subdevice = PCI_ANY_ID,
1128 .init = pci_ni8420_init,
1129 .setup = pci_default_setup,
1130 .exit = __devexit_p(pci_ni8420_exit),
1131 },
1132 {
1133 .vendor = PCI_VENDOR_ID_NI,
1134 .device = PCI_DEVICE_ID_NI_PCI2324,
1135 .subvendor = PCI_ANY_ID,
1136 .subdevice = PCI_ANY_ID,
1137 .init = pci_ni8420_init,
1138 .setup = pci_default_setup,
1139 .exit = __devexit_p(pci_ni8420_exit),
1140 },
1141 {
1142 .vendor = PCI_VENDOR_ID_NI,
1143 .device = PCI_DEVICE_ID_NI_PCI2322,
1144 .subvendor = PCI_ANY_ID,
1145 .subdevice = PCI_ANY_ID,
1146 .init = pci_ni8420_init,
1147 .setup = pci_default_setup,
1148 .exit = __devexit_p(pci_ni8420_exit),
1149 },
1150 {
1151 .vendor = PCI_VENDOR_ID_NI,
1152 .device = PCI_DEVICE_ID_NI_PCI2324I,
1153 .subvendor = PCI_ANY_ID,
1154 .subdevice = PCI_ANY_ID,
1155 .init = pci_ni8420_init,
1156 .setup = pci_default_setup,
1157 .exit = __devexit_p(pci_ni8420_exit),
1158 },
1159 {
1160 .vendor = PCI_VENDOR_ID_NI,
1161 .device = PCI_DEVICE_ID_NI_PCI2322I,
1162 .subvendor = PCI_ANY_ID,
1163 .subdevice = PCI_ANY_ID,
1164 .init = pci_ni8420_init,
1165 .setup = pci_default_setup,
1166 .exit = __devexit_p(pci_ni8420_exit),
1167 },
1168 {
1169 .vendor = PCI_VENDOR_ID_NI,
1170 .device = PCI_DEVICE_ID_NI_PXI8420_23216,
1171 .subvendor = PCI_ANY_ID,
1172 .subdevice = PCI_ANY_ID,
1173 .init = pci_ni8420_init,
1174 .setup = pci_default_setup,
1175 .exit = __devexit_p(pci_ni8420_exit),
1176 },
1177 {
1178 .vendor = PCI_VENDOR_ID_NI,
1179 .device = PCI_DEVICE_ID_NI_PXI8420_2328,
1180 .subvendor = PCI_ANY_ID,
1181 .subdevice = PCI_ANY_ID,
1182 .init = pci_ni8420_init,
1183 .setup = pci_default_setup,
1184 .exit = __devexit_p(pci_ni8420_exit),
1185 },
1186 {
1187 .vendor = PCI_VENDOR_ID_NI,
1188 .device = PCI_DEVICE_ID_NI_PXI8420_2324,
1189 .subvendor = PCI_ANY_ID,
1190 .subdevice = PCI_ANY_ID,
1191 .init = pci_ni8420_init,
1192 .setup = pci_default_setup,
1193 .exit = __devexit_p(pci_ni8420_exit),
1194 },
1195 {
1196 .vendor = PCI_VENDOR_ID_NI,
1197 .device = PCI_DEVICE_ID_NI_PXI8420_2322,
1198 .subvendor = PCI_ANY_ID,
1199 .subdevice = PCI_ANY_ID,
1200 .init = pci_ni8420_init,
1201 .setup = pci_default_setup,
1202 .exit = __devexit_p(pci_ni8420_exit),
1203 },
1204 {
1205 .vendor = PCI_VENDOR_ID_NI,
1206 .device = PCI_DEVICE_ID_NI_PXI8422_2324,
1207 .subvendor = PCI_ANY_ID,
1208 .subdevice = PCI_ANY_ID,
1209 .init = pci_ni8420_init,
1210 .setup = pci_default_setup,
1211 .exit = __devexit_p(pci_ni8420_exit),
1212 },
1213 {
1214 .vendor = PCI_VENDOR_ID_NI,
1215 .device = PCI_DEVICE_ID_NI_PXI8422_2322,
1216 .subvendor = PCI_ANY_ID,
1217 .subdevice = PCI_ANY_ID,
1218 .init = pci_ni8420_init,
1219 .setup = pci_default_setup,
1220 .exit = __devexit_p(pci_ni8420_exit),
1221 },
1222 {
1223 .vendor = PCI_VENDOR_ID_NI,
1224 .device = PCI_ANY_ID,
1225 .subvendor = PCI_ANY_ID,
1226 .subdevice = PCI_ANY_ID,
1227 .init = pci_ni8430_init,
1228 .setup = pci_ni8430_setup,
1229 .exit = __devexit_p(pci_ni8430_exit),
1230 },
1231 /*
1232 * Panacom
1233 */
1234 {
1235 .vendor = PCI_VENDOR_ID_PANACOM,
1236 .device = PCI_DEVICE_ID_PANACOM_QUADMODEM,
1237 .subvendor = PCI_ANY_ID,
1238 .subdevice = PCI_ANY_ID,
1239 .init = pci_plx9050_init,
1240 .setup = pci_default_setup,
1241 .exit = __devexit_p(pci_plx9050_exit),
1242 },
1243 {
1244 .vendor = PCI_VENDOR_ID_PANACOM,
1245 .device = PCI_DEVICE_ID_PANACOM_DUALMODEM,
1246 .subvendor = PCI_ANY_ID,
1247 .subdevice = PCI_ANY_ID,
1248 .init = pci_plx9050_init,
1249 .setup = pci_default_setup,
1250 .exit = __devexit_p(pci_plx9050_exit),
1251 },
1252 /*
1253 * PLX
1254 */
1255 {
1256 .vendor = PCI_VENDOR_ID_PLX,
1257 .device = PCI_DEVICE_ID_PLX_9030,
1258 .subvendor = PCI_SUBVENDOR_ID_PERLE,
1259 .subdevice = PCI_ANY_ID,
1260 .setup = pci_default_setup,
1261 },
1262 {
1263 .vendor = PCI_VENDOR_ID_PLX,
1264 .device = PCI_DEVICE_ID_PLX_9050,
1265 .subvendor = PCI_SUBVENDOR_ID_EXSYS,
1266 .subdevice = PCI_SUBDEVICE_ID_EXSYS_4055,
1267 .init = pci_plx9050_init,
1268 .setup = pci_default_setup,
1269 .exit = __devexit_p(pci_plx9050_exit),
1270 },
1271 {
1272 .vendor = PCI_VENDOR_ID_PLX,
1273 .device = PCI_DEVICE_ID_PLX_9050,
1274 .subvendor = PCI_SUBVENDOR_ID_KEYSPAN,
1275 .subdevice = PCI_SUBDEVICE_ID_KEYSPAN_SX2,
1276 .init = pci_plx9050_init,
1277 .setup = pci_default_setup,
1278 .exit = __devexit_p(pci_plx9050_exit),
1279 },
1280 {
1281 .vendor = PCI_VENDOR_ID_PLX,
1282 .device = PCI_DEVICE_ID_PLX_9050,
1283 .subvendor = PCI_VENDOR_ID_PLX,
1284 .subdevice = PCI_SUBDEVICE_ID_UNKNOWN_0x1584,
1285 .init = pci_plx9050_init,
1286 .setup = pci_default_setup,
1287 .exit = __devexit_p(pci_plx9050_exit),
1288 },
1289 {
1290 .vendor = PCI_VENDOR_ID_PLX,
1291 .device = PCI_DEVICE_ID_PLX_ROMULUS,
1292 .subvendor = PCI_VENDOR_ID_PLX,
1293 .subdevice = PCI_DEVICE_ID_PLX_ROMULUS,
1294 .init = pci_plx9050_init,
1295 .setup = pci_default_setup,
1296 .exit = __devexit_p(pci_plx9050_exit),
1297 },
1298 /*
1299 * SBS Technologies, Inc., PMC-OCTALPRO 232
1300 */
1301 {
1302 .vendor = PCI_VENDOR_ID_SBSMODULARIO,
1303 .device = PCI_DEVICE_ID_OCTPRO,
1304 .subvendor = PCI_SUBVENDOR_ID_SBSMODULARIO,
1305 .subdevice = PCI_SUBDEVICE_ID_OCTPRO232,
1306 .init = sbs_init,
1307 .setup = sbs_setup,
1308 .exit = __devexit_p(sbs_exit),
1309 },
1310 /*
1311 * SBS Technologies, Inc., PMC-OCTALPRO 422
1312 */
1313 {
1314 .vendor = PCI_VENDOR_ID_SBSMODULARIO,
1315 .device = PCI_DEVICE_ID_OCTPRO,
1316 .subvendor = PCI_SUBVENDOR_ID_SBSMODULARIO,
1317 .subdevice = PCI_SUBDEVICE_ID_OCTPRO422,
1318 .init = sbs_init,
1319 .setup = sbs_setup,
1320 .exit = __devexit_p(sbs_exit),
1321 },
1322 /*
1323 * SBS Technologies, Inc., P-Octal 232
1324 */
1325 {
1326 .vendor = PCI_VENDOR_ID_SBSMODULARIO,
1327 .device = PCI_DEVICE_ID_OCTPRO,
1328 .subvendor = PCI_SUBVENDOR_ID_SBSMODULARIO,
1329 .subdevice = PCI_SUBDEVICE_ID_POCTAL232,
1330 .init = sbs_init,
1331 .setup = sbs_setup,
1332 .exit = __devexit_p(sbs_exit),
1333 },
1334 /*
1335 * SBS Technologies, Inc., P-Octal 422
1336 */
1337 {
1338 .vendor = PCI_VENDOR_ID_SBSMODULARIO,
1339 .device = PCI_DEVICE_ID_OCTPRO,
1340 .subvendor = PCI_SUBVENDOR_ID_SBSMODULARIO,
1341 .subdevice = PCI_SUBDEVICE_ID_POCTAL422,
1342 .init = sbs_init,
1343 .setup = sbs_setup,
1344 .exit = __devexit_p(sbs_exit),
1345 },
1346 /*
1347 * SIIG cards - these may be called via parport_serial
1348 */
1349 {
1350 .vendor = PCI_VENDOR_ID_SIIG,
1351 .device = PCI_ANY_ID,
1352 .subvendor = PCI_ANY_ID,
1353 .subdevice = PCI_ANY_ID,
1354 .init = pci_siig_init,
1355 .setup = pci_siig_setup,
1356 },
1357 /*
1358 * Titan cards
1359 */
1360 {
1361 .vendor = PCI_VENDOR_ID_TITAN,
1362 .device = PCI_DEVICE_ID_TITAN_400L,
1363 .subvendor = PCI_ANY_ID,
1364 .subdevice = PCI_ANY_ID,
1365 .setup = titan_400l_800l_setup,
1366 },
1367 {
1368 .vendor = PCI_VENDOR_ID_TITAN,
1369 .device = PCI_DEVICE_ID_TITAN_800L,
1370 .subvendor = PCI_ANY_ID,
1371 .subdevice = PCI_ANY_ID,
1372 .setup = titan_400l_800l_setup,
1373 },
1374 /*
1375 * Timedia cards
1376 */
1377 {
1378 .vendor = PCI_VENDOR_ID_TIMEDIA,
1379 .device = PCI_DEVICE_ID_TIMEDIA_1889,
1380 .subvendor = PCI_VENDOR_ID_TIMEDIA,
1381 .subdevice = PCI_ANY_ID,
1382 .init = pci_timedia_init,
1383 .setup = pci_timedia_setup,
1384 },
1385 {
1386 .vendor = PCI_VENDOR_ID_TIMEDIA,
1387 .device = PCI_ANY_ID,
1388 .subvendor = PCI_ANY_ID,
1389 .subdevice = PCI_ANY_ID,
1390 .setup = pci_timedia_setup,
1391 },
1392 /*
1393 * Xircom cards
1394 */
1395 {
1396 .vendor = PCI_VENDOR_ID_XIRCOM,
1397 .device = PCI_DEVICE_ID_XIRCOM_X3201_MDM,
1398 .subvendor = PCI_ANY_ID,
1399 .subdevice = PCI_ANY_ID,
1400 .init = pci_xircom_init,
1401 .setup = pci_default_setup,
1402 },
1403 /*
1404 * Netmos cards - these may be called via parport_serial
1405 */
1406 {
1407 .vendor = PCI_VENDOR_ID_NETMOS,
1408 .device = PCI_ANY_ID,
1409 .subvendor = PCI_ANY_ID,
1410 .subdevice = PCI_ANY_ID,
1411 .init = pci_netmos_init,
1412 .setup = pci_default_setup,
1413 },
1414 /*
1415 * For Oxford Semiconductor and Mainpine
1416 */
1417 {
1418 .vendor = PCI_VENDOR_ID_OXSEMI,
1419 .device = PCI_ANY_ID,
1420 .subvendor = PCI_ANY_ID,
1421 .subdevice = PCI_ANY_ID,
1422 .init = pci_oxsemi_tornado_init,
1423 .setup = pci_default_setup,
1424 },
1425 {
1426 .vendor = PCI_VENDOR_ID_MAINPINE,
1427 .device = PCI_ANY_ID,
1428 .subvendor = PCI_ANY_ID,
1429 .subdevice = PCI_ANY_ID,
1430 .init = pci_oxsemi_tornado_init,
1431 .setup = pci_default_setup,
1432 },
1433 /*
1434 * Default "match everything" terminator entry
1435 */
1436 {
1437 .vendor = PCI_ANY_ID,
1438 .device = PCI_ANY_ID,
1439 .subvendor = PCI_ANY_ID,
1440 .subdevice = PCI_ANY_ID,
1441 .setup = pci_default_setup,
1442 }
1443};
1444
1445static inline int quirk_id_matches(u32 quirk_id, u32 dev_id)
1446{
1447 return quirk_id == PCI_ANY_ID || quirk_id == dev_id;
1448}
1449
1450static struct pci_serial_quirk *find_quirk(struct pci_dev *dev)
1451{
1452 struct pci_serial_quirk *quirk;
1453
1454 for (quirk = pci_serial_quirks; ; quirk++)
1455 if (quirk_id_matches(quirk->vendor, dev->vendor) &&
1456 quirk_id_matches(quirk->device, dev->device) &&
1457 quirk_id_matches(quirk->subvendor, dev->subsystem_vendor) &&
1458 quirk_id_matches(quirk->subdevice, dev->subsystem_device))
1459 break;
1460 return quirk;
1461}
1462
1463static inline int get_pci_irq(struct pci_dev *dev,
1464 const struct pciserial_board *board)
1465{
1466 if (board->flags & FL_NOIRQ)
1467 return 0;
1468 else
1469 return dev->irq;
1470}
1471
1472/*
1473 * This is the configuration table for all of the PCI serial boards
1474 * which we support. It is directly indexed by the pci_board_num_t enum
1475 * value, which is encoded in the pci_device_id PCI probe table's
1476 * driver_data member.
1477 *
1478 * The makeup of these names are:
1479 * pbn_bn{_bt}_n_baud{_offsetinhex}
1480 *
1481 * bn = PCI BAR number
1482 * bt = Index using PCI BARs
1483 * n = number of serial ports
1484 * baud = baud rate
1485 * offsetinhex = offset for each sequential port (in hex)
1486 *
1487 * This table is sorted by (in order): bn, bt, baud, offsetindex, n.
1488 *
1489 * Please note: in theory if n = 1, _bt infix should make no difference.
1490 * ie, pbn_b0_1_115200 is the same as pbn_b0_bt_1_115200
1491 */
1492enum pci_board_num_t {
1493 pbn_default = 0,
1494
1495 pbn_b0_1_115200,
1496 pbn_b0_2_115200,
1497 pbn_b0_4_115200,
1498 pbn_b0_5_115200,
1499 pbn_b0_8_115200,
1500
1501 pbn_b0_1_921600,
1502 pbn_b0_2_921600,
1503 pbn_b0_4_921600,
1504
1505 pbn_b0_2_1130000,
1506
1507 pbn_b0_4_1152000,
1508
1509 pbn_b0_2_1843200,
1510 pbn_b0_4_1843200,
1511
1512 pbn_b0_2_1843200_200,
1513 pbn_b0_4_1843200_200,
1514 pbn_b0_8_1843200_200,
1515
1516 pbn_b0_1_4000000,
1517
1518 pbn_b0_bt_1_115200,
1519 pbn_b0_bt_2_115200,
1520 pbn_b0_bt_4_115200,
1521 pbn_b0_bt_8_115200,
1522
1523 pbn_b0_bt_1_460800,
1524 pbn_b0_bt_2_460800,
1525 pbn_b0_bt_4_460800,
1526
1527 pbn_b0_bt_1_921600,
1528 pbn_b0_bt_2_921600,
1529 pbn_b0_bt_4_921600,
1530 pbn_b0_bt_8_921600,
1531
1532 pbn_b1_1_115200,
1533 pbn_b1_2_115200,
1534 pbn_b1_4_115200,
1535 pbn_b1_8_115200,
1536 pbn_b1_16_115200,
1537
1538 pbn_b1_1_921600,
1539 pbn_b1_2_921600,
1540 pbn_b1_4_921600,
1541 pbn_b1_8_921600,
1542
1543 pbn_b1_2_1250000,
1544
1545 pbn_b1_bt_1_115200,
1546 pbn_b1_bt_2_115200,
1547 pbn_b1_bt_4_115200,
1548
1549 pbn_b1_bt_2_921600,
1550
1551 pbn_b1_1_1382400,
1552 pbn_b1_2_1382400,
1553 pbn_b1_4_1382400,
1554 pbn_b1_8_1382400,
1555
1556 pbn_b2_1_115200,
1557 pbn_b2_2_115200,
1558 pbn_b2_4_115200,
1559 pbn_b2_8_115200,
1560
1561 pbn_b2_1_460800,
1562 pbn_b2_4_460800,
1563 pbn_b2_8_460800,
1564 pbn_b2_16_460800,
1565
1566 pbn_b2_1_921600,
1567 pbn_b2_4_921600,
1568 pbn_b2_8_921600,
1569
1570 pbn_b2_8_1152000,
1571
1572 pbn_b2_bt_1_115200,
1573 pbn_b2_bt_2_115200,
1574 pbn_b2_bt_4_115200,
1575
1576 pbn_b2_bt_2_921600,
1577 pbn_b2_bt_4_921600,
1578
1579 pbn_b3_2_115200,
1580 pbn_b3_4_115200,
1581 pbn_b3_8_115200,
1582
1583 pbn_b4_bt_2_921600,
1584 pbn_b4_bt_4_921600,
1585 pbn_b4_bt_8_921600,
1586
1587 /*
1588 * Board-specific versions.
1589 */
1590 pbn_panacom,
1591 pbn_panacom2,
1592 pbn_panacom4,
1593 pbn_exsys_4055,
1594 pbn_plx_romulus,
1595 pbn_oxsemi,
1596 pbn_oxsemi_1_4000000,
1597 pbn_oxsemi_2_4000000,
1598 pbn_oxsemi_4_4000000,
1599 pbn_oxsemi_8_4000000,
1600 pbn_intel_i960,
1601 pbn_sgi_ioc3,
1602 pbn_computone_4,
1603 pbn_computone_6,
1604 pbn_computone_8,
1605 pbn_sbsxrsio,
1606 pbn_exar_XR17C152,
1607 pbn_exar_XR17C154,
1608 pbn_exar_XR17C158,
1609 pbn_exar_ibm_saturn,
1610 pbn_pasemi_1682M,
1611 pbn_ni8430_2,
1612 pbn_ni8430_4,
1613 pbn_ni8430_8,
1614 pbn_ni8430_16,
1615 pbn_ADDIDATA_PCIe_1_3906250,
1616 pbn_ADDIDATA_PCIe_2_3906250,
1617 pbn_ADDIDATA_PCIe_4_3906250,
1618 pbn_ADDIDATA_PCIe_8_3906250,
1619 pbn_ce4100_1_115200,
1620};
1621
1622/*
1623 * uart_offset - the space between channels
1624 * reg_shift - describes how the UART registers are mapped
1625 * to PCI memory by the card.
1626 * For example IER register on SBS, Inc. PMC-OctPro is located at
1627 * offset 0x10 from the UART base, while UART_IER is defined as 1
1628 * in include/linux/serial_reg.h,
1629 * see first lines of serial_in() and serial_out() in 8250.c
1630*/
1631
1632static struct pciserial_board pci_boards[] __devinitdata = {
1633 [pbn_default] = {
1634 .flags = FL_BASE0,
1635 .num_ports = 1,
1636 .base_baud = 115200,
1637 .uart_offset = 8,
1638 },
1639 [pbn_b0_1_115200] = {
1640 .flags = FL_BASE0,
1641 .num_ports = 1,
1642 .base_baud = 115200,
1643 .uart_offset = 8,
1644 },
1645 [pbn_b0_2_115200] = {
1646 .flags = FL_BASE0,
1647 .num_ports = 2,
1648 .base_baud = 115200,
1649 .uart_offset = 8,
1650 },
1651 [pbn_b0_4_115200] = {
1652 .flags = FL_BASE0,
1653 .num_ports = 4,
1654 .base_baud = 115200,
1655 .uart_offset = 8,
1656 },
1657 [pbn_b0_5_115200] = {
1658 .flags = FL_BASE0,
1659 .num_ports = 5,
1660 .base_baud = 115200,
1661 .uart_offset = 8,
1662 },
1663 [pbn_b0_8_115200] = {
1664 .flags = FL_BASE0,
1665 .num_ports = 8,
1666 .base_baud = 115200,
1667 .uart_offset = 8,
1668 },
1669 [pbn_b0_1_921600] = {
1670 .flags = FL_BASE0,
1671 .num_ports = 1,
1672 .base_baud = 921600,
1673 .uart_offset = 8,
1674 },
1675 [pbn_b0_2_921600] = {
1676 .flags = FL_BASE0,
1677 .num_ports = 2,
1678 .base_baud = 921600,
1679 .uart_offset = 8,
1680 },
1681 [pbn_b0_4_921600] = {
1682 .flags = FL_BASE0,
1683 .num_ports = 4,
1684 .base_baud = 921600,
1685 .uart_offset = 8,
1686 },
1687
1688 [pbn_b0_2_1130000] = {
1689 .flags = FL_BASE0,
1690 .num_ports = 2,
1691 .base_baud = 1130000,
1692 .uart_offset = 8,
1693 },
1694
1695 [pbn_b0_4_1152000] = {
1696 .flags = FL_BASE0,
1697 .num_ports = 4,
1698 .base_baud = 1152000,
1699 .uart_offset = 8,
1700 },
1701
1702 [pbn_b0_2_1843200] = {
1703 .flags = FL_BASE0,
1704 .num_ports = 2,
1705 .base_baud = 1843200,
1706 .uart_offset = 8,
1707 },
1708 [pbn_b0_4_1843200] = {
1709 .flags = FL_BASE0,
1710 .num_ports = 4,
1711 .base_baud = 1843200,
1712 .uart_offset = 8,
1713 },
1714
1715 [pbn_b0_2_1843200_200] = {
1716 .flags = FL_BASE0,
1717 .num_ports = 2,
1718 .base_baud = 1843200,
1719 .uart_offset = 0x200,
1720 },
1721 [pbn_b0_4_1843200_200] = {
1722 .flags = FL_BASE0,
1723 .num_ports = 4,
1724 .base_baud = 1843200,
1725 .uart_offset = 0x200,
1726 },
1727 [pbn_b0_8_1843200_200] = {
1728 .flags = FL_BASE0,
1729 .num_ports = 8,
1730 .base_baud = 1843200,
1731 .uart_offset = 0x200,
1732 },
1733 [pbn_b0_1_4000000] = {
1734 .flags = FL_BASE0,
1735 .num_ports = 1,
1736 .base_baud = 4000000,
1737 .uart_offset = 8,
1738 },
1739
1740 [pbn_b0_bt_1_115200] = {
1741 .flags = FL_BASE0|FL_BASE_BARS,
1742 .num_ports = 1,
1743 .base_baud = 115200,
1744 .uart_offset = 8,
1745 },
1746 [pbn_b0_bt_2_115200] = {
1747 .flags = FL_BASE0|FL_BASE_BARS,
1748 .num_ports = 2,
1749 .base_baud = 115200,
1750 .uart_offset = 8,
1751 },
1752 [pbn_b0_bt_4_115200] = {
1753 .flags = FL_BASE0|FL_BASE_BARS,
1754 .num_ports = 4,
1755 .base_baud = 115200,
1756 .uart_offset = 8,
1757 },
1758 [pbn_b0_bt_8_115200] = {
1759 .flags = FL_BASE0|FL_BASE_BARS,
1760 .num_ports = 8,
1761 .base_baud = 115200,
1762 .uart_offset = 8,
1763 },
1764
1765 [pbn_b0_bt_1_460800] = {
1766 .flags = FL_BASE0|FL_BASE_BARS,
1767 .num_ports = 1,
1768 .base_baud = 460800,
1769 .uart_offset = 8,
1770 },
1771 [pbn_b0_bt_2_460800] = {
1772 .flags = FL_BASE0|FL_BASE_BARS,
1773 .num_ports = 2,
1774 .base_baud = 460800,
1775 .uart_offset = 8,
1776 },
1777 [pbn_b0_bt_4_460800] = {
1778 .flags = FL_BASE0|FL_BASE_BARS,
1779 .num_ports = 4,
1780 .base_baud = 460800,
1781 .uart_offset = 8,
1782 },
1783
1784 [pbn_b0_bt_1_921600] = {
1785 .flags = FL_BASE0|FL_BASE_BARS,
1786 .num_ports = 1,
1787 .base_baud = 921600,
1788 .uart_offset = 8,
1789 },
1790 [pbn_b0_bt_2_921600] = {
1791 .flags = FL_BASE0|FL_BASE_BARS,
1792 .num_ports = 2,
1793 .base_baud = 921600,
1794 .uart_offset = 8,
1795 },
1796 [pbn_b0_bt_4_921600] = {
1797 .flags = FL_BASE0|FL_BASE_BARS,
1798 .num_ports = 4,
1799 .base_baud = 921600,
1800 .uart_offset = 8,
1801 },
1802 [pbn_b0_bt_8_921600] = {
1803 .flags = FL_BASE0|FL_BASE_BARS,
1804 .num_ports = 8,
1805 .base_baud = 921600,
1806 .uart_offset = 8,
1807 },
1808
1809 [pbn_b1_1_115200] = {
1810 .flags = FL_BASE1,
1811 .num_ports = 1,
1812 .base_baud = 115200,
1813 .uart_offset = 8,
1814 },
1815 [pbn_b1_2_115200] = {
1816 .flags = FL_BASE1,
1817 .num_ports = 2,
1818 .base_baud = 115200,
1819 .uart_offset = 8,
1820 },
1821 [pbn_b1_4_115200] = {
1822 .flags = FL_BASE1,
1823 .num_ports = 4,
1824 .base_baud = 115200,
1825 .uart_offset = 8,
1826 },
1827 [pbn_b1_8_115200] = {
1828 .flags = FL_BASE1,
1829 .num_ports = 8,
1830 .base_baud = 115200,
1831 .uart_offset = 8,
1832 },
1833 [pbn_b1_16_115200] = {
1834 .flags = FL_BASE1,
1835 .num_ports = 16,
1836 .base_baud = 115200,
1837 .uart_offset = 8,
1838 },
1839
1840 [pbn_b1_1_921600] = {
1841 .flags = FL_BASE1,
1842 .num_ports = 1,
1843 .base_baud = 921600,
1844 .uart_offset = 8,
1845 },
1846 [pbn_b1_2_921600] = {
1847 .flags = FL_BASE1,
1848 .num_ports = 2,
1849 .base_baud = 921600,
1850 .uart_offset = 8,
1851 },
1852 [pbn_b1_4_921600] = {
1853 .flags = FL_BASE1,
1854 .num_ports = 4,
1855 .base_baud = 921600,
1856 .uart_offset = 8,
1857 },
1858 [pbn_b1_8_921600] = {
1859 .flags = FL_BASE1,
1860 .num_ports = 8,
1861 .base_baud = 921600,
1862 .uart_offset = 8,
1863 },
1864 [pbn_b1_2_1250000] = {
1865 .flags = FL_BASE1,
1866 .num_ports = 2,
1867 .base_baud = 1250000,
1868 .uart_offset = 8,
1869 },
1870
1871 [pbn_b1_bt_1_115200] = {
1872 .flags = FL_BASE1|FL_BASE_BARS,
1873 .num_ports = 1,
1874 .base_baud = 115200,
1875 .uart_offset = 8,
1876 },
1877 [pbn_b1_bt_2_115200] = {
1878 .flags = FL_BASE1|FL_BASE_BARS,
1879 .num_ports = 2,
1880 .base_baud = 115200,
1881 .uart_offset = 8,
1882 },
1883 [pbn_b1_bt_4_115200] = {
1884 .flags = FL_BASE1|FL_BASE_BARS,
1885 .num_ports = 4,
1886 .base_baud = 115200,
1887 .uart_offset = 8,
1888 },
1889
1890 [pbn_b1_bt_2_921600] = {
1891 .flags = FL_BASE1|FL_BASE_BARS,
1892 .num_ports = 2,
1893 .base_baud = 921600,
1894 .uart_offset = 8,
1895 },
1896
1897 [pbn_b1_1_1382400] = {
1898 .flags = FL_BASE1,
1899 .num_ports = 1,
1900 .base_baud = 1382400,
1901 .uart_offset = 8,
1902 },
1903 [pbn_b1_2_1382400] = {
1904 .flags = FL_BASE1,
1905 .num_ports = 2,
1906 .base_baud = 1382400,
1907 .uart_offset = 8,
1908 },
1909 [pbn_b1_4_1382400] = {
1910 .flags = FL_BASE1,
1911 .num_ports = 4,
1912 .base_baud = 1382400,
1913 .uart_offset = 8,
1914 },
1915 [pbn_b1_8_1382400] = {
1916 .flags = FL_BASE1,
1917 .num_ports = 8,
1918 .base_baud = 1382400,
1919 .uart_offset = 8,
1920 },
1921
1922 [pbn_b2_1_115200] = {
1923 .flags = FL_BASE2,
1924 .num_ports = 1,
1925 .base_baud = 115200,
1926 .uart_offset = 8,
1927 },
1928 [pbn_b2_2_115200] = {
1929 .flags = FL_BASE2,
1930 .num_ports = 2,
1931 .base_baud = 115200,
1932 .uart_offset = 8,
1933 },
1934 [pbn_b2_4_115200] = {
1935 .flags = FL_BASE2,
1936 .num_ports = 4,
1937 .base_baud = 115200,
1938 .uart_offset = 8,
1939 },
1940 [pbn_b2_8_115200] = {
1941 .flags = FL_BASE2,
1942 .num_ports = 8,
1943 .base_baud = 115200,
1944 .uart_offset = 8,
1945 },
1946
1947 [pbn_b2_1_460800] = {
1948 .flags = FL_BASE2,
1949 .num_ports = 1,
1950 .base_baud = 460800,
1951 .uart_offset = 8,
1952 },
1953 [pbn_b2_4_460800] = {
1954 .flags = FL_BASE2,
1955 .num_ports = 4,
1956 .base_baud = 460800,
1957 .uart_offset = 8,
1958 },
1959 [pbn_b2_8_460800] = {
1960 .flags = FL_BASE2,
1961 .num_ports = 8,
1962 .base_baud = 460800,
1963 .uart_offset = 8,
1964 },
1965 [pbn_b2_16_460800] = {
1966 .flags = FL_BASE2,
1967 .num_ports = 16,
1968 .base_baud = 460800,
1969 .uart_offset = 8,
1970 },
1971
1972 [pbn_b2_1_921600] = {
1973 .flags = FL_BASE2,
1974 .num_ports = 1,
1975 .base_baud = 921600,
1976 .uart_offset = 8,
1977 },
1978 [pbn_b2_4_921600] = {
1979 .flags = FL_BASE2,
1980 .num_ports = 4,
1981 .base_baud = 921600,
1982 .uart_offset = 8,
1983 },
1984 [pbn_b2_8_921600] = {
1985 .flags = FL_BASE2,
1986 .num_ports = 8,
1987 .base_baud = 921600,
1988 .uart_offset = 8,
1989 },
1990
1991 [pbn_b2_8_1152000] = {
1992 .flags = FL_BASE2,
1993 .num_ports = 8,
1994 .base_baud = 1152000,
1995 .uart_offset = 8,
1996 },
1997
1998 [pbn_b2_bt_1_115200] = {
1999 .flags = FL_BASE2|FL_BASE_BARS,
2000 .num_ports = 1,
2001 .base_baud = 115200,
2002 .uart_offset = 8,
2003 },
2004 [pbn_b2_bt_2_115200] = {
2005 .flags = FL_BASE2|FL_BASE_BARS,
2006 .num_ports = 2,
2007 .base_baud = 115200,
2008 .uart_offset = 8,
2009 },
2010 [pbn_b2_bt_4_115200] = {
2011 .flags = FL_BASE2|FL_BASE_BARS,
2012 .num_ports = 4,
2013 .base_baud = 115200,
2014 .uart_offset = 8,
2015 },
2016
2017 [pbn_b2_bt_2_921600] = {
2018 .flags = FL_BASE2|FL_BASE_BARS,
2019 .num_ports = 2,
2020 .base_baud = 921600,
2021 .uart_offset = 8,
2022 },
2023 [pbn_b2_bt_4_921600] = {
2024 .flags = FL_BASE2|FL_BASE_BARS,
2025 .num_ports = 4,
2026 .base_baud = 921600,
2027 .uart_offset = 8,
2028 },
2029
2030 [pbn_b3_2_115200] = {
2031 .flags = FL_BASE3,
2032 .num_ports = 2,
2033 .base_baud = 115200,
2034 .uart_offset = 8,
2035 },
2036 [pbn_b3_4_115200] = {
2037 .flags = FL_BASE3,
2038 .num_ports = 4,
2039 .base_baud = 115200,
2040 .uart_offset = 8,
2041 },
2042 [pbn_b3_8_115200] = {
2043 .flags = FL_BASE3,
2044 .num_ports = 8,
2045 .base_baud = 115200,
2046 .uart_offset = 8,
2047 },
2048
2049 [pbn_b4_bt_2_921600] = {
2050 .flags = FL_BASE4,
2051 .num_ports = 2,
2052 .base_baud = 921600,
2053 .uart_offset = 8,
2054 },
2055 [pbn_b4_bt_4_921600] = {
2056 .flags = FL_BASE4,
2057 .num_ports = 4,
2058 .base_baud = 921600,
2059 .uart_offset = 8,
2060 },
2061 [pbn_b4_bt_8_921600] = {
2062 .flags = FL_BASE4,
2063 .num_ports = 8,
2064 .base_baud = 921600,
2065 .uart_offset = 8,
2066 },
2067
2068 /*
2069 * Entries following this are board-specific.
2070 */
2071
2072 /*
2073 * Panacom - IOMEM
2074 */
2075 [pbn_panacom] = {
2076 .flags = FL_BASE2,
2077 .num_ports = 2,
2078 .base_baud = 921600,
2079 .uart_offset = 0x400,
2080 .reg_shift = 7,
2081 },
2082 [pbn_panacom2] = {
2083 .flags = FL_BASE2|FL_BASE_BARS,
2084 .num_ports = 2,
2085 .base_baud = 921600,
2086 .uart_offset = 0x400,
2087 .reg_shift = 7,
2088 },
2089 [pbn_panacom4] = {
2090 .flags = FL_BASE2|FL_BASE_BARS,
2091 .num_ports = 4,
2092 .base_baud = 921600,
2093 .uart_offset = 0x400,
2094 .reg_shift = 7,
2095 },
2096
2097 [pbn_exsys_4055] = {
2098 .flags = FL_BASE2,
2099 .num_ports = 4,
2100 .base_baud = 115200,
2101 .uart_offset = 8,
2102 },
2103
2104 /* I think this entry is broken - the first_offset looks wrong --rmk */
2105 [pbn_plx_romulus] = {
2106 .flags = FL_BASE2,
2107 .num_ports = 4,
2108 .base_baud = 921600,
2109 .uart_offset = 8 << 2,
2110 .reg_shift = 2,
2111 .first_offset = 0x03,
2112 },
2113
2114 /*
2115 * This board uses the size of PCI Base region 0 to
2116 * signal now many ports are available
2117 */
2118 [pbn_oxsemi] = {
2119 .flags = FL_BASE0|FL_REGION_SZ_CAP,
2120 .num_ports = 32,
2121 .base_baud = 115200,
2122 .uart_offset = 8,
2123 },
2124 [pbn_oxsemi_1_4000000] = {
2125 .flags = FL_BASE0,
2126 .num_ports = 1,
2127 .base_baud = 4000000,
2128 .uart_offset = 0x200,
2129 .first_offset = 0x1000,
2130 },
2131 [pbn_oxsemi_2_4000000] = {
2132 .flags = FL_BASE0,
2133 .num_ports = 2,
2134 .base_baud = 4000000,
2135 .uart_offset = 0x200,
2136 .first_offset = 0x1000,
2137 },
2138 [pbn_oxsemi_4_4000000] = {
2139 .flags = FL_BASE0,
2140 .num_ports = 4,
2141 .base_baud = 4000000,
2142 .uart_offset = 0x200,
2143 .first_offset = 0x1000,
2144 },
2145 [pbn_oxsemi_8_4000000] = {
2146 .flags = FL_BASE0,
2147 .num_ports = 8,
2148 .base_baud = 4000000,
2149 .uart_offset = 0x200,
2150 .first_offset = 0x1000,
2151 },
2152
2153
2154 /*
2155 * EKF addition for i960 Boards form EKF with serial port.
2156 * Max 256 ports.
2157 */
2158 [pbn_intel_i960] = {
2159 .flags = FL_BASE0,
2160 .num_ports = 32,
2161 .base_baud = 921600,
2162 .uart_offset = 8 << 2,
2163 .reg_shift = 2,
2164 .first_offset = 0x10000,
2165 },
2166 [pbn_sgi_ioc3] = {
2167 .flags = FL_BASE0|FL_NOIRQ,
2168 .num_ports = 1,
2169 .base_baud = 458333,
2170 .uart_offset = 8,
2171 .reg_shift = 0,
2172 .first_offset = 0x20178,
2173 },
2174
2175 /*
2176 * Computone - uses IOMEM.
2177 */
2178 [pbn_computone_4] = {
2179 .flags = FL_BASE0,
2180 .num_ports = 4,
2181 .base_baud = 921600,
2182 .uart_offset = 0x40,
2183 .reg_shift = 2,
2184 .first_offset = 0x200,
2185 },
2186 [pbn_computone_6] = {
2187 .flags = FL_BASE0,
2188 .num_ports = 6,
2189 .base_baud = 921600,
2190 .uart_offset = 0x40,
2191 .reg_shift = 2,
2192 .first_offset = 0x200,
2193 },
2194 [pbn_computone_8] = {
2195 .flags = FL_BASE0,
2196 .num_ports = 8,
2197 .base_baud = 921600,
2198 .uart_offset = 0x40,
2199 .reg_shift = 2,
2200 .first_offset = 0x200,
2201 },
2202 [pbn_sbsxrsio] = {
2203 .flags = FL_BASE0,
2204 .num_ports = 8,
2205 .base_baud = 460800,
2206 .uart_offset = 256,
2207 .reg_shift = 4,
2208 },
2209 /*
2210 * Exar Corp. XR17C15[248] Dual/Quad/Octal UART
2211 * Only basic 16550A support.
2212 * XR17C15[24] are not tested, but they should work.
2213 */
2214 [pbn_exar_XR17C152] = {
2215 .flags = FL_BASE0,
2216 .num_ports = 2,
2217 .base_baud = 921600,
2218 .uart_offset = 0x200,
2219 },
2220 [pbn_exar_XR17C154] = {
2221 .flags = FL_BASE0,
2222 .num_ports = 4,
2223 .base_baud = 921600,
2224 .uart_offset = 0x200,
2225 },
2226 [pbn_exar_XR17C158] = {
2227 .flags = FL_BASE0,
2228 .num_ports = 8,
2229 .base_baud = 921600,
2230 .uart_offset = 0x200,
2231 },
2232 [pbn_exar_ibm_saturn] = {
2233 .flags = FL_BASE0,
2234 .num_ports = 1,
2235 .base_baud = 921600,
2236 .uart_offset = 0x200,
2237 },
2238
2239 /*
2240 * PA Semi PWRficient PA6T-1682M on-chip UART
2241 */
2242 [pbn_pasemi_1682M] = {
2243 .flags = FL_BASE0,
2244 .num_ports = 1,
2245 .base_baud = 8333333,
2246 },
2247 /*
2248 * National Instruments 843x
2249 */
2250 [pbn_ni8430_16] = {
2251 .flags = FL_BASE0,
2252 .num_ports = 16,
2253 .base_baud = 3686400,
2254 .uart_offset = 0x10,
2255 .first_offset = 0x800,
2256 },
2257 [pbn_ni8430_8] = {
2258 .flags = FL_BASE0,
2259 .num_ports = 8,
2260 .base_baud = 3686400,
2261 .uart_offset = 0x10,
2262 .first_offset = 0x800,
2263 },
2264 [pbn_ni8430_4] = {
2265 .flags = FL_BASE0,
2266 .num_ports = 4,
2267 .base_baud = 3686400,
2268 .uart_offset = 0x10,
2269 .first_offset = 0x800,
2270 },
2271 [pbn_ni8430_2] = {
2272 .flags = FL_BASE0,
2273 .num_ports = 2,
2274 .base_baud = 3686400,
2275 .uart_offset = 0x10,
2276 .first_offset = 0x800,
2277 },
2278 /*
2279 * ADDI-DATA GmbH PCI-Express communication cards <info@addi-data.com>
2280 */
2281 [pbn_ADDIDATA_PCIe_1_3906250] = {
2282 .flags = FL_BASE0,
2283 .num_ports = 1,
2284 .base_baud = 3906250,
2285 .uart_offset = 0x200,
2286 .first_offset = 0x1000,
2287 },
2288 [pbn_ADDIDATA_PCIe_2_3906250] = {
2289 .flags = FL_BASE0,
2290 .num_ports = 2,
2291 .base_baud = 3906250,
2292 .uart_offset = 0x200,
2293 .first_offset = 0x1000,
2294 },
2295 [pbn_ADDIDATA_PCIe_4_3906250] = {
2296 .flags = FL_BASE0,
2297 .num_ports = 4,
2298 .base_baud = 3906250,
2299 .uart_offset = 0x200,
2300 .first_offset = 0x1000,
2301 },
2302 [pbn_ADDIDATA_PCIe_8_3906250] = {
2303 .flags = FL_BASE0,
2304 .num_ports = 8,
2305 .base_baud = 3906250,
2306 .uart_offset = 0x200,
2307 .first_offset = 0x1000,
2308 },
2309 [pbn_ce4100_1_115200] = {
2310 .flags = FL_BASE0,
2311 .num_ports = 1,
2312 .base_baud = 921600,
2313 .reg_shift = 2,
2314 },
2315};
2316
2317static const struct pci_device_id softmodem_blacklist[] = {
2318 { PCI_VDEVICE(AL, 0x5457), }, /* ALi Corporation M5457 AC'97 Modem */
2319 { PCI_VDEVICE(MOTOROLA, 0x3052), }, /* Motorola Si3052-based modem */
2320 { PCI_DEVICE(0x1543, 0x3052), }, /* Si3052-based modem, default IDs */
2321};
2322
2323/*
2324 * Given a complete unknown PCI device, try to use some heuristics to
2325 * guess what the configuration might be, based on the pitiful PCI
2326 * serial specs. Returns 0 on success, 1 on failure.
2327 */
2328static int __devinit
2329serial_pci_guess_board(struct pci_dev *dev, struct pciserial_board *board)
2330{
2331 const struct pci_device_id *blacklist;
2332 int num_iomem, num_port, first_port = -1, i;
2333
2334 /*
2335 * If it is not a communications device or the programming
2336 * interface is greater than 6, give up.
2337 *
2338 * (Should we try to make guesses for multiport serial devices
2339 * later?)
2340 */
2341 if ((((dev->class >> 8) != PCI_CLASS_COMMUNICATION_SERIAL) &&
2342 ((dev->class >> 8) != PCI_CLASS_COMMUNICATION_MODEM)) ||
2343 (dev->class & 0xff) > 6)
2344 return -ENODEV;
2345
2346 /*
2347 * Do not access blacklisted devices that are known not to
2348 * feature serial ports.
2349 */
2350 for (blacklist = softmodem_blacklist;
2351 blacklist < softmodem_blacklist + ARRAY_SIZE(softmodem_blacklist);
2352 blacklist++) {
2353 if (dev->vendor == blacklist->vendor &&
2354 dev->device == blacklist->device)
2355 return -ENODEV;
2356 }
2357
2358 num_iomem = num_port = 0;
2359 for (i = 0; i < PCI_NUM_BAR_RESOURCES; i++) {
2360 if (pci_resource_flags(dev, i) & IORESOURCE_IO) {
2361 num_port++;
2362 if (first_port == -1)
2363 first_port = i;
2364 }
2365 if (pci_resource_flags(dev, i) & IORESOURCE_MEM)
2366 num_iomem++;
2367 }
2368
2369 /*
2370 * If there is 1 or 0 iomem regions, and exactly one port,
2371 * use it. We guess the number of ports based on the IO
2372 * region size.
2373 */
2374 if (num_iomem <= 1 && num_port == 1) {
2375 board->flags = first_port;
2376 board->num_ports = pci_resource_len(dev, first_port) / 8;
2377 return 0;
2378 }
2379
2380 /*
2381 * Now guess if we've got a board which indexes by BARs.
2382 * Each IO BAR should be 8 bytes, and they should follow
2383 * consecutively.
2384 */
2385 first_port = -1;
2386 num_port = 0;
2387 for (i = 0; i < PCI_NUM_BAR_RESOURCES; i++) {
2388 if (pci_resource_flags(dev, i) & IORESOURCE_IO &&
2389 pci_resource_len(dev, i) == 8 &&
2390 (first_port == -1 || (first_port + num_port) == i)) {
2391 num_port++;
2392 if (first_port == -1)
2393 first_port = i;
2394 }
2395 }
2396
2397 if (num_port > 1) {
2398 board->flags = first_port | FL_BASE_BARS;
2399 board->num_ports = num_port;
2400 return 0;
2401 }
2402
2403 return -ENODEV;
2404}
2405
2406static inline int
2407serial_pci_matches(const struct pciserial_board *board,
2408 const struct pciserial_board *guessed)
2409{
2410 return
2411 board->num_ports == guessed->num_ports &&
2412 board->base_baud == guessed->base_baud &&
2413 board->uart_offset == guessed->uart_offset &&
2414 board->reg_shift == guessed->reg_shift &&
2415 board->first_offset == guessed->first_offset;
2416}
2417
2418struct serial_private *
2419pciserial_init_ports(struct pci_dev *dev, const struct pciserial_board *board)
2420{
2421 struct uart_port serial_port;
2422 struct serial_private *priv;
2423 struct pci_serial_quirk *quirk;
2424 int rc, nr_ports, i;
2425
2426 nr_ports = board->num_ports;
2427
2428 /*
2429 * Find an init and setup quirks.
2430 */
2431 quirk = find_quirk(dev);
2432
2433 /*
2434 * Run the new-style initialization function.
2435 * The initialization function returns:
2436 * <0 - error
2437 * 0 - use board->num_ports
2438 * >0 - number of ports
2439 */
2440 if (quirk->init) {
2441 rc = quirk->init(dev);
2442 if (rc < 0) {
2443 priv = ERR_PTR(rc);
2444 goto err_out;
2445 }
2446 if (rc)
2447 nr_ports = rc;
2448 }
2449
2450 priv = kzalloc(sizeof(struct serial_private) +
2451 sizeof(unsigned int) * nr_ports,
2452 GFP_KERNEL);
2453 if (!priv) {
2454 priv = ERR_PTR(-ENOMEM);
2455 goto err_deinit;
2456 }
2457
2458 priv->dev = dev;
2459 priv->quirk = quirk;
2460
2461 memset(&serial_port, 0, sizeof(struct uart_port));
2462 serial_port.flags = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF | UPF_SHARE_IRQ;
2463 serial_port.uartclk = board->base_baud * 16;
2464 serial_port.irq = get_pci_irq(dev, board);
2465 serial_port.dev = &dev->dev;
2466
2467 for (i = 0; i < nr_ports; i++) {
2468 if (quirk->setup(priv, board, &serial_port, i))
2469 break;
2470
2471#ifdef SERIAL_DEBUG_PCI
2472 printk(KERN_DEBUG "Setup PCI port: port %lx, irq %d, type %d\n",
2473 serial_port.iobase, serial_port.irq, serial_port.iotype);
2474#endif
2475
2476 priv->line[i] = serial8250_register_port(&serial_port);
2477 if (priv->line[i] < 0) {
2478 printk(KERN_WARNING "Couldn't register serial port %s: %d\n", pci_name(dev), priv->line[i]);
2479 break;
2480 }
2481 }
2482 priv->nr = i;
2483 return priv;
2484
2485err_deinit:
2486 if (quirk->exit)
2487 quirk->exit(dev);
2488err_out:
2489 return priv;
2490}
2491EXPORT_SYMBOL_GPL(pciserial_init_ports);
2492
2493void pciserial_remove_ports(struct serial_private *priv)
2494{
2495 struct pci_serial_quirk *quirk;
2496 int i;
2497
2498 for (i = 0; i < priv->nr; i++)
2499 serial8250_unregister_port(priv->line[i]);
2500
2501 for (i = 0; i < PCI_NUM_BAR_RESOURCES; i++) {
2502 if (priv->remapped_bar[i])
2503 iounmap(priv->remapped_bar[i]);
2504 priv->remapped_bar[i] = NULL;
2505 }
2506
2507 /*
2508 * Find the exit quirks.
2509 */
2510 quirk = find_quirk(priv->dev);
2511 if (quirk->exit)
2512 quirk->exit(priv->dev);
2513
2514 kfree(priv);
2515}
2516EXPORT_SYMBOL_GPL(pciserial_remove_ports);
2517
2518void pciserial_suspend_ports(struct serial_private *priv)
2519{
2520 int i;
2521
2522 for (i = 0; i < priv->nr; i++)
2523 if (priv->line[i] >= 0)
2524 serial8250_suspend_port(priv->line[i]);
2525}
2526EXPORT_SYMBOL_GPL(pciserial_suspend_ports);
2527
2528void pciserial_resume_ports(struct serial_private *priv)
2529{
2530 int i;
2531
2532 /*
2533 * Ensure that the board is correctly configured.
2534 */
2535 if (priv->quirk->init)
2536 priv->quirk->init(priv->dev);
2537
2538 for (i = 0; i < priv->nr; i++)
2539 if (priv->line[i] >= 0)
2540 serial8250_resume_port(priv->line[i]);
2541}
2542EXPORT_SYMBOL_GPL(pciserial_resume_ports);
2543
2544/*
2545 * Probe one serial board. Unfortunately, there is no rhyme nor reason
2546 * to the arrangement of serial ports on a PCI card.
2547 */
2548static int __devinit
2549pciserial_init_one(struct pci_dev *dev, const struct pci_device_id *ent)
2550{
2551 struct serial_private *priv;
2552 const struct pciserial_board *board;
2553 struct pciserial_board tmp;
2554 int rc;
2555
2556 if (ent->driver_data >= ARRAY_SIZE(pci_boards)) {
2557 printk(KERN_ERR "pci_init_one: invalid driver_data: %ld\n",
2558 ent->driver_data);
2559 return -EINVAL;
2560 }
2561
2562 board = &pci_boards[ent->driver_data];
2563
2564 rc = pci_enable_device(dev);
2565 if (rc)
2566 return rc;
2567
2568 if (ent->driver_data == pbn_default) {
2569 /*
2570 * Use a copy of the pci_board entry for this;
2571 * avoid changing entries in the table.
2572 */
2573 memcpy(&tmp, board, sizeof(struct pciserial_board));
2574 board = &tmp;
2575
2576 /*
2577 * We matched one of our class entries. Try to
2578 * determine the parameters of this board.
2579 */
2580 rc = serial_pci_guess_board(dev, &tmp);
2581 if (rc)
2582 goto disable;
2583 } else {
2584 /*
2585 * We matched an explicit entry. If we are able to
2586 * detect this boards settings with our heuristic,
2587 * then we no longer need this entry.
2588 */
2589 memcpy(&tmp, &pci_boards[pbn_default],
2590 sizeof(struct pciserial_board));
2591 rc = serial_pci_guess_board(dev, &tmp);
2592 if (rc == 0 && serial_pci_matches(board, &tmp))
2593 moan_device("Redundant entry in serial pci_table.",
2594 dev);
2595 }
2596
2597 priv = pciserial_init_ports(dev, board);
2598 if (!IS_ERR(priv)) {
2599 pci_set_drvdata(dev, priv);
2600 return 0;
2601 }
2602
2603 rc = PTR_ERR(priv);
2604
2605 disable:
2606 pci_disable_device(dev);
2607 return rc;
2608}
2609
2610static void __devexit pciserial_remove_one(struct pci_dev *dev)
2611{
2612 struct serial_private *priv = pci_get_drvdata(dev);
2613
2614 pci_set_drvdata(dev, NULL);
2615
2616 pciserial_remove_ports(priv);
2617
2618 pci_disable_device(dev);
2619}
2620
2621#ifdef CONFIG_PM
2622static int pciserial_suspend_one(struct pci_dev *dev, pm_message_t state)
2623{
2624 struct serial_private *priv = pci_get_drvdata(dev);
2625
2626 if (priv)
2627 pciserial_suspend_ports(priv);
2628
2629 pci_save_state(dev);
2630 pci_set_power_state(dev, pci_choose_state(dev, state));
2631 return 0;
2632}
2633
2634static int pciserial_resume_one(struct pci_dev *dev)
2635{
2636 int err;
2637 struct serial_private *priv = pci_get_drvdata(dev);
2638
2639 pci_set_power_state(dev, PCI_D0);
2640 pci_restore_state(dev);
2641
2642 if (priv) {
2643 /*
2644 * The device may have been disabled. Re-enable it.
2645 */
2646 err = pci_enable_device(dev);
2647 /* FIXME: We cannot simply error out here */
2648 if (err)
2649 printk(KERN_ERR "pciserial: Unable to re-enable ports, trying to continue.\n");
2650 pciserial_resume_ports(priv);
2651 }
2652 return 0;
2653}
2654#endif
2655
2656static struct pci_device_id serial_pci_tbl[] = {
2657 /* Advantech use PCI_DEVICE_ID_ADVANTECH_PCI3620 (0x3620) as 'PCI_SUBVENDOR_ID' */
2658 { PCI_VENDOR_ID_ADVANTECH, PCI_DEVICE_ID_ADVANTECH_PCI3620,
2659 PCI_DEVICE_ID_ADVANTECH_PCI3620, 0x0001, 0, 0,
2660 pbn_b2_8_921600 },
2661 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V960,
2662 PCI_SUBVENDOR_ID_CONNECT_TECH,
2663 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_232, 0, 0,
2664 pbn_b1_8_1382400 },
2665 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V960,
2666 PCI_SUBVENDOR_ID_CONNECT_TECH,
2667 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_232, 0, 0,
2668 pbn_b1_4_1382400 },
2669 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V960,
2670 PCI_SUBVENDOR_ID_CONNECT_TECH,
2671 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_232, 0, 0,
2672 pbn_b1_2_1382400 },
2673 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
2674 PCI_SUBVENDOR_ID_CONNECT_TECH,
2675 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_232, 0, 0,
2676 pbn_b1_8_1382400 },
2677 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
2678 PCI_SUBVENDOR_ID_CONNECT_TECH,
2679 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_232, 0, 0,
2680 pbn_b1_4_1382400 },
2681 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
2682 PCI_SUBVENDOR_ID_CONNECT_TECH,
2683 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_232, 0, 0,
2684 pbn_b1_2_1382400 },
2685 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
2686 PCI_SUBVENDOR_ID_CONNECT_TECH,
2687 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485, 0, 0,
2688 pbn_b1_8_921600 },
2689 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
2690 PCI_SUBVENDOR_ID_CONNECT_TECH,
2691 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485_4_4, 0, 0,
2692 pbn_b1_8_921600 },
2693 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
2694 PCI_SUBVENDOR_ID_CONNECT_TECH,
2695 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_485, 0, 0,
2696 pbn_b1_4_921600 },
2697 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
2698 PCI_SUBVENDOR_ID_CONNECT_TECH,
2699 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_485_2_2, 0, 0,
2700 pbn_b1_4_921600 },
2701 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
2702 PCI_SUBVENDOR_ID_CONNECT_TECH,
2703 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_485, 0, 0,
2704 pbn_b1_2_921600 },
2705 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
2706 PCI_SUBVENDOR_ID_CONNECT_TECH,
2707 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485_2_6, 0, 0,
2708 pbn_b1_8_921600 },
2709 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
2710 PCI_SUBVENDOR_ID_CONNECT_TECH,
2711 PCI_SUBDEVICE_ID_CONNECT_TECH_BH081101V1, 0, 0,
2712 pbn_b1_8_921600 },
2713 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
2714 PCI_SUBVENDOR_ID_CONNECT_TECH,
2715 PCI_SUBDEVICE_ID_CONNECT_TECH_BH041101V1, 0, 0,
2716 pbn_b1_4_921600 },
2717 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
2718 PCI_SUBVENDOR_ID_CONNECT_TECH,
2719 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_20MHZ, 0, 0,
2720 pbn_b1_2_1250000 },
2721 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
2722 PCI_SUBVENDOR_ID_CONNECT_TECH,
2723 PCI_SUBDEVICE_ID_CONNECT_TECH_TITAN_2, 0, 0,
2724 pbn_b0_2_1843200 },
2725 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
2726 PCI_SUBVENDOR_ID_CONNECT_TECH,
2727 PCI_SUBDEVICE_ID_CONNECT_TECH_TITAN_4, 0, 0,
2728 pbn_b0_4_1843200 },
2729 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
2730 PCI_VENDOR_ID_AFAVLAB,
2731 PCI_SUBDEVICE_ID_AFAVLAB_P061, 0, 0,
2732 pbn_b0_4_1152000 },
2733 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
2734 PCI_SUBVENDOR_ID_CONNECT_TECH,
2735 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2_232, 0, 0,
2736 pbn_b0_2_1843200_200 },
2737 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154,
2738 PCI_SUBVENDOR_ID_CONNECT_TECH,
2739 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_232, 0, 0,
2740 pbn_b0_4_1843200_200 },
2741 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158,
2742 PCI_SUBVENDOR_ID_CONNECT_TECH,
2743 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8_232, 0, 0,
2744 pbn_b0_8_1843200_200 },
2745 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
2746 PCI_SUBVENDOR_ID_CONNECT_TECH,
2747 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_1_1, 0, 0,
2748 pbn_b0_2_1843200_200 },
2749 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154,
2750 PCI_SUBVENDOR_ID_CONNECT_TECH,
2751 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2_2, 0, 0,
2752 pbn_b0_4_1843200_200 },
2753 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158,
2754 PCI_SUBVENDOR_ID_CONNECT_TECH,
2755 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_4, 0, 0,
2756 pbn_b0_8_1843200_200 },
2757 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
2758 PCI_SUBVENDOR_ID_CONNECT_TECH,
2759 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2, 0, 0,
2760 pbn_b0_2_1843200_200 },
2761 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154,
2762 PCI_SUBVENDOR_ID_CONNECT_TECH,
2763 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4, 0, 0,
2764 pbn_b0_4_1843200_200 },
2765 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158,
2766 PCI_SUBVENDOR_ID_CONNECT_TECH,
2767 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8, 0, 0,
2768 pbn_b0_8_1843200_200 },
2769 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
2770 PCI_SUBVENDOR_ID_CONNECT_TECH,
2771 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2_485, 0, 0,
2772 pbn_b0_2_1843200_200 },
2773 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154,
2774 PCI_SUBVENDOR_ID_CONNECT_TECH,
2775 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_485, 0, 0,
2776 pbn_b0_4_1843200_200 },
2777 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158,
2778 PCI_SUBVENDOR_ID_CONNECT_TECH,
2779 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8_485, 0, 0,
2780 pbn_b0_8_1843200_200 },
2781 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
2782 PCI_VENDOR_ID_IBM, PCI_SUBDEVICE_ID_IBM_SATURN_SERIAL_ONE_PORT,
2783 0, 0, pbn_exar_ibm_saturn },
2784
2785 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_U530,
2786 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2787 pbn_b2_bt_1_115200 },
2788 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM2,
2789 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2790 pbn_b2_bt_2_115200 },
2791 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM422,
2792 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2793 pbn_b2_bt_4_115200 },
2794 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM232,
2795 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2796 pbn_b2_bt_2_115200 },
2797 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_COMM4,
2798 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2799 pbn_b2_bt_4_115200 },
2800 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_COMM8,
2801 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2802 pbn_b2_8_115200 },
2803 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_7803,
2804 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2805 pbn_b2_8_460800 },
2806 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM8,
2807 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2808 pbn_b2_8_115200 },
2809
2810 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_GTEK_SERIAL2,
2811 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2812 pbn_b2_bt_2_115200 },
2813 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_SPCOM200,
2814 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2815 pbn_b2_bt_2_921600 },
2816 /*
2817 * VScom SPCOM800, from sl@s.pl
2818 */
2819 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_SPCOM800,
2820 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2821 pbn_b2_8_921600 },
2822 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_1077,
2823 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2824 pbn_b2_4_921600 },
2825 /* Unknown card - subdevice 0x1584 */
2826 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
2827 PCI_VENDOR_ID_PLX,
2828 PCI_SUBDEVICE_ID_UNKNOWN_0x1584, 0, 0,
2829 pbn_b0_4_115200 },
2830 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
2831 PCI_SUBVENDOR_ID_KEYSPAN,
2832 PCI_SUBDEVICE_ID_KEYSPAN_SX2, 0, 0,
2833 pbn_panacom },
2834 { PCI_VENDOR_ID_PANACOM, PCI_DEVICE_ID_PANACOM_QUADMODEM,
2835 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2836 pbn_panacom4 },
2837 { PCI_VENDOR_ID_PANACOM, PCI_DEVICE_ID_PANACOM_DUALMODEM,
2838 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2839 pbn_panacom2 },
2840 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030,
2841 PCI_VENDOR_ID_ESDGMBH,
2842 PCI_DEVICE_ID_ESDGMBH_CPCIASIO4, 0, 0,
2843 pbn_b2_4_115200 },
2844 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
2845 PCI_SUBVENDOR_ID_CHASE_PCIFAST,
2846 PCI_SUBDEVICE_ID_CHASE_PCIFAST4, 0, 0,
2847 pbn_b2_4_460800 },
2848 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
2849 PCI_SUBVENDOR_ID_CHASE_PCIFAST,
2850 PCI_SUBDEVICE_ID_CHASE_PCIFAST8, 0, 0,
2851 pbn_b2_8_460800 },
2852 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
2853 PCI_SUBVENDOR_ID_CHASE_PCIFAST,
2854 PCI_SUBDEVICE_ID_CHASE_PCIFAST16, 0, 0,
2855 pbn_b2_16_460800 },
2856 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
2857 PCI_SUBVENDOR_ID_CHASE_PCIFAST,
2858 PCI_SUBDEVICE_ID_CHASE_PCIFAST16FMC, 0, 0,
2859 pbn_b2_16_460800 },
2860 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
2861 PCI_SUBVENDOR_ID_CHASE_PCIRAS,
2862 PCI_SUBDEVICE_ID_CHASE_PCIRAS4, 0, 0,
2863 pbn_b2_4_460800 },
2864 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
2865 PCI_SUBVENDOR_ID_CHASE_PCIRAS,
2866 PCI_SUBDEVICE_ID_CHASE_PCIRAS8, 0, 0,
2867 pbn_b2_8_460800 },
2868 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
2869 PCI_SUBVENDOR_ID_EXSYS,
2870 PCI_SUBDEVICE_ID_EXSYS_4055, 0, 0,
2871 pbn_exsys_4055 },
2872 /*
2873 * Megawolf Romulus PCI Serial Card, from Mike Hudson
2874 * (Exoray@isys.ca)
2875 */
2876 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_ROMULUS,
2877 0x10b5, 0x106a, 0, 0,
2878 pbn_plx_romulus },
2879 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSC100,
2880 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2881 pbn_b1_4_115200 },
2882 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSC100,
2883 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2884 pbn_b1_2_115200 },
2885 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_ESC100D,
2886 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2887 pbn_b1_8_115200 },
2888 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_ESC100M,
2889 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2890 pbn_b1_8_115200 },
2891 { PCI_VENDOR_ID_SPECIALIX, PCI_DEVICE_ID_OXSEMI_16PCI954,
2892 PCI_VENDOR_ID_SPECIALIX, PCI_SUBDEVICE_ID_SPECIALIX_SPEED4,
2893 0, 0,
2894 pbn_b0_4_921600 },
2895 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
2896 PCI_SUBVENDOR_ID_SIIG, PCI_SUBDEVICE_ID_SIIG_QUARTET_SERIAL,
2897 0, 0,
2898 pbn_b0_4_1152000 },
2899 { PCI_VENDOR_ID_OXSEMI, 0x9505,
2900 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2901 pbn_b0_bt_2_921600 },
2902
2903 /*
2904 * The below card is a little controversial since it is the
2905 * subject of a PCI vendor/device ID clash. (See
2906 * www.ussg.iu.edu/hypermail/linux/kernel/0303.1/0516.html).
2907 * For now just used the hex ID 0x950a.
2908 */
2909 { PCI_VENDOR_ID_OXSEMI, 0x950a,
2910 PCI_SUBVENDOR_ID_SIIG, PCI_SUBDEVICE_ID_SIIG_DUAL_SERIAL, 0, 0,
2911 pbn_b0_2_115200 },
2912 { PCI_VENDOR_ID_OXSEMI, 0x950a,
2913 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2914 pbn_b0_2_1130000 },
2915 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_C950,
2916 PCI_VENDOR_ID_OXSEMI, PCI_SUBDEVICE_ID_OXSEMI_C950, 0, 0,
2917 pbn_b0_1_921600 },
2918 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
2919 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2920 pbn_b0_4_115200 },
2921 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI952,
2922 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2923 pbn_b0_bt_2_921600 },
2924 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI958,
2925 PCI_ANY_ID , PCI_ANY_ID, 0, 0,
2926 pbn_b2_8_1152000 },
2927
2928 /*
2929 * Oxford Semiconductor Inc. Tornado PCI express device range.
2930 */
2931 { PCI_VENDOR_ID_OXSEMI, 0xc101, /* OXPCIe952 1 Legacy UART */
2932 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2933 pbn_b0_1_4000000 },
2934 { PCI_VENDOR_ID_OXSEMI, 0xc105, /* OXPCIe952 1 Legacy UART */
2935 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2936 pbn_b0_1_4000000 },
2937 { PCI_VENDOR_ID_OXSEMI, 0xc11b, /* OXPCIe952 1 Native UART */
2938 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2939 pbn_oxsemi_1_4000000 },
2940 { PCI_VENDOR_ID_OXSEMI, 0xc11f, /* OXPCIe952 1 Native UART */
2941 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2942 pbn_oxsemi_1_4000000 },
2943 { PCI_VENDOR_ID_OXSEMI, 0xc120, /* OXPCIe952 1 Legacy UART */
2944 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2945 pbn_b0_1_4000000 },
2946 { PCI_VENDOR_ID_OXSEMI, 0xc124, /* OXPCIe952 1 Legacy UART */
2947 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2948 pbn_b0_1_4000000 },
2949 { PCI_VENDOR_ID_OXSEMI, 0xc138, /* OXPCIe952 1 Native UART */
2950 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2951 pbn_oxsemi_1_4000000 },
2952 { PCI_VENDOR_ID_OXSEMI, 0xc13d, /* OXPCIe952 1 Native UART */
2953 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2954 pbn_oxsemi_1_4000000 },
2955 { PCI_VENDOR_ID_OXSEMI, 0xc140, /* OXPCIe952 1 Legacy UART */
2956 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2957 pbn_b0_1_4000000 },
2958 { PCI_VENDOR_ID_OXSEMI, 0xc141, /* OXPCIe952 1 Legacy UART */
2959 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2960 pbn_b0_1_4000000 },
2961 { PCI_VENDOR_ID_OXSEMI, 0xc144, /* OXPCIe952 1 Legacy UART */
2962 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2963 pbn_b0_1_4000000 },
2964 { PCI_VENDOR_ID_OXSEMI, 0xc145, /* OXPCIe952 1 Legacy UART */
2965 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2966 pbn_b0_1_4000000 },
2967 { PCI_VENDOR_ID_OXSEMI, 0xc158, /* OXPCIe952 2 Native UART */
2968 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2969 pbn_oxsemi_2_4000000 },
2970 { PCI_VENDOR_ID_OXSEMI, 0xc15d, /* OXPCIe952 2 Native UART */
2971 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2972 pbn_oxsemi_2_4000000 },
2973 { PCI_VENDOR_ID_OXSEMI, 0xc208, /* OXPCIe954 4 Native UART */
2974 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2975 pbn_oxsemi_4_4000000 },
2976 { PCI_VENDOR_ID_OXSEMI, 0xc20d, /* OXPCIe954 4 Native UART */
2977 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2978 pbn_oxsemi_4_4000000 },
2979 { PCI_VENDOR_ID_OXSEMI, 0xc308, /* OXPCIe958 8 Native UART */
2980 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2981 pbn_oxsemi_8_4000000 },
2982 { PCI_VENDOR_ID_OXSEMI, 0xc30d, /* OXPCIe958 8 Native UART */
2983 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2984 pbn_oxsemi_8_4000000 },
2985 { PCI_VENDOR_ID_OXSEMI, 0xc40b, /* OXPCIe200 1 Native UART */
2986 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2987 pbn_oxsemi_1_4000000 },
2988 { PCI_VENDOR_ID_OXSEMI, 0xc40f, /* OXPCIe200 1 Native UART */
2989 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2990 pbn_oxsemi_1_4000000 },
2991 { PCI_VENDOR_ID_OXSEMI, 0xc41b, /* OXPCIe200 1 Native UART */
2992 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2993 pbn_oxsemi_1_4000000 },
2994 { PCI_VENDOR_ID_OXSEMI, 0xc41f, /* OXPCIe200 1 Native UART */
2995 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2996 pbn_oxsemi_1_4000000 },
2997 { PCI_VENDOR_ID_OXSEMI, 0xc42b, /* OXPCIe200 1 Native UART */
2998 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2999 pbn_oxsemi_1_4000000 },
3000 { PCI_VENDOR_ID_OXSEMI, 0xc42f, /* OXPCIe200 1 Native UART */
3001 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3002 pbn_oxsemi_1_4000000 },
3003 { PCI_VENDOR_ID_OXSEMI, 0xc43b, /* OXPCIe200 1 Native UART */
3004 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3005 pbn_oxsemi_1_4000000 },
3006 { PCI_VENDOR_ID_OXSEMI, 0xc43f, /* OXPCIe200 1 Native UART */
3007 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3008 pbn_oxsemi_1_4000000 },
3009 { PCI_VENDOR_ID_OXSEMI, 0xc44b, /* OXPCIe200 1 Native UART */
3010 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3011 pbn_oxsemi_1_4000000 },
3012 { PCI_VENDOR_ID_OXSEMI, 0xc44f, /* OXPCIe200 1 Native UART */
3013 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3014 pbn_oxsemi_1_4000000 },
3015 { PCI_VENDOR_ID_OXSEMI, 0xc45b, /* OXPCIe200 1 Native UART */
3016 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3017 pbn_oxsemi_1_4000000 },
3018 { PCI_VENDOR_ID_OXSEMI, 0xc45f, /* OXPCIe200 1 Native UART */
3019 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3020 pbn_oxsemi_1_4000000 },
3021 { PCI_VENDOR_ID_OXSEMI, 0xc46b, /* OXPCIe200 1 Native UART */
3022 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3023 pbn_oxsemi_1_4000000 },
3024 { PCI_VENDOR_ID_OXSEMI, 0xc46f, /* OXPCIe200 1 Native UART */
3025 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3026 pbn_oxsemi_1_4000000 },
3027 { PCI_VENDOR_ID_OXSEMI, 0xc47b, /* OXPCIe200 1 Native UART */
3028 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3029 pbn_oxsemi_1_4000000 },
3030 { PCI_VENDOR_ID_OXSEMI, 0xc47f, /* OXPCIe200 1 Native UART */
3031 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3032 pbn_oxsemi_1_4000000 },
3033 { PCI_VENDOR_ID_OXSEMI, 0xc48b, /* OXPCIe200 1 Native UART */
3034 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3035 pbn_oxsemi_1_4000000 },
3036 { PCI_VENDOR_ID_OXSEMI, 0xc48f, /* OXPCIe200 1 Native UART */
3037 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3038 pbn_oxsemi_1_4000000 },
3039 { PCI_VENDOR_ID_OXSEMI, 0xc49b, /* OXPCIe200 1 Native UART */
3040 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3041 pbn_oxsemi_1_4000000 },
3042 { PCI_VENDOR_ID_OXSEMI, 0xc49f, /* OXPCIe200 1 Native UART */
3043 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3044 pbn_oxsemi_1_4000000 },
3045 { PCI_VENDOR_ID_OXSEMI, 0xc4ab, /* OXPCIe200 1 Native UART */
3046 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3047 pbn_oxsemi_1_4000000 },
3048 { PCI_VENDOR_ID_OXSEMI, 0xc4af, /* OXPCIe200 1 Native UART */
3049 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3050 pbn_oxsemi_1_4000000 },
3051 { PCI_VENDOR_ID_OXSEMI, 0xc4bb, /* OXPCIe200 1 Native UART */
3052 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3053 pbn_oxsemi_1_4000000 },
3054 { PCI_VENDOR_ID_OXSEMI, 0xc4bf, /* OXPCIe200 1 Native UART */
3055 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3056 pbn_oxsemi_1_4000000 },
3057 { PCI_VENDOR_ID_OXSEMI, 0xc4cb, /* OXPCIe200 1 Native UART */
3058 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3059 pbn_oxsemi_1_4000000 },
3060 { PCI_VENDOR_ID_OXSEMI, 0xc4cf, /* OXPCIe200 1 Native UART */
3061 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3062 pbn_oxsemi_1_4000000 },
3063 /*
3064 * Mainpine Inc. IQ Express "Rev3" utilizing OxSemi Tornado
3065 */
3066 { PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 1 Port V.34 Super-G3 Fax */
3067 PCI_VENDOR_ID_MAINPINE, 0x4001, 0, 0,
3068 pbn_oxsemi_1_4000000 },
3069 { PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 2 Port V.34 Super-G3 Fax */
3070 PCI_VENDOR_ID_MAINPINE, 0x4002, 0, 0,
3071 pbn_oxsemi_2_4000000 },
3072 { PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 4 Port V.34 Super-G3 Fax */
3073 PCI_VENDOR_ID_MAINPINE, 0x4004, 0, 0,
3074 pbn_oxsemi_4_4000000 },
3075 { PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 8 Port V.34 Super-G3 Fax */
3076 PCI_VENDOR_ID_MAINPINE, 0x4008, 0, 0,
3077 pbn_oxsemi_8_4000000 },
3078 /*
3079 * SBS Technologies, Inc. P-Octal and PMC-OCTPRO cards,
3080 * from skokodyn@yahoo.com
3081 */
3082 { PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
3083 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_OCTPRO232, 0, 0,
3084 pbn_sbsxrsio },
3085 { PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
3086 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_OCTPRO422, 0, 0,
3087 pbn_sbsxrsio },
3088 { PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
3089 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_POCTAL232, 0, 0,
3090 pbn_sbsxrsio },
3091 { PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
3092 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_POCTAL422, 0, 0,
3093 pbn_sbsxrsio },
3094
3095 /*
3096 * Digitan DS560-558, from jimd@esoft.com
3097 */
3098 { PCI_VENDOR_ID_ATT, PCI_DEVICE_ID_ATT_VENUS_MODEM,
3099 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3100 pbn_b1_1_115200 },
3101
3102 /*
3103 * Titan Electronic cards
3104 * The 400L and 800L have a custom setup quirk.
3105 */
3106 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_100,
3107 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3108 pbn_b0_1_921600 },
3109 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200,
3110 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3111 pbn_b0_2_921600 },
3112 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400,
3113 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3114 pbn_b0_4_921600 },
3115 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800B,
3116 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3117 pbn_b0_4_921600 },
3118 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_100L,
3119 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3120 pbn_b1_1_921600 },
3121 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200L,
3122 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3123 pbn_b1_bt_2_921600 },
3124 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400L,
3125 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3126 pbn_b0_bt_4_921600 },
3127 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800L,
3128 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3129 pbn_b0_bt_8_921600 },
3130 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200I,
3131 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3132 pbn_b4_bt_2_921600 },
3133 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400I,
3134 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3135 pbn_b4_bt_4_921600 },
3136 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800I,
3137 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3138 pbn_b4_bt_8_921600 },
3139 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400EH,
3140 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3141 pbn_b0_4_921600 },
3142 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800EH,
3143 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3144 pbn_b0_4_921600 },
3145 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800EHB,
3146 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3147 pbn_b0_4_921600 },
3148 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_100E,
3149 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3150 pbn_oxsemi_1_4000000 },
3151 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200E,
3152 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3153 pbn_oxsemi_2_4000000 },
3154 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400E,
3155 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3156 pbn_oxsemi_4_4000000 },
3157 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800E,
3158 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3159 pbn_oxsemi_8_4000000 },
3160 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200EI,
3161 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3162 pbn_oxsemi_2_4000000 },
3163 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200EISI,
3164 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3165 pbn_oxsemi_2_4000000 },
3166
3167 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_10x_550,
3168 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3169 pbn_b2_1_460800 },
3170 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_10x_650,
3171 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3172 pbn_b2_1_460800 },
3173 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_10x_850,
3174 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3175 pbn_b2_1_460800 },
3176 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_10x_550,
3177 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3178 pbn_b2_bt_2_921600 },
3179 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_10x_650,
3180 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3181 pbn_b2_bt_2_921600 },
3182 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_10x_850,
3183 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3184 pbn_b2_bt_2_921600 },
3185 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_10x_550,
3186 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3187 pbn_b2_bt_4_921600 },
3188 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_10x_650,
3189 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3190 pbn_b2_bt_4_921600 },
3191 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_10x_850,
3192 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3193 pbn_b2_bt_4_921600 },
3194 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_20x_550,
3195 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3196 pbn_b0_1_921600 },
3197 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_20x_650,
3198 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3199 pbn_b0_1_921600 },
3200 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_20x_850,
3201 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3202 pbn_b0_1_921600 },
3203 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_20x_550,
3204 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3205 pbn_b0_bt_2_921600 },
3206 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_20x_650,
3207 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3208 pbn_b0_bt_2_921600 },
3209 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_20x_850,
3210 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3211 pbn_b0_bt_2_921600 },
3212 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_20x_550,
3213 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3214 pbn_b0_bt_4_921600 },
3215 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_20x_650,
3216 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3217 pbn_b0_bt_4_921600 },
3218 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_20x_850,
3219 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3220 pbn_b0_bt_4_921600 },
3221 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_8S_20x_550,
3222 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3223 pbn_b0_bt_8_921600 },
3224 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_8S_20x_650,
3225 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3226 pbn_b0_bt_8_921600 },
3227 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_8S_20x_850,
3228 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3229 pbn_b0_bt_8_921600 },
3230
3231 /*
3232 * Computone devices submitted by Doug McNash dmcnash@computone.com
3233 */
3234 { PCI_VENDOR_ID_COMPUTONE, PCI_DEVICE_ID_COMPUTONE_PG,
3235 PCI_SUBVENDOR_ID_COMPUTONE, PCI_SUBDEVICE_ID_COMPUTONE_PG4,
3236 0, 0, pbn_computone_4 },
3237 { PCI_VENDOR_ID_COMPUTONE, PCI_DEVICE_ID_COMPUTONE_PG,
3238 PCI_SUBVENDOR_ID_COMPUTONE, PCI_SUBDEVICE_ID_COMPUTONE_PG8,
3239 0, 0, pbn_computone_8 },
3240 { PCI_VENDOR_ID_COMPUTONE, PCI_DEVICE_ID_COMPUTONE_PG,
3241 PCI_SUBVENDOR_ID_COMPUTONE, PCI_SUBDEVICE_ID_COMPUTONE_PG6,
3242 0, 0, pbn_computone_6 },
3243
3244 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI95N,
3245 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3246 pbn_oxsemi },
3247 { PCI_VENDOR_ID_TIMEDIA, PCI_DEVICE_ID_TIMEDIA_1889,
3248 PCI_VENDOR_ID_TIMEDIA, PCI_ANY_ID, 0, 0,
3249 pbn_b0_bt_1_921600 },
3250
3251 /*
3252 * AFAVLAB serial card, from Harald Welte <laforge@gnumonks.org>
3253 */
3254 { PCI_VENDOR_ID_AFAVLAB, PCI_DEVICE_ID_AFAVLAB_P028,
3255 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3256 pbn_b0_bt_8_115200 },
3257 { PCI_VENDOR_ID_AFAVLAB, PCI_DEVICE_ID_AFAVLAB_P030,
3258 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3259 pbn_b0_bt_8_115200 },
3260
3261 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_DSERIAL,
3262 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3263 pbn_b0_bt_2_115200 },
3264 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATRO_A,
3265 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3266 pbn_b0_bt_2_115200 },
3267 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATRO_B,
3268 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3269 pbn_b0_bt_2_115200 },
3270 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATTRO_A,
3271 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3272 pbn_b0_bt_2_115200 },
3273 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATTRO_B,
3274 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3275 pbn_b0_bt_2_115200 },
3276 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_OCTO_A,
3277 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3278 pbn_b0_bt_4_460800 },
3279 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_OCTO_B,
3280 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3281 pbn_b0_bt_4_460800 },
3282 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_PORT_PLUS,
3283 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3284 pbn_b0_bt_2_460800 },
3285 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUAD_A,
3286 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3287 pbn_b0_bt_2_460800 },
3288 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUAD_B,
3289 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3290 pbn_b0_bt_2_460800 },
3291 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_SSERIAL,
3292 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3293 pbn_b0_bt_1_115200 },
3294 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_PORT_650,
3295 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3296 pbn_b0_bt_1_460800 },
3297
3298 /*
3299 * Korenix Jetcard F0/F1 cards (JC1204, JC1208, JC1404, JC1408).
3300 * Cards are identified by their subsystem vendor IDs, which
3301 * (in hex) match the model number.
3302 *
3303 * Note that JC140x are RS422/485 cards which require ox950
3304 * ACR = 0x10, and as such are not currently fully supported.
3305 */
3306 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0,
3307 0x1204, 0x0004, 0, 0,
3308 pbn_b0_4_921600 },
3309 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0,
3310 0x1208, 0x0004, 0, 0,
3311 pbn_b0_4_921600 },
3312/* { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0,
3313 0x1402, 0x0002, 0, 0,
3314 pbn_b0_2_921600 }, */
3315/* { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0,
3316 0x1404, 0x0004, 0, 0,
3317 pbn_b0_4_921600 }, */
3318 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF1,
3319 0x1208, 0x0004, 0, 0,
3320 pbn_b0_4_921600 },
3321
3322 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF2,
3323 0x1204, 0x0004, 0, 0,
3324 pbn_b0_4_921600 },
3325 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF2,
3326 0x1208, 0x0004, 0, 0,
3327 pbn_b0_4_921600 },
3328 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF3,
3329 0x1208, 0x0004, 0, 0,
3330 pbn_b0_4_921600 },
3331 /*
3332 * Dell Remote Access Card 4 - Tim_T_Murphy@Dell.com
3333 */
3334 { PCI_VENDOR_ID_DELL, PCI_DEVICE_ID_DELL_RAC4,
3335 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3336 pbn_b1_1_1382400 },
3337
3338 /*
3339 * Dell Remote Access Card III - Tim_T_Murphy@Dell.com
3340 */
3341 { PCI_VENDOR_ID_DELL, PCI_DEVICE_ID_DELL_RACIII,
3342 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3343 pbn_b1_1_1382400 },
3344
3345 /*
3346 * RAStel 2 port modem, gerg@moreton.com.au
3347 */
3348 { PCI_VENDOR_ID_MORETON, PCI_DEVICE_ID_RASTEL_2PORT,
3349 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3350 pbn_b2_bt_2_115200 },
3351
3352 /*
3353 * EKF addition for i960 Boards form EKF with serial port
3354 */
3355 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80960_RP,
3356 0xE4BF, PCI_ANY_ID, 0, 0,
3357 pbn_intel_i960 },
3358
3359 /*
3360 * Xircom Cardbus/Ethernet combos
3361 */
3362 { PCI_VENDOR_ID_XIRCOM, PCI_DEVICE_ID_XIRCOM_X3201_MDM,
3363 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3364 pbn_b0_1_115200 },
3365 /*
3366 * Xircom RBM56G cardbus modem - Dirk Arnold (temp entry)
3367 */
3368 { PCI_VENDOR_ID_XIRCOM, PCI_DEVICE_ID_XIRCOM_RBM56G,
3369 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3370 pbn_b0_1_115200 },
3371
3372 /*
3373 * Untested PCI modems, sent in from various folks...
3374 */
3375
3376 /*
3377 * Elsa Model 56K PCI Modem, from Andreas Rath <arh@01019freenet.de>
3378 */
3379 { PCI_VENDOR_ID_ROCKWELL, 0x1004,
3380 0x1048, 0x1500, 0, 0,
3381 pbn_b1_1_115200 },
3382
3383 { PCI_VENDOR_ID_SGI, PCI_DEVICE_ID_SGI_IOC3,
3384 0xFF00, 0, 0, 0,
3385 pbn_sgi_ioc3 },
3386
3387 /*
3388 * HP Diva card
3389 */
3390 { PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA,
3391 PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA_RMP3, 0, 0,
3392 pbn_b1_1_115200 },
3393 { PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA,
3394 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3395 pbn_b0_5_115200 },
3396 { PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA_AUX,
3397 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3398 pbn_b2_1_115200 },
3399
3400 { PCI_VENDOR_ID_DCI, PCI_DEVICE_ID_DCI_PCCOM2,
3401 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3402 pbn_b3_2_115200 },
3403 { PCI_VENDOR_ID_DCI, PCI_DEVICE_ID_DCI_PCCOM4,
3404 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3405 pbn_b3_4_115200 },
3406 { PCI_VENDOR_ID_DCI, PCI_DEVICE_ID_DCI_PCCOM8,
3407 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3408 pbn_b3_8_115200 },
3409
3410 /*
3411 * Exar Corp. XR17C15[248] Dual/Quad/Octal UART
3412 */
3413 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
3414 PCI_ANY_ID, PCI_ANY_ID,
3415 0,
3416 0, pbn_exar_XR17C152 },
3417 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154,
3418 PCI_ANY_ID, PCI_ANY_ID,
3419 0,
3420 0, pbn_exar_XR17C154 },
3421 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158,
3422 PCI_ANY_ID, PCI_ANY_ID,
3423 0,
3424 0, pbn_exar_XR17C158 },
3425
3426 /*
3427 * Topic TP560 Data/Fax/Voice 56k modem (reported by Evan Clarke)
3428 */
3429 { PCI_VENDOR_ID_TOPIC, PCI_DEVICE_ID_TOPIC_TP560,
3430 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3431 pbn_b0_1_115200 },
3432 /*
3433 * ITE
3434 */
3435 { PCI_VENDOR_ID_ITE, PCI_DEVICE_ID_ITE_8872,
3436 PCI_ANY_ID, PCI_ANY_ID,
3437 0, 0,
3438 pbn_b1_bt_1_115200 },
3439
3440 /*
3441 * IntaShield IS-200
3442 */
3443 { PCI_VENDOR_ID_INTASHIELD, PCI_DEVICE_ID_INTASHIELD_IS200,
3444 PCI_ANY_ID, PCI_ANY_ID, 0, 0, /* 135a.0811 */
3445 pbn_b2_2_115200 },
3446 /*
3447 * IntaShield IS-400
3448 */
3449 { PCI_VENDOR_ID_INTASHIELD, PCI_DEVICE_ID_INTASHIELD_IS400,
3450 PCI_ANY_ID, PCI_ANY_ID, 0, 0, /* 135a.0dc0 */
3451 pbn_b2_4_115200 },
3452 /*
3453 * Perle PCI-RAS cards
3454 */
3455 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030,
3456 PCI_SUBVENDOR_ID_PERLE, PCI_SUBDEVICE_ID_PCI_RAS4,
3457 0, 0, pbn_b2_4_921600 },
3458 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030,
3459 PCI_SUBVENDOR_ID_PERLE, PCI_SUBDEVICE_ID_PCI_RAS8,
3460 0, 0, pbn_b2_8_921600 },
3461
3462 /*
3463 * Mainpine series cards: Fairly standard layout but fools
3464 * parts of the autodetect in some cases and uses otherwise
3465 * unmatched communications subclasses in the PCI Express case
3466 */
3467
3468 { /* RockForceDUO */
3469 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3470 PCI_VENDOR_ID_MAINPINE, 0x0200,
3471 0, 0, pbn_b0_2_115200 },
3472 { /* RockForceQUATRO */
3473 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3474 PCI_VENDOR_ID_MAINPINE, 0x0300,
3475 0, 0, pbn_b0_4_115200 },
3476 { /* RockForceDUO+ */
3477 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3478 PCI_VENDOR_ID_MAINPINE, 0x0400,
3479 0, 0, pbn_b0_2_115200 },
3480 { /* RockForceQUATRO+ */
3481 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3482 PCI_VENDOR_ID_MAINPINE, 0x0500,
3483 0, 0, pbn_b0_4_115200 },
3484 { /* RockForce+ */
3485 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3486 PCI_VENDOR_ID_MAINPINE, 0x0600,
3487 0, 0, pbn_b0_2_115200 },
3488 { /* RockForce+ */
3489 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3490 PCI_VENDOR_ID_MAINPINE, 0x0700,
3491 0, 0, pbn_b0_4_115200 },
3492 { /* RockForceOCTO+ */
3493 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3494 PCI_VENDOR_ID_MAINPINE, 0x0800,
3495 0, 0, pbn_b0_8_115200 },
3496 { /* RockForceDUO+ */
3497 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3498 PCI_VENDOR_ID_MAINPINE, 0x0C00,
3499 0, 0, pbn_b0_2_115200 },
3500 { /* RockForceQUARTRO+ */
3501 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3502 PCI_VENDOR_ID_MAINPINE, 0x0D00,
3503 0, 0, pbn_b0_4_115200 },
3504 { /* RockForceOCTO+ */
3505 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3506 PCI_VENDOR_ID_MAINPINE, 0x1D00,
3507 0, 0, pbn_b0_8_115200 },
3508 { /* RockForceD1 */
3509 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3510 PCI_VENDOR_ID_MAINPINE, 0x2000,
3511 0, 0, pbn_b0_1_115200 },
3512 { /* RockForceF1 */
3513 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3514 PCI_VENDOR_ID_MAINPINE, 0x2100,
3515 0, 0, pbn_b0_1_115200 },
3516 { /* RockForceD2 */
3517 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3518 PCI_VENDOR_ID_MAINPINE, 0x2200,
3519 0, 0, pbn_b0_2_115200 },
3520 { /* RockForceF2 */
3521 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3522 PCI_VENDOR_ID_MAINPINE, 0x2300,
3523 0, 0, pbn_b0_2_115200 },
3524 { /* RockForceD4 */
3525 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3526 PCI_VENDOR_ID_MAINPINE, 0x2400,
3527 0, 0, pbn_b0_4_115200 },
3528 { /* RockForceF4 */
3529 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3530 PCI_VENDOR_ID_MAINPINE, 0x2500,
3531 0, 0, pbn_b0_4_115200 },
3532 { /* RockForceD8 */
3533 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3534 PCI_VENDOR_ID_MAINPINE, 0x2600,
3535 0, 0, pbn_b0_8_115200 },
3536 { /* RockForceF8 */
3537 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3538 PCI_VENDOR_ID_MAINPINE, 0x2700,
3539 0, 0, pbn_b0_8_115200 },
3540 { /* IQ Express D1 */
3541 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3542 PCI_VENDOR_ID_MAINPINE, 0x3000,
3543 0, 0, pbn_b0_1_115200 },
3544 { /* IQ Express F1 */
3545 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3546 PCI_VENDOR_ID_MAINPINE, 0x3100,
3547 0, 0, pbn_b0_1_115200 },
3548 { /* IQ Express D2 */
3549 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3550 PCI_VENDOR_ID_MAINPINE, 0x3200,
3551 0, 0, pbn_b0_2_115200 },
3552 { /* IQ Express F2 */
3553 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3554 PCI_VENDOR_ID_MAINPINE, 0x3300,
3555 0, 0, pbn_b0_2_115200 },
3556 { /* IQ Express D4 */
3557 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3558 PCI_VENDOR_ID_MAINPINE, 0x3400,
3559 0, 0, pbn_b0_4_115200 },
3560 { /* IQ Express F4 */
3561 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3562 PCI_VENDOR_ID_MAINPINE, 0x3500,
3563 0, 0, pbn_b0_4_115200 },
3564 { /* IQ Express D8 */
3565 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3566 PCI_VENDOR_ID_MAINPINE, 0x3C00,
3567 0, 0, pbn_b0_8_115200 },
3568 { /* IQ Express F8 */
3569 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3570 PCI_VENDOR_ID_MAINPINE, 0x3D00,
3571 0, 0, pbn_b0_8_115200 },
3572
3573
3574 /*
3575 * PA Semi PA6T-1682M on-chip UART
3576 */
3577 { PCI_VENDOR_ID_PASEMI, 0xa004,
3578 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3579 pbn_pasemi_1682M },
3580
3581 /*
3582 * National Instruments
3583 */
3584 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI23216,
3585 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3586 pbn_b1_16_115200 },
3587 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2328,
3588 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3589 pbn_b1_8_115200 },
3590 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2324,
3591 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3592 pbn_b1_bt_4_115200 },
3593 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2322,
3594 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3595 pbn_b1_bt_2_115200 },
3596 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2324I,
3597 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3598 pbn_b1_bt_4_115200 },
3599 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2322I,
3600 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3601 pbn_b1_bt_2_115200 },
3602 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8420_23216,
3603 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3604 pbn_b1_16_115200 },
3605 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8420_2328,
3606 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3607 pbn_b1_8_115200 },
3608 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8420_2324,
3609 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3610 pbn_b1_bt_4_115200 },
3611 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8420_2322,
3612 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3613 pbn_b1_bt_2_115200 },
3614 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8422_2324,
3615 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3616 pbn_b1_bt_4_115200 },
3617 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8422_2322,
3618 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3619 pbn_b1_bt_2_115200 },
3620 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8430_2322,
3621 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3622 pbn_ni8430_2 },
3623 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8430_2322,
3624 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3625 pbn_ni8430_2 },
3626 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8430_2324,
3627 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3628 pbn_ni8430_4 },
3629 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8430_2324,
3630 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3631 pbn_ni8430_4 },
3632 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8430_2328,
3633 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3634 pbn_ni8430_8 },
3635 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8430_2328,
3636 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3637 pbn_ni8430_8 },
3638 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8430_23216,
3639 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3640 pbn_ni8430_16 },
3641 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8430_23216,
3642 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3643 pbn_ni8430_16 },
3644 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8432_2322,
3645 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3646 pbn_ni8430_2 },
3647 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8432_2322,
3648 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3649 pbn_ni8430_2 },
3650 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8432_2324,
3651 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3652 pbn_ni8430_4 },
3653 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8432_2324,
3654 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3655 pbn_ni8430_4 },
3656
3657 /*
3658 * ADDI-DATA GmbH communication cards <info@addi-data.com>
3659 */
3660 { PCI_VENDOR_ID_ADDIDATA,
3661 PCI_DEVICE_ID_ADDIDATA_APCI7500,
3662 PCI_ANY_ID,
3663 PCI_ANY_ID,
3664 0,
3665 0,
3666 pbn_b0_4_115200 },
3667
3668 { PCI_VENDOR_ID_ADDIDATA,
3669 PCI_DEVICE_ID_ADDIDATA_APCI7420,
3670 PCI_ANY_ID,
3671 PCI_ANY_ID,
3672 0,
3673 0,
3674 pbn_b0_2_115200 },
3675
3676 { PCI_VENDOR_ID_ADDIDATA,
3677 PCI_DEVICE_ID_ADDIDATA_APCI7300,
3678 PCI_ANY_ID,
3679 PCI_ANY_ID,
3680 0,
3681 0,
3682 pbn_b0_1_115200 },
3683
3684 { PCI_VENDOR_ID_ADDIDATA_OLD,
3685 PCI_DEVICE_ID_ADDIDATA_APCI7800,
3686 PCI_ANY_ID,
3687 PCI_ANY_ID,
3688 0,
3689 0,
3690 pbn_b1_8_115200 },
3691
3692 { PCI_VENDOR_ID_ADDIDATA,
3693 PCI_DEVICE_ID_ADDIDATA_APCI7500_2,
3694 PCI_ANY_ID,
3695 PCI_ANY_ID,
3696 0,
3697 0,
3698 pbn_b0_4_115200 },
3699
3700 { PCI_VENDOR_ID_ADDIDATA,
3701 PCI_DEVICE_ID_ADDIDATA_APCI7420_2,
3702 PCI_ANY_ID,
3703 PCI_ANY_ID,
3704 0,
3705 0,
3706 pbn_b0_2_115200 },
3707
3708 { PCI_VENDOR_ID_ADDIDATA,
3709 PCI_DEVICE_ID_ADDIDATA_APCI7300_2,
3710 PCI_ANY_ID,
3711 PCI_ANY_ID,
3712 0,
3713 0,
3714 pbn_b0_1_115200 },
3715
3716 { PCI_VENDOR_ID_ADDIDATA,
3717 PCI_DEVICE_ID_ADDIDATA_APCI7500_3,
3718 PCI_ANY_ID,
3719 PCI_ANY_ID,
3720 0,
3721 0,
3722 pbn_b0_4_115200 },
3723
3724 { PCI_VENDOR_ID_ADDIDATA,
3725 PCI_DEVICE_ID_ADDIDATA_APCI7420_3,
3726 PCI_ANY_ID,
3727 PCI_ANY_ID,
3728 0,
3729 0,
3730 pbn_b0_2_115200 },
3731
3732 { PCI_VENDOR_ID_ADDIDATA,
3733 PCI_DEVICE_ID_ADDIDATA_APCI7300_3,
3734 PCI_ANY_ID,
3735 PCI_ANY_ID,
3736 0,
3737 0,
3738 pbn_b0_1_115200 },
3739
3740 { PCI_VENDOR_ID_ADDIDATA,
3741 PCI_DEVICE_ID_ADDIDATA_APCI7800_3,
3742 PCI_ANY_ID,
3743 PCI_ANY_ID,
3744 0,
3745 0,
3746 pbn_b0_8_115200 },
3747
3748 { PCI_VENDOR_ID_ADDIDATA,
3749 PCI_DEVICE_ID_ADDIDATA_APCIe7500,
3750 PCI_ANY_ID,
3751 PCI_ANY_ID,
3752 0,
3753 0,
3754 pbn_ADDIDATA_PCIe_4_3906250 },
3755
3756 { PCI_VENDOR_ID_ADDIDATA,
3757 PCI_DEVICE_ID_ADDIDATA_APCIe7420,
3758 PCI_ANY_ID,
3759 PCI_ANY_ID,
3760 0,
3761 0,
3762 pbn_ADDIDATA_PCIe_2_3906250 },
3763
3764 { PCI_VENDOR_ID_ADDIDATA,
3765 PCI_DEVICE_ID_ADDIDATA_APCIe7300,
3766 PCI_ANY_ID,
3767 PCI_ANY_ID,
3768 0,
3769 0,
3770 pbn_ADDIDATA_PCIe_1_3906250 },
3771
3772 { PCI_VENDOR_ID_ADDIDATA,
3773 PCI_DEVICE_ID_ADDIDATA_APCIe7800,
3774 PCI_ANY_ID,
3775 PCI_ANY_ID,
3776 0,
3777 0,
3778 pbn_ADDIDATA_PCIe_8_3906250 },
3779
3780 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9835,
3781 PCI_VENDOR_ID_IBM, 0x0299,
3782 0, 0, pbn_b0_bt_2_115200 },
3783
3784 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9901,
3785 0xA000, 0x1000,
3786 0, 0, pbn_b0_1_115200 },
3787
3788 /*
3789 * Best Connectivity PCI Multi I/O cards
3790 */
3791
3792 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9865,
3793 0xA000, 0x1000,
3794 0, 0, pbn_b0_1_115200 },
3795
3796 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9865,
3797 0xA000, 0x3004,
3798 0, 0, pbn_b0_bt_4_115200 },
3799 /* Intel CE4100 */
3800 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CE4100_UART,
3801 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3802 pbn_ce4100_1_115200 },
3803
3804
3805 /*
3806 * These entries match devices with class COMMUNICATION_SERIAL,
3807 * COMMUNICATION_MODEM or COMMUNICATION_MULTISERIAL
3808 */
3809 { PCI_ANY_ID, PCI_ANY_ID,
3810 PCI_ANY_ID, PCI_ANY_ID,
3811 PCI_CLASS_COMMUNICATION_SERIAL << 8,
3812 0xffff00, pbn_default },
3813 { PCI_ANY_ID, PCI_ANY_ID,
3814 PCI_ANY_ID, PCI_ANY_ID,
3815 PCI_CLASS_COMMUNICATION_MODEM << 8,
3816 0xffff00, pbn_default },
3817 { PCI_ANY_ID, PCI_ANY_ID,
3818 PCI_ANY_ID, PCI_ANY_ID,
3819 PCI_CLASS_COMMUNICATION_MULTISERIAL << 8,
3820 0xffff00, pbn_default },
3821 { 0, }
3822};
3823
3824static struct pci_driver serial_pci_driver = {
3825 .name = "serial",
3826 .probe = pciserial_init_one,
3827 .remove = __devexit_p(pciserial_remove_one),
3828#ifdef CONFIG_PM
3829 .suspend = pciserial_suspend_one,
3830 .resume = pciserial_resume_one,
3831#endif
3832 .id_table = serial_pci_tbl,
3833};
3834
3835static int __init serial8250_pci_init(void)
3836{
3837 return pci_register_driver(&serial_pci_driver);
3838}
3839
3840static void __exit serial8250_pci_exit(void)
3841{
3842 pci_unregister_driver(&serial_pci_driver);
3843}
3844
3845module_init(serial8250_pci_init);
3846module_exit(serial8250_pci_exit);
3847
3848MODULE_LICENSE("GPL");
3849MODULE_DESCRIPTION("Generic 8250/16x50 PCI serial probe module");
3850MODULE_DEVICE_TABLE(pci, serial_pci_tbl);
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-13 12:05:18 -0500