diff options
author | Dmitri Belimov <d.belimov@gmail.com> | 2011-01-20 01:05:08 -0500 |
---|---|---|
committer | Mauro Carvalho Chehab <mchehab@redhat.com> | 2011-03-21 19:31:53 -0400 |
commit | 8e030cabf1bb8601ad3efe09b9dc65a441a294ec (patch) | |
tree | 0cf70f1f1762b74b150a0c44bfab00eb9004e83c /drivers/staging | |
parent | cbfb3daa66bc43f4e2d4f2063db7472a8b2837f5 (diff) |
[media] tm6000: add/rework reg.defines
Rework registers defines. Add TM6000 specific registers defines.
Add marks and comments for TM6010 specific registers.
Signed-off-by: Beholder Intl. Ltd. Dmitry Belimov <d.belimov@gmail.com>
Signed-off-by: Mauro Carvalho Chehab <mchehab@redhat.com>
Diffstat (limited to 'drivers/staging')
-rw-r--r-- | drivers/staging/tm6000/tm6000-regs.h | 63 |
1 files changed, 60 insertions, 3 deletions
diff --git a/drivers/staging/tm6000/tm6000-regs.h b/drivers/staging/tm6000/tm6000-regs.h index 1f0ced8fa20f..5375a8347374 100644 --- a/drivers/staging/tm6000/tm6000-regs.h +++ b/drivers/staging/tm6000/tm6000-regs.h | |||
@@ -97,6 +97,34 @@ enum { | |||
97 | TM6000_URB_MSG_ERR, | 97 | TM6000_URB_MSG_ERR, |
98 | }; | 98 | }; |
99 | 99 | ||
100 | /* Define specific TM6000 Video decoder registers */ | ||
101 | #define TM6000_REQ07_RD8_TEST_SEL 0x07, 0xd8 | ||
102 | #define TM6000_REQ07_RD9_A_SIM_SEL 0x07, 0xd9 | ||
103 | #define TM6000_REQ07_RDA_CLK_SEL 0x07, 0xda | ||
104 | #define TM6000_REQ07_RDB_OUT_SEL 0x07, 0xdb | ||
105 | #define TM6000_REQ07_RDC_NSEL_I2S 0x07, 0xdc | ||
106 | #define TM6000_REQ07_RDD_GPIO2_MDRV 0x07, 0xdd | ||
107 | #define TM6000_REQ07_RDE_GPIO1_MDRV 0x07, 0xde | ||
108 | #define TM6000_REQ07_RDF_PWDOWN_ACLK 0x07, 0xdf | ||
109 | #define TM6000_REQ07_RE0_VADC_REF_CTL 0x07, 0xe0 | ||
110 | #define TM6000_REQ07_RE1_VADC_DACLIMP 0x07, 0xe1 | ||
111 | #define TM6000_REQ07_RE2_VADC_STATUS_CTL 0x07, 0xe2 | ||
112 | #define TM6000_REQ07_RE3_VADC_INP_LPF_SEL1 0x07, 0xe3 | ||
113 | #define TM6000_REQ07_RE4_VADC_TARGET1 0x07, 0xe4 | ||
114 | #define TM6000_REQ07_RE5_VADC_INP_LPF_SEL2 0x07, 0xe5 | ||
115 | #define TM6000_REQ07_RE6_VADC_TARGET2 0x07, 0xe6 | ||
116 | #define TM6000_REQ07_RE7_VADC_AGAIN_CTL 0x07, 0xe7 | ||
117 | #define TM6000_REQ07_RE8_VADC_PWDOWN_CTL 0x07, 0xe8 | ||
118 | #define TM6000_REQ07_RE9_VADC_INPUT_CTL1 0x07, 0xe9 | ||
119 | #define TM6000_REQ07_REA_VADC_INPUT_CTL2 0x07, 0xea | ||
120 | #define TM6000_REQ07_REB_VADC_AADC_MODE 0x07, 0xeb | ||
121 | #define TM6000_REQ07_REC_VADC_AADC_LVOL 0x07, 0xec | ||
122 | #define TM6000_REQ07_RED_VADC_AADC_RVOL 0x07, 0xed | ||
123 | #define TM6000_REQ07_REE_VADC_CTRL_SEL_CONTROL 0x07, 0xee | ||
124 | #define TM6000_REQ07_REF_VADC_GAIN_MAP_CTL 0x07, 0xef | ||
125 | #define TM6000_REQ07_RFD_BIST_ERR_VST_LOW 0x07, 0xfd | ||
126 | #define TM6000_REQ07_RFE_BIST_ERR_VST_HIGH 0x07, 0xfe | ||
127 | |||
100 | /* Define TM6000/TM6010 Video decoder registers */ | 128 | /* Define TM6000/TM6010 Video decoder registers */ |
101 | #define TM6010_REQ07_R00_VIDEO_CONTROL0 0x07, 0x00 | 129 | #define TM6010_REQ07_R00_VIDEO_CONTROL0 0x07, 0x00 |
102 | #define TM6010_REQ07_R01_VIDEO_CONTROL1 0x07, 0x01 | 130 | #define TM6010_REQ07_R01_VIDEO_CONTROL1 0x07, 0x01 |
@@ -241,6 +269,7 @@ enum { | |||
241 | #define TM6010_REQ07_RC9_VEND1 0x07, 0xc9 | 269 | #define TM6010_REQ07_RC9_VEND1 0x07, 0xc9 |
242 | #define TM6010_REQ07_RCA_VEND0 0x07, 0xca | 270 | #define TM6010_REQ07_RCA_VEND0 0x07, 0xca |
243 | #define TM6010_REQ07_RCB_DELAY 0x07, 0xcb | 271 | #define TM6010_REQ07_RCB_DELAY 0x07, 0xcb |
272 | /* ONLY for TM6010 */ | ||
244 | #define TM6010_REQ07_RCC_ACTIVE_VIDEO_IF 0x07, 0xcc | 273 | #define TM6010_REQ07_RCC_ACTIVE_VIDEO_IF 0x07, 0xcc |
245 | #define TM6010_REQ07_RD0_USB_PERIPHERY_CONTROL 0x07, 0xd0 | 274 | #define TM6010_REQ07_RD0_USB_PERIPHERY_CONTROL 0x07, 0xd0 |
246 | #define TM6010_REQ07_RD1_ADDR_FOR_REQ1 0x07, 0xd1 | 275 | #define TM6010_REQ07_RD1_ADDR_FOR_REQ1 0x07, 0xd1 |
@@ -250,32 +279,59 @@ enum { | |||
250 | #define TM6010_REQ07_RD5_POWERSAVE 0x07, 0xd5 | 279 | #define TM6010_REQ07_RD5_POWERSAVE 0x07, 0xd5 |
251 | #define TM6010_REQ07_RD6_ENDP_REQ1_REQ2 0x07, 0xd6 | 280 | #define TM6010_REQ07_RD6_ENDP_REQ1_REQ2 0x07, 0xd6 |
252 | #define TM6010_REQ07_RD7_ENDP_REQ3_REQ4 0x07, 0xd7 | 281 | #define TM6010_REQ07_RD7_ENDP_REQ3_REQ4 0x07, 0xd7 |
282 | /* ONLY for TM6010 */ | ||
253 | #define TM6010_REQ07_RD8_IR 0x07, 0xd8 | 283 | #define TM6010_REQ07_RD8_IR 0x07, 0xd8 |
284 | /* ONLY for TM6010 */ | ||
254 | #define TM6010_REQ07_RD8_IR_BSIZE 0x07, 0xd9 | 285 | #define TM6010_REQ07_RD8_IR_BSIZE 0x07, 0xd9 |
286 | /* ONLY for TM6010 */ | ||
255 | #define TM6010_REQ07_RD8_IR_WAKEUP_SEL 0x07, 0xda | 287 | #define TM6010_REQ07_RD8_IR_WAKEUP_SEL 0x07, 0xda |
288 | /* ONLY for TM6010 */ | ||
256 | #define TM6010_REQ07_RD8_IR_WAKEUP_ADD 0x07, 0xdb | 289 | #define TM6010_REQ07_RD8_IR_WAKEUP_ADD 0x07, 0xdb |
290 | /* ONLY for TM6010 */ | ||
257 | #define TM6010_REQ07_RD8_IR_LEADER1 0x07, 0xdc | 291 | #define TM6010_REQ07_RD8_IR_LEADER1 0x07, 0xdc |
292 | /* ONLY for TM6010 */ | ||
258 | #define TM6010_REQ07_RD8_IR_LEADER0 0x07, 0xdd | 293 | #define TM6010_REQ07_RD8_IR_LEADER0 0x07, 0xdd |
294 | /* ONLY for TM6010 */ | ||
259 | #define TM6010_REQ07_RD8_IR_PULSE_CNT1 0x07, 0xde | 295 | #define TM6010_REQ07_RD8_IR_PULSE_CNT1 0x07, 0xde |
296 | /* ONLY for TM6010 */ | ||
260 | #define TM6010_REQ07_RD8_IR_PULSE_CNT0 0x07, 0xdf | 297 | #define TM6010_REQ07_RD8_IR_PULSE_CNT0 0x07, 0xdf |
298 | /* ONLY for TM6010 */ | ||
261 | #define TM6010_REQ07_RE0_DVIDEO_SOURCE 0x07, 0xe0 | 299 | #define TM6010_REQ07_RE0_DVIDEO_SOURCE 0x07, 0xe0 |
300 | /* ONLY for TM6010 */ | ||
262 | #define TM6010_REQ07_RE0_DVIDEO_SOURCE_IF 0x07, 0xe1 | 301 | #define TM6010_REQ07_RE0_DVIDEO_SOURCE_IF 0x07, 0xe1 |
302 | /* ONLY for TM6010 */ | ||
263 | #define TM6010_REQ07_RE2_OUT_SEL2 0x07, 0xe2 | 303 | #define TM6010_REQ07_RE2_OUT_SEL2 0x07, 0xe2 |
304 | /* ONLY for TM6010 */ | ||
264 | #define TM6010_REQ07_RE3_OUT_SEL1 0x07, 0xe3 | 305 | #define TM6010_REQ07_RE3_OUT_SEL1 0x07, 0xe3 |
306 | /* ONLY for TM6010 */ | ||
265 | #define TM6010_REQ07_RE4_OUT_SEL0 0x07, 0xe4 | 307 | #define TM6010_REQ07_RE4_OUT_SEL0 0x07, 0xe4 |
308 | /* ONLY for TM6010 */ | ||
266 | #define TM6010_REQ07_RE5_REMOTE_WAKEUP 0x07, 0xe5 | 309 | #define TM6010_REQ07_RE5_REMOTE_WAKEUP 0x07, 0xe5 |
310 | /* ONLY for TM6010 */ | ||
267 | #define TM6010_REQ07_RE7_PUB_GPIO 0x07, 0xe7 | 311 | #define TM6010_REQ07_RE7_PUB_GPIO 0x07, 0xe7 |
312 | /* ONLY for TM6010 */ | ||
268 | #define TM6010_REQ07_RE8_TYPESEL_MOS_I2S 0x07, 0xe8 | 313 | #define TM6010_REQ07_RE8_TYPESEL_MOS_I2S 0x07, 0xe8 |
314 | /* ONLY for TM6010 */ | ||
269 | #define TM6010_REQ07_RE9_TYPESEL_MOS_TS 0x07, 0xe9 | 315 | #define TM6010_REQ07_RE9_TYPESEL_MOS_TS 0x07, 0xe9 |
316 | /* ONLY for TM6010 */ | ||
270 | #define TM6010_REQ07_REA_TYPESEL_MOS_CCIR 0x07, 0xea | 317 | #define TM6010_REQ07_REA_TYPESEL_MOS_CCIR 0x07, 0xea |
318 | /* ONLY for TM6010 */ | ||
271 | #define TM6010_REQ07_RF0_BIST_CRC_RESULT0 0x07, 0xf0 | 319 | #define TM6010_REQ07_RF0_BIST_CRC_RESULT0 0x07, 0xf0 |
320 | /* ONLY for TM6010 */ | ||
272 | #define TM6010_REQ07_RF1_BIST_CRC_RESULT1 0x07, 0xf1 | 321 | #define TM6010_REQ07_RF1_BIST_CRC_RESULT1 0x07, 0xf1 |
322 | /* ONLY for TM6010 */ | ||
273 | #define TM6010_REQ07_RF2_BIST_CRC_RESULT2 0x07, 0xf2 | 323 | #define TM6010_REQ07_RF2_BIST_CRC_RESULT2 0x07, 0xf2 |
324 | /* ONLY for TM6010 */ | ||
274 | #define TM6010_REQ07_RF3_BIST_CRC_RESULT3 0x07, 0xf3 | 325 | #define TM6010_REQ07_RF3_BIST_CRC_RESULT3 0x07, 0xf3 |
326 | /* ONLY for TM6010 */ | ||
275 | #define TM6010_REQ07_RF4_BIST_ERR_VST2 0x07, 0xf4 | 327 | #define TM6010_REQ07_RF4_BIST_ERR_VST2 0x07, 0xf4 |
328 | /* ONLY for TM6010 */ | ||
276 | #define TM6010_REQ07_RF5_BIST_ERR_VST1 0x07, 0xf5 | 329 | #define TM6010_REQ07_RF5_BIST_ERR_VST1 0x07, 0xf5 |
330 | /* ONLY for TM6010 */ | ||
277 | #define TM6010_REQ07_RF6_BIST_ERR_VST0 0x07, 0xf6 | 331 | #define TM6010_REQ07_RF6_BIST_ERR_VST0 0x07, 0xf6 |
332 | /* ONLY for TM6010 */ | ||
278 | #define TM6010_REQ07_RF7_BIST 0x07, 0xf7 | 333 | #define TM6010_REQ07_RF7_BIST 0x07, 0xf7 |
334 | /* ONLY for TM6010 */ | ||
279 | #define TM6010_REQ07_RFE_POWER_DOWN 0x07, 0xfe | 335 | #define TM6010_REQ07_RFE_POWER_DOWN 0x07, 0xfe |
280 | #define TM6010_REQ07_RFF_SOFT_RESET 0x07, 0xff | 336 | #define TM6010_REQ07_RFF_SOFT_RESET 0x07, 0xff |
281 | 337 | ||
@@ -477,7 +533,8 @@ enum { | |||
477 | #define TM6010_REQ05_RC4_DATA_FIFO14 0x05, 0xf8 | 533 | #define TM6010_REQ05_RC4_DATA_FIFO14 0x05, 0xf8 |
478 | #define TM6010_REQ05_RC4_DATA_FIFO15 0x05, 0xfc | 534 | #define TM6010_REQ05_RC4_DATA_FIFO15 0x05, 0xfc |
479 | 535 | ||
480 | /* Define TM6000/TM6010 Audio decoder registers */ | 536 | /* Define TM6010 Audio decoder registers */ |
537 | /* This core available only in TM6010 */ | ||
481 | #define TM6010_REQ08_R00_A_VERSION 0x08, 0x00 | 538 | #define TM6010_REQ08_R00_A_VERSION 0x08, 0x00 |
482 | #define TM6010_REQ08_R01_A_INIT 0x08, 0x01 | 539 | #define TM6010_REQ08_R01_A_INIT 0x08, 0x01 |
483 | #define TM6010_REQ08_R02_A_FIX_GAIN_CTRL 0x08, 0x02 | 540 | #define TM6010_REQ08_R02_A_FIX_GAIN_CTRL 0x08, 0x02 |
@@ -518,7 +575,7 @@ enum { | |||
518 | #define TM6010_REQ08_R27_A_NOISE_AMP 0x08, 0x27 | 575 | #define TM6010_REQ08_R27_A_NOISE_AMP 0x08, 0x27 |
519 | #define TM6010_REQ08_R28_A_AUDIO_MODE_RES 0x08, 0x28 | 576 | #define TM6010_REQ08_R28_A_AUDIO_MODE_RES 0x08, 0x28 |
520 | 577 | ||
521 | /* Define TM6000/TM6010 Video ADC registers */ | 578 | /* Define TM6010 Video ADC registers */ |
522 | #define TM6010_REQ08_RE0_ADC_REF 0x08, 0xe0 | 579 | #define TM6010_REQ08_RE0_ADC_REF 0x08, 0xe0 |
523 | #define TM6010_REQ08_RE1_DAC_CLMP 0x08, 0xe1 | 580 | #define TM6010_REQ08_RE1_DAC_CLMP 0x08, 0xe1 |
524 | #define TM6010_REQ08_RE2_POWER_DOWN_CTRL1 0x08, 0xe2 | 581 | #define TM6010_REQ08_RE2_POWER_DOWN_CTRL1 0x08, 0xe2 |
@@ -534,7 +591,7 @@ enum { | |||
534 | #define TM6010_REQ08_REC_REVERSE_YC_CTRL 0x08, 0xec | 591 | #define TM6010_REQ08_REC_REVERSE_YC_CTRL 0x08, 0xec |
535 | #define TM6010_REQ08_RED_GAIN_SEL 0x08, 0xed | 592 | #define TM6010_REQ08_RED_GAIN_SEL 0x08, 0xed |
536 | 593 | ||
537 | /* Define TM6000/TM6010 Audio ADC registers */ | 594 | /* Define TM6010 Audio ADC registers */ |
538 | #define TM6010_REQ08_RF0_DAUDIO_INPUT_CONFIG 0x08, 0xf0 | 595 | #define TM6010_REQ08_RF0_DAUDIO_INPUT_CONFIG 0x08, 0xf0 |
539 | #define TM6010_REQ08_RF1_AADC_POWER_DOWN 0x08, 0xf1 | 596 | #define TM6010_REQ08_RF1_AADC_POWER_DOWN 0x08, 0xf1 |
540 | #define TM6010_REQ08_RF2_LEFT_CHANNEL_VOL 0x08, 0xf2 | 597 | #define TM6010_REQ08_RF2_LEFT_CHANNEL_VOL 0x08, 0xf2 |