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authorJonathan Cameron <jic23@cam.ac.uk>2011-05-18 09:42:35 -0400
committerGreg Kroah-Hartman <gregkh@suse.de>2011-05-19 19:15:05 -0400
commit7df86302f4258764a3b8b1d63848dab3aa292654 (patch)
tree65820fa745852f1cdb1a692ec97f6fc5881dc021 /drivers/staging
parent8d213f24f2291a3edc7f94ac2bec8c85015aed96 (diff)
staging:iio:accel:lis3l02dq make write_reg_8 take value not a pointer to value.
Silliness that has been there a long time. Signed-off-by: Jonathan Cameron <jic23@cam.ac.uk> Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
Diffstat (limited to 'drivers/staging')
-rw-r--r--drivers/staging/iio/accel/lis3l02dq.h2
-rw-r--r--drivers/staging/iio/accel/lis3l02dq_core.c30
-rw-r--r--drivers/staging/iio/accel/lis3l02dq_ring.c10
3 files changed, 21 insertions, 21 deletions
diff --git a/drivers/staging/iio/accel/lis3l02dq.h b/drivers/staging/iio/accel/lis3l02dq.h
index 94d98695995c..18b23acfb6f4 100644
--- a/drivers/staging/iio/accel/lis3l02dq.h
+++ b/drivers/staging/iio/accel/lis3l02dq.h
@@ -170,7 +170,7 @@ int lis3l02dq_spi_read_reg_8(struct iio_dev *indio_dev,
170 170
171int lis3l02dq_spi_write_reg_8(struct iio_dev *indio_dev, 171int lis3l02dq_spi_write_reg_8(struct iio_dev *indio_dev,
172 u8 reg_address, 172 u8 reg_address,
173 u8 *val); 173 u8 val);
174 174
175int lis3l02dq_disable_all_events(struct iio_dev *indio_dev); 175int lis3l02dq_disable_all_events(struct iio_dev *indio_dev);
176 176
diff --git a/drivers/staging/iio/accel/lis3l02dq_core.c b/drivers/staging/iio/accel/lis3l02dq_core.c
index 6b5414c913ff..942139a02ed7 100644
--- a/drivers/staging/iio/accel/lis3l02dq_core.c
+++ b/drivers/staging/iio/accel/lis3l02dq_core.c
@@ -82,14 +82,14 @@ int lis3l02dq_spi_read_reg_8(struct iio_dev *indio_dev,
82 **/ 82 **/
83int lis3l02dq_spi_write_reg_8(struct iio_dev *indio_dev, 83int lis3l02dq_spi_write_reg_8(struct iio_dev *indio_dev,
84 u8 reg_address, 84 u8 reg_address,
85 u8 *val) 85 u8 val)
86{ 86{
87 int ret; 87 int ret;
88 struct lis3l02dq_state *st = iio_priv(indio_dev); 88 struct lis3l02dq_state *st = iio_priv(indio_dev);
89 89
90 mutex_lock(&st->buf_lock); 90 mutex_lock(&st->buf_lock);
91 st->tx[0] = LIS3L02DQ_WRITE_REG(reg_address); 91 st->tx[0] = LIS3L02DQ_WRITE_REG(reg_address);
92 st->tx[1] = *val; 92 st->tx[1] = val;
93 ret = spi_write(st->us, st->tx, 2); 93 ret = spi_write(st->us, st->tx, 2);
94 mutex_unlock(&st->buf_lock); 94 mutex_unlock(&st->buf_lock);
95 95
@@ -232,14 +232,14 @@ static int lis3l02dq_write_raw(struct iio_dev *indio_dev,
232 return -EINVAL; 232 return -EINVAL;
233 sval = val; 233 sval = val;
234 reg = lis3l02dq_axis_map[LIS3L02DQ_BIAS][chan->address]; 234 reg = lis3l02dq_axis_map[LIS3L02DQ_BIAS][chan->address];
235 ret = lis3l02dq_spi_write_reg_8(indio_dev, reg, (u8 *)&sval); 235 ret = lis3l02dq_spi_write_reg_8(indio_dev, reg, sval);
236 break; 236 break;
237 case (1 << IIO_CHAN_INFO_CALIBSCALE_SEPARATE): 237 case (1 << IIO_CHAN_INFO_CALIBSCALE_SEPARATE):
238 if (val & ~0xFF) 238 if (val & ~0xFF)
239 return -EINVAL; 239 return -EINVAL;
240 uval = val; 240 uval = val;
241 reg = lis3l02dq_axis_map[LIS3L02DQ_GAIN][chan->address]; 241 reg = lis3l02dq_axis_map[LIS3L02DQ_GAIN][chan->address];
242 ret = lis3l02dq_spi_write_reg_8(indio_dev, reg, &uval); 242 ret = lis3l02dq_spi_write_reg_8(indio_dev, reg, uval);
243 break; 243 break;
244 } 244 }
245 return ret; 245 return ret;
@@ -367,7 +367,7 @@ static ssize_t lis3l02dq_write_frequency(struct device *dev,
367 367
368 ret = lis3l02dq_spi_write_reg_8(indio_dev, 368 ret = lis3l02dq_spi_write_reg_8(indio_dev,
369 LIS3L02DQ_REG_CTRL_1_ADDR, 369 LIS3L02DQ_REG_CTRL_1_ADDR,
370 &t); 370 t);
371 371
372error_ret_mutex: 372error_ret_mutex:
373 mutex_unlock(&indio_dev->mlock); 373 mutex_unlock(&indio_dev->mlock);
@@ -389,7 +389,7 @@ static int lis3l02dq_initial_setup(struct iio_dev *indio_dev)
389 /* Write suitable defaults to ctrl1 */ 389 /* Write suitable defaults to ctrl1 */
390 ret = lis3l02dq_spi_write_reg_8(indio_dev, 390 ret = lis3l02dq_spi_write_reg_8(indio_dev,
391 LIS3L02DQ_REG_CTRL_1_ADDR, 391 LIS3L02DQ_REG_CTRL_1_ADDR,
392 &val); 392 val);
393 if (ret) { 393 if (ret) {
394 dev_err(&st->us->dev, "problem with setup control register 1"); 394 dev_err(&st->us->dev, "problem with setup control register 1");
395 goto err_ret; 395 goto err_ret;
@@ -397,7 +397,7 @@ static int lis3l02dq_initial_setup(struct iio_dev *indio_dev)
397 /* Repeat as sometimes doesn't work first time?*/ 397 /* Repeat as sometimes doesn't work first time?*/
398 ret = lis3l02dq_spi_write_reg_8(indio_dev, 398 ret = lis3l02dq_spi_write_reg_8(indio_dev,
399 LIS3L02DQ_REG_CTRL_1_ADDR, 399 LIS3L02DQ_REG_CTRL_1_ADDR,
400 &val); 400 val);
401 if (ret) { 401 if (ret) {
402 dev_err(&st->us->dev, "problem with setup control register 1"); 402 dev_err(&st->us->dev, "problem with setup control register 1");
403 goto err_ret; 403 goto err_ret;
@@ -418,7 +418,7 @@ static int lis3l02dq_initial_setup(struct iio_dev *indio_dev)
418 val = LIS3L02DQ_DEFAULT_CTRL2; 418 val = LIS3L02DQ_DEFAULT_CTRL2;
419 ret = lis3l02dq_spi_write_reg_8(indio_dev, 419 ret = lis3l02dq_spi_write_reg_8(indio_dev,
420 LIS3L02DQ_REG_CTRL_2_ADDR, 420 LIS3L02DQ_REG_CTRL_2_ADDR,
421 &val); 421 val);
422 if (ret) { 422 if (ret) {
423 dev_err(&st->us->dev, "problem with setup control register 2"); 423 dev_err(&st->us->dev, "problem with setup control register 2");
424 goto err_ret; 424 goto err_ret;
@@ -427,7 +427,7 @@ static int lis3l02dq_initial_setup(struct iio_dev *indio_dev)
427 val = LIS3L02DQ_REG_WAKE_UP_CFG_LATCH_SRC; 427 val = LIS3L02DQ_REG_WAKE_UP_CFG_LATCH_SRC;
428 ret = lis3l02dq_spi_write_reg_8(indio_dev, 428 ret = lis3l02dq_spi_write_reg_8(indio_dev,
429 LIS3L02DQ_REG_WAKE_UP_CFG_ADDR, 429 LIS3L02DQ_REG_WAKE_UP_CFG_ADDR,
430 &val); 430 val);
431 if (ret) 431 if (ret)
432 dev_err(&st->us->dev, "problem with interrupt cfg register"); 432 dev_err(&st->us->dev, "problem with interrupt cfg register");
433err_ret: 433err_ret:
@@ -564,7 +564,7 @@ int lis3l02dq_disable_all_events(struct iio_dev *indio_dev)
564 control &= ~LIS3L02DQ_REG_CTRL_2_ENABLE_INTERRUPT; 564 control &= ~LIS3L02DQ_REG_CTRL_2_ENABLE_INTERRUPT;
565 ret = lis3l02dq_spi_write_reg_8(indio_dev, 565 ret = lis3l02dq_spi_write_reg_8(indio_dev,
566 LIS3L02DQ_REG_CTRL_2_ADDR, 566 LIS3L02DQ_REG_CTRL_2_ADDR,
567 &control); 567 control);
568 if (ret) 568 if (ret)
569 goto error_ret; 569 goto error_ret;
570 /* Also for consistency clear the mask */ 570 /* Also for consistency clear the mask */
@@ -577,7 +577,7 @@ int lis3l02dq_disable_all_events(struct iio_dev *indio_dev)
577 577
578 ret = lis3l02dq_spi_write_reg_8(indio_dev, 578 ret = lis3l02dq_spi_write_reg_8(indio_dev,
579 LIS3L02DQ_REG_WAKE_UP_CFG_ADDR, 579 LIS3L02DQ_REG_WAKE_UP_CFG_ADDR,
580 &val); 580 val);
581 if (ret) 581 if (ret)
582 goto error_ret; 582 goto error_ret;
583 583
@@ -623,7 +623,7 @@ static int lis3l02dq_write_event_config(struct iio_dev *indio_dev,
623 if (changed) { 623 if (changed) {
624 ret = lis3l02dq_spi_write_reg_8(indio_dev, 624 ret = lis3l02dq_spi_write_reg_8(indio_dev,
625 LIS3L02DQ_REG_WAKE_UP_CFG_ADDR, 625 LIS3L02DQ_REG_WAKE_UP_CFG_ADDR,
626 &val); 626 val);
627 if (ret) 627 if (ret)
628 goto error_ret; 628 goto error_ret;
629 control = val & 0x3f ? 629 control = val & 0x3f ?
@@ -631,7 +631,7 @@ static int lis3l02dq_write_event_config(struct iio_dev *indio_dev,
631 (control & ~LIS3L02DQ_REG_CTRL_2_ENABLE_INTERRUPT); 631 (control & ~LIS3L02DQ_REG_CTRL_2_ENABLE_INTERRUPT);
632 ret = lis3l02dq_spi_write_reg_8(indio_dev, 632 ret = lis3l02dq_spi_write_reg_8(indio_dev,
633 LIS3L02DQ_REG_CTRL_2_ADDR, 633 LIS3L02DQ_REG_CTRL_2_ADDR,
634 &control); 634 control);
635 if (ret) 635 if (ret)
636 goto error_ret; 636 goto error_ret;
637 } 637 }
@@ -750,7 +750,7 @@ static int lis3l02dq_stop_device(struct iio_dev *indio_dev)
750 mutex_lock(&indio_dev->mlock); 750 mutex_lock(&indio_dev->mlock);
751 ret = lis3l02dq_spi_write_reg_8(indio_dev, 751 ret = lis3l02dq_spi_write_reg_8(indio_dev,
752 LIS3L02DQ_REG_CTRL_1_ADDR, 752 LIS3L02DQ_REG_CTRL_1_ADDR,
753 &val); 753 val);
754 if (ret) { 754 if (ret) {
755 dev_err(&st->us->dev, "problem with turning device off: ctrl1"); 755 dev_err(&st->us->dev, "problem with turning device off: ctrl1");
756 goto err_ret; 756 goto err_ret;
@@ -758,7 +758,7 @@ static int lis3l02dq_stop_device(struct iio_dev *indio_dev)
758 758
759 ret = lis3l02dq_spi_write_reg_8(indio_dev, 759 ret = lis3l02dq_spi_write_reg_8(indio_dev,
760 LIS3L02DQ_REG_CTRL_2_ADDR, 760 LIS3L02DQ_REG_CTRL_2_ADDR,
761 &val); 761 val);
762 if (ret) 762 if (ret)
763 dev_err(&st->us->dev, "problem with turning device off: ctrl2"); 763 dev_err(&st->us->dev, "problem with turning device off: ctrl2");
764err_ret: 764err_ret:
diff --git a/drivers/staging/iio/accel/lis3l02dq_ring.c b/drivers/staging/iio/accel/lis3l02dq_ring.c
index c8f29bc73f68..1c208d268c73 100644
--- a/drivers/staging/iio/accel/lis3l02dq_ring.c
+++ b/drivers/staging/iio/accel/lis3l02dq_ring.c
@@ -220,12 +220,12 @@ __lis3l02dq_write_data_ready_config(struct device *dev, bool state)
220 /* The double write is to overcome a hardware bug?*/ 220 /* The double write is to overcome a hardware bug?*/
221 ret = lis3l02dq_spi_write_reg_8(indio_dev, 221 ret = lis3l02dq_spi_write_reg_8(indio_dev,
222 LIS3L02DQ_REG_CTRL_2_ADDR, 222 LIS3L02DQ_REG_CTRL_2_ADDR,
223 &valold); 223 valold);
224 if (ret) 224 if (ret)
225 goto error_ret; 225 goto error_ret;
226 ret = lis3l02dq_spi_write_reg_8(indio_dev, 226 ret = lis3l02dq_spi_write_reg_8(indio_dev,
227 LIS3L02DQ_REG_CTRL_2_ADDR, 227 LIS3L02DQ_REG_CTRL_2_ADDR,
228 &valold); 228 valold);
229 if (ret) 229 if (ret)
230 goto error_ret; 230 goto error_ret;
231 st->trigger_on = false; 231 st->trigger_on = false;
@@ -243,7 +243,7 @@ __lis3l02dq_write_data_ready_config(struct device *dev, bool state)
243 st->trigger_on = true; 243 st->trigger_on = true;
244 ret = lis3l02dq_spi_write_reg_8(indio_dev, 244 ret = lis3l02dq_spi_write_reg_8(indio_dev,
245 LIS3L02DQ_REG_CTRL_2_ADDR, 245 LIS3L02DQ_REG_CTRL_2_ADDR,
246 &valold); 246 valold);
247 if (ret) 247 if (ret)
248 goto error_ret; 248 goto error_ret;
249 } 249 }
@@ -382,7 +382,7 @@ static int lis3l02dq_ring_postenable(struct iio_dev *indio_dev)
382 return -EINVAL; 382 return -EINVAL;
383 ret = lis3l02dq_spi_write_reg_8(indio_dev, 383 ret = lis3l02dq_spi_write_reg_8(indio_dev,
384 LIS3L02DQ_REG_CTRL_1_ADDR, 384 LIS3L02DQ_REG_CTRL_1_ADDR,
385 &t); 385 t);
386 if (ret) 386 if (ret)
387 goto error_ret; 387 goto error_ret;
388 388
@@ -412,7 +412,7 @@ static int lis3l02dq_ring_predisable(struct iio_dev *indio_dev)
412 412
413 ret = lis3l02dq_spi_write_reg_8(indio_dev, 413 ret = lis3l02dq_spi_write_reg_8(indio_dev,
414 LIS3L02DQ_REG_CTRL_1_ADDR, 414 LIS3L02DQ_REG_CTRL_1_ADDR,
415 &t); 415 t);
416 416
417error_ret: 417error_ret:
418 return ret; 418 return ret;