diff options
author | Mark Einon <mark.einon@gmail.com> | 2011-10-23 05:22:51 -0400 |
---|---|---|
committer | Greg Kroah-Hartman <gregkh@suse.de> | 2011-10-23 05:35:13 -0400 |
commit | 2288760e3bc1639d8a33ae751f36738b7d96af8f (patch) | |
tree | 80d30eac29e4d8a806942fd99388aaa77e83e86d /drivers/staging | |
parent | a4d444bdef709d37838f83f92cab33b6c4475627 (diff) |
staging: et131x: Remove even more forward declarations
Moved functions in et131x.c file to remove the forward declarations of:
et1310_in_phy_coma
et1310_phy_access_mii_bit
et131x_phy_mii_read
et131x_mii_write
et131x_rx_dma_memory_free
Signed-off-by: Mark Einon <mark.einon@gmail.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
Diffstat (limited to 'drivers/staging')
-rw-r--r-- | drivers/staging/et131x/et131x.c | 395 |
1 files changed, 193 insertions, 202 deletions
diff --git a/drivers/staging/et131x/et131x.c b/drivers/staging/et131x/et131x.c index 208c69fcb76e..2e621aaadd68 100644 --- a/drivers/staging/et131x/et131x.c +++ b/drivers/staging/et131x/et131x.c | |||
@@ -576,15 +576,6 @@ struct et131x_adapter { | |||
576 | struct net_device_stats net_stats; | 576 | struct net_device_stats net_stats; |
577 | }; | 577 | }; |
578 | 578 | ||
579 | int et1310_in_phy_coma(struct et131x_adapter *adapter); | ||
580 | void et1310_phy_access_mii_bit(struct et131x_adapter *adapter, | ||
581 | u16 action, | ||
582 | u16 regnum, u16 bitnum, u8 *value); | ||
583 | int et131x_phy_mii_read(struct et131x_adapter *adapter, u8 addr, | ||
584 | u8 reg, u16 *value); | ||
585 | int32_t et131x_mii_write(struct et131x_adapter *adapter, | ||
586 | u8 reg, u16 value); | ||
587 | void et131x_rx_dma_memory_free(struct et131x_adapter *adapter); | ||
588 | void et131x_rx_dma_disable(struct et131x_adapter *adapter); | 579 | void et131x_rx_dma_disable(struct et131x_adapter *adapter); |
589 | void et131x_rx_dma_enable(struct et131x_adapter *adapter); | 580 | void et131x_rx_dma_enable(struct et131x_adapter *adapter); |
590 | void et131x_init_send(struct et131x_adapter *adapter); | 581 | void et131x_init_send(struct et131x_adapter *adapter); |
@@ -1019,6 +1010,21 @@ void et1310_config_mac_regs2(struct et131x_adapter *adapter) | |||
1019 | } | 1010 | } |
1020 | } | 1011 | } |
1021 | 1012 | ||
1013 | /** | ||
1014 | * et1310_in_phy_coma - check if the device is in phy coma | ||
1015 | * @adapter: pointer to our adapter structure | ||
1016 | * | ||
1017 | * Returns 0 if the device is not in phy coma, 1 if it is in phy coma | ||
1018 | */ | ||
1019 | int et1310_in_phy_coma(struct et131x_adapter *adapter) | ||
1020 | { | ||
1021 | u32 pmcsr; | ||
1022 | |||
1023 | pmcsr = readl(&adapter->regs->global.pm_csr); | ||
1024 | |||
1025 | return ET_PM_PHY_SW_COMA & pmcsr ? 1 : 0; | ||
1026 | } | ||
1027 | |||
1022 | void et1310_setup_device_for_multicast(struct et131x_adapter *adapter) | 1028 | void et1310_setup_device_for_multicast(struct et131x_adapter *adapter) |
1023 | { | 1029 | { |
1024 | struct rxmac_regs __iomem *rxmac = &adapter->regs->rxmac; | 1030 | struct rxmac_regs __iomem *rxmac = &adapter->regs->rxmac; |
@@ -1318,6 +1324,184 @@ void et1310_config_macstat_regs(struct et131x_adapter *adapter) | |||
1318 | writel(0xFFFE7E8B, &macstat->carry_reg2_mask); | 1324 | writel(0xFFFE7E8B, &macstat->carry_reg2_mask); |
1319 | } | 1325 | } |
1320 | 1326 | ||
1327 | /** | ||
1328 | * et131x_phy_mii_read - Read from the PHY through the MII Interface on the MAC | ||
1329 | * @adapter: pointer to our private adapter structure | ||
1330 | * @addr: the address of the transceiver | ||
1331 | * @reg: the register to read | ||
1332 | * @value: pointer to a 16-bit value in which the value will be stored | ||
1333 | * | ||
1334 | * Returns 0 on success, errno on failure (as defined in errno.h) | ||
1335 | */ | ||
1336 | int et131x_phy_mii_read(struct et131x_adapter *adapter, u8 addr, | ||
1337 | u8 reg, u16 *value) | ||
1338 | { | ||
1339 | struct mac_regs __iomem *mac = &adapter->regs->mac; | ||
1340 | int status = 0; | ||
1341 | u32 delay = 0; | ||
1342 | u32 mii_addr; | ||
1343 | u32 mii_cmd; | ||
1344 | u32 mii_indicator; | ||
1345 | |||
1346 | /* Save a local copy of the registers we are dealing with so we can | ||
1347 | * set them back | ||
1348 | */ | ||
1349 | mii_addr = readl(&mac->mii_mgmt_addr); | ||
1350 | mii_cmd = readl(&mac->mii_mgmt_cmd); | ||
1351 | |||
1352 | /* Stop the current operation */ | ||
1353 | writel(0, &mac->mii_mgmt_cmd); | ||
1354 | |||
1355 | /* Set up the register we need to read from on the correct PHY */ | ||
1356 | writel(MII_ADDR(addr, reg), &mac->mii_mgmt_addr); | ||
1357 | |||
1358 | writel(0x1, &mac->mii_mgmt_cmd); | ||
1359 | |||
1360 | do { | ||
1361 | udelay(50); | ||
1362 | delay++; | ||
1363 | mii_indicator = readl(&mac->mii_mgmt_indicator); | ||
1364 | } while ((mii_indicator & MGMT_WAIT) && delay < 50); | ||
1365 | |||
1366 | /* If we hit the max delay, we could not read the register */ | ||
1367 | if (delay == 50) { | ||
1368 | dev_warn(&adapter->pdev->dev, | ||
1369 | "reg 0x%08x could not be read\n", reg); | ||
1370 | dev_warn(&adapter->pdev->dev, "status is 0x%08x\n", | ||
1371 | mii_indicator); | ||
1372 | |||
1373 | status = -EIO; | ||
1374 | } | ||
1375 | |||
1376 | /* If we hit here we were able to read the register and we need to | ||
1377 | * return the value to the caller */ | ||
1378 | *value = readl(&mac->mii_mgmt_stat) & 0xFFFF; | ||
1379 | |||
1380 | /* Stop the read operation */ | ||
1381 | writel(0, &mac->mii_mgmt_cmd); | ||
1382 | |||
1383 | /* set the registers we touched back to the state at which we entered | ||
1384 | * this function | ||
1385 | */ | ||
1386 | writel(mii_addr, &mac->mii_mgmt_addr); | ||
1387 | writel(mii_cmd, &mac->mii_mgmt_cmd); | ||
1388 | |||
1389 | return status; | ||
1390 | } | ||
1391 | |||
1392 | int et131x_mii_read(struct et131x_adapter *adapter, u8 reg, u16 *value) | ||
1393 | { | ||
1394 | struct phy_device *phydev = adapter->phydev; | ||
1395 | |||
1396 | if (!phydev) | ||
1397 | return -EIO; | ||
1398 | |||
1399 | return et131x_phy_mii_read(adapter, phydev->addr, reg, value); | ||
1400 | } | ||
1401 | |||
1402 | /** | ||
1403 | * et131x_mii_write - Write to a PHY register through the MII interface of the MAC | ||
1404 | * @adapter: pointer to our private adapter structure | ||
1405 | * @reg: the register to read | ||
1406 | * @value: 16-bit value to write | ||
1407 | * | ||
1408 | * FIXME: one caller in netdev still | ||
1409 | * | ||
1410 | * Return 0 on success, errno on failure (as defined in errno.h) | ||
1411 | */ | ||
1412 | int et131x_mii_write(struct et131x_adapter *adapter, u8 reg, u16 value) | ||
1413 | { | ||
1414 | struct mac_regs __iomem *mac = &adapter->regs->mac; | ||
1415 | struct phy_device *phydev = adapter->phydev; | ||
1416 | int status = 0; | ||
1417 | u8 addr; | ||
1418 | u32 delay = 0; | ||
1419 | u32 mii_addr; | ||
1420 | u32 mii_cmd; | ||
1421 | u32 mii_indicator; | ||
1422 | |||
1423 | if (!phydev) | ||
1424 | return -EIO; | ||
1425 | |||
1426 | addr = phydev->addr; | ||
1427 | |||
1428 | /* Save a local copy of the registers we are dealing with so we can | ||
1429 | * set them back | ||
1430 | */ | ||
1431 | mii_addr = readl(&mac->mii_mgmt_addr); | ||
1432 | mii_cmd = readl(&mac->mii_mgmt_cmd); | ||
1433 | |||
1434 | /* Stop the current operation */ | ||
1435 | writel(0, &mac->mii_mgmt_cmd); | ||
1436 | |||
1437 | /* Set up the register we need to write to on the correct PHY */ | ||
1438 | writel(MII_ADDR(addr, reg), &mac->mii_mgmt_addr); | ||
1439 | |||
1440 | /* Add the value to write to the registers to the mac */ | ||
1441 | writel(value, &mac->mii_mgmt_ctrl); | ||
1442 | |||
1443 | do { | ||
1444 | udelay(50); | ||
1445 | delay++; | ||
1446 | mii_indicator = readl(&mac->mii_mgmt_indicator); | ||
1447 | } while ((mii_indicator & MGMT_BUSY) && delay < 100); | ||
1448 | |||
1449 | /* If we hit the max delay, we could not write the register */ | ||
1450 | if (delay == 100) { | ||
1451 | u16 tmp; | ||
1452 | |||
1453 | dev_warn(&adapter->pdev->dev, | ||
1454 | "reg 0x%08x could not be written", reg); | ||
1455 | dev_warn(&adapter->pdev->dev, "status is 0x%08x\n", | ||
1456 | mii_indicator); | ||
1457 | dev_warn(&adapter->pdev->dev, "command is 0x%08x\n", | ||
1458 | readl(&mac->mii_mgmt_cmd)); | ||
1459 | |||
1460 | et131x_mii_read(adapter, reg, &tmp); | ||
1461 | |||
1462 | status = -EIO; | ||
1463 | } | ||
1464 | /* Stop the write operation */ | ||
1465 | writel(0, &mac->mii_mgmt_cmd); | ||
1466 | |||
1467 | /* | ||
1468 | * set the registers we touched back to the state at which we entered | ||
1469 | * this function | ||
1470 | */ | ||
1471 | writel(mii_addr, &mac->mii_mgmt_addr); | ||
1472 | writel(mii_cmd, &mac->mii_mgmt_cmd); | ||
1473 | |||
1474 | return status; | ||
1475 | } | ||
1476 | |||
1477 | /* Still used from _mac for BIT_READ */ | ||
1478 | void et1310_phy_access_mii_bit(struct et131x_adapter *adapter, u16 action, | ||
1479 | u16 regnum, u16 bitnum, u8 *value) | ||
1480 | { | ||
1481 | u16 reg; | ||
1482 | u16 mask = 0x0001 << bitnum; | ||
1483 | |||
1484 | /* Read the requested register */ | ||
1485 | et131x_mii_read(adapter, regnum, ®); | ||
1486 | |||
1487 | switch (action) { | ||
1488 | case TRUEPHY_BIT_READ: | ||
1489 | *value = (reg & mask) >> bitnum; | ||
1490 | break; | ||
1491 | |||
1492 | case TRUEPHY_BIT_SET: | ||
1493 | et131x_mii_write(adapter, regnum, reg | mask); | ||
1494 | break; | ||
1495 | |||
1496 | case TRUEPHY_BIT_CLEAR: | ||
1497 | et131x_mii_write(adapter, regnum, reg & ~mask); | ||
1498 | break; | ||
1499 | |||
1500 | default: | ||
1501 | break; | ||
1502 | } | ||
1503 | } | ||
1504 | |||
1321 | void et1310_config_flow_control(struct et131x_adapter *adapter) | 1505 | void et1310_config_flow_control(struct et131x_adapter *adapter) |
1322 | { | 1506 | { |
1323 | struct phy_device *phydev = adapter->phydev; | 1507 | struct phy_device *phydev = adapter->phydev; |
@@ -1476,156 +1660,6 @@ int et131x_mdio_reset(struct mii_bus *bus) | |||
1476 | return 0; | 1660 | return 0; |
1477 | } | 1661 | } |
1478 | 1662 | ||
1479 | int et131x_mii_read(struct et131x_adapter *adapter, u8 reg, u16 *value) | ||
1480 | { | ||
1481 | struct phy_device *phydev = adapter->phydev; | ||
1482 | |||
1483 | if (!phydev) | ||
1484 | return -EIO; | ||
1485 | |||
1486 | return et131x_phy_mii_read(adapter, phydev->addr, reg, value); | ||
1487 | } | ||
1488 | |||
1489 | /** | ||
1490 | * et131x_phy_mii_read - Read from the PHY through the MII Interface on the MAC | ||
1491 | * @adapter: pointer to our private adapter structure | ||
1492 | * @addr: the address of the transceiver | ||
1493 | * @reg: the register to read | ||
1494 | * @value: pointer to a 16-bit value in which the value will be stored | ||
1495 | * | ||
1496 | * Returns 0 on success, errno on failure (as defined in errno.h) | ||
1497 | */ | ||
1498 | int et131x_phy_mii_read(struct et131x_adapter *adapter, u8 addr, | ||
1499 | u8 reg, u16 *value) | ||
1500 | { | ||
1501 | struct mac_regs __iomem *mac = &adapter->regs->mac; | ||
1502 | int status = 0; | ||
1503 | u32 delay = 0; | ||
1504 | u32 mii_addr; | ||
1505 | u32 mii_cmd; | ||
1506 | u32 mii_indicator; | ||
1507 | |||
1508 | /* Save a local copy of the registers we are dealing with so we can | ||
1509 | * set them back | ||
1510 | */ | ||
1511 | mii_addr = readl(&mac->mii_mgmt_addr); | ||
1512 | mii_cmd = readl(&mac->mii_mgmt_cmd); | ||
1513 | |||
1514 | /* Stop the current operation */ | ||
1515 | writel(0, &mac->mii_mgmt_cmd); | ||
1516 | |||
1517 | /* Set up the register we need to read from on the correct PHY */ | ||
1518 | writel(MII_ADDR(addr, reg), &mac->mii_mgmt_addr); | ||
1519 | |||
1520 | writel(0x1, &mac->mii_mgmt_cmd); | ||
1521 | |||
1522 | do { | ||
1523 | udelay(50); | ||
1524 | delay++; | ||
1525 | mii_indicator = readl(&mac->mii_mgmt_indicator); | ||
1526 | } while ((mii_indicator & MGMT_WAIT) && delay < 50); | ||
1527 | |||
1528 | /* If we hit the max delay, we could not read the register */ | ||
1529 | if (delay == 50) { | ||
1530 | dev_warn(&adapter->pdev->dev, | ||
1531 | "reg 0x%08x could not be read\n", reg); | ||
1532 | dev_warn(&adapter->pdev->dev, "status is 0x%08x\n", | ||
1533 | mii_indicator); | ||
1534 | |||
1535 | status = -EIO; | ||
1536 | } | ||
1537 | |||
1538 | /* If we hit here we were able to read the register and we need to | ||
1539 | * return the value to the caller */ | ||
1540 | *value = readl(&mac->mii_mgmt_stat) & 0xFFFF; | ||
1541 | |||
1542 | /* Stop the read operation */ | ||
1543 | writel(0, &mac->mii_mgmt_cmd); | ||
1544 | |||
1545 | /* set the registers we touched back to the state at which we entered | ||
1546 | * this function | ||
1547 | */ | ||
1548 | writel(mii_addr, &mac->mii_mgmt_addr); | ||
1549 | writel(mii_cmd, &mac->mii_mgmt_cmd); | ||
1550 | |||
1551 | return status; | ||
1552 | } | ||
1553 | |||
1554 | /** | ||
1555 | * et131x_mii_write - Write to a PHY register through the MII interface of the MAC | ||
1556 | * @adapter: pointer to our private adapter structure | ||
1557 | * @reg: the register to read | ||
1558 | * @value: 16-bit value to write | ||
1559 | * | ||
1560 | * FIXME: one caller in netdev still | ||
1561 | * | ||
1562 | * Return 0 on success, errno on failure (as defined in errno.h) | ||
1563 | */ | ||
1564 | int et131x_mii_write(struct et131x_adapter *adapter, u8 reg, u16 value) | ||
1565 | { | ||
1566 | struct mac_regs __iomem *mac = &adapter->regs->mac; | ||
1567 | struct phy_device *phydev = adapter->phydev; | ||
1568 | int status = 0; | ||
1569 | u8 addr; | ||
1570 | u32 delay = 0; | ||
1571 | u32 mii_addr; | ||
1572 | u32 mii_cmd; | ||
1573 | u32 mii_indicator; | ||
1574 | |||
1575 | if (!phydev) | ||
1576 | return -EIO; | ||
1577 | |||
1578 | addr = phydev->addr; | ||
1579 | |||
1580 | /* Save a local copy of the registers we are dealing with so we can | ||
1581 | * set them back | ||
1582 | */ | ||
1583 | mii_addr = readl(&mac->mii_mgmt_addr); | ||
1584 | mii_cmd = readl(&mac->mii_mgmt_cmd); | ||
1585 | |||
1586 | /* Stop the current operation */ | ||
1587 | writel(0, &mac->mii_mgmt_cmd); | ||
1588 | |||
1589 | /* Set up the register we need to write to on the correct PHY */ | ||
1590 | writel(MII_ADDR(addr, reg), &mac->mii_mgmt_addr); | ||
1591 | |||
1592 | /* Add the value to write to the registers to the mac */ | ||
1593 | writel(value, &mac->mii_mgmt_ctrl); | ||
1594 | |||
1595 | do { | ||
1596 | udelay(50); | ||
1597 | delay++; | ||
1598 | mii_indicator = readl(&mac->mii_mgmt_indicator); | ||
1599 | } while ((mii_indicator & MGMT_BUSY) && delay < 100); | ||
1600 | |||
1601 | /* If we hit the max delay, we could not write the register */ | ||
1602 | if (delay == 100) { | ||
1603 | u16 tmp; | ||
1604 | |||
1605 | dev_warn(&adapter->pdev->dev, | ||
1606 | "reg 0x%08x could not be written", reg); | ||
1607 | dev_warn(&adapter->pdev->dev, "status is 0x%08x\n", | ||
1608 | mii_indicator); | ||
1609 | dev_warn(&adapter->pdev->dev, "command is 0x%08x\n", | ||
1610 | readl(&mac->mii_mgmt_cmd)); | ||
1611 | |||
1612 | et131x_mii_read(adapter, reg, &tmp); | ||
1613 | |||
1614 | status = -EIO; | ||
1615 | } | ||
1616 | /* Stop the write operation */ | ||
1617 | writel(0, &mac->mii_mgmt_cmd); | ||
1618 | |||
1619 | /* | ||
1620 | * set the registers we touched back to the state at which we entered | ||
1621 | * this function | ||
1622 | */ | ||
1623 | writel(mii_addr, &mac->mii_mgmt_addr); | ||
1624 | writel(mii_cmd, &mac->mii_mgmt_cmd); | ||
1625 | |||
1626 | return status; | ||
1627 | } | ||
1628 | |||
1629 | /** | 1663 | /** |
1630 | * et1310_phy_power_down - PHY power control | 1664 | * et1310_phy_power_down - PHY power control |
1631 | * @adapter: device to control | 1665 | * @adapter: device to control |
@@ -1647,34 +1681,6 @@ void et1310_phy_power_down(struct et131x_adapter *adapter, bool down) | |||
1647 | et131x_mii_write(adapter, MII_BMCR, data); | 1681 | et131x_mii_write(adapter, MII_BMCR, data); |
1648 | } | 1682 | } |
1649 | 1683 | ||
1650 | /* Still used from _mac for BIT_READ */ | ||
1651 | void et1310_phy_access_mii_bit(struct et131x_adapter *adapter, u16 action, | ||
1652 | u16 regnum, u16 bitnum, u8 *value) | ||
1653 | { | ||
1654 | u16 reg; | ||
1655 | u16 mask = 0x0001 << bitnum; | ||
1656 | |||
1657 | /* Read the requested register */ | ||
1658 | et131x_mii_read(adapter, regnum, ®); | ||
1659 | |||
1660 | switch (action) { | ||
1661 | case TRUEPHY_BIT_READ: | ||
1662 | *value = (reg & mask) >> bitnum; | ||
1663 | break; | ||
1664 | |||
1665 | case TRUEPHY_BIT_SET: | ||
1666 | et131x_mii_write(adapter, regnum, reg | mask); | ||
1667 | break; | ||
1668 | |||
1669 | case TRUEPHY_BIT_CLEAR: | ||
1670 | et131x_mii_write(adapter, regnum, reg & ~mask); | ||
1671 | break; | ||
1672 | |||
1673 | default: | ||
1674 | break; | ||
1675 | } | ||
1676 | } | ||
1677 | |||
1678 | /** | 1684 | /** |
1679 | * et131x_xcvr_init - Init the phy if we are setting it into force mode | 1685 | * et131x_xcvr_init - Init the phy if we are setting it into force mode |
1680 | * @adapter: pointer to our private adapter structure | 1686 | * @adapter: pointer to our private adapter structure |
@@ -1771,21 +1777,6 @@ void et131x_configure_global_regs(struct et131x_adapter *adapter) | |||
1771 | /* PM functions */ | 1777 | /* PM functions */ |
1772 | 1778 | ||
1773 | /** | 1779 | /** |
1774 | * et1310_in_phy_coma - check if the device is in phy coma | ||
1775 | * @adapter: pointer to our adapter structure | ||
1776 | * | ||
1777 | * Returns 0 if the device is not in phy coma, 1 if it is in phy coma | ||
1778 | */ | ||
1779 | int et1310_in_phy_coma(struct et131x_adapter *adapter) | ||
1780 | { | ||
1781 | u32 pmcsr; | ||
1782 | |||
1783 | pmcsr = readl(&adapter->regs->global.pm_csr); | ||
1784 | |||
1785 | return ET_PM_PHY_SW_COMA & pmcsr ? 1 : 0; | ||
1786 | } | ||
1787 | |||
1788 | /** | ||
1789 | * et131x_config_rx_dma_regs - Start of Rx_DMA init sequence | 1780 | * et131x_config_rx_dma_regs - Start of Rx_DMA init sequence |
1790 | * @adapter: pointer to our adapter structure | 1781 | * @adapter: pointer to our adapter structure |
1791 | */ | 1782 | */ |