Merge git://git.kernel.org/pub/scm/linux/kernel/git/davem/net-2.6

* git://git.kernel.org/pub/scm/linux/kernel/git/davem/net-2.6: (37 commits)
  [NETFILTER]: fix ebtable targets return
  [IP_TUNNEL]: Don't limit the number of tunnels with generic name explicitly.
  [NET]: Restore sanity wrt. print_mac().
  [NEIGH]: Fix race between neighbor lookup and table's hash_rnd update.
  [RTNL]: Validate hardware and broadcast address attribute for RTM_NEWLINK
  tg3: ethtool phys_id default
  [BNX2]: Update version to 1.7.4.
  [BNX2]: Disable parallel detect on an HP blade.
  [BNX2]: More 5706S link down workaround.
  ssb: Fix support for PCI devices behind a SSB->PCI bridge
  zd1211rw: fix sparse warnings
  rtl818x: fix sparse warnings
  ssb: Fix pcicore cardbus mode
  ssb: Make the GPIO API reentrancy safe
  ssb: Fix the GPIO API
  ssb: Fix watchdog access for devices without a chipcommon
  ssb: Fix serial console on new bcm47xx devices
  ath5k: Fix build warnings on some 64-bit platforms.
  WDEV, ath5k, don't return int from bool function
  WDEV: ath5k, fix lock imbalance
  ...

7 files changed, 256 insertions, 22 deletions

diff --git a/drivers/ssb/Kconfig b/drivers/ssb/Kconfig
index d976660cb7f0..78fd33125e02 100644
--- a/drivers/ssb/Kconfig
+++ b/drivers/ssb/Kconfig
@@ -105,6 +105,12 @@ config SSB_DRIVER_MIPS
 
           If unsure, say N
 
+# Assumption: We are on embedded, if we compile the MIPS core.
+config SSB_EMBEDDED
+        bool
+        depends on SSB_DRIVER_MIPS
+        default y
+
 config SSB_DRIVER_EXTIF
         bool "SSB Broadcom EXTIF core driver (EXPERIMENTAL)"
         depends on SSB_DRIVER_MIPS && EXPERIMENTAL
diff --git a/drivers/ssb/Makefile b/drivers/ssb/Makefile
index 7be397595805..e235144add7c 100644
--- a/drivers/ssb/Makefile
+++ b/drivers/ssb/Makefile
@@ -1,5 +1,6 @@
 # core
 ssb-y                                   += main.o scan.o
+ssb-$(CONFIG_SSB_EMBEDDED)              += embedded.o
 
 # host support
 ssb-$(CONFIG_SSB_PCIHOST)               += pci.o pcihost_wrapper.o
diff --git a/drivers/ssb/driver_chipcommon.c b/drivers/ssb/driver_chipcommon.c
index 6fbf1c53b6f2..e586321a473a 100644
--- a/drivers/ssb/driver_chipcommon.c
+++ b/drivers/ssb/driver_chipcommon.c
@@ -39,12 +39,14 @@ static inline void chipco_write32(struct ssb_chipcommon *cc,
         ssb_write32(cc->dev, offset, value);
 }
 
-static inline void chipco_write32_masked(struct ssb_chipcommon *cc, u16 offset,
-                                         u32 mask, u32 value)
+static inline u32 chipco_write32_masked(struct ssb_chipcommon *cc, u16 offset,
+                                        u32 mask, u32 value)
 {
         value &= mask;
         value |= chipco_read32(cc, offset) & ~mask;
         chipco_write32(cc, offset, value);
+
+        return value;
 }
 
 void ssb_chipco_set_clockmode(struct ssb_chipcommon *cc,
@@ -356,14 +358,29 @@ u32 ssb_chipco_gpio_in(struct ssb_chipcommon *cc, u32 mask)
         return chipco_read32(cc, SSB_CHIPCO_GPIOIN) & mask;
 }
 
-void ssb_chipco_gpio_out(struct ssb_chipcommon *cc, u32 mask, u32 value)
+u32 ssb_chipco_gpio_out(struct ssb_chipcommon *cc, u32 mask, u32 value)
+{
+        return chipco_write32_masked(cc, SSB_CHIPCO_GPIOOUT, mask, value);
+}
+
+u32 ssb_chipco_gpio_outen(struct ssb_chipcommon *cc, u32 mask, u32 value)
+{
+        return chipco_write32_masked(cc, SSB_CHIPCO_GPIOOUTEN, mask, value);
+}
+
+u32 ssb_chipco_gpio_control(struct ssb_chipcommon *cc, u32 mask, u32 value)
+{
+        return chipco_write32_masked(cc, SSB_CHIPCO_GPIOCTL, mask, value);
+}
+
+u32 ssb_chipco_gpio_intmask(struct ssb_chipcommon *cc, u32 mask, u32 value)
 {
-        chipco_write32_masked(cc, SSB_CHIPCO_GPIOOUT, mask, value);
+        return chipco_write32_masked(cc, SSB_CHIPCO_GPIOIRQ, mask, value);
 }
 
-void ssb_chipco_gpio_outen(struct ssb_chipcommon *cc, u32 mask, u32 value)
+u32 ssb_chipco_gpio_polarity(struct ssb_chipcommon *cc, u32 mask, u32 value)
 {
-        chipco_write32_masked(cc, SSB_CHIPCO_GPIOOUTEN, mask, value);
+        return chipco_write32_masked(cc, SSB_CHIPCO_GPIOPOL, mask, value);
 }
 
 #ifdef CONFIG_SSB_SERIAL
@@ -376,6 +393,7 @@ int ssb_chipco_serial_init(struct ssb_chipcommon *cc,
         unsigned int irq;
         u32 baud_base, div;
         u32 i, n;
+        unsigned int ccrev = cc->dev->id.revision;
 
         plltype = (cc->capabilities & SSB_CHIPCO_CAP_PLLT);
         irq = ssb_mips_irq(cc->dev);
@@ -387,14 +405,39 @@ int ssb_chipco_serial_init(struct ssb_chipcommon *cc,
                                                 chipco_read32(cc, SSB_CHIPCO_CLOCK_M2));
                 div = 1;
         } else {
-                if (cc->dev->id.revision >= 11) {
+                if (ccrev == 20) {
+                        /* BCM5354 uses constant 25MHz clock */
+                        baud_base = 25000000;
+                        div = 48;
+                        /* Set the override bit so we don't divide it */
+                        chipco_write32(cc, SSB_CHIPCO_CORECTL,
+                                       chipco_read32(cc, SSB_CHIPCO_CORECTL)
+                                       | SSB_CHIPCO_CORECTL_UARTCLK0);
+                } else if ((ccrev >= 11) && (ccrev != 15)) {
                         /* Fixed ALP clock */
                         baud_base = 20000000;
+                        if (cc->capabilities & SSB_CHIPCO_CAP_PMU) {
+                                /* FIXME: baud_base is different for devices with a PMU */
+                                SSB_WARN_ON(1);
+                        }
                         div = 1;
+                        if (ccrev >= 21) {
+                                /* Turn off UART clock before switching clocksource. */
+                                chipco_write32(cc, SSB_CHIPCO_CORECTL,
+                                               chipco_read32(cc, SSB_CHIPCO_CORECTL)
+                                               & ~SSB_CHIPCO_CORECTL_UARTCLKEN);
+                        }
                         /* Set the override bit so we don't divide it */
                         chipco_write32(cc, SSB_CHIPCO_CORECTL,
-                                       SSB_CHIPCO_CORECTL_UARTCLK0);
-                } else if (cc->dev->id.revision >= 3) {
+                                       chipco_read32(cc, SSB_CHIPCO_CORECTL)
+                                       | SSB_CHIPCO_CORECTL_UARTCLK0);
+                        if (ccrev >= 21) {
+                                /* Re-enable the UART clock. */
+                                chipco_write32(cc, SSB_CHIPCO_CORECTL,
+                                               chipco_read32(cc, SSB_CHIPCO_CORECTL)
+                                               | SSB_CHIPCO_CORECTL_UARTCLKEN);
+                        }
+                } else if (ccrev >= 3) {
                         /* Internal backplane clock */
                         baud_base = ssb_clockspeed(bus);
                         div = chipco_read32(cc, SSB_CHIPCO_CLKDIV)
@@ -406,7 +449,7 @@ int ssb_chipco_serial_init(struct ssb_chipcommon *cc,
                 }
 
                 /* Clock source depends on strapping if UartClkOverride is unset */
-                if ((cc->dev->id.revision > 0) &&
+                if ((ccrev > 0) &&
                     !(chipco_read32(cc, SSB_CHIPCO_CORECTL) & SSB_CHIPCO_CORECTL_UARTCLK0)) {
                         if ((cc->capabilities & SSB_CHIPCO_CAP_UARTCLK) ==
                             SSB_CHIPCO_CAP_UARTCLK_INT) {
@@ -428,7 +471,7 @@ int ssb_chipco_serial_init(struct ssb_chipcommon *cc,
                 cc_mmio = cc->dev->bus->mmio + (cc->dev->core_index * SSB_CORE_SIZE);
                 uart_regs = cc_mmio + SSB_CHIPCO_UART0_DATA;
                 /* Offset changed at after rev 0 */
-                if (cc->dev->id.revision == 0)
+                if (ccrev == 0)
                         uart_regs += (i * 8);
                 else
                         uart_regs += (i * 256);
diff --git a/drivers/ssb/driver_extif.c b/drivers/ssb/driver_extif.c
index fe55eb8b038a..c3e1d3e6d610 100644
--- a/drivers/ssb/driver_extif.c
+++ b/drivers/ssb/driver_extif.c
@@ -27,12 +27,14 @@ static inline void extif_write32(struct ssb_extif *extif, u16 offset, u32 value)
         ssb_write32(extif->dev, offset, value);
 }
 
-static inline void extif_write32_masked(struct ssb_extif *extif, u16 offset,
-                                        u32 mask, u32 value)
+static inline u32 extif_write32_masked(struct ssb_extif *extif, u16 offset,
+                                       u32 mask, u32 value)
 {
         value &= mask;
         value |= extif_read32(extif, offset) & ~mask;
         extif_write32(extif, offset, value);
+
+        return value;
 }
 
 #ifdef CONFIG_SSB_SERIAL
@@ -110,20 +112,35 @@ void ssb_extif_get_clockcontrol(struct ssb_extif *extif,
         *m = extif_read32(extif, SSB_EXTIF_CLOCK_SB);
 }
 
+void ssb_extif_watchdog_timer_set(struct ssb_extif *extif,
+                                  u32 ticks)
+{
+        extif_write32(extif, SSB_EXTIF_WATCHDOG, ticks);
+}
+
 u32 ssb_extif_gpio_in(struct ssb_extif *extif, u32 mask)
 {
         return extif_read32(extif, SSB_EXTIF_GPIO_IN) & mask;
 }
 
-void ssb_extif_gpio_out(struct ssb_extif *extif, u32 mask, u32 value)
+u32 ssb_extif_gpio_out(struct ssb_extif *extif, u32 mask, u32 value)
 {
         return extif_write32_masked(extif, SSB_EXTIF_GPIO_OUT(0),
                                    mask, value);
 }
 
-void ssb_extif_gpio_outen(struct ssb_extif *extif, u32 mask, u32 value)
+u32 ssb_extif_gpio_outen(struct ssb_extif *extif, u32 mask, u32 value)
 {
         return extif_write32_masked(extif, SSB_EXTIF_GPIO_OUTEN(0),
                                    mask, value);
 }
 
+u32 ssb_extif_gpio_polarity(struct ssb_extif *extif, u32 mask, u32 value)
+{
+        return extif_write32_masked(extif, SSB_EXTIF_GPIO_INTPOL, mask, value);
+}
+
+u32 ssb_extif_gpio_intmask(struct ssb_extif *extif, u32 mask, u32 value)
+{
+        return extif_write32_masked(extif, SSB_EXTIF_GPIO_INTMASK, mask, value);
+}
diff --git a/drivers/ssb/driver_pcicore.c b/drivers/ssb/driver_pcicore.c
index 2faaa906d5d6..6d99a9880055 100644
--- a/drivers/ssb/driver_pcicore.c
+++ b/drivers/ssb/driver_pcicore.c
@@ -11,6 +11,7 @@
 #include <linux/ssb/ssb.h>
 #include <linux/pci.h>
 #include <linux/delay.h>
+#include <linux/ssb/ssb_embedded.h>
 
 #include "ssb_private.h"
 
@@ -27,6 +28,18 @@ void pcicore_write32(struct ssb_pcicore *pc, u16 offset, u32 value)
         ssb_write32(pc->dev, offset, value);
 }
 
+static inline
+u16 pcicore_read16(struct ssb_pcicore *pc, u16 offset)
+{
+        return ssb_read16(pc->dev, offset);
+}
+
+static inline
+void pcicore_write16(struct ssb_pcicore *pc, u16 offset, u16 value)
+{
+        ssb_write16(pc->dev, offset, value);
+}
+
 /**************************************************
  * Code for hostmode operation.
  **************************************************/
@@ -66,6 +79,7 @@ int pcibios_plat_dev_init(struct pci_dev *d)
                         base = &ssb_pcicore_pcibus_iobase;
                 else
                         base = &ssb_pcicore_pcibus_membase;
+                res->flags |= IORESOURCE_PCI_FIXED;
                 if (res->end) {
                         size = res->end - res->start + 1;
                         if (*base & (size - 1))
@@ -88,10 +102,12 @@ int pcibios_plat_dev_init(struct pci_dev *d)
 
 static void __init ssb_fixup_pcibridge(struct pci_dev *dev)
 {
+        u8 lat;
+
         if (dev->bus->number != 0 || PCI_SLOT(dev->devfn) != 0)
                 return;
 
-        ssb_printk(KERN_INFO "PCI: fixing up bridge\n");
+        ssb_printk(KERN_INFO "PCI: Fixing up bridge %s\n", pci_name(dev));
 
         /* Enable PCI bridge bus mastering and memory space */
         pci_set_master(dev);
@@ -101,7 +117,10 @@ static void __init ssb_fixup_pcibridge(struct pci_dev *dev)
         pci_write_config_dword(dev, SSB_BAR1_CONTROL, 3);
 
         /* Make sure our latency is high enough to handle the devices behind us */
-        pci_write_config_byte(dev, PCI_LATENCY_TIMER, 0xa8);
+        lat = 168;
+        ssb_printk(KERN_INFO "PCI: Fixing latency timer of device %s to %u\n",
+                   pci_name(dev), lat);
+        pci_write_config_byte(dev, PCI_LATENCY_TIMER, lat);
 }
 DECLARE_PCI_FIXUP_EARLY(PCI_ANY_ID, PCI_ANY_ID, ssb_fixup_pcibridge);
 
@@ -117,8 +136,10 @@ static u32 get_cfgspace_addr(struct ssb_pcicore *pc,
         u32 addr = 0;
         u32 tmp;
 
-        if (unlikely(pc->cardbusmode && dev > 1))
+        /* We do only have one cardbus device behind the bridge. */
+        if (pc->cardbusmode && (dev >= 1))
                 goto out;
+
         if (bus == 0) {
                 /* Type 0 transaction */
                 if (unlikely(dev >= SSB_PCI_SLOT_MAX))
@@ -279,14 +300,14 @@ static struct resource ssb_pcicore_mem_resource = {
         .name   = "SSB PCIcore external memory",
         .start  = SSB_PCI_DMA,
         .end    = SSB_PCI_DMA + SSB_PCI_DMA_SZ - 1,
-        .flags  = IORESOURCE_MEM,
+        .flags  = IORESOURCE_MEM | IORESOURCE_PCI_FIXED,
 };
 
 static struct resource ssb_pcicore_io_resource = {
         .name   = "SSB PCIcore external I/O",
         .start  = 0x100,
         .end    = 0x7FF,
-        .flags  = IORESOURCE_IO,
+        .flags  = IORESOURCE_IO | IORESOURCE_PCI_FIXED,
 };
 
 static struct pci_controller ssb_pcicore_controller = {
@@ -318,7 +339,16 @@ static void ssb_pcicore_init_hostmode(struct ssb_pcicore *pc)
         pcicore_write32(pc, SSB_PCICORE_ARBCTL, val);
         udelay(1); /* Assertion time demanded by the PCI standard */
 
-        /*TODO cardbus mode */
+        if (pc->dev->bus->has_cardbus_slot) {
+                ssb_dprintk(KERN_INFO PFX "CardBus slot detected\n");
+                pc->cardbusmode = 1;
+                /* GPIO 1 resets the bridge */
+                ssb_gpio_out(pc->dev->bus, 1, 1);
+                ssb_gpio_outen(pc->dev->bus, 1, 1);
+                pcicore_write16(pc, SSB_PCICORE_SPROM(0),
+                                pcicore_read16(pc, SSB_PCICORE_SPROM(0))
+                                | 0x0400);
+        }
 
         /* 64MB I/O window */
         pcicore_write32(pc, SSB_PCICORE_SBTOPCI0,
@@ -344,7 +374,8 @@ static void ssb_pcicore_init_hostmode(struct ssb_pcicore *pc)
         /* Ok, ready to run, register it to the system.
          * The following needs change, if we want to port hostmode
          * to non-MIPS platform. */
-        set_io_port_base((unsigned long)ioremap_nocache(SSB_PCI_MEM, 0x04000000));
+        ssb_pcicore_controller.io_map_base = (unsigned long)ioremap_nocache(SSB_PCI_MEM, 0x04000000);
+        set_io_port_base(ssb_pcicore_controller.io_map_base);
         /* Give some time to the PCI controller to configure itself with the new
          * values. Not waiting at this point causes crashes of the machine. */
         mdelay(10);
diff --git a/drivers/ssb/embedded.c b/drivers/ssb/embedded.c
new file mode 100644
index 000000000000..d3ade821555c
--- /dev/null
+++ b/drivers/ssb/embedded.c
@@ -0,0 +1,132 @@
+/*
+ * Sonics Silicon Backplane
+ * Embedded systems support code
+ *
+ * Copyright 2005-2008, Broadcom Corporation
+ * Copyright 2006-2008, Michael Buesch <mb@bu3sch.de>
+ *
+ * Licensed under the GNU/GPL. See COPYING for details.
+ */
+
+#include <linux/ssb/ssb.h>
+#include <linux/ssb/ssb_embedded.h>
+
+#include "ssb_private.h"
+
+
+int ssb_watchdog_timer_set(struct ssb_bus *bus, u32 ticks)
+{
+        if (ssb_chipco_available(&bus->chipco)) {
+                ssb_chipco_watchdog_timer_set(&bus->chipco, ticks);
+                return 0;
+        }
+        if (ssb_extif_available(&bus->extif)) {
+                ssb_extif_watchdog_timer_set(&bus->extif, ticks);
+                return 0;
+        }
+        return -ENODEV;
+}
+
+u32 ssb_gpio_in(struct ssb_bus *bus, u32 mask)
+{
+        unsigned long flags;
+        u32 res = 0;
+
+        spin_lock_irqsave(&bus->gpio_lock, flags);
+        if (ssb_chipco_available(&bus->chipco))
+                res = ssb_chipco_gpio_in(&bus->chipco, mask);
+        else if (ssb_extif_available(&bus->extif))
+                res = ssb_extif_gpio_in(&bus->extif, mask);
+        else
+                SSB_WARN_ON(1);
+        spin_unlock_irqrestore(&bus->gpio_lock, flags);
+
+        return res;
+}
+EXPORT_SYMBOL(ssb_gpio_in);
+
+u32 ssb_gpio_out(struct ssb_bus *bus, u32 mask, u32 value)
+{
+        unsigned long flags;
+        u32 res = 0;
+
+        spin_lock_irqsave(&bus->gpio_lock, flags);
+        if (ssb_chipco_available(&bus->chipco))
+                res = ssb_chipco_gpio_out(&bus->chipco, mask, value);
+        else if (ssb_extif_available(&bus->extif))
+                res = ssb_extif_gpio_out(&bus->extif, mask, value);
+        else
+                SSB_WARN_ON(1);
+        spin_unlock_irqrestore(&bus->gpio_lock, flags);
+
+        return res;
+}
+EXPORT_SYMBOL(ssb_gpio_out);
+
+u32 ssb_gpio_outen(struct ssb_bus *bus, u32 mask, u32 value)
+{
+        unsigned long flags;
+        u32 res = 0;
+
+        spin_lock_irqsave(&bus->gpio_lock, flags);
+        if (ssb_chipco_available(&bus->chipco))
+                res = ssb_chipco_gpio_outen(&bus->chipco, mask, value);
+        else if (ssb_extif_available(&bus->extif))
+                res = ssb_extif_gpio_outen(&bus->extif, mask, value);
+        else
+                SSB_WARN_ON(1);
+        spin_unlock_irqrestore(&bus->gpio_lock, flags);
+
+        return res;
+}
+EXPORT_SYMBOL(ssb_gpio_outen);
+
+u32 ssb_gpio_control(struct ssb_bus *bus, u32 mask, u32 value)
+{
+        unsigned long flags;
+        u32 res = 0;
+
+        spin_lock_irqsave(&bus->gpio_lock, flags);
+        if (ssb_chipco_available(&bus->chipco))
+                res = ssb_chipco_gpio_control(&bus->chipco, mask, value);
+        spin_unlock_irqrestore(&bus->gpio_lock, flags);
+
+        return res;
+}
+EXPORT_SYMBOL(ssb_gpio_control);
+
+u32 ssb_gpio_intmask(struct ssb_bus *bus, u32 mask, u32 value)
+{
+        unsigned long flags;
+        u32 res = 0;
+
+        spin_lock_irqsave(&bus->gpio_lock, flags);
+        if (ssb_chipco_available(&bus->chipco))
+                res = ssb_chipco_gpio_intmask(&bus->chipco, mask, value);
+        else if (ssb_extif_available(&bus->extif))
+                res = ssb_extif_gpio_intmask(&bus->extif, mask, value);
+        else
+                SSB_WARN_ON(1);
+        spin_unlock_irqrestore(&bus->gpio_lock, flags);
+
+        return res;
+}
+EXPORT_SYMBOL(ssb_gpio_intmask);
+
+u32 ssb_gpio_polarity(struct ssb_bus *bus, u32 mask, u32 value)
+{
+        unsigned long flags;
+        u32 res = 0;
+
+        spin_lock_irqsave(&bus->gpio_lock, flags);
+        if (ssb_chipco_available(&bus->chipco))
+                res = ssb_chipco_gpio_polarity(&bus->chipco, mask, value);
+        else if (ssb_extif_available(&bus->extif))
+                res = ssb_extif_gpio_polarity(&bus->extif, mask, value);
+        else
+                SSB_WARN_ON(1);
+        spin_unlock_irqrestore(&bus->gpio_lock, flags);
+
+        return res;
+}
+EXPORT_SYMBOL(ssb_gpio_polarity);
diff --git a/drivers/ssb/main.c b/drivers/ssb/main.c
index 9028ed5715a1..bedb2b4ee9d2 100644
--- a/drivers/ssb/main.c
+++ b/drivers/ssb/main.c
@@ -557,6 +557,7 @@ static int ssb_fetch_invariants(struct ssb_bus *bus,
                 goto out;
         memcpy(&bus->boardinfo, &iv.boardinfo, sizeof(iv.boardinfo));
         memcpy(&bus->sprom, &iv.sprom, sizeof(iv.sprom));
+        bus->has_cardbus_slot = iv.has_cardbus_slot;
 out:
         return err;
 }
@@ -569,6 +570,9 @@ static int ssb_bus_register(struct ssb_bus *bus,
 
         spin_lock_init(&bus->bar_lock);
         INIT_LIST_HEAD(&bus->list);
+#ifdef CONFIG_SSB_EMBEDDED
+        spin_lock_init(&bus->gpio_lock);
+#endif
 
         /* Powerup the bus */
         err = ssb_pci_xtal(bus, SSB_GPIO_XTAL | SSB_GPIO_PLL, 1);