diff options
author | Victor Kamensky <victor.kamensky@linaro.org> | 2013-11-15 19:01:16 -0500 |
---|---|---|
committer | Mark Brown <broonie@linaro.org> | 2013-11-24 09:06:45 -0500 |
commit | 21b2ce5e992f274c9cc45710d29aec11c8b5599a (patch) | |
tree | 211ed601bf5dcf7ed87e25912406f32c0b702dea /drivers/spi | |
parent | 6ce4eac1f600b34f2f7f58f9cd8f0503d79e42ae (diff) |
spi: omap2-mcspi: raw read and write endian fix
All OMAP IP blocks expect LE data, but CPU may operate in BE mode.
Need to use endian neutral functions to read/write h/w registers.
I.e instead of __raw_read[lw] and __raw_write[lw] functions code
need to use read[lw]_relaxed and write[lw]_relaxed functions.
If the first simply reads/writes register, the second will byteswap
it if host operates in BE mode.
Changes are trivial sed like replacement of __raw_xxx functions
with xxx_relaxed variant.
Signed-off-by: Victor Kamensky <victor.kamensky@linaro.org>
Signed-off-by: Taras Kondratiuk <taras.kondratiuk@linaro.org>
Signed-off-by: Mark Brown <broonie@linaro.org>
Diffstat (limited to 'drivers/spi')
-rw-r--r-- | drivers/spi/spi-omap2-mcspi.c | 38 |
1 files changed, 19 insertions, 19 deletions
diff --git a/drivers/spi/spi-omap2-mcspi.c b/drivers/spi/spi-omap2-mcspi.c index 443df39840bc..a72127f08e39 100644 --- a/drivers/spi/spi-omap2-mcspi.c +++ b/drivers/spi/spi-omap2-mcspi.c | |||
@@ -157,14 +157,14 @@ static inline void mcspi_write_reg(struct spi_master *master, | |||
157 | { | 157 | { |
158 | struct omap2_mcspi *mcspi = spi_master_get_devdata(master); | 158 | struct omap2_mcspi *mcspi = spi_master_get_devdata(master); |
159 | 159 | ||
160 | __raw_writel(val, mcspi->base + idx); | 160 | writel_relaxed(val, mcspi->base + idx); |
161 | } | 161 | } |
162 | 162 | ||
163 | static inline u32 mcspi_read_reg(struct spi_master *master, int idx) | 163 | static inline u32 mcspi_read_reg(struct spi_master *master, int idx) |
164 | { | 164 | { |
165 | struct omap2_mcspi *mcspi = spi_master_get_devdata(master); | 165 | struct omap2_mcspi *mcspi = spi_master_get_devdata(master); |
166 | 166 | ||
167 | return __raw_readl(mcspi->base + idx); | 167 | return readl_relaxed(mcspi->base + idx); |
168 | } | 168 | } |
169 | 169 | ||
170 | static inline void mcspi_write_cs_reg(const struct spi_device *spi, | 170 | static inline void mcspi_write_cs_reg(const struct spi_device *spi, |
@@ -172,14 +172,14 @@ static inline void mcspi_write_cs_reg(const struct spi_device *spi, | |||
172 | { | 172 | { |
173 | struct omap2_mcspi_cs *cs = spi->controller_state; | 173 | struct omap2_mcspi_cs *cs = spi->controller_state; |
174 | 174 | ||
175 | __raw_writel(val, cs->base + idx); | 175 | writel_relaxed(val, cs->base + idx); |
176 | } | 176 | } |
177 | 177 | ||
178 | static inline u32 mcspi_read_cs_reg(const struct spi_device *spi, int idx) | 178 | static inline u32 mcspi_read_cs_reg(const struct spi_device *spi, int idx) |
179 | { | 179 | { |
180 | struct omap2_mcspi_cs *cs = spi->controller_state; | 180 | struct omap2_mcspi_cs *cs = spi->controller_state; |
181 | 181 | ||
182 | return __raw_readl(cs->base + idx); | 182 | return readl_relaxed(cs->base + idx); |
183 | } | 183 | } |
184 | 184 | ||
185 | static inline u32 mcspi_cached_chconf0(const struct spi_device *spi) | 185 | static inline u32 mcspi_cached_chconf0(const struct spi_device *spi) |
@@ -338,7 +338,7 @@ static void omap2_mcspi_restore_ctx(struct omap2_mcspi *mcspi) | |||
338 | mcspi_write_reg(spi_cntrl, OMAP2_MCSPI_WAKEUPENABLE, ctx->wakeupenable); | 338 | mcspi_write_reg(spi_cntrl, OMAP2_MCSPI_WAKEUPENABLE, ctx->wakeupenable); |
339 | 339 | ||
340 | list_for_each_entry(cs, &ctx->cs, node) | 340 | list_for_each_entry(cs, &ctx->cs, node) |
341 | __raw_writel(cs->chconf0, cs->base + OMAP2_MCSPI_CHCONF0); | 341 | writel_relaxed(cs->chconf0, cs->base + OMAP2_MCSPI_CHCONF0); |
342 | } | 342 | } |
343 | 343 | ||
344 | static int mcspi_wait_for_reg_bit(void __iomem *reg, unsigned long bit) | 344 | static int mcspi_wait_for_reg_bit(void __iomem *reg, unsigned long bit) |
@@ -346,9 +346,9 @@ static int mcspi_wait_for_reg_bit(void __iomem *reg, unsigned long bit) | |||
346 | unsigned long timeout; | 346 | unsigned long timeout; |
347 | 347 | ||
348 | timeout = jiffies + msecs_to_jiffies(1000); | 348 | timeout = jiffies + msecs_to_jiffies(1000); |
349 | while (!(__raw_readl(reg) & bit)) { | 349 | while (!(readl_relaxed(reg) & bit)) { |
350 | if (time_after(jiffies, timeout)) { | 350 | if (time_after(jiffies, timeout)) { |
351 | if (!(__raw_readl(reg) & bit)) | 351 | if (!(readl_relaxed(reg) & bit)) |
352 | return -ETIMEDOUT; | 352 | return -ETIMEDOUT; |
353 | else | 353 | else |
354 | return 0; | 354 | return 0; |
@@ -675,7 +675,7 @@ omap2_mcspi_txrx_pio(struct spi_device *spi, struct spi_transfer *xfer) | |||
675 | } | 675 | } |
676 | dev_vdbg(&spi->dev, "write-%d %02x\n", | 676 | dev_vdbg(&spi->dev, "write-%d %02x\n", |
677 | word_len, *tx); | 677 | word_len, *tx); |
678 | __raw_writel(*tx++, tx_reg); | 678 | writel_relaxed(*tx++, tx_reg); |
679 | } | 679 | } |
680 | if (rx != NULL) { | 680 | if (rx != NULL) { |
681 | if (mcspi_wait_for_reg_bit(chstat_reg, | 681 | if (mcspi_wait_for_reg_bit(chstat_reg, |
@@ -687,7 +687,7 @@ omap2_mcspi_txrx_pio(struct spi_device *spi, struct spi_transfer *xfer) | |||
687 | if (c == 1 && tx == NULL && | 687 | if (c == 1 && tx == NULL && |
688 | (l & OMAP2_MCSPI_CHCONF_TURBO)) { | 688 | (l & OMAP2_MCSPI_CHCONF_TURBO)) { |
689 | omap2_mcspi_set_enable(spi, 0); | 689 | omap2_mcspi_set_enable(spi, 0); |
690 | *rx++ = __raw_readl(rx_reg); | 690 | *rx++ = readl_relaxed(rx_reg); |
691 | dev_vdbg(&spi->dev, "read-%d %02x\n", | 691 | dev_vdbg(&spi->dev, "read-%d %02x\n", |
692 | word_len, *(rx - 1)); | 692 | word_len, *(rx - 1)); |
693 | if (mcspi_wait_for_reg_bit(chstat_reg, | 693 | if (mcspi_wait_for_reg_bit(chstat_reg, |
@@ -701,7 +701,7 @@ omap2_mcspi_txrx_pio(struct spi_device *spi, struct spi_transfer *xfer) | |||
701 | omap2_mcspi_set_enable(spi, 0); | 701 | omap2_mcspi_set_enable(spi, 0); |
702 | } | 702 | } |
703 | 703 | ||
704 | *rx++ = __raw_readl(rx_reg); | 704 | *rx++ = readl_relaxed(rx_reg); |
705 | dev_vdbg(&spi->dev, "read-%d %02x\n", | 705 | dev_vdbg(&spi->dev, "read-%d %02x\n", |
706 | word_len, *(rx - 1)); | 706 | word_len, *(rx - 1)); |
707 | } | 707 | } |
@@ -722,7 +722,7 @@ omap2_mcspi_txrx_pio(struct spi_device *spi, struct spi_transfer *xfer) | |||
722 | } | 722 | } |
723 | dev_vdbg(&spi->dev, "write-%d %04x\n", | 723 | dev_vdbg(&spi->dev, "write-%d %04x\n", |
724 | word_len, *tx); | 724 | word_len, *tx); |
725 | __raw_writel(*tx++, tx_reg); | 725 | writel_relaxed(*tx++, tx_reg); |
726 | } | 726 | } |
727 | if (rx != NULL) { | 727 | if (rx != NULL) { |
728 | if (mcspi_wait_for_reg_bit(chstat_reg, | 728 | if (mcspi_wait_for_reg_bit(chstat_reg, |
@@ -734,7 +734,7 @@ omap2_mcspi_txrx_pio(struct spi_device *spi, struct spi_transfer *xfer) | |||
734 | if (c == 2 && tx == NULL && | 734 | if (c == 2 && tx == NULL && |
735 | (l & OMAP2_MCSPI_CHCONF_TURBO)) { | 735 | (l & OMAP2_MCSPI_CHCONF_TURBO)) { |
736 | omap2_mcspi_set_enable(spi, 0); | 736 | omap2_mcspi_set_enable(spi, 0); |
737 | *rx++ = __raw_readl(rx_reg); | 737 | *rx++ = readl_relaxed(rx_reg); |
738 | dev_vdbg(&spi->dev, "read-%d %04x\n", | 738 | dev_vdbg(&spi->dev, "read-%d %04x\n", |
739 | word_len, *(rx - 1)); | 739 | word_len, *(rx - 1)); |
740 | if (mcspi_wait_for_reg_bit(chstat_reg, | 740 | if (mcspi_wait_for_reg_bit(chstat_reg, |
@@ -748,7 +748,7 @@ omap2_mcspi_txrx_pio(struct spi_device *spi, struct spi_transfer *xfer) | |||
748 | omap2_mcspi_set_enable(spi, 0); | 748 | omap2_mcspi_set_enable(spi, 0); |
749 | } | 749 | } |
750 | 750 | ||
751 | *rx++ = __raw_readl(rx_reg); | 751 | *rx++ = readl_relaxed(rx_reg); |
752 | dev_vdbg(&spi->dev, "read-%d %04x\n", | 752 | dev_vdbg(&spi->dev, "read-%d %04x\n", |
753 | word_len, *(rx - 1)); | 753 | word_len, *(rx - 1)); |
754 | } | 754 | } |
@@ -769,7 +769,7 @@ omap2_mcspi_txrx_pio(struct spi_device *spi, struct spi_transfer *xfer) | |||
769 | } | 769 | } |
770 | dev_vdbg(&spi->dev, "write-%d %08x\n", | 770 | dev_vdbg(&spi->dev, "write-%d %08x\n", |
771 | word_len, *tx); | 771 | word_len, *tx); |
772 | __raw_writel(*tx++, tx_reg); | 772 | writel_relaxed(*tx++, tx_reg); |
773 | } | 773 | } |
774 | if (rx != NULL) { | 774 | if (rx != NULL) { |
775 | if (mcspi_wait_for_reg_bit(chstat_reg, | 775 | if (mcspi_wait_for_reg_bit(chstat_reg, |
@@ -781,7 +781,7 @@ omap2_mcspi_txrx_pio(struct spi_device *spi, struct spi_transfer *xfer) | |||
781 | if (c == 4 && tx == NULL && | 781 | if (c == 4 && tx == NULL && |
782 | (l & OMAP2_MCSPI_CHCONF_TURBO)) { | 782 | (l & OMAP2_MCSPI_CHCONF_TURBO)) { |
783 | omap2_mcspi_set_enable(spi, 0); | 783 | omap2_mcspi_set_enable(spi, 0); |
784 | *rx++ = __raw_readl(rx_reg); | 784 | *rx++ = readl_relaxed(rx_reg); |
785 | dev_vdbg(&spi->dev, "read-%d %08x\n", | 785 | dev_vdbg(&spi->dev, "read-%d %08x\n", |
786 | word_len, *(rx - 1)); | 786 | word_len, *(rx - 1)); |
787 | if (mcspi_wait_for_reg_bit(chstat_reg, | 787 | if (mcspi_wait_for_reg_bit(chstat_reg, |
@@ -795,7 +795,7 @@ omap2_mcspi_txrx_pio(struct spi_device *spi, struct spi_transfer *xfer) | |||
795 | omap2_mcspi_set_enable(spi, 0); | 795 | omap2_mcspi_set_enable(spi, 0); |
796 | } | 796 | } |
797 | 797 | ||
798 | *rx++ = __raw_readl(rx_reg); | 798 | *rx++ = readl_relaxed(rx_reg); |
799 | dev_vdbg(&spi->dev, "read-%d %08x\n", | 799 | dev_vdbg(&spi->dev, "read-%d %08x\n", |
800 | word_len, *(rx - 1)); | 800 | word_len, *(rx - 1)); |
801 | } | 801 | } |
@@ -1107,7 +1107,7 @@ static void omap2_mcspi_work(struct omap2_mcspi *mcspi, struct spi_message *m) | |||
1107 | 1107 | ||
1108 | /* RX_ONLY mode needs dummy data in TX reg */ | 1108 | /* RX_ONLY mode needs dummy data in TX reg */ |
1109 | if (t->tx_buf == NULL) | 1109 | if (t->tx_buf == NULL) |
1110 | __raw_writel(0, cs->base | 1110 | writel_relaxed(0, cs->base |
1111 | + OMAP2_MCSPI_TX0); | 1111 | + OMAP2_MCSPI_TX0); |
1112 | 1112 | ||
1113 | if ((mcspi_dma->dma_rx && mcspi_dma->dma_tx) && | 1113 | if ((mcspi_dma->dma_rx && mcspi_dma->dma_tx) && |
@@ -1470,9 +1470,9 @@ static int omap2_mcspi_resume(struct device *dev) | |||
1470 | * change in account. | 1470 | * change in account. |
1471 | */ | 1471 | */ |
1472 | cs->chconf0 |= OMAP2_MCSPI_CHCONF_FORCE; | 1472 | cs->chconf0 |= OMAP2_MCSPI_CHCONF_FORCE; |
1473 | __raw_writel(cs->chconf0, cs->base + OMAP2_MCSPI_CHCONF0); | 1473 | writel_relaxed(cs->chconf0, cs->base + OMAP2_MCSPI_CHCONF0); |
1474 | cs->chconf0 &= ~OMAP2_MCSPI_CHCONF_FORCE; | 1474 | cs->chconf0 &= ~OMAP2_MCSPI_CHCONF_FORCE; |
1475 | __raw_writel(cs->chconf0, cs->base + OMAP2_MCSPI_CHCONF0); | 1475 | writel_relaxed(cs->chconf0, cs->base + OMAP2_MCSPI_CHCONF0); |
1476 | } | 1476 | } |
1477 | } | 1477 | } |
1478 | pm_runtime_mark_last_busy(mcspi->dev); | 1478 | pm_runtime_mark_last_busy(mcspi->dev); |