diff options
author | Andrea Bastoni <bastoni@cs.unc.edu> | 2010-05-30 19:16:45 -0400 |
---|---|---|
committer | Andrea Bastoni <bastoni@cs.unc.edu> | 2010-05-30 19:16:45 -0400 |
commit | ada47b5fe13d89735805b566185f4885f5a3f750 (patch) | |
tree | 644b88f8a71896307d71438e9b3af49126ffb22b /drivers/spi/omap_spi_100k.c | |
parent | 43e98717ad40a4ae64545b5ba047c7b86aa44f4f (diff) | |
parent | 3280f21d43ee541f97f8cda5792150d2dbec20d5 (diff) |
Merge branch 'wip-2.6.34' into old-private-masterarchived-private-master
Diffstat (limited to 'drivers/spi/omap_spi_100k.c')
-rw-r--r-- | drivers/spi/omap_spi_100k.c | 636 |
1 files changed, 636 insertions, 0 deletions
diff --git a/drivers/spi/omap_spi_100k.c b/drivers/spi/omap_spi_100k.c new file mode 100644 index 000000000000..24668b30a52d --- /dev/null +++ b/drivers/spi/omap_spi_100k.c | |||
@@ -0,0 +1,636 @@ | |||
1 | /* | ||
2 | * OMAP7xx SPI 100k controller driver | ||
3 | * Author: Fabrice Crohas <fcrohas@gmail.com> | ||
4 | * from original omap1_mcspi driver | ||
5 | * | ||
6 | * Copyright (C) 2005, 2006 Nokia Corporation | ||
7 | * Author: Samuel Ortiz <samuel.ortiz@nokia.com> and | ||
8 | * Juha Yrj�l� <juha.yrjola@nokia.com> | ||
9 | * | ||
10 | * This program is free software; you can redistribute it and/or modify | ||
11 | * it under the terms of the GNU General Public License as published by | ||
12 | * the Free Software Foundation; either version 2 of the License, or | ||
13 | * (at your option) any later version. | ||
14 | * | ||
15 | * This program is distributed in the hope that it will be useful, | ||
16 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
17 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
18 | * GNU General Public License for more details. | ||
19 | * | ||
20 | * You should have received a copy of the GNU General Public License | ||
21 | * along with this program; if not, write to the Free Software | ||
22 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | ||
23 | * | ||
24 | */ | ||
25 | #include <linux/kernel.h> | ||
26 | #include <linux/init.h> | ||
27 | #include <linux/interrupt.h> | ||
28 | #include <linux/module.h> | ||
29 | #include <linux/device.h> | ||
30 | #include <linux/delay.h> | ||
31 | #include <linux/platform_device.h> | ||
32 | #include <linux/err.h> | ||
33 | #include <linux/clk.h> | ||
34 | #include <linux/io.h> | ||
35 | #include <linux/gpio.h> | ||
36 | #include <linux/slab.h> | ||
37 | |||
38 | #include <linux/spi/spi.h> | ||
39 | |||
40 | #include <plat/clock.h> | ||
41 | |||
42 | #define OMAP1_SPI100K_MAX_FREQ 48000000 | ||
43 | |||
44 | #define ICR_SPITAS (OMAP7XX_ICR_BASE + 0x12) | ||
45 | |||
46 | #define SPI_SETUP1 0x00 | ||
47 | #define SPI_SETUP2 0x02 | ||
48 | #define SPI_CTRL 0x04 | ||
49 | #define SPI_STATUS 0x06 | ||
50 | #define SPI_TX_LSB 0x08 | ||
51 | #define SPI_TX_MSB 0x0a | ||
52 | #define SPI_RX_LSB 0x0c | ||
53 | #define SPI_RX_MSB 0x0e | ||
54 | |||
55 | #define SPI_SETUP1_INT_READ_ENABLE (1UL << 5) | ||
56 | #define SPI_SETUP1_INT_WRITE_ENABLE (1UL << 4) | ||
57 | #define SPI_SETUP1_CLOCK_DIVISOR(x) ((x) << 1) | ||
58 | #define SPI_SETUP1_CLOCK_ENABLE (1UL << 0) | ||
59 | |||
60 | #define SPI_SETUP2_ACTIVE_EDGE_FALLING (0UL << 0) | ||
61 | #define SPI_SETUP2_ACTIVE_EDGE_RISING (1UL << 0) | ||
62 | #define SPI_SETUP2_NEGATIVE_LEVEL (0UL << 5) | ||
63 | #define SPI_SETUP2_POSITIVE_LEVEL (1UL << 5) | ||
64 | #define SPI_SETUP2_LEVEL_TRIGGER (0UL << 10) | ||
65 | #define SPI_SETUP2_EDGE_TRIGGER (1UL << 10) | ||
66 | |||
67 | #define SPI_CTRL_SEN(x) ((x) << 7) | ||
68 | #define SPI_CTRL_WORD_SIZE(x) (((x) - 1) << 2) | ||
69 | #define SPI_CTRL_WR (1UL << 1) | ||
70 | #define SPI_CTRL_RD (1UL << 0) | ||
71 | |||
72 | #define SPI_STATUS_WE (1UL << 1) | ||
73 | #define SPI_STATUS_RD (1UL << 0) | ||
74 | |||
75 | #define WRITE 0 | ||
76 | #define READ 1 | ||
77 | |||
78 | |||
79 | /* use PIO for small transfers, avoiding DMA setup/teardown overhead and | ||
80 | * cache operations; better heuristics consider wordsize and bitrate. | ||
81 | */ | ||
82 | #define DMA_MIN_BYTES 8 | ||
83 | |||
84 | #define SPI_RUNNING 0 | ||
85 | #define SPI_SHUTDOWN 1 | ||
86 | |||
87 | struct omap1_spi100k { | ||
88 | struct work_struct work; | ||
89 | |||
90 | /* lock protects queue and registers */ | ||
91 | spinlock_t lock; | ||
92 | struct list_head msg_queue; | ||
93 | struct spi_master *master; | ||
94 | struct clk *ick; | ||
95 | struct clk *fck; | ||
96 | |||
97 | /* Virtual base address of the controller */ | ||
98 | void __iomem *base; | ||
99 | |||
100 | /* State of the SPI */ | ||
101 | unsigned int state; | ||
102 | }; | ||
103 | |||
104 | struct omap1_spi100k_cs { | ||
105 | void __iomem *base; | ||
106 | int word_len; | ||
107 | }; | ||
108 | |||
109 | static struct workqueue_struct *omap1_spi100k_wq; | ||
110 | |||
111 | #define MOD_REG_BIT(val, mask, set) do { \ | ||
112 | if (set) \ | ||
113 | val |= mask; \ | ||
114 | else \ | ||
115 | val &= ~mask; \ | ||
116 | } while (0) | ||
117 | |||
118 | static void spi100k_enable_clock(struct spi_master *master) | ||
119 | { | ||
120 | unsigned int val; | ||
121 | struct omap1_spi100k *spi100k = spi_master_get_devdata(master); | ||
122 | |||
123 | /* enable SPI */ | ||
124 | val = readw(spi100k->base + SPI_SETUP1); | ||
125 | val |= SPI_SETUP1_CLOCK_ENABLE; | ||
126 | writew(val, spi100k->base + SPI_SETUP1); | ||
127 | } | ||
128 | |||
129 | static void spi100k_disable_clock(struct spi_master *master) | ||
130 | { | ||
131 | unsigned int val; | ||
132 | struct omap1_spi100k *spi100k = spi_master_get_devdata(master); | ||
133 | |||
134 | /* disable SPI */ | ||
135 | val = readw(spi100k->base + SPI_SETUP1); | ||
136 | val &= ~SPI_SETUP1_CLOCK_ENABLE; | ||
137 | writew(val, spi100k->base + SPI_SETUP1); | ||
138 | } | ||
139 | |||
140 | static void spi100k_write_data(struct spi_master *master, int len, int data) | ||
141 | { | ||
142 | struct omap1_spi100k *spi100k = spi_master_get_devdata(master); | ||
143 | |||
144 | /* write 16-bit word */ | ||
145 | spi100k_enable_clock(master); | ||
146 | writew( data , spi100k->base + SPI_TX_MSB); | ||
147 | |||
148 | writew(SPI_CTRL_SEN(0) | | ||
149 | SPI_CTRL_WORD_SIZE(len) | | ||
150 | SPI_CTRL_WR, | ||
151 | spi100k->base + SPI_CTRL); | ||
152 | |||
153 | /* Wait for bit ack send change */ | ||
154 | while((readw(spi100k->base + SPI_STATUS) & SPI_STATUS_WE) != SPI_STATUS_WE); | ||
155 | udelay(1000); | ||
156 | |||
157 | spi100k_disable_clock(master); | ||
158 | } | ||
159 | |||
160 | static int spi100k_read_data(struct spi_master *master, int len) | ||
161 | { | ||
162 | int dataH,dataL; | ||
163 | struct omap1_spi100k *spi100k = spi_master_get_devdata(master); | ||
164 | |||
165 | spi100k_enable_clock(master); | ||
166 | writew(SPI_CTRL_SEN(0) | | ||
167 | SPI_CTRL_WORD_SIZE(len) | | ||
168 | SPI_CTRL_RD, | ||
169 | spi100k->base + SPI_CTRL); | ||
170 | |||
171 | while((readw(spi100k->base + SPI_STATUS) & SPI_STATUS_RD) != SPI_STATUS_RD); | ||
172 | udelay(1000); | ||
173 | |||
174 | dataL = readw(spi100k->base + SPI_RX_LSB); | ||
175 | dataH = readw(spi100k->base + SPI_RX_MSB); | ||
176 | spi100k_disable_clock(master); | ||
177 | |||
178 | return dataL; | ||
179 | } | ||
180 | |||
181 | static void spi100k_open(struct spi_master *master) | ||
182 | { | ||
183 | /* get control of SPI */ | ||
184 | struct omap1_spi100k *spi100k = spi_master_get_devdata(master); | ||
185 | |||
186 | writew(SPI_SETUP1_INT_READ_ENABLE | | ||
187 | SPI_SETUP1_INT_WRITE_ENABLE | | ||
188 | SPI_SETUP1_CLOCK_DIVISOR(0), spi100k->base + SPI_SETUP1); | ||
189 | |||
190 | /* configure clock and interrupts */ | ||
191 | writew(SPI_SETUP2_ACTIVE_EDGE_FALLING | | ||
192 | SPI_SETUP2_NEGATIVE_LEVEL | | ||
193 | SPI_SETUP2_LEVEL_TRIGGER, spi100k->base + SPI_SETUP2); | ||
194 | } | ||
195 | |||
196 | static void omap1_spi100k_force_cs(struct omap1_spi100k *spi100k, int enable) | ||
197 | { | ||
198 | if (enable) | ||
199 | writew(0x05fc, spi100k->base + SPI_CTRL); | ||
200 | else | ||
201 | writew(0x05fd, spi100k->base + SPI_CTRL); | ||
202 | } | ||
203 | |||
204 | static unsigned | ||
205 | omap1_spi100k_txrx_pio(struct spi_device *spi, struct spi_transfer *xfer) | ||
206 | { | ||
207 | struct omap1_spi100k *spi100k; | ||
208 | struct omap1_spi100k_cs *cs = spi->controller_state; | ||
209 | unsigned int count, c; | ||
210 | int word_len; | ||
211 | |||
212 | spi100k = spi_master_get_devdata(spi->master); | ||
213 | count = xfer->len; | ||
214 | c = count; | ||
215 | word_len = cs->word_len; | ||
216 | |||
217 | /* RX_ONLY mode needs dummy data in TX reg */ | ||
218 | if (xfer->tx_buf == NULL) | ||
219 | spi100k_write_data(spi->master,word_len, 0); | ||
220 | |||
221 | if (word_len <= 8) { | ||
222 | u8 *rx; | ||
223 | const u8 *tx; | ||
224 | |||
225 | rx = xfer->rx_buf; | ||
226 | tx = xfer->tx_buf; | ||
227 | do { | ||
228 | c-=1; | ||
229 | if (xfer->tx_buf != NULL) | ||
230 | spi100k_write_data(spi->master,word_len, *tx); | ||
231 | if (xfer->rx_buf != NULL) | ||
232 | *rx = spi100k_read_data(spi->master,word_len); | ||
233 | } while(c); | ||
234 | } else if (word_len <= 16) { | ||
235 | u16 *rx; | ||
236 | const u16 *tx; | ||
237 | |||
238 | rx = xfer->rx_buf; | ||
239 | tx = xfer->tx_buf; | ||
240 | do { | ||
241 | c-=2; | ||
242 | if (xfer->tx_buf != NULL) | ||
243 | spi100k_write_data(spi->master,word_len, *tx++); | ||
244 | if (xfer->rx_buf != NULL) | ||
245 | *rx++ = spi100k_read_data(spi->master,word_len); | ||
246 | } while(c); | ||
247 | } else if (word_len <= 32) { | ||
248 | u32 *rx; | ||
249 | const u32 *tx; | ||
250 | |||
251 | rx = xfer->rx_buf; | ||
252 | tx = xfer->tx_buf; | ||
253 | do { | ||
254 | c-=4; | ||
255 | if (xfer->tx_buf != NULL) | ||
256 | spi100k_write_data(spi->master,word_len, *tx); | ||
257 | if (xfer->rx_buf != NULL) | ||
258 | *rx = spi100k_read_data(spi->master,word_len); | ||
259 | } while(c); | ||
260 | } | ||
261 | return count - c; | ||
262 | } | ||
263 | |||
264 | /* called only when no transfer is active to this device */ | ||
265 | static int omap1_spi100k_setup_transfer(struct spi_device *spi, | ||
266 | struct spi_transfer *t) | ||
267 | { | ||
268 | struct omap1_spi100k *spi100k = spi_master_get_devdata(spi->master); | ||
269 | struct omap1_spi100k_cs *cs = spi->controller_state; | ||
270 | u8 word_len = spi->bits_per_word; | ||
271 | |||
272 | if (t != NULL && t->bits_per_word) | ||
273 | word_len = t->bits_per_word; | ||
274 | if (!word_len) | ||
275 | word_len = 8; | ||
276 | |||
277 | if (spi->bits_per_word > 32) | ||
278 | return -EINVAL; | ||
279 | cs->word_len = word_len; | ||
280 | |||
281 | /* SPI init before transfer */ | ||
282 | writew(0x3e , spi100k->base + SPI_SETUP1); | ||
283 | writew(0x00 , spi100k->base + SPI_STATUS); | ||
284 | writew(0x3e , spi100k->base + SPI_CTRL); | ||
285 | |||
286 | return 0; | ||
287 | } | ||
288 | |||
289 | /* the spi->mode bits understood by this driver: */ | ||
290 | #define MODEBITS (SPI_CPOL | SPI_CPHA | SPI_CS_HIGH) | ||
291 | |||
292 | static int omap1_spi100k_setup(struct spi_device *spi) | ||
293 | { | ||
294 | int ret; | ||
295 | struct omap1_spi100k *spi100k; | ||
296 | struct omap1_spi100k_cs *cs = spi->controller_state; | ||
297 | |||
298 | if (spi->bits_per_word < 4 || spi->bits_per_word > 32) { | ||
299 | dev_dbg(&spi->dev, "setup: unsupported %d bit words\n", | ||
300 | spi->bits_per_word); | ||
301 | return -EINVAL; | ||
302 | } | ||
303 | |||
304 | spi100k = spi_master_get_devdata(spi->master); | ||
305 | |||
306 | if (!cs) { | ||
307 | cs = kzalloc(sizeof *cs, GFP_KERNEL); | ||
308 | if (!cs) | ||
309 | return -ENOMEM; | ||
310 | cs->base = spi100k->base + spi->chip_select * 0x14; | ||
311 | spi->controller_state = cs; | ||
312 | } | ||
313 | |||
314 | spi100k_open(spi->master); | ||
315 | |||
316 | clk_enable(spi100k->ick); | ||
317 | clk_enable(spi100k->fck); | ||
318 | |||
319 | ret = omap1_spi100k_setup_transfer(spi, NULL); | ||
320 | |||
321 | clk_disable(spi100k->ick); | ||
322 | clk_disable(spi100k->fck); | ||
323 | |||
324 | return ret; | ||
325 | } | ||
326 | |||
327 | static void omap1_spi100k_work(struct work_struct *work) | ||
328 | { | ||
329 | struct omap1_spi100k *spi100k; | ||
330 | int status = 0; | ||
331 | |||
332 | spi100k = container_of(work, struct omap1_spi100k, work); | ||
333 | spin_lock_irq(&spi100k->lock); | ||
334 | |||
335 | clk_enable(spi100k->ick); | ||
336 | clk_enable(spi100k->fck); | ||
337 | |||
338 | /* We only enable one channel at a time -- the one whose message is | ||
339 | * at the head of the queue -- although this controller would gladly | ||
340 | * arbitrate among multiple channels. This corresponds to "single | ||
341 | * channel" master mode. As a side effect, we need to manage the | ||
342 | * chipselect with the FORCE bit ... CS != channel enable. | ||
343 | */ | ||
344 | while (!list_empty(&spi100k->msg_queue)) { | ||
345 | struct spi_message *m; | ||
346 | struct spi_device *spi; | ||
347 | struct spi_transfer *t = NULL; | ||
348 | int cs_active = 0; | ||
349 | struct omap1_spi100k_cs *cs; | ||
350 | int par_override = 0; | ||
351 | |||
352 | m = container_of(spi100k->msg_queue.next, struct spi_message, | ||
353 | queue); | ||
354 | |||
355 | list_del_init(&m->queue); | ||
356 | spin_unlock_irq(&spi100k->lock); | ||
357 | |||
358 | spi = m->spi; | ||
359 | cs = spi->controller_state; | ||
360 | |||
361 | list_for_each_entry(t, &m->transfers, transfer_list) { | ||
362 | if (t->tx_buf == NULL && t->rx_buf == NULL && t->len) { | ||
363 | status = -EINVAL; | ||
364 | break; | ||
365 | } | ||
366 | if (par_override || t->speed_hz || t->bits_per_word) { | ||
367 | par_override = 1; | ||
368 | status = omap1_spi100k_setup_transfer(spi, t); | ||
369 | if (status < 0) | ||
370 | break; | ||
371 | if (!t->speed_hz && !t->bits_per_word) | ||
372 | par_override = 0; | ||
373 | } | ||
374 | |||
375 | if (!cs_active) { | ||
376 | omap1_spi100k_force_cs(spi100k, 1); | ||
377 | cs_active = 1; | ||
378 | } | ||
379 | |||
380 | if (t->len) { | ||
381 | unsigned count; | ||
382 | |||
383 | /* RX_ONLY mode needs dummy data in TX reg */ | ||
384 | if (t->tx_buf == NULL) | ||
385 | spi100k_write_data(spi->master, 8, 0); | ||
386 | |||
387 | count = omap1_spi100k_txrx_pio(spi, t); | ||
388 | m->actual_length += count; | ||
389 | |||
390 | if (count != t->len) { | ||
391 | status = -EIO; | ||
392 | break; | ||
393 | } | ||
394 | } | ||
395 | |||
396 | if (t->delay_usecs) | ||
397 | udelay(t->delay_usecs); | ||
398 | |||
399 | /* ignore the "leave it on after last xfer" hint */ | ||
400 | |||
401 | if (t->cs_change) { | ||
402 | omap1_spi100k_force_cs(spi100k, 0); | ||
403 | cs_active = 0; | ||
404 | } | ||
405 | } | ||
406 | |||
407 | /* Restore defaults if they were overriden */ | ||
408 | if (par_override) { | ||
409 | par_override = 0; | ||
410 | status = omap1_spi100k_setup_transfer(spi, NULL); | ||
411 | } | ||
412 | |||
413 | if (cs_active) | ||
414 | omap1_spi100k_force_cs(spi100k, 0); | ||
415 | |||
416 | m->status = status; | ||
417 | m->complete(m->context); | ||
418 | |||
419 | spin_lock_irq(&spi100k->lock); | ||
420 | } | ||
421 | |||
422 | clk_disable(spi100k->ick); | ||
423 | clk_disable(spi100k->fck); | ||
424 | spin_unlock_irq(&spi100k->lock); | ||
425 | |||
426 | if (status < 0) | ||
427 | printk(KERN_WARNING "spi transfer failed with %d\n", status); | ||
428 | } | ||
429 | |||
430 | static int omap1_spi100k_transfer(struct spi_device *spi, struct spi_message *m) | ||
431 | { | ||
432 | struct omap1_spi100k *spi100k; | ||
433 | unsigned long flags; | ||
434 | struct spi_transfer *t; | ||
435 | |||
436 | m->actual_length = 0; | ||
437 | m->status = -EINPROGRESS; | ||
438 | |||
439 | spi100k = spi_master_get_devdata(spi->master); | ||
440 | |||
441 | /* Don't accept new work if we're shutting down */ | ||
442 | if (spi100k->state == SPI_SHUTDOWN) | ||
443 | return -ESHUTDOWN; | ||
444 | |||
445 | /* reject invalid messages and transfers */ | ||
446 | if (list_empty(&m->transfers) || !m->complete) | ||
447 | return -EINVAL; | ||
448 | |||
449 | list_for_each_entry(t, &m->transfers, transfer_list) { | ||
450 | const void *tx_buf = t->tx_buf; | ||
451 | void *rx_buf = t->rx_buf; | ||
452 | unsigned len = t->len; | ||
453 | |||
454 | if (t->speed_hz > OMAP1_SPI100K_MAX_FREQ | ||
455 | || (len && !(rx_buf || tx_buf)) | ||
456 | || (t->bits_per_word && | ||
457 | ( t->bits_per_word < 4 | ||
458 | || t->bits_per_word > 32))) { | ||
459 | dev_dbg(&spi->dev, "transfer: %d Hz, %d %s%s, %d bpw\n", | ||
460 | t->speed_hz, | ||
461 | len, | ||
462 | tx_buf ? "tx" : "", | ||
463 | rx_buf ? "rx" : "", | ||
464 | t->bits_per_word); | ||
465 | return -EINVAL; | ||
466 | } | ||
467 | |||
468 | if (t->speed_hz && t->speed_hz < OMAP1_SPI100K_MAX_FREQ/(1<<16)) { | ||
469 | dev_dbg(&spi->dev, "%d Hz max exceeds %d\n", | ||
470 | t->speed_hz, | ||
471 | OMAP1_SPI100K_MAX_FREQ/(1<<16)); | ||
472 | return -EINVAL; | ||
473 | } | ||
474 | |||
475 | } | ||
476 | |||
477 | spin_lock_irqsave(&spi100k->lock, flags); | ||
478 | list_add_tail(&m->queue, &spi100k->msg_queue); | ||
479 | queue_work(omap1_spi100k_wq, &spi100k->work); | ||
480 | spin_unlock_irqrestore(&spi100k->lock, flags); | ||
481 | |||
482 | return 0; | ||
483 | } | ||
484 | |||
485 | static int __init omap1_spi100k_reset(struct omap1_spi100k *spi100k) | ||
486 | { | ||
487 | return 0; | ||
488 | } | ||
489 | |||
490 | static int __devinit omap1_spi100k_probe(struct platform_device *pdev) | ||
491 | { | ||
492 | struct spi_master *master; | ||
493 | struct omap1_spi100k *spi100k; | ||
494 | int status = 0; | ||
495 | |||
496 | if (!pdev->id) | ||
497 | return -EINVAL; | ||
498 | |||
499 | master = spi_alloc_master(&pdev->dev, sizeof *spi100k); | ||
500 | if (master == NULL) { | ||
501 | dev_dbg(&pdev->dev, "master allocation failed\n"); | ||
502 | return -ENOMEM; | ||
503 | } | ||
504 | |||
505 | if (pdev->id != -1) | ||
506 | master->bus_num = pdev->id; | ||
507 | |||
508 | master->setup = omap1_spi100k_setup; | ||
509 | master->transfer = omap1_spi100k_transfer; | ||
510 | master->cleanup = NULL; | ||
511 | master->num_chipselect = 2; | ||
512 | master->mode_bits = MODEBITS; | ||
513 | |||
514 | dev_set_drvdata(&pdev->dev, master); | ||
515 | |||
516 | spi100k = spi_master_get_devdata(master); | ||
517 | spi100k->master = master; | ||
518 | |||
519 | /* | ||
520 | * The memory region base address is taken as the platform_data. | ||
521 | * You should allocate this with ioremap() before initializing | ||
522 | * the SPI. | ||
523 | */ | ||
524 | spi100k->base = (void __iomem *) pdev->dev.platform_data; | ||
525 | |||
526 | INIT_WORK(&spi100k->work, omap1_spi100k_work); | ||
527 | |||
528 | spin_lock_init(&spi100k->lock); | ||
529 | INIT_LIST_HEAD(&spi100k->msg_queue); | ||
530 | spi100k->ick = clk_get(&pdev->dev, "ick"); | ||
531 | if (IS_ERR(spi100k->ick)) { | ||
532 | dev_dbg(&pdev->dev, "can't get spi100k_ick\n"); | ||
533 | status = PTR_ERR(spi100k->ick); | ||
534 | goto err1; | ||
535 | } | ||
536 | |||
537 | spi100k->fck = clk_get(&pdev->dev, "fck"); | ||
538 | if (IS_ERR(spi100k->fck)) { | ||
539 | dev_dbg(&pdev->dev, "can't get spi100k_fck\n"); | ||
540 | status = PTR_ERR(spi100k->fck); | ||
541 | goto err2; | ||
542 | } | ||
543 | |||
544 | if (omap1_spi100k_reset(spi100k) < 0) | ||
545 | goto err3; | ||
546 | |||
547 | status = spi_register_master(master); | ||
548 | if (status < 0) | ||
549 | goto err3; | ||
550 | |||
551 | spi100k->state = SPI_RUNNING; | ||
552 | |||
553 | return status; | ||
554 | |||
555 | err3: | ||
556 | clk_put(spi100k->fck); | ||
557 | err2: | ||
558 | clk_put(spi100k->ick); | ||
559 | err1: | ||
560 | spi_master_put(master); | ||
561 | return status; | ||
562 | } | ||
563 | |||
564 | static int __exit omap1_spi100k_remove(struct platform_device *pdev) | ||
565 | { | ||
566 | struct spi_master *master; | ||
567 | struct omap1_spi100k *spi100k; | ||
568 | struct resource *r; | ||
569 | unsigned limit = 500; | ||
570 | unsigned long flags; | ||
571 | int status = 0; | ||
572 | |||
573 | master = dev_get_drvdata(&pdev->dev); | ||
574 | spi100k = spi_master_get_devdata(master); | ||
575 | |||
576 | spin_lock_irqsave(&spi100k->lock, flags); | ||
577 | |||
578 | spi100k->state = SPI_SHUTDOWN; | ||
579 | while (!list_empty(&spi100k->msg_queue) && limit--) { | ||
580 | spin_unlock_irqrestore(&spi100k->lock, flags); | ||
581 | msleep(10); | ||
582 | spin_lock_irqsave(&spi100k->lock, flags); | ||
583 | } | ||
584 | |||
585 | if (!list_empty(&spi100k->msg_queue)) | ||
586 | status = -EBUSY; | ||
587 | |||
588 | spin_unlock_irqrestore(&spi100k->lock, flags); | ||
589 | |||
590 | if (status != 0) | ||
591 | return status; | ||
592 | |||
593 | clk_put(spi100k->fck); | ||
594 | clk_put(spi100k->ick); | ||
595 | |||
596 | r = platform_get_resource(pdev, IORESOURCE_MEM, 0); | ||
597 | |||
598 | spi_unregister_master(master); | ||
599 | |||
600 | return 0; | ||
601 | } | ||
602 | |||
603 | static struct platform_driver omap1_spi100k_driver = { | ||
604 | .driver = { | ||
605 | .name = "omap1_spi100k", | ||
606 | .owner = THIS_MODULE, | ||
607 | }, | ||
608 | .remove = __exit_p(omap1_spi100k_remove), | ||
609 | }; | ||
610 | |||
611 | |||
612 | static int __init omap1_spi100k_init(void) | ||
613 | { | ||
614 | omap1_spi100k_wq = create_singlethread_workqueue( | ||
615 | omap1_spi100k_driver.driver.name); | ||
616 | |||
617 | if (omap1_spi100k_wq == NULL) | ||
618 | return -1; | ||
619 | |||
620 | return platform_driver_probe(&omap1_spi100k_driver, omap1_spi100k_probe); | ||
621 | } | ||
622 | |||
623 | static void __exit omap1_spi100k_exit(void) | ||
624 | { | ||
625 | platform_driver_unregister(&omap1_spi100k_driver); | ||
626 | |||
627 | destroy_workqueue(omap1_spi100k_wq); | ||
628 | } | ||
629 | |||
630 | module_init(omap1_spi100k_init); | ||
631 | module_exit(omap1_spi100k_exit); | ||
632 | |||
633 | MODULE_DESCRIPTION("OMAP7xx SPI 100k controller driver"); | ||
634 | MODULE_AUTHOR("Fabrice Crohas <fcrohas@gmail.com>"); | ||
635 | MODULE_LICENSE("GPL"); | ||
636 | |||