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authorSekhar Nori <nsekhar@ti.com>2010-10-11 01:11:39 -0400
committerSekhar Nori <nsekhar@ti.com>2010-11-18 08:08:38 -0500
commit212d4b69652171d4474bc9dfc08e829737264632 (patch)
tree23e21bbca0bd6ff51ae011acb93b853b0fbb0ee8 /drivers/spi/davinci_spi.c
parent0e0eae4d1cdff5fa6608bcc6f6990774dec2527d (diff)
spi: davinci: shorten variable names
Shorten names of local variables and structure members where possible. Local variables: * 'davinci_spi' is being renamed 'dspi' * 'davinci_spi_dma' is being renamed 'dma' Structure members: * 'dma_{tx|rx}_channel' is being renamed '{tx|rx}_channel' since the structure containing them is already called 'davinci_spi_dma' * 'davinci_spi_dma' in 'davinci_spi' structure is being renamed 'dma' Tested-By: Brian Niebuhr <bniebuhr@efjohnson.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com>
Diffstat (limited to 'drivers/spi/davinci_spi.c')
-rw-r--r--drivers/spi/davinci_spi.c409
1 files changed, 198 insertions, 211 deletions
diff --git a/drivers/spi/davinci_spi.c b/drivers/spi/davinci_spi.c
index f6f63d058140..6beab99bf95b 100644
--- a/drivers/spi/davinci_spi.c
+++ b/drivers/spi/davinci_spi.c
@@ -115,8 +115,8 @@
115 115
116/* We have 2 DMA channels per CS, one for RX and one for TX */ 116/* We have 2 DMA channels per CS, one for RX and one for TX */
117struct davinci_spi_dma { 117struct davinci_spi_dma {
118 int dma_tx_channel; 118 int tx_channel;
119 int dma_rx_channel; 119 int rx_channel;
120 int dummy_param_slot; 120 int dummy_param_slot;
121 enum dma_event_q eventq; 121 enum dma_event_q eventq;
122}; 122};
@@ -138,7 +138,7 @@ struct davinci_spi {
138 u8 rx_tmp_buf[SPI_TMP_BUFSZ]; 138 u8 rx_tmp_buf[SPI_TMP_BUFSZ];
139 int rcount; 139 int rcount;
140 int wcount; 140 int wcount;
141 struct davinci_spi_dma dma_channels; 141 struct davinci_spi_dma dma;
142 struct davinci_spi_platform_data *pdata; 142 struct davinci_spi_platform_data *pdata;
143 143
144 void (*get_rx)(u32 rx_data, struct davinci_spi *); 144 void (*get_rx)(u32 rx_data, struct davinci_spi *);
@@ -149,42 +149,42 @@ struct davinci_spi {
149 149
150static struct davinci_spi_config davinci_spi_default_cfg; 150static struct davinci_spi_config davinci_spi_default_cfg;
151 151
152static void davinci_spi_rx_buf_u8(u32 data, struct davinci_spi *davinci_spi) 152static void davinci_spi_rx_buf_u8(u32 data, struct davinci_spi *dspi)
153{ 153{
154 if (davinci_spi->rx) { 154 if (dspi->rx) {
155 u8 *rx = davinci_spi->rx; 155 u8 *rx = dspi->rx;
156 *rx++ = (u8)data; 156 *rx++ = (u8)data;
157 davinci_spi->rx = rx; 157 dspi->rx = rx;
158 } 158 }
159} 159}
160 160
161static void davinci_spi_rx_buf_u16(u32 data, struct davinci_spi *davinci_spi) 161static void davinci_spi_rx_buf_u16(u32 data, struct davinci_spi *dspi)
162{ 162{
163 if (davinci_spi->rx) { 163 if (dspi->rx) {
164 u16 *rx = davinci_spi->rx; 164 u16 *rx = dspi->rx;
165 *rx++ = (u16)data; 165 *rx++ = (u16)data;
166 davinci_spi->rx = rx; 166 dspi->rx = rx;
167 } 167 }
168} 168}
169 169
170static u32 davinci_spi_tx_buf_u8(struct davinci_spi *davinci_spi) 170static u32 davinci_spi_tx_buf_u8(struct davinci_spi *dspi)
171{ 171{
172 u32 data = 0; 172 u32 data = 0;
173 if (davinci_spi->tx) { 173 if (dspi->tx) {
174 const u8 *tx = davinci_spi->tx; 174 const u8 *tx = dspi->tx;
175 data = *tx++; 175 data = *tx++;
176 davinci_spi->tx = tx; 176 dspi->tx = tx;
177 } 177 }
178 return data; 178 return data;
179} 179}
180 180
181static u32 davinci_spi_tx_buf_u16(struct davinci_spi *davinci_spi) 181static u32 davinci_spi_tx_buf_u16(struct davinci_spi *dspi)
182{ 182{
183 u32 data = 0; 183 u32 data = 0;
184 if (davinci_spi->tx) { 184 if (dspi->tx) {
185 const u16 *tx = davinci_spi->tx; 185 const u16 *tx = dspi->tx;
186 data = *tx++; 186 data = *tx++;
187 davinci_spi->tx = tx; 187 dspi->tx = tx;
188 } 188 }
189 return data; 189 return data;
190} 190}
@@ -210,14 +210,14 @@ static inline void clear_io_bits(void __iomem *addr, u32 bits)
210 */ 210 */
211static void davinci_spi_chipselect(struct spi_device *spi, int value) 211static void davinci_spi_chipselect(struct spi_device *spi, int value)
212{ 212{
213 struct davinci_spi *davinci_spi; 213 struct davinci_spi *dspi;
214 struct davinci_spi_platform_data *pdata; 214 struct davinci_spi_platform_data *pdata;
215 u8 chip_sel = spi->chip_select; 215 u8 chip_sel = spi->chip_select;
216 u16 spidat1_cfg = CS_DEFAULT; 216 u16 spidat1 = CS_DEFAULT;
217 bool gpio_chipsel = false; 217 bool gpio_chipsel = false;
218 218
219 davinci_spi = spi_master_get_devdata(spi->master); 219 dspi = spi_master_get_devdata(spi->master);
220 pdata = davinci_spi->pdata; 220 pdata = dspi->pdata;
221 221
222 if (pdata->chip_sel && chip_sel < pdata->num_chipselect && 222 if (pdata->chip_sel && chip_sel < pdata->num_chipselect &&
223 pdata->chip_sel[chip_sel] != SPI_INTERN_CS) 223 pdata->chip_sel[chip_sel] != SPI_INTERN_CS)
@@ -234,11 +234,11 @@ static void davinci_spi_chipselect(struct spi_device *spi, int value)
234 gpio_set_value(pdata->chip_sel[chip_sel], 1); 234 gpio_set_value(pdata->chip_sel[chip_sel], 1);
235 } else { 235 } else {
236 if (value == BITBANG_CS_ACTIVE) { 236 if (value == BITBANG_CS_ACTIVE) {
237 spidat1_cfg |= SPIDAT1_CSHOLD_MASK; 237 spidat1 |= SPIDAT1_CSHOLD_MASK;
238 spidat1_cfg &= ~(0x1 << chip_sel); 238 spidat1 &= ~(0x1 << chip_sel);
239 } 239 }
240 240
241 iowrite16(spidat1_cfg, davinci_spi->base + SPIDAT1 + 2); 241 iowrite16(spidat1, dspi->base + SPIDAT1 + 2);
242 } 242 }
243} 243}
244 244
@@ -252,12 +252,12 @@ static void davinci_spi_chipselect(struct spi_device *spi, int value)
252 * Returns: calculated prescale - 1 for easy programming into SPI registers 252 * Returns: calculated prescale - 1 for easy programming into SPI registers
253 * or negative error number if valid prescalar cannot be updated. 253 * or negative error number if valid prescalar cannot be updated.
254 */ 254 */
255static inline int davinci_spi_get_prescale(struct davinci_spi *davinci_spi, 255static inline int davinci_spi_get_prescale(struct davinci_spi *dspi,
256 u32 max_speed_hz) 256 u32 max_speed_hz)
257{ 257{
258 int ret; 258 int ret;
259 259
260 ret = DIV_ROUND_UP(clk_get_rate(davinci_spi->clk), max_speed_hz); 260 ret = DIV_ROUND_UP(clk_get_rate(dspi->clk), max_speed_hz);
261 261
262 if (ret < 3 || ret > 256) 262 if (ret < 3 || ret > 256)
263 return -EINVAL; 263 return -EINVAL;
@@ -278,12 +278,12 @@ static int davinci_spi_setup_transfer(struct spi_device *spi,
278 struct spi_transfer *t) 278 struct spi_transfer *t)
279{ 279{
280 280
281 struct davinci_spi *davinci_spi; 281 struct davinci_spi *dspi;
282 struct davinci_spi_config *spicfg; 282 struct davinci_spi_config *spicfg;
283 u8 bits_per_word = 0; 283 u8 bits_per_word = 0;
284 u32 hz = 0, spifmt = 0, prescale = 0; 284 u32 hz = 0, spifmt = 0, prescale = 0;
285 285
286 davinci_spi = spi_master_get_devdata(spi->master); 286 dspi = spi_master_get_devdata(spi->master);
287 spicfg = (struct davinci_spi_config *)spi->controller_data; 287 spicfg = (struct davinci_spi_config *)spi->controller_data;
288 if (!spicfg) 288 if (!spicfg)
289 spicfg = &davinci_spi_default_cfg; 289 spicfg = &davinci_spi_default_cfg;
@@ -302,13 +302,13 @@ static int davinci_spi_setup_transfer(struct spi_device *spi,
302 * 8bit, 16bit or 32bit transfer 302 * 8bit, 16bit or 32bit transfer
303 */ 303 */
304 if (bits_per_word <= 8 && bits_per_word >= 2) { 304 if (bits_per_word <= 8 && bits_per_word >= 2) {
305 davinci_spi->get_rx = davinci_spi_rx_buf_u8; 305 dspi->get_rx = davinci_spi_rx_buf_u8;
306 davinci_spi->get_tx = davinci_spi_tx_buf_u8; 306 dspi->get_tx = davinci_spi_tx_buf_u8;
307 davinci_spi->bytes_per_word[spi->chip_select] = 1; 307 dspi->bytes_per_word[spi->chip_select] = 1;
308 } else if (bits_per_word <= 16 && bits_per_word >= 2) { 308 } else if (bits_per_word <= 16 && bits_per_word >= 2) {
309 davinci_spi->get_rx = davinci_spi_rx_buf_u16; 309 dspi->get_rx = davinci_spi_rx_buf_u16;
310 davinci_spi->get_tx = davinci_spi_tx_buf_u16; 310 dspi->get_tx = davinci_spi_tx_buf_u16;
311 davinci_spi->bytes_per_word[spi->chip_select] = 2; 311 dspi->bytes_per_word[spi->chip_select] = 2;
312 } else 312 } else
313 return -EINVAL; 313 return -EINVAL;
314 314
@@ -317,7 +317,7 @@ static int davinci_spi_setup_transfer(struct spi_device *spi,
317 317
318 /* Set up SPIFMTn register, unique to this chipselect. */ 318 /* Set up SPIFMTn register, unique to this chipselect. */
319 319
320 prescale = davinci_spi_get_prescale(davinci_spi, hz); 320 prescale = davinci_spi_get_prescale(dspi, hz);
321 if (prescale < 0) 321 if (prescale < 0)
322 return prescale; 322 return prescale;
323 323
@@ -345,7 +345,7 @@ static int davinci_spi_setup_transfer(struct spi_device *spi,
345 * - 4 pin with enable is (SPI_READY | SPI_NO_CS) 345 * - 4 pin with enable is (SPI_READY | SPI_NO_CS)
346 */ 346 */
347 347
348 if (davinci_spi->version == SPI_VERSION_2) { 348 if (dspi->version == SPI_VERSION_2) {
349 349
350 u32 delay = 0; 350 u32 delay = 0;
351 351
@@ -375,10 +375,10 @@ static int davinci_spi_setup_transfer(struct spi_device *spi,
375 & SPIDELAY_C2EDELAY_MASK; 375 & SPIDELAY_C2EDELAY_MASK;
376 } 376 }
377 377
378 iowrite32(delay, davinci_spi->base + SPIDELAY); 378 iowrite32(delay, dspi->base + SPIDELAY);
379 } 379 }
380 380
381 iowrite32(spifmt, davinci_spi->base + SPIFMT0); 381 iowrite32(spifmt, dspi->base + SPIFMT0);
382 382
383 return 0; 383 return 0;
384} 384}
@@ -392,11 +392,11 @@ static int davinci_spi_setup_transfer(struct spi_device *spi,
392static int davinci_spi_setup(struct spi_device *spi) 392static int davinci_spi_setup(struct spi_device *spi)
393{ 393{
394 int retval = 0; 394 int retval = 0;
395 struct davinci_spi *davinci_spi; 395 struct davinci_spi *dspi;
396 struct davinci_spi_platform_data *pdata; 396 struct davinci_spi_platform_data *pdata;
397 397
398 davinci_spi = spi_master_get_devdata(spi->master); 398 dspi = spi_master_get_devdata(spi->master);
399 pdata = davinci_spi->pdata; 399 pdata = dspi->pdata;
400 400
401 /* if bits per word length is zero then set it default 8 */ 401 /* if bits per word length is zero then set it default 8 */
402 if (!spi->bits_per_word) 402 if (!spi->bits_per_word)
@@ -405,28 +405,24 @@ static int davinci_spi_setup(struct spi_device *spi)
405 if (!(spi->mode & SPI_NO_CS)) { 405 if (!(spi->mode & SPI_NO_CS)) {
406 if ((pdata->chip_sel == NULL) || 406 if ((pdata->chip_sel == NULL) ||
407 (pdata->chip_sel[spi->chip_select] == SPI_INTERN_CS)) 407 (pdata->chip_sel[spi->chip_select] == SPI_INTERN_CS))
408 set_io_bits(davinci_spi->base + SPIPC0, 408 set_io_bits(dspi->base + SPIPC0, 1 << spi->chip_select);
409 1 << spi->chip_select);
410 409
411 } 410 }
412 411
413 if (spi->mode & SPI_READY) 412 if (spi->mode & SPI_READY)
414 set_io_bits(davinci_spi->base + SPIPC0, SPIPC0_SPIENA_MASK); 413 set_io_bits(dspi->base + SPIPC0, SPIPC0_SPIENA_MASK);
415 414
416 if (spi->mode & SPI_LOOP) 415 if (spi->mode & SPI_LOOP)
417 set_io_bits(davinci_spi->base + SPIGCR1, 416 set_io_bits(dspi->base + SPIGCR1, SPIGCR1_LOOPBACK_MASK);
418 SPIGCR1_LOOPBACK_MASK);
419 else 417 else
420 clear_io_bits(davinci_spi->base + SPIGCR1, 418 clear_io_bits(dspi->base + SPIGCR1, SPIGCR1_LOOPBACK_MASK);
421 SPIGCR1_LOOPBACK_MASK);
422 419
423 return retval; 420 return retval;
424} 421}
425 422
426static int davinci_spi_check_error(struct davinci_spi *davinci_spi, 423static int davinci_spi_check_error(struct davinci_spi *dspi, int int_status)
427 int int_status)
428{ 424{
429 struct device *sdev = davinci_spi->bitbang.master->dev.parent; 425 struct device *sdev = dspi->bitbang.master->dev.parent;
430 426
431 if (int_status & SPIFLG_TIMEOUT_MASK) { 427 if (int_status & SPIFLG_TIMEOUT_MASK) {
432 dev_dbg(sdev, "SPI Time-out Error\n"); 428 dev_dbg(sdev, "SPI Time-out Error\n");
@@ -441,7 +437,7 @@ static int davinci_spi_check_error(struct davinci_spi *davinci_spi,
441 return -EIO; 437 return -EIO;
442 } 438 }
443 439
444 if (davinci_spi->version == SPI_VERSION_2) { 440 if (dspi->version == SPI_VERSION_2) {
445 if (int_status & SPIFLG_DLEN_ERR_MASK) { 441 if (int_status & SPIFLG_DLEN_ERR_MASK) {
446 dev_dbg(sdev, "SPI Data Length Error\n"); 442 dev_dbg(sdev, "SPI Data Length Error\n");
447 return -EIO; 443 return -EIO;
@@ -465,35 +461,35 @@ static int davinci_spi_check_error(struct davinci_spi *davinci_spi,
465 461
466/** 462/**
467 * davinci_spi_process_events - check for and handle any SPI controller events 463 * davinci_spi_process_events - check for and handle any SPI controller events
468 * @davinci_spi: the controller data 464 * @dspi: the controller data
469 * 465 *
470 * This function will check the SPIFLG register and handle any events that are 466 * This function will check the SPIFLG register and handle any events that are
471 * detected there 467 * detected there
472 */ 468 */
473static int davinci_spi_process_events(struct davinci_spi *davinci_spi) 469static int davinci_spi_process_events(struct davinci_spi *dspi)
474{ 470{
475 u32 buf, status, errors = 0, data1_reg_val; 471 u32 buf, status, errors = 0, spidat1;
476 472
477 buf = ioread32(davinci_spi->base + SPIBUF); 473 buf = ioread32(dspi->base + SPIBUF);
478 474
479 if (davinci_spi->rcount > 0 && !(buf & SPIBUF_RXEMPTY_MASK)) { 475 if (dspi->rcount > 0 && !(buf & SPIBUF_RXEMPTY_MASK)) {
480 davinci_spi->get_rx(buf & 0xFFFF, davinci_spi); 476 dspi->get_rx(buf & 0xFFFF, dspi);
481 davinci_spi->rcount--; 477 dspi->rcount--;
482 } 478 }
483 479
484 status = ioread32(davinci_spi->base + SPIFLG); 480 status = ioread32(dspi->base + SPIFLG);
485 481
486 if (unlikely(status & SPIFLG_ERROR_MASK)) { 482 if (unlikely(status & SPIFLG_ERROR_MASK)) {
487 errors = status & SPIFLG_ERROR_MASK; 483 errors = status & SPIFLG_ERROR_MASK;
488 goto out; 484 goto out;
489 } 485 }
490 486
491 if (davinci_spi->wcount > 0 && !(buf & SPIBUF_TXFULL_MASK)) { 487 if (dspi->wcount > 0 && !(buf & SPIBUF_TXFULL_MASK)) {
492 data1_reg_val = ioread32(davinci_spi->base + SPIDAT1); 488 spidat1 = ioread32(dspi->base + SPIDAT1);
493 davinci_spi->wcount--; 489 dspi->wcount--;
494 data1_reg_val &= ~0xFFFF; 490 spidat1 &= ~0xFFFF;
495 data1_reg_val |= 0xFFFF & davinci_spi->get_tx(davinci_spi); 491 spidat1 |= 0xFFFF & dspi->get_tx(dspi);
496 iowrite32(data1_reg_val, davinci_spi->base + SPIDAT1); 492 iowrite32(spidat1, dspi->base + SPIDAT1);
497 } 493 }
498 494
499out: 495out:
@@ -502,21 +498,20 @@ out:
502 498
503static void davinci_spi_dma_callback(unsigned lch, u16 status, void *data) 499static void davinci_spi_dma_callback(unsigned lch, u16 status, void *data)
504{ 500{
505 struct davinci_spi *davinci_spi = data; 501 struct davinci_spi *dspi = data;
506 struct davinci_spi_dma *davinci_spi_dma = &davinci_spi->dma_channels; 502 struct davinci_spi_dma *dma = &dspi->dma;
507 503
508 edma_stop(lch); 504 edma_stop(lch);
509 505
510 if (status == DMA_COMPLETE) { 506 if (status == DMA_COMPLETE) {
511 if (lch == davinci_spi_dma->dma_rx_channel) 507 if (lch == dma->rx_channel)
512 davinci_spi->rcount = 0; 508 dspi->rcount = 0;
513 if (lch == davinci_spi_dma->dma_tx_channel) 509 if (lch == dma->tx_channel)
514 davinci_spi->wcount = 0; 510 dspi->wcount = 0;
515 } 511 }
516 512
517 if ((!davinci_spi->wcount && !davinci_spi->rcount) || 513 if ((!dspi->wcount && !dspi->rcount) || (status != DMA_COMPLETE))
518 (status != DMA_COMPLETE)) 514 complete(&dspi->done);
519 complete(&davinci_spi->done);
520} 515}
521 516
522/** 517/**
@@ -530,57 +525,57 @@ static void davinci_spi_dma_callback(unsigned lch, u16 status, void *data)
530 */ 525 */
531static int davinci_spi_bufs(struct spi_device *spi, struct spi_transfer *t) 526static int davinci_spi_bufs(struct spi_device *spi, struct spi_transfer *t)
532{ 527{
533 struct davinci_spi *davinci_spi; 528 struct davinci_spi *dspi;
534 int data_type, ret; 529 int data_type, ret;
535 u32 tx_data, data1_reg_val; 530 u32 tx_data, spidat1;
536 u32 errors = 0; 531 u32 errors = 0;
537 struct davinci_spi_config *spicfg; 532 struct davinci_spi_config *spicfg;
538 struct davinci_spi_platform_data *pdata; 533 struct davinci_spi_platform_data *pdata;
539 unsigned uninitialized_var(rx_buf_count); 534 unsigned uninitialized_var(rx_buf_count);
540 struct device *sdev; 535 struct device *sdev;
541 536
542 davinci_spi = spi_master_get_devdata(spi->master); 537 dspi = spi_master_get_devdata(spi->master);
543 pdata = davinci_spi->pdata; 538 pdata = dspi->pdata;
544 spicfg = (struct davinci_spi_config *)spi->controller_data; 539 spicfg = (struct davinci_spi_config *)spi->controller_data;
545 if (!spicfg) 540 if (!spicfg)
546 spicfg = &davinci_spi_default_cfg; 541 spicfg = &davinci_spi_default_cfg;
547 sdev = davinci_spi->bitbang.master->dev.parent; 542 sdev = dspi->bitbang.master->dev.parent;
548 543
549 /* convert len to words based on bits_per_word */ 544 /* convert len to words based on bits_per_word */
550 data_type = davinci_spi->bytes_per_word[spi->chip_select]; 545 data_type = dspi->bytes_per_word[spi->chip_select];
551 546
552 davinci_spi->tx = t->tx_buf; 547 dspi->tx = t->tx_buf;
553 davinci_spi->rx = t->rx_buf; 548 dspi->rx = t->rx_buf;
554 davinci_spi->wcount = t->len / data_type; 549 dspi->wcount = t->len / data_type;
555 davinci_spi->rcount = davinci_spi->wcount; 550 dspi->rcount = dspi->wcount;
556 551
557 data1_reg_val = ioread32(davinci_spi->base + SPIDAT1); 552 spidat1 = ioread32(dspi->base + SPIDAT1);
558 553
559 clear_io_bits(davinci_spi->base + SPIGCR1, SPIGCR1_POWERDOWN_MASK); 554 clear_io_bits(dspi->base + SPIGCR1, SPIGCR1_POWERDOWN_MASK);
560 set_io_bits(davinci_spi->base + SPIGCR1, SPIGCR1_SPIENA_MASK); 555 set_io_bits(dspi->base + SPIGCR1, SPIGCR1_SPIENA_MASK);
561 556
562 INIT_COMPLETION(davinci_spi->done); 557 INIT_COMPLETION(dspi->done);
563 558
564 if (spicfg->io_type == SPI_IO_TYPE_INTR) 559 if (spicfg->io_type == SPI_IO_TYPE_INTR)
565 set_io_bits(davinci_spi->base + SPIINT, SPIINT_MASKINT); 560 set_io_bits(dspi->base + SPIINT, SPIINT_MASKINT);
566 561
567 if (spicfg->io_type != SPI_IO_TYPE_DMA) { 562 if (spicfg->io_type != SPI_IO_TYPE_DMA) {
568 /* start the transfer */ 563 /* start the transfer */
569 davinci_spi->wcount--; 564 dspi->wcount--;
570 tx_data = davinci_spi->get_tx(davinci_spi); 565 tx_data = dspi->get_tx(dspi);
571 data1_reg_val &= 0xFFFF0000; 566 spidat1 &= 0xFFFF0000;
572 data1_reg_val |= tx_data & 0xFFFF; 567 spidat1 |= tx_data & 0xFFFF;
573 iowrite32(data1_reg_val, davinci_spi->base + SPIDAT1); 568 iowrite32(spidat1, dspi->base + SPIDAT1);
574 } else { 569 } else {
575 struct davinci_spi_dma *davinci_spi_dma; 570 struct davinci_spi_dma *dma;
576 unsigned long tx_reg, rx_reg; 571 unsigned long tx_reg, rx_reg;
577 struct edmacc_param param; 572 struct edmacc_param param;
578 void *rx_buf; 573 void *rx_buf;
579 574
580 davinci_spi_dma = &davinci_spi->dma_channels; 575 dma = &dspi->dma;
581 576
582 tx_reg = (unsigned long)davinci_spi->pbase + SPIDAT1; 577 tx_reg = (unsigned long)dspi->pbase + SPIDAT1;
583 rx_reg = (unsigned long)davinci_spi->pbase + SPIBUF; 578 rx_reg = (unsigned long)dspi->pbase + SPIBUF;
584 579
585 /* 580 /*
586 * Transmit DMA setup 581 * Transmit DMA setup
@@ -596,26 +591,24 @@ static int davinci_spi_bufs(struct spi_device *spi, struct spi_transfer *t)
596 591
597 if (t->tx_buf) { 592 if (t->tx_buf) {
598 t->tx_dma = dma_map_single(&spi->dev, (void *)t->tx_buf, 593 t->tx_dma = dma_map_single(&spi->dev, (void *)t->tx_buf,
599 davinci_spi->wcount, DMA_TO_DEVICE); 594 dspi->wcount, DMA_TO_DEVICE);
600 if (dma_mapping_error(&spi->dev, t->tx_dma)) { 595 if (dma_mapping_error(&spi->dev, t->tx_dma)) {
601 dev_dbg(sdev, "Unable to DMA map %d bytes" 596 dev_dbg(sdev, "Unable to DMA map %d bytes"
602 "TX buffer\n", 597 "TX buffer\n", dspi->wcount);
603 davinci_spi->wcount);
604 return -ENOMEM; 598 return -ENOMEM;
605 } 599 }
606 } 600 }
607 601
608 param.opt = TCINTEN | EDMA_TCC(davinci_spi_dma->dma_tx_channel); 602 param.opt = TCINTEN | EDMA_TCC(dma->tx_channel);
609 param.src = t->tx_buf ? t->tx_dma : tx_reg; 603 param.src = t->tx_buf ? t->tx_dma : tx_reg;
610 param.a_b_cnt = davinci_spi->wcount << 16 | data_type; 604 param.a_b_cnt = dspi->wcount << 16 | data_type;
611 param.dst = tx_reg; 605 param.dst = tx_reg;
612 param.src_dst_bidx = t->tx_buf ? data_type : 0; 606 param.src_dst_bidx = t->tx_buf ? data_type : 0;
613 param.link_bcntrld = 0xffff; 607 param.link_bcntrld = 0xffff;
614 param.src_dst_cidx = 0; 608 param.src_dst_cidx = 0;
615 param.ccnt = 1; 609 param.ccnt = 1;
616 edma_write_slot(davinci_spi_dma->dma_tx_channel, &param); 610 edma_write_slot(dma->tx_channel, &param);
617 edma_link(davinci_spi_dma->dma_tx_channel, 611 edma_link(dma->tx_channel, dma->dummy_param_slot);
618 davinci_spi_dma->dummy_param_slot);
619 612
620 /* 613 /*
621 * Receive DMA setup 614 * Receive DMA setup
@@ -631,10 +624,10 @@ static int davinci_spi_bufs(struct spi_device *spi, struct spi_transfer *t)
631 624
632 if (t->rx_buf) { 625 if (t->rx_buf) {
633 rx_buf = t->rx_buf; 626 rx_buf = t->rx_buf;
634 rx_buf_count = davinci_spi->rcount; 627 rx_buf_count = dspi->rcount;
635 } else { 628 } else {
636 rx_buf = davinci_spi->rx_tmp_buf; 629 rx_buf = dspi->rx_tmp_buf;
637 rx_buf_count = sizeof(davinci_spi->rx_tmp_buf); 630 rx_buf_count = sizeof(dspi->rx_tmp_buf);
638 } 631 }
639 632
640 t->rx_dma = dma_map_single(&spi->dev, rx_buf, rx_buf_count, 633 t->rx_dma = dma_map_single(&spi->dev, rx_buf, rx_buf_count,
@@ -643,71 +636,69 @@ static int davinci_spi_bufs(struct spi_device *spi, struct spi_transfer *t)
643 dev_dbg(sdev, "Couldn't DMA map a %d bytes RX buffer\n", 636 dev_dbg(sdev, "Couldn't DMA map a %d bytes RX buffer\n",
644 rx_buf_count); 637 rx_buf_count);
645 if (t->tx_buf) 638 if (t->tx_buf)
646 dma_unmap_single(NULL, t->tx_dma, 639 dma_unmap_single(NULL, t->tx_dma, dspi->wcount,
647 davinci_spi->wcount, 640 DMA_TO_DEVICE);
648 DMA_TO_DEVICE);
649 return -ENOMEM; 641 return -ENOMEM;
650 } 642 }
651 643
652 param.opt = TCINTEN | EDMA_TCC(davinci_spi_dma->dma_rx_channel); 644 param.opt = TCINTEN | EDMA_TCC(dma->rx_channel);
653 param.src = rx_reg; 645 param.src = rx_reg;
654 param.a_b_cnt = davinci_spi->rcount << 16 | data_type; 646 param.a_b_cnt = dspi->rcount << 16 | data_type;
655 param.dst = t->rx_dma; 647 param.dst = t->rx_dma;
656 param.src_dst_bidx = (t->rx_buf ? data_type : 0) << 16; 648 param.src_dst_bidx = (t->rx_buf ? data_type : 0) << 16;
657 param.link_bcntrld = 0xffff; 649 param.link_bcntrld = 0xffff;
658 param.src_dst_cidx = 0; 650 param.src_dst_cidx = 0;
659 param.ccnt = 1; 651 param.ccnt = 1;
660 edma_write_slot(davinci_spi_dma->dma_rx_channel, &param); 652 edma_write_slot(dma->rx_channel, &param);
661 653
662 if (pdata->cshold_bug) 654 if (pdata->cshold_bug)
663 iowrite16(data1_reg_val >> 16, 655 iowrite16(spidat1 >> 16, dspi->base + SPIDAT1 + 2);
664 davinci_spi->base + SPIDAT1 + 2);
665 656
666 edma_start(davinci_spi_dma->dma_rx_channel); 657 edma_start(dma->rx_channel);
667 edma_start(davinci_spi_dma->dma_tx_channel); 658 edma_start(dma->tx_channel);
668 set_io_bits(davinci_spi->base + SPIINT, SPIINT_DMA_REQ_EN); 659 set_io_bits(dspi->base + SPIINT, SPIINT_DMA_REQ_EN);
669 } 660 }
670 661
671 /* Wait for the transfer to complete */ 662 /* Wait for the transfer to complete */
672 if (spicfg->io_type != SPI_IO_TYPE_POLL) { 663 if (spicfg->io_type != SPI_IO_TYPE_POLL) {
673 wait_for_completion_interruptible(&(davinci_spi->done)); 664 wait_for_completion_interruptible(&(dspi->done));
674 } else { 665 } else {
675 while (davinci_spi->rcount > 0 || davinci_spi->wcount > 0) { 666 while (dspi->rcount > 0 || dspi->wcount > 0) {
676 errors = davinci_spi_process_events(davinci_spi); 667 errors = davinci_spi_process_events(dspi);
677 if (errors) 668 if (errors)
678 break; 669 break;
679 cpu_relax(); 670 cpu_relax();
680 } 671 }
681 } 672 }
682 673
683 clear_io_bits(davinci_spi->base + SPIINT, SPIINT_MASKALL); 674 clear_io_bits(dspi->base + SPIINT, SPIINT_MASKALL);
684 if (spicfg->io_type == SPI_IO_TYPE_DMA) { 675 if (spicfg->io_type == SPI_IO_TYPE_DMA) {
685 676
686 if (t->tx_buf) 677 if (t->tx_buf)
687 dma_unmap_single(NULL, t->tx_dma, davinci_spi->wcount, 678 dma_unmap_single(NULL, t->tx_dma, dspi->wcount,
688 DMA_TO_DEVICE); 679 DMA_TO_DEVICE);
689 680
690 dma_unmap_single(NULL, t->rx_dma, rx_buf_count, 681 dma_unmap_single(NULL, t->rx_dma, rx_buf_count,
691 DMA_FROM_DEVICE); 682 DMA_FROM_DEVICE);
692 683
693 clear_io_bits(davinci_spi->base + SPIINT, SPIINT_DMA_REQ_EN); 684 clear_io_bits(dspi->base + SPIINT, SPIINT_DMA_REQ_EN);
694 } 685 }
695 686
696 clear_io_bits(davinci_spi->base + SPIGCR1, SPIGCR1_SPIENA_MASK); 687 clear_io_bits(dspi->base + SPIGCR1, SPIGCR1_SPIENA_MASK);
697 set_io_bits(davinci_spi->base + SPIGCR1, SPIGCR1_POWERDOWN_MASK); 688 set_io_bits(dspi->base + SPIGCR1, SPIGCR1_POWERDOWN_MASK);
698 689
699 /* 690 /*
700 * Check for bit error, desync error,parity error,timeout error and 691 * Check for bit error, desync error,parity error,timeout error and
701 * receive overflow errors 692 * receive overflow errors
702 */ 693 */
703 if (errors) { 694 if (errors) {
704 ret = davinci_spi_check_error(davinci_spi, errors); 695 ret = davinci_spi_check_error(dspi, errors);
705 WARN(!ret, "%s: error reported but no error found!\n", 696 WARN(!ret, "%s: error reported but no error found!\n",
706 dev_name(&spi->dev)); 697 dev_name(&spi->dev));
707 return ret; 698 return ret;
708 } 699 }
709 700
710 if (davinci_spi->rcount != 0 || davinci_spi->wcount != 0) { 701 if (dspi->rcount != 0 || dspi->wcount != 0) {
711 dev_err(sdev, "SPI data transfer error\n"); 702 dev_err(sdev, "SPI data transfer error\n");
712 return -EIO; 703 return -EIO;
713 } 704 }
@@ -726,60 +717,56 @@ static int davinci_spi_bufs(struct spi_device *spi, struct spi_transfer *t)
726 * If transfer length is zero then it will indicate the COMPLETION so that 717 * If transfer length is zero then it will indicate the COMPLETION so that
727 * davinci_spi_bufs function can go ahead. 718 * davinci_spi_bufs function can go ahead.
728 */ 719 */
729static irqreturn_t davinci_spi_irq(s32 irq, void *context_data) 720static irqreturn_t davinci_spi_irq(s32 irq, void *data)
730{ 721{
731 struct davinci_spi *davinci_spi = context_data; 722 struct davinci_spi *dspi = data;
732 int status; 723 int status;
733 724
734 status = davinci_spi_process_events(davinci_spi); 725 status = davinci_spi_process_events(dspi);
735 if (unlikely(status != 0)) 726 if (unlikely(status != 0))
736 clear_io_bits(davinci_spi->base + SPIINT, SPIINT_MASKINT); 727 clear_io_bits(dspi->base + SPIINT, SPIINT_MASKINT);
737 728
738 if ((!davinci_spi->rcount && !davinci_spi->wcount) || status) 729 if ((!dspi->rcount && !dspi->wcount) || status)
739 complete(&davinci_spi->done); 730 complete(&dspi->done);
740 731
741 return IRQ_HANDLED; 732 return IRQ_HANDLED;
742} 733}
743 734
744static int davinci_spi_request_dma(struct davinci_spi *davinci_spi) 735static int davinci_spi_request_dma(struct davinci_spi *dspi)
745{ 736{
746 int r; 737 int r;
747 struct davinci_spi_dma *davinci_spi_dma = &davinci_spi->dma_channels; 738 struct davinci_spi_dma *dma = &dspi->dma;
748 739
749 r = edma_alloc_channel(davinci_spi_dma->dma_rx_channel, 740 r = edma_alloc_channel(dma->rx_channel, davinci_spi_dma_callback, dspi,
750 davinci_spi_dma_callback, davinci_spi, 741 dma->eventq);
751 davinci_spi_dma->eventq);
752 if (r < 0) { 742 if (r < 0) {
753 pr_err("Unable to request DMA channel for SPI RX\n"); 743 pr_err("Unable to request DMA channel for SPI RX\n");
754 r = -EAGAIN; 744 r = -EAGAIN;
755 goto rx_dma_failed; 745 goto rx_dma_failed;
756 } 746 }
757 747
758 r = edma_alloc_channel(davinci_spi_dma->dma_tx_channel, 748 r = edma_alloc_channel(dma->tx_channel, davinci_spi_dma_callback, dspi,
759 davinci_spi_dma_callback, davinci_spi, 749 dma->eventq);
760 davinci_spi_dma->eventq);
761 if (r < 0) { 750 if (r < 0) {
762 pr_err("Unable to request DMA channel for SPI TX\n"); 751 pr_err("Unable to request DMA channel for SPI TX\n");
763 r = -EAGAIN; 752 r = -EAGAIN;
764 goto tx_dma_failed; 753 goto tx_dma_failed;
765 } 754 }
766 755
767 r = edma_alloc_slot(EDMA_CTLR(davinci_spi_dma->dma_tx_channel), 756 r = edma_alloc_slot(EDMA_CTLR(dma->tx_channel), EDMA_SLOT_ANY);
768 EDMA_SLOT_ANY);
769 if (r < 0) { 757 if (r < 0) {
770 pr_err("Unable to request SPI TX DMA param slot\n"); 758 pr_err("Unable to request SPI TX DMA param slot\n");
771 r = -EAGAIN; 759 r = -EAGAIN;
772 goto param_failed; 760 goto param_failed;
773 } 761 }
774 davinci_spi_dma->dummy_param_slot = r; 762 dma->dummy_param_slot = r;
775 edma_link(davinci_spi_dma->dummy_param_slot, 763 edma_link(dma->dummy_param_slot, dma->dummy_param_slot);
776 davinci_spi_dma->dummy_param_slot);
777 764
778 return 0; 765 return 0;
779param_failed: 766param_failed:
780 edma_free_channel(davinci_spi_dma->dma_tx_channel); 767 edma_free_channel(dma->tx_channel);
781tx_dma_failed: 768tx_dma_failed:
782 edma_free_channel(davinci_spi_dma->dma_rx_channel); 769 edma_free_channel(dma->rx_channel);
783rx_dma_failed: 770rx_dma_failed:
784 return r; 771 return r;
785} 772}
@@ -798,7 +785,7 @@ rx_dma_failed:
798static int davinci_spi_probe(struct platform_device *pdev) 785static int davinci_spi_probe(struct platform_device *pdev)
799{ 786{
800 struct spi_master *master; 787 struct spi_master *master;
801 struct davinci_spi *davinci_spi; 788 struct davinci_spi *dspi;
802 struct davinci_spi_platform_data *pdata; 789 struct davinci_spi_platform_data *pdata;
803 struct resource *r, *mem; 790 struct resource *r, *mem;
804 resource_size_t dma_rx_chan = SPI_NO_RESOURCE; 791 resource_size_t dma_rx_chan = SPI_NO_RESOURCE;
@@ -821,8 +808,8 @@ static int davinci_spi_probe(struct platform_device *pdev)
821 808
822 dev_set_drvdata(&pdev->dev, master); 809 dev_set_drvdata(&pdev->dev, master);
823 810
824 davinci_spi = spi_master_get_devdata(master); 811 dspi = spi_master_get_devdata(master);
825 if (davinci_spi == NULL) { 812 if (dspi == NULL) {
826 ret = -ENOENT; 813 ret = -ENOENT;
827 goto free_master; 814 goto free_master;
828 } 815 }
@@ -833,8 +820,8 @@ static int davinci_spi_probe(struct platform_device *pdev)
833 goto free_master; 820 goto free_master;
834 } 821 }
835 822
836 davinci_spi->pbase = r->start; 823 dspi->pbase = r->start;
837 davinci_spi->pdata = pdata; 824 dspi->pdata = pdata;
838 825
839 mem = request_mem_region(r->start, resource_size(r), pdev->name); 826 mem = request_mem_region(r->start, resource_size(r), pdev->name);
840 if (mem == NULL) { 827 if (mem == NULL) {
@@ -842,48 +829,48 @@ static int davinci_spi_probe(struct platform_device *pdev)
842 goto free_master; 829 goto free_master;
843 } 830 }
844 831
845 davinci_spi->base = ioremap(r->start, resource_size(r)); 832 dspi->base = ioremap(r->start, resource_size(r));
846 if (davinci_spi->base == NULL) { 833 if (dspi->base == NULL) {
847 ret = -ENOMEM; 834 ret = -ENOMEM;
848 goto release_region; 835 goto release_region;
849 } 836 }
850 837
851 davinci_spi->irq = platform_get_irq(pdev, 0); 838 dspi->irq = platform_get_irq(pdev, 0);
852 if (davinci_spi->irq <= 0) { 839 if (dspi->irq <= 0) {
853 ret = -EINVAL; 840 ret = -EINVAL;
854 goto unmap_io; 841 goto unmap_io;
855 } 842 }
856 843
857 ret = request_irq(davinci_spi->irq, davinci_spi_irq, 0, 844 ret = request_irq(dspi->irq, davinci_spi_irq, 0, dev_name(&pdev->dev),
858 dev_name(&pdev->dev), davinci_spi); 845 dspi);
859 if (ret) 846 if (ret)
860 goto unmap_io; 847 goto unmap_io;
861 848
862 davinci_spi->bitbang.master = spi_master_get(master); 849 dspi->bitbang.master = spi_master_get(master);
863 if (davinci_spi->bitbang.master == NULL) { 850 if (dspi->bitbang.master == NULL) {
864 ret = -ENODEV; 851 ret = -ENODEV;
865 goto irq_free; 852 goto irq_free;
866 } 853 }
867 854
868 davinci_spi->clk = clk_get(&pdev->dev, NULL); 855 dspi->clk = clk_get(&pdev->dev, NULL);
869 if (IS_ERR(davinci_spi->clk)) { 856 if (IS_ERR(dspi->clk)) {
870 ret = -ENODEV; 857 ret = -ENODEV;
871 goto put_master; 858 goto put_master;
872 } 859 }
873 clk_enable(davinci_spi->clk); 860 clk_enable(dspi->clk);
874 861
875 master->bus_num = pdev->id; 862 master->bus_num = pdev->id;
876 master->num_chipselect = pdata->num_chipselect; 863 master->num_chipselect = pdata->num_chipselect;
877 master->setup = davinci_spi_setup; 864 master->setup = davinci_spi_setup;
878 865
879 davinci_spi->bitbang.chipselect = davinci_spi_chipselect; 866 dspi->bitbang.chipselect = davinci_spi_chipselect;
880 davinci_spi->bitbang.setup_transfer = davinci_spi_setup_transfer; 867 dspi->bitbang.setup_transfer = davinci_spi_setup_transfer;
881 868
882 davinci_spi->version = pdata->version; 869 dspi->version = pdata->version;
883 870
884 davinci_spi->bitbang.flags = SPI_NO_CS | SPI_LSB_FIRST | SPI_LOOP; 871 dspi->bitbang.flags = SPI_NO_CS | SPI_LSB_FIRST | SPI_LOOP;
885 if (davinci_spi->version == SPI_VERSION_2) 872 if (dspi->version == SPI_VERSION_2)
886 davinci_spi->bitbang.flags |= SPI_READY; 873 dspi->bitbang.flags |= SPI_READY;
887 874
888 r = platform_get_resource(pdev, IORESOURCE_DMA, 0); 875 r = platform_get_resource(pdev, IORESOURCE_DMA, 0);
889 if (r) 876 if (r)
@@ -895,15 +882,15 @@ static int davinci_spi_probe(struct platform_device *pdev)
895 if (r) 882 if (r)
896 dma_eventq = r->start; 883 dma_eventq = r->start;
897 884
898 davinci_spi->bitbang.txrx_bufs = davinci_spi_bufs; 885 dspi->bitbang.txrx_bufs = davinci_spi_bufs;
899 if (dma_rx_chan != SPI_NO_RESOURCE && 886 if (dma_rx_chan != SPI_NO_RESOURCE &&
900 dma_tx_chan != SPI_NO_RESOURCE && 887 dma_tx_chan != SPI_NO_RESOURCE &&
901 dma_eventq != SPI_NO_RESOURCE) { 888 dma_eventq != SPI_NO_RESOURCE) {
902 davinci_spi->dma_channels.dma_rx_channel = dma_rx_chan; 889 dspi->dma.rx_channel = dma_rx_chan;
903 davinci_spi->dma_channels.dma_tx_channel = dma_tx_chan; 890 dspi->dma.tx_channel = dma_tx_chan;
904 davinci_spi->dma_channels.eventq = dma_eventq; 891 dspi->dma.eventq = dma_eventq;
905 892
906 ret = davinci_spi_request_dma(davinci_spi); 893 ret = davinci_spi_request_dma(dspi);
907 if (ret) 894 if (ret)
908 goto free_clk; 895 goto free_clk;
909 896
@@ -913,19 +900,19 @@ static int davinci_spi_probe(struct platform_device *pdev)
913 dma_eventq); 900 dma_eventq);
914 } 901 }
915 902
916 davinci_spi->get_rx = davinci_spi_rx_buf_u8; 903 dspi->get_rx = davinci_spi_rx_buf_u8;
917 davinci_spi->get_tx = davinci_spi_tx_buf_u8; 904 dspi->get_tx = davinci_spi_tx_buf_u8;
918 905
919 init_completion(&davinci_spi->done); 906 init_completion(&dspi->done);
920 907
921 /* Reset In/OUT SPI module */ 908 /* Reset In/OUT SPI module */
922 iowrite32(0, davinci_spi->base + SPIGCR0); 909 iowrite32(0, dspi->base + SPIGCR0);
923 udelay(100); 910 udelay(100);
924 iowrite32(1, davinci_spi->base + SPIGCR0); 911 iowrite32(1, dspi->base + SPIGCR0);
925 912
926 /* Set up SPIPC0. CS and ENA init is done in davinci_spi_setup */ 913 /* Set up SPIPC0. CS and ENA init is done in davinci_spi_setup */
927 spipc0 = SPIPC0_DIFUN_MASK | SPIPC0_DOFUN_MASK | SPIPC0_CLKFUN_MASK; 914 spipc0 = SPIPC0_DIFUN_MASK | SPIPC0_DOFUN_MASK | SPIPC0_CLKFUN_MASK;
928 iowrite32(spipc0, davinci_spi->base + SPIPC0); 915 iowrite32(spipc0, dspi->base + SPIPC0);
929 916
930 /* initialize chip selects */ 917 /* initialize chip selects */
931 if (pdata->chip_sel) { 918 if (pdata->chip_sel) {
@@ -936,40 +923,40 @@ static int davinci_spi_probe(struct platform_device *pdev)
936 } 923 }
937 924
938 if (pdata->intr_line) 925 if (pdata->intr_line)
939 iowrite32(SPI_INTLVL_1, davinci_spi->base + SPILVL); 926 iowrite32(SPI_INTLVL_1, dspi->base + SPILVL);
940 else 927 else
941 iowrite32(SPI_INTLVL_0, davinci_spi->base + SPILVL); 928 iowrite32(SPI_INTLVL_0, dspi->base + SPILVL);
942 929
943 iowrite32(CS_DEFAULT, davinci_spi->base + SPIDEF); 930 iowrite32(CS_DEFAULT, dspi->base + SPIDEF);
944 931
945 /* master mode default */ 932 /* master mode default */
946 set_io_bits(davinci_spi->base + SPIGCR1, SPIGCR1_CLKMOD_MASK); 933 set_io_bits(dspi->base + SPIGCR1, SPIGCR1_CLKMOD_MASK);
947 set_io_bits(davinci_spi->base + SPIGCR1, SPIGCR1_MASTER_MASK); 934 set_io_bits(dspi->base + SPIGCR1, SPIGCR1_MASTER_MASK);
948 set_io_bits(davinci_spi->base + SPIGCR1, SPIGCR1_POWERDOWN_MASK); 935 set_io_bits(dspi->base + SPIGCR1, SPIGCR1_POWERDOWN_MASK);
949 936
950 ret = spi_bitbang_start(&davinci_spi->bitbang); 937 ret = spi_bitbang_start(&dspi->bitbang);
951 if (ret) 938 if (ret)
952 goto free_dma; 939 goto free_dma;
953 940
954 dev_info(&pdev->dev, "Controller at 0x%p\n", davinci_spi->base); 941 dev_info(&pdev->dev, "Controller at 0x%p\n", dspi->base);
955 942
956 return ret; 943 return ret;
957 944
958free_dma: 945free_dma:
959 edma_free_channel(davinci_spi->dma_channels.dma_tx_channel); 946 edma_free_channel(dspi->dma.tx_channel);
960 edma_free_channel(davinci_spi->dma_channels.dma_rx_channel); 947 edma_free_channel(dspi->dma.rx_channel);
961 edma_free_slot(davinci_spi->dma_channels.dummy_param_slot); 948 edma_free_slot(dspi->dma.dummy_param_slot);
962free_clk: 949free_clk:
963 clk_disable(davinci_spi->clk); 950 clk_disable(dspi->clk);
964 clk_put(davinci_spi->clk); 951 clk_put(dspi->clk);
965put_master: 952put_master:
966 spi_master_put(master); 953 spi_master_put(master);
967irq_free: 954irq_free:
968 free_irq(davinci_spi->irq, davinci_spi); 955 free_irq(dspi->irq, dspi);
969unmap_io: 956unmap_io:
970 iounmap(davinci_spi->base); 957 iounmap(dspi->base);
971release_region: 958release_region:
972 release_mem_region(davinci_spi->pbase, resource_size(r)); 959 release_mem_region(dspi->pbase, resource_size(r));
973free_master: 960free_master:
974 kfree(master); 961 kfree(master);
975err: 962err:
@@ -987,22 +974,22 @@ err:
987 */ 974 */
988static int __exit davinci_spi_remove(struct platform_device *pdev) 975static int __exit davinci_spi_remove(struct platform_device *pdev)
989{ 976{
990 struct davinci_spi *davinci_spi; 977 struct davinci_spi *dspi;
991 struct spi_master *master; 978 struct spi_master *master;
992 struct resource *r; 979 struct resource *r;
993 980
994 master = dev_get_drvdata(&pdev->dev); 981 master = dev_get_drvdata(&pdev->dev);
995 davinci_spi = spi_master_get_devdata(master); 982 dspi = spi_master_get_devdata(master);
996 983
997 spi_bitbang_stop(&davinci_spi->bitbang); 984 spi_bitbang_stop(&dspi->bitbang);
998 985
999 clk_disable(davinci_spi->clk); 986 clk_disable(dspi->clk);
1000 clk_put(davinci_spi->clk); 987 clk_put(dspi->clk);
1001 spi_master_put(master); 988 spi_master_put(master);
1002 free_irq(davinci_spi->irq, davinci_spi); 989 free_irq(dspi->irq, dspi);
1003 iounmap(davinci_spi->base); 990 iounmap(dspi->base);
1004 r = platform_get_resource(pdev, IORESOURCE_MEM, 0); 991 r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1005 release_mem_region(davinci_spi->pbase, resource_size(r)); 992 release_mem_region(dspi->pbase, resource_size(r));
1006 993
1007 return 0; 994 return 0;
1008} 995}