SPI: add CSR SiRFprimaII SPI controller driver

CSR SiRFprimaII has two SPIs (SPI0 and SPI1). Features:
* Master and slave modes
* 8-/12-/16-/32-bit data unit
* 256 bytes receive data FIFO and 256 bytes transmit data FIFO
* Multi-unit frame
* Configurable SPI_EN (chip select pin) active state
* Configurable SPI_CLK polarity
* Configurable SPI_CLK phase
* Configurable MSB/LSB first

Signed-off-by: Zhiwu Song <zhiwu.song@csr.com>
Signed-off-by: Barry Song <Baohua.Song@csr.com>
Signed-off-by: Grant Likely <grant.likely@secretlab.ca>

1 files changed, 1 insertions, 0 deletions

diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile
index d9a7aed4ae9a..2e556484345a 100644
--- a/drivers/spi/Makefile
+++ b/drivers/spi/Makefile
@@ -53,6 +53,7 @@ obj-$(CONFIG_SPI_SH)			+= spi-sh.o
 obj-$(CONFIG_SPI_SH_HSPI)               += spi-sh-hspi.o
 obj-$(CONFIG_SPI_SH_MSIOF)              += spi-sh-msiof.o
 obj-$(CONFIG_SPI_SH_SCI)                += spi-sh-sci.o
+obj-$(CONFIG_SPI_SIRF)          += spi-sirf.o
 obj-$(CONFIG_SPI_STMP3XXX)              += spi-stmp.o
 obj-$(CONFIG_SPI_TEGRA)                 += spi-tegra.o
 obj-$(CONFIG_SPI_TI_SSP)                += spi-ti-ssp.o