Merge branch 'wip-2.6.34' into old-private-masterarchived-private-master

4 files changed, 936 insertions, 74 deletions

diff --git a/drivers/sh/Makefile b/drivers/sh/Makefile
index 6a025cefe6dc..4956bf1f2134 100644
--- a/drivers/sh/Makefile
+++ b/drivers/sh/Makefile
@@ -3,4 +3,5 @@
 #
 obj-$(CONFIG_SUPERHYWAY)        += superhyway/
 obj-$(CONFIG_MAPLE)             += maple/
+obj-$(CONFIG_GENERIC_GPIO)      += pfc.o
 obj-y                           += intc.o
diff --git a/drivers/sh/intc.c b/drivers/sh/intc.c
index 559b5fe9dc0f..94ad6bd86a00 100644
--- a/drivers/sh/intc.c
+++ b/drivers/sh/intc.c
@@ -2,6 +2,7 @@
  * Shared interrupt handling code for IPR and INTC2 types of IRQs.
  *
  * Copyright (C) 2007, 2008 Magnus Damm
+ * Copyright (C) 2009, 2010 Paul Mundt
  *
  * Based on intc2.c and ipr.c
  *
@@ -19,11 +20,14 @@
 #include <linux/irq.h>
 #include <linux/module.h>
 #include <linux/io.h>
+#include <linux/slab.h>
 #include <linux/interrupt.h>
 #include <linux/sh_intc.h>
 #include <linux/sysdev.h>
 #include <linux/list.h>
 #include <linux/topology.h>
+#include <linux/bitmap.h>
+#include <linux/cpumask.h>
 
 #define _INTC_MK(fn, mode, addr_e, addr_d, width, shift) \
         ((shift) | ((width) << 5) | ((fn) << 9) | ((mode) << 13) | \
@@ -59,6 +63,20 @@ struct intc_desc_int {
 
 static LIST_HEAD(intc_list);
 
+/*
+ * The intc_irq_map provides a global map of bound IRQ vectors for a
+ * given platform. Allocation of IRQs are either static through the CPU
+ * vector map, or dynamic in the case of board mux vectors or MSI.
+ *
+ * As this is a central point for all IRQ controllers on the system,
+ * each of the available sources are mapped out here. This combined with
+ * sparseirq makes it quite trivial to keep the vector map tightly packed
+ * when dynamically creating IRQs, as well as tying in to otherwise
+ * unused irq_desc positions in the sparse array.
+ */
+static DECLARE_BITMAP(intc_irq_map, NR_IRQS);
+static DEFINE_SPINLOCK(vector_lock);
+
 #ifdef CONFIG_SMP
 #define IS_SMP(x) x.smp
 #define INTC_REG(d, x, c) (d->reg[(x)] + ((d->smp[(x)] & 0xff) * c))
@@ -70,9 +88,7 @@ static LIST_HEAD(intc_list);
 #endif
 
 static unsigned int intc_prio_level[NR_IRQS]; /* for now */
-#if defined(CONFIG_CPU_SH3) || defined(CONFIG_CPU_SH4A)
 static unsigned long ack_handle[NR_IRQS];
-#endif
 
 static inline struct intc_desc_int *get_intc_desc(unsigned int irq)
 {
@@ -220,6 +236,10 @@ static inline void _intc_enable(unsigned int irq, unsigned long handle)
         unsigned int cpu;
 
         for (cpu = 0; cpu < SMP_NR(d, _INTC_ADDR_E(handle)); cpu++) {
+#ifdef CONFIG_SMP
+                if (!cpumask_test_cpu(cpu, irq_to_desc(irq)->affinity))
+                        continue;
+#endif
                 addr = INTC_REG(d, _INTC_ADDR_E(handle), cpu);
                 intc_enable_fns[_INTC_MODE(handle)](addr, handle, intc_reg_fns\
                                                     [_INTC_FN(handle)], irq);
@@ -239,18 +259,75 @@ static void intc_disable(unsigned int irq)
         unsigned int cpu;
 
         for (cpu = 0; cpu < SMP_NR(d, _INTC_ADDR_D(handle)); cpu++) {
+#ifdef CONFIG_SMP
+                if (!cpumask_test_cpu(cpu, irq_to_desc(irq)->affinity))
+                        continue;
+#endif
                 addr = INTC_REG(d, _INTC_ADDR_D(handle), cpu);
                 intc_disable_fns[_INTC_MODE(handle)](addr, handle,intc_reg_fns\
                                                      [_INTC_FN(handle)], irq);
         }
 }
 
+static void (*intc_enable_noprio_fns[])(unsigned long addr,
+                                        unsigned long handle,
+                                        void (*fn)(unsigned long,
+                                                   unsigned long,
+                                                   unsigned long),
+                                        unsigned int irq) = {
+        [MODE_ENABLE_REG] = intc_mode_field,
+        [MODE_MASK_REG] = intc_mode_zero,
+        [MODE_DUAL_REG] = intc_mode_field,
+        [MODE_PRIO_REG] = intc_mode_field,
+        [MODE_PCLR_REG] = intc_mode_field,
+};
+
+static void intc_enable_disable(struct intc_desc_int *d,
+                                unsigned long handle, int do_enable)
+{
+        unsigned long addr;
+        unsigned int cpu;
+        void (*fn)(unsigned long, unsigned long,
+                   void (*)(unsigned long, unsigned long, unsigned long),
+                   unsigned int);
+
+        if (do_enable) {
+                for (cpu = 0; cpu < SMP_NR(d, _INTC_ADDR_E(handle)); cpu++) {
+                        addr = INTC_REG(d, _INTC_ADDR_E(handle), cpu);
+                        fn = intc_enable_noprio_fns[_INTC_MODE(handle)];
+                        fn(addr, handle, intc_reg_fns[_INTC_FN(handle)], 0);
+                }
+        } else {
+                for (cpu = 0; cpu < SMP_NR(d, _INTC_ADDR_D(handle)); cpu++) {
+                        addr = INTC_REG(d, _INTC_ADDR_D(handle), cpu);
+                        fn = intc_disable_fns[_INTC_MODE(handle)];
+                        fn(addr, handle, intc_reg_fns[_INTC_FN(handle)], 0);
+                }
+        }
+}
+
 static int intc_set_wake(unsigned int irq, unsigned int on)
 {
         return 0; /* allow wakeup, but setup hardware in intc_suspend() */
 }
 
-#if defined(CONFIG_CPU_SH3) || defined(CONFIG_CPU_SH4A)
+#ifdef CONFIG_SMP
+/*
+ * This is held with the irq desc lock held, so we don't require any
+ * additional locking here at the intc desc level. The affinity mask is
+ * later tested in the enable/disable paths.
+ */
+static int intc_set_affinity(unsigned int irq, const struct cpumask *cpumask)
+{
+        if (!cpumask_intersects(cpumask, cpu_online_mask))
+                return -1;
+
+        cpumask_copy(irq_to_desc(irq)->affinity, cpumask);
+
+        return 0;
+}
+#endif
+
 static void intc_mask_ack(unsigned int irq)
 {
         struct intc_desc_int *d = get_intc_desc(irq);
@@ -282,7 +359,6 @@ static void intc_mask_ack(unsigned int irq)
                 }
         }
 }
-#endif
 
 static struct intc_handle_int *intc_find_irq(struct intc_handle_int *hp,
                                              unsigned int nr_hp,
@@ -388,11 +464,11 @@ static unsigned int __init intc_get_reg(struct intc_desc_int *d,
 static intc_enum __init intc_grp_id(struct intc_desc *desc,
                                     intc_enum enum_id)
 {
-        struct intc_group *g = desc->groups;
+        struct intc_group *g = desc->hw.groups;
         unsigned int i, j;
 
-        for (i = 0; g && enum_id && i < desc->nr_groups; i++) {
-                g = desc->groups + i;
+        for (i = 0; g && enum_id && i < desc->hw.nr_groups; i++) {
+                g = desc->hw.groups + i;
 
                 for (j = 0; g->enum_ids[j]; j++) {
                         if (g->enum_ids[j] != enum_id)
@@ -405,19 +481,21 @@ static intc_enum __init intc_grp_id(struct intc_desc *desc,
         return 0;
 }
 
-static unsigned int __init intc_mask_data(struct intc_desc *desc,
-                                          struct intc_desc_int *d,
-                                          intc_enum enum_id, int do_grps)
+static unsigned int __init _intc_mask_data(struct intc_desc *desc,
+                                           struct intc_desc_int *d,
+                                           intc_enum enum_id,
+                                           unsigned int *reg_idx,
+                                           unsigned int *fld_idx)
 {
-        struct intc_mask_reg *mr = desc->mask_regs;
-        unsigned int i, j, fn, mode;
+        struct intc_mask_reg *mr = desc->hw.mask_regs;
+        unsigned int fn, mode;
         unsigned long reg_e, reg_d;
 
-        for (i = 0; mr && enum_id && i < desc->nr_mask_regs; i++) {
-                mr = desc->mask_regs + i;
+        while (mr && enum_id && *reg_idx < desc->hw.nr_mask_regs) {
+                mr = desc->hw.mask_regs + *reg_idx;
 
-                for (j = 0; j < ARRAY_SIZE(mr->enum_ids); j++) {
-                        if (mr->enum_ids[j] != enum_id)
+                for (; *fld_idx < ARRAY_SIZE(mr->enum_ids); (*fld_idx)++) {
+                        if (mr->enum_ids[*fld_idx] != enum_id)
                                 continue;
 
                         if (mr->set_reg && mr->clr_reg) {
@@ -443,29 +521,49 @@ static unsigned int __init intc_mask_data(struct intc_desc *desc,
                                         intc_get_reg(d, reg_e),
                                         intc_get_reg(d, reg_d),
                                         1,
-                                        (mr->reg_width - 1) - j);
+                                        (mr->reg_width - 1) - *fld_idx);
                 }
+
+                *fld_idx = 0;
+                (*reg_idx)++;
         }
 
+        return 0;
+}
+
+static unsigned int __init intc_mask_data(struct intc_desc *desc,
+                                          struct intc_desc_int *d,
+                                          intc_enum enum_id, int do_grps)
+{
+        unsigned int i = 0;
+        unsigned int j = 0;
+        unsigned int ret;
+
+        ret = _intc_mask_data(desc, d, enum_id, &i, &j);
+        if (ret)
+                return ret;
+
         if (do_grps)
                 return intc_mask_data(desc, d, intc_grp_id(desc, enum_id), 0);
 
         return 0;
 }
 
-static unsigned int __init intc_prio_data(struct intc_desc *desc,
-                                          struct intc_desc_int *d,
-                                          intc_enum enum_id, int do_grps)
+static unsigned int __init _intc_prio_data(struct intc_desc *desc,
+                                           struct intc_desc_int *d,
+                                           intc_enum enum_id,
+                                           unsigned int *reg_idx,
+                                           unsigned int *fld_idx)
 {
-        struct intc_prio_reg *pr = desc->prio_regs;
-        unsigned int i, j, fn, mode, bit;
+        struct intc_prio_reg *pr = desc->hw.prio_regs;
+        unsigned int fn, n, mode, bit;
         unsigned long reg_e, reg_d;
 
-        for (i = 0; pr && enum_id && i < desc->nr_prio_regs; i++) {
-                pr = desc->prio_regs + i;
+        while (pr && enum_id && *reg_idx < desc->hw.nr_prio_regs) {
+                pr = desc->hw.prio_regs + *reg_idx;
 
-                for (j = 0; j < ARRAY_SIZE(pr->enum_ids); j++) {
-                        if (pr->enum_ids[j] != enum_id)
+                for (; *fld_idx < ARRAY_SIZE(pr->enum_ids); (*fld_idx)++) {
+                        if (pr->enum_ids[*fld_idx] != enum_id)
                                 continue;
 
                         if (pr->set_reg && pr->clr_reg) {
@@ -483,35 +581,79 @@ static unsigned int __init intc_prio_data(struct intc_desc *desc,
                         }
 
                         fn += (pr->reg_width >> 3) - 1;
+                        n = *fld_idx + 1;
 
-                        BUG_ON((j + 1) * pr->field_width > pr->reg_width);
+                        BUG_ON(n * pr->field_width > pr->reg_width);
 
-                        bit = pr->reg_width - ((j + 1) * pr->field_width);
+                        bit = pr->reg_width - (n * pr->field_width);
 
                         return _INTC_MK(fn, mode,
                                         intc_get_reg(d, reg_e),
                                         intc_get_reg(d, reg_d),
                                         pr->field_width, bit);
                 }
+
+                *fld_idx = 0;
+                (*reg_idx)++;
         }
 
+        return 0;
+}
+
+static unsigned int __init intc_prio_data(struct intc_desc *desc,
+                                          struct intc_desc_int *d,
+                                          intc_enum enum_id, int do_grps)
+{
+        unsigned int i = 0;
+        unsigned int j = 0;
+        unsigned int ret;
+
+        ret = _intc_prio_data(desc, d, enum_id, &i, &j);
+        if (ret)
+                return ret;
+
         if (do_grps)
                 return intc_prio_data(desc, d, intc_grp_id(desc, enum_id), 0);
 
         return 0;
 }
 
-#if defined(CONFIG_CPU_SH3) || defined(CONFIG_CPU_SH4A)
+static void __init intc_enable_disable_enum(struct intc_desc *desc,
+                                            struct intc_desc_int *d,
+                                            intc_enum enum_id, int enable)
+{
+        unsigned int i, j, data;
+
+        /* go through and enable/disable all mask bits */
+        i = j = 0;
+        do {
+                data = _intc_mask_data(desc, d, enum_id, &i, &j);
+                if (data)
+                        intc_enable_disable(d, data, enable);
+                j++;
+        } while (data);
+
+        /* go through and enable/disable all priority fields */
+        i = j = 0;
+        do {
+                data = _intc_prio_data(desc, d, enum_id, &i, &j);
+                if (data)
+                        intc_enable_disable(d, data, enable);
+
+                j++;
+        } while (data);
+}
+
 static unsigned int __init intc_ack_data(struct intc_desc *desc,
                                           struct intc_desc_int *d,
                                           intc_enum enum_id)
 {
-        struct intc_mask_reg *mr = desc->ack_regs;
+        struct intc_mask_reg *mr = desc->hw.ack_regs;
         unsigned int i, j, fn, mode;
         unsigned long reg_e, reg_d;
 
-        for (i = 0; mr && enum_id && i < desc->nr_ack_regs; i++) {
-                mr = desc->ack_regs + i;
+        for (i = 0; mr && enum_id && i < desc->hw.nr_ack_regs; i++) {
+                mr = desc->hw.ack_regs + i;
 
                 for (j = 0; j < ARRAY_SIZE(mr->enum_ids); j++) {
                         if (mr->enum_ids[j] != enum_id)
@@ -533,17 +675,16 @@ static unsigned int __init intc_ack_data(struct intc_desc *desc,
 
         return 0;
 }
-#endif
 
 static unsigned int __init intc_sense_data(struct intc_desc *desc,
                                            struct intc_desc_int *d,
                                            intc_enum enum_id)
 {
-        struct intc_sense_reg *sr = desc->sense_regs;
+        struct intc_sense_reg *sr = desc->hw.sense_regs;
         unsigned int i, j, fn, bit;
 
-        for (i = 0; sr && enum_id && i < desc->nr_sense_regs; i++) {
-                sr = desc->sense_regs + i;
+        for (i = 0; sr && enum_id && i < desc->hw.nr_sense_regs; i++) {
+                sr = desc->hw.sense_regs + i;
 
                 for (j = 0; j < ARRAY_SIZE(sr->enum_ids); j++) {
                         if (sr->enum_ids[j] != enum_id)
@@ -572,6 +713,11 @@ static void __init intc_register_irq(struct intc_desc *desc,
         struct intc_handle_int *hp;
         unsigned int data[2], primary;
 
+        /*
+         * Register the IRQ position with the global IRQ map
+         */
+        set_bit(irq, intc_irq_map);
+
         /* Prefer single interrupt source bitmap over other combinations:
          * 1. bitmap, single interrupt source
          * 2. priority, single interrupt source
@@ -641,9 +787,11 @@ static void __init intc_register_irq(struct intc_desc *desc,
         /* irq should be disabled by default */
         d->chip.mask(irq);
 
-#if defined(CONFIG_CPU_SH3) || defined(CONFIG_CPU_SH4A)
-        if (desc->ack_regs)
+        if (desc->hw.ack_regs)
                 ack_handle[irq] = intc_ack_data(desc, d, enum_id);
+
+#ifdef CONFIG_ARM
+        set_irq_flags(irq, IRQF_VALID); /* Enable IRQ on ARM systems */
 #endif
 }
 
@@ -671,6 +819,7 @@ static void intc_redirect_irq(unsigned int irq, struct irq_desc *desc)
 void __init register_intc_controller(struct intc_desc *desc)
 {
         unsigned int i, k, smp;
+        struct intc_hw_desc *hw = &desc->hw;
         struct intc_desc_int *d;
 
         d = kzalloc(sizeof(*d), GFP_NOWAIT);
@@ -678,43 +827,42 @@ void __init register_intc_controller(struct intc_desc *desc)
         INIT_LIST_HEAD(&d->list);
         list_add(&d->list, &intc_list);
 
-        d->nr_reg = desc->mask_regs ? desc->nr_mask_regs * 2 : 0;
-        d->nr_reg += desc->prio_regs ? desc->nr_prio_regs * 2 : 0;
-        d->nr_reg += desc->sense_regs ? desc->nr_sense_regs : 0;
+        d->nr_reg = hw->mask_regs ? hw->nr_mask_regs * 2 : 0;
+        d->nr_reg += hw->prio_regs ? hw->nr_prio_regs * 2 : 0;
+        d->nr_reg += hw->sense_regs ? hw->nr_sense_regs : 0;
+        d->nr_reg += hw->ack_regs ? hw->nr_ack_regs : 0;
 
-#if defined(CONFIG_CPU_SH3) || defined(CONFIG_CPU_SH4A)
-        d->nr_reg += desc->ack_regs ? desc->nr_ack_regs : 0;
-#endif
         d->reg = kzalloc(d->nr_reg * sizeof(*d->reg), GFP_NOWAIT);
 #ifdef CONFIG_SMP
         d->smp = kzalloc(d->nr_reg * sizeof(*d->smp), GFP_NOWAIT);
 #endif
         k = 0;
 
-        if (desc->mask_regs) {
-                for (i = 0; i < desc->nr_mask_regs; i++) {
-                        smp = IS_SMP(desc->mask_regs[i]);
-                        k += save_reg(d, k, desc->mask_regs[i].set_reg, smp);
-                        k += save_reg(d, k, desc->mask_regs[i].clr_reg, smp);
+        if (hw->mask_regs) {
+                for (i = 0; i < hw->nr_mask_regs; i++) {
+                        smp = IS_SMP(hw->mask_regs[i]);
+                        k += save_reg(d, k, hw->mask_regs[i].set_reg, smp);
+                        k += save_reg(d, k, hw->mask_regs[i].clr_reg, smp);
                 }
         }
 
-        if (desc->prio_regs) {
-                d->prio = kzalloc(desc->nr_vectors * sizeof(*d->prio), GFP_NOWAIT);
+        if (hw->prio_regs) {
+                d->prio = kzalloc(hw->nr_vectors * sizeof(*d->prio),
+                                  GFP_NOWAIT);
 
-                for (i = 0; i < desc->nr_prio_regs; i++) {
-                        smp = IS_SMP(desc->prio_regs[i]);
-                        k += save_reg(d, k, desc->prio_regs[i].set_reg, smp);
-                        k += save_reg(d, k, desc->prio_regs[i].clr_reg, smp);
+                for (i = 0; i < hw->nr_prio_regs; i++) {
+                        smp = IS_SMP(hw->prio_regs[i]);
+                        k += save_reg(d, k, hw->prio_regs[i].set_reg, smp);
+                        k += save_reg(d, k, hw->prio_regs[i].clr_reg, smp);
                 }
         }
 
-        if (desc->sense_regs) {
-                d->sense = kzalloc(desc->nr_vectors * sizeof(*d->sense), GFP_NOWAIT);
+        if (hw->sense_regs) {
+                d->sense = kzalloc(hw->nr_vectors * sizeof(*d->sense),
+                                   GFP_NOWAIT);
 
-                for (i = 0; i < desc->nr_sense_regs; i++) {
-                        k += save_reg(d, k, desc->sense_regs[i].reg, 0);
-                }
+                for (i = 0; i < hw->nr_sense_regs; i++)
+                        k += save_reg(d, k, hw->sense_regs[i].reg, 0);
         }
 
         d->chip.name = desc->name;
@@ -726,21 +874,30 @@ void __init register_intc_controller(struct intc_desc *desc)
         d->chip.shutdown = intc_disable;
         d->chip.set_type = intc_set_sense;
         d->chip.set_wake = intc_set_wake;
+#ifdef CONFIG_SMP
+        d->chip.set_affinity = intc_set_affinity;
+#endif
 
-#if defined(CONFIG_CPU_SH3) || defined(CONFIG_CPU_SH4A)
-        if (desc->ack_regs) {
-                for (i = 0; i < desc->nr_ack_regs; i++)
-                        k += save_reg(d, k, desc->ack_regs[i].set_reg, 0);
+        if (hw->ack_regs) {
+                for (i = 0; i < hw->nr_ack_regs; i++)
+                        k += save_reg(d, k, hw->ack_regs[i].set_reg, 0);
 
                 d->chip.mask_ack = intc_mask_ack;
         }
-#endif
+
+        /* disable bits matching force_disable before registering irqs */
+        if (desc->force_disable)
+                intc_enable_disable_enum(desc, d, desc->force_disable, 0);
+
+        /* disable bits matching force_enable before registering irqs */
+        if (desc->force_enable)
+                intc_enable_disable_enum(desc, d, desc->force_enable, 0);
 
         BUG_ON(k > 256); /* _INTC_ADDR_E() and _INTC_ADDR_D() are 8 bits */
 
         /* register the vectors one by one */
-        for (i = 0; i < desc->nr_vectors; i++) {
-                struct intc_vect *vect = desc->vectors + i;
+        for (i = 0; i < hw->nr_vectors; i++) {
+                struct intc_vect *vect = hw->vectors + i;
                 unsigned int irq = evt2irq(vect->vect);
                 struct irq_desc *irq_desc;
 
@@ -755,8 +912,8 @@ void __init register_intc_controller(struct intc_desc *desc)
 
                 intc_register_irq(desc, d, vect->enum_id, irq);
 
-                for (k = i + 1; k < desc->nr_vectors; k++) {
-                        struct intc_vect *vect2 = desc->vectors + k;
+                for (k = i + 1; k < hw->nr_vectors; k++) {
+                        struct intc_vect *vect2 = hw->vectors + k;
                         unsigned int irq2 = evt2irq(vect2->vect);
 
                         if (vect->enum_id != vect2->enum_id)
@@ -776,11 +933,15 @@ void __init register_intc_controller(struct intc_desc *desc)
                         vect2->enum_id = 0;
 
                         /* redirect this interrupts to the first one */
-                        set_irq_chip_and_handler_name(irq2, &d->chip,
-                                        intc_redirect_irq, "redirect");
+                        set_irq_chip(irq2, &dummy_irq_chip);
+                        set_irq_chained_handler(irq2, intc_redirect_irq);
                         set_irq_data(irq2, (void *)irq);
                 }
         }
+
+        /* enable bits matching force_enable after registering irqs */
+        if (desc->force_enable)
+                intc_enable_disable_enum(desc, d, desc->force_enable, 1);
 }
 
 static int intc_suspend(struct sys_device *dev, pm_message_t state)
@@ -797,6 +958,8 @@ static int intc_suspend(struct sys_device *dev, pm_message_t state)
                 if (d->state.event != PM_EVENT_FREEZE)
                         break;
                 for_each_irq_desc(irq, desc) {
+                        if (desc->handle_irq == intc_redirect_irq)
+                                continue;
                         if (desc->chip != &d->chip)
                                 continue;
                         if (desc->status & IRQ_DISABLED)
@@ -856,5 +1019,99 @@ static int __init register_intc_sysdevs(void)
 
         return error;
 }
-
 device_initcall(register_intc_sysdevs);
+
+/*
+ * Dynamic IRQ allocation and deallocation
+ */
+unsigned int create_irq_nr(unsigned int irq_want, int node)
+{
+        unsigned int irq = 0, new;
+        unsigned long flags;
+        struct irq_desc *desc;
+
+        spin_lock_irqsave(&vector_lock, flags);
+
+        /*
+         * First try the wanted IRQ
+         */
+        if (test_and_set_bit(irq_want, intc_irq_map) == 0) {
+                new = irq_want;
+        } else {
+                /* .. then fall back to scanning. */
+                new = find_first_zero_bit(intc_irq_map, nr_irqs);
+                if (unlikely(new == nr_irqs))
+                        goto out_unlock;
+
+                __set_bit(new, intc_irq_map);
+        }
+
+        desc = irq_to_desc_alloc_node(new, node);
+        if (unlikely(!desc)) {
+                pr_info("can't get irq_desc for %d\n", new);
+                goto out_unlock;
+        }
+
+        desc = move_irq_desc(desc, node);
+        irq = new;
+
+out_unlock:
+        spin_unlock_irqrestore(&vector_lock, flags);
+
+        if (irq > 0) {
+                dynamic_irq_init(irq);
+#ifdef CONFIG_ARM
+                set_irq_flags(irq, IRQF_VALID); /* Enable IRQ on ARM systems */
+#endif
+        }
+
+        return irq;
+}
+
+int create_irq(void)
+{
+        int nid = cpu_to_node(smp_processor_id());
+        int irq;
+
+        irq = create_irq_nr(NR_IRQS_LEGACY, nid);
+        if (irq == 0)
+                irq = -1;
+
+        return irq;
+}
+
+void destroy_irq(unsigned int irq)
+{
+        unsigned long flags;
+
+        dynamic_irq_cleanup(irq);
+
+        spin_lock_irqsave(&vector_lock, flags);
+        __clear_bit(irq, intc_irq_map);
+        spin_unlock_irqrestore(&vector_lock, flags);
+}
+
+int reserve_irq_vector(unsigned int irq)
+{
+        unsigned long flags;
+        int ret = 0;
+
+        spin_lock_irqsave(&vector_lock, flags);
+        if (test_and_set_bit(irq, intc_irq_map))
+                ret = -EBUSY;
+        spin_unlock_irqrestore(&vector_lock, flags);
+
+        return ret;
+}
+
+void reserve_irq_legacy(void)
+{
+        unsigned long flags;
+        int i, j;
+
+        spin_lock_irqsave(&vector_lock, flags);
+        j = find_first_bit(intc_irq_map, nr_irqs);
+        for (i = 0; i < j; i++)
+                __set_bit(i, intc_irq_map);
+        spin_unlock_irqrestore(&vector_lock, flags);
+}
diff --git a/drivers/sh/maple/maple.c b/drivers/sh/maple/maple.c
index 93c20e135ee1..4e8f57d4131f 100644
--- a/drivers/sh/maple/maple.c
+++ b/drivers/sh/maple/maple.c
@@ -106,7 +106,7 @@ static void maple_dma_reset(void)
         * max delay is 11
         */
         ctrl_outl(MAPLE_2MBPS | MAPLE_TIMEOUT(0xFFFF), MAPLE_SPEED);
-        ctrl_outl(PHYSADDR(maple_sendbuf), MAPLE_DMAADDR);
+        ctrl_outl(virt_to_phys(maple_sendbuf), MAPLE_DMAADDR);
         ctrl_outl(1, MAPLE_ENABLE);
 }
 
@@ -258,7 +258,7 @@ static void maple_build_block(struct mapleq *mq)
         maple_lastptr = maple_sendptr;
 
         *maple_sendptr++ = (port << 16) | len | 0x80000000;
-        *maple_sendptr++ = PHYSADDR(mq->recvbuf->buf);
+        *maple_sendptr++ = virt_to_phys(mq->recvbuf->buf);
         *maple_sendptr++ =
             mq->command | (to << 8) | (from << 16) | (len << 24);
         while (len-- > 0)
diff --git a/drivers/sh/pfc.c b/drivers/sh/pfc.c
new file mode 100644
index 000000000000..cf0303acab8e
--- /dev/null
+++ b/drivers/sh/pfc.c
@@ -0,0 +1,604 @@
+/*
+ * Pinmuxed GPIO support for SuperH.
+ *
+ * Copyright (C) 2008 Magnus Damm
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ */
+#include <linux/errno.h>
+#include <linux/kernel.h>
+#include <linux/list.h>
+#include <linux/module.h>
+#include <linux/clk.h>
+#include <linux/err.h>
+#include <linux/io.h>
+#include <linux/irq.h>
+#include <linux/bitops.h>
+#include <linux/gpio.h>
+
+static int enum_in_range(pinmux_enum_t enum_id, struct pinmux_range *r)
+{
+        if (enum_id < r->begin)
+                return 0;
+
+        if (enum_id > r->end)
+                return 0;
+
+        return 1;
+}
+
+static unsigned long gpio_read_raw_reg(unsigned long reg,
+                                       unsigned long reg_width)
+{
+        switch (reg_width) {
+        case 8:
+                return __raw_readb(reg);
+        case 16:
+                return __raw_readw(reg);
+        case 32:
+                return __raw_readl(reg);
+        }
+
+        BUG();
+        return 0;
+}
+
+static void gpio_write_raw_reg(unsigned long reg,
+                               unsigned long reg_width,
+                               unsigned long data)
+{
+        switch (reg_width) {
+        case 8:
+                __raw_writeb(data, reg);
+                return;
+        case 16:
+                __raw_writew(data, reg);
+                return;
+        case 32:
+                __raw_writel(data, reg);
+                return;
+        }
+
+        BUG();
+}
+
+static void gpio_write_bit(struct pinmux_data_reg *dr,
+                           unsigned long in_pos, unsigned long value)
+{
+        unsigned long pos;
+
+        pos = dr->reg_width - (in_pos + 1);
+
+        pr_debug("write_bit addr = %lx, value = %d, pos = %ld, "
+                 "r_width = %ld\n",
+                 dr->reg, !!value, pos, dr->reg_width);
+
+        if (value)
+                set_bit(pos, &dr->reg_shadow);
+        else
+                clear_bit(pos, &dr->reg_shadow);
+
+        gpio_write_raw_reg(dr->reg, dr->reg_width, dr->reg_shadow);
+}
+
+static int gpio_read_reg(unsigned long reg, unsigned long reg_width,
+                         unsigned long field_width, unsigned long in_pos)
+{
+        unsigned long data, mask, pos;
+
+        data = 0;
+        mask = (1 << field_width) - 1;
+        pos = reg_width - ((in_pos + 1) * field_width);
+
+        pr_debug("read_reg: addr = %lx, pos = %ld, "
+                 "r_width = %ld, f_width = %ld\n",
+                 reg, pos, reg_width, field_width);
+
+        data = gpio_read_raw_reg(reg, reg_width);
+        return (data >> pos) & mask;
+}
+
+static void gpio_write_reg(unsigned long reg, unsigned long reg_width,
+                           unsigned long field_width, unsigned long in_pos,
+                           unsigned long value)
+{
+        unsigned long mask, pos;
+
+        mask = (1 << field_width) - 1;
+        pos = reg_width - ((in_pos + 1) * field_width);
+
+        pr_debug("write_reg addr = %lx, value = %ld, pos = %ld, "
+                 "r_width = %ld, f_width = %ld\n",
+                 reg, value, pos, reg_width, field_width);
+
+        mask = ~(mask << pos);
+        value = value << pos;
+
+        switch (reg_width) {
+        case 8:
+                __raw_writeb((__raw_readb(reg) & mask) | value, reg);
+                break;
+        case 16:
+                __raw_writew((__raw_readw(reg) & mask) | value, reg);
+                break;
+        case 32:
+                __raw_writel((__raw_readl(reg) & mask) | value, reg);
+                break;
+        }
+}
+
+static int setup_data_reg(struct pinmux_info *gpioc, unsigned gpio)
+{
+        struct pinmux_gpio *gpiop = &gpioc->gpios[gpio];
+        struct pinmux_data_reg *data_reg;
+        int k, n;
+
+        if (!enum_in_range(gpiop->enum_id, &gpioc->data))
+                return -1;
+
+        k = 0;
+        while (1) {
+                data_reg = gpioc->data_regs + k;
+
+                if (!data_reg->reg_width)
+                        break;
+
+                for (n = 0; n < data_reg->reg_width; n++) {
+                        if (data_reg->enum_ids[n] == gpiop->enum_id) {
+                                gpiop->flags &= ~PINMUX_FLAG_DREG;
+                                gpiop->flags |= (k << PINMUX_FLAG_DREG_SHIFT);
+                                gpiop->flags &= ~PINMUX_FLAG_DBIT;
+                                gpiop->flags |= (n << PINMUX_FLAG_DBIT_SHIFT);
+                                return 0;
+                        }
+                }
+                k++;
+        }
+
+        BUG();
+
+        return -1;
+}
+
+static void setup_data_regs(struct pinmux_info *gpioc)
+{
+        struct pinmux_data_reg *drp;
+        int k;
+
+        for (k = gpioc->first_gpio; k <= gpioc->last_gpio; k++)
+                setup_data_reg(gpioc, k);
+
+        k = 0;
+        while (1) {
+                drp = gpioc->data_regs + k;
+
+                if (!drp->reg_width)
+                        break;
+
+                drp->reg_shadow = gpio_read_raw_reg(drp->reg, drp->reg_width);
+                k++;
+        }
+}
+
+static int get_data_reg(struct pinmux_info *gpioc, unsigned gpio,
+                        struct pinmux_data_reg **drp, int *bitp)
+{
+        struct pinmux_gpio *gpiop = &gpioc->gpios[gpio];
+        int k, n;
+
+        if (!enum_in_range(gpiop->enum_id, &gpioc->data))
+                return -1;
+
+        k = (gpiop->flags & PINMUX_FLAG_DREG) >> PINMUX_FLAG_DREG_SHIFT;
+        n = (gpiop->flags & PINMUX_FLAG_DBIT) >> PINMUX_FLAG_DBIT_SHIFT;
+        *drp = gpioc->data_regs + k;
+        *bitp = n;
+        return 0;
+}
+
+static int get_config_reg(struct pinmux_info *gpioc, pinmux_enum_t enum_id,
+                          struct pinmux_cfg_reg **crp, int *indexp,
+                          unsigned long **cntp)
+{
+        struct pinmux_cfg_reg *config_reg;
+        unsigned long r_width, f_width;
+        int k, n;
+
+        k = 0;
+        while (1) {
+                config_reg = gpioc->cfg_regs + k;
+
+                r_width = config_reg->reg_width;
+                f_width = config_reg->field_width;
+
+                if (!r_width)
+                        break;
+                for (n = 0; n < (r_width / f_width) * 1 << f_width; n++) {
+                        if (config_reg->enum_ids[n] == enum_id) {
+                                *crp = config_reg;
+                                *indexp = n;
+                                *cntp = &config_reg->cnt[n / (1 << f_width)];
+                                return 0;
+                        }
+                }
+                k++;
+        }
+
+        return -1;
+}
+
+static int get_gpio_enum_id(struct pinmux_info *gpioc, unsigned gpio,
+                            int pos, pinmux_enum_t *enum_idp)
+{
+        pinmux_enum_t enum_id = gpioc->gpios[gpio].enum_id;
+        pinmux_enum_t *data = gpioc->gpio_data;
+        int k;
+
+        if (!enum_in_range(enum_id, &gpioc->data)) {
+                if (!enum_in_range(enum_id, &gpioc->mark)) {
+                        pr_err("non data/mark enum_id for gpio %d\n", gpio);
+                        return -1;
+                }
+        }
+
+        if (pos) {
+                *enum_idp = data[pos + 1];
+                return pos + 1;
+        }
+
+        for (k = 0; k < gpioc->gpio_data_size; k++) {
+                if (data[k] == enum_id) {
+                        *enum_idp = data[k + 1];
+                        return k + 1;
+                }
+        }
+
+        pr_err("cannot locate data/mark enum_id for gpio %d\n", gpio);
+        return -1;
+}
+
+static void write_config_reg(struct pinmux_info *gpioc,
+                             struct pinmux_cfg_reg *crp,
+                             int index)
+{
+        unsigned long ncomb, pos, value;
+
+        ncomb = 1 << crp->field_width;
+        pos = index / ncomb;
+        value = index % ncomb;
+
+        gpio_write_reg(crp->reg, crp->reg_width, crp->field_width, pos, value);
+}
+
+static int check_config_reg(struct pinmux_info *gpioc,
+                            struct pinmux_cfg_reg *crp,
+                            int index)
+{
+        unsigned long ncomb, pos, value;
+
+        ncomb = 1 << crp->field_width;
+        pos = index / ncomb;
+        value = index % ncomb;
+
+        if (gpio_read_reg(crp->reg, crp->reg_width,
+                          crp->field_width, pos) == value)
+                return 0;
+
+        return -1;
+}
+
+enum { GPIO_CFG_DRYRUN, GPIO_CFG_REQ, GPIO_CFG_FREE };
+
+static int pinmux_config_gpio(struct pinmux_info *gpioc, unsigned gpio,
+                              int pinmux_type, int cfg_mode)
+{
+        struct pinmux_cfg_reg *cr = NULL;
+        pinmux_enum_t enum_id;
+        struct pinmux_range *range;
+        int in_range, pos, index;
+        unsigned long *cntp;
+
+        switch (pinmux_type) {
+
+        case PINMUX_TYPE_FUNCTION:
+                range = NULL;
+                break;
+
+        case PINMUX_TYPE_OUTPUT:
+                range = &gpioc->output;
+                break;
+
+        case PINMUX_TYPE_INPUT:
+                range = &gpioc->input;
+                break;
+
+        case PINMUX_TYPE_INPUT_PULLUP:
+                range = &gpioc->input_pu;
+                break;
+
+        case PINMUX_TYPE_INPUT_PULLDOWN:
+                range = &gpioc->input_pd;
+                break;
+
+        default:
+                goto out_err;
+        }
+
+        pos = 0;
+        enum_id = 0;
+        index = 0;
+        while (1) {
+                pos = get_gpio_enum_id(gpioc, gpio, pos, &enum_id);
+                if (pos <= 0)
+                        goto out_err;
+
+                if (!enum_id)
+                        break;
+
+                /* first check if this is a function enum */
+                in_range = enum_in_range(enum_id, &gpioc->function);
+                if (!in_range) {
+                        /* not a function enum */
+                        if (range) {
+                                /*
+                                 * other range exists, so this pin is
+                                 * a regular GPIO pin that now is being
+                                 * bound to a specific direction.
+                                 *
+                                 * for this case we only allow function enums
+                                 * and the enums that match the other range.
+                                 */
+                                in_range = enum_in_range(enum_id, range);
+
+                                /*
+                                 * special case pass through for fixed
+                                 * input-only or output-only pins without
+                                 * function enum register association.
+                                 */
+                                if (in_range && enum_id == range->force)
+                                        continue;
+                        } else {
+                                /*
+                                 * no other range exists, so this pin
+                                 * must then be of the function type.
+                                 *
+                                 * allow function type pins to select
+                                 * any combination of function/in/out
+                                 * in their MARK lists.
+                                 */
+                                in_range = 1;
+                        }
+                }
+
+                if (!in_range)
+                        continue;
+
+                if (get_config_reg(gpioc, enum_id, &cr, &index, &cntp) != 0)
+                        goto out_err;
+
+                switch (cfg_mode) {
+                case GPIO_CFG_DRYRUN:
+                        if (!*cntp || !check_config_reg(gpioc, cr, index))
+                                continue;
+                        break;
+
+                case GPIO_CFG_REQ:
+                        write_config_reg(gpioc, cr, index);
+                        *cntp = *cntp + 1;
+                        break;
+
+                case GPIO_CFG_FREE:
+                        *cntp = *cntp - 1;
+                        break;
+                }
+        }
+
+        return 0;
+ out_err:
+        return -1;
+}
+
+static DEFINE_SPINLOCK(gpio_lock);
+
+static struct pinmux_info *chip_to_pinmux(struct gpio_chip *chip)
+{
+        return container_of(chip, struct pinmux_info, chip);
+}
+
+static int sh_gpio_request(struct gpio_chip *chip, unsigned offset)
+{
+        struct pinmux_info *gpioc = chip_to_pinmux(chip);
+        struct pinmux_data_reg *dummy;
+        unsigned long flags;
+        int i, ret, pinmux_type;
+
+        ret = -EINVAL;
+
+        if (!gpioc)
+                goto err_out;
+
+        spin_lock_irqsave(&gpio_lock, flags);
+
+        if ((gpioc->gpios[offset].flags & PINMUX_FLAG_TYPE) != PINMUX_TYPE_NONE)
+                goto err_unlock;
+
+        /* setup pin function here if no data is associated with pin */
+
+        if (get_data_reg(gpioc, offset, &dummy, &i) != 0)
+                pinmux_type = PINMUX_TYPE_FUNCTION;
+        else
+                pinmux_type = PINMUX_TYPE_GPIO;
+
+        if (pinmux_type == PINMUX_TYPE_FUNCTION) {
+                if (pinmux_config_gpio(gpioc, offset,
+                                       pinmux_type,
+                                       GPIO_CFG_DRYRUN) != 0)
+                        goto err_unlock;
+
+                if (pinmux_config_gpio(gpioc, offset,
+                                       pinmux_type,
+                                       GPIO_CFG_REQ) != 0)
+                        BUG();
+        }
+
+        gpioc->gpios[offset].flags &= ~PINMUX_FLAG_TYPE;
+        gpioc->gpios[offset].flags |= pinmux_type;
+
+        ret = 0;
+ err_unlock:
+        spin_unlock_irqrestore(&gpio_lock, flags);
+ err_out:
+        return ret;
+}
+
+static void sh_gpio_free(struct gpio_chip *chip, unsigned offset)
+{
+        struct pinmux_info *gpioc = chip_to_pinmux(chip);
+        unsigned long flags;
+        int pinmux_type;
+
+        if (!gpioc)
+                return;
+
+        spin_lock_irqsave(&gpio_lock, flags);
+
+        pinmux_type = gpioc->gpios[offset].flags & PINMUX_FLAG_TYPE;
+        pinmux_config_gpio(gpioc, offset, pinmux_type, GPIO_CFG_FREE);
+        gpioc->gpios[offset].flags &= ~PINMUX_FLAG_TYPE;
+        gpioc->gpios[offset].flags |= PINMUX_TYPE_NONE;
+
+        spin_unlock_irqrestore(&gpio_lock, flags);
+}
+
+static int pinmux_direction(struct pinmux_info *gpioc,
+                            unsigned gpio, int new_pinmux_type)
+{
+        int pinmux_type;
+        int ret = -EINVAL;
+
+        if (!gpioc)
+                goto err_out;
+
+        pinmux_type = gpioc->gpios[gpio].flags & PINMUX_FLAG_TYPE;
+
+        switch (pinmux_type) {
+        case PINMUX_TYPE_GPIO:
+                break;
+        case PINMUX_TYPE_OUTPUT:
+        case PINMUX_TYPE_INPUT:
+        case PINMUX_TYPE_INPUT_PULLUP:
+        case PINMUX_TYPE_INPUT_PULLDOWN:
+                pinmux_config_gpio(gpioc, gpio, pinmux_type, GPIO_CFG_FREE);
+                break;
+        default:
+                goto err_out;
+        }
+
+        if (pinmux_config_gpio(gpioc, gpio,
+                               new_pinmux_type,
+                               GPIO_CFG_DRYRUN) != 0)
+                goto err_out;
+
+        if (pinmux_config_gpio(gpioc, gpio,
+                               new_pinmux_type,
+                               GPIO_CFG_REQ) != 0)
+                BUG();
+
+        gpioc->gpios[gpio].flags &= ~PINMUX_FLAG_TYPE;
+        gpioc->gpios[gpio].flags |= new_pinmux_type;
+
+        ret = 0;
+ err_out:
+        return ret;
+}
+
+static int sh_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
+{
+        struct pinmux_info *gpioc = chip_to_pinmux(chip);
+        unsigned long flags;
+        int ret;
+
+        spin_lock_irqsave(&gpio_lock, flags);
+        ret = pinmux_direction(gpioc, offset, PINMUX_TYPE_INPUT);
+        spin_unlock_irqrestore(&gpio_lock, flags);
+
+        return ret;
+}
+
+static void sh_gpio_set_value(struct pinmux_info *gpioc,
+                             unsigned gpio, int value)
+{
+        struct pinmux_data_reg *dr = NULL;
+        int bit = 0;
+
+        if (!gpioc || get_data_reg(gpioc, gpio, &dr, &bit) != 0)
+                BUG();
+        else
+                gpio_write_bit(dr, bit, value);
+}
+
+static int sh_gpio_direction_output(struct gpio_chip *chip, unsigned offset,
+                                    int value)
+{
+        struct pinmux_info *gpioc = chip_to_pinmux(chip);
+        unsigned long flags;
+        int ret;
+
+        sh_gpio_set_value(gpioc, offset, value);
+        spin_lock_irqsave(&gpio_lock, flags);
+        ret = pinmux_direction(gpioc, offset, PINMUX_TYPE_OUTPUT);
+        spin_unlock_irqrestore(&gpio_lock, flags);
+
+        return ret;
+}
+
+static int sh_gpio_get_value(struct pinmux_info *gpioc, unsigned gpio)
+{
+        struct pinmux_data_reg *dr = NULL;
+        int bit = 0;
+
+        if (!gpioc || get_data_reg(gpioc, gpio, &dr, &bit) != 0) {
+                BUG();
+                return 0;
+        }
+
+        return gpio_read_reg(dr->reg, dr->reg_width, 1, bit);
+}
+
+static int sh_gpio_get(struct gpio_chip *chip, unsigned offset)
+{
+        return sh_gpio_get_value(chip_to_pinmux(chip), offset);
+}
+
+static void sh_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
+{
+        sh_gpio_set_value(chip_to_pinmux(chip), offset, value);
+}
+
+int register_pinmux(struct pinmux_info *pip)
+{
+        struct gpio_chip *chip = &pip->chip;
+
+        pr_info("sh pinmux: %s handling gpio %d -> %d\n",
+                pip->name, pip->first_gpio, pip->last_gpio);
+
+        setup_data_regs(pip);
+
+        chip->request = sh_gpio_request;
+        chip->free = sh_gpio_free;
+        chip->direction_input = sh_gpio_direction_input;
+        chip->get = sh_gpio_get;
+        chip->direction_output = sh_gpio_direction_output;
+        chip->set = sh_gpio_set;
+
+        WARN_ON(pip->first_gpio != 0); /* needs testing */
+
+        chip->label = pip->name;
+        chip->owner = THIS_MODULE;
+        chip->base = pip->first_gpio;
+        chip->ngpio = (pip->last_gpio - pip->first_gpio) + 1;
+
+        return gpiochip_add(chip);
+}