diff options
author | Sascha Hauer <s.hauer@pengutronix.de> | 2008-07-05 04:02:48 -0400 |
---|---|---|
committer | Robert Schwebel <r.schwebel@pengutronix.de> | 2008-07-05 04:02:48 -0400 |
commit | e3d13ff4b9d3b05d7a969153e2c049548e25deea (patch) | |
tree | 34210b2efa3d3c614f1a13797fb133e05d391045 /drivers/serial | |
parent | df1bf4bdb2a3a26d4bde8ae1aefc16385dd4898f (diff) |
mxc: add MX3 support for i.MX internal UART driver
This patch adds MX3 support for the i.MX internal uart driver.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Diffstat (limited to 'drivers/serial')
-rw-r--r-- | drivers/serial/Kconfig | 2 | ||||
-rw-r--r-- | drivers/serial/imx.c | 100 |
2 files changed, 81 insertions, 21 deletions
diff --git a/drivers/serial/Kconfig b/drivers/serial/Kconfig index 9bc42763623c..0843c5400684 100644 --- a/drivers/serial/Kconfig +++ b/drivers/serial/Kconfig | |||
@@ -753,7 +753,7 @@ config BFIN_UART3_CTSRTS | |||
753 | 753 | ||
754 | config SERIAL_IMX | 754 | config SERIAL_IMX |
755 | bool "IMX serial port support" | 755 | bool "IMX serial port support" |
756 | depends on ARM && ARCH_IMX | 756 | depends on ARM && (ARCH_IMX || ARCH_MXC) |
757 | select SERIAL_CORE | 757 | select SERIAL_CORE |
758 | help | 758 | help |
759 | If you have a machine based on a Motorola IMX CPU you | 759 | If you have a machine based on a Motorola IMX CPU you |
diff --git a/drivers/serial/imx.c b/drivers/serial/imx.c index 9e2162ebf1bb..549440b098b2 100644 --- a/drivers/serial/imx.c +++ b/drivers/serial/imx.c | |||
@@ -62,6 +62,11 @@ | |||
62 | #define UBIR 0xa4 /* BRM Incremental Register */ | 62 | #define UBIR 0xa4 /* BRM Incremental Register */ |
63 | #define UBMR 0xa8 /* BRM Modulator Register */ | 63 | #define UBMR 0xa8 /* BRM Modulator Register */ |
64 | #define UBRC 0xac /* Baud Rate Count Register */ | 64 | #define UBRC 0xac /* Baud Rate Count Register */ |
65 | #ifdef CONFIG_ARCH_MX3 | ||
66 | #define ONEMS 0xb0 /* One Millisecond register */ | ||
67 | #define UTS 0xb4 /* UART Test Register */ | ||
68 | #endif | ||
69 | #ifdef CONFIG_ARCH_IMX | ||
65 | #define BIPR1 0xb0 /* Incremental Preset Register 1 */ | 70 | #define BIPR1 0xb0 /* Incremental Preset Register 1 */ |
66 | #define BIPR2 0xb4 /* Incremental Preset Register 2 */ | 71 | #define BIPR2 0xb4 /* Incremental Preset Register 2 */ |
67 | #define BIPR3 0xb8 /* Incremental Preset Register 3 */ | 72 | #define BIPR3 0xb8 /* Incremental Preset Register 3 */ |
@@ -71,6 +76,7 @@ | |||
71 | #define BMPR3 0xc8 /* BRM Modulator Register 3 */ | 76 | #define BMPR3 0xc8 /* BRM Modulator Register 3 */ |
72 | #define BMPR4 0xcc /* BRM Modulator Register 4 */ | 77 | #define BMPR4 0xcc /* BRM Modulator Register 4 */ |
73 | #define UTS 0xd0 /* UART Test Register */ | 78 | #define UTS 0xd0 /* UART Test Register */ |
79 | #endif | ||
74 | 80 | ||
75 | /* UART Control Register Bit Fields.*/ | 81 | /* UART Control Register Bit Fields.*/ |
76 | #define URXD_CHARRDY (1<<15) | 82 | #define URXD_CHARRDY (1<<15) |
@@ -90,7 +96,12 @@ | |||
90 | #define UCR1_RTSDEN (1<<5) /* RTS delta interrupt enable */ | 96 | #define UCR1_RTSDEN (1<<5) /* RTS delta interrupt enable */ |
91 | #define UCR1_SNDBRK (1<<4) /* Send break */ | 97 | #define UCR1_SNDBRK (1<<4) /* Send break */ |
92 | #define UCR1_TDMAEN (1<<3) /* Transmitter ready DMA enable */ | 98 | #define UCR1_TDMAEN (1<<3) /* Transmitter ready DMA enable */ |
99 | #ifdef CONFIG_ARCH_IMX | ||
93 | #define UCR1_UARTCLKEN (1<<2) /* UART clock enabled */ | 100 | #define UCR1_UARTCLKEN (1<<2) /* UART clock enabled */ |
101 | #endif | ||
102 | #ifdef CONFIG_ARCH_MX3 | ||
103 | #define UCR1_UARTCLKEN (0) /* not present on mx2/mx3 */ | ||
104 | #endif | ||
94 | #define UCR1_DOZE (1<<1) /* Doze */ | 105 | #define UCR1_DOZE (1<<1) /* Doze */ |
95 | #define UCR1_UARTEN (1<<0) /* UART enabled */ | 106 | #define UCR1_UARTEN (1<<0) /* UART enabled */ |
96 | #define UCR2_ESCI (1<<15) /* Escape seq interrupt enable */ | 107 | #define UCR2_ESCI (1<<15) /* Escape seq interrupt enable */ |
@@ -164,8 +175,19 @@ | |||
164 | #define UTS_SOFTRST (1<<0) /* Software reset */ | 175 | #define UTS_SOFTRST (1<<0) /* Software reset */ |
165 | 176 | ||
166 | /* We've been assigned a range on the "Low-density serial ports" major */ | 177 | /* We've been assigned a range on the "Low-density serial ports" major */ |
178 | #ifdef CONFIG_ARCH_IMX | ||
167 | #define SERIAL_IMX_MAJOR 204 | 179 | #define SERIAL_IMX_MAJOR 204 |
168 | #define MINOR_START 41 | 180 | #define MINOR_START 41 |
181 | #define DEV_NAME "ttySMX" | ||
182 | #define MAX_INTERNAL_IRQ IMX_IRQS | ||
183 | #endif | ||
184 | |||
185 | #ifdef CONFIG_ARCH_MX3 | ||
186 | #define SERIAL_IMX_MAJOR 207 | ||
187 | #define MINOR_START 16 | ||
188 | #define DEV_NAME "ttymxc" | ||
189 | #define MAX_INTERNAL_IRQ MXC_MAX_INT_LINES | ||
190 | #endif | ||
169 | 191 | ||
170 | /* | 192 | /* |
171 | * This determines how often we check the modem status signals | 193 | * This determines how often we check the modem status signals |
@@ -409,6 +431,26 @@ out: | |||
409 | return IRQ_HANDLED; | 431 | return IRQ_HANDLED; |
410 | } | 432 | } |
411 | 433 | ||
434 | static irqreturn_t imx_int(int irq, void *dev_id) | ||
435 | { | ||
436 | struct imx_port *sport = dev_id; | ||
437 | unsigned int sts; | ||
438 | |||
439 | sts = readl(sport->port.membase + USR1); | ||
440 | |||
441 | if (sts & USR1_RRDY) | ||
442 | imx_rxint(irq, dev_id); | ||
443 | |||
444 | if (sts & USR1_TRDY && | ||
445 | readl(sport->port.membase + UCR1) & UCR1_TXMPTYEN) | ||
446 | imx_txint(irq, dev_id); | ||
447 | |||
448 | if (sts & USR1_RTSS) | ||
449 | imx_rtsint(irq, dev_id); | ||
450 | |||
451 | return IRQ_HANDLED; | ||
452 | } | ||
453 | |||
412 | /* | 454 | /* |
413 | * Return TIOCSER_TEMT when transmitter is not busy. | 455 | * Return TIOCSER_TEMT when transmitter is not busy. |
414 | */ | 456 | */ |
@@ -514,21 +556,34 @@ static int imx_startup(struct uart_port *port) | |||
514 | writel(temp & ~UCR4_DREN, sport->port.membase + UCR4); | 556 | writel(temp & ~UCR4_DREN, sport->port.membase + UCR4); |
515 | 557 | ||
516 | /* | 558 | /* |
517 | * Allocate the IRQ | 559 | * Allocate the IRQ(s) i.MX1 has three interrupts whereas later |
560 | * chips only have one interrupt. | ||
518 | */ | 561 | */ |
519 | retval = request_irq(sport->rxirq, imx_rxint, 0, | 562 | if (sport->txirq > 0) { |
520 | DRIVER_NAME, sport); | 563 | retval = request_irq(sport->rxirq, imx_rxint, 0, |
521 | if (retval) goto error_out1; | 564 | DRIVER_NAME, sport); |
522 | 565 | if (retval) | |
523 | retval = request_irq(sport->txirq, imx_txint, 0, | 566 | goto error_out1; |
524 | DRIVER_NAME, sport); | 567 | |
525 | if (retval) goto error_out2; | 568 | retval = request_irq(sport->txirq, imx_txint, 0, |
526 | 569 | DRIVER_NAME, sport); | |
527 | retval = request_irq(sport->rtsirq, imx_rtsint, | 570 | if (retval) |
528 | (sport->rtsirq < IMX_IRQS) ? 0 : | 571 | goto error_out2; |
572 | |||
573 | retval = request_irq(sport->rtsirq, imx_rtsint, | ||
574 | (sport->rtsirq < MAX_INTERNAL_IRQ) ? 0 : | ||
529 | IRQF_TRIGGER_FALLING | IRQF_TRIGGER_RISING, | 575 | IRQF_TRIGGER_FALLING | IRQF_TRIGGER_RISING, |
530 | DRIVER_NAME, sport); | 576 | DRIVER_NAME, sport); |
531 | if (retval) goto error_out3; | 577 | if (retval) |
578 | goto error_out3; | ||
579 | } else { | ||
580 | retval = request_irq(sport->port.irq, imx_int, 0, | ||
581 | DRIVER_NAME, sport); | ||
582 | if (retval) { | ||
583 | free_irq(sport->port.irq, sport); | ||
584 | goto error_out1; | ||
585 | } | ||
586 | } | ||
532 | 587 | ||
533 | /* | 588 | /* |
534 | * Finally, clear and enable interrupts | 589 | * Finally, clear and enable interrupts |
@@ -553,9 +608,11 @@ static int imx_startup(struct uart_port *port) | |||
553 | return 0; | 608 | return 0; |
554 | 609 | ||
555 | error_out3: | 610 | error_out3: |
556 | free_irq(sport->txirq, sport); | 611 | if (sport->txirq) |
612 | free_irq(sport->txirq, sport); | ||
557 | error_out2: | 613 | error_out2: |
558 | free_irq(sport->rxirq, sport); | 614 | if (sport->rxirq) |
615 | free_irq(sport->rxirq, sport); | ||
559 | error_out1: | 616 | error_out1: |
560 | return retval; | 617 | return retval; |
561 | } | 618 | } |
@@ -573,9 +630,12 @@ static void imx_shutdown(struct uart_port *port) | |||
573 | /* | 630 | /* |
574 | * Free the interrupts | 631 | * Free the interrupts |
575 | */ | 632 | */ |
576 | free_irq(sport->rtsirq, sport); | 633 | if (sport->txirq > 0) { |
577 | free_irq(sport->txirq, sport); | 634 | free_irq(sport->rtsirq, sport); |
578 | free_irq(sport->rxirq, sport); | 635 | free_irq(sport->txirq, sport); |
636 | free_irq(sport->rxirq, sport); | ||
637 | } else | ||
638 | free_irq(sport->port.irq, sport); | ||
579 | 639 | ||
580 | /* | 640 | /* |
581 | * Disable all interrupts, port and break condition. | 641 | * Disable all interrupts, port and break condition. |
@@ -973,7 +1033,7 @@ imx_console_setup(struct console *co, char *options) | |||
973 | 1033 | ||
974 | static struct uart_driver imx_reg; | 1034 | static struct uart_driver imx_reg; |
975 | static struct console imx_console = { | 1035 | static struct console imx_console = { |
976 | .name = "ttySMX", | 1036 | .name = DEV_NAME, |
977 | .write = imx_console_write, | 1037 | .write = imx_console_write, |
978 | .device = uart_console_device, | 1038 | .device = uart_console_device, |
979 | .setup = imx_console_setup, | 1039 | .setup = imx_console_setup, |
@@ -990,7 +1050,7 @@ static struct console imx_console = { | |||
990 | static struct uart_driver imx_reg = { | 1050 | static struct uart_driver imx_reg = { |
991 | .owner = THIS_MODULE, | 1051 | .owner = THIS_MODULE, |
992 | .driver_name = DRIVER_NAME, | 1052 | .driver_name = DRIVER_NAME, |
993 | .dev_name = "ttySMX", | 1053 | .dev_name = DEV_NAME, |
994 | .major = SERIAL_IMX_MAJOR, | 1054 | .major = SERIAL_IMX_MAJOR, |
995 | .minor = MINOR_START, | 1055 | .minor = MINOR_START, |
996 | .nr = ARRAY_SIZE(imx_ports), | 1056 | .nr = ARRAY_SIZE(imx_ports), |