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authorDan Williams <dan.j.williams@intel.com>2009-09-08 20:55:21 -0400
committerDan Williams <dan.j.williams@intel.com>2009-09-08 20:55:21 -0400
commitbbb20089a3275a19e475dbc21320c3742e3ca423 (patch)
tree216fdc1cbef450ca688135c5b8969169482d9a48 /drivers/serial/ucc_uart.c
parent3e48e656903e9fd8bc805c6a2c4264d7808d315b (diff)
parent657a77fa7284d8ae28dfa48f1dc5d919bf5b2843 (diff)
Merge branch 'dmaengine' into async-tx-next
Conflicts: crypto/async_tx/async_xor.c drivers/dma/ioat/dma_v2.h drivers/dma/ioat/pci.c drivers/md/raid5.c
Diffstat (limited to 'drivers/serial/ucc_uart.c')
-rw-r--r--drivers/serial/ucc_uart.c19
1 files changed, 14 insertions, 5 deletions
diff --git a/drivers/serial/ucc_uart.c b/drivers/serial/ucc_uart.c
index 7de66c06b05d..e945e780b5c9 100644
--- a/drivers/serial/ucc_uart.c
+++ b/drivers/serial/ucc_uart.c
@@ -681,22 +681,27 @@ static void qe_uart_init_ucc(struct uart_qe_port *qe_port)
681 out_be16(&uccup->rccm, 0xc0ff); 681 out_be16(&uccup->rccm, 0xc0ff);
682 682
683 /* Configure the GUMR registers for UART */ 683 /* Configure the GUMR registers for UART */
684 if (soft_uart) 684 if (soft_uart) {
685 /* Soft-UART requires a 1X multiplier for TX */ 685 /* Soft-UART requires a 1X multiplier for TX */
686 clrsetbits_be32(&uccp->gumr_l, 686 clrsetbits_be32(&uccp->gumr_l,
687 UCC_SLOW_GUMR_L_MODE_MASK | UCC_SLOW_GUMR_L_TDCR_MASK | 687 UCC_SLOW_GUMR_L_MODE_MASK | UCC_SLOW_GUMR_L_TDCR_MASK |
688 UCC_SLOW_GUMR_L_RDCR_MASK, 688 UCC_SLOW_GUMR_L_RDCR_MASK,
689 UCC_SLOW_GUMR_L_MODE_UART | UCC_SLOW_GUMR_L_TDCR_1 | 689 UCC_SLOW_GUMR_L_MODE_UART | UCC_SLOW_GUMR_L_TDCR_1 |
690 UCC_SLOW_GUMR_L_RDCR_16); 690 UCC_SLOW_GUMR_L_RDCR_16);
691 else 691
692 clrsetbits_be32(&uccp->gumr_h, UCC_SLOW_GUMR_H_RFW,
693 UCC_SLOW_GUMR_H_TRX | UCC_SLOW_GUMR_H_TTX);
694 } else {
692 clrsetbits_be32(&uccp->gumr_l, 695 clrsetbits_be32(&uccp->gumr_l,
693 UCC_SLOW_GUMR_L_MODE_MASK | UCC_SLOW_GUMR_L_TDCR_MASK | 696 UCC_SLOW_GUMR_L_MODE_MASK | UCC_SLOW_GUMR_L_TDCR_MASK |
694 UCC_SLOW_GUMR_L_RDCR_MASK, 697 UCC_SLOW_GUMR_L_RDCR_MASK,
695 UCC_SLOW_GUMR_L_MODE_UART | UCC_SLOW_GUMR_L_TDCR_16 | 698 UCC_SLOW_GUMR_L_MODE_UART | UCC_SLOW_GUMR_L_TDCR_16 |
696 UCC_SLOW_GUMR_L_RDCR_16); 699 UCC_SLOW_GUMR_L_RDCR_16);
697 700
698 clrsetbits_be32(&uccp->gumr_h, UCC_SLOW_GUMR_H_RFW, 701 clrsetbits_be32(&uccp->gumr_h,
699 UCC_SLOW_GUMR_H_TRX | UCC_SLOW_GUMR_H_TTX); 702 UCC_SLOW_GUMR_H_TRX | UCC_SLOW_GUMR_H_TTX,
703 UCC_SLOW_GUMR_H_RFW);
704 }
700 705
701#ifdef LOOPBACK 706#ifdef LOOPBACK
702 clrsetbits_be32(&uccp->gumr_l, UCC_SLOW_GUMR_L_DIAG_MASK, 707 clrsetbits_be32(&uccp->gumr_l, UCC_SLOW_GUMR_L_DIAG_MASK,
@@ -706,7 +711,7 @@ static void qe_uart_init_ucc(struct uart_qe_port *qe_port)
706 UCC_SLOW_GUMR_H_CDS); 711 UCC_SLOW_GUMR_H_CDS);
707#endif 712#endif
708 713
709 /* Enable rx interrupts and clear all pending events. */ 714 /* Disable rx interrupts and clear all pending events. */
710 out_be16(&uccp->uccm, 0); 715 out_be16(&uccp->uccm, 0);
711 out_be16(&uccp->ucce, 0xffff); 716 out_be16(&uccp->ucce, 0xffff);
712 out_be16(&uccp->udsr, 0x7e7e); 717 out_be16(&uccp->udsr, 0x7e7e);
@@ -765,6 +770,10 @@ static void qe_uart_init_ucc(struct uart_qe_port *qe_port)
765 cecr_subblock = ucc_slow_get_qe_cr_subblock(qe_port->ucc_num); 770 cecr_subblock = ucc_slow_get_qe_cr_subblock(qe_port->ucc_num);
766 qe_issue_cmd(QE_INIT_TX_RX, cecr_subblock, 771 qe_issue_cmd(QE_INIT_TX_RX, cecr_subblock,
767 QE_CR_PROTOCOL_UNSPECIFIED, 0); 772 QE_CR_PROTOCOL_UNSPECIFIED, 0);
773 } else {
774 cecr_subblock = ucc_slow_get_qe_cr_subblock(qe_port->ucc_num);
775 qe_issue_cmd(QE_INIT_TX_RX, cecr_subblock,
776 QE_CR_PROTOCOL_UART, 0);
768 } 777 }
769} 778}
770 779