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authorLinus Torvalds <torvalds@ppc970.osdl.org>2005-04-16 18:20:36 -0400
committerLinus Torvalds <torvalds@ppc970.osdl.org>2005-04-16 18:20:36 -0400
commit1da177e4c3f41524e886b7f1b8a0c1fc7321cac2 (patch)
tree0bba044c4ce775e45a88a51686b5d9f90697ea9d /drivers/serial/mpc52xx_uart.c
Linux-2.6.12-rc2v2.6.12-rc2
Initial git repository build. I'm not bothering with the full history, even though we have it. We can create a separate "historical" git archive of that later if we want to, and in the meantime it's about 3.2GB when imported into git - space that would just make the early git days unnecessarily complicated, when we don't have a lot of good infrastructure for it. Let it rip!
Diffstat (limited to 'drivers/serial/mpc52xx_uart.c')
-rw-r--r--drivers/serial/mpc52xx_uart.c852
1 files changed, 852 insertions, 0 deletions
diff --git a/drivers/serial/mpc52xx_uart.c b/drivers/serial/mpc52xx_uart.c
new file mode 100644
index 000000000000..2a5cf174ca30
--- /dev/null
+++ b/drivers/serial/mpc52xx_uart.c
@@ -0,0 +1,852 @@
1/*
2 * drivers/serial/mpc52xx_uart.c
3 *
4 * Driver for the PSC of the Freescale MPC52xx PSCs configured as UARTs.
5 *
6 * FIXME According to the usermanual the status bits in the status register
7 * are only updated when the peripherals access the FIFO and not when the
8 * CPU access them. So since we use this bits to know when we stop writing
9 * and reading, they may not be updated in-time and a race condition may
10 * exists. But I haven't be able to prove this and I don't care. But if
11 * any problem arises, it might worth checking. The TX/RX FIFO Stats
12 * registers should be used in addition.
13 * Update: Actually, they seem updated ... At least the bits we use.
14 *
15 *
16 * Maintainer : Sylvain Munaut <tnt@246tNt.com>
17 *
18 * Some of the code has been inspired/copied from the 2.4 code written
19 * by Dale Farnsworth <dfarnsworth@mvista.com>.
20 *
21 * Copyright (C) 2004-2005 Sylvain Munaut <tnt@246tNt.com>
22 * Copyright (C) 2003 MontaVista, Software, Inc.
23 *
24 * This file is licensed under the terms of the GNU General Public License
25 * version 2. This program is licensed "as is" without any warranty of any
26 * kind, whether express or implied.
27 */
28
29/* Platform device Usage :
30 *
31 * Since PSCs can have multiple function, the correct driver for each one
32 * is selected by calling mpc52xx_match_psc_function(...). The function
33 * handled by this driver is "uart".
34 *
35 * The driver init all necessary registers to place the PSC in uart mode without
36 * DCD. However, the pin multiplexing aren't changed and should be set either
37 * by the bootloader or in the platform init code.
38 *
39 * The idx field must be equal to the PSC index ( e.g. 0 for PSC1, 1 for PSC2,
40 * and so on). So the PSC1 is mapped to /dev/ttyS0, PSC2 to /dev/ttyS1 and so
41 * on. But be warned, it's an ABSOLUTE REQUIREMENT ! This is needed mainly for
42 * the console code : without this 1:1 mapping, at early boot time, when we are
43 * parsing the kernel args console=ttyS?, we wouldn't know wich PSC it will be
44 * mapped to.
45 */
46
47#include <linux/config.h>
48#include <linux/device.h>
49#include <linux/module.h>
50#include <linux/tty.h>
51#include <linux/serial.h>
52#include <linux/sysrq.h>
53#include <linux/console.h>
54
55#include <asm/delay.h>
56#include <asm/io.h>
57
58#include <asm/mpc52xx.h>
59#include <asm/mpc52xx_psc.h>
60
61#if defined(CONFIG_SERIAL_MPC52xx_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
62#define SUPPORT_SYSRQ
63#endif
64
65#include <linux/serial_core.h>
66
67
68
69#define ISR_PASS_LIMIT 256 /* Max number of iteration in the interrupt */
70
71
72static struct uart_port mpc52xx_uart_ports[MPC52xx_PSC_MAXNUM];
73 /* Rem: - We use the read_status_mask as a shadow of
74 * psc->mpc52xx_psc_imr
75 * - It's important that is array is all zero on start as we
76 * use it to know if it's initialized or not ! If it's not sure
77 * it's cleared, then a memset(...,0,...) should be added to
78 * the console_init
79 */
80
81#define PSC(port) ((struct mpc52xx_psc __iomem *)((port)->membase))
82
83
84/* Forward declaration of the interruption handling routine */
85static irqreturn_t mpc52xx_uart_int(int irq,void *dev_id,struct pt_regs *regs);
86
87
88/* Simple macro to test if a port is console or not. This one is taken
89 * for serial_core.c and maybe should be moved to serial_core.h ? */
90#ifdef CONFIG_SERIAL_CORE_CONSOLE
91#define uart_console(port) ((port)->cons && (port)->cons->index == (port)->line)
92#else
93#define uart_console(port) (0)
94#endif
95
96
97/* ======================================================================== */
98/* UART operations */
99/* ======================================================================== */
100
101static unsigned int
102mpc52xx_uart_tx_empty(struct uart_port *port)
103{
104 int status = in_be16(&PSC(port)->mpc52xx_psc_status);
105 return (status & MPC52xx_PSC_SR_TXEMP) ? TIOCSER_TEMT : 0;
106}
107
108static void
109mpc52xx_uart_set_mctrl(struct uart_port *port, unsigned int mctrl)
110{
111 /* Not implemented */
112}
113
114static unsigned int
115mpc52xx_uart_get_mctrl(struct uart_port *port)
116{
117 /* Not implemented */
118 return TIOCM_CTS | TIOCM_DSR | TIOCM_CAR;
119}
120
121static void
122mpc52xx_uart_stop_tx(struct uart_port *port, unsigned int tty_stop)
123{
124 /* port->lock taken by caller */
125 port->read_status_mask &= ~MPC52xx_PSC_IMR_TXRDY;
126 out_be16(&PSC(port)->mpc52xx_psc_imr,port->read_status_mask);
127}
128
129static void
130mpc52xx_uart_start_tx(struct uart_port *port, unsigned int tty_start)
131{
132 /* port->lock taken by caller */
133 port->read_status_mask |= MPC52xx_PSC_IMR_TXRDY;
134 out_be16(&PSC(port)->mpc52xx_psc_imr,port->read_status_mask);
135}
136
137static void
138mpc52xx_uart_send_xchar(struct uart_port *port, char ch)
139{
140 unsigned long flags;
141 spin_lock_irqsave(&port->lock, flags);
142
143 port->x_char = ch;
144 if (ch) {
145 /* Make sure tx interrupts are on */
146 /* Truly necessary ??? They should be anyway */
147 port->read_status_mask |= MPC52xx_PSC_IMR_TXRDY;
148 out_be16(&PSC(port)->mpc52xx_psc_imr,port->read_status_mask);
149 }
150
151 spin_unlock_irqrestore(&port->lock, flags);
152}
153
154static void
155mpc52xx_uart_stop_rx(struct uart_port *port)
156{
157 /* port->lock taken by caller */
158 port->read_status_mask &= ~MPC52xx_PSC_IMR_RXRDY;
159 out_be16(&PSC(port)->mpc52xx_psc_imr,port->read_status_mask);
160}
161
162static void
163mpc52xx_uart_enable_ms(struct uart_port *port)
164{
165 /* Not implemented */
166}
167
168static void
169mpc52xx_uart_break_ctl(struct uart_port *port, int ctl)
170{
171 unsigned long flags;
172 spin_lock_irqsave(&port->lock, flags);
173
174 if ( ctl == -1 )
175 out_8(&PSC(port)->command,MPC52xx_PSC_START_BRK);
176 else
177 out_8(&PSC(port)->command,MPC52xx_PSC_STOP_BRK);
178
179 spin_unlock_irqrestore(&port->lock, flags);
180}
181
182static int
183mpc52xx_uart_startup(struct uart_port *port)
184{
185 struct mpc52xx_psc __iomem *psc = PSC(port);
186 int ret;
187
188 /* Request IRQ */
189 ret = request_irq(port->irq, mpc52xx_uart_int,
190 SA_INTERRUPT | SA_SAMPLE_RANDOM, "mpc52xx_psc_uart", port);
191 if (ret)
192 return ret;
193
194 /* Reset/activate the port, clear and enable interrupts */
195 out_8(&psc->command,MPC52xx_PSC_RST_RX);
196 out_8(&psc->command,MPC52xx_PSC_RST_TX);
197
198 out_be32(&psc->sicr,0); /* UART mode DCD ignored */
199
200 out_be16(&psc->mpc52xx_psc_clock_select, 0xdd00); /* /16 prescaler on */
201
202 out_8(&psc->rfcntl, 0x00);
203 out_be16(&psc->rfalarm, 0x1ff);
204 out_8(&psc->tfcntl, 0x07);
205 out_be16(&psc->tfalarm, 0x80);
206
207 port->read_status_mask |= MPC52xx_PSC_IMR_RXRDY | MPC52xx_PSC_IMR_TXRDY;
208 out_be16(&psc->mpc52xx_psc_imr,port->read_status_mask);
209
210 out_8(&psc->command,MPC52xx_PSC_TX_ENABLE);
211 out_8(&psc->command,MPC52xx_PSC_RX_ENABLE);
212
213 return 0;
214}
215
216static void
217mpc52xx_uart_shutdown(struct uart_port *port)
218{
219 struct mpc52xx_psc __iomem *psc = PSC(port);
220
221 /* Shut down the port, interrupt and all */
222 out_8(&psc->command,MPC52xx_PSC_RST_RX);
223 out_8(&psc->command,MPC52xx_PSC_RST_TX);
224
225 port->read_status_mask = 0;
226 out_be16(&psc->mpc52xx_psc_imr,port->read_status_mask);
227
228 /* Release interrupt */
229 free_irq(port->irq, port);
230}
231
232static void
233mpc52xx_uart_set_termios(struct uart_port *port, struct termios *new,
234 struct termios *old)
235{
236 struct mpc52xx_psc __iomem *psc = PSC(port);
237 unsigned long flags;
238 unsigned char mr1, mr2;
239 unsigned short ctr;
240 unsigned int j, baud, quot;
241
242 /* Prepare what we're gonna write */
243 mr1 = 0;
244
245 switch (new->c_cflag & CSIZE) {
246 case CS5: mr1 |= MPC52xx_PSC_MODE_5_BITS;
247 break;
248 case CS6: mr1 |= MPC52xx_PSC_MODE_6_BITS;
249 break;
250 case CS7: mr1 |= MPC52xx_PSC_MODE_7_BITS;
251 break;
252 case CS8:
253 default: mr1 |= MPC52xx_PSC_MODE_8_BITS;
254 }
255
256 if (new->c_cflag & PARENB) {
257 mr1 |= (new->c_cflag & PARODD) ?
258 MPC52xx_PSC_MODE_PARODD : MPC52xx_PSC_MODE_PAREVEN;
259 } else
260 mr1 |= MPC52xx_PSC_MODE_PARNONE;
261
262
263 mr2 = 0;
264
265 if (new->c_cflag & CSTOPB)
266 mr2 |= MPC52xx_PSC_MODE_TWO_STOP;
267 else
268 mr2 |= ((new->c_cflag & CSIZE) == CS5) ?
269 MPC52xx_PSC_MODE_ONE_STOP_5_BITS :
270 MPC52xx_PSC_MODE_ONE_STOP;
271
272
273 baud = uart_get_baud_rate(port, new, old, 0, port->uartclk/16);
274 quot = uart_get_divisor(port, baud);
275 ctr = quot & 0xffff;
276
277 /* Get the lock */
278 spin_lock_irqsave(&port->lock, flags);
279
280 /* Update the per-port timeout */
281 uart_update_timeout(port, new->c_cflag, baud);
282
283 /* Do our best to flush TX & RX, so we don't loose anything */
284 /* But we don't wait indefinitly ! */
285 j = 5000000; /* Maximum wait */
286 /* FIXME Can't receive chars since set_termios might be called at early
287 * boot for the console, all stuff is not yet ready to receive at that
288 * time and that just makes the kernel oops */
289 /* while (j-- && mpc52xx_uart_int_rx_chars(port)); */
290 while (!(in_be16(&psc->mpc52xx_psc_status) & MPC52xx_PSC_SR_TXEMP) &&
291 --j)
292 udelay(1);
293
294 if (!j)
295 printk( KERN_ERR "mpc52xx_uart.c: "
296 "Unable to flush RX & TX fifos in-time in set_termios."
297 "Some chars may have been lost.\n" );
298
299 /* Reset the TX & RX */
300 out_8(&psc->command,MPC52xx_PSC_RST_RX);
301 out_8(&psc->command,MPC52xx_PSC_RST_TX);
302
303 /* Send new mode settings */
304 out_8(&psc->command,MPC52xx_PSC_SEL_MODE_REG_1);
305 out_8(&psc->mode,mr1);
306 out_8(&psc->mode,mr2);
307 out_8(&psc->ctur,ctr >> 8);
308 out_8(&psc->ctlr,ctr & 0xff);
309
310 /* Reenable TX & RX */
311 out_8(&psc->command,MPC52xx_PSC_TX_ENABLE);
312 out_8(&psc->command,MPC52xx_PSC_RX_ENABLE);
313
314 /* We're all set, release the lock */
315 spin_unlock_irqrestore(&port->lock, flags);
316}
317
318static const char *
319mpc52xx_uart_type(struct uart_port *port)
320{
321 return port->type == PORT_MPC52xx ? "MPC52xx PSC" : NULL;
322}
323
324static void
325mpc52xx_uart_release_port(struct uart_port *port)
326{
327 if (port->flags & UPF_IOREMAP) { /* remapped by us ? */
328 iounmap(port->membase);
329 port->membase = NULL;
330 }
331
332 release_mem_region(port->mapbase, MPC52xx_PSC_SIZE);
333}
334
335static int
336mpc52xx_uart_request_port(struct uart_port *port)
337{
338 if (port->flags & UPF_IOREMAP) /* Need to remap ? */
339 port->membase = ioremap(port->mapbase, MPC52xx_PSC_SIZE);
340
341 if (!port->membase)
342 return -EINVAL;
343
344 return request_mem_region(port->mapbase, MPC52xx_PSC_SIZE,
345 "mpc52xx_psc_uart") != NULL ? 0 : -EBUSY;
346}
347
348static void
349mpc52xx_uart_config_port(struct uart_port *port, int flags)
350{
351 if ( (flags & UART_CONFIG_TYPE) &&
352 (mpc52xx_uart_request_port(port) == 0) )
353 port->type = PORT_MPC52xx;
354}
355
356static int
357mpc52xx_uart_verify_port(struct uart_port *port, struct serial_struct *ser)
358{
359 if ( ser->type != PORT_UNKNOWN && ser->type != PORT_MPC52xx )
360 return -EINVAL;
361
362 if ( (ser->irq != port->irq) ||
363 (ser->io_type != SERIAL_IO_MEM) ||
364 (ser->baud_base != port->uartclk) ||
365 (ser->iomem_base != (void*)port->mapbase) ||
366 (ser->hub6 != 0 ) )
367 return -EINVAL;
368
369 return 0;
370}
371
372
373static struct uart_ops mpc52xx_uart_ops = {
374 .tx_empty = mpc52xx_uart_tx_empty,
375 .set_mctrl = mpc52xx_uart_set_mctrl,
376 .get_mctrl = mpc52xx_uart_get_mctrl,
377 .stop_tx = mpc52xx_uart_stop_tx,
378 .start_tx = mpc52xx_uart_start_tx,
379 .send_xchar = mpc52xx_uart_send_xchar,
380 .stop_rx = mpc52xx_uart_stop_rx,
381 .enable_ms = mpc52xx_uart_enable_ms,
382 .break_ctl = mpc52xx_uart_break_ctl,
383 .startup = mpc52xx_uart_startup,
384 .shutdown = mpc52xx_uart_shutdown,
385 .set_termios = mpc52xx_uart_set_termios,
386/* .pm = mpc52xx_uart_pm, Not supported yet */
387/* .set_wake = mpc52xx_uart_set_wake, Not supported yet */
388 .type = mpc52xx_uart_type,
389 .release_port = mpc52xx_uart_release_port,
390 .request_port = mpc52xx_uart_request_port,
391 .config_port = mpc52xx_uart_config_port,
392 .verify_port = mpc52xx_uart_verify_port
393};
394
395
396/* ======================================================================== */
397/* Interrupt handling */
398/* ======================================================================== */
399
400static inline int
401mpc52xx_uart_int_rx_chars(struct uart_port *port, struct pt_regs *regs)
402{
403 struct tty_struct *tty = port->info->tty;
404 unsigned char ch;
405 unsigned short status;
406
407 /* While we can read, do so ! */
408 while ( (status = in_be16(&PSC(port)->mpc52xx_psc_status)) &
409 MPC52xx_PSC_SR_RXRDY) {
410
411 /* If we are full, just stop reading */
412 if (tty->flip.count >= TTY_FLIPBUF_SIZE)
413 break;
414
415 /* Get the char */
416 ch = in_8(&PSC(port)->mpc52xx_psc_buffer_8);
417
418 /* Handle sysreq char */
419#ifdef SUPPORT_SYSRQ
420 if (uart_handle_sysrq_char(port, ch, regs)) {
421 port->sysrq = 0;
422 continue;
423 }
424#endif
425
426 /* Store it */
427 *tty->flip.char_buf_ptr = ch;
428 *tty->flip.flag_buf_ptr = 0;
429 port->icount.rx++;
430
431 if ( status & (MPC52xx_PSC_SR_PE |
432 MPC52xx_PSC_SR_FE |
433 MPC52xx_PSC_SR_RB |
434 MPC52xx_PSC_SR_OE) ) {
435
436 if (status & MPC52xx_PSC_SR_RB) {
437 *tty->flip.flag_buf_ptr = TTY_BREAK;
438 uart_handle_break(port);
439 } else if (status & MPC52xx_PSC_SR_PE)
440 *tty->flip.flag_buf_ptr = TTY_PARITY;
441 else if (status & MPC52xx_PSC_SR_FE)
442 *tty->flip.flag_buf_ptr = TTY_FRAME;
443 if (status & MPC52xx_PSC_SR_OE) {
444 /*
445 * Overrun is special, since it's
446 * reported immediately, and doesn't
447 * affect the current character
448 */
449 if (tty->flip.count < (TTY_FLIPBUF_SIZE-1)) {
450 tty->flip.flag_buf_ptr++;
451 tty->flip.char_buf_ptr++;
452 tty->flip.count++;
453 }
454 *tty->flip.flag_buf_ptr = TTY_OVERRUN;
455 }
456
457 /* Clear error condition */
458 out_8(&PSC(port)->command,MPC52xx_PSC_RST_ERR_STAT);
459
460 }
461
462 tty->flip.char_buf_ptr++;
463 tty->flip.flag_buf_ptr++;
464 tty->flip.count++;
465
466 }
467
468 tty_flip_buffer_push(tty);
469
470 return in_be16(&PSC(port)->mpc52xx_psc_status) & MPC52xx_PSC_SR_RXRDY;
471}
472
473static inline int
474mpc52xx_uart_int_tx_chars(struct uart_port *port)
475{
476 struct circ_buf *xmit = &port->info->xmit;
477
478 /* Process out of band chars */
479 if (port->x_char) {
480 out_8(&PSC(port)->mpc52xx_psc_buffer_8, port->x_char);
481 port->icount.tx++;
482 port->x_char = 0;
483 return 1;
484 }
485
486 /* Nothing to do ? */
487 if (uart_circ_empty(xmit) || uart_tx_stopped(port)) {
488 mpc52xx_uart_stop_tx(port,0);
489 return 0;
490 }
491
492 /* Send chars */
493 while (in_be16(&PSC(port)->mpc52xx_psc_status) & MPC52xx_PSC_SR_TXRDY) {
494 out_8(&PSC(port)->mpc52xx_psc_buffer_8, xmit->buf[xmit->tail]);
495 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
496 port->icount.tx++;
497 if (uart_circ_empty(xmit))
498 break;
499 }
500
501 /* Wake up */
502 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
503 uart_write_wakeup(port);
504
505 /* Maybe we're done after all */
506 if (uart_circ_empty(xmit)) {
507 mpc52xx_uart_stop_tx(port,0);
508 return 0;
509 }
510
511 return 1;
512}
513
514static irqreturn_t
515mpc52xx_uart_int(int irq, void *dev_id, struct pt_regs *regs)
516{
517 struct uart_port *port = (struct uart_port *) dev_id;
518 unsigned long pass = ISR_PASS_LIMIT;
519 unsigned int keepgoing;
520 unsigned short status;
521
522 if ( irq != port->irq ) {
523 printk( KERN_WARNING
524 "mpc52xx_uart_int : " \
525 "Received wrong int %d. Waiting for %d\n",
526 irq, port->irq);
527 return IRQ_NONE;
528 }
529
530 spin_lock(&port->lock);
531
532 /* While we have stuff to do, we continue */
533 do {
534 /* If we don't find anything to do, we stop */
535 keepgoing = 0;
536
537 /* Read status */
538 status = in_be16(&PSC(port)->mpc52xx_psc_isr);
539 status &= port->read_status_mask;
540
541 /* Do we need to receive chars ? */
542 /* For this RX interrupts must be on and some chars waiting */
543 if ( status & MPC52xx_PSC_IMR_RXRDY )
544 keepgoing |= mpc52xx_uart_int_rx_chars(port, regs);
545
546 /* Do we need to send chars ? */
547 /* For this, TX must be ready and TX interrupt enabled */
548 if ( status & MPC52xx_PSC_IMR_TXRDY )
549 keepgoing |= mpc52xx_uart_int_tx_chars(port);
550
551 /* Limit number of iteration */
552 if ( !(--pass) )
553 keepgoing = 0;
554
555 } while (keepgoing);
556
557 spin_unlock(&port->lock);
558
559 return IRQ_HANDLED;
560}
561
562
563/* ======================================================================== */
564/* Console ( if applicable ) */
565/* ======================================================================== */
566
567#ifdef CONFIG_SERIAL_MPC52xx_CONSOLE
568
569static void __init
570mpc52xx_console_get_options(struct uart_port *port,
571 int *baud, int *parity, int *bits, int *flow)
572{
573 struct mpc52xx_psc __iomem *psc = PSC(port);
574 unsigned char mr1;
575
576 /* Read the mode registers */
577 out_8(&psc->command,MPC52xx_PSC_SEL_MODE_REG_1);
578 mr1 = in_8(&psc->mode);
579
580 /* CT{U,L}R are write-only ! */
581 *baud = __res.bi_baudrate ?
582 __res.bi_baudrate : CONFIG_SERIAL_MPC52xx_CONSOLE_BAUD;
583
584 /* Parse them */
585 switch (mr1 & MPC52xx_PSC_MODE_BITS_MASK) {
586 case MPC52xx_PSC_MODE_5_BITS: *bits = 5; break;
587 case MPC52xx_PSC_MODE_6_BITS: *bits = 6; break;
588 case MPC52xx_PSC_MODE_7_BITS: *bits = 7; break;
589 case MPC52xx_PSC_MODE_8_BITS:
590 default: *bits = 8;
591 }
592
593 if (mr1 & MPC52xx_PSC_MODE_PARNONE)
594 *parity = 'n';
595 else
596 *parity = mr1 & MPC52xx_PSC_MODE_PARODD ? 'o' : 'e';
597}
598
599static void
600mpc52xx_console_write(struct console *co, const char *s, unsigned int count)
601{
602 struct uart_port *port = &mpc52xx_uart_ports[co->index];
603 struct mpc52xx_psc __iomem *psc = PSC(port);
604 unsigned int i, j;
605
606 /* Disable interrupts */
607 out_be16(&psc->mpc52xx_psc_imr, 0);
608
609 /* Wait the TX buffer to be empty */
610 j = 5000000; /* Maximum wait */
611 while (!(in_be16(&psc->mpc52xx_psc_status) & MPC52xx_PSC_SR_TXEMP) &&
612 --j)
613 udelay(1);
614
615 /* Write all the chars */
616 for ( i=0 ; i<count ; i++ ) {
617
618 /* Send the char */
619 out_8(&psc->mpc52xx_psc_buffer_8, *s);
620
621 /* Line return handling */
622 if ( *s++ == '\n' )
623 out_8(&psc->mpc52xx_psc_buffer_8, '\r');
624
625 /* Wait the TX buffer to be empty */
626 j = 20000; /* Maximum wait */
627 while (!(in_be16(&psc->mpc52xx_psc_status) &
628 MPC52xx_PSC_SR_TXEMP) && --j)
629 udelay(1);
630 }
631
632 /* Restore interrupt state */
633 out_be16(&psc->mpc52xx_psc_imr, port->read_status_mask);
634}
635
636static int __init
637mpc52xx_console_setup(struct console *co, char *options)
638{
639 struct uart_port *port = &mpc52xx_uart_ports[co->index];
640
641 int baud = CONFIG_SERIAL_MPC52xx_CONSOLE_BAUD;
642 int bits = 8;
643 int parity = 'n';
644 int flow = 'n';
645
646 if (co->index < 0 || co->index >= MPC52xx_PSC_MAXNUM)
647 return -EINVAL;
648
649 /* Basic port init. Needed since we use some uart_??? func before
650 * real init for early access */
651 spin_lock_init(&port->lock);
652 port->uartclk = __res.bi_ipbfreq / 2; /* Look at CTLR doc */
653 port->ops = &mpc52xx_uart_ops;
654 port->mapbase = MPC52xx_PA(MPC52xx_PSCx_OFFSET(co->index+1));
655
656 /* We ioremap ourself */
657 port->membase = ioremap(port->mapbase, MPC52xx_PSC_SIZE);
658 if (port->membase == NULL)
659 return -EINVAL;
660
661 /* Setup the port parameters accoding to options */
662 if (options)
663 uart_parse_options(options, &baud, &parity, &bits, &flow);
664 else
665 mpc52xx_console_get_options(port, &baud, &parity, &bits, &flow);
666
667 return uart_set_options(port, co, baud, parity, bits, flow);
668}
669
670
671extern struct uart_driver mpc52xx_uart_driver;
672
673static struct console mpc52xx_console = {
674 .name = "ttyS",
675 .write = mpc52xx_console_write,
676 .device = uart_console_device,
677 .setup = mpc52xx_console_setup,
678 .flags = CON_PRINTBUFFER,
679 .index = -1, /* Specified on the cmdline (e.g. console=ttyS0 ) */
680 .data = &mpc52xx_uart_driver,
681};
682
683
684static int __init
685mpc52xx_console_init(void)
686{
687 register_console(&mpc52xx_console);
688 return 0;
689}
690
691console_initcall(mpc52xx_console_init);
692
693#define MPC52xx_PSC_CONSOLE &mpc52xx_console
694#else
695#define MPC52xx_PSC_CONSOLE NULL
696#endif
697
698
699/* ======================================================================== */
700/* UART Driver */
701/* ======================================================================== */
702
703static struct uart_driver mpc52xx_uart_driver = {
704 .owner = THIS_MODULE,
705 .driver_name = "mpc52xx_psc_uart",
706 .dev_name = "ttyS",
707 .devfs_name = "ttyS",
708 .major = TTY_MAJOR,
709 .minor = 64,
710 .nr = MPC52xx_PSC_MAXNUM,
711 .cons = MPC52xx_PSC_CONSOLE,
712};
713
714
715/* ======================================================================== */
716/* Platform Driver */
717/* ======================================================================== */
718
719static int __devinit
720mpc52xx_uart_probe(struct device *dev)
721{
722 struct platform_device *pdev = to_platform_device(dev);
723 struct resource *res = pdev->resource;
724
725 struct uart_port *port = NULL;
726 int i, idx, ret;
727
728 /* Check validity & presence */
729 idx = pdev->id;
730 if (idx < 0 || idx >= MPC52xx_PSC_MAXNUM)
731 return -EINVAL;
732
733 if (!mpc52xx_match_psc_function(idx,"uart"))
734 return -ENODEV;
735
736 /* Init the port structure */
737 port = &mpc52xx_uart_ports[idx];
738
739 memset(port, 0x00, sizeof(struct uart_port));
740
741 spin_lock_init(&port->lock);
742 port->uartclk = __res.bi_ipbfreq / 2; /* Look at CTLR doc */
743 port->fifosize = 255; /* Should be 512 ! But it can't be */
744 /* stored in a unsigned char */
745 port->iotype = UPIO_MEM;
746 port->flags = UPF_BOOT_AUTOCONF |
747 ( uart_console(port) ? 0 : UPF_IOREMAP );
748 port->line = idx;
749 port->ops = &mpc52xx_uart_ops;
750
751 /* Search for IRQ and mapbase */
752 for (i=0 ; i<pdev->num_resources ; i++, res++) {
753 if (res->flags & IORESOURCE_MEM)
754 port->mapbase = res->start;
755 else if (res->flags & IORESOURCE_IRQ)
756 port->irq = res->start;
757 }
758 if (!port->irq || !port->mapbase)
759 return -EINVAL;
760
761 /* Add the port to the uart sub-system */
762 ret = uart_add_one_port(&mpc52xx_uart_driver, port);
763 if (!ret)
764 dev_set_drvdata(dev, (void*)port);
765
766 return ret;
767}
768
769static int
770mpc52xx_uart_remove(struct device *dev)
771{
772 struct uart_port *port = (struct uart_port *) dev_get_drvdata(dev);
773
774 dev_set_drvdata(dev, NULL);
775
776 if (port)
777 uart_remove_one_port(&mpc52xx_uart_driver, port);
778
779 return 0;
780}
781
782#ifdef CONFIG_PM
783static int
784mpc52xx_uart_suspend(struct device *dev, u32 state, u32 level)
785{
786 struct uart_port *port = (struct uart_port *) dev_get_drvdata(dev);
787
788 if (sport && level == SUSPEND_DISABLE)
789 uart_suspend_port(&mpc52xx_uart_driver, port);
790
791 return 0;
792}
793
794static int
795mpc52xx_uart_resume(struct device *dev, u32 level)
796{
797 struct uart_port *port = (struct uart_port *) dev_get_drvdata(dev);
798
799 if (port && level == RESUME_ENABLE)
800 uart_resume_port(&mpc52xx_uart_driver, port);
801
802 return 0;
803}
804#endif
805
806static struct device_driver mpc52xx_uart_platform_driver = {
807 .name = "mpc52xx-psc",
808 .bus = &platform_bus_type,
809 .probe = mpc52xx_uart_probe,
810 .remove = mpc52xx_uart_remove,
811#ifdef CONFIG_PM
812 .suspend = mpc52xx_uart_suspend,
813 .resume = mpc52xx_uart_resume,
814#endif
815};
816
817
818/* ======================================================================== */
819/* Module */
820/* ======================================================================== */
821
822static int __init
823mpc52xx_uart_init(void)
824{
825 int ret;
826
827 printk(KERN_INFO "Serial: MPC52xx PSC driver\n");
828
829 ret = uart_register_driver(&mpc52xx_uart_driver);
830 if (ret == 0) {
831 ret = driver_register(&mpc52xx_uart_platform_driver);
832 if (ret)
833 uart_unregister_driver(&mpc52xx_uart_driver);
834 }
835
836 return ret;
837}
838
839static void __exit
840mpc52xx_uart_exit(void)
841{
842 driver_unregister(&mpc52xx_uart_platform_driver);
843 uart_unregister_driver(&mpc52xx_uart_driver);
844}
845
846
847module_init(mpc52xx_uart_init);
848module_exit(mpc52xx_uart_exit);
849
850MODULE_AUTHOR("Sylvain Munaut <tnt@246tNt.com>");
851MODULE_DESCRIPTION("Freescale MPC52xx PSC UART");
852MODULE_LICENSE("GPL");