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authorJames Bottomley <jejb@mulgrave.il.steeleye.com>2006-06-10 14:47:26 -0400
committerJames Bottomley <jejb@mulgrave.il.steeleye.com>2006-06-10 14:47:26 -0400
commitf0cd91a68acdc9b49d7f6738b514a426da627649 (patch)
tree8ad73564015794197583b094217ae0a71e71e753 /drivers/serial/cpm_uart/cpm_uart_cpm2.c
parent60eef25701d25e99c991dd0f4a9f3832a0c3ad3e (diff)
parent128e6ced247cda88f96fa9f2e4ba8b2c4a681560 (diff)
Merge ../linux-2.6
Diffstat (limited to 'drivers/serial/cpm_uart/cpm_uart_cpm2.c')
-rw-r--r--drivers/serial/cpm_uart/cpm_uart_cpm2.c16
1 files changed, 6 insertions, 10 deletions
diff --git a/drivers/serial/cpm_uart/cpm_uart_cpm2.c b/drivers/serial/cpm_uart/cpm_uart_cpm2.c
index fd9e53ed3feb..cdba128250a9 100644
--- a/drivers/serial/cpm_uart/cpm_uart_cpm2.c
+++ b/drivers/serial/cpm_uart/cpm_uart_cpm2.c
@@ -8,6 +8,8 @@
8 * 8 *
9 * Copyright (C) 2004 Freescale Semiconductor, Inc. 9 * Copyright (C) 2004 Freescale Semiconductor, Inc.
10 * (C) 2004 Intracom, S.A. 10 * (C) 2004 Intracom, S.A.
11 * (C) 2006 MontaVista Software, Inc.
12 * Vitaly Bordug <vbordug@ru.mvista.com>
11 * 13 *
12 * This program is free software; you can redistribute it and/or modify 14 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License as published by 15 * it under the terms of the GNU General Public License as published by
@@ -142,14 +144,6 @@ void scc2_lineif(struct uart_cpm_port *pinfo)
142 * be supported in a sane fashion. 144 * be supported in a sane fashion.
143 */ 145 */
144#ifndef CONFIG_STX_GP3 146#ifndef CONFIG_STX_GP3
145#ifdef CONFIG_MPC8560_ADS
146 volatile iop_cpm2_t *io = &cpm2_immr->im_ioport;
147 io->iop_ppard |= 0x00000018;
148 io->iop_psord &= ~0x00000008; /* Rx */
149 io->iop_psord &= ~0x00000010; /* Tx */
150 io->iop_pdird &= ~0x00000008; /* Rx */
151 io->iop_pdird |= 0x00000010; /* Tx */
152#else
153 volatile iop_cpm2_t *io = &cpm2_immr->im_ioport; 147 volatile iop_cpm2_t *io = &cpm2_immr->im_ioport;
154 io->iop_pparb |= 0x008b0000; 148 io->iop_pparb |= 0x008b0000;
155 io->iop_pdirb |= 0x00880000; 149 io->iop_pdirb |= 0x00880000;
@@ -157,7 +151,6 @@ void scc2_lineif(struct uart_cpm_port *pinfo)
157 io->iop_pdirb &= ~0x00030000; 151 io->iop_pdirb &= ~0x00030000;
158 io->iop_psorb &= ~0x00030000; 152 io->iop_psorb &= ~0x00030000;
159#endif 153#endif
160#endif
161 cpm2_immr->im_cpmux.cmx_scr &= 0xff00ffff; 154 cpm2_immr->im_cpmux.cmx_scr &= 0xff00ffff;
162 cpm2_immr->im_cpmux.cmx_scr |= 0x00090000; 155 cpm2_immr->im_cpmux.cmx_scr |= 0x00090000;
163 pinfo->brg = 2; 156 pinfo->brg = 2;
@@ -218,8 +211,10 @@ int cpm_uart_allocbuf(struct uart_cpm_port *pinfo, unsigned int is_con)
218 211
219 memsz = L1_CACHE_ALIGN(pinfo->rx_nrfifos * pinfo->rx_fifosize) + 212 memsz = L1_CACHE_ALIGN(pinfo->rx_nrfifos * pinfo->rx_fifosize) +
220 L1_CACHE_ALIGN(pinfo->tx_nrfifos * pinfo->tx_fifosize); 213 L1_CACHE_ALIGN(pinfo->tx_nrfifos * pinfo->tx_fifosize);
221 if (is_con) 214 if (is_con) {
222 mem_addr = alloc_bootmem(memsz); 215 mem_addr = alloc_bootmem(memsz);
216 dma_addr = virt_to_bus(mem_addr);
217 }
223 else 218 else
224 mem_addr = dma_alloc_coherent(NULL, memsz, &dma_addr, 219 mem_addr = dma_alloc_coherent(NULL, memsz, &dma_addr,
225 GFP_KERNEL); 220 GFP_KERNEL);
@@ -234,6 +229,7 @@ int cpm_uart_allocbuf(struct uart_cpm_port *pinfo, unsigned int is_con)
234 pinfo->dp_addr = dp_offset; 229 pinfo->dp_addr = dp_offset;
235 pinfo->mem_addr = mem_addr; 230 pinfo->mem_addr = mem_addr;
236 pinfo->dma_addr = dma_addr; 231 pinfo->dma_addr = dma_addr;
232 pinfo->mem_size = memsz;
237 233
238 pinfo->rx_buf = mem_addr; 234 pinfo->rx_buf = mem_addr;
239 pinfo->tx_buf = pinfo->rx_buf + L1_CACHE_ALIGN(pinfo->rx_nrfifos 235 pinfo->tx_buf = pinfo->rx_buf + L1_CACHE_ALIGN(pinfo->rx_nrfifos