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authorVlad Zolotarov <vladz@broadcom.com>2011-06-14 07:33:44 -0400
committerDavid S. Miller <davem@conan.davemloft.net>2011-06-15 10:56:37 -0400
commit619c5cb6885b936c44ae1422ef805b69c6291485 (patch)
tree4604ae08f1eb12c6ad1f65106879c2e73946ae12 /drivers/scsi
parent042181f5aa8833a8918e1a91cfaf292146ffc62c (diff)
New 7.0 FW: bnx2x, cnic, bnx2i, bnx2fc
New FW/HSI (7.0): - Added support to 578xx chips - Improved HSI - much less driver's direct access to the FW internal memory needed. New implementation of the HSI handling layer in the bnx2x (bnx2x_sp.c): - Introduced chip dependent objects that have chip independent interfaces for configuration of MACs, multicast addresses, Rx mode, indirection table, fast path queues and function initialization/cleanup. - Objects functionality is based on the private function pointers, which allows not only a per-chip but also PF/VF differentiation while still preserving the same interface towards the driver. - Objects interface is not influenced by the HSI changes which do not require providing new parameters keeping the code outside the bnx2x_sp.c invariant with regard to such HSI chnages. Changes in a CNIC, bnx2fc and bnx2i modules due to the new HSI. Signed-off-by: Vladislav Zolotarov <vladz@broadcom.com> Signed-off-by: Michael Chan <mchan@broadcom.com> Signed-off-by: Bhanu Prakash Gollapudi <bprakash@broadcom.com> Signed-off-by: Eilon Greenstein <eilong@broadcom.com> Signed-off-by: David S. Miller <davem@conan.davemloft.net>
Diffstat (limited to 'drivers/scsi')
-rw-r--r--drivers/scsi/bnx2fc/57xx_hsi_bnx2fc.h1162
-rw-r--r--drivers/scsi/bnx2fc/bnx2fc.h10
-rw-r--r--drivers/scsi/bnx2fc/bnx2fc_constants.h139
-rw-r--r--drivers/scsi/bnx2fc/bnx2fc_els.c7
-rw-r--r--drivers/scsi/bnx2fc/bnx2fc_fcoe.c4
-rw-r--r--drivers/scsi/bnx2fc/bnx2fc_hwi.c442
-rw-r--r--drivers/scsi/bnx2fc/bnx2fc_io.c23
-rw-r--r--drivers/scsi/bnx2fc/bnx2fc_tgt.c24
-rw-r--r--drivers/scsi/bnx2i/57xx_iscsi_hsi.h12
9 files changed, 933 insertions, 890 deletions
diff --git a/drivers/scsi/bnx2fc/57xx_hsi_bnx2fc.h b/drivers/scsi/bnx2fc/57xx_hsi_bnx2fc.h
index 97a61b4d81b7..e1f1e3448f98 100644
--- a/drivers/scsi/bnx2fc/57xx_hsi_bnx2fc.h
+++ b/drivers/scsi/bnx2fc/57xx_hsi_bnx2fc.h
@@ -19,6 +19,23 @@ struct b577xx_doorbell_hdr {
19/* 19/*
20 * doorbell message sent to the chip 20 * doorbell message sent to the chip
21 */ 21 */
22struct b577xx_doorbell {
23#if defined(__BIG_ENDIAN)
24 u16 zero_fill2;
25 u8 zero_fill1;
26 struct b577xx_doorbell_hdr header;
27#elif defined(__LITTLE_ENDIAN)
28 struct b577xx_doorbell_hdr header;
29 u8 zero_fill1;
30 u16 zero_fill2;
31#endif
32};
33
34
35
36/*
37 * doorbell message sent to the chip
38 */
22struct b577xx_doorbell_set_prod { 39struct b577xx_doorbell_set_prod {
23#if defined(__BIG_ENDIAN) 40#if defined(__BIG_ENDIAN)
24 u16 prod; 41 u16 prod;
@@ -39,106 +56,63 @@ struct regpair {
39 56
40 57
41/* 58/*
42 * Fixed size structure in order to plant it in Union structure 59 * ABTS info $$KEEP_ENDIANNESS$$
43 */ 60 */
44struct fcoe_abts_rsp_union { 61struct fcoe_abts_info {
45 u32 r_ctl; 62 __le16 aborted_task_id;
46 u32 abts_rsp_payload[7]; 63 __le16 reserved0;
64 __le32 reserved1;
47}; 65};
48 66
49 67
50/* 68/*
51 * 4 regs size 69 * Fixed size structure in order to plant it in Union structure
70 * $$KEEP_ENDIANNESS$$
52 */ 71 */
53struct fcoe_bd_ctx { 72struct fcoe_abts_rsp_union {
54 u32 buf_addr_hi; 73 u8 r_ctl;
55 u32 buf_addr_lo; 74 u8 rsrv[3];
56#if defined(__BIG_ENDIAN) 75 __le32 abts_rsp_payload[7];
57 u16 rsrv0;
58 u16 buf_len;
59#elif defined(__LITTLE_ENDIAN)
60 u16 buf_len;
61 u16 rsrv0;
62#endif
63#if defined(__BIG_ENDIAN)
64 u16 rsrv1;
65 u16 flags;
66#elif defined(__LITTLE_ENDIAN)
67 u16 flags;
68 u16 rsrv1;
69#endif
70}; 76};
71 77
72 78
73struct fcoe_cleanup_flow_info { 79/*
74#if defined(__BIG_ENDIAN) 80 * 4 regs size $$KEEP_ENDIANNESS$$
75 u16 reserved1; 81 */
76 u16 task_id; 82struct fcoe_bd_ctx {
77#elif defined(__LITTLE_ENDIAN) 83 __le32 buf_addr_hi;
78 u16 task_id; 84 __le32 buf_addr_lo;
79 u16 reserved1; 85 __le16 buf_len;
80#endif 86 __le16 rsrv0;
81 u32 reserved2[7]; 87 __le16 flags;
88 __le16 rsrv1;
82}; 89};
83 90
84 91
85struct fcoe_fcp_cmd_payload { 92/*
86 u32 opaque[8]; 93 * FCoE cached sges context $$KEEP_ENDIANNESS$$
87}; 94 */
88 95struct fcoe_cached_sge_ctx {
89struct fcoe_fc_hdr { 96 struct regpair cur_buf_addr;
90#if defined(__BIG_ENDIAN) 97 __le16 cur_buf_rem;
91 u8 cs_ctl; 98 __le16 second_buf_rem;
92 u8 s_id[3]; 99 struct regpair second_buf_addr;
93#elif defined(__LITTLE_ENDIAN)
94 u8 s_id[3];
95 u8 cs_ctl;
96#endif
97#if defined(__BIG_ENDIAN)
98 u8 r_ctl;
99 u8 d_id[3];
100#elif defined(__LITTLE_ENDIAN)
101 u8 d_id[3];
102 u8 r_ctl;
103#endif
104#if defined(__BIG_ENDIAN)
105 u8 seq_id;
106 u8 df_ctl;
107 u16 seq_cnt;
108#elif defined(__LITTLE_ENDIAN)
109 u16 seq_cnt;
110 u8 df_ctl;
111 u8 seq_id;
112#endif
113#if defined(__BIG_ENDIAN)
114 u8 type;
115 u8 f_ctl[3];
116#elif defined(__LITTLE_ENDIAN)
117 u8 f_ctl[3];
118 u8 type;
119#endif
120 u32 parameters;
121#if defined(__BIG_ENDIAN)
122 u16 ox_id;
123 u16 rx_id;
124#elif defined(__LITTLE_ENDIAN)
125 u16 rx_id;
126 u16 ox_id;
127#endif
128}; 100};
129 101
130struct fcoe_fc_frame {
131 struct fcoe_fc_hdr fc_hdr;
132 u32 reserved0[2];
133};
134 102
135union fcoe_cmd_flow_info { 103/*
136 struct fcoe_fcp_cmd_payload fcp_cmd_payload; 104 * Cleanup info $$KEEP_ENDIANNESS$$
137 struct fcoe_fc_frame mp_fc_frame; 105 */
106struct fcoe_cleanup_info {
107 __le16 cleaned_task_id;
108 __le16 rolled_tx_seq_cnt;
109 __le32 rolled_tx_data_offset;
138}; 110};
139 111
140 112
141 113/*
114 * Fcp RSP flags $$KEEP_ENDIANNESS$$
115 */
142struct fcoe_fcp_rsp_flags { 116struct fcoe_fcp_rsp_flags {
143 u8 flags; 117 u8 flags;
144#define FCOE_FCP_RSP_FLAGS_FCP_RSP_LEN_VALID (0x1<<0) 118#define FCOE_FCP_RSP_FLAGS_FCP_RSP_LEN_VALID (0x1<<0)
@@ -155,95 +129,168 @@ struct fcoe_fcp_rsp_flags {
155#define FCOE_FCP_RSP_FLAGS_FCP_BIDI_FLAGS_SHIFT 5 129#define FCOE_FCP_RSP_FLAGS_FCP_BIDI_FLAGS_SHIFT 5
156}; 130};
157 131
158 132/*
133 * Fcp RSP payload $$KEEP_ENDIANNESS$$
134 */
159struct fcoe_fcp_rsp_payload { 135struct fcoe_fcp_rsp_payload {
160 struct regpair reserved0; 136 struct regpair reserved0;
161 u32 fcp_resid; 137 __le32 fcp_resid;
162#if defined(__BIG_ENDIAN)
163 u16 retry_delay_timer;
164 struct fcoe_fcp_rsp_flags fcp_flags;
165 u8 scsi_status_code;
166#elif defined(__LITTLE_ENDIAN)
167 u8 scsi_status_code; 138 u8 scsi_status_code;
168 struct fcoe_fcp_rsp_flags fcp_flags; 139 struct fcoe_fcp_rsp_flags fcp_flags;
169 u16 retry_delay_timer; 140 __le16 retry_delay_timer;
170#endif 141 __le32 fcp_rsp_len;
171 u32 fcp_rsp_len; 142 __le32 fcp_sns_len;
172 u32 fcp_sns_len;
173}; 143};
174 144
175
176/* 145/*
177 * Fixed size structure in order to plant it in Union structure 146 * Fixed size structure in order to plant it in Union structure
147 * $$KEEP_ENDIANNESS$$
178 */ 148 */
179struct fcoe_fcp_rsp_union { 149struct fcoe_fcp_rsp_union {
180 struct fcoe_fcp_rsp_payload payload; 150 struct fcoe_fcp_rsp_payload payload;
181 struct regpair reserved0; 151 struct regpair reserved0;
182}; 152};
183 153
154/*
155 * FC header $$KEEP_ENDIANNESS$$
156 */
157struct fcoe_fc_hdr {
158 u8 s_id[3];
159 u8 cs_ctl;
160 u8 d_id[3];
161 u8 r_ctl;
162 __le16 seq_cnt;
163 u8 df_ctl;
164 u8 seq_id;
165 u8 f_ctl[3];
166 u8 type;
167 __le32 parameters;
168 __le16 rx_id;
169 __le16 ox_id;
170};
184 171
185struct fcoe_fcp_xfr_rdy_payload { 172/*
186 u32 burst_len; 173 * FC header union $$KEEP_ENDIANNESS$$
187 u32 data_ro; 174 */
175struct fcoe_mp_rsp_union {
176 struct fcoe_fc_hdr fc_hdr;
177 __le32 mp_payload_len;
178 __le32 rsrv;
188}; 179};
189 180
190struct fcoe_read_flow_info { 181/*
191 struct fcoe_fc_hdr fc_data_in_hdr; 182 * Completion information $$KEEP_ENDIANNESS$$
192 u32 reserved[2]; 183 */
184union fcoe_comp_flow_info {
185 struct fcoe_fcp_rsp_union fcp_rsp;
186 struct fcoe_abts_rsp_union abts_rsp;
187 struct fcoe_mp_rsp_union mp_rsp;
188 __le32 opaque[8];
193}; 189};
194 190
195struct fcoe_write_flow_info { 191
196 struct fcoe_fc_hdr fc_data_out_hdr; 192/*
197 struct fcoe_fcp_xfr_rdy_payload fcp_xfr_payload; 193 * External ABTS info $$KEEP_ENDIANNESS$$
194 */
195struct fcoe_ext_abts_info {
196 __le32 rsrv0[6];
197 struct fcoe_abts_info ctx;
198}; 198};
199 199
200union fcoe_rsp_flow_info { 200
201 struct fcoe_fcp_rsp_union fcp_rsp; 201/*
202 struct fcoe_abts_rsp_union abts_rsp; 202 * External cleanup info $$KEEP_ENDIANNESS$$
203 */
204struct fcoe_ext_cleanup_info {
205 __le32 rsrv0[6];
206 struct fcoe_cleanup_info ctx;
203}; 207};
204 208
209
205/* 210/*
206 * 32 bytes used for general purposes 211 * Fcoe FW Tx sequence context $$KEEP_ENDIANNESS$$
207 */ 212 */
208union fcoe_general_task_ctx { 213struct fcoe_fw_tx_seq_ctx {
209 union fcoe_cmd_flow_info cmd_info; 214 __le32 data_offset;
210 struct fcoe_read_flow_info read_info; 215 __le16 seq_cnt;
211 struct fcoe_write_flow_info write_info; 216 __le16 rsrv0;
212 union fcoe_rsp_flow_info rsp_info; 217};
213 struct fcoe_cleanup_flow_info cleanup_info; 218
214 u32 comp_info[8]; 219/*
220 * Fcoe external FW Tx sequence context $$KEEP_ENDIANNESS$$
221 */
222struct fcoe_ext_fw_tx_seq_ctx {
223 __le32 rsrv0[6];
224 struct fcoe_fw_tx_seq_ctx ctx;
225};
226
227
228/*
229 * FCoE multiple sges context $$KEEP_ENDIANNESS$$
230 */
231struct fcoe_mul_sges_ctx {
232 struct regpair cur_sge_addr;
233 __le16 cur_sge_off;
234 u8 cur_sge_idx;
235 u8 sgl_size;
236};
237
238/*
239 * FCoE external multiple sges context $$KEEP_ENDIANNESS$$
240 */
241struct fcoe_ext_mul_sges_ctx {
242 struct fcoe_mul_sges_ctx mul_sgl;
243 struct regpair rsrv0;
215}; 244};
216 245
217 246
218/* 247/*
219 * FCoE KCQ CQE parameters 248 * FCP CMD payload $$KEEP_ENDIANNESS$$
249 */
250struct fcoe_fcp_cmd_payload {
251 __le32 opaque[8];
252};
253
254
255
256
257
258/*
259 * Fcp xfr rdy payload $$KEEP_ENDIANNESS$$
260 */
261struct fcoe_fcp_xfr_rdy_payload {
262 __le32 burst_len;
263 __le32 data_ro;
264};
265
266
267/*
268 * FC frame $$KEEP_ENDIANNESS$$
269 */
270struct fcoe_fc_frame {
271 struct fcoe_fc_hdr fc_hdr;
272 __le32 reserved0[2];
273};
274
275
276
277
278/*
279 * FCoE KCQ CQE parameters $$KEEP_ENDIANNESS$$
220 */ 280 */
221union fcoe_kcqe_params { 281union fcoe_kcqe_params {
222 u32 reserved0[4]; 282 __le32 reserved0[4];
223}; 283};
224 284
225/* 285/*
226 * FCoE KCQ CQE 286 * FCoE KCQ CQE $$KEEP_ENDIANNESS$$
227 */ 287 */
228struct fcoe_kcqe { 288struct fcoe_kcqe {
229 u32 fcoe_conn_id; 289 __le32 fcoe_conn_id;
230 u32 completion_status; 290 __le32 completion_status;
231 u32 fcoe_conn_context_id; 291 __le32 fcoe_conn_context_id;
232 union fcoe_kcqe_params params; 292 union fcoe_kcqe_params params;
233#if defined(__BIG_ENDIAN) 293 __le16 qe_self_seq;
234 u8 flags;
235#define FCOE_KCQE_RESERVED0 (0x7<<0)
236#define FCOE_KCQE_RESERVED0_SHIFT 0
237#define FCOE_KCQE_RAMROD_COMPLETION (0x1<<3)
238#define FCOE_KCQE_RAMROD_COMPLETION_SHIFT 3
239#define FCOE_KCQE_LAYER_CODE (0x7<<4)
240#define FCOE_KCQE_LAYER_CODE_SHIFT 4
241#define FCOE_KCQE_LINKED_WITH_NEXT (0x1<<7)
242#define FCOE_KCQE_LINKED_WITH_NEXT_SHIFT 7
243 u8 op_code;
244 u16 qe_self_seq;
245#elif defined(__LITTLE_ENDIAN)
246 u16 qe_self_seq;
247 u8 op_code; 294 u8 op_code;
248 u8 flags; 295 u8 flags;
249#define FCOE_KCQE_RESERVED0 (0x7<<0) 296#define FCOE_KCQE_RESERVED0 (0x7<<0)
@@ -254,23 +301,14 @@ struct fcoe_kcqe {
254#define FCOE_KCQE_LAYER_CODE_SHIFT 4 301#define FCOE_KCQE_LAYER_CODE_SHIFT 4
255#define FCOE_KCQE_LINKED_WITH_NEXT (0x1<<7) 302#define FCOE_KCQE_LINKED_WITH_NEXT (0x1<<7)
256#define FCOE_KCQE_LINKED_WITH_NEXT_SHIFT 7 303#define FCOE_KCQE_LINKED_WITH_NEXT_SHIFT 7
257#endif
258}; 304};
259 305
306
307
260/* 308/*
261 * FCoE KWQE header 309 * FCoE KWQE header $$KEEP_ENDIANNESS$$
262 */ 310 */
263struct fcoe_kwqe_header { 311struct fcoe_kwqe_header {
264#if defined(__BIG_ENDIAN)
265 u8 flags;
266#define FCOE_KWQE_HEADER_RESERVED0 (0xF<<0)
267#define FCOE_KWQE_HEADER_RESERVED0_SHIFT 0
268#define FCOE_KWQE_HEADER_LAYER_CODE (0x7<<4)
269#define FCOE_KWQE_HEADER_LAYER_CODE_SHIFT 4
270#define FCOE_KWQE_HEADER_RESERVED1 (0x1<<7)
271#define FCOE_KWQE_HEADER_RESERVED1_SHIFT 7
272 u8 op_code;
273#elif defined(__LITTLE_ENDIAN)
274 u8 op_code; 312 u8 op_code;
275 u8 flags; 313 u8 flags;
276#define FCOE_KWQE_HEADER_RESERVED0 (0xF<<0) 314#define FCOE_KWQE_HEADER_RESERVED0 (0xF<<0)
@@ -279,50 +317,23 @@ struct fcoe_kwqe_header {
279#define FCOE_KWQE_HEADER_LAYER_CODE_SHIFT 4 317#define FCOE_KWQE_HEADER_LAYER_CODE_SHIFT 4
280#define FCOE_KWQE_HEADER_RESERVED1 (0x1<<7) 318#define FCOE_KWQE_HEADER_RESERVED1 (0x1<<7)
281#define FCOE_KWQE_HEADER_RESERVED1_SHIFT 7 319#define FCOE_KWQE_HEADER_RESERVED1_SHIFT 7
282#endif
283}; 320};
284 321
285/* 322/*
286 * FCoE firmware init request 1 323 * FCoE firmware init request 1 $$KEEP_ENDIANNESS$$
287 */ 324 */
288struct fcoe_kwqe_init1 { 325struct fcoe_kwqe_init1 {
289#if defined(__BIG_ENDIAN) 326 __le16 num_tasks;
290 struct fcoe_kwqe_header hdr; 327 struct fcoe_kwqe_header hdr;
291 u16 num_tasks; 328 __le32 task_list_pbl_addr_lo;
292#elif defined(__LITTLE_ENDIAN) 329 __le32 task_list_pbl_addr_hi;
293 u16 num_tasks; 330 __le32 dummy_buffer_addr_lo;
294 struct fcoe_kwqe_header hdr; 331 __le32 dummy_buffer_addr_hi;
295#endif 332 __le16 sq_num_wqes;
296 u32 task_list_pbl_addr_lo; 333 __le16 rq_num_wqes;
297 u32 task_list_pbl_addr_hi; 334 __le16 rq_buffer_log_size;
298 u32 dummy_buffer_addr_lo; 335 __le16 cq_num_wqes;
299 u32 dummy_buffer_addr_hi; 336 __le16 mtu;
300#if defined(__BIG_ENDIAN)
301 u16 rq_num_wqes;
302 u16 sq_num_wqes;
303#elif defined(__LITTLE_ENDIAN)
304 u16 sq_num_wqes;
305 u16 rq_num_wqes;
306#endif
307#if defined(__BIG_ENDIAN)
308 u16 cq_num_wqes;
309 u16 rq_buffer_log_size;
310#elif defined(__LITTLE_ENDIAN)
311 u16 rq_buffer_log_size;
312 u16 cq_num_wqes;
313#endif
314#if defined(__BIG_ENDIAN)
315 u8 flags;
316#define FCOE_KWQE_INIT1_LOG_PAGE_SIZE (0xF<<0)
317#define FCOE_KWQE_INIT1_LOG_PAGE_SIZE_SHIFT 0
318#define FCOE_KWQE_INIT1_LOG_CACHED_PBES_PER_FUNC (0x7<<4)
319#define FCOE_KWQE_INIT1_LOG_CACHED_PBES_PER_FUNC_SHIFT 4
320#define FCOE_KWQE_INIT1_RESERVED1 (0x1<<7)
321#define FCOE_KWQE_INIT1_RESERVED1_SHIFT 7
322 u8 num_sessions_log;
323 u16 mtu;
324#elif defined(__LITTLE_ENDIAN)
325 u16 mtu;
326 u8 num_sessions_log; 337 u8 num_sessions_log;
327 u8 flags; 338 u8 flags;
328#define FCOE_KWQE_INIT1_LOG_PAGE_SIZE (0xF<<0) 339#define FCOE_KWQE_INIT1_LOG_PAGE_SIZE (0xF<<0)
@@ -331,113 +342,73 @@ struct fcoe_kwqe_init1 {
331#define FCOE_KWQE_INIT1_LOG_CACHED_PBES_PER_FUNC_SHIFT 4 342#define FCOE_KWQE_INIT1_LOG_CACHED_PBES_PER_FUNC_SHIFT 4
332#define FCOE_KWQE_INIT1_RESERVED1 (0x1<<7) 343#define FCOE_KWQE_INIT1_RESERVED1 (0x1<<7)
333#define FCOE_KWQE_INIT1_RESERVED1_SHIFT 7 344#define FCOE_KWQE_INIT1_RESERVED1_SHIFT 7
334#endif
335}; 345};
336 346
337/* 347/*
338 * FCoE firmware init request 2 348 * FCoE firmware init request 2 $$KEEP_ENDIANNESS$$
339 */ 349 */
340struct fcoe_kwqe_init2 { 350struct fcoe_kwqe_init2 {
341#if defined(__BIG_ENDIAN) 351 u8 hsi_major_version;
342 struct fcoe_kwqe_header hdr; 352 u8 hsi_minor_version;
343 u16 reserved0;
344#elif defined(__LITTLE_ENDIAN)
345 u16 reserved0;
346 struct fcoe_kwqe_header hdr; 353 struct fcoe_kwqe_header hdr;
347#endif 354 __le32 hash_tbl_pbl_addr_lo;
348 u32 hash_tbl_pbl_addr_lo; 355 __le32 hash_tbl_pbl_addr_hi;
349 u32 hash_tbl_pbl_addr_hi; 356 __le32 t2_hash_tbl_addr_lo;
350 u32 t2_hash_tbl_addr_lo; 357 __le32 t2_hash_tbl_addr_hi;
351 u32 t2_hash_tbl_addr_hi; 358 __le32 t2_ptr_hash_tbl_addr_lo;
352 u32 t2_ptr_hash_tbl_addr_lo; 359 __le32 t2_ptr_hash_tbl_addr_hi;
353 u32 t2_ptr_hash_tbl_addr_hi; 360 __le32 free_list_count;
354 u32 free_list_count;
355}; 361};
356 362
357/* 363/*
358 * FCoE firmware init request 3 364 * FCoE firmware init request 3 $$KEEP_ENDIANNESS$$
359 */ 365 */
360struct fcoe_kwqe_init3 { 366struct fcoe_kwqe_init3 {
361#if defined(__BIG_ENDIAN) 367 __le16 reserved0;
362 struct fcoe_kwqe_header hdr;
363 u16 reserved0;
364#elif defined(__LITTLE_ENDIAN)
365 u16 reserved0;
366 struct fcoe_kwqe_header hdr; 368 struct fcoe_kwqe_header hdr;
367#endif 369 __le32 error_bit_map_lo;
368 u32 error_bit_map_lo; 370 __le32 error_bit_map_hi;
369 u32 error_bit_map_hi; 371 u8 perf_config;
370#if defined(__BIG_ENDIAN)
371 u8 reserved21[3];
372 u8 cached_session_enable;
373#elif defined(__LITTLE_ENDIAN)
374 u8 cached_session_enable;
375 u8 reserved21[3]; 372 u8 reserved21[3];
376#endif 373 __le32 reserved2[4];
377 u32 reserved2[4];
378}; 374};
379 375
380/* 376/*
381 * FCoE connection offload request 1 377 * FCoE connection offload request 1 $$KEEP_ENDIANNESS$$
382 */ 378 */
383struct fcoe_kwqe_conn_offload1 { 379struct fcoe_kwqe_conn_offload1 {
384#if defined(__BIG_ENDIAN) 380 __le16 fcoe_conn_id;
385 struct fcoe_kwqe_header hdr; 381 struct fcoe_kwqe_header hdr;
386 u16 fcoe_conn_id; 382 __le32 sq_addr_lo;
387#elif defined(__LITTLE_ENDIAN) 383 __le32 sq_addr_hi;
388 u16 fcoe_conn_id; 384 __le32 rq_pbl_addr_lo;
389 struct fcoe_kwqe_header hdr; 385 __le32 rq_pbl_addr_hi;
390#endif 386 __le32 rq_first_pbe_addr_lo;
391 u32 sq_addr_lo; 387 __le32 rq_first_pbe_addr_hi;
392 u32 sq_addr_hi; 388 __le16 rq_prod;
393 u32 rq_pbl_addr_lo; 389 __le16 reserved0;
394 u32 rq_pbl_addr_hi;
395 u32 rq_first_pbe_addr_lo;
396 u32 rq_first_pbe_addr_hi;
397#if defined(__BIG_ENDIAN)
398 u16 reserved0;
399 u16 rq_prod;
400#elif defined(__LITTLE_ENDIAN)
401 u16 rq_prod;
402 u16 reserved0;
403#endif
404}; 390};
405 391
406/* 392/*
407 * FCoE connection offload request 2 393 * FCoE connection offload request 2 $$KEEP_ENDIANNESS$$
408 */ 394 */
409struct fcoe_kwqe_conn_offload2 { 395struct fcoe_kwqe_conn_offload2 {
410#if defined(__BIG_ENDIAN) 396 __le16 tx_max_fc_pay_len;
411 struct fcoe_kwqe_header hdr;
412 u16 tx_max_fc_pay_len;
413#elif defined(__LITTLE_ENDIAN)
414 u16 tx_max_fc_pay_len;
415 struct fcoe_kwqe_header hdr; 397 struct fcoe_kwqe_header hdr;
416#endif 398 __le32 cq_addr_lo;
417 u32 cq_addr_lo; 399 __le32 cq_addr_hi;
418 u32 cq_addr_hi; 400 __le32 xferq_addr_lo;
419 u32 xferq_addr_lo; 401 __le32 xferq_addr_hi;
420 u32 xferq_addr_hi; 402 __le32 conn_db_addr_lo;
421 u32 conn_db_addr_lo; 403 __le32 conn_db_addr_hi;
422 u32 conn_db_addr_hi; 404 __le32 reserved1;
423 u32 reserved1;
424}; 405};
425 406
426/* 407/*
427 * FCoE connection offload request 3 408 * FCoE connection offload request 3 $$KEEP_ENDIANNESS$$
428 */ 409 */
429struct fcoe_kwqe_conn_offload3 { 410struct fcoe_kwqe_conn_offload3 {
430#if defined(__BIG_ENDIAN) 411 __le16 vlan_tag;
431 struct fcoe_kwqe_header hdr;
432 u16 vlan_tag;
433#define FCOE_KWQE_CONN_OFFLOAD3_VLAN_ID (0xFFF<<0)
434#define FCOE_KWQE_CONN_OFFLOAD3_VLAN_ID_SHIFT 0
435#define FCOE_KWQE_CONN_OFFLOAD3_CFI (0x1<<12)
436#define FCOE_KWQE_CONN_OFFLOAD3_CFI_SHIFT 12
437#define FCOE_KWQE_CONN_OFFLOAD3_PRIORITY (0x7<<13)
438#define FCOE_KWQE_CONN_OFFLOAD3_PRIORITY_SHIFT 13
439#elif defined(__LITTLE_ENDIAN)
440 u16 vlan_tag;
441#define FCOE_KWQE_CONN_OFFLOAD3_VLAN_ID (0xFFF<<0) 412#define FCOE_KWQE_CONN_OFFLOAD3_VLAN_ID (0xFFF<<0)
442#define FCOE_KWQE_CONN_OFFLOAD3_VLAN_ID_SHIFT 0 413#define FCOE_KWQE_CONN_OFFLOAD3_VLAN_ID_SHIFT 0
443#define FCOE_KWQE_CONN_OFFLOAD3_CFI (0x1<<12) 414#define FCOE_KWQE_CONN_OFFLOAD3_CFI (0x1<<12)
@@ -445,34 +416,8 @@ struct fcoe_kwqe_conn_offload3 {
445#define FCOE_KWQE_CONN_OFFLOAD3_PRIORITY (0x7<<13) 416#define FCOE_KWQE_CONN_OFFLOAD3_PRIORITY (0x7<<13)
446#define FCOE_KWQE_CONN_OFFLOAD3_PRIORITY_SHIFT 13 417#define FCOE_KWQE_CONN_OFFLOAD3_PRIORITY_SHIFT 13
447 struct fcoe_kwqe_header hdr; 418 struct fcoe_kwqe_header hdr;
448#endif
449#if defined(__BIG_ENDIAN)
450 u8 tx_max_conc_seqs_c3;
451 u8 s_id[3];
452#elif defined(__LITTLE_ENDIAN)
453 u8 s_id[3]; 419 u8 s_id[3];
454 u8 tx_max_conc_seqs_c3; 420 u8 tx_max_conc_seqs_c3;
455#endif
456#if defined(__BIG_ENDIAN)
457 u8 flags;
458#define FCOE_KWQE_CONN_OFFLOAD3_B_MUL_N_PORT_IDS (0x1<<0)
459#define FCOE_KWQE_CONN_OFFLOAD3_B_MUL_N_PORT_IDS_SHIFT 0
460#define FCOE_KWQE_CONN_OFFLOAD3_B_E_D_TOV_RES (0x1<<1)
461#define FCOE_KWQE_CONN_OFFLOAD3_B_E_D_TOV_RES_SHIFT 1
462#define FCOE_KWQE_CONN_OFFLOAD3_B_CONT_INCR_SEQ_CNT (0x1<<2)
463#define FCOE_KWQE_CONN_OFFLOAD3_B_CONT_INCR_SEQ_CNT_SHIFT 2
464#define FCOE_KWQE_CONN_OFFLOAD3_B_CONF_REQ (0x1<<3)
465#define FCOE_KWQE_CONN_OFFLOAD3_B_CONF_REQ_SHIFT 3
466#define FCOE_KWQE_CONN_OFFLOAD3_B_REC_VALID (0x1<<4)
467#define FCOE_KWQE_CONN_OFFLOAD3_B_REC_VALID_SHIFT 4
468#define FCOE_KWQE_CONN_OFFLOAD3_B_C2_VALID (0x1<<5)
469#define FCOE_KWQE_CONN_OFFLOAD3_B_C2_VALID_SHIFT 5
470#define FCOE_KWQE_CONN_OFFLOAD3_B_ACK_0 (0x1<<6)
471#define FCOE_KWQE_CONN_OFFLOAD3_B_ACK_0_SHIFT 6
472#define FCOE_KWQE_CONN_OFFLOAD3_B_VLAN_FLAG (0x1<<7)
473#define FCOE_KWQE_CONN_OFFLOAD3_B_VLAN_FLAG_SHIFT 7
474 u8 d_id[3];
475#elif defined(__LITTLE_ENDIAN)
476 u8 d_id[3]; 421 u8 d_id[3];
477 u8 flags; 422 u8 flags;
478#define FCOE_KWQE_CONN_OFFLOAD3_B_MUL_N_PORT_IDS (0x1<<0) 423#define FCOE_KWQE_CONN_OFFLOAD3_B_MUL_N_PORT_IDS (0x1<<0)
@@ -491,79 +436,44 @@ struct fcoe_kwqe_conn_offload3 {
491#define FCOE_KWQE_CONN_OFFLOAD3_B_ACK_0_SHIFT 6 436#define FCOE_KWQE_CONN_OFFLOAD3_B_ACK_0_SHIFT 6
492#define FCOE_KWQE_CONN_OFFLOAD3_B_VLAN_FLAG (0x1<<7) 437#define FCOE_KWQE_CONN_OFFLOAD3_B_VLAN_FLAG (0x1<<7)
493#define FCOE_KWQE_CONN_OFFLOAD3_B_VLAN_FLAG_SHIFT 7 438#define FCOE_KWQE_CONN_OFFLOAD3_B_VLAN_FLAG_SHIFT 7
494#endif 439 __le32 reserved;
495 u32 reserved; 440 __le32 confq_first_pbe_addr_lo;
496 u32 confq_first_pbe_addr_lo; 441 __le32 confq_first_pbe_addr_hi;
497 u32 confq_first_pbe_addr_hi; 442 __le16 tx_total_conc_seqs;
498#if defined(__BIG_ENDIAN) 443 __le16 rx_max_fc_pay_len;
499 u16 rx_max_fc_pay_len; 444 __le16 rx_total_conc_seqs;
500 u16 tx_total_conc_seqs;
501#elif defined(__LITTLE_ENDIAN)
502 u16 tx_total_conc_seqs;
503 u16 rx_max_fc_pay_len;
504#endif
505#if defined(__BIG_ENDIAN)
506 u8 rx_open_seqs_exch_c3;
507 u8 rx_max_conc_seqs_c3;
508 u16 rx_total_conc_seqs;
509#elif defined(__LITTLE_ENDIAN)
510 u16 rx_total_conc_seqs;
511 u8 rx_max_conc_seqs_c3; 445 u8 rx_max_conc_seqs_c3;
512 u8 rx_open_seqs_exch_c3; 446 u8 rx_open_seqs_exch_c3;
513#endif
514}; 447};
515 448
516/* 449/*
517 * FCoE connection offload request 4 450 * FCoE connection offload request 4 $$KEEP_ENDIANNESS$$
518 */ 451 */
519struct fcoe_kwqe_conn_offload4 { 452struct fcoe_kwqe_conn_offload4 {
520#if defined(__BIG_ENDIAN)
521 struct fcoe_kwqe_header hdr;
522 u8 reserved2;
523 u8 e_d_tov_timer_val;
524#elif defined(__LITTLE_ENDIAN)
525 u8 e_d_tov_timer_val; 453 u8 e_d_tov_timer_val;
526 u8 reserved2; 454 u8 reserved2;
527 struct fcoe_kwqe_header hdr; 455 struct fcoe_kwqe_header hdr;
528#endif 456 u8 src_mac_addr_lo[2];
529 u8 src_mac_addr_lo32[4]; 457 u8 src_mac_addr_mid[2];
530#if defined(__BIG_ENDIAN) 458 u8 src_mac_addr_hi[2];
531 u8 dst_mac_addr_hi16[2]; 459 u8 dst_mac_addr_hi[2];
532 u8 src_mac_addr_hi16[2]; 460 u8 dst_mac_addr_lo[2];
533#elif defined(__LITTLE_ENDIAN) 461 u8 dst_mac_addr_mid[2];
534 u8 src_mac_addr_hi16[2]; 462 __le32 lcq_addr_lo;
535 u8 dst_mac_addr_hi16[2]; 463 __le32 lcq_addr_hi;
536#endif 464 __le32 confq_pbl_base_addr_lo;
537 u8 dst_mac_addr_lo32[4]; 465 __le32 confq_pbl_base_addr_hi;
538 u32 lcq_addr_lo;
539 u32 lcq_addr_hi;
540 u32 confq_pbl_base_addr_lo;
541 u32 confq_pbl_base_addr_hi;
542}; 466};
543 467
544/* 468/*
545 * FCoE connection enable request 469 * FCoE connection enable request $$KEEP_ENDIANNESS$$
546 */ 470 */
547struct fcoe_kwqe_conn_enable_disable { 471struct fcoe_kwqe_conn_enable_disable {
548#if defined(__BIG_ENDIAN) 472 __le16 reserved0;
549 struct fcoe_kwqe_header hdr;
550 u16 reserved0;
551#elif defined(__LITTLE_ENDIAN)
552 u16 reserved0;
553 struct fcoe_kwqe_header hdr; 473 struct fcoe_kwqe_header hdr;
554#endif 474 u8 src_mac_addr_lo[2];
555 u8 src_mac_addr_lo32[4]; 475 u8 src_mac_addr_mid[2];
556#if defined(__BIG_ENDIAN) 476 u8 src_mac_addr_hi[2];
557 u16 vlan_tag;
558#define FCOE_KWQE_CONN_ENABLE_DISABLE_VLAN_ID (0xFFF<<0)
559#define FCOE_KWQE_CONN_ENABLE_DISABLE_VLAN_ID_SHIFT 0
560#define FCOE_KWQE_CONN_ENABLE_DISABLE_CFI (0x1<<12)
561#define FCOE_KWQE_CONN_ENABLE_DISABLE_CFI_SHIFT 12
562#define FCOE_KWQE_CONN_ENABLE_DISABLE_PRIORITY (0x7<<13)
563#define FCOE_KWQE_CONN_ENABLE_DISABLE_PRIORITY_SHIFT 13
564 u8 src_mac_addr_hi16[2];
565#elif defined(__LITTLE_ENDIAN)
566 u8 src_mac_addr_hi16[2];
567 u16 vlan_tag; 477 u16 vlan_tag;
568#define FCOE_KWQE_CONN_ENABLE_DISABLE_VLAN_ID (0xFFF<<0) 478#define FCOE_KWQE_CONN_ENABLE_DISABLE_VLAN_ID (0xFFF<<0)
569#define FCOE_KWQE_CONN_ENABLE_DISABLE_VLAN_ID_SHIFT 0 479#define FCOE_KWQE_CONN_ENABLE_DISABLE_VLAN_ID_SHIFT 0
@@ -571,82 +481,52 @@ struct fcoe_kwqe_conn_enable_disable {
571#define FCOE_KWQE_CONN_ENABLE_DISABLE_CFI_SHIFT 12 481#define FCOE_KWQE_CONN_ENABLE_DISABLE_CFI_SHIFT 12
572#define FCOE_KWQE_CONN_ENABLE_DISABLE_PRIORITY (0x7<<13) 482#define FCOE_KWQE_CONN_ENABLE_DISABLE_PRIORITY (0x7<<13)
573#define FCOE_KWQE_CONN_ENABLE_DISABLE_PRIORITY_SHIFT 13 483#define FCOE_KWQE_CONN_ENABLE_DISABLE_PRIORITY_SHIFT 13
574#endif 484 u8 dst_mac_addr_lo[2];
575 u8 dst_mac_addr_lo32[4]; 485 u8 dst_mac_addr_mid[2];
576#if defined(__BIG_ENDIAN) 486 u8 dst_mac_addr_hi[2];
577 u16 reserved1; 487 __le16 reserved1;
578 u8 dst_mac_addr_hi16[2];
579#elif defined(__LITTLE_ENDIAN)
580 u8 dst_mac_addr_hi16[2];
581 u16 reserved1;
582#endif
583#if defined(__BIG_ENDIAN)
584 u8 vlan_flag;
585 u8 s_id[3];
586#elif defined(__LITTLE_ENDIAN)
587 u8 s_id[3]; 488 u8 s_id[3];
588 u8 vlan_flag; 489 u8 vlan_flag;
589#endif
590#if defined(__BIG_ENDIAN)
591 u8 reserved3;
592 u8 d_id[3];
593#elif defined(__LITTLE_ENDIAN)
594 u8 d_id[3]; 490 u8 d_id[3];
595 u8 reserved3; 491 u8 reserved3;
596#endif 492 __le32 context_id;
597 u32 context_id; 493 __le32 conn_id;
598 u32 conn_id; 494 __le32 reserved4;
599 u32 reserved4;
600}; 495};
601 496
602/* 497/*
603 * FCoE connection destroy request 498 * FCoE connection destroy request $$KEEP_ENDIANNESS$$
604 */ 499 */
605struct fcoe_kwqe_conn_destroy { 500struct fcoe_kwqe_conn_destroy {
606#if defined(__BIG_ENDIAN) 501 __le16 reserved0;
607 struct fcoe_kwqe_header hdr;
608 u16 reserved0;
609#elif defined(__LITTLE_ENDIAN)
610 u16 reserved0;
611 struct fcoe_kwqe_header hdr; 502 struct fcoe_kwqe_header hdr;
612#endif 503 __le32 context_id;
613 u32 context_id; 504 __le32 conn_id;
614 u32 conn_id; 505 __le32 reserved1[5];
615 u32 reserved1[5];
616}; 506};
617 507
618/* 508/*
619 * FCoe destroy request 509 * FCoe destroy request $$KEEP_ENDIANNESS$$
620 */ 510 */
621struct fcoe_kwqe_destroy { 511struct fcoe_kwqe_destroy {
622#if defined(__BIG_ENDIAN) 512 __le16 reserved0;
623 struct fcoe_kwqe_header hdr;
624 u16 reserved0;
625#elif defined(__LITTLE_ENDIAN)
626 u16 reserved0;
627 struct fcoe_kwqe_header hdr; 513 struct fcoe_kwqe_header hdr;
628#endif 514 __le32 reserved1[7];
629 u32 reserved1[7];
630}; 515};
631 516
632/* 517/*
633 * FCoe statistics request 518 * FCoe statistics request $$KEEP_ENDIANNESS$$
634 */ 519 */
635struct fcoe_kwqe_stat { 520struct fcoe_kwqe_stat {
636#if defined(__BIG_ENDIAN) 521 __le16 reserved0;
637 struct fcoe_kwqe_header hdr; 522 struct fcoe_kwqe_header hdr;
638 u16 reserved0; 523 __le32 stat_params_addr_lo;
639#elif defined(__LITTLE_ENDIAN) 524 __le32 stat_params_addr_hi;
640 u16 reserved0; 525 __le32 reserved1[5];
641 struct fcoe_kwqe_header hdr;
642#endif
643 u32 stat_params_addr_lo;
644 u32 stat_params_addr_hi;
645 u32 reserved1[5];
646}; 526};
647 527
648/* 528/*
649 * FCoE KWQ WQE 529 * FCoE KWQ WQE $$KEEP_ENDIANNESS$$
650 */ 530 */
651union fcoe_kwqe { 531union fcoe_kwqe {
652 struct fcoe_kwqe_init1 init1; 532 struct fcoe_kwqe_init1 init1;
@@ -662,19 +542,42 @@ union fcoe_kwqe {
662 struct fcoe_kwqe_stat statistics; 542 struct fcoe_kwqe_stat statistics;
663}; 543};
664 544
665struct fcoe_mul_sges_ctx { 545
666 struct regpair cur_sge_addr; 546
667#if defined(__BIG_ENDIAN) 547
668 u8 sgl_size; 548
669 u8 cur_sge_idx; 549
670 u16 cur_sge_off; 550
671#elif defined(__LITTLE_ENDIAN) 551
672 u16 cur_sge_off; 552
673 u8 cur_sge_idx; 553
674 u8 sgl_size; 554
675#endif 555
556
557
558
559
560/*
561 * TX SGL context $$KEEP_ENDIANNESS$$
562 */
563union fcoe_sgl_union_ctx {
564 struct fcoe_cached_sge_ctx cached_sge;
565 struct fcoe_ext_mul_sges_ctx sgl;
566 __le32 opaque[5];
676}; 567};
677 568
569/*
570 * Data-In/ELS/BLS information $$KEEP_ENDIANNESS$$
571 */
572struct fcoe_read_flow_info {
573 union fcoe_sgl_union_ctx sgl_ctx;
574 __le32 rsrv0[3];
575};
576
577
578/*
579 * Fcoe stat context $$KEEP_ENDIANNESS$$
580 */
678struct fcoe_s_stat_ctx { 581struct fcoe_s_stat_ctx {
679 u8 flags; 582 u8 flags;
680#define FCOE_S_STAT_CTX_ACTIVE (0x1<<0) 583#define FCOE_S_STAT_CTX_ACTIVE (0x1<<0)
@@ -693,51 +596,34 @@ struct fcoe_s_stat_ctx {
693#define FCOE_S_STAT_CTX_RSRV1_SHIFT 6 596#define FCOE_S_STAT_CTX_RSRV1_SHIFT 6
694}; 597};
695 598
696struct fcoe_seq_ctx { 599/*
697#if defined(__BIG_ENDIAN) 600 * Fcoe rx seq context $$KEEP_ENDIANNESS$$
698 u16 low_seq_cnt; 601 */
699 struct fcoe_s_stat_ctx s_stat; 602struct fcoe_rx_seq_ctx {
700 u8 seq_id;
701#elif defined(__LITTLE_ENDIAN)
702 u8 seq_id; 603 u8 seq_id;
703 struct fcoe_s_stat_ctx s_stat; 604 struct fcoe_s_stat_ctx s_stat;
704 u16 low_seq_cnt; 605 __le16 seq_cnt;
705#endif 606 __le32 low_exp_ro;
706#if defined(__BIG_ENDIAN) 607 __le32 high_exp_ro;
707 u16 err_seq_cnt;
708 u16 high_seq_cnt;
709#elif defined(__LITTLE_ENDIAN)
710 u16 high_seq_cnt;
711 u16 err_seq_cnt;
712#endif
713 u32 low_exp_ro;
714 u32 high_exp_ro;
715}; 608};
716 609
717 610
718struct fcoe_single_sge_ctx { 611/*
719 struct regpair cur_buf_addr; 612 * Fcoe rx_wr union context $$KEEP_ENDIANNESS$$
720#if defined(__BIG_ENDIAN) 613 */
721 u16 reserved0; 614union fcoe_rx_wr_union_ctx {
722 u16 cur_buf_rem; 615 struct fcoe_read_flow_info read_info;
723#elif defined(__LITTLE_ENDIAN) 616 union fcoe_comp_flow_info comp_info;
724 u16 cur_buf_rem; 617 __le32 opaque[8];
725 u16 reserved0;
726#endif
727};
728
729union fcoe_sgl_ctx {
730 struct fcoe_single_sge_ctx single_sge;
731 struct fcoe_mul_sges_ctx mul_sges;
732}; 618};
733 619
734 620
735 621
736/* 622/*
737 * FCoE SQ element 623 * FCoE SQ element $$KEEP_ENDIANNESS$$
738 */ 624 */
739struct fcoe_sqe { 625struct fcoe_sqe {
740 u16 wqe; 626 __le16 wqe;
741#define FCOE_SQE_TASK_ID (0x7FFF<<0) 627#define FCOE_SQE_TASK_ID (0x7FFF<<0)
742#define FCOE_SQE_TASK_ID_SHIFT 0 628#define FCOE_SQE_TASK_ID_SHIFT 0
743#define FCOE_SQE_TOGGLE_BIT (0x1<<15) 629#define FCOE_SQE_TOGGLE_BIT (0x1<<15)
@@ -746,135 +632,141 @@ struct fcoe_sqe {
746 632
747 633
748 634
749struct fcoe_task_ctx_entry_tx_only { 635/*
750 union fcoe_sgl_ctx sgl_ctx; 636 * 14 regs $$KEEP_ENDIANNESS$$
637 */
638struct fcoe_tce_tx_only {
639 union fcoe_sgl_union_ctx sgl_ctx;
640 __le32 rsrv0;
751}; 641};
752 642
753struct fcoe_task_ctx_entry_txwr_rxrd { 643/*
754#if defined(__BIG_ENDIAN) 644 * 32 bytes (8 regs) used for TX only purposes $$KEEP_ENDIANNESS$$
755 u16 verify_tx_seq; 645 */
646union fcoe_tx_wr_rx_rd_union_ctx {
647 struct fcoe_fc_frame tx_frame;
648 struct fcoe_fcp_cmd_payload fcp_cmd;
649 struct fcoe_ext_cleanup_info cleanup;
650 struct fcoe_ext_abts_info abts;
651 struct fcoe_ext_fw_tx_seq_ctx tx_seq;
652 __le32 opaque[8];
653};
654
655/*
656 * tce_tx_wr_rx_rd_const $$KEEP_ENDIANNESS$$
657 */
658struct fcoe_tce_tx_wr_rx_rd_const {
756 u8 init_flags; 659 u8 init_flags;
757#define FCOE_TASK_CTX_ENTRY_TXWR_RXRD_TASK_TYPE (0x7<<0) 660#define FCOE_TCE_TX_WR_RX_RD_CONST_TASK_TYPE (0x7<<0)
758#define FCOE_TASK_CTX_ENTRY_TXWR_RXRD_TASK_TYPE_SHIFT 0 661#define FCOE_TCE_TX_WR_RX_RD_CONST_TASK_TYPE_SHIFT 0
759#define FCOE_TASK_CTX_ENTRY_TXWR_RXRD_DEV_TYPE (0x1<<3) 662#define FCOE_TCE_TX_WR_RX_RD_CONST_DEV_TYPE (0x1<<3)
760#define FCOE_TASK_CTX_ENTRY_TXWR_RXRD_DEV_TYPE_SHIFT 3 663#define FCOE_TCE_TX_WR_RX_RD_CONST_DEV_TYPE_SHIFT 3
761#define FCOE_TASK_CTX_ENTRY_TXWR_RXRD_CLASS_TYPE (0x1<<4) 664#define FCOE_TCE_TX_WR_RX_RD_CONST_CLASS_TYPE (0x1<<4)
762#define FCOE_TASK_CTX_ENTRY_TXWR_RXRD_CLASS_TYPE_SHIFT 4 665#define FCOE_TCE_TX_WR_RX_RD_CONST_CLASS_TYPE_SHIFT 4
763#define FCOE_TASK_CTX_ENTRY_TXWR_RXRD_SINGLE_SGE (0x1<<5) 666#define FCOE_TCE_TX_WR_RX_RD_CONST_CACHED_SGE (0x3<<5)
764#define FCOE_TASK_CTX_ENTRY_TXWR_RXRD_SINGLE_SGE_SHIFT 5 667#define FCOE_TCE_TX_WR_RX_RD_CONST_CACHED_SGE_SHIFT 5
765#define FCOE_TASK_CTX_ENTRY_TXWR_RXRD_RSRV5 (0x3<<6) 668#define FCOE_TCE_TX_WR_RX_RD_CONST_SUPPORT_REC_TOV (0x1<<7)
766#define FCOE_TASK_CTX_ENTRY_TXWR_RXRD_RSRV5_SHIFT 6 669#define FCOE_TCE_TX_WR_RX_RD_CONST_SUPPORT_REC_TOV_SHIFT 7
767 u8 tx_flags;
768#define FCOE_TASK_CTX_ENTRY_TXWR_RXRD_TX_STATE (0xF<<0)
769#define FCOE_TASK_CTX_ENTRY_TXWR_RXRD_TX_STATE_SHIFT 0
770#define FCOE_TASK_CTX_ENTRY_TXWR_RXRD_RSRV4 (0xF<<4)
771#define FCOE_TASK_CTX_ENTRY_TXWR_RXRD_RSRV4_SHIFT 4
772#elif defined(__LITTLE_ENDIAN)
773 u8 tx_flags; 670 u8 tx_flags;
774#define FCOE_TASK_CTX_ENTRY_TXWR_RXRD_TX_STATE (0xF<<0) 671#define FCOE_TCE_TX_WR_RX_RD_CONST_TX_VALID (0x1<<0)
775#define FCOE_TASK_CTX_ENTRY_TXWR_RXRD_TX_STATE_SHIFT 0 672#define FCOE_TCE_TX_WR_RX_RD_CONST_TX_VALID_SHIFT 0
776#define FCOE_TASK_CTX_ENTRY_TXWR_RXRD_RSRV4 (0xF<<4) 673#define FCOE_TCE_TX_WR_RX_RD_CONST_TX_STATE (0xF<<1)
777#define FCOE_TASK_CTX_ENTRY_TXWR_RXRD_RSRV4_SHIFT 4 674#define FCOE_TCE_TX_WR_RX_RD_CONST_TX_STATE_SHIFT 1
778 u8 init_flags; 675#define FCOE_TCE_TX_WR_RX_RD_CONST_RSRV1 (0x1<<5)
779#define FCOE_TASK_CTX_ENTRY_TXWR_RXRD_TASK_TYPE (0x7<<0) 676#define FCOE_TCE_TX_WR_RX_RD_CONST_RSRV1_SHIFT 5
780#define FCOE_TASK_CTX_ENTRY_TXWR_RXRD_TASK_TYPE_SHIFT 0 677#define FCOE_TCE_TX_WR_RX_RD_CONST_TX_SEQ_INIT (0x1<<6)
781#define FCOE_TASK_CTX_ENTRY_TXWR_RXRD_DEV_TYPE (0x1<<3) 678#define FCOE_TCE_TX_WR_RX_RD_CONST_TX_SEQ_INIT_SHIFT 6
782#define FCOE_TASK_CTX_ENTRY_TXWR_RXRD_DEV_TYPE_SHIFT 3 679#define FCOE_TCE_TX_WR_RX_RD_CONST_RSRV2 (0x1<<7)
783#define FCOE_TASK_CTX_ENTRY_TXWR_RXRD_CLASS_TYPE (0x1<<4) 680#define FCOE_TCE_TX_WR_RX_RD_CONST_RSRV2_SHIFT 7
784#define FCOE_TASK_CTX_ENTRY_TXWR_RXRD_CLASS_TYPE_SHIFT 4 681 __le16 rsrv3;
785#define FCOE_TASK_CTX_ENTRY_TXWR_RXRD_SINGLE_SGE (0x1<<5) 682 __le32 verify_tx_seq;
786#define FCOE_TASK_CTX_ENTRY_TXWR_RXRD_SINGLE_SGE_SHIFT 5
787#define FCOE_TASK_CTX_ENTRY_TXWR_RXRD_RSRV5 (0x3<<6)
788#define FCOE_TASK_CTX_ENTRY_TXWR_RXRD_RSRV5_SHIFT 6
789 u16 verify_tx_seq;
790#endif
791}; 683};
792 684
793/* 685/*
794 * Common section. Both TX and RX processing might write and read from it in 686 * tce_tx_wr_rx_rd $$KEEP_ENDIANNESS$$
795 * different flows
796 */ 687 */
797struct fcoe_task_ctx_entry_tx_rx_cmn { 688struct fcoe_tce_tx_wr_rx_rd {
798 u32 data_2_trns; 689 union fcoe_tx_wr_rx_rd_union_ctx union_ctx;
799 union fcoe_general_task_ctx general; 690 struct fcoe_tce_tx_wr_rx_rd_const const_ctx;
800#if defined(__BIG_ENDIAN)
801 u16 tx_low_seq_cnt;
802 struct fcoe_s_stat_ctx tx_s_stat;
803 u8 tx_seq_id;
804#elif defined(__LITTLE_ENDIAN)
805 u8 tx_seq_id;
806 struct fcoe_s_stat_ctx tx_s_stat;
807 u16 tx_low_seq_cnt;
808#endif
809 u32 common_flags;
810#define FCOE_TASK_CTX_ENTRY_TX_RX_CMN_CID (0xFFFFFF<<0)
811#define FCOE_TASK_CTX_ENTRY_TX_RX_CMN_CID_SHIFT 0
812#define FCOE_TASK_CTX_ENTRY_TX_RX_CMN_VALID (0x1<<24)
813#define FCOE_TASK_CTX_ENTRY_TX_RX_CMN_VALID_SHIFT 24
814#define FCOE_TASK_CTX_ENTRY_TX_RX_CMN_SEQ_INIT (0x1<<25)
815#define FCOE_TASK_CTX_ENTRY_TX_RX_CMN_SEQ_INIT_SHIFT 25
816#define FCOE_TASK_CTX_ENTRY_TX_RX_CMN_PEND_XFER (0x1<<26)
817#define FCOE_TASK_CTX_ENTRY_TX_RX_CMN_PEND_XFER_SHIFT 26
818#define FCOE_TASK_CTX_ENTRY_TX_RX_CMN_PEND_CONF (0x1<<27)
819#define FCOE_TASK_CTX_ENTRY_TX_RX_CMN_PEND_CONF_SHIFT 27
820#define FCOE_TASK_CTX_ENTRY_TX_RX_CMN_EXP_FIRST_FRAME (0x1<<28)
821#define FCOE_TASK_CTX_ENTRY_TX_RX_CMN_EXP_FIRST_FRAME_SHIFT 28
822#define FCOE_TASK_CTX_ENTRY_TX_RX_CMN_RSRV (0x7<<29)
823#define FCOE_TASK_CTX_ENTRY_TX_RX_CMN_RSRV_SHIFT 29
824};
825
826struct fcoe_task_ctx_entry_rxwr_txrd {
827#if defined(__BIG_ENDIAN)
828 u16 rx_id;
829 u16 rx_flags;
830#define FCOE_TASK_CTX_ENTRY_RXWR_TXRD_RX_STATE (0xF<<0)
831#define FCOE_TASK_CTX_ENTRY_RXWR_TXRD_RX_STATE_SHIFT 0
832#define FCOE_TASK_CTX_ENTRY_RXWR_TXRD_NUM_RQ_WQE (0x7<<4)
833#define FCOE_TASK_CTX_ENTRY_RXWR_TXRD_NUM_RQ_WQE_SHIFT 4
834#define FCOE_TASK_CTX_ENTRY_RXWR_TXRD_CONF_REQ (0x1<<7)
835#define FCOE_TASK_CTX_ENTRY_RXWR_TXRD_CONF_REQ_SHIFT 7
836#define FCOE_TASK_CTX_ENTRY_RXWR_TXRD_MISS_FRAME (0x1<<8)
837#define FCOE_TASK_CTX_ENTRY_RXWR_TXRD_MISS_FRAME_SHIFT 8
838#define FCOE_TASK_CTX_ENTRY_RXWR_TXRD_RESERVED0 (0x7F<<9)
839#define FCOE_TASK_CTX_ENTRY_RXWR_TXRD_RESERVED0_SHIFT 9
840#elif defined(__LITTLE_ENDIAN)
841 u16 rx_flags;
842#define FCOE_TASK_CTX_ENTRY_RXWR_TXRD_RX_STATE (0xF<<0)
843#define FCOE_TASK_CTX_ENTRY_RXWR_TXRD_RX_STATE_SHIFT 0
844#define FCOE_TASK_CTX_ENTRY_RXWR_TXRD_NUM_RQ_WQE (0x7<<4)
845#define FCOE_TASK_CTX_ENTRY_RXWR_TXRD_NUM_RQ_WQE_SHIFT 4
846#define FCOE_TASK_CTX_ENTRY_RXWR_TXRD_CONF_REQ (0x1<<7)
847#define FCOE_TASK_CTX_ENTRY_RXWR_TXRD_CONF_REQ_SHIFT 7
848#define FCOE_TASK_CTX_ENTRY_RXWR_TXRD_MISS_FRAME (0x1<<8)
849#define FCOE_TASK_CTX_ENTRY_RXWR_TXRD_MISS_FRAME_SHIFT 8
850#define FCOE_TASK_CTX_ENTRY_RXWR_TXRD_RESERVED0 (0x7F<<9)
851#define FCOE_TASK_CTX_ENTRY_RXWR_TXRD_RESERVED0_SHIFT 9
852 u16 rx_id;
853#endif
854}; 691};
855 692
856struct fcoe_task_ctx_entry_rx_only { 693/*
857 struct fcoe_seq_ctx seq_ctx; 694 * tce_rx_wr_tx_rd_const $$KEEP_ENDIANNESS$$
858 struct fcoe_seq_ctx ooo_seq_ctx; 695 */
859 u32 rsrv3; 696struct fcoe_tce_rx_wr_tx_rd_const {
860 union fcoe_sgl_ctx sgl_ctx; 697 __le32 data_2_trns;
698 __le32 init_flags;
699#define FCOE_TCE_RX_WR_TX_RD_CONST_CID (0xFFFFFF<<0)
700#define FCOE_TCE_RX_WR_TX_RD_CONST_CID_SHIFT 0
701#define FCOE_TCE_RX_WR_TX_RD_CONST_RSRV0 (0xFF<<24)
702#define FCOE_TCE_RX_WR_TX_RD_CONST_RSRV0_SHIFT 24
703};
704
705/*
706 * tce_rx_wr_tx_rd_var $$KEEP_ENDIANNESS$$
707 */
708struct fcoe_tce_rx_wr_tx_rd_var {
709 __le16 rx_flags;
710#define FCOE_TCE_RX_WR_TX_RD_VAR_RSRV1 (0xF<<0)
711#define FCOE_TCE_RX_WR_TX_RD_VAR_RSRV1_SHIFT 0
712#define FCOE_TCE_RX_WR_TX_RD_VAR_NUM_RQ_WQE (0x7<<4)
713#define FCOE_TCE_RX_WR_TX_RD_VAR_NUM_RQ_WQE_SHIFT 4
714#define FCOE_TCE_RX_WR_TX_RD_VAR_CONF_REQ (0x1<<7)
715#define FCOE_TCE_RX_WR_TX_RD_VAR_CONF_REQ_SHIFT 7
716#define FCOE_TCE_RX_WR_TX_RD_VAR_RX_STATE (0xF<<8)
717#define FCOE_TCE_RX_WR_TX_RD_VAR_RX_STATE_SHIFT 8
718#define FCOE_TCE_RX_WR_TX_RD_VAR_EXP_FIRST_FRAME (0x1<<12)
719#define FCOE_TCE_RX_WR_TX_RD_VAR_EXP_FIRST_FRAME_SHIFT 12
720#define FCOE_TCE_RX_WR_TX_RD_VAR_RX_SEQ_INIT (0x1<<13)
721#define FCOE_TCE_RX_WR_TX_RD_VAR_RX_SEQ_INIT_SHIFT 13
722#define FCOE_TCE_RX_WR_TX_RD_VAR_RSRV2 (0x1<<14)
723#define FCOE_TCE_RX_WR_TX_RD_VAR_RSRV2_SHIFT 14
724#define FCOE_TCE_RX_WR_TX_RD_VAR_RX_VALID (0x1<<15)
725#define FCOE_TCE_RX_WR_TX_RD_VAR_RX_VALID_SHIFT 15
726 __le16 rx_id;
727 struct fcoe_fcp_xfr_rdy_payload fcp_xfr_rdy;
728};
729
730/*
731 * tce_rx_wr_tx_rd $$KEEP_ENDIANNESS$$
732 */
733struct fcoe_tce_rx_wr_tx_rd {
734 struct fcoe_tce_rx_wr_tx_rd_const const_ctx;
735 struct fcoe_tce_rx_wr_tx_rd_var var_ctx;
736};
737
738/*
739 * tce_rx_only $$KEEP_ENDIANNESS$$
740 */
741struct fcoe_tce_rx_only {
742 struct fcoe_rx_seq_ctx rx_seq_ctx;
743 union fcoe_rx_wr_union_ctx union_ctx;
861}; 744};
862 745
746/*
747 * task_ctx_entry $$KEEP_ENDIANNESS$$
748 */
863struct fcoe_task_ctx_entry { 749struct fcoe_task_ctx_entry {
864 struct fcoe_task_ctx_entry_tx_only tx_wr_only; 750 struct fcoe_tce_tx_only txwr_only;
865 struct fcoe_task_ctx_entry_txwr_rxrd tx_wr_rx_rd; 751 struct fcoe_tce_tx_wr_rx_rd txwr_rxrd;
866 struct fcoe_task_ctx_entry_tx_rx_cmn cmn; 752 struct fcoe_tce_rx_wr_tx_rd rxwr_txrd;
867 struct fcoe_task_ctx_entry_rxwr_txrd rx_wr_tx_rd; 753 struct fcoe_tce_rx_only rxwr_only;
868 struct fcoe_task_ctx_entry_rx_only rx_wr_only;
869 u32 reserved[4];
870}; 754};
871 755
872 756
757
758
759
760
761
762
763
764
873/* 765/*
874 * FCoE XFRQ element 766 * FCoE XFRQ element $$KEEP_ENDIANNESS$$
875 */ 767 */
876struct fcoe_xfrqe { 768struct fcoe_xfrqe {
877 u16 wqe; 769 __le16 wqe;
878#define FCOE_XFRQE_TASK_ID (0x7FFF<<0) 770#define FCOE_XFRQE_TASK_ID (0x7FFF<<0)
879#define FCOE_XFRQE_TASK_ID_SHIFT 0 771#define FCOE_XFRQE_TASK_ID_SHIFT 0
880#define FCOE_XFRQE_TOGGLE_BIT (0x1<<15) 772#define FCOE_XFRQE_TOGGLE_BIT (0x1<<15)
@@ -883,22 +775,31 @@ struct fcoe_xfrqe {
883 775
884 776
885/* 777/*
886 * FCoE CONFQ element 778 * fcoe rx doorbell message sent to the chip $$KEEP_ENDIANNESS$$
779 */
780struct b577xx_fcoe_rx_doorbell {
781 struct b577xx_doorbell_hdr hdr;
782 u8 params;
783#define B577XX_FCOE_RX_DOORBELL_NEGATIVE_ARM (0x1F<<0)
784#define B577XX_FCOE_RX_DOORBELL_NEGATIVE_ARM_SHIFT 0
785#define B577XX_FCOE_RX_DOORBELL_OPCODE (0x7<<5)
786#define B577XX_FCOE_RX_DOORBELL_OPCODE_SHIFT 5
787 __le16 doorbell_cq_cons;
788};
789
790
791/*
792 * FCoE CONFQ element $$KEEP_ENDIANNESS$$
887 */ 793 */
888struct fcoe_confqe { 794struct fcoe_confqe {
889#if defined(__BIG_ENDIAN) 795 __le16 ox_id;
890 u16 rx_id; 796 __le16 rx_id;
891 u16 ox_id; 797 __le32 param;
892#elif defined(__LITTLE_ENDIAN)
893 u16 ox_id;
894 u16 rx_id;
895#endif
896 u32 param;
897}; 798};
898 799
899 800
900/* 801/*
901 * FCoE connection data base 802 * FCoE conection data base
902 */ 803 */
903struct fcoe_conn_db { 804struct fcoe_conn_db {
904#if defined(__BIG_ENDIAN) 805#if defined(__BIG_ENDIAN)
@@ -914,10 +815,10 @@ struct fcoe_conn_db {
914 815
915 816
916/* 817/*
917 * FCoE CQ element 818 * FCoE CQ element $$KEEP_ENDIANNESS$$
918 */ 819 */
919struct fcoe_cqe { 820struct fcoe_cqe {
920 u16 wqe; 821 __le16 wqe;
921#define FCOE_CQE_CQE_INFO (0x3FFF<<0) 822#define FCOE_CQE_CQE_INFO (0x3FFF<<0)
922#define FCOE_CQE_CQE_INFO_SHIFT 0 823#define FCOE_CQE_CQE_INFO_SHIFT 0
923#define FCOE_CQE_CQE_TYPE (0x1<<14) 824#define FCOE_CQE_CQE_TYPE (0x1<<14)
@@ -928,61 +829,46 @@ struct fcoe_cqe {
928 829
929 830
930/* 831/*
931 * FCoE error/warning resporting entry 832 * FCoE error/warning reporting entry $$KEEP_ENDIANNESS$$
833 */
834struct fcoe_partial_err_report_entry {
835 __le32 err_warn_bitmap_lo;
836 __le32 err_warn_bitmap_hi;
837 __le32 tx_buf_off;
838 __le32 rx_buf_off;
839};
840
841/*
842 * FCoE error/warning reporting entry $$KEEP_ENDIANNESS$$
932 */ 843 */
933struct fcoe_err_report_entry { 844struct fcoe_err_report_entry {
934 u32 err_warn_bitmap_lo; 845 struct fcoe_partial_err_report_entry data;
935 u32 err_warn_bitmap_hi;
936 u32 tx_buf_off;
937 u32 rx_buf_off;
938 struct fcoe_fc_hdr fc_hdr; 846 struct fcoe_fc_hdr fc_hdr;
939}; 847};
940 848
941 849
942/* 850/*
943 * FCoE hash table entry (32 bytes) 851 * FCoE hash table entry (32 bytes) $$KEEP_ENDIANNESS$$
944 */ 852 */
945struct fcoe_hash_table_entry { 853struct fcoe_hash_table_entry {
946#if defined(__BIG_ENDIAN)
947 u8 d_id_0;
948 u8 s_id_2;
949 u8 s_id_1;
950 u8 s_id_0;
951#elif defined(__LITTLE_ENDIAN)
952 u8 s_id_0; 854 u8 s_id_0;
953 u8 s_id_1; 855 u8 s_id_1;
954 u8 s_id_2; 856 u8 s_id_2;
955 u8 d_id_0; 857 u8 d_id_0;
956#endif
957#if defined(__BIG_ENDIAN)
958 u16 dst_mac_addr_hi;
959 u8 d_id_2;
960 u8 d_id_1;
961#elif defined(__LITTLE_ENDIAN)
962 u8 d_id_1; 858 u8 d_id_1;
963 u8 d_id_2; 859 u8 d_id_2;
964 u16 dst_mac_addr_hi; 860 __le16 dst_mac_addr_hi;
965#endif 861 __le16 dst_mac_addr_mid;
966 u32 dst_mac_addr_lo; 862 __le16 dst_mac_addr_lo;
967#if defined(__BIG_ENDIAN) 863 __le16 src_mac_addr_hi;
968 u16 vlan_id; 864 __le16 vlan_id;
969 u16 src_mac_addr_hi; 865 __le16 src_mac_addr_lo;
970#elif defined(__LITTLE_ENDIAN) 866 __le16 src_mac_addr_mid;
971 u16 src_mac_addr_hi;
972 u16 vlan_id;
973#endif
974 u32 src_mac_addr_lo;
975#if defined(__BIG_ENDIAN)
976 u16 reserved1;
977 u8 reserved0;
978 u8 vlan_flag;
979#elif defined(__LITTLE_ENDIAN)
980 u8 vlan_flag; 867 u8 vlan_flag;
981 u8 reserved0; 868 u8 reserved0;
982 u16 reserved1; 869 __le16 reserved1;
983#endif 870 __le32 reserved2;
984 u32 reserved2; 871 __le32 field_id;
985 u32 field_id;
986#define FCOE_HASH_TABLE_ENTRY_CID (0xFFFFFF<<0) 872#define FCOE_HASH_TABLE_ENTRY_CID (0xFFFFFF<<0)
987#define FCOE_HASH_TABLE_ENTRY_CID_SHIFT 0 873#define FCOE_HASH_TABLE_ENTRY_CID_SHIFT 0
988#define FCOE_HASH_TABLE_ENTRY_RESERVED3 (0x7F<<24) 874#define FCOE_HASH_TABLE_ENTRY_RESERVED3 (0x7F<<24)
@@ -991,11 +877,27 @@ struct fcoe_hash_table_entry {
991#define FCOE_HASH_TABLE_ENTRY_VALID_SHIFT 31 877#define FCOE_HASH_TABLE_ENTRY_VALID_SHIFT 31
992}; 878};
993 879
880
994/* 881/*
995 * FCoE pending work request CQE 882 * FCoE LCQ element $$KEEP_ENDIANNESS$$
883 */
884struct fcoe_lcqe {
885 __le32 wqe;
886#define FCOE_LCQE_TASK_ID (0xFFFF<<0)
887#define FCOE_LCQE_TASK_ID_SHIFT 0
888#define FCOE_LCQE_LCQE_TYPE (0xFF<<16)
889#define FCOE_LCQE_LCQE_TYPE_SHIFT 16
890#define FCOE_LCQE_RESERVED (0xFF<<24)
891#define FCOE_LCQE_RESERVED_SHIFT 24
892};
893
894
895
896/*
897 * FCoE pending work request CQE $$KEEP_ENDIANNESS$$
996 */ 898 */
997struct fcoe_pend_wq_cqe { 899struct fcoe_pend_wq_cqe {
998 u16 wqe; 900 __le16 wqe;
999#define FCOE_PEND_WQ_CQE_TASK_ID (0x3FFF<<0) 901#define FCOE_PEND_WQ_CQE_TASK_ID (0x3FFF<<0)
1000#define FCOE_PEND_WQ_CQE_TASK_ID_SHIFT 0 902#define FCOE_PEND_WQ_CQE_TASK_ID_SHIFT 0
1001#define FCOE_PEND_WQ_CQE_CQE_TYPE (0x1<<14) 903#define FCOE_PEND_WQ_CQE_CQE_TYPE (0x1<<14)
@@ -1006,53 +908,61 @@ struct fcoe_pend_wq_cqe {
1006 908
1007 909
1008/* 910/*
1009 * FCoE RX statistics parameters section#0 911 * FCoE RX statistics parameters section#0 $$KEEP_ENDIANNESS$$
1010 */ 912 */
1011struct fcoe_rx_stat_params_section0 { 913struct fcoe_rx_stat_params_section0 {
1012 u32 fcoe_ver_cnt; 914 __le32 fcoe_rx_pkt_cnt;
1013 u32 fcoe_rx_pkt_cnt; 915 __le32 fcoe_rx_byte_cnt;
1014 u32 fcoe_rx_byte_cnt;
1015 u32 fcoe_rx_drop_pkt_cnt;
1016}; 916};
1017 917
1018 918
1019/* 919/*
1020 * FCoE RX statistics parameters section#1 920 * FCoE RX statistics parameters section#1 $$KEEP_ENDIANNESS$$
1021 */ 921 */
1022struct fcoe_rx_stat_params_section1 { 922struct fcoe_rx_stat_params_section1 {
1023 u32 fc_crc_cnt; 923 __le32 fcoe_ver_cnt;
1024 u32 eofa_del_cnt; 924 __le32 fcoe_rx_drop_pkt_cnt;
1025 u32 miss_frame_cnt; 925};
1026 u32 seq_timeout_cnt; 926
1027 u32 drop_seq_cnt; 927
1028 u32 fcoe_rx_drop_pkt_cnt; 928/*
1029 u32 fcp_rx_pkt_cnt; 929 * FCoE RX statistics parameters section#2 $$KEEP_ENDIANNESS$$
1030 u32 reserved0; 930 */
931struct fcoe_rx_stat_params_section2 {
932 __le32 fc_crc_cnt;
933 __le32 eofa_del_cnt;
934 __le32 miss_frame_cnt;
935 __le32 seq_timeout_cnt;
936 __le32 drop_seq_cnt;
937 __le32 fcoe_rx_drop_pkt_cnt;
938 __le32 fcp_rx_pkt_cnt;
939 __le32 reserved0;
1031}; 940};
1032 941
1033 942
1034/* 943/*
1035 * FCoE TX statistics parameters 944 * FCoE TX statistics parameters $$KEEP_ENDIANNESS$$
1036 */ 945 */
1037struct fcoe_tx_stat_params { 946struct fcoe_tx_stat_params {
1038 u32 fcoe_tx_pkt_cnt; 947 __le32 fcoe_tx_pkt_cnt;
1039 u32 fcoe_tx_byte_cnt; 948 __le32 fcoe_tx_byte_cnt;
1040 u32 fcp_tx_pkt_cnt; 949 __le32 fcp_tx_pkt_cnt;
1041 u32 reserved0; 950 __le32 reserved0;
1042}; 951};
1043 952
1044/* 953/*
1045 * FCoE statistics parameters 954 * FCoE statistics parameters $$KEEP_ENDIANNESS$$
1046 */ 955 */
1047struct fcoe_statistics_params { 956struct fcoe_statistics_params {
1048 struct fcoe_tx_stat_params tx_stat; 957 struct fcoe_tx_stat_params tx_stat;
1049 struct fcoe_rx_stat_params_section0 rx_stat0; 958 struct fcoe_rx_stat_params_section0 rx_stat0;
1050 struct fcoe_rx_stat_params_section1 rx_stat1; 959 struct fcoe_rx_stat_params_section1 rx_stat1;
960 struct fcoe_rx_stat_params_section2 rx_stat2;
1051}; 961};
1052 962
1053 963
1054/* 964/*
1055 * FCoE t2 hash table entry (64 bytes) 965 * FCoE t2 hash table entry (64 bytes) $$KEEP_ENDIANNESS$$
1056 */ 966 */
1057struct fcoe_t2_hash_table_entry { 967struct fcoe_t2_hash_table_entry {
1058 struct fcoe_hash_table_entry data; 968 struct fcoe_hash_table_entry data;
@@ -1060,11 +970,13 @@ struct fcoe_t2_hash_table_entry {
1060 struct regpair reserved0[3]; 970 struct regpair reserved0[3];
1061}; 971};
1062 972
973
974
1063/* 975/*
1064 * FCoE unsolicited CQE 976 * FCoE unsolicited CQE $$KEEP_ENDIANNESS$$
1065 */ 977 */
1066struct fcoe_unsolicited_cqe { 978struct fcoe_unsolicited_cqe {
1067 u16 wqe; 979 __le16 wqe;
1068#define FCOE_UNSOLICITED_CQE_SUBTYPE (0x3<<0) 980#define FCOE_UNSOLICITED_CQE_SUBTYPE (0x3<<0)
1069#define FCOE_UNSOLICITED_CQE_SUBTYPE_SHIFT 0 981#define FCOE_UNSOLICITED_CQE_SUBTYPE_SHIFT 0
1070#define FCOE_UNSOLICITED_CQE_PKT_LEN (0xFFF<<2) 982#define FCOE_UNSOLICITED_CQE_PKT_LEN (0xFFF<<2)
@@ -1075,6 +987,4 @@ struct fcoe_unsolicited_cqe {
1075#define FCOE_UNSOLICITED_CQE_TOGGLE_BIT_SHIFT 15 987#define FCOE_UNSOLICITED_CQE_TOGGLE_BIT_SHIFT 15
1076}; 988};
1077 989
1078
1079
1080#endif /* __57XX_FCOE_HSI_LINUX_LE__ */ 990#endif /* __57XX_FCOE_HSI_LINUX_LE__ */
diff --git a/drivers/scsi/bnx2fc/bnx2fc.h b/drivers/scsi/bnx2fc/bnx2fc.h
index 0a404bfb44fe..907672e86063 100644
--- a/drivers/scsi/bnx2fc/bnx2fc.h
+++ b/drivers/scsi/bnx2fc/bnx2fc.h
@@ -62,7 +62,7 @@
62#include "bnx2fc_constants.h" 62#include "bnx2fc_constants.h"
63 63
64#define BNX2FC_NAME "bnx2fc" 64#define BNX2FC_NAME "bnx2fc"
65#define BNX2FC_VERSION "1.0.1" 65#define BNX2FC_VERSION "1.0.3"
66 66
67#define PFX "bnx2fc: " 67#define PFX "bnx2fc: "
68 68
@@ -262,9 +262,14 @@ struct bnx2fc_rport {
262#define BNX2FC_FLAG_UPLD_REQ_COMPL 0x8 262#define BNX2FC_FLAG_UPLD_REQ_COMPL 0x8
263#define BNX2FC_FLAG_EXPL_LOGO 0x9 263#define BNX2FC_FLAG_EXPL_LOGO 0x9
264 264
265 u8 src_addr[ETH_ALEN];
265 u32 max_sqes; 266 u32 max_sqes;
266 u32 max_rqes; 267 u32 max_rqes;
267 u32 max_cqes; 268 u32 max_cqes;
269 atomic_t free_sqes;
270
271 struct b577xx_doorbell_set_prod sq_db;
272 struct b577xx_fcoe_rx_doorbell rx_db;
268 273
269 struct fcoe_sqe *sq; 274 struct fcoe_sqe *sq;
270 dma_addr_t sq_dma; 275 dma_addr_t sq_dma;
@@ -274,7 +279,7 @@ struct bnx2fc_rport {
274 279
275 struct fcoe_cqe *cq; 280 struct fcoe_cqe *cq;
276 dma_addr_t cq_dma; 281 dma_addr_t cq_dma;
277 u32 cq_cons_idx; 282 u16 cq_cons_idx;
278 u8 cq_curr_toggle_bit; 283 u8 cq_curr_toggle_bit;
279 u32 cq_mem_size; 284 u32 cq_mem_size;
280 285
@@ -505,6 +510,7 @@ struct fc_seq *bnx2fc_elsct_send(struct fc_lport *lport, u32 did,
505 struct fc_frame *, 510 struct fc_frame *,
506 void *), 511 void *),
507 void *arg, u32 timeout); 512 void *arg, u32 timeout);
513void bnx2fc_arm_cq(struct bnx2fc_rport *tgt);
508int bnx2fc_process_new_cqes(struct bnx2fc_rport *tgt); 514int bnx2fc_process_new_cqes(struct bnx2fc_rport *tgt);
509void bnx2fc_process_cq_compl(struct bnx2fc_rport *tgt, u16 wqe); 515void bnx2fc_process_cq_compl(struct bnx2fc_rport *tgt, u16 wqe);
510struct bnx2fc_rport *bnx2fc_tgt_lookup(struct fcoe_port *port, 516struct bnx2fc_rport *bnx2fc_tgt_lookup(struct fcoe_port *port,
diff --git a/drivers/scsi/bnx2fc/bnx2fc_constants.h b/drivers/scsi/bnx2fc/bnx2fc_constants.h
index fe7769173c43..399cda047a77 100644
--- a/drivers/scsi/bnx2fc/bnx2fc_constants.h
+++ b/drivers/scsi/bnx2fc/bnx2fc_constants.h
@@ -5,6 +5,12 @@
5 * This file defines HSI constants for the FCoE flows 5 * This file defines HSI constants for the FCoE flows
6 */ 6 */
7 7
8/* Current FCoE HSI version number composed of two fields (16 bit) */
9/* Implies on a change broken previous HSI */
10#define FCOE_HSI_MAJOR_VERSION (1)
11/* Implies on a change which does not broken previous HSI */
12#define FCOE_HSI_MINOR_VERSION (1)
13
8/* KWQ/KCQ FCoE layer code */ 14/* KWQ/KCQ FCoE layer code */
9#define FCOE_KWQE_LAYER_CODE (7) 15#define FCOE_KWQE_LAYER_CODE (7)
10 16
@@ -40,21 +46,62 @@
40#define FCOE_KCQE_COMPLETION_STATUS_CTX_ALLOC_FAILURE (0x3) 46#define FCOE_KCQE_COMPLETION_STATUS_CTX_ALLOC_FAILURE (0x3)
41#define FCOE_KCQE_COMPLETION_STATUS_CTX_FREE_FAILURE (0x4) 47#define FCOE_KCQE_COMPLETION_STATUS_CTX_FREE_FAILURE (0x4)
42#define FCOE_KCQE_COMPLETION_STATUS_NIC_ERROR (0x5) 48#define FCOE_KCQE_COMPLETION_STATUS_NIC_ERROR (0x5)
49#define FCOE_KCQE_COMPLETION_STATUS_WRONG_HSI_VERSION (0x6)
50
51/* CQE type */
52#define FCOE_PENDING_CQE_TYPE 0
53#define FCOE_UNSOLIC_CQE_TYPE 1
43 54
44/* Unsolicited CQE type */ 55/* Unsolicited CQE type */
45#define FCOE_UNSOLICITED_FRAME_CQE_TYPE 0 56#define FCOE_UNSOLICITED_FRAME_CQE_TYPE 0
46#define FCOE_ERROR_DETECTION_CQE_TYPE 1 57#define FCOE_ERROR_DETECTION_CQE_TYPE 1
47#define FCOE_WARNING_DETECTION_CQE_TYPE 2 58#define FCOE_WARNING_DETECTION_CQE_TYPE 2
48 59
60/* E_D_TOV timer resolution in ms */
61#define FCOE_E_D_TOV_TIMER_RESOLUTION_MS (20)
62
63/* E_D_TOV timer resolution for SDM (4 micro) */
64#define FCOE_E_D_TOV_SDM_TIMER_RESOLUTION \
65 (FCOE_E_D_TOV_TIMER_RESOLUTION_MS * 1000 / 4)
66
67/* REC timer resolution in ms */
68#define FCOE_REC_TIMER_RESOLUTION_MS (20)
69
70/* REC timer resolution for SDM (4 micro) */
71#define FCOE_REC_SDM_TIMER_RESOLUTION (FCOE_REC_TIMER_RESOLUTION_MS * 1000 / 4)
72
73/* E_D_TOV timer default wraparound value (2 sec) in 20 ms resolution */
74#define FCOE_E_D_TOV_DEFAULT_WRAPAROUND_VAL \
75 (2000 / FCOE_E_D_TOV_TIMER_RESOLUTION_MS)
76
77/* REC_TOV timer default wraparound value (3 sec) in 20 ms resolution */
78#define FCOE_REC_TOV_DEFAULT_WRAPAROUND_VAL \
79 (3000 / FCOE_REC_TIMER_RESOLUTION_MS)
80
81#define FCOE_NUM_OF_TIMER_TASKS (8 * 1024)
82
83#define FCOE_NUM_OF_CACHED_TASKS_TIMER (8)
84
49/* Task context constants */ 85/* Task context constants */
86/******** Remove FCP_CMD write tce sleep ***********************/
87/* In case timer services are required then shall be updated by Xstorm after
88 * start processing the task. In case no timer facilities are required then the
89 * driver would initialize the state to this value
90 *
91#define FCOE_TASK_TX_STATE_NORMAL 0
92 * After driver has initialize the task in case timer services required *
93#define FCOE_TASK_TX_STATE_INIT 1
94******** Remove FCP_CMD write tce sleep ***********************/
50/* After driver has initialize the task in case timer services required */ 95/* After driver has initialize the task in case timer services required */
51#define FCOE_TASK_TX_STATE_INIT 0 96#define FCOE_TASK_TX_STATE_INIT 0
52/* In case timer services are required then shall be updated by Xstorm after 97/* In case timer services are required then shall be updated by Xstorm after
53 * start processing the task. In case no timer facilities are required then the 98 * start processing the task. In case no timer facilities are required then the
54 * driver would initialize the state to this value */ 99 * driver would initialize the state to this value
100 */
55#define FCOE_TASK_TX_STATE_NORMAL 1 101#define FCOE_TASK_TX_STATE_NORMAL 1
56/* Task is under abort procedure. Updated in order to stop processing of 102/* Task is under abort procedure. Updated in order to stop processing of
57 * pending WQEs on this task */ 103 * pending WQEs on this task
104 */
58#define FCOE_TASK_TX_STATE_ABORT 2 105#define FCOE_TASK_TX_STATE_ABORT 2
59/* For E_D_T_TOV timer expiration in Xstorm (Class 2 only) */ 106/* For E_D_T_TOV timer expiration in Xstorm (Class 2 only) */
60#define FCOE_TASK_TX_STATE_ERROR 3 107#define FCOE_TASK_TX_STATE_ERROR 3
@@ -66,17 +113,8 @@
66#define FCOE_TASK_TX_STATE_EXCHANGE_CLEANUP 6 113#define FCOE_TASK_TX_STATE_EXCHANGE_CLEANUP 6
67/* For sequence cleanup request task */ 114/* For sequence cleanup request task */
68#define FCOE_TASK_TX_STATE_SEQUENCE_CLEANUP 7 115#define FCOE_TASK_TX_STATE_SEQUENCE_CLEANUP 7
69/* Mark task as aborted and indicate that ABTS was not transmitted */
70#define FCOE_TASK_TX_STATE_BEFORE_ABTS_TX 8
71/* Mark task as aborted and indicate that ABTS was transmitted */
72#define FCOE_TASK_TX_STATE_AFTER_ABTS_TX 9
73/* For completion the ABTS task. */ 116/* For completion the ABTS task. */
74#define FCOE_TASK_TX_STATE_ABTS_TX_COMPLETED 10 117#define FCOE_TASK_TX_STATE_ABTS_TX 8
75/* Mark task as aborted and indicate that Exchange cleanup was not transmitted
76 */
77#define FCOE_TASK_TX_STATE_BEFORE_EXCHANGE_CLEANUP_TX 11
78/* Mark task as aborted and indicate that Exchange cleanup was transmitted */
79#define FCOE_TASK_TX_STATE_AFTER_EXCHANGE_CLEANUP_TX 12
80 118
81#define FCOE_TASK_RX_STATE_NORMAL 0 119#define FCOE_TASK_RX_STATE_NORMAL 0
82#define FCOE_TASK_RX_STATE_COMPLETED 1 120#define FCOE_TASK_RX_STATE_COMPLETED 1
@@ -86,25 +124,25 @@
86#define FCOE_TASK_RX_STATE_WARNING 3 124#define FCOE_TASK_RX_STATE_WARNING 3
87/* For E_D_T_TOV timer expiration in Ustorm */ 125/* For E_D_T_TOV timer expiration in Ustorm */
88#define FCOE_TASK_RX_STATE_ERROR 4 126#define FCOE_TASK_RX_STATE_ERROR 4
89/* ABTS ACC arrived wait for local completion to finally complete the task. */ 127/* FW only: First visit at rx-path, part of the abts round trip */
90#define FCOE_TASK_RX_STATE_ABTS_ACC_ARRIVED 5 128#define FCOE_TASK_RX_STATE_ABTS_IN_PROCESS 5
91/* local completion arrived wait for ABTS ACC to finally complete the task. */ 129/* FW only: Second visit at rx-path, after ABTS frame transmitted */
92#define FCOE_TASK_RX_STATE_ABTS_LOCAL_COMP_ARRIVED 6 130#define FCOE_TASK_RX_STATE_ABTS_TRANSMITTED 6
93/* Special completion indication in case of task was aborted. */ 131/* Special completion indication in case of task was aborted. */
94#define FCOE_TASK_RX_STATE_ABTS_COMPLETED 7 132#define FCOE_TASK_RX_STATE_ABTS_COMPLETED 7
95/* Special completion indication in case of task was cleaned. */ 133/* FW only: First visit at rx-path, part of the cleanup round trip */
96#define FCOE_TASK_RX_STATE_EXCHANGE_CLEANUP_COMPLETED 8 134#define FCOE_TASK_RX_STATE_EXCHANGE_CLEANUP_IN_PROCESS 8
97/* Special completion indication (in task requested the exchange cleanup) in 135/* FW only: Special completion indication in case of task was cleaned. */
98 * case cleaned task is in non-valid. */ 136#define FCOE_TASK_RX_STATE_EXCHANGE_CLEANUP_COMPLETED 9
99#define FCOE_TASK_RX_STATE_ABORT_CLEANUP_COMPLETED 9 137/* Not in used: Special completion indication (in task requested the exchange
138 * cleanup) in case cleaned task is in non-valid.
139 */
140#define FCOE_TASK_RX_STATE_ABORT_CLEANUP_COMPLETED 10
100/* Special completion indication (in task requested the sequence cleanup) in 141/* Special completion indication (in task requested the sequence cleanup) in
101 * case cleaned task was already returned to normal. */ 142 * case cleaned task was already returned to normal.
102#define FCOE_TASK_RX_STATE_IGNORED_SEQUENCE_CLEANUP 10 143 */
103/* Exchange cleanup arrived wait until xfer will be handled to finally 144#define FCOE_TASK_RX_STATE_IGNORED_SEQUENCE_CLEANUP 11
104 * complete the task. */ 145
105#define FCOE_TASK_RX_STATE_EXCHANGE_CLEANUP_ARRIVED 11
106/* Xfer handled, wait for exchange cleanup to finally complete the task. */
107#define FCOE_TASK_RX_STATE_EXCHANGE_CLEANUP_HANDLED_XFER 12
108 146
109#define FCOE_TASK_TYPE_WRITE 0 147#define FCOE_TASK_TYPE_WRITE 0
110#define FCOE_TASK_TYPE_READ 1 148#define FCOE_TASK_TYPE_READ 1
@@ -120,11 +158,40 @@
120#define FCOE_TASK_CLASS_TYPE_3 0 158#define FCOE_TASK_CLASS_TYPE_3 0
121#define FCOE_TASK_CLASS_TYPE_2 1 159#define FCOE_TASK_CLASS_TYPE_2 1
122 160
161/* FCoE/FC packet fields */
162#define FCOE_ETH_TYPE 0x8906
163
164/* FCoE maximum elements in hash table */
165#define FCOE_MAX_ELEMENTS_IN_HASH_TABLE_ROW 8
166
167/* FCoE half of the elements in hash table */
168#define FCOE_HALF_ELEMENTS_IN_HASH_TABLE_ROW \
169 (FCOE_MAX_ELEMENTS_IN_HASH_TABLE_ROW / 2)
170
171/* FcoE number of cached T2 entries */
172#define T_FCOE_NUMBER_OF_CACHED_T2_ENTRIES (4)
173
174/* FCoE maximum elements in hash table */
175#define FCOE_HASH_TBL_CHUNK_SIZE 16384
176
123/* Everest FCoE connection type */ 177/* Everest FCoE connection type */
124#define B577XX_FCOE_CONNECTION_TYPE 4 178#define B577XX_FCOE_CONNECTION_TYPE 4
125 179
126/* Error codes for Error Reporting in fast path flows */ 180/* FCoE number of rows (in log). This number derives
127/* XFER error codes */ 181 * from the maximum connections supported which is 2048.
182 * TBA: Need a different constant for E2
183 */
184#define FCOE_MAX_NUM_SESSIONS_LOG 11
185
186#define FC_ABTS_REPLY_MAX_PAYLOAD_LEN 12
187
188/* Error codes for Error Reporting in slow path flows */
189#define FCOE_SLOW_PATH_ERROR_CODE_TOO_MANY_FUNCS 0
190#define FCOE_SLOW_PATH_ERROR_CODE_NO_LICENSE 1
191
192/* Error codes for Error Reporting in fast path flows
193 * XFER error codes
194 */
128#define FCOE_ERROR_CODE_XFER_OOO_RO 0 195#define FCOE_ERROR_CODE_XFER_OOO_RO 0
129#define FCOE_ERROR_CODE_XFER_RO_NOT_ALIGNED 1 196#define FCOE_ERROR_CODE_XFER_RO_NOT_ALIGNED 1
130#define FCOE_ERROR_CODE_XFER_NULL_BURST_LEN 2 197#define FCOE_ERROR_CODE_XFER_NULL_BURST_LEN 2
@@ -155,17 +222,17 @@
155#define FCOE_ERROR_CODE_DATA_SOFI3_SEQ_ACTIVE_SET 23 222#define FCOE_ERROR_CODE_DATA_SOFI3_SEQ_ACTIVE_SET 23
156#define FCOE_ERROR_CODE_DATA_SOFN_SEQ_ACTIVE_RESET 24 223#define FCOE_ERROR_CODE_DATA_SOFN_SEQ_ACTIVE_RESET 24
157#define FCOE_ERROR_CODE_DATA_EOFN_END_SEQ_SET 25 224#define FCOE_ERROR_CODE_DATA_EOFN_END_SEQ_SET 25
158#define FCOE_ERROR_CODE_DATA_EOFT_END_SEQ_RESET 26 225#define FCOE_ERROR_CODE_DATA_EOFT_END_SEQ_RESET 26
159#define FCOE_ERROR_CODE_DATA_TASK_TYPE_NOT_READ 27 226#define FCOE_ERROR_CODE_DATA_TASK_TYPE_NOT_READ 27
160#define FCOE_ERROR_CODE_DATA_FCTL 28 227#define FCOE_ERROR_CODE_DATA_FCTL 28
161 228
162/* Middle path error codes */ 229/* Middle path error codes */
163#define FCOE_ERROR_CODE_MIDPATH_TYPE_NOT_ELS 29 230#define FCOE_ERROR_CODE_MIDPATH_INVALID_TYPE 29
164#define FCOE_ERROR_CODE_MIDPATH_SOFI3_SEQ_ACTIVE_SET 30 231#define FCOE_ERROR_CODE_MIDPATH_SOFI3_SEQ_ACTIVE_SET 30
165#define FCOE_ERROR_CODE_MIDPATH_SOFN_SEQ_ACTIVE_RESET 31 232#define FCOE_ERROR_CODE_MIDPATH_SOFN_SEQ_ACTIVE_RESET 31
166#define FCOE_ERROR_CODE_MIDPATH_EOFN_END_SEQ_SET 32 233#define FCOE_ERROR_CODE_MIDPATH_EOFN_END_SEQ_SET 32
167#define FCOE_ERROR_CODE_MIDPATH_EOFT_END_SEQ_RESET 33 234#define FCOE_ERROR_CODE_MIDPATH_EOFT_END_SEQ_RESET 33
168#define FCOE_ERROR_CODE_MIDPATH_ELS_REPLY_FCTL 34 235#define FCOE_ERROR_CODE_MIDPATH_REPLY_FCTL 34
169#define FCOE_ERROR_CODE_MIDPATH_INVALID_REPLY 35 236#define FCOE_ERROR_CODE_MIDPATH_INVALID_REPLY 35
170#define FCOE_ERROR_CODE_MIDPATH_ELS_REPLY_RCTL 36 237#define FCOE_ERROR_CODE_MIDPATH_ELS_REPLY_RCTL 36
171 238
@@ -173,7 +240,7 @@
173#define FCOE_ERROR_CODE_ABTS_REPLY_F_CTL 37 240#define FCOE_ERROR_CODE_ABTS_REPLY_F_CTL 37
174#define FCOE_ERROR_CODE_ABTS_REPLY_DDF_RCTL_FIELD 38 241#define FCOE_ERROR_CODE_ABTS_REPLY_DDF_RCTL_FIELD 38
175#define FCOE_ERROR_CODE_ABTS_REPLY_INVALID_BLS_RCTL 39 242#define FCOE_ERROR_CODE_ABTS_REPLY_INVALID_BLS_RCTL 39
176#define FCOE_ERROR_CODE_ABTS_REPLY_INVALID_RCTL 40 243#define FCOE_ERROR_CODE_ABTS_REPLY_INVALID_RCTL 40
177#define FCOE_ERROR_CODE_ABTS_REPLY_RCTL_GENERAL_MISMATCH 41 244#define FCOE_ERROR_CODE_ABTS_REPLY_RCTL_GENERAL_MISMATCH 41
178 245
179/* Common error codes */ 246/* Common error codes */
@@ -185,7 +252,7 @@
185#define FCOE_ERROR_CODE_COMMON_DATA_NO_MORE_SGES 47 252#define FCOE_ERROR_CODE_COMMON_DATA_NO_MORE_SGES 47
186#define FCOE_ERROR_CODE_COMMON_OPTIONAL_FC_HDR 48 253#define FCOE_ERROR_CODE_COMMON_OPTIONAL_FC_HDR 48
187#define FCOE_ERROR_CODE_COMMON_READ_TCE_OX_ID_TOO_BIG 49 254#define FCOE_ERROR_CODE_COMMON_READ_TCE_OX_ID_TOO_BIG 49
188#define FCOE_ERROR_CODE_COMMON_DATA_WAS_NOT_TRANSMITTED 50 255#define FCOE_ERROR_CODE_COMMON_DATA_WAS_NOT_TRANSMITTED 50
189 256
190/* Unsolicited Rx error codes */ 257/* Unsolicited Rx error codes */
191#define FCOE_ERROR_CODE_UNSOLICITED_TYPE_NOT_ELS 51 258#define FCOE_ERROR_CODE_UNSOLICITED_TYPE_NOT_ELS 51
diff --git a/drivers/scsi/bnx2fc/bnx2fc_els.c b/drivers/scsi/bnx2fc/bnx2fc_els.c
index 52c358427ce2..7e89143f15cf 100644
--- a/drivers/scsi/bnx2fc/bnx2fc_els.c
+++ b/drivers/scsi/bnx2fc/bnx2fc_els.c
@@ -83,7 +83,7 @@ int bnx2fc_send_rrq(struct bnx2fc_cmd *aborted_io_req)
83 rrq.rrq_cmd = ELS_RRQ; 83 rrq.rrq_cmd = ELS_RRQ;
84 hton24(rrq.rrq_s_id, sid); 84 hton24(rrq.rrq_s_id, sid);
85 rrq.rrq_ox_id = htons(aborted_io_req->xid); 85 rrq.rrq_ox_id = htons(aborted_io_req->xid);
86 rrq.rrq_rx_id = htons(aborted_io_req->task->rx_wr_tx_rd.rx_id); 86 rrq.rrq_rx_id = htons(aborted_io_req->task->rxwr_txrd.var_ctx.rx_id);
87 87
88retry_rrq: 88retry_rrq:
89 rc = bnx2fc_initiate_els(tgt, ELS_RRQ, &rrq, sizeof(rrq), 89 rc = bnx2fc_initiate_els(tgt, ELS_RRQ, &rrq, sizeof(rrq),
@@ -417,12 +417,13 @@ void bnx2fc_process_els_compl(struct bnx2fc_cmd *els_req,
417 417
418 hdr = (u64 *)fc_hdr; 418 hdr = (u64 *)fc_hdr;
419 temp_hdr = (u64 *) 419 temp_hdr = (u64 *)
420 &task->cmn.general.cmd_info.mp_fc_frame.fc_hdr; 420 &task->rxwr_only.union_ctx.comp_info.mp_rsp.fc_hdr;
421 hdr[0] = cpu_to_be64(temp_hdr[0]); 421 hdr[0] = cpu_to_be64(temp_hdr[0]);
422 hdr[1] = cpu_to_be64(temp_hdr[1]); 422 hdr[1] = cpu_to_be64(temp_hdr[1]);
423 hdr[2] = cpu_to_be64(temp_hdr[2]); 423 hdr[2] = cpu_to_be64(temp_hdr[2]);
424 424
425 mp_req->resp_len = task->rx_wr_only.sgl_ctx.mul_sges.cur_sge_off; 425 mp_req->resp_len =
426 task->rxwr_only.union_ctx.comp_info.mp_rsp.mp_payload_len;
426 427
427 /* Parse ELS response */ 428 /* Parse ELS response */
428 if ((els_req->cb_func) && (els_req->cb_arg)) { 429 if ((els_req->cb_func) && (els_req->cb_arg)) {
diff --git a/drivers/scsi/bnx2fc/bnx2fc_fcoe.c b/drivers/scsi/bnx2fc/bnx2fc_fcoe.c
index ab255fbc7f36..7a16ca1c3ecf 100644
--- a/drivers/scsi/bnx2fc/bnx2fc_fcoe.c
+++ b/drivers/scsi/bnx2fc/bnx2fc_fcoe.c
@@ -21,7 +21,7 @@ DEFINE_PER_CPU(struct bnx2fc_percpu_s, bnx2fc_percpu);
21 21
22#define DRV_MODULE_NAME "bnx2fc" 22#define DRV_MODULE_NAME "bnx2fc"
23#define DRV_MODULE_VERSION BNX2FC_VERSION 23#define DRV_MODULE_VERSION BNX2FC_VERSION
24#define DRV_MODULE_RELDATE "Mar 17, 2011" 24#define DRV_MODULE_RELDATE "Jun 10, 2011"
25 25
26 26
27static char version[] __devinitdata = 27static char version[] __devinitdata =
@@ -612,7 +612,7 @@ static struct fc_host_statistics *bnx2fc_get_host_stats(struct Scsi_Host *shost)
612 BNX2FC_HBA_DBG(lport, "FW stat req timed out\n"); 612 BNX2FC_HBA_DBG(lport, "FW stat req timed out\n");
613 return bnx2fc_stats; 613 return bnx2fc_stats;
614 } 614 }
615 bnx2fc_stats->invalid_crc_count += fw_stats->rx_stat1.fc_crc_cnt; 615 bnx2fc_stats->invalid_crc_count += fw_stats->rx_stat2.fc_crc_cnt;
616 bnx2fc_stats->tx_frames += fw_stats->tx_stat.fcoe_tx_pkt_cnt; 616 bnx2fc_stats->tx_frames += fw_stats->tx_stat.fcoe_tx_pkt_cnt;
617 bnx2fc_stats->tx_words += (fw_stats->tx_stat.fcoe_tx_byte_cnt) / 4; 617 bnx2fc_stats->tx_words += (fw_stats->tx_stat.fcoe_tx_byte_cnt) / 4;
618 bnx2fc_stats->rx_frames += fw_stats->rx_stat0.fcoe_rx_pkt_cnt; 618 bnx2fc_stats->rx_frames += fw_stats->rx_stat0.fcoe_rx_pkt_cnt;
diff --git a/drivers/scsi/bnx2fc/bnx2fc_hwi.c b/drivers/scsi/bnx2fc/bnx2fc_hwi.c
index f756d5f85c7a..d8e8a825560d 100644
--- a/drivers/scsi/bnx2fc/bnx2fc_hwi.c
+++ b/drivers/scsi/bnx2fc/bnx2fc_hwi.c
@@ -100,6 +100,9 @@ int bnx2fc_send_fw_fcoe_init_msg(struct bnx2fc_hba *hba)
100 fcoe_init2.hdr.flags = (FCOE_KWQE_LAYER_CODE << 100 fcoe_init2.hdr.flags = (FCOE_KWQE_LAYER_CODE <<
101 FCOE_KWQE_HEADER_LAYER_CODE_SHIFT); 101 FCOE_KWQE_HEADER_LAYER_CODE_SHIFT);
102 102
103 fcoe_init2.hsi_major_version = FCOE_HSI_MAJOR_VERSION;
104 fcoe_init2.hsi_minor_version = FCOE_HSI_MINOR_VERSION;
105
103 fcoe_init2.hash_tbl_pbl_addr_lo = (u32) hba->hash_tbl_pbl_dma; 106 fcoe_init2.hash_tbl_pbl_addr_lo = (u32) hba->hash_tbl_pbl_dma;
104 fcoe_init2.hash_tbl_pbl_addr_hi = (u32) 107 fcoe_init2.hash_tbl_pbl_addr_hi = (u32)
105 ((u64) hba->hash_tbl_pbl_dma >> 32); 108 ((u64) hba->hash_tbl_pbl_dma >> 32);
@@ -122,6 +125,7 @@ int bnx2fc_send_fw_fcoe_init_msg(struct bnx2fc_hba *hba)
122 fcoe_init3.error_bit_map_lo = 0xffffffff; 125 fcoe_init3.error_bit_map_lo = 0xffffffff;
123 fcoe_init3.error_bit_map_hi = 0xffffffff; 126 fcoe_init3.error_bit_map_hi = 0xffffffff;
124 127
128 fcoe_init3.perf_config = 1;
125 129
126 kwqe_arr[0] = (struct kwqe *) &fcoe_init1; 130 kwqe_arr[0] = (struct kwqe *) &fcoe_init1;
127 kwqe_arr[1] = (struct kwqe *) &fcoe_init2; 131 kwqe_arr[1] = (struct kwqe *) &fcoe_init2;
@@ -289,19 +293,19 @@ int bnx2fc_send_session_ofld_req(struct fcoe_port *port,
289 ofld_req4.e_d_tov_timer_val = lport->e_d_tov / 20; 293 ofld_req4.e_d_tov_timer_val = lport->e_d_tov / 20;
290 294
291 295
292 ofld_req4.src_mac_addr_lo32[0] = port->data_src_addr[5]; 296 ofld_req4.src_mac_addr_lo[0] = port->data_src_addr[5];
293 /* local mac */ 297 /* local mac */
294 ofld_req4.src_mac_addr_lo32[1] = port->data_src_addr[4]; 298 ofld_req4.src_mac_addr_lo[1] = port->data_src_addr[4];
295 ofld_req4.src_mac_addr_lo32[2] = port->data_src_addr[3]; 299 ofld_req4.src_mac_addr_mid[0] = port->data_src_addr[3];
296 ofld_req4.src_mac_addr_lo32[3] = port->data_src_addr[2]; 300 ofld_req4.src_mac_addr_mid[1] = port->data_src_addr[2];
297 ofld_req4.src_mac_addr_hi16[0] = port->data_src_addr[1]; 301 ofld_req4.src_mac_addr_hi[0] = port->data_src_addr[1];
298 ofld_req4.src_mac_addr_hi16[1] = port->data_src_addr[0]; 302 ofld_req4.src_mac_addr_hi[1] = port->data_src_addr[0];
299 ofld_req4.dst_mac_addr_lo32[0] = hba->ctlr.dest_addr[5];/* fcf mac */ 303 ofld_req4.dst_mac_addr_lo[0] = hba->ctlr.dest_addr[5];/* fcf mac */
300 ofld_req4.dst_mac_addr_lo32[1] = hba->ctlr.dest_addr[4]; 304 ofld_req4.dst_mac_addr_lo[1] = hba->ctlr.dest_addr[4];
301 ofld_req4.dst_mac_addr_lo32[2] = hba->ctlr.dest_addr[3]; 305 ofld_req4.dst_mac_addr_mid[0] = hba->ctlr.dest_addr[3];
302 ofld_req4.dst_mac_addr_lo32[3] = hba->ctlr.dest_addr[2]; 306 ofld_req4.dst_mac_addr_mid[1] = hba->ctlr.dest_addr[2];
303 ofld_req4.dst_mac_addr_hi16[0] = hba->ctlr.dest_addr[1]; 307 ofld_req4.dst_mac_addr_hi[0] = hba->ctlr.dest_addr[1];
304 ofld_req4.dst_mac_addr_hi16[1] = hba->ctlr.dest_addr[0]; 308 ofld_req4.dst_mac_addr_hi[1] = hba->ctlr.dest_addr[0];
305 309
306 ofld_req4.lcq_addr_lo = (u32) tgt->lcq_dma; 310 ofld_req4.lcq_addr_lo = (u32) tgt->lcq_dma;
307 ofld_req4.lcq_addr_hi = (u32)((u64) tgt->lcq_dma >> 32); 311 ofld_req4.lcq_addr_hi = (u32)((u64) tgt->lcq_dma >> 32);
@@ -345,20 +349,21 @@ static int bnx2fc_send_session_enable_req(struct fcoe_port *port,
345 enbl_req.hdr.flags = 349 enbl_req.hdr.flags =
346 (FCOE_KWQE_LAYER_CODE << FCOE_KWQE_HEADER_LAYER_CODE_SHIFT); 350 (FCOE_KWQE_LAYER_CODE << FCOE_KWQE_HEADER_LAYER_CODE_SHIFT);
347 351
348 enbl_req.src_mac_addr_lo32[0] = port->data_src_addr[5]; 352 enbl_req.src_mac_addr_lo[0] = port->data_src_addr[5];
349 /* local mac */ 353 /* local mac */
350 enbl_req.src_mac_addr_lo32[1] = port->data_src_addr[4]; 354 enbl_req.src_mac_addr_lo[1] = port->data_src_addr[4];
351 enbl_req.src_mac_addr_lo32[2] = port->data_src_addr[3]; 355 enbl_req.src_mac_addr_mid[0] = port->data_src_addr[3];
352 enbl_req.src_mac_addr_lo32[3] = port->data_src_addr[2]; 356 enbl_req.src_mac_addr_mid[1] = port->data_src_addr[2];
353 enbl_req.src_mac_addr_hi16[0] = port->data_src_addr[1]; 357 enbl_req.src_mac_addr_hi[0] = port->data_src_addr[1];
354 enbl_req.src_mac_addr_hi16[1] = port->data_src_addr[0]; 358 enbl_req.src_mac_addr_hi[1] = port->data_src_addr[0];
355 359 memcpy(tgt->src_addr, port->data_src_addr, ETH_ALEN);
356 enbl_req.dst_mac_addr_lo32[0] = hba->ctlr.dest_addr[5];/* fcf mac */ 360
357 enbl_req.dst_mac_addr_lo32[1] = hba->ctlr.dest_addr[4]; 361 enbl_req.dst_mac_addr_lo[0] = hba->ctlr.dest_addr[5];/* fcf mac */
358 enbl_req.dst_mac_addr_lo32[2] = hba->ctlr.dest_addr[3]; 362 enbl_req.dst_mac_addr_lo[1] = hba->ctlr.dest_addr[4];
359 enbl_req.dst_mac_addr_lo32[3] = hba->ctlr.dest_addr[2]; 363 enbl_req.dst_mac_addr_mid[0] = hba->ctlr.dest_addr[3];
360 enbl_req.dst_mac_addr_hi16[0] = hba->ctlr.dest_addr[1]; 364 enbl_req.dst_mac_addr_mid[1] = hba->ctlr.dest_addr[2];
361 enbl_req.dst_mac_addr_hi16[1] = hba->ctlr.dest_addr[0]; 365 enbl_req.dst_mac_addr_hi[0] = hba->ctlr.dest_addr[1];
366 enbl_req.dst_mac_addr_hi[1] = hba->ctlr.dest_addr[0];
362 367
363 port_id = fc_host_port_id(lport->host); 368 port_id = fc_host_port_id(lport->host);
364 if (port_id != tgt->sid) { 369 if (port_id != tgt->sid) {
@@ -411,18 +416,19 @@ int bnx2fc_send_session_disable_req(struct fcoe_port *port,
411 disable_req.hdr.flags = 416 disable_req.hdr.flags =
412 (FCOE_KWQE_LAYER_CODE << FCOE_KWQE_HEADER_LAYER_CODE_SHIFT); 417 (FCOE_KWQE_LAYER_CODE << FCOE_KWQE_HEADER_LAYER_CODE_SHIFT);
413 418
414 disable_req.src_mac_addr_lo32[0] = port->data_src_addr[5]; 419 disable_req.src_mac_addr_lo[0] = tgt->src_addr[5];
415 disable_req.src_mac_addr_lo32[2] = port->data_src_addr[3]; 420 disable_req.src_mac_addr_lo[1] = tgt->src_addr[4];
416 disable_req.src_mac_addr_lo32[3] = port->data_src_addr[2]; 421 disable_req.src_mac_addr_mid[0] = tgt->src_addr[3];
417 disable_req.src_mac_addr_hi16[0] = port->data_src_addr[1]; 422 disable_req.src_mac_addr_mid[1] = tgt->src_addr[2];
418 disable_req.src_mac_addr_hi16[1] = port->data_src_addr[0]; 423 disable_req.src_mac_addr_hi[0] = tgt->src_addr[1];
424 disable_req.src_mac_addr_hi[1] = tgt->src_addr[0];
419 425
420 disable_req.dst_mac_addr_lo32[0] = hba->ctlr.dest_addr[5];/* fcf mac */ 426 disable_req.dst_mac_addr_lo[0] = hba->ctlr.dest_addr[5];/* fcf mac */
421 disable_req.dst_mac_addr_lo32[1] = hba->ctlr.dest_addr[4]; 427 disable_req.dst_mac_addr_lo[1] = hba->ctlr.dest_addr[4];
422 disable_req.dst_mac_addr_lo32[2] = hba->ctlr.dest_addr[3]; 428 disable_req.dst_mac_addr_mid[0] = hba->ctlr.dest_addr[3];
423 disable_req.dst_mac_addr_lo32[3] = hba->ctlr.dest_addr[2]; 429 disable_req.dst_mac_addr_mid[1] = hba->ctlr.dest_addr[2];
424 disable_req.dst_mac_addr_hi16[0] = hba->ctlr.dest_addr[1]; 430 disable_req.dst_mac_addr_hi[0] = hba->ctlr.dest_addr[1];
425 disable_req.dst_mac_addr_hi16[1] = hba->ctlr.dest_addr[0]; 431 disable_req.dst_mac_addr_hi[1] = hba->ctlr.dest_addr[0];
426 432
427 port_id = tgt->sid; 433 port_id = tgt->sid;
428 disable_req.s_id[0] = (port_id & 0x000000FF); 434 disable_req.s_id[0] = (port_id & 0x000000FF);
@@ -640,10 +646,10 @@ static void bnx2fc_process_unsol_compl(struct bnx2fc_rport *tgt, u16 wqe)
640 xid = err_entry->fc_hdr.ox_id; 646 xid = err_entry->fc_hdr.ox_id;
641 BNX2FC_TGT_DBG(tgt, "Unsol Error Frame OX_ID = 0x%x\n", xid); 647 BNX2FC_TGT_DBG(tgt, "Unsol Error Frame OX_ID = 0x%x\n", xid);
642 BNX2FC_TGT_DBG(tgt, "err_warn_bitmap = %08x:%08x\n", 648 BNX2FC_TGT_DBG(tgt, "err_warn_bitmap = %08x:%08x\n",
643 err_entry->err_warn_bitmap_hi, 649 err_entry->data.err_warn_bitmap_hi,
644 err_entry->err_warn_bitmap_lo); 650 err_entry->data.err_warn_bitmap_lo);
645 BNX2FC_TGT_DBG(tgt, "buf_offsets - tx = 0x%x, rx = 0x%x\n", 651 BNX2FC_TGT_DBG(tgt, "buf_offsets - tx = 0x%x, rx = 0x%x\n",
646 err_entry->tx_buf_off, err_entry->rx_buf_off); 652 err_entry->data.tx_buf_off, err_entry->data.rx_buf_off);
647 653
648 bnx2fc_return_rqe(tgt, 1); 654 bnx2fc_return_rqe(tgt, 1);
649 655
@@ -722,10 +728,10 @@ static void bnx2fc_process_unsol_compl(struct bnx2fc_rport *tgt, u16 wqe)
722 xid = cpu_to_be16(err_entry->fc_hdr.ox_id); 728 xid = cpu_to_be16(err_entry->fc_hdr.ox_id);
723 BNX2FC_TGT_DBG(tgt, "Unsol Warning Frame OX_ID = 0x%x\n", xid); 729 BNX2FC_TGT_DBG(tgt, "Unsol Warning Frame OX_ID = 0x%x\n", xid);
724 BNX2FC_TGT_DBG(tgt, "err_warn_bitmap = %08x:%08x", 730 BNX2FC_TGT_DBG(tgt, "err_warn_bitmap = %08x:%08x",
725 err_entry->err_warn_bitmap_hi, 731 err_entry->data.err_warn_bitmap_hi,
726 err_entry->err_warn_bitmap_lo); 732 err_entry->data.err_warn_bitmap_lo);
727 BNX2FC_TGT_DBG(tgt, "buf_offsets - tx = 0x%x, rx = 0x%x", 733 BNX2FC_TGT_DBG(tgt, "buf_offsets - tx = 0x%x, rx = 0x%x",
728 err_entry->tx_buf_off, err_entry->rx_buf_off); 734 err_entry->data.tx_buf_off, err_entry->data.rx_buf_off);
729 735
730 bnx2fc_return_rqe(tgt, 1); 736 bnx2fc_return_rqe(tgt, 1);
731 spin_unlock_bh(&tgt->tgt_lock); 737 spin_unlock_bh(&tgt->tgt_lock);
@@ -762,9 +768,9 @@ void bnx2fc_process_cq_compl(struct bnx2fc_rport *tgt, u16 wqe)
762 task_page = (struct fcoe_task_ctx_entry *)hba->task_ctx[task_idx]; 768 task_page = (struct fcoe_task_ctx_entry *)hba->task_ctx[task_idx];
763 task = &(task_page[index]); 769 task = &(task_page[index]);
764 770
765 num_rq = ((task->rx_wr_tx_rd.rx_flags & 771 num_rq = ((task->rxwr_txrd.var_ctx.rx_flags &
766 FCOE_TASK_CTX_ENTRY_RXWR_TXRD_NUM_RQ_WQE) >> 772 FCOE_TCE_RX_WR_TX_RD_VAR_NUM_RQ_WQE) >>
767 FCOE_TASK_CTX_ENTRY_RXWR_TXRD_NUM_RQ_WQE_SHIFT); 773 FCOE_TCE_RX_WR_TX_RD_VAR_NUM_RQ_WQE_SHIFT);
768 774
769 io_req = (struct bnx2fc_cmd *)hba->cmd_mgr->cmds[xid]; 775 io_req = (struct bnx2fc_cmd *)hba->cmd_mgr->cmds[xid];
770 776
@@ -777,22 +783,19 @@ void bnx2fc_process_cq_compl(struct bnx2fc_rport *tgt, u16 wqe)
777 /* Timestamp IO completion time */ 783 /* Timestamp IO completion time */
778 cmd_type = io_req->cmd_type; 784 cmd_type = io_req->cmd_type;
779 785
780 /* optimized completion path */ 786 rx_state = ((task->rxwr_txrd.var_ctx.rx_flags &
781 if (cmd_type == BNX2FC_SCSI_CMD) { 787 FCOE_TCE_RX_WR_TX_RD_VAR_RX_STATE) >>
782 rx_state = ((task->rx_wr_tx_rd.rx_flags & 788 FCOE_TCE_RX_WR_TX_RD_VAR_RX_STATE_SHIFT);
783 FCOE_TASK_CTX_ENTRY_RXWR_TXRD_RX_STATE) >>
784 FCOE_TASK_CTX_ENTRY_RXWR_TXRD_RX_STATE_SHIFT);
785 789
790 /* Process other IO completion types */
791 switch (cmd_type) {
792 case BNX2FC_SCSI_CMD:
786 if (rx_state == FCOE_TASK_RX_STATE_COMPLETED) { 793 if (rx_state == FCOE_TASK_RX_STATE_COMPLETED) {
787 bnx2fc_process_scsi_cmd_compl(io_req, task, num_rq); 794 bnx2fc_process_scsi_cmd_compl(io_req, task, num_rq);
788 spin_unlock_bh(&tgt->tgt_lock); 795 spin_unlock_bh(&tgt->tgt_lock);
789 return; 796 return;
790 } 797 }
791 }
792 798
793 /* Process other IO completion types */
794 switch (cmd_type) {
795 case BNX2FC_SCSI_CMD:
796 if (rx_state == FCOE_TASK_RX_STATE_ABTS_COMPLETED) 799 if (rx_state == FCOE_TASK_RX_STATE_ABTS_COMPLETED)
797 bnx2fc_process_abts_compl(io_req, task, num_rq); 800 bnx2fc_process_abts_compl(io_req, task, num_rq);
798 else if (rx_state == 801 else if (rx_state ==
@@ -819,8 +822,16 @@ void bnx2fc_process_cq_compl(struct bnx2fc_rport *tgt, u16 wqe)
819 break; 822 break;
820 823
821 case BNX2FC_ELS: 824 case BNX2FC_ELS:
822 BNX2FC_IO_DBG(io_req, "cq_compl - call process_els_compl\n"); 825 if (rx_state == FCOE_TASK_RX_STATE_COMPLETED)
823 bnx2fc_process_els_compl(io_req, task, num_rq); 826 bnx2fc_process_els_compl(io_req, task, num_rq);
827 else if (rx_state == FCOE_TASK_RX_STATE_ABTS_COMPLETED)
828 bnx2fc_process_abts_compl(io_req, task, num_rq);
829 else if (rx_state ==
830 FCOE_TASK_RX_STATE_EXCHANGE_CLEANUP_COMPLETED)
831 bnx2fc_process_cleanup_compl(io_req, task, num_rq);
832 else
833 printk(KERN_ERR PFX "Invalid rx state = %d\n",
834 rx_state);
824 break; 835 break;
825 836
826 case BNX2FC_CLEANUP: 837 case BNX2FC_CLEANUP:
@@ -835,6 +846,20 @@ void bnx2fc_process_cq_compl(struct bnx2fc_rport *tgt, u16 wqe)
835 spin_unlock_bh(&tgt->tgt_lock); 846 spin_unlock_bh(&tgt->tgt_lock);
836} 847}
837 848
849void bnx2fc_arm_cq(struct bnx2fc_rport *tgt)
850{
851 struct b577xx_fcoe_rx_doorbell *rx_db = &tgt->rx_db;
852 u32 msg;
853
854 wmb();
855 rx_db->doorbell_cq_cons = tgt->cq_cons_idx | (tgt->cq_curr_toggle_bit <<
856 FCOE_CQE_TOGGLE_BIT_SHIFT);
857 msg = *((u32 *)rx_db);
858 writel(cpu_to_le32(msg), tgt->ctx_base);
859 mmiowb();
860
861}
862
838struct bnx2fc_work *bnx2fc_alloc_work(struct bnx2fc_rport *tgt, u16 wqe) 863struct bnx2fc_work *bnx2fc_alloc_work(struct bnx2fc_rport *tgt, u16 wqe)
839{ 864{
840 struct bnx2fc_work *work; 865 struct bnx2fc_work *work;
@@ -853,8 +878,8 @@ int bnx2fc_process_new_cqes(struct bnx2fc_rport *tgt)
853 struct fcoe_cqe *cq; 878 struct fcoe_cqe *cq;
854 u32 cq_cons; 879 u32 cq_cons;
855 struct fcoe_cqe *cqe; 880 struct fcoe_cqe *cqe;
881 u32 num_free_sqes = 0;
856 u16 wqe; 882 u16 wqe;
857 bool more_cqes_found = false;
858 883
859 /* 884 /*
860 * cq_lock is a low contention lock used to protect 885 * cq_lock is a low contention lock used to protect
@@ -872,62 +897,51 @@ int bnx2fc_process_new_cqes(struct bnx2fc_rport *tgt)
872 cq_cons = tgt->cq_cons_idx; 897 cq_cons = tgt->cq_cons_idx;
873 cqe = &cq[cq_cons]; 898 cqe = &cq[cq_cons];
874 899
875 do { 900 while (((wqe = cqe->wqe) & FCOE_CQE_TOGGLE_BIT) ==
876 more_cqes_found ^= true; 901 (tgt->cq_curr_toggle_bit <<
877 902 FCOE_CQE_TOGGLE_BIT_SHIFT)) {
878 while (((wqe = cqe->wqe) & FCOE_CQE_TOGGLE_BIT) ==
879 (tgt->cq_curr_toggle_bit <<
880 FCOE_CQE_TOGGLE_BIT_SHIFT)) {
881 903
882 /* new entry on the cq */ 904 /* new entry on the cq */
883 if (wqe & FCOE_CQE_CQE_TYPE) { 905 if (wqe & FCOE_CQE_CQE_TYPE) {
884 /* Unsolicited event notification */ 906 /* Unsolicited event notification */
885 bnx2fc_process_unsol_compl(tgt, wqe); 907 bnx2fc_process_unsol_compl(tgt, wqe);
886 } else { 908 } else {
887 struct bnx2fc_work *work = NULL; 909 /* Pending work request completion */
888 struct bnx2fc_percpu_s *fps = NULL; 910 struct bnx2fc_work *work = NULL;
889 unsigned int cpu = wqe % num_possible_cpus(); 911 struct bnx2fc_percpu_s *fps = NULL;
890 912 unsigned int cpu = wqe % num_possible_cpus();
891 fps = &per_cpu(bnx2fc_percpu, cpu); 913
892 spin_lock_bh(&fps->fp_work_lock); 914 fps = &per_cpu(bnx2fc_percpu, cpu);
893 if (unlikely(!fps->iothread)) 915 spin_lock_bh(&fps->fp_work_lock);
894 goto unlock; 916 if (unlikely(!fps->iothread))
895 917 goto unlock;
896 work = bnx2fc_alloc_work(tgt, wqe); 918
897 if (work) 919 work = bnx2fc_alloc_work(tgt, wqe);
898 list_add_tail(&work->list, 920 if (work)
899 &fps->work_list); 921 list_add_tail(&work->list,
922 &fps->work_list);
900unlock: 923unlock:
901 spin_unlock_bh(&fps->fp_work_lock); 924 spin_unlock_bh(&fps->fp_work_lock);
902 925
903 /* Pending work request completion */ 926 /* Pending work request completion */
904 if (fps->iothread && work) 927 if (fps->iothread && work)
905 wake_up_process(fps->iothread); 928 wake_up_process(fps->iothread);
906 else 929 else
907 bnx2fc_process_cq_compl(tgt, wqe); 930 bnx2fc_process_cq_compl(tgt, wqe);
908 }
909 cqe++;
910 tgt->cq_cons_idx++;
911
912 if (tgt->cq_cons_idx == BNX2FC_CQ_WQES_MAX) {
913 tgt->cq_cons_idx = 0;
914 cqe = cq;
915 tgt->cq_curr_toggle_bit =
916 1 - tgt->cq_curr_toggle_bit;
917 }
918 } 931 }
919 /* Re-arm CQ */ 932 cqe++;
920 if (more_cqes_found) { 933 tgt->cq_cons_idx++;
921 tgt->conn_db->cq_arm.lo = -1; 934 num_free_sqes++;
922 wmb(); 935
936 if (tgt->cq_cons_idx == BNX2FC_CQ_WQES_MAX) {
937 tgt->cq_cons_idx = 0;
938 cqe = cq;
939 tgt->cq_curr_toggle_bit =
940 1 - tgt->cq_curr_toggle_bit;
923 } 941 }
924 } while (more_cqes_found); 942 }
925 943 bnx2fc_arm_cq(tgt);
926 /* 944 atomic_add(num_free_sqes, &tgt->free_sqes);
927 * Commit tgt->cq_cons_idx change to the memory
928 * spin_lock implies full memory barrier, no need to smp_wmb
929 */
930
931 spin_unlock_bh(&tgt->cq_lock); 945 spin_unlock_bh(&tgt->cq_lock);
932 return 0; 946 return 0;
933} 947}
@@ -1141,7 +1155,11 @@ static void bnx2fc_init_failure(struct bnx2fc_hba *hba, u32 err_code)
1141 case FCOE_KCQE_COMPLETION_STATUS_NIC_ERROR: 1155 case FCOE_KCQE_COMPLETION_STATUS_NIC_ERROR:
1142 printk(KERN_ERR PFX "init_failure due to NIC error\n"); 1156 printk(KERN_ERR PFX "init_failure due to NIC error\n");
1143 break; 1157 break;
1144 1158 case FCOE_KCQE_COMPLETION_STATUS_ERROR:
1159 printk(KERN_ERR PFX "init failure due to compl status err\n");
1160 break;
1161 case FCOE_KCQE_COMPLETION_STATUS_WRONG_HSI_VERSION:
1162 printk(KERN_ERR PFX "init failure due to HSI mismatch\n");
1145 default: 1163 default:
1146 printk(KERN_ERR PFX "Unknown Error code %d\n", err_code); 1164 printk(KERN_ERR PFX "Unknown Error code %d\n", err_code);
1147 } 1165 }
@@ -1247,21 +1265,14 @@ void bnx2fc_add_2_sq(struct bnx2fc_rport *tgt, u16 xid)
1247 1265
1248void bnx2fc_ring_doorbell(struct bnx2fc_rport *tgt) 1266void bnx2fc_ring_doorbell(struct bnx2fc_rport *tgt)
1249{ 1267{
1250 struct b577xx_doorbell_set_prod ev_doorbell; 1268 struct b577xx_doorbell_set_prod *sq_db = &tgt->sq_db;
1251 u32 msg; 1269 u32 msg;
1252 1270
1253 wmb(); 1271 wmb();
1254 1272 sq_db->prod = tgt->sq_prod_idx |
1255 memset(&ev_doorbell, 0, sizeof(struct b577xx_doorbell_set_prod));
1256 ev_doorbell.header.header = B577XX_DOORBELL_HDR_DB_TYPE;
1257
1258 ev_doorbell.prod = tgt->sq_prod_idx |
1259 (tgt->sq_curr_toggle_bit << 15); 1273 (tgt->sq_curr_toggle_bit << 15);
1260 ev_doorbell.header.header |= B577XX_FCOE_CONNECTION_TYPE << 1274 msg = *((u32 *)sq_db);
1261 B577XX_DOORBELL_HDR_CONN_TYPE_SHIFT;
1262 msg = *((u32 *)&ev_doorbell);
1263 writel(cpu_to_le32(msg), tgt->ctx_base); 1275 writel(cpu_to_le32(msg), tgt->ctx_base);
1264
1265 mmiowb(); 1276 mmiowb();
1266 1277
1267} 1278}
@@ -1322,18 +1333,26 @@ void bnx2fc_init_cleanup_task(struct bnx2fc_cmd *io_req,
1322 memset(task, 0, sizeof(struct fcoe_task_ctx_entry)); 1333 memset(task, 0, sizeof(struct fcoe_task_ctx_entry));
1323 1334
1324 /* Tx Write Rx Read */ 1335 /* Tx Write Rx Read */
1325 task->tx_wr_rx_rd.tx_flags = FCOE_TASK_TX_STATE_EXCHANGE_CLEANUP << 1336 /* init flags */
1326 FCOE_TASK_CTX_ENTRY_TXWR_RXRD_TX_STATE_SHIFT; 1337 task->txwr_rxrd.const_ctx.init_flags = task_type <<
1327 task->tx_wr_rx_rd.init_flags = task_type << 1338 FCOE_TCE_TX_WR_RX_RD_CONST_TASK_TYPE_SHIFT;
1328 FCOE_TASK_CTX_ENTRY_TXWR_RXRD_TASK_TYPE_SHIFT; 1339 task->txwr_rxrd.const_ctx.init_flags |= FCOE_TASK_CLASS_TYPE_3 <<
1329 task->tx_wr_rx_rd.init_flags |= FCOE_TASK_CLASS_TYPE_3 << 1340 FCOE_TCE_TX_WR_RX_RD_CONST_CLASS_TYPE_SHIFT;
1330 FCOE_TASK_CTX_ENTRY_TXWR_RXRD_CLASS_TYPE_SHIFT; 1341 task->txwr_rxrd.const_ctx.init_flags |=
1331 /* Common */ 1342 FCOE_TASK_DEV_TYPE_DISK <<
1332 task->cmn.common_flags = context_id << 1343 FCOE_TCE_TX_WR_RX_RD_CONST_DEV_TYPE_SHIFT;
1333 FCOE_TASK_CTX_ENTRY_TX_RX_CMN_CID_SHIFT; 1344 task->txwr_rxrd.union_ctx.cleanup.ctx.cleaned_task_id = orig_xid;
1334 task->cmn.general.cleanup_info.task_id = orig_xid; 1345
1335 1346 /* Tx flags */
1336 1347 task->txwr_rxrd.const_ctx.tx_flags =
1348 FCOE_TASK_TX_STATE_EXCHANGE_CLEANUP <<
1349 FCOE_TCE_TX_WR_RX_RD_CONST_TX_STATE_SHIFT;
1350
1351 /* Rx Read Tx Write */
1352 task->rxwr_txrd.const_ctx.init_flags = context_id <<
1353 FCOE_TCE_RX_WR_TX_RD_CONST_CID_SHIFT;
1354 task->rxwr_txrd.var_ctx.rx_flags |= 1 <<
1355 FCOE_TCE_RX_WR_TX_RD_VAR_EXP_FIRST_FRAME_SHIFT;
1337} 1356}
1338 1357
1339void bnx2fc_init_mp_task(struct bnx2fc_cmd *io_req, 1358void bnx2fc_init_mp_task(struct bnx2fc_cmd *io_req,
@@ -1342,6 +1361,7 @@ void bnx2fc_init_mp_task(struct bnx2fc_cmd *io_req,
1342 struct bnx2fc_mp_req *mp_req = &(io_req->mp_req); 1361 struct bnx2fc_mp_req *mp_req = &(io_req->mp_req);
1343 struct bnx2fc_rport *tgt = io_req->tgt; 1362 struct bnx2fc_rport *tgt = io_req->tgt;
1344 struct fc_frame_header *fc_hdr; 1363 struct fc_frame_header *fc_hdr;
1364 struct fcoe_ext_mul_sges_ctx *sgl;
1345 u8 task_type = 0; 1365 u8 task_type = 0;
1346 u64 *hdr; 1366 u64 *hdr;
1347 u64 temp_hdr[3]; 1367 u64 temp_hdr[3];
@@ -1367,47 +1387,49 @@ void bnx2fc_init_mp_task(struct bnx2fc_cmd *io_req,
1367 /* Tx only */ 1387 /* Tx only */
1368 if ((task_type == FCOE_TASK_TYPE_MIDPATH) || 1388 if ((task_type == FCOE_TASK_TYPE_MIDPATH) ||
1369 (task_type == FCOE_TASK_TYPE_UNSOLICITED)) { 1389 (task_type == FCOE_TASK_TYPE_UNSOLICITED)) {
1370 task->tx_wr_only.sgl_ctx.mul_sges.cur_sge_addr.lo = 1390 task->txwr_only.sgl_ctx.sgl.mul_sgl.cur_sge_addr.lo =
1371 (u32)mp_req->mp_req_bd_dma; 1391 (u32)mp_req->mp_req_bd_dma;
1372 task->tx_wr_only.sgl_ctx.mul_sges.cur_sge_addr.hi = 1392 task->txwr_only.sgl_ctx.sgl.mul_sgl.cur_sge_addr.hi =
1373 (u32)((u64)mp_req->mp_req_bd_dma >> 32); 1393 (u32)((u64)mp_req->mp_req_bd_dma >> 32);
1374 task->tx_wr_only.sgl_ctx.mul_sges.sgl_size = 1; 1394 task->txwr_only.sgl_ctx.sgl.mul_sgl.sgl_size = 1;
1375 BNX2FC_IO_DBG(io_req, "init_mp_task - bd_dma = 0x%llx\n",
1376 (unsigned long long)mp_req->mp_req_bd_dma);
1377 } 1395 }
1378 1396
1379 /* Tx Write Rx Read */ 1397 /* Tx Write Rx Read */
1380 task->tx_wr_rx_rd.tx_flags = FCOE_TASK_TX_STATE_INIT << 1398 /* init flags */
1381 FCOE_TASK_CTX_ENTRY_TXWR_RXRD_TX_STATE_SHIFT; 1399 task->txwr_rxrd.const_ctx.init_flags = task_type <<
1382 task->tx_wr_rx_rd.init_flags = task_type << 1400 FCOE_TCE_TX_WR_RX_RD_CONST_TASK_TYPE_SHIFT;
1383 FCOE_TASK_CTX_ENTRY_TXWR_RXRD_TASK_TYPE_SHIFT; 1401 task->txwr_rxrd.const_ctx.init_flags |=
1384 task->tx_wr_rx_rd.init_flags |= FCOE_TASK_DEV_TYPE_DISK << 1402 FCOE_TASK_DEV_TYPE_DISK <<
1385 FCOE_TASK_CTX_ENTRY_TXWR_RXRD_DEV_TYPE_SHIFT; 1403 FCOE_TCE_TX_WR_RX_RD_CONST_DEV_TYPE_SHIFT;
1386 task->tx_wr_rx_rd.init_flags |= FCOE_TASK_CLASS_TYPE_3 << 1404 task->txwr_rxrd.const_ctx.init_flags |= FCOE_TASK_CLASS_TYPE_3 <<
1387 FCOE_TASK_CTX_ENTRY_TXWR_RXRD_CLASS_TYPE_SHIFT; 1405 FCOE_TCE_TX_WR_RX_RD_CONST_CLASS_TYPE_SHIFT;
1388 1406
1389 /* Common */ 1407 /* tx flags */
1390 task->cmn.data_2_trns = io_req->data_xfer_len; 1408 task->txwr_rxrd.const_ctx.tx_flags = FCOE_TASK_TX_STATE_INIT <<
1391 context_id = tgt->context_id; 1409 FCOE_TCE_TX_WR_RX_RD_CONST_TX_STATE_SHIFT;
1392 task->cmn.common_flags = context_id <<
1393 FCOE_TASK_CTX_ENTRY_TX_RX_CMN_CID_SHIFT;
1394 task->cmn.common_flags |= 1 <<
1395 FCOE_TASK_CTX_ENTRY_TX_RX_CMN_VALID_SHIFT;
1396 task->cmn.common_flags |= 1 <<
1397 FCOE_TASK_CTX_ENTRY_TX_RX_CMN_EXP_FIRST_FRAME_SHIFT;
1398 1410
1399 /* Rx Write Tx Read */ 1411 /* Rx Write Tx Read */
1412 task->rxwr_txrd.const_ctx.data_2_trns = io_req->data_xfer_len;
1413
1414 /* rx flags */
1415 task->rxwr_txrd.var_ctx.rx_flags |= 1 <<
1416 FCOE_TCE_RX_WR_TX_RD_VAR_EXP_FIRST_FRAME_SHIFT;
1417
1418 context_id = tgt->context_id;
1419 task->rxwr_txrd.const_ctx.init_flags = context_id <<
1420 FCOE_TCE_RX_WR_TX_RD_CONST_CID_SHIFT;
1421
1400 fc_hdr = &(mp_req->req_fc_hdr); 1422 fc_hdr = &(mp_req->req_fc_hdr);
1401 if (task_type == FCOE_TASK_TYPE_MIDPATH) { 1423 if (task_type == FCOE_TASK_TYPE_MIDPATH) {
1402 fc_hdr->fh_ox_id = cpu_to_be16(io_req->xid); 1424 fc_hdr->fh_ox_id = cpu_to_be16(io_req->xid);
1403 fc_hdr->fh_rx_id = htons(0xffff); 1425 fc_hdr->fh_rx_id = htons(0xffff);
1404 task->rx_wr_tx_rd.rx_id = 0xffff; 1426 task->rxwr_txrd.var_ctx.rx_id = 0xffff;
1405 } else if (task_type == FCOE_TASK_TYPE_UNSOLICITED) { 1427 } else if (task_type == FCOE_TASK_TYPE_UNSOLICITED) {
1406 fc_hdr->fh_rx_id = cpu_to_be16(io_req->xid); 1428 fc_hdr->fh_rx_id = cpu_to_be16(io_req->xid);
1407 } 1429 }
1408 1430
1409 /* Fill FC Header into middle path buffer */ 1431 /* Fill FC Header into middle path buffer */
1410 hdr = (u64 *) &task->cmn.general.cmd_info.mp_fc_frame.fc_hdr; 1432 hdr = (u64 *) &task->txwr_rxrd.union_ctx.tx_frame.fc_hdr;
1411 memcpy(temp_hdr, fc_hdr, sizeof(temp_hdr)); 1433 memcpy(temp_hdr, fc_hdr, sizeof(temp_hdr));
1412 hdr[0] = cpu_to_be64(temp_hdr[0]); 1434 hdr[0] = cpu_to_be64(temp_hdr[0]);
1413 hdr[1] = cpu_to_be64(temp_hdr[1]); 1435 hdr[1] = cpu_to_be64(temp_hdr[1]);
@@ -1415,12 +1437,12 @@ void bnx2fc_init_mp_task(struct bnx2fc_cmd *io_req,
1415 1437
1416 /* Rx Only */ 1438 /* Rx Only */
1417 if (task_type == FCOE_TASK_TYPE_MIDPATH) { 1439 if (task_type == FCOE_TASK_TYPE_MIDPATH) {
1440 sgl = &task->rxwr_only.union_ctx.read_info.sgl_ctx.sgl;
1418 1441
1419 task->rx_wr_only.sgl_ctx.mul_sges.cur_sge_addr.lo = 1442 sgl->mul_sgl.cur_sge_addr.lo = (u32)mp_req->mp_resp_bd_dma;
1420 (u32)mp_req->mp_resp_bd_dma; 1443 sgl->mul_sgl.cur_sge_addr.hi =
1421 task->rx_wr_only.sgl_ctx.mul_sges.cur_sge_addr.hi =
1422 (u32)((u64)mp_req->mp_resp_bd_dma >> 32); 1444 (u32)((u64)mp_req->mp_resp_bd_dma >> 32);
1423 task->rx_wr_only.sgl_ctx.mul_sges.sgl_size = 1; 1445 sgl->mul_sgl.sgl_size = 1;
1424 } 1446 }
1425} 1447}
1426 1448
@@ -1431,6 +1453,8 @@ void bnx2fc_init_task(struct bnx2fc_cmd *io_req,
1431 struct scsi_cmnd *sc_cmd = io_req->sc_cmd; 1453 struct scsi_cmnd *sc_cmd = io_req->sc_cmd;
1432 struct io_bdt *bd_tbl = io_req->bd_tbl; 1454 struct io_bdt *bd_tbl = io_req->bd_tbl;
1433 struct bnx2fc_rport *tgt = io_req->tgt; 1455 struct bnx2fc_rport *tgt = io_req->tgt;
1456 struct fcoe_cached_sge_ctx *cached_sge;
1457 struct fcoe_ext_mul_sges_ctx *sgl;
1434 u64 *fcp_cmnd; 1458 u64 *fcp_cmnd;
1435 u64 tmp_fcp_cmnd[4]; 1459 u64 tmp_fcp_cmnd[4];
1436 u32 context_id; 1460 u32 context_id;
@@ -1449,47 +1473,33 @@ void bnx2fc_init_task(struct bnx2fc_cmd *io_req,
1449 1473
1450 /* Tx only */ 1474 /* Tx only */
1451 if (task_type == FCOE_TASK_TYPE_WRITE) { 1475 if (task_type == FCOE_TASK_TYPE_WRITE) {
1452 task->tx_wr_only.sgl_ctx.mul_sges.cur_sge_addr.lo = 1476 task->txwr_only.sgl_ctx.sgl.mul_sgl.cur_sge_addr.lo =
1453 (u32)bd_tbl->bd_tbl_dma; 1477 (u32)bd_tbl->bd_tbl_dma;
1454 task->tx_wr_only.sgl_ctx.mul_sges.cur_sge_addr.hi = 1478 task->txwr_only.sgl_ctx.sgl.mul_sgl.cur_sge_addr.hi =
1455 (u32)((u64)bd_tbl->bd_tbl_dma >> 32); 1479 (u32)((u64)bd_tbl->bd_tbl_dma >> 32);
1456 task->tx_wr_only.sgl_ctx.mul_sges.sgl_size = 1480 task->txwr_only.sgl_ctx.sgl.mul_sgl.sgl_size =
1457 bd_tbl->bd_valid; 1481 bd_tbl->bd_valid;
1458 } 1482 }
1459 1483
1460 /*Tx Write Rx Read */ 1484 /*Tx Write Rx Read */
1461 /* Init state to NORMAL */ 1485 /* Init state to NORMAL */
1462 task->tx_wr_rx_rd.tx_flags = FCOE_TASK_TX_STATE_NORMAL << 1486 task->txwr_rxrd.const_ctx.init_flags = task_type <<
1463 FCOE_TASK_CTX_ENTRY_TXWR_RXRD_TX_STATE_SHIFT; 1487 FCOE_TCE_TX_WR_RX_RD_CONST_TASK_TYPE_SHIFT;
1464 task->tx_wr_rx_rd.init_flags = task_type << 1488 task->txwr_rxrd.const_ctx.init_flags |=
1465 FCOE_TASK_CTX_ENTRY_TXWR_RXRD_TASK_TYPE_SHIFT; 1489 FCOE_TASK_DEV_TYPE_DISK <<
1466 task->tx_wr_rx_rd.init_flags |= FCOE_TASK_DEV_TYPE_DISK << 1490 FCOE_TCE_TX_WR_RX_RD_CONST_DEV_TYPE_SHIFT;
1467 FCOE_TASK_CTX_ENTRY_TXWR_RXRD_DEV_TYPE_SHIFT; 1491 task->txwr_rxrd.const_ctx.init_flags |= FCOE_TASK_CLASS_TYPE_3 <<
1468 task->tx_wr_rx_rd.init_flags |= FCOE_TASK_CLASS_TYPE_3 << 1492 FCOE_TCE_TX_WR_RX_RD_CONST_CLASS_TYPE_SHIFT;
1469 FCOE_TASK_CTX_ENTRY_TXWR_RXRD_CLASS_TYPE_SHIFT; 1493 /* tx flags */
1470 1494 task->txwr_rxrd.const_ctx.tx_flags = FCOE_TASK_TX_STATE_NORMAL <<
1471 /* Common */ 1495 FCOE_TCE_TX_WR_RX_RD_CONST_TX_STATE_SHIFT;
1472 task->cmn.data_2_trns = io_req->data_xfer_len;
1473 context_id = tgt->context_id;
1474 task->cmn.common_flags = context_id <<
1475 FCOE_TASK_CTX_ENTRY_TX_RX_CMN_CID_SHIFT;
1476 task->cmn.common_flags |= 1 <<
1477 FCOE_TASK_CTX_ENTRY_TX_RX_CMN_VALID_SHIFT;
1478 task->cmn.common_flags |= 1 <<
1479 FCOE_TASK_CTX_ENTRY_TX_RX_CMN_EXP_FIRST_FRAME_SHIFT;
1480
1481 /* Set initiative ownership */
1482 task->cmn.common_flags |= FCOE_TASK_CTX_ENTRY_TX_RX_CMN_SEQ_INIT;
1483 1496
1484 /* Set initial seq counter */ 1497 /* Set initial seq counter */
1485 task->cmn.tx_low_seq_cnt = 1; 1498 task->txwr_rxrd.union_ctx.tx_seq.ctx.seq_cnt = 1;
1486
1487 /* Set state to "waiting for the first packet" */
1488 task->cmn.common_flags |= FCOE_TASK_CTX_ENTRY_TX_RX_CMN_EXP_FIRST_FRAME;
1489 1499
1490 /* Fill FCP_CMND IU */ 1500 /* Fill FCP_CMND IU */
1491 fcp_cmnd = (u64 *) 1501 fcp_cmnd = (u64 *)
1492 task->cmn.general.cmd_info.fcp_cmd_payload.opaque; 1502 task->txwr_rxrd.union_ctx.fcp_cmd.opaque;
1493 bnx2fc_build_fcp_cmnd(io_req, (struct fcp_cmnd *)&tmp_fcp_cmnd); 1503 bnx2fc_build_fcp_cmnd(io_req, (struct fcp_cmnd *)&tmp_fcp_cmnd);
1494 1504
1495 /* swap fcp_cmnd */ 1505 /* swap fcp_cmnd */
@@ -1501,32 +1511,54 @@ void bnx2fc_init_task(struct bnx2fc_cmd *io_req,
1501 } 1511 }
1502 1512
1503 /* Rx Write Tx Read */ 1513 /* Rx Write Tx Read */
1504 task->rx_wr_tx_rd.rx_id = 0xffff; 1514 task->rxwr_txrd.const_ctx.data_2_trns = io_req->data_xfer_len;
1515
1516 context_id = tgt->context_id;
1517 task->rxwr_txrd.const_ctx.init_flags = context_id <<
1518 FCOE_TCE_RX_WR_TX_RD_CONST_CID_SHIFT;
1519
1520 /* rx flags */
1521 /* Set state to "waiting for the first packet" */
1522 task->rxwr_txrd.var_ctx.rx_flags |= 1 <<
1523 FCOE_TCE_RX_WR_TX_RD_VAR_EXP_FIRST_FRAME_SHIFT;
1524
1525 task->rxwr_txrd.var_ctx.rx_id = 0xffff;
1505 1526
1506 /* Rx Only */ 1527 /* Rx Only */
1528 cached_sge = &task->rxwr_only.union_ctx.read_info.sgl_ctx.cached_sge;
1529 sgl = &task->rxwr_only.union_ctx.read_info.sgl_ctx.sgl;
1530 bd_count = bd_tbl->bd_valid;
1507 if (task_type == FCOE_TASK_TYPE_READ) { 1531 if (task_type == FCOE_TASK_TYPE_READ) {
1508
1509 bd_count = bd_tbl->bd_valid;
1510 if (bd_count == 1) { 1532 if (bd_count == 1) {
1511 1533
1512 struct fcoe_bd_ctx *fcoe_bd_tbl = bd_tbl->bd_tbl; 1534 struct fcoe_bd_ctx *fcoe_bd_tbl = bd_tbl->bd_tbl;
1513 1535
1514 task->rx_wr_only.sgl_ctx.single_sge.cur_buf_addr.lo = 1536 cached_sge->cur_buf_addr.lo = fcoe_bd_tbl->buf_addr_lo;
1515 fcoe_bd_tbl->buf_addr_lo; 1537 cached_sge->cur_buf_addr.hi = fcoe_bd_tbl->buf_addr_hi;
1516 task->rx_wr_only.sgl_ctx.single_sge.cur_buf_addr.hi = 1538 cached_sge->cur_buf_rem = fcoe_bd_tbl->buf_len;
1517 fcoe_bd_tbl->buf_addr_hi; 1539 task->txwr_rxrd.const_ctx.init_flags |= 1 <<
1518 task->rx_wr_only.sgl_ctx.single_sge.cur_buf_rem = 1540 FCOE_TCE_TX_WR_RX_RD_CONST_CACHED_SGE_SHIFT;
1519 fcoe_bd_tbl->buf_len; 1541 } else if (bd_count == 2) {
1520 task->tx_wr_rx_rd.init_flags |= 1 << 1542 struct fcoe_bd_ctx *fcoe_bd_tbl = bd_tbl->bd_tbl;
1521 FCOE_TASK_CTX_ENTRY_TXWR_RXRD_SINGLE_SGE_SHIFT; 1543
1544 cached_sge->cur_buf_addr.lo = fcoe_bd_tbl->buf_addr_lo;
1545 cached_sge->cur_buf_addr.hi = fcoe_bd_tbl->buf_addr_hi;
1546 cached_sge->cur_buf_rem = fcoe_bd_tbl->buf_len;
1547
1548 fcoe_bd_tbl++;
1549 cached_sge->second_buf_addr.lo =
1550 fcoe_bd_tbl->buf_addr_lo;
1551 cached_sge->second_buf_addr.hi =
1552 fcoe_bd_tbl->buf_addr_hi;
1553 cached_sge->second_buf_rem = fcoe_bd_tbl->buf_len;
1554 task->txwr_rxrd.const_ctx.init_flags |= 1 <<
1555 FCOE_TCE_TX_WR_RX_RD_CONST_CACHED_SGE_SHIFT;
1522 } else { 1556 } else {
1523 1557
1524 task->rx_wr_only.sgl_ctx.mul_sges.cur_sge_addr.lo = 1558 sgl->mul_sgl.cur_sge_addr.lo = (u32)bd_tbl->bd_tbl_dma;
1525 (u32)bd_tbl->bd_tbl_dma; 1559 sgl->mul_sgl.cur_sge_addr.hi =
1526 task->rx_wr_only.sgl_ctx.mul_sges.cur_sge_addr.hi =
1527 (u32)((u64)bd_tbl->bd_tbl_dma >> 32); 1560 (u32)((u64)bd_tbl->bd_tbl_dma >> 32);
1528 task->rx_wr_only.sgl_ctx.mul_sges.sgl_size = 1561 sgl->mul_sgl.sgl_size = bd_count;
1529 bd_tbl->bd_valid;
1530 } 1562 }
1531 } 1563 }
1532} 1564}
diff --git a/drivers/scsi/bnx2fc/bnx2fc_io.c b/drivers/scsi/bnx2fc/bnx2fc_io.c
index b5b5c346d779..5dc4205ed8af 100644
--- a/drivers/scsi/bnx2fc/bnx2fc_io.c
+++ b/drivers/scsi/bnx2fc/bnx2fc_io.c
@@ -425,6 +425,7 @@ struct bnx2fc_cmd *bnx2fc_elstm_alloc(struct bnx2fc_rport *tgt, int type)
425 struct list_head *listp; 425 struct list_head *listp;
426 struct io_bdt *bd_tbl; 426 struct io_bdt *bd_tbl;
427 int index = RESERVE_FREE_LIST_INDEX; 427 int index = RESERVE_FREE_LIST_INDEX;
428 u32 free_sqes;
428 u32 max_sqes; 429 u32 max_sqes;
429 u16 xid; 430 u16 xid;
430 431
@@ -445,8 +446,10 @@ struct bnx2fc_cmd *bnx2fc_elstm_alloc(struct bnx2fc_rport *tgt, int type)
445 * cmgr lock 446 * cmgr lock
446 */ 447 */
447 spin_lock_bh(&cmd_mgr->free_list_lock[index]); 448 spin_lock_bh(&cmd_mgr->free_list_lock[index]);
449 free_sqes = atomic_read(&tgt->free_sqes);
448 if ((list_empty(&(cmd_mgr->free_list[index]))) || 450 if ((list_empty(&(cmd_mgr->free_list[index]))) ||
449 (tgt->num_active_ios.counter >= max_sqes)) { 451 (tgt->num_active_ios.counter >= max_sqes) ||
452 (free_sqes + max_sqes <= BNX2FC_SQ_WQES_MAX)) {
450 BNX2FC_TGT_DBG(tgt, "No free els_tm cmds available " 453 BNX2FC_TGT_DBG(tgt, "No free els_tm cmds available "
451 "ios(%d):sqes(%d)\n", 454 "ios(%d):sqes(%d)\n",
452 tgt->num_active_ios.counter, tgt->max_sqes); 455 tgt->num_active_ios.counter, tgt->max_sqes);
@@ -463,6 +466,7 @@ struct bnx2fc_cmd *bnx2fc_elstm_alloc(struct bnx2fc_rport *tgt, int type)
463 xid = io_req->xid; 466 xid = io_req->xid;
464 cmd_mgr->cmds[xid] = io_req; 467 cmd_mgr->cmds[xid] = io_req;
465 atomic_inc(&tgt->num_active_ios); 468 atomic_inc(&tgt->num_active_ios);
469 atomic_dec(&tgt->free_sqes);
466 spin_unlock_bh(&cmd_mgr->free_list_lock[index]); 470 spin_unlock_bh(&cmd_mgr->free_list_lock[index]);
467 471
468 INIT_LIST_HEAD(&io_req->link); 472 INIT_LIST_HEAD(&io_req->link);
@@ -489,6 +493,7 @@ static struct bnx2fc_cmd *bnx2fc_cmd_alloc(struct bnx2fc_rport *tgt)
489 struct bnx2fc_cmd *io_req; 493 struct bnx2fc_cmd *io_req;
490 struct list_head *listp; 494 struct list_head *listp;
491 struct io_bdt *bd_tbl; 495 struct io_bdt *bd_tbl;
496 u32 free_sqes;
492 u32 max_sqes; 497 u32 max_sqes;
493 u16 xid; 498 u16 xid;
494 int index = get_cpu(); 499 int index = get_cpu();
@@ -499,8 +504,10 @@ static struct bnx2fc_cmd *bnx2fc_cmd_alloc(struct bnx2fc_rport *tgt)
499 * cmgr lock 504 * cmgr lock
500 */ 505 */
501 spin_lock_bh(&cmd_mgr->free_list_lock[index]); 506 spin_lock_bh(&cmd_mgr->free_list_lock[index]);
507 free_sqes = atomic_read(&tgt->free_sqes);
502 if ((list_empty(&cmd_mgr->free_list[index])) || 508 if ((list_empty(&cmd_mgr->free_list[index])) ||
503 (tgt->num_active_ios.counter >= max_sqes)) { 509 (tgt->num_active_ios.counter >= max_sqes) ||
510 (free_sqes + max_sqes <= BNX2FC_SQ_WQES_MAX)) {
504 spin_unlock_bh(&cmd_mgr->free_list_lock[index]); 511 spin_unlock_bh(&cmd_mgr->free_list_lock[index]);
505 put_cpu(); 512 put_cpu();
506 return NULL; 513 return NULL;
@@ -513,6 +520,7 @@ static struct bnx2fc_cmd *bnx2fc_cmd_alloc(struct bnx2fc_rport *tgt)
513 xid = io_req->xid; 520 xid = io_req->xid;
514 cmd_mgr->cmds[xid] = io_req; 521 cmd_mgr->cmds[xid] = io_req;
515 atomic_inc(&tgt->num_active_ios); 522 atomic_inc(&tgt->num_active_ios);
523 atomic_dec(&tgt->free_sqes);
516 spin_unlock_bh(&cmd_mgr->free_list_lock[index]); 524 spin_unlock_bh(&cmd_mgr->free_list_lock[index]);
517 put_cpu(); 525 put_cpu();
518 526
@@ -873,7 +881,7 @@ int bnx2fc_initiate_abts(struct bnx2fc_cmd *io_req)
873 881
874 /* Obtain oxid and rxid for the original exchange to be aborted */ 882 /* Obtain oxid and rxid for the original exchange to be aborted */
875 fc_hdr->fh_ox_id = htons(io_req->xid); 883 fc_hdr->fh_ox_id = htons(io_req->xid);
876 fc_hdr->fh_rx_id = htons(io_req->task->rx_wr_tx_rd.rx_id); 884 fc_hdr->fh_rx_id = htons(io_req->task->rxwr_txrd.var_ctx.rx_id);
877 885
878 sid = tgt->sid; 886 sid = tgt->sid;
879 did = rport->port_id; 887 did = rport->port_id;
@@ -1189,7 +1197,7 @@ void bnx2fc_process_abts_compl(struct bnx2fc_cmd *io_req,
1189 kref_put(&io_req->refcount, 1197 kref_put(&io_req->refcount,
1190 bnx2fc_cmd_release); /* drop timer hold */ 1198 bnx2fc_cmd_release); /* drop timer hold */
1191 1199
1192 r_ctl = task->cmn.general.rsp_info.abts_rsp.r_ctl; 1200 r_ctl = (u8)task->rxwr_only.union_ctx.comp_info.abts_rsp.r_ctl;
1193 1201
1194 switch (r_ctl) { 1202 switch (r_ctl) {
1195 case FC_RCTL_BA_ACC: 1203 case FC_RCTL_BA_ACC:
@@ -1344,12 +1352,13 @@ void bnx2fc_process_tm_compl(struct bnx2fc_cmd *io_req,
1344 fc_hdr = &(tm_req->resp_fc_hdr); 1352 fc_hdr = &(tm_req->resp_fc_hdr);
1345 hdr = (u64 *)fc_hdr; 1353 hdr = (u64 *)fc_hdr;
1346 temp_hdr = (u64 *) 1354 temp_hdr = (u64 *)
1347 &task->cmn.general.cmd_info.mp_fc_frame.fc_hdr; 1355 &task->rxwr_only.union_ctx.comp_info.mp_rsp.fc_hdr;
1348 hdr[0] = cpu_to_be64(temp_hdr[0]); 1356 hdr[0] = cpu_to_be64(temp_hdr[0]);
1349 hdr[1] = cpu_to_be64(temp_hdr[1]); 1357 hdr[1] = cpu_to_be64(temp_hdr[1]);
1350 hdr[2] = cpu_to_be64(temp_hdr[2]); 1358 hdr[2] = cpu_to_be64(temp_hdr[2]);
1351 1359
1352 tm_req->resp_len = task->rx_wr_only.sgl_ctx.mul_sges.cur_sge_off; 1360 tm_req->resp_len =
1361 task->rxwr_only.union_ctx.comp_info.mp_rsp.mp_payload_len;
1353 1362
1354 rsp_buf = tm_req->resp_buf; 1363 rsp_buf = tm_req->resp_buf;
1355 1364
@@ -1724,7 +1733,7 @@ void bnx2fc_process_scsi_cmd_compl(struct bnx2fc_cmd *io_req,
1724 1733
1725 /* Fetch fcp_rsp from task context and perform cmd completion */ 1734 /* Fetch fcp_rsp from task context and perform cmd completion */
1726 fcp_rsp = (struct fcoe_fcp_rsp_payload *) 1735 fcp_rsp = (struct fcoe_fcp_rsp_payload *)
1727 &(task->cmn.general.rsp_info.fcp_rsp.payload); 1736 &(task->rxwr_only.union_ctx.comp_info.fcp_rsp.payload);
1728 1737
1729 /* parse fcp_rsp and obtain sense data from RQ if available */ 1738 /* parse fcp_rsp and obtain sense data from RQ if available */
1730 bnx2fc_parse_fcp_rsp(io_req, fcp_rsp, num_rq); 1739 bnx2fc_parse_fcp_rsp(io_req, fcp_rsp, num_rq);
diff --git a/drivers/scsi/bnx2fc/bnx2fc_tgt.c b/drivers/scsi/bnx2fc/bnx2fc_tgt.c
index a2e3830bd268..3e892bd66fbe 100644
--- a/drivers/scsi/bnx2fc/bnx2fc_tgt.c
+++ b/drivers/scsi/bnx2fc/bnx2fc_tgt.c
@@ -133,6 +133,8 @@ retry_ofld:
133 /* upload will take care of cleaning up sess resc */ 133 /* upload will take care of cleaning up sess resc */
134 lport->tt.rport_logoff(rdata); 134 lport->tt.rport_logoff(rdata);
135 } 135 }
136 /* Arm CQ */
137 bnx2fc_arm_cq(tgt);
136 return; 138 return;
137 139
138ofld_err: 140ofld_err:
@@ -315,6 +317,8 @@ static int bnx2fc_init_tgt(struct bnx2fc_rport *tgt,
315 317
316 struct fc_rport *rport = rdata->rport; 318 struct fc_rport *rport = rdata->rport;
317 struct bnx2fc_hba *hba = port->priv; 319 struct bnx2fc_hba *hba = port->priv;
320 struct b577xx_doorbell_set_prod *sq_db = &tgt->sq_db;
321 struct b577xx_fcoe_rx_doorbell *rx_db = &tgt->rx_db;
318 322
319 tgt->rport = rport; 323 tgt->rport = rport;
320 tgt->rdata = rdata; 324 tgt->rdata = rdata;
@@ -335,6 +339,7 @@ static int bnx2fc_init_tgt(struct bnx2fc_rport *tgt,
335 tgt->max_sqes = BNX2FC_SQ_WQES_MAX; 339 tgt->max_sqes = BNX2FC_SQ_WQES_MAX;
336 tgt->max_rqes = BNX2FC_RQ_WQES_MAX; 340 tgt->max_rqes = BNX2FC_RQ_WQES_MAX;
337 tgt->max_cqes = BNX2FC_CQ_WQES_MAX; 341 tgt->max_cqes = BNX2FC_CQ_WQES_MAX;
342 atomic_set(&tgt->free_sqes, BNX2FC_SQ_WQES_MAX);
338 343
339 /* Initialize the toggle bit */ 344 /* Initialize the toggle bit */
340 tgt->sq_curr_toggle_bit = 1; 345 tgt->sq_curr_toggle_bit = 1;
@@ -345,7 +350,17 @@ static int bnx2fc_init_tgt(struct bnx2fc_rport *tgt,
345 tgt->rq_cons_idx = 0; 350 tgt->rq_cons_idx = 0;
346 atomic_set(&tgt->num_active_ios, 0); 351 atomic_set(&tgt->num_active_ios, 0);
347 352
348 tgt->work_time_slice = 2; 353 /* initialize sq doorbell */
354 sq_db->header.header = B577XX_DOORBELL_HDR_DB_TYPE;
355 sq_db->header.header |= B577XX_FCOE_CONNECTION_TYPE <<
356 B577XX_DOORBELL_HDR_CONN_TYPE_SHIFT;
357 /* initialize rx doorbell */
358 rx_db->hdr.header = ((0x1 << B577XX_DOORBELL_HDR_RX_SHIFT) |
359 (0x1 << B577XX_DOORBELL_HDR_DB_TYPE_SHIFT) |
360 (B577XX_FCOE_CONNECTION_TYPE <<
361 B577XX_DOORBELL_HDR_CONN_TYPE_SHIFT));
362 rx_db->params = (0x2 << B577XX_FCOE_RX_DOORBELL_NEGATIVE_ARM_SHIFT) |
363 (0x3 << B577XX_FCOE_RX_DOORBELL_OPCODE_SHIFT);
349 364
350 spin_lock_init(&tgt->tgt_lock); 365 spin_lock_init(&tgt->tgt_lock);
351 spin_lock_init(&tgt->cq_lock); 366 spin_lock_init(&tgt->cq_lock);
@@ -758,8 +773,6 @@ static int bnx2fc_alloc_session_resc(struct bnx2fc_hba *hba,
758 } 773 }
759 memset(tgt->lcq, 0, tgt->lcq_mem_size); 774 memset(tgt->lcq, 0, tgt->lcq_mem_size);
760 775
761 /* Arm CQ */
762 tgt->conn_db->cq_arm.lo = -1;
763 tgt->conn_db->rq_prod = 0x8000; 776 tgt->conn_db->rq_prod = 0x8000;
764 777
765 return 0; 778 return 0;
@@ -787,6 +800,8 @@ static void bnx2fc_free_session_resc(struct bnx2fc_hba *hba,
787 iounmap(tgt->ctx_base); 800 iounmap(tgt->ctx_base);
788 tgt->ctx_base = NULL; 801 tgt->ctx_base = NULL;
789 } 802 }
803
804 spin_lock_bh(&tgt->cq_lock);
790 /* Free LCQ */ 805 /* Free LCQ */
791 if (tgt->lcq) { 806 if (tgt->lcq) {
792 dma_free_coherent(&hba->pcidev->dev, tgt->lcq_mem_size, 807 dma_free_coherent(&hba->pcidev->dev, tgt->lcq_mem_size,
@@ -828,17 +843,16 @@ static void bnx2fc_free_session_resc(struct bnx2fc_hba *hba,
828 tgt->rq = NULL; 843 tgt->rq = NULL;
829 } 844 }
830 /* Free CQ */ 845 /* Free CQ */
831 spin_lock_bh(&tgt->cq_lock);
832 if (tgt->cq) { 846 if (tgt->cq) {
833 dma_free_coherent(&hba->pcidev->dev, tgt->cq_mem_size, 847 dma_free_coherent(&hba->pcidev->dev, tgt->cq_mem_size,
834 tgt->cq, tgt->cq_dma); 848 tgt->cq, tgt->cq_dma);
835 tgt->cq = NULL; 849 tgt->cq = NULL;
836 } 850 }
837 spin_unlock_bh(&tgt->cq_lock);
838 /* Free SQ */ 851 /* Free SQ */
839 if (tgt->sq) { 852 if (tgt->sq) {
840 dma_free_coherent(&hba->pcidev->dev, tgt->sq_mem_size, 853 dma_free_coherent(&hba->pcidev->dev, tgt->sq_mem_size,
841 tgt->sq, tgt->sq_dma); 854 tgt->sq, tgt->sq_dma);
842 tgt->sq = NULL; 855 tgt->sq = NULL;
843 } 856 }
857 spin_unlock_bh(&tgt->cq_lock);
844} 858}
diff --git a/drivers/scsi/bnx2i/57xx_iscsi_hsi.h b/drivers/scsi/bnx2i/57xx_iscsi_hsi.h
index dad6c8a34317..71890a063cd3 100644
--- a/drivers/scsi/bnx2i/57xx_iscsi_hsi.h
+++ b/drivers/scsi/bnx2i/57xx_iscsi_hsi.h
@@ -707,8 +707,10 @@ struct iscsi_kwqe_conn_update {
707#define ISCSI_KWQE_CONN_UPDATE_INITIAL_R2T_SHIFT 2 707#define ISCSI_KWQE_CONN_UPDATE_INITIAL_R2T_SHIFT 2
708#define ISCSI_KWQE_CONN_UPDATE_IMMEDIATE_DATA (0x1<<3) 708#define ISCSI_KWQE_CONN_UPDATE_IMMEDIATE_DATA (0x1<<3)
709#define ISCSI_KWQE_CONN_UPDATE_IMMEDIATE_DATA_SHIFT 3 709#define ISCSI_KWQE_CONN_UPDATE_IMMEDIATE_DATA_SHIFT 3
710#define ISCSI_KWQE_CONN_UPDATE_RESERVED1 (0xF<<4) 710#define ISCSI_KWQE_CONN_UPDATE_OOO_SUPPORT_MODE (0x3<<4)
711#define ISCSI_KWQE_CONN_UPDATE_RESERVED1_SHIFT 4 711#define ISCSI_KWQE_CONN_UPDATE_OOO_SUPPORT_MODE_SHIFT 4
712#define ISCSI_KWQE_CONN_UPDATE_RESERVED1 (0x3<<6)
713#define ISCSI_KWQE_CONN_UPDATE_RESERVED1_SHIFT 6
712#elif defined(__LITTLE_ENDIAN) 714#elif defined(__LITTLE_ENDIAN)
713 u8 conn_flags; 715 u8 conn_flags;
714#define ISCSI_KWQE_CONN_UPDATE_HEADER_DIGEST (0x1<<0) 716#define ISCSI_KWQE_CONN_UPDATE_HEADER_DIGEST (0x1<<0)
@@ -719,8 +721,10 @@ struct iscsi_kwqe_conn_update {
719#define ISCSI_KWQE_CONN_UPDATE_INITIAL_R2T_SHIFT 2 721#define ISCSI_KWQE_CONN_UPDATE_INITIAL_R2T_SHIFT 2
720#define ISCSI_KWQE_CONN_UPDATE_IMMEDIATE_DATA (0x1<<3) 722#define ISCSI_KWQE_CONN_UPDATE_IMMEDIATE_DATA (0x1<<3)
721#define ISCSI_KWQE_CONN_UPDATE_IMMEDIATE_DATA_SHIFT 3 723#define ISCSI_KWQE_CONN_UPDATE_IMMEDIATE_DATA_SHIFT 3
722#define ISCSI_KWQE_CONN_UPDATE_RESERVED1 (0xF<<4) 724#define ISCSI_KWQE_CONN_UPDATE_OOO_SUPPORT_MODE (0x3<<4)
723#define ISCSI_KWQE_CONN_UPDATE_RESERVED1_SHIFT 4 725#define ISCSI_KWQE_CONN_UPDATE_OOO_SUPPORT_MODE_SHIFT 4
726#define ISCSI_KWQE_CONN_UPDATE_RESERVED1 (0x3<<6)
727#define ISCSI_KWQE_CONN_UPDATE_RESERVED1_SHIFT 6
724 u8 reserved2; 728 u8 reserved2;
725 u8 max_outstanding_r2ts; 729 u8 max_outstanding_r2ts;
726 u8 session_error_recovery_level; 730 u8 session_error_recovery_level;
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-11 11:39:20 -0500