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authorAndrew Vasquez <andrew.vasquez@qlogic.com>2005-07-06 13:30:26 -0400
committerJames Bottomley <jejb@mulgrave.(none)>2005-07-14 10:54:46 -0400
commit3d71644cf952fd1157a13173237258422ba3c569 (patch)
tree1bae220781b973a9dca754a08aa7630e05ffc50e /drivers/scsi
parentac96202ba096f8fc1ccaf45a2f159a52639ece29 (diff)
[SCSI] qla2xxx: Add ISP24xx definitions.
Add ISP24xx definitions. Add requisite structure definitions and #define's for ISP24xx support. Also drop volatile modifiers from device_reg_* register layouts as the members are never really accessed, only their offsets within the layout are used during reads and writes. Signed-off-by: Andrew Vasquez <andrew.vasquez@qlogic.com> Signed-off-by: James Bottomley <James.Bottomley@SteelEye.com>
Diffstat (limited to 'drivers/scsi')
-rw-r--r--drivers/scsi/qla2xxx/qla_dbg.c6
-rw-r--r--drivers/scsi/qla2xxx/qla_def.h278
-rw-r--r--drivers/scsi/qla2xxx/qla_fw.h1076
-rw-r--r--drivers/scsi/qla2xxx/qla_init.c49
-rw-r--r--drivers/scsi/qla2xxx/qla_inline.h11
-rw-r--r--drivers/scsi/qla2xxx/qla_iocb.c8
-rw-r--r--drivers/scsi/qla2xxx/qla_isr.c14
-rw-r--r--drivers/scsi/qla2xxx/qla_mbx.c2
-rw-r--r--drivers/scsi/qla2xxx/qla_os.c8
-rw-r--r--drivers/scsi/qla2xxx/qla_rscn.c2
-rw-r--r--drivers/scsi/qla2xxx/qla_sup.c16
11 files changed, 1318 insertions, 152 deletions
diff --git a/drivers/scsi/qla2xxx/qla_dbg.c b/drivers/scsi/qla2xxx/qla_dbg.c
index 20f4ed1cd7ff..8e93dd7065a1 100644
--- a/drivers/scsi/qla2xxx/qla_dbg.c
+++ b/drivers/scsi/qla2xxx/qla_dbg.c
@@ -36,7 +36,7 @@ qla2300_fw_dump(scsi_qla_host_t *ha, int hardware_locked)
36 uint16_t mb0, mb2; 36 uint16_t mb0, mb2;
37 37
38 uint32_t stat; 38 uint32_t stat;
39 device_reg_t __iomem *reg = ha->iobase; 39 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
40 uint16_t __iomem *dmp_reg; 40 uint16_t __iomem *dmp_reg;
41 unsigned long flags; 41 unsigned long flags;
42 struct qla2300_fw_dump *fw; 42 struct qla2300_fw_dump *fw;
@@ -587,7 +587,7 @@ qla2100_fw_dump(scsi_qla_host_t *ha, int hardware_locked)
587 uint32_t cnt, timer; 587 uint32_t cnt, timer;
588 uint16_t risc_address; 588 uint16_t risc_address;
589 uint16_t mb0, mb2; 589 uint16_t mb0, mb2;
590 device_reg_t __iomem *reg = ha->iobase; 590 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
591 uint16_t __iomem *dmp_reg; 591 uint16_t __iomem *dmp_reg;
592 unsigned long flags; 592 unsigned long flags;
593 struct qla2100_fw_dump *fw; 593 struct qla2100_fw_dump *fw;
@@ -984,7 +984,7 @@ qla_uprintf(char **uiter, char *fmt, ...)
984void 984void
985qla2x00_dump_regs(scsi_qla_host_t *ha) 985qla2x00_dump_regs(scsi_qla_host_t *ha)
986{ 986{
987 device_reg_t __iomem *reg = ha->iobase; 987 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
988 988
989 printk("Mailbox registers:\n"); 989 printk("Mailbox registers:\n");
990 printk("scsi(%ld): mbox 0 0x%04x \n", 990 printk("scsi(%ld): mbox 0 0x%04x \n",
diff --git a/drivers/scsi/qla2xxx/qla_def.h b/drivers/scsi/qla2xxx/qla_def.h
index 13901c24b9a0..03074e52160f 100644
--- a/drivers/scsi/qla2xxx/qla_def.h
+++ b/drivers/scsi/qla2xxx/qla_def.h
@@ -75,9 +75,28 @@
75#define IS_QLA6322(ha) 0 75#define IS_QLA6322(ha) 0
76#endif 76#endif
77 77
78#if defined(CONFIG_SCSI_QLA24XX) || defined(CONFIG_SCSI_QLA24XX_MODULE)
79#define IS_QLA2422(ha) ((ha)->pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2422)
80#define IS_QLA2432(ha) ((ha)->pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2432)
81#else
82#define IS_QLA2422(ha) 0
83#define IS_QLA2432(ha) 0
84#endif
85
86#if defined(CONFIG_SCSI_QLA25XX) || defined(CONFIG_SCSI_QLA25XX_MODULE)
87#define IS_QLA2512(ha) ((ha)->pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2512)
88#define IS_QLA2522(ha) ((ha)->pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2522)
89#else
90#define IS_QLA2512(ha) 0
91#define IS_QLA2522(ha) 0
92#endif
93
78#define IS_QLA23XX(ha) (IS_QLA2300(ha) || IS_QLA2312(ha) || IS_QLA2322(ha) || \ 94#define IS_QLA23XX(ha) (IS_QLA2300(ha) || IS_QLA2312(ha) || IS_QLA2322(ha) || \
79 IS_QLA6312(ha) || IS_QLA6322(ha)) 95 IS_QLA6312(ha) || IS_QLA6322(ha))
80 96
97#define IS_QLA24XX(ha) (IS_QLA2422(ha) || IS_QLA2432(ha))
98#define IS_QLA25XX(ha) (IS_QLA2512(ha) || IS_QLA2522(ha))
99
81/* 100/*
82 * Only non-ISP2[12]00 have extended addressing support in the firmware. 101 * Only non-ISP2[12]00 have extended addressing support in the firmware.
83 */ 102 */
@@ -191,10 +210,18 @@
191#define MANAGEMENT_SERVER 0xfe 210#define MANAGEMENT_SERVER 0xfe
192#define BROADCAST 0xff 211#define BROADCAST 0xff
193 212
194#define RESERVED_LOOP_ID(x) ((x > LAST_LOCAL_LOOP_ID && \ 213/*
195 x < SNS_FIRST_LOOP_ID) || \ 214 * There is no correspondence between an N-PORT id and an AL_PA. Therefore the
196 x == MANAGEMENT_SERVER || \ 215 * valid range of an N-PORT id is 0 through 0x7ef.
197 x == BROADCAST) 216 */
217#define NPH_LAST_HANDLE 0x7ef
218#define NPH_SNS 0x7fc /* FFFFFC */
219#define NPH_FABRIC_CONTROLLER 0x7fd /* FFFFFD */
220#define NPH_F_PORT 0x7fe /* FFFFFE */
221#define NPH_IP_BROADCAST 0x7ff /* FFFFFF */
222
223#define MAX_CMDSZ 16 /* SCSI maximum CDB size. */
224#include "qla_fw.h"
198 225
199/* 226/*
200 * Timeout timer counts in seconds 227 * Timeout timer counts in seconds
@@ -211,6 +238,7 @@
211#define REQUEST_ENTRY_CNT_2100 128 /* Number of request entries. */ 238#define REQUEST_ENTRY_CNT_2100 128 /* Number of request entries. */
212#define REQUEST_ENTRY_CNT_2200 2048 /* Number of request entries. */ 239#define REQUEST_ENTRY_CNT_2200 2048 /* Number of request entries. */
213#define REQUEST_ENTRY_CNT_2XXX_EXT_MEM 4096 /* Number of request entries. */ 240#define REQUEST_ENTRY_CNT_2XXX_EXT_MEM 4096 /* Number of request entries. */
241#define REQUEST_ENTRY_CNT_24XX 4096 /* Number of request entries. */
214#define RESPONSE_ENTRY_CNT_2100 64 /* Number of response entries.*/ 242#define RESPONSE_ENTRY_CNT_2100 64 /* Number of response entries.*/
215#define RESPONSE_ENTRY_CNT_2300 512 /* Number of response entries.*/ 243#define RESPONSE_ENTRY_CNT_2300 512 /* Number of response entries.*/
216 244
@@ -279,24 +307,24 @@ typedef struct srb {
279/* 307/*
280 * ISP I/O Register Set structure definitions. 308 * ISP I/O Register Set structure definitions.
281 */ 309 */
282typedef volatile struct { 310struct device_reg_2xxx {
283 volatile uint16_t flash_address; /* Flash BIOS address */ 311 uint16_t flash_address; /* Flash BIOS address */
284 volatile uint16_t flash_data; /* Flash BIOS data */ 312 uint16_t flash_data; /* Flash BIOS data */
285 uint16_t unused_1[1]; /* Gap */ 313 uint16_t unused_1[1]; /* Gap */
286 volatile uint16_t ctrl_status; /* Control/Status */ 314 uint16_t ctrl_status; /* Control/Status */
287#define CSR_FLASH_64K_BANK BIT_3 /* Flash upper 64K bank select */ 315#define CSR_FLASH_64K_BANK BIT_3 /* Flash upper 64K bank select */
288#define CSR_FLASH_ENABLE BIT_1 /* Flash BIOS Read/Write enable */ 316#define CSR_FLASH_ENABLE BIT_1 /* Flash BIOS Read/Write enable */
289#define CSR_ISP_SOFT_RESET BIT_0 /* ISP soft reset */ 317#define CSR_ISP_SOFT_RESET BIT_0 /* ISP soft reset */
290 318
291 volatile uint16_t ictrl; /* Interrupt control */ 319 uint16_t ictrl; /* Interrupt control */
292#define ICR_EN_INT BIT_15 /* ISP enable interrupts. */ 320#define ICR_EN_INT BIT_15 /* ISP enable interrupts. */
293#define ICR_EN_RISC BIT_3 /* ISP enable RISC interrupts. */ 321#define ICR_EN_RISC BIT_3 /* ISP enable RISC interrupts. */
294 322
295 volatile uint16_t istatus; /* Interrupt status */ 323 uint16_t istatus; /* Interrupt status */
296#define ISR_RISC_INT BIT_3 /* RISC interrupt */ 324#define ISR_RISC_INT BIT_3 /* RISC interrupt */
297 325
298 volatile uint16_t semaphore; /* Semaphore */ 326 uint16_t semaphore; /* Semaphore */
299 volatile uint16_t nvram; /* NVRAM register. */ 327 uint16_t nvram; /* NVRAM register. */
300#define NVR_DESELECT 0 328#define NVR_DESELECT 0
301#define NVR_BUSY BIT_15 329#define NVR_BUSY BIT_15
302#define NVR_WRT_ENABLE BIT_14 /* Write enable */ 330#define NVR_WRT_ENABLE BIT_14 /* Write enable */
@@ -308,78 +336,78 @@ typedef volatile struct {
308 336
309 union { 337 union {
310 struct { 338 struct {
311 volatile uint16_t mailbox0; 339 uint16_t mailbox0;
312 volatile uint16_t mailbox1; 340 uint16_t mailbox1;
313 volatile uint16_t mailbox2; 341 uint16_t mailbox2;
314 volatile uint16_t mailbox3; 342 uint16_t mailbox3;
315 volatile uint16_t mailbox4; 343 uint16_t mailbox4;
316 volatile uint16_t mailbox5; 344 uint16_t mailbox5;
317 volatile uint16_t mailbox6; 345 uint16_t mailbox6;
318 volatile uint16_t mailbox7; 346 uint16_t mailbox7;
319 uint16_t unused_2[59]; /* Gap */ 347 uint16_t unused_2[59]; /* Gap */
320 } __attribute__((packed)) isp2100; 348 } __attribute__((packed)) isp2100;
321 struct { 349 struct {
322 /* Request Queue */ 350 /* Request Queue */
323 volatile uint16_t req_q_in; /* In-Pointer */ 351 uint16_t req_q_in; /* In-Pointer */
324 volatile uint16_t req_q_out; /* Out-Pointer */ 352 uint16_t req_q_out; /* Out-Pointer */
325 /* Response Queue */ 353 /* Response Queue */
326 volatile uint16_t rsp_q_in; /* In-Pointer */ 354 uint16_t rsp_q_in; /* In-Pointer */
327 volatile uint16_t rsp_q_out; /* Out-Pointer */ 355 uint16_t rsp_q_out; /* Out-Pointer */
328 356
329 /* RISC to Host Status */ 357 /* RISC to Host Status */
330 volatile uint32_t host_status; 358 uint32_t host_status;
331#define HSR_RISC_INT BIT_15 /* RISC interrupt */ 359#define HSR_RISC_INT BIT_15 /* RISC interrupt */
332#define HSR_RISC_PAUSED BIT_8 /* RISC Paused */ 360#define HSR_RISC_PAUSED BIT_8 /* RISC Paused */
333 361
334 /* Host to Host Semaphore */ 362 /* Host to Host Semaphore */
335 volatile uint16_t host_semaphore; 363 uint16_t host_semaphore;
336 uint16_t unused_3[17]; /* Gap */ 364 uint16_t unused_3[17]; /* Gap */
337 volatile uint16_t mailbox0; 365 uint16_t mailbox0;
338 volatile uint16_t mailbox1; 366 uint16_t mailbox1;
339 volatile uint16_t mailbox2; 367 uint16_t mailbox2;
340 volatile uint16_t mailbox3; 368 uint16_t mailbox3;
341 volatile uint16_t mailbox4; 369 uint16_t mailbox4;
342 volatile uint16_t mailbox5; 370 uint16_t mailbox5;
343 volatile uint16_t mailbox6; 371 uint16_t mailbox6;
344 volatile uint16_t mailbox7; 372 uint16_t mailbox7;
345 volatile uint16_t mailbox8; 373 uint16_t mailbox8;
346 volatile uint16_t mailbox9; 374 uint16_t mailbox9;
347 volatile uint16_t mailbox10; 375 uint16_t mailbox10;
348 volatile uint16_t mailbox11; 376 uint16_t mailbox11;
349 volatile uint16_t mailbox12; 377 uint16_t mailbox12;
350 volatile uint16_t mailbox13; 378 uint16_t mailbox13;
351 volatile uint16_t mailbox14; 379 uint16_t mailbox14;
352 volatile uint16_t mailbox15; 380 uint16_t mailbox15;
353 volatile uint16_t mailbox16; 381 uint16_t mailbox16;
354 volatile uint16_t mailbox17; 382 uint16_t mailbox17;
355 volatile uint16_t mailbox18; 383 uint16_t mailbox18;
356 volatile uint16_t mailbox19; 384 uint16_t mailbox19;
357 volatile uint16_t mailbox20; 385 uint16_t mailbox20;
358 volatile uint16_t mailbox21; 386 uint16_t mailbox21;
359 volatile uint16_t mailbox22; 387 uint16_t mailbox22;
360 volatile uint16_t mailbox23; 388 uint16_t mailbox23;
361 volatile uint16_t mailbox24; 389 uint16_t mailbox24;
362 volatile uint16_t mailbox25; 390 uint16_t mailbox25;
363 volatile uint16_t mailbox26; 391 uint16_t mailbox26;
364 volatile uint16_t mailbox27; 392 uint16_t mailbox27;
365 volatile uint16_t mailbox28; 393 uint16_t mailbox28;
366 volatile uint16_t mailbox29; 394 uint16_t mailbox29;
367 volatile uint16_t mailbox30; 395 uint16_t mailbox30;
368 volatile uint16_t mailbox31; 396 uint16_t mailbox31;
369 volatile uint16_t fb_cmd; 397 uint16_t fb_cmd;
370 uint16_t unused_4[10]; /* Gap */ 398 uint16_t unused_4[10]; /* Gap */
371 } __attribute__((packed)) isp2300; 399 } __attribute__((packed)) isp2300;
372 } u; 400 } u;
373 401
374 volatile uint16_t fpm_diag_config; 402 uint16_t fpm_diag_config;
375 uint16_t unused_5[0x6]; /* Gap */ 403 uint16_t unused_5[0x6]; /* Gap */
376 volatile uint16_t pcr; /* Processor Control Register. */ 404 uint16_t pcr; /* Processor Control Register. */
377 uint16_t unused_6[0x5]; /* Gap */ 405 uint16_t unused_6[0x5]; /* Gap */
378 volatile uint16_t mctr; /* Memory Configuration and Timing. */ 406 uint16_t mctr; /* Memory Configuration and Timing. */
379 uint16_t unused_7[0x3]; /* Gap */ 407 uint16_t unused_7[0x3]; /* Gap */
380 volatile uint16_t fb_cmd_2100; /* Unused on 23XX */ 408 uint16_t fb_cmd_2100; /* Unused on 23XX */
381 uint16_t unused_8[0x3]; /* Gap */ 409 uint16_t unused_8[0x3]; /* Gap */
382 volatile uint16_t hccr; /* Host command & control register. */ 410 uint16_t hccr; /* Host command & control register. */
383#define HCCR_HOST_INT BIT_7 /* Host interrupt bit */ 411#define HCCR_HOST_INT BIT_7 /* Host interrupt bit */
384#define HCCR_RISC_PAUSE BIT_5 /* Pause mode bit */ 412#define HCCR_RISC_PAUSE BIT_5 /* Pause mode bit */
385 /* HCCR commands */ 413 /* HCCR commands */
@@ -393,8 +421,8 @@ typedef volatile struct {
393#define HCCR_ENABLE_PARITY 0xA000 /* Enable PARITY interrupt */ 421#define HCCR_ENABLE_PARITY 0xA000 /* Enable PARITY interrupt */
394 422
395 uint16_t unused_9[5]; /* Gap */ 423 uint16_t unused_9[5]; /* Gap */
396 volatile uint16_t gpiod; /* GPIO Data register. */ 424 uint16_t gpiod; /* GPIO Data register. */
397 volatile uint16_t gpioe; /* GPIO Enable register. */ 425 uint16_t gpioe; /* GPIO Enable register. */
398#define GPIO_LED_MASK 0x00C0 426#define GPIO_LED_MASK 0x00C0
399#define GPIO_LED_GREEN_OFF_AMBER_OFF 0x0000 427#define GPIO_LED_GREEN_OFF_AMBER_OFF 0x0000
400#define GPIO_LED_GREEN_ON_AMBER_OFF 0x0040 428#define GPIO_LED_GREEN_ON_AMBER_OFF 0x0040
@@ -403,25 +431,32 @@ typedef volatile struct {
403 431
404 union { 432 union {
405 struct { 433 struct {
406 uint16_t unused_10[8]; /* Gap */ 434 uint16_t unused_10[8]; /* Gap */
407 volatile uint16_t mailbox8; 435 uint16_t mailbox8;
408 volatile uint16_t mailbox9; 436 uint16_t mailbox9;
409 volatile uint16_t mailbox10; 437 uint16_t mailbox10;
410 volatile uint16_t mailbox11; 438 uint16_t mailbox11;
411 volatile uint16_t mailbox12; 439 uint16_t mailbox12;
412 volatile uint16_t mailbox13; 440 uint16_t mailbox13;
413 volatile uint16_t mailbox14; 441 uint16_t mailbox14;
414 volatile uint16_t mailbox15; 442 uint16_t mailbox15;
415 volatile uint16_t mailbox16; 443 uint16_t mailbox16;
416 volatile uint16_t mailbox17; 444 uint16_t mailbox17;
417 volatile uint16_t mailbox18; 445 uint16_t mailbox18;
418 volatile uint16_t mailbox19; 446 uint16_t mailbox19;
419 volatile uint16_t mailbox20; 447 uint16_t mailbox20;
420 volatile uint16_t mailbox21; 448 uint16_t mailbox21;
421 volatile uint16_t mailbox22; 449 uint16_t mailbox22;
422 volatile uint16_t mailbox23; /* Also probe reg. */ 450 uint16_t mailbox23; /* Also probe reg. */
423 } __attribute__((packed)) isp2200; 451 } __attribute__((packed)) isp2200;
424 } u_end; 452 } u_end;
453};
454
455typedef struct {
456 union {
457 struct device_reg_2xxx isp;
458 struct device_reg_24xx isp24;
459 };
425} device_reg_t; 460} device_reg_t;
426 461
427#define ISP_REQ_Q_IN(ha, reg) \ 462#define ISP_REQ_Q_IN(ha, reg) \
@@ -504,6 +539,8 @@ typedef struct {
504#define MBS_LOOP_ID_USED 0x4008 539#define MBS_LOOP_ID_USED 0x4008
505#define MBS_ALL_IDS_IN_USE 0x4009 540#define MBS_ALL_IDS_IN_USE 0x4009
506#define MBS_NOT_LOGGED_IN 0x400A 541#define MBS_NOT_LOGGED_IN 0x400A
542#define MBS_LINK_DOWN_ERROR 0x400B
543#define MBS_DIAG_ECHO_TEST_ERROR 0x400C
507 544
508/* 545/*
509 * ISP mailbox asynchronous event status codes 546 * ISP mailbox asynchronous event status codes
@@ -555,7 +592,7 @@ typedef struct {
555#define FO1_CTIO_RETRY BIT_3 592#define FO1_CTIO_RETRY BIT_3
556#define FO1_DISABLE_LIP_F7_SW BIT_4 593#define FO1_DISABLE_LIP_F7_SW BIT_4
557#define FO1_DISABLE_100MS_LOS_WAIT BIT_5 594#define FO1_DISABLE_100MS_LOS_WAIT BIT_5
558#define FO1_DISABLE_GPIO6_7 BIT_6 595#define FO1_DISABLE_GPIO6_7 BIT_6 /* LED bits */
559#define FO1_AE_ON_LOOP_INIT_ERR BIT_7 596#define FO1_AE_ON_LOOP_INIT_ERR BIT_7
560#define FO1_SET_EMPHASIS_SWING BIT_8 597#define FO1_SET_EMPHASIS_SWING BIT_8
561#define FO1_AE_AUTO_BYPASS BIT_9 598#define FO1_AE_AUTO_BYPASS BIT_9
@@ -570,6 +607,15 @@ typedef struct {
570#define FO3_ENABLE_EMERG_IOCB BIT_0 607#define FO3_ENABLE_EMERG_IOCB BIT_0
571#define FO3_AE_RND_ERROR BIT_1 608#define FO3_AE_RND_ERROR BIT_1
572 609
610/* 24XX additional firmware options */
611#define ADD_FO_COUNT 3
612#define ADD_FO1_DISABLE_GPIO_LED_CTRL BIT_6 /* LED bits */
613#define ADD_FO1_ENABLE_PUREX_IOCB BIT_10
614
615#define ADD_FO2_ENABLE_SEL_CLS2 BIT_5
616
617#define ADD_FO3_NO_ABT_ON_LINK_DOWN BIT_14
618
573/* 619/*
574 * ISP mailbox commands 620 * ISP mailbox commands
575 */ 621 */
@@ -638,6 +684,22 @@ typedef struct {
638#define MBC_SEND_LFA_COMMAND 0x7D /* Send Loop Fabric Address */ 684#define MBC_SEND_LFA_COMMAND 0x7D /* Send Loop Fabric Address */
639#define MBC_LUN_RESET 0x7E /* Send LUN reset */ 685#define MBC_LUN_RESET 0x7E /* Send LUN reset */
640 686
687/*
688 * ISP24xx mailbox commands
689 */
690#define MBC_SERDES_PARAMS 0x10 /* Serdes Tx Parameters. */
691#define MBC_GET_IOCB_STATUS 0x12 /* Get IOCB status command. */
692#define MBC_GET_TIMEOUT_PARAMS 0x22 /* Get FW timeouts. */
693#define MBC_GEN_SYSTEM_ERROR 0x2a /* Generate System Error. */
694#define MBC_SET_TIMEOUT_PARAMS 0x32 /* Set FW timeouts. */
695#define MBC_MID_INITIALIZE_FIRMWARE 0x48 /* MID Initialize firmware. */
696#define MBC_MID_GET_VP_DATABASE 0x49 /* MID Get VP Database. */
697#define MBC_MID_GET_VP_ENTRY 0x4a /* MID Get VP Entry. */
698#define MBC_HOST_MEMORY_COPY 0x53 /* Host Memory Copy. */
699#define MBC_SEND_RNFT_ELS 0x5e /* Send RNFT ELS request */
700#define MBC_GET_LINK_PRIV_STATS 0x6d /* Get link & private data. */
701#define MBC_SET_VENDOR_ID 0x76 /* Set Vendor ID. */
702
641/* Firmware return data sizes */ 703/* Firmware return data sizes */
642#define FCAL_MAP_SIZE 128 704#define FCAL_MAP_SIZE 128
643 705
@@ -867,6 +929,9 @@ typedef struct {
867/* 929/*
868 * Get Link Status mailbox command return buffer. 930 * Get Link Status mailbox command return buffer.
869 */ 931 */
932#define GLSO_SEND_RPS BIT_0
933#define GLSO_USE_DID BIT_3
934
870typedef struct { 935typedef struct {
871 uint32_t link_fail_cnt; 936 uint32_t link_fail_cnt;
872 uint32_t loss_sync_cnt; 937 uint32_t loss_sync_cnt;
@@ -1161,7 +1226,6 @@ do { \
1161 * ISP queue - command entry structure definition. 1226 * ISP queue - command entry structure definition.
1162 */ 1227 */
1163#define COMMAND_TYPE 0x11 /* Command entry */ 1228#define COMMAND_TYPE 0x11 /* Command entry */
1164#define MAX_CMDSZ 16 /* SCSI maximum CDB size. */
1165typedef struct { 1229typedef struct {
1166 uint8_t entry_type; /* Entry type. */ 1230 uint8_t entry_type; /* Entry type. */
1167 uint8_t entry_count; /* Entry count. */ 1231 uint8_t entry_count; /* Entry count. */
@@ -1284,11 +1348,16 @@ typedef struct {
1284/* 1348/*
1285 * Status entry entry status 1349 * Status entry entry status
1286 */ 1350 */
1351#define RF_RQ_DMA_ERROR BIT_6 /* Request Queue DMA error. */
1287#define RF_INV_E_ORDER BIT_5 /* Invalid entry order. */ 1352#define RF_INV_E_ORDER BIT_5 /* Invalid entry order. */
1288#define RF_INV_E_COUNT BIT_4 /* Invalid entry count. */ 1353#define RF_INV_E_COUNT BIT_4 /* Invalid entry count. */
1289#define RF_INV_E_PARAM BIT_3 /* Invalid entry parameter. */ 1354#define RF_INV_E_PARAM BIT_3 /* Invalid entry parameter. */
1290#define RF_INV_E_TYPE BIT_2 /* Invalid entry type. */ 1355#define RF_INV_E_TYPE BIT_2 /* Invalid entry type. */
1291#define RF_BUSY BIT_1 /* Busy */ 1356#define RF_BUSY BIT_1 /* Busy */
1357#define RF_MASK (RF_RQ_DMA_ERROR | RF_INV_E_ORDER | RF_INV_E_COUNT | \
1358 RF_INV_E_PARAM | RF_INV_E_TYPE | RF_BUSY)
1359#define RF_MASK_24XX (RF_INV_E_ORDER | RF_INV_E_COUNT | RF_INV_E_PARAM | \
1360 RF_INV_E_TYPE)
1292 1361
1293/* 1362/*
1294 * Status entry SCSI status bit definitions. 1363 * Status entry SCSI status bit definitions.
@@ -1503,9 +1572,6 @@ typedef struct {
1503 port_id_t d_id; 1572 port_id_t d_id;
1504 uint8_t node_name[WWN_SIZE]; 1573 uint8_t node_name[WWN_SIZE];
1505 uint8_t port_name[WWN_SIZE]; 1574 uint8_t port_name[WWN_SIZE];
1506 uint32_t type;
1507#define SW_TYPE_IP BIT_1
1508#define SW_TYPE_SCSI BIT_0
1509} sw_info_t; 1575} sw_info_t;
1510 1576
1511/* 1577/*
@@ -1520,6 +1586,8 @@ typedef struct {
1520 union { 1586 union {
1521 cmd_a64_entry_t cmd; 1587 cmd_a64_entry_t cmd;
1522 sts_entry_t rsp; 1588 sts_entry_t rsp;
1589 struct cmd_type_7 cmd24;
1590 struct sts_entry_24xx rsp24;
1523 } p; 1591 } p;
1524 uint8_t inq[INQ_DATA_SIZE]; 1592 uint8_t inq[INQ_DATA_SIZE];
1525} inq_cmd_rsp_t; 1593} inq_cmd_rsp_t;
@@ -1555,10 +1623,13 @@ typedef struct {
1555 union { 1623 union {
1556 cmd_a64_entry_t cmd; 1624 cmd_a64_entry_t cmd;
1557 sts_entry_t rsp; 1625 sts_entry_t rsp;
1626 struct cmd_type_7 cmd24;
1627 struct sts_entry_24xx rsp24;
1558 } p; 1628 } p;
1559 rpt_lun_lst_t list; 1629 rpt_lun_lst_t list;
1560} rpt_lun_cmd_rsp_t; 1630} rpt_lun_cmd_rsp_t;
1561 1631
1632
1562/* 1633/*
1563 * Fibre channel port type. 1634 * Fibre channel port type.
1564 */ 1635 */
@@ -1646,6 +1717,7 @@ typedef struct fc_port {
1646#define FCF_FAILOVER_DISABLE BIT_22 1717#define FCF_FAILOVER_DISABLE BIT_22
1647#define FCF_DSXXX_DEVICE BIT_23 1718#define FCF_DSXXX_DEVICE BIT_23
1648#define FCF_AA_EVA_DEVICE BIT_24 1719#define FCF_AA_EVA_DEVICE BIT_24
1720#define FCF_AA_MSA_DEVICE BIT_25
1649 1721
1650/* No loop ID flag. */ 1722/* No loop ID flag. */
1651#define FC_NO_LOOP_ID 0x1000 1723#define FC_NO_LOOP_ID 0x1000
@@ -1917,6 +1989,7 @@ struct qla_board_info {
1917 1989
1918 char isp_name[8]; 1990 char isp_name[8];
1919 struct qla_fw_info *fw_info; 1991 struct qla_fw_info *fw_info;
1992 char *fw_fname;;
1920}; 1993};
1921 1994
1922/* Return data from MBC_GET_ID_LIST call. */ 1995/* Return data from MBC_GET_ID_LIST call. */
@@ -1926,6 +1999,7 @@ struct gid_list_info {
1926 uint8_t domain; 1999 uint8_t domain;
1927 uint8_t loop_id_2100; /* ISP2100/ISP2200 -- 4 bytes. */ 2000 uint8_t loop_id_2100; /* ISP2100/ISP2200 -- 4 bytes. */
1928 uint16_t loop_id; /* ISP23XX -- 6 bytes. */ 2001 uint16_t loop_id; /* ISP23XX -- 6 bytes. */
2002 uint16_t reserved_1; /* ISP24XX -- 8 bytes. */
1929}; 2003};
1930#define GID_LIST_SIZE (sizeof(struct gid_list_info) * MAX_FIBRE_DEVICES) 2004#define GID_LIST_SIZE (sizeof(struct gid_list_info) * MAX_FIBRE_DEVICES)
1931 2005
@@ -2000,6 +2074,8 @@ typedef struct scsi_qla_host {
2000 uint32_t enable_lip_full_login :1; 2074 uint32_t enable_lip_full_login :1;
2001 uint32_t enable_target_reset :1; 2075 uint32_t enable_target_reset :1;
2002 uint32_t enable_led_scheme :1; 2076 uint32_t enable_led_scheme :1;
2077 uint32_t msi_enabled :1;
2078 uint32_t msix_enabled :1;
2003 } flags; 2079 } flags;
2004 2080
2005 atomic_t loop_state; 2081 atomic_t loop_state;
@@ -2036,6 +2112,7 @@ typedef struct scsi_qla_host {
2036#define IODESC_PROCESS_NEEDED 22 /* IO descriptor processing needed */ 2112#define IODESC_PROCESS_NEEDED 22 /* IO descriptor processing needed */
2037#define IOCTL_ERROR_RECOVERY 23 2113#define IOCTL_ERROR_RECOVERY 23
2038#define LOOP_RESET_NEEDED 24 2114#define LOOP_RESET_NEEDED 24
2115#define BEACON_BLINK_NEEDED 25
2039 2116
2040 uint32_t device_flags; 2117 uint32_t device_flags;
2041#define DFLG_LOCAL_DEVICES BIT_0 2118#define DFLG_LOCAL_DEVICES BIT_0
@@ -2119,6 +2196,7 @@ typedef struct scsi_qla_host {
2119 uint8_t serial2; 2196 uint8_t serial2;
2120 2197
2121 /* NVRAM configuration data */ 2198 /* NVRAM configuration data */
2199 uint16_t nvram_size;
2122 uint16_t nvram_base; 2200 uint16_t nvram_base;
2123 2201
2124 uint16_t loop_reset_delay; 2202 uint16_t loop_reset_delay;
@@ -2179,7 +2257,8 @@ typedef struct scsi_qla_host {
2179 struct dma_pool *s_dma_pool; 2257 struct dma_pool *s_dma_pool;
2180 2258
2181 dma_addr_t init_cb_dma; 2259 dma_addr_t init_cb_dma;
2182 init_cb_t *init_cb; 2260 init_cb_t *init_cb;
2261 int init_cb_size;
2183 2262
2184 dma_addr_t iodesc_pd_dma; 2263 dma_addr_t iodesc_pd_dma;
2185 port_database_t *iodesc_pd; 2264 port_database_t *iodesc_pd;
@@ -2220,6 +2299,7 @@ typedef struct scsi_qla_host {
2220 2299
2221 uint16_t fw_options[16]; /* slots: 1,2,3,10,11 */ 2300 uint16_t fw_options[16]; /* slots: 1,2,3,10,11 */
2222 uint8_t fw_seriallink_options[4]; 2301 uint8_t fw_seriallink_options[4];
2302 uint16_t fw_seriallink_options24[4];
2223 2303
2224 /* Firmware dump information. */ 2304 /* Firmware dump information. */
2225 void *fw_dump; 2305 void *fw_dump;
@@ -2228,8 +2308,12 @@ typedef struct scsi_qla_host {
2228 char *fw_dump_buffer; 2308 char *fw_dump_buffer;
2229 int fw_dump_buffer_len; 2309 int fw_dump_buffer_len;
2230 2310
2311 int fw_dumped;
2312 void *fw_dump24;
2313 int fw_dump24_len;
2314
2231 uint8_t host_str[16]; 2315 uint8_t host_str[16];
2232 uint16_t pci_attr; 2316 uint32_t pci_attr;
2233 2317
2234 uint16_t product_id[4]; 2318 uint16_t product_id[4];
2235 2319
@@ -2237,8 +2321,8 @@ typedef struct scsi_qla_host {
2237#define BINZERO "\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0" 2321#define BINZERO "\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0"
2238 char *model_desc; 2322 char *model_desc;
2239 2323
2240 uint8_t node_name[WWN_SIZE]; 2324 uint8_t *node_name;
2241 uint8_t nvram_version; 2325 uint8_t *port_name;
2242 uint32_t isp_abort_cnt; 2326 uint32_t isp_abort_cnt;
2243 2327
2244 /* Needed for BEACON */ 2328 /* Needed for BEACON */
diff --git a/drivers/scsi/qla2xxx/qla_fw.h b/drivers/scsi/qla2xxx/qla_fw.h
new file mode 100644
index 000000000000..694d09f3a43b
--- /dev/null
+++ b/drivers/scsi/qla2xxx/qla_fw.h
@@ -0,0 +1,1076 @@
1
2/********************************************************************************
3* QLOGIC LINUX SOFTWARE
4*
5* QLogic ISP2x00 device driver for Linux 2.6.x
6* Copyright (C) 2003-2004 QLogic Corporation
7* (www.qlogic.com)
8*
9* This program is free software; you can redistribute it and/or modify it
10* under the terms of the GNU General Public License as published by the
11* Free Software Foundation; either version 2, or (at your option) any
12* later version.
13*
14* This program is distributed in the hope that it will be useful, but
15* WITHOUT ANY WARRANTY; without even the implied warranty of
16* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
17* General Public License for more details.
18**
19******************************************************************************/
20
21#ifndef __QLA_FW_H
22#define __QLA_FW_H
23
24// ISP24xx
25
26#define RISC_SADDRESS 0x100000
27#define MBS_CHECKSUM_ERROR 0x4010
28
29/*
30 * Firmware Options.
31 */
32#define FO1_ENABLE_PUREX BIT_10
33#define FO1_DISABLE_LED_CTRL BIT_6
34#define FO2_ENABLE_SEL_CLASS2 BIT_5
35#define FO3_NO_ABTS_ON_LINKDOWN BIT_14
36
37/*
38 * Port Database structure definition for ISP 24xx.
39 */
40#define PDO_FORCE_ADISC BIT_1
41#define PDO_FORCE_PLOGI BIT_0
42
43
44#define PORT_DATABASE_24XX_SIZE 64
45struct port_database_24xx {
46 uint16_t flags;
47#define PDF_TASK_RETRY_ID BIT_14
48#define PDF_FC_TAPE BIT_7
49#define PDF_ACK0_CAPABLE BIT_6
50#define PDF_FCP2_CONF BIT_5
51#define PDF_CLASS_2 BIT_4
52#define PDF_HARD_ADDR BIT_1
53
54 uint8_t current_login_state;
55 uint8_t last_login_state;
56#define PDS_PLOGI_PENDING 0x03
57#define PDS_PLOGI_COMPLETE 0x04
58#define PDS_PRLI_PENDING 0x05
59#define PDS_PRLI_COMPLETE 0x06
60#define PDS_PORT_UNAVAILABLE 0x07
61#define PDS_PRLO_PENDING 0x09
62#define PDS_LOGO_PENDING 0x11
63//FIXME
64#define PDS_PRLI2_PENDING 0x12
65
66 uint8_t hard_address[3];
67 uint8_t reserved_1;
68
69 uint8_t port_id[3];
70 uint8_t sequence_id;
71
72 uint16_t port_timer;
73
74 uint16_t nport_handle; /* N_PORT handle. */
75
76 uint16_t receive_data_size;
77 uint16_t reserved_2;
78
79 uint8_t prli_svc_param_word_0[2]; /* Big endian */
80 /* Bits 15-0 of word 0 */
81 uint8_t prli_svc_param_word_3[2]; /* Big endian */
82 /* Bits 15-0 of word 3 */
83
84 uint8_t port_name[WWN_SIZE];
85 uint8_t node_name[WWN_SIZE];
86
87 uint8_t reserved_3[24];
88};
89
90struct nvram_24xx {
91 /* NVRAM header. */
92 uint8_t id[4];
93 uint16_t nvram_version;
94 uint16_t reserved_0;
95
96 /* Firmware Initialization Control Block. */
97 uint16_t version;
98 uint16_t reserved_1;
99 uint16_t frame_payload_size;
100 uint16_t execution_throttle;
101 uint16_t exchange_count;
102 uint16_t hard_address;
103
104 uint8_t port_name[WWN_SIZE];
105 uint8_t node_name[WWN_SIZE];
106
107 uint16_t login_retry_count;
108 uint16_t link_down_on_nos;
109 uint16_t interrupt_delay_timer;
110 uint16_t login_timeout;
111
112 uint32_t firmware_options_1;
113 uint32_t firmware_options_2;
114 uint32_t firmware_options_3;
115
116 /* Offset 56. */
117
118 /*
119 * BIT 0 = Control Enable
120 * BIT 1-15 =
121 *
122 * BIT 0-7 = Reserved
123 * BIT 8-10 = Output Swing 1G
124 * BIT 11-13 = Output Emphasis 1G
125 * BIT 14-15 = Reserved
126 *
127 * BIT 0-7 = Reserved
128 * BIT 8-10 = Output Swing 2G
129 * BIT 11-13 = Output Emphasis 2G
130 * BIT 14-15 = Reserved
131 *
132 * BIT 0-7 = Reserved
133 * BIT 8-10 = Output Swing 4G
134 * BIT 11-13 = Output Emphasis 4G
135 * BIT 14-15 = Reserved
136 */
137 uint16_t seriallink_options[4];
138
139 uint16_t reserved_2[16];
140
141 /* Offset 96. */
142 uint16_t reserved_3[16];
143
144 /* PCIe table entries. */
145 uint16_t reserved_4[16];
146
147 /* Offset 160. */
148 uint16_t reserved_5[16];
149
150 /* Offset 192. */
151 uint16_t reserved_6[16];
152
153 /* Offset 224. */
154 uint16_t reserved_7[16];
155
156 /*
157 * BIT 0 = Enable spinup delay
158 * BIT 1 = Disable BIOS
159 * BIT 2 = Enable Memory Map BIOS
160 * BIT 3 = Enable Selectable Boot
161 * BIT 4 = Disable RISC code load
162 * BIT 5 =
163 * BIT 6 =
164 * BIT 7 =
165 *
166 * BIT 8 =
167 * BIT 9 =
168 * BIT 10 = Enable lip full login
169 * BIT 11 = Enable target reset
170 * BIT 12 =
171 * BIT 13 =
172 * BIT 14 =
173 * BIT 15 = Enable alternate WWN
174 *
175 * BIT 16-31 =
176 */
177 uint32_t host_p;
178
179 uint8_t alternate_port_name[WWN_SIZE];
180 uint8_t alternate_node_name[WWN_SIZE];
181
182 uint8_t boot_port_name[WWN_SIZE];
183 uint16_t boot_lun_number;
184 uint16_t reserved_8;
185
186 uint8_t alt1_boot_port_name[WWN_SIZE];
187 uint16_t alt1_boot_lun_number;
188 uint16_t reserved_9;
189
190 uint8_t alt2_boot_port_name[WWN_SIZE];
191 uint16_t alt2_boot_lun_number;
192 uint16_t reserved_10;
193
194 uint8_t alt3_boot_port_name[WWN_SIZE];
195 uint16_t alt3_boot_lun_number;
196 uint16_t reserved_11;
197
198 /*
199 * BIT 0 = Selective Login
200 * BIT 1 = Alt-Boot Enable
201 * BIT 2 = Reserved
202 * BIT 3 = Boot Order List
203 * BIT 4 = Reserved
204 * BIT 5 = Selective LUN
205 * BIT 6 = Reserved
206 * BIT 7-31 =
207 */
208 uint32_t efi_parameters;
209
210 uint8_t reset_delay;
211 uint8_t reserved_12;
212 uint16_t reserved_13;
213
214 uint16_t boot_id_number;
215 uint16_t reserved_14;
216
217 uint16_t max_luns_per_target;
218 uint16_t reserved_15;
219
220 uint16_t port_down_retry_count;
221 uint16_t link_down_timeout;
222
223 /* FCode parameters. */
224 uint16_t fcode_parameter;
225
226 uint16_t reserved_16[3];
227
228 /* Offset 352. */
229 uint8_t prev_drv_ver_major;
230 uint8_t prev_drv_ver_submajob;
231 uint8_t prev_drv_ver_minor;
232 uint8_t prev_drv_ver_subminor;
233
234 uint16_t prev_bios_ver_major;
235 uint16_t prev_bios_ver_minor;
236
237 uint16_t prev_efi_ver_major;
238 uint16_t prev_efi_ver_minor;
239
240 uint16_t prev_fw_ver_major;
241 uint8_t prev_fw_ver_minor;
242 uint8_t prev_fw_ver_subminor;
243
244 uint16_t reserved_17[8];
245
246 /* Offset 384. */
247 uint16_t reserved_18[16];
248
249 /* Offset 416. */
250 uint16_t reserved_19[16];
251
252 /* Offset 448. */
253 uint16_t reserved_20[16];
254
255 /* Offset 480. */
256 uint8_t model_name[16];
257
258 uint16_t reserved_21[2];
259
260 /* Offset 500. */
261 /* HW Parameter Block. */
262 uint16_t pcie_table_sig;
263 uint16_t pcie_table_offset;
264
265 uint16_t subsystem_vendor_id;
266 uint16_t subsystem_device_id;
267
268 uint32_t checksum;
269};
270
271/*
272 * ISP Initialization Control Block.
273 * Little endian except where noted.
274 */
275#define ICB_VERSION 1
276struct init_cb_24xx {
277 uint16_t version;
278 uint16_t reserved_1;
279
280 uint16_t frame_payload_size;
281 uint16_t execution_throttle;
282 uint16_t exchange_count;
283
284 uint16_t hard_address;
285
286 uint8_t port_name[WWN_SIZE]; /* Big endian. */
287 uint8_t node_name[WWN_SIZE]; /* Big endian. */
288
289 uint16_t response_q_inpointer;
290 uint16_t request_q_outpointer;
291
292 uint16_t login_retry_count;
293
294 uint16_t prio_request_q_outpointer;
295
296 uint16_t response_q_length;
297 uint16_t request_q_length;
298
299 uint16_t link_down_timeout; /* Milliseconds. */
300
301 uint16_t prio_request_q_length;
302
303 uint32_t request_q_address[2];
304 uint32_t response_q_address[2];
305 uint32_t prio_request_q_address[2];
306
307 uint8_t reserved_2[8];
308
309 uint16_t atio_q_inpointer;
310 uint16_t atio_q_length;
311 uint32_t atio_q_address[2];
312
313 uint16_t interrupt_delay_timer; /* 100us increments. */
314 uint16_t login_timeout;
315
316 /*
317 * BIT 0 = Enable Hard Loop Id
318 * BIT 1 = Enable Fairness
319 * BIT 2 = Enable Full-Duplex
320 * BIT 3 = Reserved
321 * BIT 4 = Enable Target Mode
322 * BIT 5 = Disable Initiator Mode
323 * BIT 6 = Reserved
324 * BIT 7 = Reserved
325 *
326 * BIT 8 = Reserved
327 * BIT 9 = Non Participating LIP
328 * BIT 10 = Descending Loop ID Search
329 * BIT 11 = Acquire Loop ID in LIPA
330 * BIT 12 = Reserved
331 * BIT 13 = Full Login after LIP
332 * BIT 14 = Node Name Option
333 * BIT 15-31 = Reserved
334 */
335 uint32_t firmware_options_1;
336
337 /*
338 * BIT 0 = Operation Mode bit 0
339 * BIT 1 = Operation Mode bit 1
340 * BIT 2 = Operation Mode bit 2
341 * BIT 3 = Operation Mode bit 3
342 * BIT 4 = Connection Options bit 0
343 * BIT 5 = Connection Options bit 1
344 * BIT 6 = Connection Options bit 2
345 * BIT 7 = Enable Non part on LIHA failure
346 *
347 * BIT 8 = Enable Class 2
348 * BIT 9 = Enable ACK0
349 * BIT 10 = Reserved
350 * BIT 11 = Enable FC-SP Security
351 * BIT 12 = FC Tape Enable
352 * BIT 13-31 = Reserved
353 */
354 uint32_t firmware_options_2;
355
356 /*
357 * BIT 0 = Reserved
358 * BIT 1 = Soft ID only
359 * BIT 2 = Reserved
360 * BIT 3 = Reserved
361 * BIT 4 = FCP RSP Payload bit 0
362 * BIT 5 = FCP RSP Payload bit 1
363 * BIT 6 = Enable Receive Out-of-Order data frame handling
364 * BIT 7 = Disable Automatic PLOGI on Local Loop
365 *
366 * BIT 8 = Reserved
367 * BIT 9 = Enable Out-of-Order FCP_XFER_RDY relative offset handling
368 * BIT 10 = Reserved
369 * BIT 11 = Reserved
370 * BIT 12 = Reserved
371 * BIT 13 = Data Rate bit 0
372 * BIT 14 = Data Rate bit 1
373 * BIT 15 = Data Rate bit 2
374 * BIT 16-31 = Reserved
375 */
376 uint32_t firmware_options_3;
377
378 uint8_t reserved_3[24];
379};
380
381/*
382 * ISP queue - command entry structure definition.
383 */
384#define COMMAND_TYPE_6 0x48 /* Command Type 6 entry */
385struct cmd_type_6 {
386 uint8_t entry_type; /* Entry type. */
387 uint8_t entry_count; /* Entry count. */
388 uint8_t sys_define; /* System defined. */
389 uint8_t entry_status; /* Entry Status. */
390
391 uint32_t handle; /* System handle. */
392
393 uint16_t nport_handle; /* N_PORT handle. */
394 uint16_t timeout; /* Command timeout. */
395
396 uint16_t dseg_count; /* Data segment count. */
397
398 uint16_t fcp_rsp_dsd_len; /* FCP_RSP DSD length. */
399
400 uint8_t lun[8]; /* FCP LUN (BE). */
401
402 uint16_t control_flags; /* Control flags. */
403#define CF_DATA_SEG_DESCR_ENABLE BIT_2
404#define CF_READ_DATA BIT_1
405#define CF_WRITE_DATA BIT_0
406
407 uint16_t fcp_cmnd_dseg_len; /* Data segment length. */
408 uint32_t fcp_cmnd_dseg_address[2]; /* Data segment address. */
409
410 uint32_t fcp_rsp_dseg_address[2]; /* Data segment address. */
411
412 uint32_t byte_count; /* Total byte count. */
413
414 uint8_t port_id[3]; /* PortID of destination port. */
415 uint8_t vp_index;
416
417 uint32_t fcp_data_dseg_address[2]; /* Data segment address. */
418 uint16_t fcp_data_dseg_len; /* Data segment length. */
419 uint16_t reserved_1; /* MUST be set to 0. */
420};
421
422#define COMMAND_TYPE_7 0x18 /* Command Type 7 entry */
423struct cmd_type_7 {
424 uint8_t entry_type; /* Entry type. */
425 uint8_t entry_count; /* Entry count. */
426 uint8_t sys_define; /* System defined. */
427 uint8_t entry_status; /* Entry Status. */
428
429 uint32_t handle; /* System handle. */
430
431 uint16_t nport_handle; /* N_PORT handle. */
432 uint16_t timeout; /* Command timeout. */
433#define FW_MAX_TIMEOUT 0x1999
434
435 uint16_t dseg_count; /* Data segment count. */
436 uint16_t reserved_1;
437
438 uint8_t lun[8]; /* FCP LUN (BE). */
439
440 uint16_t task_mgmt_flags; /* Task management flags. */
441#define TMF_CLEAR_ACA BIT_14
442#define TMF_TARGET_RESET BIT_13
443#define TMF_LUN_RESET BIT_12
444#define TMF_CLEAR_TASK_SET BIT_10
445#define TMF_ABORT_TASK_SET BIT_9
446#define TMF_READ_DATA BIT_1
447#define TMF_WRITE_DATA BIT_0
448
449 uint8_t task;
450#define TSK_SIMPLE 0
451#define TSK_HEAD_OF_QUEUE 1
452#define TSK_ORDERED 2
453#define TSK_ACA 4
454#define TSK_UNTAGGED 5
455
456 uint8_t crn;
457
458 uint8_t fcp_cdb[MAX_CMDSZ]; /* SCSI command words. */
459 uint32_t byte_count; /* Total byte count. */
460
461 uint8_t port_id[3]; /* PortID of destination port. */
462 uint8_t vp_index;
463
464 uint32_t dseg_0_address[2]; /* Data segment 0 address. */
465 uint32_t dseg_0_len; /* Data segment 0 length. */
466};
467
468/*
469 * ISP queue - status entry structure definition.
470 */
471#define STATUS_TYPE 0x03 /* Status entry. */
472struct sts_entry_24xx {
473 uint8_t entry_type; /* Entry type. */
474 uint8_t entry_count; /* Entry count. */
475 uint8_t sys_define; /* System defined. */
476 uint8_t entry_status; /* Entry Status. */
477
478 uint32_t handle; /* System handle. */
479
480 uint16_t comp_status; /* Completion status. */
481 uint16_t ox_id; /* OX_ID used by the firmware. */
482
483 uint32_t residual_len; /* Residual transfer length. */
484
485 uint16_t reserved_1;
486 uint16_t state_flags; /* State flags. */
487#define SF_TRANSFERRED_DATA BIT_11
488#define SF_FCP_RSP_DMA BIT_0
489
490 uint16_t reserved_2;
491 uint16_t scsi_status; /* SCSI status. */
492#define SS_CONFIRMATION_REQ BIT_12
493
494 uint32_t rsp_residual_count; /* FCP RSP residual count. */
495
496 uint32_t sense_len; /* FCP SENSE length. */
497 uint32_t rsp_data_len; /* FCP response data length. */
498
499 uint8_t data[28]; /* FCP response/sense information. */
500};
501
502/*
503 * Status entry completion status
504 */
505#define CS_DATA_REASSEMBLY_ERROR 0x11 /* Data Reassembly Error.. */
506#define CS_ABTS_BY_TARGET 0x13 /* Target send ABTS to abort IOCB. */
507#define CS_FW_RESOURCE 0x2C /* Firmware Resource Unavailable. */
508#define CS_TASK_MGMT_OVERRUN 0x30 /* Task management overrun (8+). */
509#define CS_ABORT_BY_TARGET 0x47 /* Abort By Target. */
510
511/*
512 * ISP queue - marker entry structure definition.
513 */
514#define MARKER_TYPE 0x04 /* Marker entry. */
515struct mrk_entry_24xx {
516 uint8_t entry_type; /* Entry type. */
517 uint8_t entry_count; /* Entry count. */
518 uint8_t handle_count; /* Handle count. */
519 uint8_t entry_status; /* Entry Status. */
520
521 uint32_t handle; /* System handle. */
522
523 uint16_t nport_handle; /* N_PORT handle. */
524
525 uint8_t modifier; /* Modifier (7-0). */
526#define MK_SYNC_ID_LUN 0 /* Synchronize ID/LUN */
527#define MK_SYNC_ID 1 /* Synchronize ID */
528#define MK_SYNC_ALL 2 /* Synchronize all ID/LUN */
529 uint8_t reserved_1;
530
531 uint8_t reserved_2;
532 uint8_t vp_index;
533
534 uint16_t reserved_3;
535
536 uint8_t lun[8]; /* FCP LUN (BE). */
537 uint8_t reserved_4[40];
538};
539
540/*
541 * ISP queue - CT Pass-Through entry structure definition.
542 */
543#define CT_IOCB_TYPE 0x29 /* CT Pass-Through IOCB entry */
544struct ct_entry_24xx {
545 uint8_t entry_type; /* Entry type. */
546 uint8_t entry_count; /* Entry count. */
547 uint8_t sys_define; /* System Defined. */
548 uint8_t entry_status; /* Entry Status. */
549
550 uint32_t handle; /* System handle. */
551
552 uint16_t comp_status; /* Completion status. */
553
554 uint16_t nport_handle; /* N_PORT handle. */
555
556 uint16_t cmd_dsd_count;
557
558 uint8_t vp_index;
559 uint8_t reserved_1;
560
561 uint16_t timeout; /* Command timeout. */
562 uint16_t reserved_2;
563
564 uint16_t rsp_dsd_count;
565
566 uint8_t reserved_3[10];
567
568 uint32_t rsp_byte_count;
569 uint32_t cmd_byte_count;
570
571 uint32_t dseg_0_address[2]; /* Data segment 0 address. */
572 uint32_t dseg_0_len; /* Data segment 0 length. */
573 uint32_t dseg_1_address[2]; /* Data segment 1 address. */
574 uint32_t dseg_1_len; /* Data segment 1 length. */
575};
576
577/*
578 * ISP queue - ELS Pass-Through entry structure definition.
579 */
580#define ELS_IOCB_TYPE 0x53 /* ELS Pass-Through IOCB entry */
581struct els_entry_24xx {
582 uint8_t entry_type; /* Entry type. */
583 uint8_t entry_count; /* Entry count. */
584 uint8_t sys_define; /* System Defined. */
585 uint8_t entry_status; /* Entry Status. */
586
587 uint32_t handle; /* System handle. */
588
589 uint16_t reserved_1;
590
591 uint16_t nport_handle; /* N_PORT handle. */
592
593 uint16_t tx_dsd_count;
594
595 uint8_t vp_index;
596 uint8_t sof_type;
597#define EST_SOFI3 (1 << 4)
598#define EST_SOFI2 (3 << 4)
599
600 uint32_t rx_xchg_address[2]; /* Receive exchange address. */
601 uint16_t rx_dsd_count;
602
603 uint8_t opcode;
604 uint8_t reserved_2;
605
606 uint8_t port_id[3];
607 uint8_t reserved_3;
608
609 uint16_t reserved_4;
610
611 uint16_t control_flags; /* Control flags. */
612#define ECF_PAYLOAD_DESCR_MASK (BIT_15|BIT_14|BIT_13)
613#define EPD_ELS_COMMAND (0 << 13)
614#define EPD_ELS_ACC (1 << 13)
615#define EPD_ELS_RJT (2 << 13)
616#define EPD_RX_XCHG (3 << 13)
617#define ECF_CLR_PASSTHRU_PEND BIT_12
618#define ECF_INCL_FRAME_HDR BIT_11
619
620 uint32_t rx_byte_count;
621 uint32_t tx_byte_count;
622
623 uint32_t tx_address[2]; /* Data segment 0 address. */
624 uint32_t tx_len; /* Data segment 0 length. */
625 uint32_t rx_address[2]; /* Data segment 1 address. */
626 uint32_t rx_len; /* Data segment 1 length. */
627};
628
629/*
630 * ISP queue - Mailbox Command entry structure definition.
631 */
632#define MBX_IOCB_TYPE 0x39
633struct mbx_entry_24xx {
634 uint8_t entry_type; /* Entry type. */
635 uint8_t entry_count; /* Entry count. */
636 uint8_t handle_count; /* Handle count. */
637 uint8_t entry_status; /* Entry Status. */
638
639 uint32_t handle; /* System handle. */
640
641 uint16_t mbx[28];
642};
643
644
645#define LOGINOUT_PORT_IOCB_TYPE 0x52 /* Login/Logout Port entry. */
646struct logio_entry_24xx {
647 uint8_t entry_type; /* Entry type. */
648 uint8_t entry_count; /* Entry count. */
649 uint8_t sys_define; /* System defined. */
650 uint8_t entry_status; /* Entry Status. */
651
652 uint32_t handle; /* System handle. */
653
654 uint16_t comp_status; /* Completion status. */
655#define CS_LOGIO_ERROR 0x31 /* Login/Logout IOCB error. */
656
657 uint16_t nport_handle; /* N_PORT handle. */
658
659 uint16_t control_flags; /* Control flags. */
660 /* Modifiers. */
661#define LCF_FCP2_OVERRIDE BIT_9 /* Set/Reset word 3 of PRLI. */
662#define LCF_CLASS_2 BIT_8 /* Enable class 2 during PLOGI. */
663#define LCF_FREE_NPORT BIT_7 /* Release NPORT handle after LOGO. */
664#define LCF_EXPL_LOGO BIT_6 /* Perform an explicit LOGO. */
665#define LCF_SKIP_PRLI BIT_5 /* Skip PRLI after PLOGI. */
666#define LCF_IMPL_LOGO_ALL BIT_5 /* Implicit LOGO to all ports. */
667#define LCF_COND_PLOGI BIT_4 /* PLOGI only if not logged-in. */
668#define LCF_IMPL_LOGO BIT_4 /* Perform an implicit LOGO. */
669#define LCF_IMPL_PRLO BIT_4 /* Perform an implicit PRLO. */
670 /* Commands. */
671#define LCF_COMMAND_PLOGI 0x00 /* PLOGI. */
672#define LCF_COMMAND_PRLI 0x01 /* PRLI. */
673#define LCF_COMMAND_PDISC 0x02 /* PDISC. */
674#define LCF_COMMAND_ADISC 0x03 /* ADISC. */
675#define LCF_COMMAND_LOGO 0x08 /* LOGO. */
676#define LCF_COMMAND_PRLO 0x09 /* PRLO. */
677#define LCF_COMMAND_TPRLO 0x0A /* TPRLO. */
678
679 uint8_t vp_index;
680 uint8_t reserved_1;
681
682 uint8_t port_id[3]; /* PortID of destination port. */
683
684 uint8_t rsp_size; /* Response size in 32bit words. */
685
686 uint32_t io_parameter[11]; /* General I/O parameters. */
687#define LSC_SCODE_NOLINK 0x01
688#define LSC_SCODE_NOIOCB 0x02
689#define LSC_SCODE_NOXCB 0x03
690#define LSC_SCODE_CMD_FAILED 0x04
691#define LSC_SCODE_NOFABRIC 0x05
692#define LSC_SCODE_FW_NOT_READY 0x07
693#define LSC_SCODE_NOT_LOGGED_IN 0x09
694#define LSC_SCODE_NOPCB 0x0A
695
696#define LSC_SCODE_ELS_REJECT 0x18
697#define LSC_SCODE_CMD_PARAM_ERR 0x19
698#define LSC_SCODE_PORTID_USED 0x1A
699#define LSC_SCODE_NPORT_USED 0x1B
700#define LSC_SCODE_NONPORT 0x1C
701#define LSC_SCODE_LOGGED_IN 0x1D
702#define LSC_SCODE_NOFLOGI_ACC 0x1F
703};
704
705#define TSK_MGMT_IOCB_TYPE 0x14
706struct tsk_mgmt_entry {
707 uint8_t entry_type; /* Entry type. */
708 uint8_t entry_count; /* Entry count. */
709 uint8_t handle_count; /* Handle count. */
710 uint8_t entry_status; /* Entry Status. */
711
712 uint32_t handle; /* System handle. */
713
714 uint16_t nport_handle; /* N_PORT handle. */
715
716 uint16_t reserved_1;
717
718 uint16_t delay; /* Activity delay in seconds. */
719
720 uint16_t timeout; /* Command timeout. */
721
722 uint8_t lun[8]; /* FCP LUN (BE). */
723
724 uint32_t control_flags; /* Control Flags. */
725#define TCF_NOTMCMD_TO_TARGET BIT_31
726#define TCF_LUN_RESET BIT_4
727#define TCF_ABORT_TASK_SET BIT_3
728#define TCF_CLEAR_TASK_SET BIT_2
729#define TCF_TARGET_RESET BIT_1
730#define TCF_CLEAR_ACA BIT_0
731
732 uint8_t reserved_2[20];
733
734 uint8_t port_id[3]; /* PortID of destination port. */
735 uint8_t vp_index;
736
737 uint8_t reserved_3[12];
738};
739
740#define ABORT_IOCB_TYPE 0x33
741struct abort_entry_24xx {
742 uint8_t entry_type; /* Entry type. */
743 uint8_t entry_count; /* Entry count. */
744 uint8_t handle_count; /* Handle count. */
745 uint8_t entry_status; /* Entry Status. */
746
747 uint32_t handle; /* System handle. */
748
749 uint16_t nport_handle; /* N_PORT handle. */
750 /* or Completion status. */
751
752 uint16_t options; /* Options. */
753#define AOF_NO_ABTS BIT_0 /* Do not send any ABTS. */
754
755 uint32_t handle_to_abort; /* System handle to abort. */
756
757 uint8_t reserved_1[32];
758
759 uint8_t port_id[3]; /* PortID of destination port. */
760 uint8_t vp_index;
761
762 uint8_t reserved_2[12];
763};
764
765/*
766 * ISP I/O Register Set structure definitions.
767 */
768struct device_reg_24xx {
769 uint32_t flash_addr; /* Flash/NVRAM BIOS address. */
770#define FARX_DATA_FLAG BIT_31
771#define FARX_ACCESS_FLASH_CONF 0x7FFD0000
772#define FARX_ACCESS_FLASH_DATA 0x7FF00000
773#define FARX_ACCESS_NVRAM_CONF 0x7FFF0000
774#define FARX_ACCESS_NVRAM_DATA 0x7FFE0000
775
776#define FA_NVRAM_FUNC0_ADDR 0x80
777#define FA_NVRAM_FUNC1_ADDR 0x180
778
779#define FA_NVRAM_VPD_SIZE 0x80
780#define FA_NVRAM_VPD0_ADDR 0x00
781#define FA_NVRAM_VPD1_ADDR 0x100
782 /*
783 * RISC code begins at offset 512KB
784 * within flash. Consisting of two
785 * contiguous RISC code segments.
786 */
787#define FA_RISC_CODE_ADDR 0x20000
788#define FA_RISC_CODE_SEGMENTS 2
789
790 uint32_t flash_data; /* Flash/NVRAM BIOS data. */
791
792 uint32_t ctrl_status; /* Control/Status. */
793#define CSRX_FLASH_ACCESS_ERROR BIT_18 /* Flash/NVRAM Access Error. */
794#define CSRX_DMA_ACTIVE BIT_17 /* DMA Active status. */
795#define CSRX_DMA_SHUTDOWN BIT_16 /* DMA Shutdown control status. */
796#define CSRX_FUNCTION BIT_15 /* Function number. */
797 /* PCI-X Bus Mode. */
798#define CSRX_PCIX_BUS_MODE_MASK (BIT_11|BIT_10|BIT_9|BIT_8)
799#define PBM_PCI_33MHZ (0 << 8)
800#define PBM_PCIX_M1_66MHZ (1 << 8)
801#define PBM_PCIX_M1_100MHZ (2 << 8)
802#define PBM_PCIX_M1_133MHZ (3 << 8)
803#define PBM_PCIX_M2_66MHZ (5 << 8)
804#define PBM_PCIX_M2_100MHZ (6 << 8)
805#define PBM_PCIX_M2_133MHZ (7 << 8)
806#define PBM_PCI_66MHZ (8 << 8)
807 /* Max Write Burst byte count. */
808#define CSRX_MAX_WRT_BURST_MASK (BIT_5|BIT_4)
809#define MWB_512_BYTES (0 << 4)
810#define MWB_1024_BYTES (1 << 4)
811#define MWB_2048_BYTES (2 << 4)
812#define MWB_4096_BYTES (3 << 4)
813
814#define CSRX_64BIT_SLOT BIT_2 /* PCI 64-Bit Bus Slot. */
815#define CSRX_FLASH_ENABLE BIT_1 /* Flash BIOS Read/Write enable. */
816#define CSRX_ISP_SOFT_RESET BIT_0 /* ISP soft reset. */
817
818 uint32_t ictrl; /* Interrupt control. */
819#define ICRX_EN_RISC_INT BIT_3 /* Enable RISC interrupts on PCI. */
820
821 uint32_t istatus; /* Interrupt status. */
822#define ISRX_RISC_INT BIT_3 /* RISC interrupt. */
823
824 uint32_t unused_1[2]; /* Gap. */
825
826 /* Request Queue. */
827 uint32_t req_q_in; /* In-Pointer. */
828 uint32_t req_q_out; /* Out-Pointer. */
829 /* Response Queue. */
830 uint32_t rsp_q_in; /* In-Pointer. */
831 uint32_t rsp_q_out; /* Out-Pointer. */
832 /* Priority Request Queue. */
833 uint32_t preq_q_in; /* In-Pointer. */
834 uint32_t preq_q_out; /* Out-Pointer. */
835
836 uint32_t unused_2[2]; /* Gap. */
837
838 /* ATIO Queue. */
839 uint32_t atio_q_in; /* In-Pointer. */
840 uint32_t atio_q_out; /* Out-Pointer. */
841
842 uint32_t host_status;
843#define HSRX_RISC_INT BIT_15 /* RISC to Host interrupt. */
844#define HSRX_RISC_PAUSED BIT_8 /* RISC Paused. */
845
846 uint32_t hccr; /* Host command & control register. */
847 /* HCCR statuses. */
848#define HCCRX_HOST_INT BIT_6 /* Host to RISC interrupt bit. */
849#define HCCRX_RISC_RESET BIT_5 /* RISC Reset mode bit. */
850#define HCCRX_RISC_PAUSE BIT_4 /* RISC Pause mode bit. */
851 /* HCCR commands. */
852 /* NOOP. */
853#define HCCRX_NOOP 0x00000000
854 /* Set RISC Reset. */
855#define HCCRX_SET_RISC_RESET 0x10000000
856 /* Clear RISC Reset. */
857#define HCCRX_CLR_RISC_RESET 0x20000000
858 /* Set RISC Pause. */
859#define HCCRX_SET_RISC_PAUSE 0x30000000
860 /* Releases RISC Pause. */
861#define HCCRX_REL_RISC_PAUSE 0x40000000
862 /* Set HOST to RISC interrupt. */
863#define HCCRX_SET_HOST_INT 0x50000000
864 /* Clear HOST to RISC interrupt. */
865#define HCCRX_CLR_HOST_INT 0x60000000
866 /* Clear RISC to PCI interrupt. */
867#define HCCRX_CLR_RISC_INT 0xA0000000
868
869 uint32_t gpiod; /* GPIO Data register. */
870 /* LED update mask. */
871#define GPDX_LED_UPDATE_MASK (BIT_20|BIT_19|BIT_18)
872 /* Data update mask. */
873#define GPDX_DATA_UPDATE_MASK (BIT_17|BIT_16)
874 /* LED control mask. */
875#define GPDX_LED_COLOR_MASK (BIT_4|BIT_3|BIT_2)
876 /* LED bit values. Color names as
877 * referenced in fw spec.
878 */
879#define GPDX_LED_YELLOW_ON BIT_2
880#define GPDX_LED_GREEN_ON BIT_3
881#define GPDX_LED_AMBER_ON BIT_4
882 /* Data in/out. */
883#define GPDX_DATA_INOUT (BIT_1|BIT_0)
884
885 uint32_t gpioe; /* GPIO Enable register. */
886 /* Enable update mask. */
887#define GPEX_ENABLE_UPDATE_MASK (BIT_17|BIT_16)
888 /* Enable. */
889#define GPEX_ENABLE (BIT_1|BIT_0)
890
891 uint32_t iobase_addr; /* I/O Bus Base Address register. */
892
893 uint32_t unused_3[10]; /* Gap. */
894
895 uint16_t mailbox0;
896 uint16_t mailbox1;
897 uint16_t mailbox2;
898 uint16_t mailbox3;
899 uint16_t mailbox4;
900 uint16_t mailbox5;
901 uint16_t mailbox6;
902 uint16_t mailbox7;
903 uint16_t mailbox8;
904 uint16_t mailbox9;
905 uint16_t mailbox10;
906 uint16_t mailbox11;
907 uint16_t mailbox12;
908 uint16_t mailbox13;
909 uint16_t mailbox14;
910 uint16_t mailbox15;
911 uint16_t mailbox16;
912 uint16_t mailbox17;
913 uint16_t mailbox18;
914 uint16_t mailbox19;
915 uint16_t mailbox20;
916 uint16_t mailbox21;
917 uint16_t mailbox22;
918 uint16_t mailbox23;
919 uint16_t mailbox24;
920 uint16_t mailbox25;
921 uint16_t mailbox26;
922 uint16_t mailbox27;
923 uint16_t mailbox28;
924 uint16_t mailbox29;
925 uint16_t mailbox30;
926 uint16_t mailbox31;
927};
928
929/* MID Support ***************************************************************/
930
931#define MAX_MID_VPS 125
932
933struct mid_conf_entry_24xx {
934 uint16_t reserved_1;
935
936 /*
937 * BIT 0 = Enable Hard Loop Id
938 * BIT 1 = Acquire Loop ID in LIPA
939 * BIT 2 = ID not Acquired
940 * BIT 3 = Enable VP
941 * BIT 4 = Enable Initiator Mode
942 * BIT 5 = Disable Target Mode
943 * BIT 6-7 = Reserved
944 */
945 uint8_t options;
946
947 uint8_t hard_address;
948
949 uint8_t port_name[WWN_SIZE];
950 uint8_t node_name[WWN_SIZE];
951};
952
953struct mid_init_cb_24xx {
954 struct init_cb_24xx init_cb;
955
956 uint16_t count;
957 uint16_t options;
958
959 struct mid_conf_entry_24xx entries[MAX_MID_VPS];
960};
961
962
963struct mid_db_entry_24xx {
964 uint16_t status;
965#define MDBS_NON_PARTIC BIT_3
966#define MDBS_ID_ACQUIRED BIT_1
967#define MDBS_ENABLED BIT_0
968
969 uint8_t options;
970 uint8_t hard_address;
971
972 uint8_t port_name[WWN_SIZE];
973 uint8_t node_name[WWN_SIZE];
974
975 uint8_t port_id[3];
976 uint8_t reserved_1;
977};
978
979struct mid_db_24xx {
980 struct mid_db_entry_24xx entries[MAX_MID_VPS];
981};
982
983#define VP_CTRL_IOCB_TYPE 0x30 /* Vitual Port Control entry. */
984struct vp_ctrl_entry_24xx {
985 uint8_t entry_type; /* Entry type. */
986 uint8_t entry_count; /* Entry count. */
987 uint8_t sys_define; /* System defined. */
988 uint8_t entry_status; /* Entry Status. */
989
990 uint32_t handle; /* System handle. */
991
992 uint16_t vp_idx_failed;
993
994 uint16_t comp_status; /* Completion status. */
995#define CS_VCE_ACQ_ID_ERROR 0x02 /* Error while acquireing ID. */
996#define CS_VCE_BUSY 0x05 /* Firmware not ready to accept cmd. */
997
998 uint16_t command;
999#define VCE_COMMAND_ENABLE_VPS 0x00 /* Enable VPs. */
1000#define VCE_COMMAND_DISABLE_VPS 0x08 /* Disable VPs. */
1001#define VCE_COMMAND_DISABLE_VPS_REINIT 0x09 /* Disable VPs and reinit link. */
1002#define VCE_COMMAND_DISABLE_VPS_LOGO 0x0a /* Disable VPs and LOGO ports. */
1003
1004 uint16_t vp_count;
1005
1006 uint8_t vp_idx_map[16];
1007
1008 uint8_t reserved_4[32];
1009};
1010
1011#define VP_CONFIG_IOCB_TYPE 0x31 /* Vitual Port Config entry. */
1012struct vp_config_entry_24xx {
1013 uint8_t entry_type; /* Entry type. */
1014 uint8_t entry_count; /* Entry count. */
1015 uint8_t sys_define; /* System defined. */
1016 uint8_t entry_status; /* Entry Status. */
1017
1018 uint32_t handle; /* System handle. */
1019
1020 uint16_t reserved_1;
1021
1022 uint16_t comp_status; /* Completion status. */
1023#define CS_VCT_STS_ERROR 0x01 /* Specified VPs were not disabled. */
1024#define CS_VCT_CNT_ERROR 0x02 /* Invalid VP count. */
1025#define CS_VCT_ERROR 0x03 /* Unknown error. */
1026#define CS_VCT_IDX_ERROR 0x02 /* Invalid VP index. */
1027#define CS_VCT_BUSY 0x05 /* Firmware not ready to accept cmd. */
1028
1029 uint8_t command;
1030#define VCT_COMMAND_MOD_VPS 0x00 /* Enable VPs. */
1031#define VCT_COMMAND_MOD_ENABLE_VPS 0x08 /* Disable VPs. */
1032
1033 uint8_t vp_count;
1034
1035 uint8_t vp_idx1;
1036 uint8_t vp_idx2;
1037
1038 uint8_t options_idx1;
1039 uint8_t hard_address_idx1;
1040 uint16_t reserved_2;
1041 uint8_t port_name_idx1[WWN_SIZE];
1042 uint8_t node_name_idx1[WWN_SIZE];
1043
1044 uint8_t options_idx2;
1045 uint8_t hard_address_idx2;
1046 uint16_t reserved_3;
1047 uint8_t port_name_idx2[WWN_SIZE];
1048 uint8_t node_name_idx2[WWN_SIZE];
1049
1050 uint8_t reserved_4[8];
1051};
1052
1053#define VP_RPT_ID_IOCB_TYPE 0x32 /* Report ID Acquisition entry. */
1054struct vp_rpt_id_entry_24xx {
1055 uint8_t entry_type; /* Entry type. */
1056 uint8_t entry_count; /* Entry count. */
1057 uint8_t sys_define; /* System defined. */
1058 uint8_t entry_status; /* Entry Status. */
1059
1060 uint32_t handle; /* System handle. */
1061
1062 uint16_t vp_count; /* Format 0 -- | VP setup | VP acq |. */
1063 /* Format 1 -- | VP count |. */
1064 uint16_t vp_idx; /* Format 0 -- Reserved. */
1065 /* Format 1 -- VP status and index. */
1066
1067 uint8_t port_id[3];
1068 uint8_t format;
1069
1070 uint8_t vp_idx_map[16];
1071
1072 uint8_t reserved_4[32];
1073};
1074
1075/* END MID Support ***********************************************************/
1076#endif
diff --git a/drivers/scsi/qla2xxx/qla_init.c b/drivers/scsi/qla2xxx/qla_init.c
index 27b7f9259f28..226bec05d4d1 100644
--- a/drivers/scsi/qla2xxx/qla_init.c
+++ b/drivers/scsi/qla2xxx/qla_init.c
@@ -195,6 +195,7 @@ qla2100_pci_config(scsi_qla_host_t *ha)
195{ 195{
196 uint16_t w, mwi; 196 uint16_t w, mwi;
197 unsigned long flags; 197 unsigned long flags;
198 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
198 199
199 qla_printk(KERN_INFO, ha, "Configuring PCI space...\n"); 200 qla_printk(KERN_INFO, ha, "Configuring PCI space...\n");
200 201
@@ -215,7 +216,7 @@ qla2100_pci_config(scsi_qla_host_t *ha)
215 216
216 /* Get PCI bus information. */ 217 /* Get PCI bus information. */
217 spin_lock_irqsave(&ha->hardware_lock, flags); 218 spin_lock_irqsave(&ha->hardware_lock, flags);
218 ha->pci_attr = RD_REG_WORD(&ha->iobase->ctrl_status); 219 ha->pci_attr = RD_REG_WORD(&reg->ctrl_status);
219 spin_unlock_irqrestore(&ha->hardware_lock, flags); 220 spin_unlock_irqrestore(&ha->hardware_lock, flags);
220 221
221 return QLA_SUCCESS; 222 return QLA_SUCCESS;
@@ -233,6 +234,7 @@ qla2300_pci_config(scsi_qla_host_t *ha)
233 uint16_t w, mwi; 234 uint16_t w, mwi;
234 unsigned long flags = 0; 235 unsigned long flags = 0;
235 uint32_t cnt; 236 uint32_t cnt;
237 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
236 238
237 qla_printk(KERN_INFO, ha, "Configuring PCI space...\n"); 239 qla_printk(KERN_INFO, ha, "Configuring PCI space...\n");
238 240
@@ -259,34 +261,32 @@ qla2300_pci_config(scsi_qla_host_t *ha)
259 spin_lock_irqsave(&ha->hardware_lock, flags); 261 spin_lock_irqsave(&ha->hardware_lock, flags);
260 262
261 /* Pause RISC. */ 263 /* Pause RISC. */
262 WRT_REG_WORD(&ha->iobase->hccr, HCCR_PAUSE_RISC); 264 WRT_REG_WORD(&reg->hccr, HCCR_PAUSE_RISC);
263 for (cnt = 0; cnt < 30000; cnt++) { 265 for (cnt = 0; cnt < 30000; cnt++) {
264 if ((RD_REG_WORD(&ha->iobase->hccr) & 266 if ((RD_REG_WORD(&reg->hccr) & HCCR_RISC_PAUSE) != 0)
265 HCCR_RISC_PAUSE) != 0)
266 break; 267 break;
267 268
268 udelay(10); 269 udelay(10);
269 } 270 }
270 271
271 /* Select FPM registers. */ 272 /* Select FPM registers. */
272 WRT_REG_WORD(&ha->iobase->ctrl_status, 0x20); 273 WRT_REG_WORD(&reg->ctrl_status, 0x20);
273 RD_REG_WORD(&ha->iobase->ctrl_status); 274 RD_REG_WORD(&reg->ctrl_status);
274 275
275 /* Get the fb rev level */ 276 /* Get the fb rev level */
276 ha->fb_rev = RD_FB_CMD_REG(ha, ha->iobase); 277 ha->fb_rev = RD_FB_CMD_REG(ha, reg);
277 278
278 if (ha->fb_rev == FPM_2300) 279 if (ha->fb_rev == FPM_2300)
279 w &= ~PCI_COMMAND_INVALIDATE; 280 w &= ~PCI_COMMAND_INVALIDATE;
280 281
281 /* Deselect FPM registers. */ 282 /* Deselect FPM registers. */
282 WRT_REG_WORD(&ha->iobase->ctrl_status, 0x0); 283 WRT_REG_WORD(&reg->ctrl_status, 0x0);
283 RD_REG_WORD(&ha->iobase->ctrl_status); 284 RD_REG_WORD(&reg->ctrl_status);
284 285
285 /* Release RISC module. */ 286 /* Release RISC module. */
286 WRT_REG_WORD(&ha->iobase->hccr, HCCR_RELEASE_RISC); 287 WRT_REG_WORD(&reg->hccr, HCCR_RELEASE_RISC);
287 for (cnt = 0; cnt < 30000; cnt++) { 288 for (cnt = 0; cnt < 30000; cnt++) {
288 if ((RD_REG_WORD(&ha->iobase->hccr) & 289 if ((RD_REG_WORD(&reg->hccr) & HCCR_RISC_PAUSE) == 0)
289 HCCR_RISC_PAUSE) == 0)
290 break; 290 break;
291 291
292 udelay(10); 292 udelay(10);
@@ -305,7 +305,7 @@ qla2300_pci_config(scsi_qla_host_t *ha)
305 305
306 /* Get PCI bus information. */ 306 /* Get PCI bus information. */
307 spin_lock_irqsave(&ha->hardware_lock, flags); 307 spin_lock_irqsave(&ha->hardware_lock, flags);
308 ha->pci_attr = RD_REG_WORD(&ha->iobase->ctrl_status); 308 ha->pci_attr = RD_REG_WORD(&reg->ctrl_status);
309 spin_unlock_irqrestore(&ha->hardware_lock, flags); 309 spin_unlock_irqrestore(&ha->hardware_lock, flags);
310 310
311 return QLA_SUCCESS; 311 return QLA_SUCCESS;
@@ -352,7 +352,7 @@ void
352qla2x00_reset_chip(scsi_qla_host_t *ha) 352qla2x00_reset_chip(scsi_qla_host_t *ha)
353{ 353{
354 unsigned long flags = 0; 354 unsigned long flags = 0;
355 device_reg_t __iomem *reg = ha->iobase; 355 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
356 uint32_t cnt; 356 uint32_t cnt;
357 unsigned long mbx_flags = 0; 357 unsigned long mbx_flags = 0;
358 uint16_t cmd; 358 uint16_t cmd;
@@ -505,7 +505,7 @@ int
505qla2x00_chip_diag(scsi_qla_host_t *ha) 505qla2x00_chip_diag(scsi_qla_host_t *ha)
506{ 506{
507 int rval; 507 int rval;
508 device_reg_t __iomem *reg = ha->iobase; 508 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
509 unsigned long flags = 0; 509 unsigned long flags = 0;
510 uint16_t data; 510 uint16_t data;
511 uint32_t cnt; 511 uint32_t cnt;
@@ -889,7 +889,7 @@ qla2x00_update_fw_options(scsi_qla_host_t *ha)
889void 889void
890qla2x00_config_rings(struct scsi_qla_host *ha) 890qla2x00_config_rings(struct scsi_qla_host *ha)
891{ 891{
892 device_reg_t __iomem *reg = ha->iobase; 892 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
893 893
894 /* Setup ring parameters in initialization control block. */ 894 /* Setup ring parameters in initialization control block. */
895 ha->init_cb->request_q_outpointer = __constant_cpu_to_le16(0); 895 ha->init_cb->request_q_outpointer = __constant_cpu_to_le16(0);
@@ -1196,7 +1196,7 @@ qla2x00_nvram_config(scsi_qla_host_t *ha)
1196 init_cb_t *icb = ha->init_cb; 1196 init_cb_t *icb = ha->init_cb;
1197 nvram_t *nv = (nvram_t *)ha->request_ring; 1197 nvram_t *nv = (nvram_t *)ha->request_ring;
1198 uint16_t *wptr = (uint16_t *)ha->request_ring; 1198 uint16_t *wptr = (uint16_t *)ha->request_ring;
1199 device_reg_t __iomem *reg = ha->iobase; 1199 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1200 uint8_t timer_mode; 1200 uint8_t timer_mode;
1201 1201
1202 rval = QLA_SUCCESS; 1202 rval = QLA_SUCCESS;
@@ -1389,8 +1389,6 @@ qla2x00_nvram_config(scsi_qla_host_t *ha)
1389 /* 1389 /*
1390 * Set host adapter parameters. 1390 * Set host adapter parameters.
1391 */ 1391 */
1392 ha->nvram_version = nv->nvram_version;
1393
1394 ha->flags.disable_risc_code_load = ((nv->host_p[0] & BIT_4) ? 1 : 0); 1392 ha->flags.disable_risc_code_load = ((nv->host_p[0] & BIT_4) ? 1 : 0);
1395 /* Always load RISC code on non ISP2[12]00 chips. */ 1393 /* Always load RISC code on non ISP2[12]00 chips. */
1396 if (!IS_QLA2100(ha) && !IS_QLA2200(ha)) 1394 if (!IS_QLA2100(ha) && !IS_QLA2200(ha))
@@ -1410,7 +1408,8 @@ qla2x00_nvram_config(scsi_qla_host_t *ha)
1410 ha->serial0 = icb->port_name[5]; 1408 ha->serial0 = icb->port_name[5];
1411 ha->serial1 = icb->port_name[6]; 1409 ha->serial1 = icb->port_name[6];
1412 ha->serial2 = icb->port_name[7]; 1410 ha->serial2 = icb->port_name[7];
1413 memcpy(ha->node_name, icb->node_name, WWN_SIZE); 1411 ha->node_name = icb->node_name;
1412 ha->port_name = icb->port_name;
1414 1413
1415 icb->execution_throttle = __constant_cpu_to_le16(0xFFFF); 1414 icb->execution_throttle = __constant_cpu_to_le16(0xFFFF);
1416 1415
@@ -2158,7 +2157,7 @@ qla2x00_find_all_fabric_devs(scsi_qla_host_t *ha, struct list_head *new_fcports)
2158 loop_id = ha->min_external_loopid; 2157 loop_id = ha->min_external_loopid;
2159 2158
2160 for (; loop_id <= ha->last_loop_id; loop_id++) { 2159 for (; loop_id <= ha->last_loop_id; loop_id++) {
2161 if (RESERVED_LOOP_ID(loop_id)) 2160 if (qla2x00_is_reserved_id(ha, loop_id))
2162 continue; 2161 continue;
2163 2162
2164 if (atomic_read(&ha->loop_down_timer) || 2163 if (atomic_read(&ha->loop_down_timer) ||
@@ -2328,7 +2327,7 @@ qla2x00_find_new_loop_id(scsi_qla_host_t *ha, fc_port_t *dev)
2328 } 2327 }
2329 2328
2330 /* Skip reserved loop IDs. */ 2329 /* Skip reserved loop IDs. */
2331 while (RESERVED_LOOP_ID(dev->loop_id)) { 2330 while (qla2x00_is_reserved_id(ha, dev->loop_id)) {
2332 dev->loop_id++; 2331 dev->loop_id++;
2333 } 2332 }
2334 2333
@@ -2888,7 +2887,7 @@ static int
2888qla2x00_restart_isp(scsi_qla_host_t *ha) 2887qla2x00_restart_isp(scsi_qla_host_t *ha)
2889{ 2888{
2890 uint8_t status = 0; 2889 uint8_t status = 0;
2891 device_reg_t __iomem *reg = ha->iobase; 2890 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
2892 unsigned long flags = 0; 2891 unsigned long flags = 0;
2893 uint32_t wait_time; 2892 uint32_t wait_time;
2894 2893
@@ -2901,8 +2900,6 @@ qla2x00_restart_isp(scsi_qla_host_t *ha)
2901 goto done; 2900 goto done;
2902 } 2901 }
2903 2902
2904 reg = ha->iobase;
2905
2906 spin_lock_irqsave(&ha->hardware_lock, flags); 2903 spin_lock_irqsave(&ha->hardware_lock, flags);
2907 2904
2908 /* Disable SRAM, Instruction RAM and GP RAM parity. */ 2905 /* Disable SRAM, Instruction RAM and GP RAM parity. */
@@ -2973,7 +2970,7 @@ void
2973qla2x00_reset_adapter(scsi_qla_host_t *ha) 2970qla2x00_reset_adapter(scsi_qla_host_t *ha)
2974{ 2971{
2975 unsigned long flags = 0; 2972 unsigned long flags = 0;
2976 device_reg_t __iomem *reg = ha->iobase; 2973 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
2977 2974
2978 ha->flags.online = 0; 2975 ha->flags.online = 0;
2979 ha->isp_ops.disable_intrs(ha); 2976 ha->isp_ops.disable_intrs(ha);
diff --git a/drivers/scsi/qla2xxx/qla_inline.h b/drivers/scsi/qla2xxx/qla_inline.h
index 8f99febc15db..6cf7036ccf4c 100644
--- a/drivers/scsi/qla2xxx/qla_inline.h
+++ b/drivers/scsi/qla2xxx/qla_inline.h
@@ -236,3 +236,14 @@ qla2x00_delete_timer_from_cmd(srb_t *sp)
236 } 236 }
237} 237}
238 238
239
240static inline int qla2x00_is_reserved_id(scsi_qla_host_t *, uint16_t);
241static inline int
242qla2x00_is_reserved_id(scsi_qla_host_t *ha, uint16_t loop_id)
243{
244 if (IS_QLA24XX(ha) || IS_QLA25XX(ha))
245 return (loop_id > NPH_LAST_HANDLE);
246
247 return ((loop_id > ha->last_loop_id && loop_id < SNS_FIRST_LOOP_ID) ||
248 loop_id == MANAGEMENT_SERVER || loop_id == BROADCAST);
249};
diff --git a/drivers/scsi/qla2xxx/qla_iocb.c b/drivers/scsi/qla2xxx/qla_iocb.c
index 5e079b5d9392..846dbfe26be3 100644
--- a/drivers/scsi/qla2xxx/qla_iocb.c
+++ b/drivers/scsi/qla2xxx/qla_iocb.c
@@ -315,13 +315,13 @@ qla2x00_start_scsi(srb_t *sp)
315 uint16_t cnt; 315 uint16_t cnt;
316 uint16_t req_cnt; 316 uint16_t req_cnt;
317 uint16_t tot_dsds; 317 uint16_t tot_dsds;
318 device_reg_t __iomem *reg; 318 struct device_reg_2xxx __iomem *reg;
319 char tag[2]; 319 char tag[2];
320 320
321 /* Setup device pointers. */ 321 /* Setup device pointers. */
322 ret = 0; 322 ret = 0;
323 ha = sp->ha; 323 ha = sp->ha;
324 reg = ha->iobase; 324 reg = &ha->iobase->isp;
325 cmd = sp->cmd; 325 cmd = sp->cmd;
326 /* So we know we haven't pci_map'ed anything yet */ 326 /* So we know we haven't pci_map'ed anything yet */
327 tot_dsds = 0; 327 tot_dsds = 0;
@@ -521,7 +521,7 @@ qla2x00_marker(scsi_qla_host_t *ha, uint16_t loop_id, uint16_t lun,
521static request_t * 521static request_t *
522qla2x00_req_pkt(scsi_qla_host_t *ha) 522qla2x00_req_pkt(scsi_qla_host_t *ha)
523{ 523{
524 device_reg_t __iomem *reg = ha->iobase; 524 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
525 request_t *pkt = NULL; 525 request_t *pkt = NULL;
526 uint16_t cnt; 526 uint16_t cnt;
527 uint32_t *dword_ptr; 527 uint32_t *dword_ptr;
@@ -586,7 +586,7 @@ qla2x00_req_pkt(scsi_qla_host_t *ha)
586void 586void
587qla2x00_isp_cmd(scsi_qla_host_t *ha) 587qla2x00_isp_cmd(scsi_qla_host_t *ha)
588{ 588{
589 device_reg_t __iomem *reg = ha->iobase; 589 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
590 590
591 DEBUG5(printk("%s(): IOCB data:\n", __func__)); 591 DEBUG5(printk("%s(): IOCB data:\n", __func__));
592 DEBUG5(qla2x00_dump_buffer( 592 DEBUG5(qla2x00_dump_buffer(
diff --git a/drivers/scsi/qla2xxx/qla_isr.c b/drivers/scsi/qla2xxx/qla_isr.c
index 117b56242ee2..f38d13628f43 100644
--- a/drivers/scsi/qla2xxx/qla_isr.c
+++ b/drivers/scsi/qla2xxx/qla_isr.c
@@ -41,7 +41,7 @@ irqreturn_t
41qla2100_intr_handler(int irq, void *dev_id, struct pt_regs *regs) 41qla2100_intr_handler(int irq, void *dev_id, struct pt_regs *regs)
42{ 42{
43 scsi_qla_host_t *ha; 43 scsi_qla_host_t *ha;
44 device_reg_t __iomem *reg; 44 struct device_reg_2xxx __iomem *reg;
45 int status; 45 int status;
46 unsigned long flags; 46 unsigned long flags;
47 unsigned long iter; 47 unsigned long iter;
@@ -54,7 +54,7 @@ qla2100_intr_handler(int irq, void *dev_id, struct pt_regs *regs)
54 return (IRQ_NONE); 54 return (IRQ_NONE);
55 } 55 }
56 56
57 reg = ha->iobase; 57 reg = &ha->iobase->isp;
58 status = 0; 58 status = 0;
59 59
60 spin_lock_irqsave(&ha->hardware_lock, flags); 60 spin_lock_irqsave(&ha->hardware_lock, flags);
@@ -118,7 +118,7 @@ irqreturn_t
118qla2300_intr_handler(int irq, void *dev_id, struct pt_regs *regs) 118qla2300_intr_handler(int irq, void *dev_id, struct pt_regs *regs)
119{ 119{
120 scsi_qla_host_t *ha; 120 scsi_qla_host_t *ha;
121 device_reg_t __iomem *reg; 121 struct device_reg_2xxx __iomem *reg;
122 int status; 122 int status;
123 unsigned long flags; 123 unsigned long flags;
124 unsigned long iter; 124 unsigned long iter;
@@ -133,7 +133,7 @@ qla2300_intr_handler(int irq, void *dev_id, struct pt_regs *regs)
133 return (IRQ_NONE); 133 return (IRQ_NONE);
134 } 134 }
135 135
136 reg = ha->iobase; 136 reg = &ha->iobase->isp;
137 status = 0; 137 status = 0;
138 138
139 spin_lock_irqsave(&ha->hardware_lock, flags); 139 spin_lock_irqsave(&ha->hardware_lock, flags);
@@ -220,7 +220,7 @@ qla2x00_mbx_completion(scsi_qla_host_t *ha, uint16_t mb0)
220{ 220{
221 uint16_t cnt; 221 uint16_t cnt;
222 uint16_t __iomem *wptr; 222 uint16_t __iomem *wptr;
223 device_reg_t __iomem *reg = ha->iobase; 223 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
224 224
225 /* Load return mailbox registers. */ 225 /* Load return mailbox registers. */
226 ha->flags.mbox_int = 1; 226 ha->flags.mbox_int = 1;
@@ -261,7 +261,7 @@ qla2x00_async_event(scsi_qla_host_t *ha, uint32_t mbx)
261 uint16_t handle_cnt; 261 uint16_t handle_cnt;
262 uint16_t cnt; 262 uint16_t cnt;
263 uint32_t handles[5]; 263 uint32_t handles[5];
264 device_reg_t __iomem *reg = ha->iobase; 264 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
265 uint32_t rscn_entry, host_pid; 265 uint32_t rscn_entry, host_pid;
266 uint8_t rscn_queue_index; 266 uint8_t rscn_queue_index;
267 267
@@ -707,7 +707,7 @@ qla2x00_process_completed_request(struct scsi_qla_host *ha, uint32_t index)
707void 707void
708qla2x00_process_response_queue(struct scsi_qla_host *ha) 708qla2x00_process_response_queue(struct scsi_qla_host *ha)
709{ 709{
710 device_reg_t __iomem *reg = ha->iobase; 710 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
711 sts_entry_t *pkt; 711 sts_entry_t *pkt;
712 uint16_t handle_cnt; 712 uint16_t handle_cnt;
713 uint16_t cnt; 713 uint16_t cnt;
diff --git a/drivers/scsi/qla2xxx/qla_mbx.c b/drivers/scsi/qla2xxx/qla_mbx.c
index eeaec7c50e6a..b201971ff28e 100644
--- a/drivers/scsi/qla2xxx/qla_mbx.c
+++ b/drivers/scsi/qla2xxx/qla_mbx.c
@@ -58,7 +58,7 @@ qla2x00_mailbox_command(scsi_qla_host_t *ha, mbx_cmd_t *mcp)
58{ 58{
59 int rval; 59 int rval;
60 unsigned long flags = 0; 60 unsigned long flags = 0;
61 device_reg_t __iomem *reg = ha->iobase; 61 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
62 struct timer_list tmp_intr_timer; 62 struct timer_list tmp_intr_timer;
63 uint8_t abort_active = test_bit(ABORT_ISP_ACTIVE, &ha->dpc_flags); 63 uint8_t abort_active = test_bit(ABORT_ISP_ACTIVE, &ha->dpc_flags);
64 uint8_t io_lock_on = ha->flags.init_done; 64 uint8_t io_lock_on = ha->flags.init_done;
diff --git a/drivers/scsi/qla2xxx/qla_os.c b/drivers/scsi/qla2xxx/qla_os.c
index 549122dc68e6..328cd26e33b9 100644
--- a/drivers/scsi/qla2xxx/qla_os.c
+++ b/drivers/scsi/qla2xxx/qla_os.c
@@ -1089,7 +1089,7 @@ static void
1089qla2x00_enable_intrs(scsi_qla_host_t *ha) 1089qla2x00_enable_intrs(scsi_qla_host_t *ha)
1090{ 1090{
1091 unsigned long flags = 0; 1091 unsigned long flags = 0;
1092 device_reg_t __iomem *reg = ha->iobase; 1092 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1093 1093
1094 spin_lock_irqsave(&ha->hardware_lock, flags); 1094 spin_lock_irqsave(&ha->hardware_lock, flags);
1095 ha->interrupts_on = 1; 1095 ha->interrupts_on = 1;
@@ -1104,7 +1104,7 @@ static void
1104qla2x00_disable_intrs(scsi_qla_host_t *ha) 1104qla2x00_disable_intrs(scsi_qla_host_t *ha)
1105{ 1105{
1106 unsigned long flags = 0; 1106 unsigned long flags = 0;
1107 device_reg_t __iomem *reg = ha->iobase; 1107 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1108 1108
1109 spin_lock_irqsave(&ha->hardware_lock, flags); 1109 spin_lock_irqsave(&ha->hardware_lock, flags);
1110 ha->interrupts_on = 0; 1110 ha->interrupts_on = 0;
@@ -1120,7 +1120,7 @@ qla2x00_disable_intrs(scsi_qla_host_t *ha)
1120int qla2x00_probe_one(struct pci_dev *pdev, struct qla_board_info *brd_info) 1120int qla2x00_probe_one(struct pci_dev *pdev, struct qla_board_info *brd_info)
1121{ 1121{
1122 int ret = -ENODEV; 1122 int ret = -ENODEV;
1123 device_reg_t __iomem *reg; 1123 struct device_reg_2xxx __iomem *reg;
1124 struct Scsi_Host *host; 1124 struct Scsi_Host *host;
1125 scsi_qla_host_t *ha; 1125 scsi_qla_host_t *ha;
1126 unsigned long flags = 0; 1126 unsigned long flags = 0;
@@ -1300,7 +1300,7 @@ int qla2x00_probe_one(struct pci_dev *pdev, struct qla_board_info *brd_info)
1300 DEBUG2(printk("DEBUG: detect hba %ld at address = %p\n", 1300 DEBUG2(printk("DEBUG: detect hba %ld at address = %p\n",
1301 ha->host_no, ha)); 1301 ha->host_no, ha));
1302 1302
1303 reg = ha->iobase; 1303 reg = &ha->iobase->isp;
1304 1304
1305 ha->isp_ops.disable_intrs(ha); 1305 ha->isp_ops.disable_intrs(ha);
1306 1306
diff --git a/drivers/scsi/qla2xxx/qla_rscn.c b/drivers/scsi/qla2xxx/qla_rscn.c
index fb545b50fc2f..416fb7308e87 100644
--- a/drivers/scsi/qla2xxx/qla_rscn.c
+++ b/drivers/scsi/qla2xxx/qla_rscn.c
@@ -348,7 +348,7 @@ static inline struct mbx_entry *
348qla2x00_get_mbx_iocb_entry(scsi_qla_host_t *ha, uint32_t handle) 348qla2x00_get_mbx_iocb_entry(scsi_qla_host_t *ha, uint32_t handle)
349{ 349{
350 uint16_t cnt; 350 uint16_t cnt;
351 device_reg_t __iomem *reg = ha->iobase; 351 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
352 struct mbx_entry *mbxentry; 352 struct mbx_entry *mbxentry;
353 353
354 mbxentry = NULL; 354 mbxentry = NULL;
diff --git a/drivers/scsi/qla2xxx/qla_sup.c b/drivers/scsi/qla2xxx/qla_sup.c
index 32583bbb487f..cf2a6bc444d2 100644
--- a/drivers/scsi/qla2xxx/qla_sup.c
+++ b/drivers/scsi/qla2xxx/qla_sup.c
@@ -38,7 +38,7 @@ void
38qla2x00_lock_nvram_access(scsi_qla_host_t *ha) 38qla2x00_lock_nvram_access(scsi_qla_host_t *ha)
39{ 39{
40 uint16_t data; 40 uint16_t data;
41 device_reg_t __iomem *reg = ha->iobase; 41 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
42 42
43 if (!IS_QLA2100(ha) && !IS_QLA2200(ha) && !IS_QLA2300(ha)) { 43 if (!IS_QLA2100(ha) && !IS_QLA2200(ha) && !IS_QLA2300(ha)) {
44 data = RD_REG_WORD(&reg->nvram); 44 data = RD_REG_WORD(&reg->nvram);
@@ -70,7 +70,7 @@ qla2x00_lock_nvram_access(scsi_qla_host_t *ha)
70void 70void
71qla2x00_unlock_nvram_access(scsi_qla_host_t *ha) 71qla2x00_unlock_nvram_access(scsi_qla_host_t *ha)
72{ 72{
73 device_reg_t __iomem *reg = ha->iobase; 73 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
74 74
75 if (!IS_QLA2100(ha) && !IS_QLA2200(ha) && !IS_QLA2300(ha)) { 75 if (!IS_QLA2100(ha) && !IS_QLA2200(ha) && !IS_QLA2300(ha)) {
76 WRT_REG_WORD(&reg->u.isp2300.host_semaphore, 0); 76 WRT_REG_WORD(&reg->u.isp2300.host_semaphore, 0);
@@ -85,11 +85,9 @@ qla2x00_unlock_nvram_access(scsi_qla_host_t *ha)
85void 85void
86qla2x00_release_nvram_protection(scsi_qla_host_t *ha) 86qla2x00_release_nvram_protection(scsi_qla_host_t *ha)
87{ 87{
88 device_reg_t __iomem *reg; 88 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
89 uint32_t word; 89 uint32_t word;
90 90
91 reg = ha->iobase;
92
93 /* Release NVRAM write protection. */ 91 /* Release NVRAM write protection. */
94 if (IS_QLA2322(ha) || IS_QLA6322(ha)) { 92 if (IS_QLA2322(ha) || IS_QLA6322(ha)) {
95 /* Write enable. */ 93 /* Write enable. */
@@ -161,7 +159,7 @@ qla2x00_write_nvram_word(scsi_qla_host_t *ha, uint32_t addr, uint16_t data)
161 int count; 159 int count;
162 uint16_t word; 160 uint16_t word;
163 uint32_t nv_cmd; 161 uint32_t nv_cmd;
164 device_reg_t __iomem *reg = ha->iobase; 162 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
165 163
166 qla2x00_nv_write(ha, NVR_DATA_OUT); 164 qla2x00_nv_write(ha, NVR_DATA_OUT);
167 qla2x00_nv_write(ha, 0); 165 qla2x00_nv_write(ha, 0);
@@ -223,7 +221,7 @@ static uint16_t
223qla2x00_nvram_request(scsi_qla_host_t *ha, uint32_t nv_cmd) 221qla2x00_nvram_request(scsi_qla_host_t *ha, uint32_t nv_cmd)
224{ 222{
225 uint8_t cnt; 223 uint8_t cnt;
226 device_reg_t __iomem *reg = ha->iobase; 224 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
227 uint16_t data = 0; 225 uint16_t data = 0;
228 uint16_t reg_data; 226 uint16_t reg_data;
229 227
@@ -265,7 +263,7 @@ qla2x00_nvram_request(scsi_qla_host_t *ha, uint32_t nv_cmd)
265static void 263static void
266qla2x00_nv_deselect(scsi_qla_host_t *ha) 264qla2x00_nv_deselect(scsi_qla_host_t *ha)
267{ 265{
268 device_reg_t __iomem *reg = ha->iobase; 266 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
269 267
270 WRT_REG_WORD(&reg->nvram, NVR_DESELECT); 268 WRT_REG_WORD(&reg->nvram, NVR_DESELECT);
271 RD_REG_WORD(&reg->nvram); /* PCI Posting. */ 269 RD_REG_WORD(&reg->nvram); /* PCI Posting. */
@@ -280,7 +278,7 @@ qla2x00_nv_deselect(scsi_qla_host_t *ha)
280static void 278static void
281qla2x00_nv_write(scsi_qla_host_t *ha, uint16_t data) 279qla2x00_nv_write(scsi_qla_host_t *ha, uint16_t data)
282{ 280{
283 device_reg_t __iomem *reg = ha->iobase; 281 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
284 282
285 WRT_REG_WORD(&reg->nvram, data | NVR_SELECT | NVR_WRT_ENABLE); 283 WRT_REG_WORD(&reg->nvram, data | NVR_SELECT | NVR_WRT_ENABLE);
286 RD_REG_WORD(&reg->nvram); /* PCI Posting. */ 284 RD_REG_WORD(&reg->nvram); /* PCI Posting. */
generated by cgit v1.2.2 (git 2.25.0) at 2024-10-09 14:15:53 -0400