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authorEd Lin <ed.lin@promise.com>2006-12-04 20:49:42 -0500
committerJames Bottomley <jejb@mulgrave.il.steeleye.com>2006-12-05 12:33:38 -0500
commit76fbf96f82636c8cdc40485506c50c880fd45a56 (patch)
treedb77fbcf17433f041fabdcbbaa52336c0eccf0be /drivers/scsi/stex.c
parent94e9108b5ad8da9c02ebf5183b861f1717409555 (diff)
[SCSI] stex: change wait loop code
The original wait loop may be much longer than intended time. Use more accurate timer_after for it. Also adjust wait value to avoid unnecessary long waiting. Signed-off-by: Ed Lin <ed.lin@promise.com> Signed-off-by: James Bottomley <James.Bottomley@SteelEye.com>
Diffstat (limited to 'drivers/scsi/stex.c')
-rw-r--r--drivers/scsi/stex.c41
1 files changed, 20 insertions, 21 deletions
diff --git a/drivers/scsi/stex.c b/drivers/scsi/stex.c
index bfd7983045b7..7edbcc9bc9d6 100644
--- a/drivers/scsi/stex.c
+++ b/drivers/scsi/stex.c
@@ -76,9 +76,10 @@ enum {
76 MU_STATE_STARTED = 4, 76 MU_STATE_STARTED = 4,
77 MU_STATE_RESETTING = 5, 77 MU_STATE_RESETTING = 5,
78 78
79 MU_MAX_DELAY_TIME = 240000, 79 MU_MAX_DELAY = 120,
80 MU_HANDSHAKE_SIGNATURE = 0x55aaaa55, 80 MU_HANDSHAKE_SIGNATURE = 0x55aaaa55,
81 MU_HANDSHAKE_SIGNATURE_HALF = 0x5a5a0000, 81 MU_HANDSHAKE_SIGNATURE_HALF = 0x5a5a0000,
82 MU_HARD_RESET_WAIT = 30000,
82 HMU_PARTNER_TYPE = 2, 83 HMU_PARTNER_TYPE = 2,
83 84
84 /* firmware returned values */ 85 /* firmware returned values */
@@ -910,23 +911,22 @@ static int stex_handshake(struct st_hba *hba)
910 struct handshake_frame *h; 911 struct handshake_frame *h;
911 dma_addr_t status_phys; 912 dma_addr_t status_phys;
912 u32 data; 913 u32 data;
913 int i; 914 unsigned long before;
914 915
915 if (readl(base + OMR0) != MU_HANDSHAKE_SIGNATURE) { 916 if (readl(base + OMR0) != MU_HANDSHAKE_SIGNATURE) {
916 writel(MU_INBOUND_DOORBELL_HANDSHAKE, base + IDBL); 917 writel(MU_INBOUND_DOORBELL_HANDSHAKE, base + IDBL);
917 readl(base + IDBL); 918 readl(base + IDBL);
918 for (i = 0; readl(base + OMR0) != MU_HANDSHAKE_SIGNATURE 919 before = jiffies;
919 && i < MU_MAX_DELAY_TIME; i++) { 920 while (readl(base + OMR0) != MU_HANDSHAKE_SIGNATURE) {
921 if (time_after(jiffies, before + MU_MAX_DELAY * HZ)) {
922 printk(KERN_ERR DRV_NAME
923 "(%s): no handshake signature\n",
924 pci_name(hba->pdev));
925 return -1;
926 }
920 rmb(); 927 rmb();
921 msleep(1); 928 msleep(1);
922 } 929 }
923
924 if (i == MU_MAX_DELAY_TIME) {
925 printk(KERN_ERR DRV_NAME
926 "(%s): no handshake signature\n",
927 pci_name(hba->pdev));
928 return -1;
929 }
930 } 930 }
931 931
932 udelay(10); 932 udelay(10);
@@ -965,19 +965,18 @@ static int stex_handshake(struct st_hba *hba)
965 readl(base + IDBL); /* flush */ 965 readl(base + IDBL); /* flush */
966 966
967 udelay(10); 967 udelay(10);
968 for (i = 0; readl(base + OMR0) != MU_HANDSHAKE_SIGNATURE 968 before = jiffies;
969 && i < MU_MAX_DELAY_TIME; i++) { 969 while (readl(base + OMR0) != MU_HANDSHAKE_SIGNATURE) {
970 if (time_after(jiffies, before + MU_MAX_DELAY * HZ)) {
971 printk(KERN_ERR DRV_NAME
972 "(%s): no signature after handshake frame\n",
973 pci_name(hba->pdev));
974 return -1;
975 }
970 rmb(); 976 rmb();
971 msleep(1); 977 msleep(1);
972 } 978 }
973 979
974 if (i == MU_MAX_DELAY_TIME) {
975 printk(KERN_ERR DRV_NAME
976 "(%s): no signature after handshake frame\n",
977 pci_name(hba->pdev));
978 return -1;
979 }
980
981 writel(0, base + IMR0); 980 writel(0, base + IMR0);
982 readl(base + IMR0); 981 readl(base + IMR0);
983 writel(0, base + OMR0); 982 writel(0, base + OMR0);
@@ -1059,7 +1058,7 @@ static void stex_hard_reset(struct st_hba *hba)
1059 pci_bctl &= ~PCI_BRIDGE_CTL_BUS_RESET; 1058 pci_bctl &= ~PCI_BRIDGE_CTL_BUS_RESET;
1060 pci_write_config_byte(bus->self, PCI_BRIDGE_CONTROL, pci_bctl); 1059 pci_write_config_byte(bus->self, PCI_BRIDGE_CONTROL, pci_bctl);
1061 1060
1062 for (i = 0; i < MU_MAX_DELAY_TIME; i++) { 1061 for (i = 0; i < MU_HARD_RESET_WAIT; i++) {
1063 pci_read_config_word(hba->pdev, PCI_COMMAND, &pci_cmd); 1062 pci_read_config_word(hba->pdev, PCI_COMMAND, &pci_cmd);
1064 if (pci_cmd != 0xffff && (pci_cmd & PCI_COMMAND_MASTER)) 1063 if (pci_cmd != 0xffff && (pci_cmd & PCI_COMMAND_MASTER))
1065 break; 1064 break;