diff options
author | Vikas Chaudhary <vikas.chaudhary@qlogic.com> | 2012-08-22 09:14:24 -0400 |
---|---|---|
committer | James Bottomley <JBottomley@Parallels.com> | 2012-09-24 04:11:06 -0400 |
commit | de8c72daa027dd71b4c7ac7db4324e9471c52429 (patch) | |
tree | f5a8c2cf85477f37adba1f972ef841b496c847be /drivers/scsi/qla4xxx | |
parent | 5e9bcec792419d335555784a1b99d4331030d18e (diff) |
[SCSI] qla4xxx: Rename 82XX macros
Signed-off-by: Vikas Chaudhary <vikas.chaudhary@qlogic.com>
Reviewed-by: Mike Christie <michaelc@cs.wisc.edu>
Signed-off-by: James Bottomley <JBottomley@Parallels.com>
Diffstat (limited to 'drivers/scsi/qla4xxx')
-rw-r--r-- | drivers/scsi/qla4xxx/ql4_attr.c | 6 | ||||
-rw-r--r-- | drivers/scsi/qla4xxx/ql4_def.h | 2 | ||||
-rw-r--r-- | drivers/scsi/qla4xxx/ql4_fw.h | 10 | ||||
-rw-r--r-- | drivers/scsi/qla4xxx/ql4_mbx.c | 2 | ||||
-rw-r--r-- | drivers/scsi/qla4xxx/ql4_nx.c | 152 | ||||
-rw-r--r-- | drivers/scsi/qla4xxx/ql4_nx.h | 86 | ||||
-rw-r--r-- | drivers/scsi/qla4xxx/ql4_os.c | 20 |
7 files changed, 139 insertions, 139 deletions
diff --git a/drivers/scsi/qla4xxx/ql4_attr.c b/drivers/scsi/qla4xxx/ql4_attr.c index d991799817d0..71b44f087148 100644 --- a/drivers/scsi/qla4xxx/ql4_attr.c +++ b/drivers/scsi/qla4xxx/ql4_attr.c | |||
@@ -77,13 +77,13 @@ qla4_8xxx_sysfs_write_fw_dump(struct file *filep, struct kobject *kobj, | |||
77 | /* Reset HBA */ | 77 | /* Reset HBA */ |
78 | qla4_82xx_idc_lock(ha); | 78 | qla4_82xx_idc_lock(ha); |
79 | dev_state = qla4_82xx_rd_32(ha, QLA82XX_CRB_DEV_STATE); | 79 | dev_state = qla4_82xx_rd_32(ha, QLA82XX_CRB_DEV_STATE); |
80 | if (dev_state == QLA82XX_DEV_READY) { | 80 | if (dev_state == QLA8XXX_DEV_READY) { |
81 | ql4_printk(KERN_INFO, ha, | 81 | ql4_printk(KERN_INFO, ha, |
82 | "%s: Setting Need reset, reset_owner is 0x%x.\n", | 82 | "%s: Setting Need reset, reset_owner is 0x%x.\n", |
83 | __func__, ha->func_num); | 83 | __func__, ha->func_num); |
84 | qla4_82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE, | 84 | qla4_82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE, |
85 | QLA82XX_DEV_NEED_RESET); | 85 | QLA8XXX_DEV_NEED_RESET); |
86 | set_bit(AF_82XX_RST_OWNER, &ha->flags); | 86 | set_bit(AF_8XXX_RST_OWNER, &ha->flags); |
87 | } else | 87 | } else |
88 | ql4_printk(KERN_INFO, ha, | 88 | ql4_printk(KERN_INFO, ha, |
89 | "%s: Reset not performed as device state is 0x%x\n", | 89 | "%s: Reset not performed as device state is 0x%x\n", |
diff --git a/drivers/scsi/qla4xxx/ql4_def.h b/drivers/scsi/qla4xxx/ql4_def.h index 1d6d1a9db0b8..82f70db08078 100644 --- a/drivers/scsi/qla4xxx/ql4_def.h +++ b/drivers/scsi/qla4xxx/ql4_def.h | |||
@@ -497,7 +497,7 @@ struct scsi_qla_host { | |||
497 | #define AF_PCI_CHANNEL_IO_PERM_FAILURE 21 /* 0x00200000 */ | 497 | #define AF_PCI_CHANNEL_IO_PERM_FAILURE 21 /* 0x00200000 */ |
498 | #define AF_BUILD_DDB_LIST 22 /* 0x00400000 */ | 498 | #define AF_BUILD_DDB_LIST 22 /* 0x00400000 */ |
499 | #define AF_82XX_FW_DUMPED 24 /* 0x01000000 */ | 499 | #define AF_82XX_FW_DUMPED 24 /* 0x01000000 */ |
500 | #define AF_82XX_RST_OWNER 25 /* 0x02000000 */ | 500 | #define AF_8XXX_RST_OWNER 25 /* 0x02000000 */ |
501 | #define AF_82XX_DUMP_READING 26 /* 0x04000000 */ | 501 | #define AF_82XX_DUMP_READING 26 /* 0x04000000 */ |
502 | 502 | ||
503 | unsigned long dpc_flags; | 503 | unsigned long dpc_flags; |
diff --git a/drivers/scsi/qla4xxx/ql4_fw.h b/drivers/scsi/qla4xxx/ql4_fw.h index 7240948fb929..037d38016c0a 100644 --- a/drivers/scsi/qla4xxx/ql4_fw.h +++ b/drivers/scsi/qla4xxx/ql4_fw.h | |||
@@ -1195,9 +1195,9 @@ struct ql_iscsi_stats { | |||
1195 | uint8_t reserved2[264]; /* 0x0308 - 0x040F */ | 1195 | uint8_t reserved2[264]; /* 0x0308 - 0x040F */ |
1196 | }; | 1196 | }; |
1197 | 1197 | ||
1198 | #define QLA82XX_DBG_STATE_ARRAY_LEN 16 | 1198 | #define QLA8XXX_DBG_STATE_ARRAY_LEN 16 |
1199 | #define QLA82XX_DBG_CAP_SIZE_ARRAY_LEN 8 | 1199 | #define QLA8XXX_DBG_CAP_SIZE_ARRAY_LEN 8 |
1200 | #define QLA82XX_DBG_RSVD_ARRAY_LEN 8 | 1200 | #define QLA8XXX_DBG_RSVD_ARRAY_LEN 8 |
1201 | 1201 | ||
1202 | struct qla4_8xxx_minidump_template_hdr { | 1202 | struct qla4_8xxx_minidump_template_hdr { |
1203 | uint32_t entry_type; | 1203 | uint32_t entry_type; |
@@ -1214,8 +1214,8 @@ struct qla4_8xxx_minidump_template_hdr { | |||
1214 | uint32_t driver_info_word3; | 1214 | uint32_t driver_info_word3; |
1215 | uint32_t driver_info_word4; | 1215 | uint32_t driver_info_word4; |
1216 | 1216 | ||
1217 | uint32_t saved_state_array[QLA82XX_DBG_STATE_ARRAY_LEN]; | 1217 | uint32_t saved_state_array[QLA8XXX_DBG_STATE_ARRAY_LEN]; |
1218 | uint32_t capture_size_array[QLA82XX_DBG_CAP_SIZE_ARRAY_LEN]; | 1218 | uint32_t capture_size_array[QLA8XXX_DBG_CAP_SIZE_ARRAY_LEN]; |
1219 | }; | 1219 | }; |
1220 | 1220 | ||
1221 | #endif /* _QLA4X_FW_H */ | 1221 | #endif /* _QLA4X_FW_H */ |
diff --git a/drivers/scsi/qla4xxx/ql4_mbx.c b/drivers/scsi/qla4xxx/ql4_mbx.c index e99b67167339..ea08e527faf7 100644 --- a/drivers/scsi/qla4xxx/ql4_mbx.c +++ b/drivers/scsi/qla4xxx/ql4_mbx.c | |||
@@ -88,7 +88,7 @@ int qla4xxx_mailbox_command(struct scsi_qla_host *ha, uint8_t inCount, | |||
88 | qla4_82xx_idc_lock(ha); | 88 | qla4_82xx_idc_lock(ha); |
89 | dev_state = qla4_82xx_rd_32(ha, QLA82XX_CRB_DEV_STATE); | 89 | dev_state = qla4_82xx_rd_32(ha, QLA82XX_CRB_DEV_STATE); |
90 | qla4_82xx_idc_unlock(ha); | 90 | qla4_82xx_idc_unlock(ha); |
91 | if (dev_state == QLA82XX_DEV_FAILED) { | 91 | if (dev_state == QLA8XXX_DEV_FAILED) { |
92 | ql4_printk(KERN_WARNING, ha, | 92 | ql4_printk(KERN_WARNING, ha, |
93 | "scsi%ld: %s: H/W is in failed state, do not send any mailbox commands\n", | 93 | "scsi%ld: %s: H/W is in failed state, do not send any mailbox commands\n", |
94 | ha->host_no, __func__); | 94 | ha->host_no, __func__); |
diff --git a/drivers/scsi/qla4xxx/ql4_nx.c b/drivers/scsi/qla4xxx/ql4_nx.c index 7764c3ff02fc..e4801845b769 100644 --- a/drivers/scsi/qla4xxx/ql4_nx.c +++ b/drivers/scsi/qla4xxx/ql4_nx.c | |||
@@ -563,7 +563,7 @@ qla4_82xx_pci_get_crb_addr_2M(struct scsi_qla_host *ha, ulong *off) | |||
563 | } | 563 | } |
564 | 564 | ||
565 | /* PCI Windowing for DDR regions. */ | 565 | /* PCI Windowing for DDR regions. */ |
566 | #define QLA82XX_ADDR_IN_RANGE(addr, low, high) \ | 566 | #define QLA8XXX_ADDR_IN_RANGE(addr, low, high) \ |
567 | (((addr) <= (high)) && ((addr) >= (low))) | 567 | (((addr) <= (high)) && ((addr) >= (low))) |
568 | 568 | ||
569 | /* | 569 | /* |
@@ -574,10 +574,10 @@ static unsigned long | |||
574 | qla4_82xx_pci_mem_bound_check(struct scsi_qla_host *ha, | 574 | qla4_82xx_pci_mem_bound_check(struct scsi_qla_host *ha, |
575 | unsigned long long addr, int size) | 575 | unsigned long long addr, int size) |
576 | { | 576 | { |
577 | if (!QLA82XX_ADDR_IN_RANGE(addr, QLA82XX_ADDR_DDR_NET, | 577 | if (!QLA8XXX_ADDR_IN_RANGE(addr, QLA8XXX_ADDR_DDR_NET, |
578 | QLA82XX_ADDR_DDR_NET_MAX) || | 578 | QLA8XXX_ADDR_DDR_NET_MAX) || |
579 | !QLA82XX_ADDR_IN_RANGE(addr + size - 1, | 579 | !QLA8XXX_ADDR_IN_RANGE(addr + size - 1, |
580 | QLA82XX_ADDR_DDR_NET, QLA82XX_ADDR_DDR_NET_MAX) || | 580 | QLA8XXX_ADDR_DDR_NET, QLA8XXX_ADDR_DDR_NET_MAX) || |
581 | ((size != 1) && (size != 2) && (size != 4) && (size != 8))) { | 581 | ((size != 1) && (size != 2) && (size != 4) && (size != 8))) { |
582 | return 0; | 582 | return 0; |
583 | } | 583 | } |
@@ -592,8 +592,8 @@ qla4_82xx_pci_set_window(struct scsi_qla_host *ha, unsigned long long addr) | |||
592 | int window; | 592 | int window; |
593 | u32 win_read; | 593 | u32 win_read; |
594 | 594 | ||
595 | if (QLA82XX_ADDR_IN_RANGE(addr, QLA82XX_ADDR_DDR_NET, | 595 | if (QLA8XXX_ADDR_IN_RANGE(addr, QLA8XXX_ADDR_DDR_NET, |
596 | QLA82XX_ADDR_DDR_NET_MAX)) { | 596 | QLA8XXX_ADDR_DDR_NET_MAX)) { |
597 | /* DDR network side */ | 597 | /* DDR network side */ |
598 | window = MN_WIN(addr); | 598 | window = MN_WIN(addr); |
599 | ha->ddr_mn_window = window; | 599 | ha->ddr_mn_window = window; |
@@ -607,8 +607,8 @@ qla4_82xx_pci_set_window(struct scsi_qla_host *ha, unsigned long long addr) | |||
607 | __func__, window, win_read); | 607 | __func__, window, win_read); |
608 | } | 608 | } |
609 | addr = GET_MEM_OFFS_2M(addr) + QLA82XX_PCI_DDR_NET; | 609 | addr = GET_MEM_OFFS_2M(addr) + QLA82XX_PCI_DDR_NET; |
610 | } else if (QLA82XX_ADDR_IN_RANGE(addr, QLA82XX_ADDR_OCM0, | 610 | } else if (QLA8XXX_ADDR_IN_RANGE(addr, QLA8XXX_ADDR_OCM0, |
611 | QLA82XX_ADDR_OCM0_MAX)) { | 611 | QLA8XXX_ADDR_OCM0_MAX)) { |
612 | unsigned int temp1; | 612 | unsigned int temp1; |
613 | /* if bits 19:18&17:11 are on */ | 613 | /* if bits 19:18&17:11 are on */ |
614 | if ((addr & 0x00ff800) == 0xff800) { | 614 | if ((addr & 0x00ff800) == 0xff800) { |
@@ -630,7 +630,7 @@ qla4_82xx_pci_set_window(struct scsi_qla_host *ha, unsigned long long addr) | |||
630 | } | 630 | } |
631 | addr = GET_MEM_OFFS_2M(addr) + QLA82XX_PCI_OCM0_2M; | 631 | addr = GET_MEM_OFFS_2M(addr) + QLA82XX_PCI_OCM0_2M; |
632 | 632 | ||
633 | } else if (QLA82XX_ADDR_IN_RANGE(addr, QLA82XX_ADDR_QDR_NET, | 633 | } else if (QLA8XXX_ADDR_IN_RANGE(addr, QLA8XXX_ADDR_QDR_NET, |
634 | QLA82XX_P3_ADDR_QDR_NET_MAX)) { | 634 | QLA82XX_P3_ADDR_QDR_NET_MAX)) { |
635 | /* QDR network side */ | 635 | /* QDR network side */ |
636 | window = MS_WIN(addr); | 636 | window = MS_WIN(addr); |
@@ -669,20 +669,20 @@ static int qla4_82xx_pci_is_same_window(struct scsi_qla_host *ha, | |||
669 | 669 | ||
670 | qdr_max = QLA82XX_P3_ADDR_QDR_NET_MAX; | 670 | qdr_max = QLA82XX_P3_ADDR_QDR_NET_MAX; |
671 | 671 | ||
672 | if (QLA82XX_ADDR_IN_RANGE(addr, QLA82XX_ADDR_DDR_NET, | 672 | if (QLA8XXX_ADDR_IN_RANGE(addr, QLA8XXX_ADDR_DDR_NET, |
673 | QLA82XX_ADDR_DDR_NET_MAX)) { | 673 | QLA8XXX_ADDR_DDR_NET_MAX)) { |
674 | /* DDR network side */ | 674 | /* DDR network side */ |
675 | BUG(); /* MN access can not come here */ | 675 | BUG(); /* MN access can not come here */ |
676 | } else if (QLA82XX_ADDR_IN_RANGE(addr, QLA82XX_ADDR_OCM0, | 676 | } else if (QLA8XXX_ADDR_IN_RANGE(addr, QLA8XXX_ADDR_OCM0, |
677 | QLA82XX_ADDR_OCM0_MAX)) { | 677 | QLA8XXX_ADDR_OCM0_MAX)) { |
678 | return 1; | 678 | return 1; |
679 | } else if (QLA82XX_ADDR_IN_RANGE(addr, QLA82XX_ADDR_OCM1, | 679 | } else if (QLA8XXX_ADDR_IN_RANGE(addr, QLA8XXX_ADDR_OCM1, |
680 | QLA82XX_ADDR_OCM1_MAX)) { | 680 | QLA8XXX_ADDR_OCM1_MAX)) { |
681 | return 1; | 681 | return 1; |
682 | } else if (QLA82XX_ADDR_IN_RANGE(addr, QLA82XX_ADDR_QDR_NET, | 682 | } else if (QLA8XXX_ADDR_IN_RANGE(addr, QLA8XXX_ADDR_QDR_NET, |
683 | qdr_max)) { | 683 | qdr_max)) { |
684 | /* QDR network side */ | 684 | /* QDR network side */ |
685 | window = ((addr - QLA82XX_ADDR_QDR_NET) >> 22) & 0x3f; | 685 | window = ((addr - QLA8XXX_ADDR_QDR_NET) >> 22) & 0x3f; |
686 | if (ha->qdr_sn_window == window) | 686 | if (ha->qdr_sn_window == window) |
687 | return 1; | 687 | return 1; |
688 | } | 688 | } |
@@ -1250,7 +1250,7 @@ qla4_82xx_pci_mem_read_2M(struct scsi_qla_host *ha, | |||
1250 | * If not MN, go check for MS or invalid. | 1250 | * If not MN, go check for MS or invalid. |
1251 | */ | 1251 | */ |
1252 | 1252 | ||
1253 | if (off >= QLA82XX_ADDR_QDR_NET && off <= QLA82XX_P3_ADDR_QDR_NET_MAX) | 1253 | if (off >= QLA8XXX_ADDR_QDR_NET && off <= QLA82XX_P3_ADDR_QDR_NET_MAX) |
1254 | mem_crb = QLA82XX_CRB_QDR_NET; | 1254 | mem_crb = QLA82XX_CRB_QDR_NET; |
1255 | else { | 1255 | else { |
1256 | mem_crb = QLA82XX_CRB_DDR_NET; | 1256 | mem_crb = QLA82XX_CRB_DDR_NET; |
@@ -1340,7 +1340,7 @@ qla4_82xx_pci_mem_write_2M(struct scsi_qla_host *ha, | |||
1340 | /* | 1340 | /* |
1341 | * If not MN, go check for MS or invalid. | 1341 | * If not MN, go check for MS or invalid. |
1342 | */ | 1342 | */ |
1343 | if (off >= QLA82XX_ADDR_QDR_NET && off <= QLA82XX_P3_ADDR_QDR_NET_MAX) | 1343 | if (off >= QLA8XXX_ADDR_QDR_NET && off <= QLA82XX_P3_ADDR_QDR_NET_MAX) |
1344 | mem_crb = QLA82XX_CRB_QDR_NET; | 1344 | mem_crb = QLA82XX_CRB_QDR_NET; |
1345 | else { | 1345 | else { |
1346 | mem_crb = QLA82XX_CRB_DDR_NET; | 1346 | mem_crb = QLA82XX_CRB_DDR_NET; |
@@ -1744,33 +1744,33 @@ static int qla4_8xxx_minidump_process_control(struct scsi_qla_host *ha, | |||
1744 | crb_addr = crb_entry->addr; | 1744 | crb_addr = crb_entry->addr; |
1745 | for (i = 0; i < crb_entry->op_count; i++) { | 1745 | for (i = 0; i < crb_entry->op_count; i++) { |
1746 | opcode = crb_entry->crb_ctrl.opcode; | 1746 | opcode = crb_entry->crb_ctrl.opcode; |
1747 | if (opcode & QLA82XX_DBG_OPCODE_WR) { | 1747 | if (opcode & QLA8XXX_DBG_OPCODE_WR) { |
1748 | qla4_8xxx_md_rw_32(ha, crb_addr, | 1748 | qla4_8xxx_md_rw_32(ha, crb_addr, |
1749 | crb_entry->value_1, 1); | 1749 | crb_entry->value_1, 1); |
1750 | opcode &= ~QLA82XX_DBG_OPCODE_WR; | 1750 | opcode &= ~QLA8XXX_DBG_OPCODE_WR; |
1751 | } | 1751 | } |
1752 | if (opcode & QLA82XX_DBG_OPCODE_RW) { | 1752 | if (opcode & QLA8XXX_DBG_OPCODE_RW) { |
1753 | read_value = qla4_8xxx_md_rw_32(ha, crb_addr, 0, 0); | 1753 | read_value = qla4_8xxx_md_rw_32(ha, crb_addr, 0, 0); |
1754 | qla4_8xxx_md_rw_32(ha, crb_addr, read_value, 1); | 1754 | qla4_8xxx_md_rw_32(ha, crb_addr, read_value, 1); |
1755 | opcode &= ~QLA82XX_DBG_OPCODE_RW; | 1755 | opcode &= ~QLA8XXX_DBG_OPCODE_RW; |
1756 | } | 1756 | } |
1757 | if (opcode & QLA82XX_DBG_OPCODE_AND) { | 1757 | if (opcode & QLA8XXX_DBG_OPCODE_AND) { |
1758 | read_value = qla4_8xxx_md_rw_32(ha, crb_addr, 0, 0); | 1758 | read_value = qla4_8xxx_md_rw_32(ha, crb_addr, 0, 0); |
1759 | read_value &= crb_entry->value_2; | 1759 | read_value &= crb_entry->value_2; |
1760 | opcode &= ~QLA82XX_DBG_OPCODE_AND; | 1760 | opcode &= ~QLA8XXX_DBG_OPCODE_AND; |
1761 | if (opcode & QLA82XX_DBG_OPCODE_OR) { | 1761 | if (opcode & QLA8XXX_DBG_OPCODE_OR) { |
1762 | read_value |= crb_entry->value_3; | 1762 | read_value |= crb_entry->value_3; |
1763 | opcode &= ~QLA82XX_DBG_OPCODE_OR; | 1763 | opcode &= ~QLA8XXX_DBG_OPCODE_OR; |
1764 | } | 1764 | } |
1765 | qla4_8xxx_md_rw_32(ha, crb_addr, read_value, 1); | 1765 | qla4_8xxx_md_rw_32(ha, crb_addr, read_value, 1); |
1766 | } | 1766 | } |
1767 | if (opcode & QLA82XX_DBG_OPCODE_OR) { | 1767 | if (opcode & QLA8XXX_DBG_OPCODE_OR) { |
1768 | read_value = qla4_8xxx_md_rw_32(ha, crb_addr, 0, 0); | 1768 | read_value = qla4_8xxx_md_rw_32(ha, crb_addr, 0, 0); |
1769 | read_value |= crb_entry->value_3; | 1769 | read_value |= crb_entry->value_3; |
1770 | qla4_8xxx_md_rw_32(ha, crb_addr, read_value, 1); | 1770 | qla4_8xxx_md_rw_32(ha, crb_addr, read_value, 1); |
1771 | opcode &= ~QLA82XX_DBG_OPCODE_OR; | 1771 | opcode &= ~QLA8XXX_DBG_OPCODE_OR; |
1772 | } | 1772 | } |
1773 | if (opcode & QLA82XX_DBG_OPCODE_POLL) { | 1773 | if (opcode & QLA8XXX_DBG_OPCODE_POLL) { |
1774 | poll_time = crb_entry->crb_strd.poll_timeout; | 1774 | poll_time = crb_entry->crb_strd.poll_timeout; |
1775 | wtime = jiffies + poll_time; | 1775 | wtime = jiffies + poll_time; |
1776 | read_value = qla4_8xxx_md_rw_32(ha, crb_addr, 0, 0); | 1776 | read_value = qla4_8xxx_md_rw_32(ha, crb_addr, 0, 0); |
@@ -1787,10 +1787,10 @@ static int qla4_8xxx_minidump_process_control(struct scsi_qla_host *ha, | |||
1787 | read_value = qla4_8xxx_md_rw_32(ha, | 1787 | read_value = qla4_8xxx_md_rw_32(ha, |
1788 | crb_addr, 0, 0); | 1788 | crb_addr, 0, 0); |
1789 | } while (1); | 1789 | } while (1); |
1790 | opcode &= ~QLA82XX_DBG_OPCODE_POLL; | 1790 | opcode &= ~QLA8XXX_DBG_OPCODE_POLL; |
1791 | } | 1791 | } |
1792 | 1792 | ||
1793 | if (opcode & QLA82XX_DBG_OPCODE_RDSTATE) { | 1793 | if (opcode & QLA8XXX_DBG_OPCODE_RDSTATE) { |
1794 | if (crb_entry->crb_strd.state_index_a) { | 1794 | if (crb_entry->crb_strd.state_index_a) { |
1795 | index = crb_entry->crb_strd.state_index_a; | 1795 | index = crb_entry->crb_strd.state_index_a; |
1796 | addr = tmplt_hdr->saved_state_array[index]; | 1796 | addr = tmplt_hdr->saved_state_array[index]; |
@@ -1801,10 +1801,10 @@ static int qla4_8xxx_minidump_process_control(struct scsi_qla_host *ha, | |||
1801 | read_value = qla4_8xxx_md_rw_32(ha, addr, 0, 0); | 1801 | read_value = qla4_8xxx_md_rw_32(ha, addr, 0, 0); |
1802 | index = crb_entry->crb_ctrl.state_index_v; | 1802 | index = crb_entry->crb_ctrl.state_index_v; |
1803 | tmplt_hdr->saved_state_array[index] = read_value; | 1803 | tmplt_hdr->saved_state_array[index] = read_value; |
1804 | opcode &= ~QLA82XX_DBG_OPCODE_RDSTATE; | 1804 | opcode &= ~QLA8XXX_DBG_OPCODE_RDSTATE; |
1805 | } | 1805 | } |
1806 | 1806 | ||
1807 | if (opcode & QLA82XX_DBG_OPCODE_WRSTATE) { | 1807 | if (opcode & QLA8XXX_DBG_OPCODE_WRSTATE) { |
1808 | if (crb_entry->crb_strd.state_index_a) { | 1808 | if (crb_entry->crb_strd.state_index_a) { |
1809 | index = crb_entry->crb_strd.state_index_a; | 1809 | index = crb_entry->crb_strd.state_index_a; |
1810 | addr = tmplt_hdr->saved_state_array[index]; | 1810 | addr = tmplt_hdr->saved_state_array[index]; |
@@ -1821,10 +1821,10 @@ static int qla4_8xxx_minidump_process_control(struct scsi_qla_host *ha, | |||
1821 | } | 1821 | } |
1822 | 1822 | ||
1823 | qla4_8xxx_md_rw_32(ha, addr, read_value, 1); | 1823 | qla4_8xxx_md_rw_32(ha, addr, read_value, 1); |
1824 | opcode &= ~QLA82XX_DBG_OPCODE_WRSTATE; | 1824 | opcode &= ~QLA8XXX_DBG_OPCODE_WRSTATE; |
1825 | } | 1825 | } |
1826 | 1826 | ||
1827 | if (opcode & QLA82XX_DBG_OPCODE_MDSTATE) { | 1827 | if (opcode & QLA8XXX_DBG_OPCODE_MDSTATE) { |
1828 | index = crb_entry->crb_ctrl.state_index_v; | 1828 | index = crb_entry->crb_ctrl.state_index_v; |
1829 | read_value = tmplt_hdr->saved_state_array[index]; | 1829 | read_value = tmplt_hdr->saved_state_array[index]; |
1830 | read_value <<= crb_entry->crb_ctrl.shl; | 1830 | read_value <<= crb_entry->crb_ctrl.shl; |
@@ -1834,7 +1834,7 @@ static int qla4_8xxx_minidump_process_control(struct scsi_qla_host *ha, | |||
1834 | read_value |= crb_entry->value_3; | 1834 | read_value |= crb_entry->value_3; |
1835 | read_value += crb_entry->value_1; | 1835 | read_value += crb_entry->value_1; |
1836 | tmplt_hdr->saved_state_array[index] = read_value; | 1836 | tmplt_hdr->saved_state_array[index] = read_value; |
1837 | opcode &= ~QLA82XX_DBG_OPCODE_MDSTATE; | 1837 | opcode &= ~QLA8XXX_DBG_OPCODE_MDSTATE; |
1838 | } | 1838 | } |
1839 | crb_addr += crb_entry->crb_strd.addr_stride; | 1839 | crb_addr += crb_entry->crb_strd.addr_stride; |
1840 | } | 1840 | } |
@@ -2081,7 +2081,7 @@ static void qla4_8xxx_mark_entry_skipped(struct scsi_qla_host *ha, | |||
2081 | struct qla8xxx_minidump_entry_hdr *entry_hdr, | 2081 | struct qla8xxx_minidump_entry_hdr *entry_hdr, |
2082 | int index) | 2082 | int index) |
2083 | { | 2083 | { |
2084 | entry_hdr->d_ctrl.driver_flags |= QLA82XX_DBG_SKIPPED_FLAG; | 2084 | entry_hdr->d_ctrl.driver_flags |= QLA8XXX_DBG_SKIPPED_FLAG; |
2085 | DEBUG2(ql4_printk(KERN_INFO, ha, | 2085 | DEBUG2(ql4_printk(KERN_INFO, ha, |
2086 | "scsi(%ld): Skipping entry[%d]: ETYPE[0x%x]-ELEVEL[0x%x]\n", | 2086 | "scsi(%ld): Skipping entry[%d]: ETYPE[0x%x]-ELEVEL[0x%x]\n", |
2087 | ha->host_no, index, entry_hdr->entry_type, | 2087 | ha->host_no, index, entry_hdr->entry_type, |
@@ -2147,7 +2147,7 @@ static int qla4_8xxx_collect_md_data(struct scsi_qla_host *ha) | |||
2147 | if (!(entry_hdr->d_ctrl.entry_capture_mask & | 2147 | if (!(entry_hdr->d_ctrl.entry_capture_mask & |
2148 | ha->fw_dump_capture_mask)) { | 2148 | ha->fw_dump_capture_mask)) { |
2149 | entry_hdr->d_ctrl.driver_flags |= | 2149 | entry_hdr->d_ctrl.driver_flags |= |
2150 | QLA82XX_DBG_SKIPPED_FLAG; | 2150 | QLA8XXX_DBG_SKIPPED_FLAG; |
2151 | goto skip_nxt_entry; | 2151 | goto skip_nxt_entry; |
2152 | } | 2152 | } |
2153 | 2153 | ||
@@ -2160,10 +2160,10 @@ static int qla4_8xxx_collect_md_data(struct scsi_qla_host *ha) | |||
2160 | * debug data | 2160 | * debug data |
2161 | */ | 2161 | */ |
2162 | switch (entry_hdr->entry_type) { | 2162 | switch (entry_hdr->entry_type) { |
2163 | case QLA82XX_RDEND: | 2163 | case QLA8XXX_RDEND: |
2164 | qla4_8xxx_mark_entry_skipped(ha, entry_hdr, i); | 2164 | qla4_8xxx_mark_entry_skipped(ha, entry_hdr, i); |
2165 | break; | 2165 | break; |
2166 | case QLA82XX_CNTRL: | 2166 | case QLA8XXX_CNTRL: |
2167 | rval = qla4_8xxx_minidump_process_control(ha, | 2167 | rval = qla4_8xxx_minidump_process_control(ha, |
2168 | entry_hdr); | 2168 | entry_hdr); |
2169 | if (rval != QLA_SUCCESS) { | 2169 | if (rval != QLA_SUCCESS) { |
@@ -2171,11 +2171,11 @@ static int qla4_8xxx_collect_md_data(struct scsi_qla_host *ha) | |||
2171 | goto md_failed; | 2171 | goto md_failed; |
2172 | } | 2172 | } |
2173 | break; | 2173 | break; |
2174 | case QLA82XX_RDCRB: | 2174 | case QLA8XXX_RDCRB: |
2175 | qla4_8xxx_minidump_process_rdcrb(ha, entry_hdr, | 2175 | qla4_8xxx_minidump_process_rdcrb(ha, entry_hdr, |
2176 | &data_ptr); | 2176 | &data_ptr); |
2177 | break; | 2177 | break; |
2178 | case QLA82XX_RDMEM: | 2178 | case QLA8XXX_RDMEM: |
2179 | rval = qla4_8xxx_minidump_process_rdmem(ha, entry_hdr, | 2179 | rval = qla4_8xxx_minidump_process_rdmem(ha, entry_hdr, |
2180 | &data_ptr); | 2180 | &data_ptr); |
2181 | if (rval != QLA_SUCCESS) { | 2181 | if (rval != QLA_SUCCESS) { |
@@ -2183,15 +2183,15 @@ static int qla4_8xxx_collect_md_data(struct scsi_qla_host *ha) | |||
2183 | goto md_failed; | 2183 | goto md_failed; |
2184 | } | 2184 | } |
2185 | break; | 2185 | break; |
2186 | case QLA82XX_BOARD: | 2186 | case QLA8XXX_BOARD: |
2187 | case QLA82XX_RDROM: | 2187 | case QLA8XXX_RDROM: |
2188 | qla4_82xx_minidump_process_rdrom(ha, entry_hdr, | 2188 | qla4_82xx_minidump_process_rdrom(ha, entry_hdr, |
2189 | &data_ptr); | 2189 | &data_ptr); |
2190 | break; | 2190 | break; |
2191 | case QLA82XX_L2DTG: | 2191 | case QLA8XXX_L2DTG: |
2192 | case QLA82XX_L2ITG: | 2192 | case QLA8XXX_L2ITG: |
2193 | case QLA82XX_L2DAT: | 2193 | case QLA8XXX_L2DAT: |
2194 | case QLA82XX_L2INS: | 2194 | case QLA8XXX_L2INS: |
2195 | rval = qla4_8xxx_minidump_process_l2tag(ha, entry_hdr, | 2195 | rval = qla4_8xxx_minidump_process_l2tag(ha, entry_hdr, |
2196 | &data_ptr); | 2196 | &data_ptr); |
2197 | if (rval != QLA_SUCCESS) { | 2197 | if (rval != QLA_SUCCESS) { |
@@ -2199,24 +2199,24 @@ static int qla4_8xxx_collect_md_data(struct scsi_qla_host *ha) | |||
2199 | goto md_failed; | 2199 | goto md_failed; |
2200 | } | 2200 | } |
2201 | break; | 2201 | break; |
2202 | case QLA82XX_L1DAT: | 2202 | case QLA8XXX_L1DAT: |
2203 | case QLA82XX_L1INS: | 2203 | case QLA8XXX_L1INS: |
2204 | qla4_8xxx_minidump_process_l1cache(ha, entry_hdr, | 2204 | qla4_8xxx_minidump_process_l1cache(ha, entry_hdr, |
2205 | &data_ptr); | 2205 | &data_ptr); |
2206 | break; | 2206 | break; |
2207 | case QLA82XX_RDOCM: | 2207 | case QLA8XXX_RDOCM: |
2208 | qla4_8xxx_minidump_process_rdocm(ha, entry_hdr, | 2208 | qla4_8xxx_minidump_process_rdocm(ha, entry_hdr, |
2209 | &data_ptr); | 2209 | &data_ptr); |
2210 | break; | 2210 | break; |
2211 | case QLA82XX_RDMUX: | 2211 | case QLA8XXX_RDMUX: |
2212 | qla4_8xxx_minidump_process_rdmux(ha, entry_hdr, | 2212 | qla4_8xxx_minidump_process_rdmux(ha, entry_hdr, |
2213 | &data_ptr); | 2213 | &data_ptr); |
2214 | break; | 2214 | break; |
2215 | case QLA82XX_QUEUE: | 2215 | case QLA8XXX_QUEUE: |
2216 | qla4_8xxx_minidump_process_queue(ha, entry_hdr, | 2216 | qla4_8xxx_minidump_process_queue(ha, entry_hdr, |
2217 | &data_ptr); | 2217 | &data_ptr); |
2218 | break; | 2218 | break; |
2219 | case QLA82XX_RDNOP: | 2219 | case QLA8XXX_RDNOP: |
2220 | default: | 2220 | default: |
2221 | qla4_8xxx_mark_entry_skipped(ha, entry_hdr, i); | 2221 | qla4_8xxx_mark_entry_skipped(ha, entry_hdr, i); |
2222 | break; | 2222 | break; |
@@ -2289,7 +2289,7 @@ qla4_8xxx_device_bootstrap(struct scsi_qla_host *ha) | |||
2289 | timeout = msleep_interruptible(200); | 2289 | timeout = msleep_interruptible(200); |
2290 | if (timeout) { | 2290 | if (timeout) { |
2291 | qla4_82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE, | 2291 | qla4_82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE, |
2292 | QLA82XX_DEV_FAILED); | 2292 | QLA8XXX_DEV_FAILED); |
2293 | return rval; | 2293 | return rval; |
2294 | } | 2294 | } |
2295 | 2295 | ||
@@ -2319,7 +2319,7 @@ qla4_8xxx_device_bootstrap(struct scsi_qla_host *ha) | |||
2319 | dev_initialize: | 2319 | dev_initialize: |
2320 | /* set to DEV_INITIALIZING */ | 2320 | /* set to DEV_INITIALIZING */ |
2321 | ql4_printk(KERN_INFO, ha, "HW State: INITIALIZING\n"); | 2321 | ql4_printk(KERN_INFO, ha, "HW State: INITIALIZING\n"); |
2322 | qla4_82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE, QLA82XX_DEV_INITIALIZING); | 2322 | qla4_82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE, QLA8XXX_DEV_INITIALIZING); |
2323 | 2323 | ||
2324 | /* Driver that sets device state to initializating sets IDC version */ | 2324 | /* Driver that sets device state to initializating sets IDC version */ |
2325 | qla4_82xx_wr_32(ha, QLA82XX_CRB_DRV_IDC_VERSION, QLA82XX_IDC_VERSION); | 2325 | qla4_82xx_wr_32(ha, QLA82XX_CRB_DRV_IDC_VERSION, QLA82XX_IDC_VERSION); |
@@ -2340,13 +2340,13 @@ dev_initialize: | |||
2340 | if (rval != QLA_SUCCESS) { | 2340 | if (rval != QLA_SUCCESS) { |
2341 | ql4_printk(KERN_INFO, ha, "HW State: FAILED\n"); | 2341 | ql4_printk(KERN_INFO, ha, "HW State: FAILED\n"); |
2342 | qla4_8xxx_clear_drv_active(ha); | 2342 | qla4_8xxx_clear_drv_active(ha); |
2343 | qla4_82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE, QLA82XX_DEV_FAILED); | 2343 | qla4_82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE, QLA8XXX_DEV_FAILED); |
2344 | return rval; | 2344 | return rval; |
2345 | } | 2345 | } |
2346 | 2346 | ||
2347 | dev_ready: | 2347 | dev_ready: |
2348 | ql4_printk(KERN_INFO, ha, "HW State: READY\n"); | 2348 | ql4_printk(KERN_INFO, ha, "HW State: READY\n"); |
2349 | qla4_82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE, QLA82XX_DEV_READY); | 2349 | qla4_82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE, QLA8XXX_DEV_READY); |
2350 | 2350 | ||
2351 | return rval; | 2351 | return rval; |
2352 | } | 2352 | } |
@@ -2373,7 +2373,7 @@ qla4_82xx_need_reset_handler(struct scsi_qla_host *ha) | |||
2373 | qla4_82xx_idc_lock(ha); | 2373 | qla4_82xx_idc_lock(ha); |
2374 | } | 2374 | } |
2375 | 2375 | ||
2376 | if (!test_bit(AF_82XX_RST_OWNER, &ha->flags)) { | 2376 | if (!test_bit(AF_8XXX_RST_OWNER, &ha->flags)) { |
2377 | DEBUG2(ql4_printk(KERN_INFO, ha, | 2377 | DEBUG2(ql4_printk(KERN_INFO, ha, |
2378 | "%s(%ld): reset acknowledged\n", | 2378 | "%s(%ld): reset acknowledged\n", |
2379 | __func__, ha->host_no)); | 2379 | __func__, ha->host_no)); |
@@ -2404,7 +2404,7 @@ qla4_82xx_need_reset_handler(struct scsi_qla_host *ha) | |||
2404 | * When reset_owner times out, check which functions | 2404 | * When reset_owner times out, check which functions |
2405 | * acked/did not ack | 2405 | * acked/did not ack |
2406 | */ | 2406 | */ |
2407 | if (test_bit(AF_82XX_RST_OWNER, &ha->flags)) { | 2407 | if (test_bit(AF_8XXX_RST_OWNER, &ha->flags)) { |
2408 | ql4_printk(KERN_INFO, ha, | 2408 | ql4_printk(KERN_INFO, ha, |
2409 | "%s(%ld): drv_state = 0x%x, drv_active = 0x%x\n", | 2409 | "%s(%ld): drv_state = 0x%x, drv_active = 0x%x\n", |
2410 | __func__, ha->host_no, drv_state, | 2410 | __func__, ha->host_no, drv_state, |
@@ -2419,16 +2419,16 @@ qla4_82xx_need_reset_handler(struct scsi_qla_host *ha) | |||
2419 | } | 2419 | } |
2420 | 2420 | ||
2421 | /* Clear RESET OWNER as we are not going to use it any further */ | 2421 | /* Clear RESET OWNER as we are not going to use it any further */ |
2422 | clear_bit(AF_82XX_RST_OWNER, &ha->flags); | 2422 | clear_bit(AF_8XXX_RST_OWNER, &ha->flags); |
2423 | 2423 | ||
2424 | dev_state = qla4_82xx_rd_32(ha, QLA82XX_CRB_DEV_STATE); | 2424 | dev_state = qla4_82xx_rd_32(ha, QLA82XX_CRB_DEV_STATE); |
2425 | ql4_printk(KERN_INFO, ha, "Device state is 0x%x = %s\n", dev_state, | 2425 | ql4_printk(KERN_INFO, ha, "Device state is 0x%x = %s\n", dev_state, |
2426 | dev_state < MAX_STATES ? qdev_state[dev_state] : "Unknown"); | 2426 | dev_state < MAX_STATES ? qdev_state[dev_state] : "Unknown"); |
2427 | 2427 | ||
2428 | /* Force to DEV_COLD unless someone else is starting a reset */ | 2428 | /* Force to DEV_COLD unless someone else is starting a reset */ |
2429 | if (dev_state != QLA82XX_DEV_INITIALIZING) { | 2429 | if (dev_state != QLA8XXX_DEV_INITIALIZING) { |
2430 | ql4_printk(KERN_INFO, ha, "HW State: COLD/RE-INIT\n"); | 2430 | ql4_printk(KERN_INFO, ha, "HW State: COLD/RE-INIT\n"); |
2431 | qla4_82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE, QLA82XX_DEV_COLD); | 2431 | qla4_82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE, QLA8XXX_DEV_COLD); |
2432 | qla4_8xxx_set_rst_ready(ha); | 2432 | qla4_8xxx_set_rst_ready(ha); |
2433 | } | 2433 | } |
2434 | } | 2434 | } |
@@ -2481,7 +2481,7 @@ int qla4_8xxx_device_state_handler(struct scsi_qla_host *ha) | |||
2481 | dev_state, dev_state < MAX_STATES ? | 2481 | dev_state, dev_state < MAX_STATES ? |
2482 | qdev_state[dev_state] : "Unknown"); | 2482 | qdev_state[dev_state] : "Unknown"); |
2483 | qla4_82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE, | 2483 | qla4_82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE, |
2484 | QLA82XX_DEV_FAILED); | 2484 | QLA8XXX_DEV_FAILED); |
2485 | } | 2485 | } |
2486 | 2486 | ||
2487 | dev_state = qla4_82xx_rd_32(ha, QLA82XX_CRB_DEV_STATE); | 2487 | dev_state = qla4_82xx_rd_32(ha, QLA82XX_CRB_DEV_STATE); |
@@ -2491,17 +2491,17 @@ int qla4_8xxx_device_state_handler(struct scsi_qla_host *ha) | |||
2491 | 2491 | ||
2492 | /* NOTE: Make sure idc unlocked upon exit of switch statement */ | 2492 | /* NOTE: Make sure idc unlocked upon exit of switch statement */ |
2493 | switch (dev_state) { | 2493 | switch (dev_state) { |
2494 | case QLA82XX_DEV_READY: | 2494 | case QLA8XXX_DEV_READY: |
2495 | goto exit; | 2495 | goto exit; |
2496 | case QLA82XX_DEV_COLD: | 2496 | case QLA8XXX_DEV_COLD: |
2497 | rval = qla4_8xxx_device_bootstrap(ha); | 2497 | rval = qla4_8xxx_device_bootstrap(ha); |
2498 | goto exit; | 2498 | goto exit; |
2499 | case QLA82XX_DEV_INITIALIZING: | 2499 | case QLA8XXX_DEV_INITIALIZING: |
2500 | qla4_82xx_idc_unlock(ha); | 2500 | qla4_82xx_idc_unlock(ha); |
2501 | msleep(1000); | 2501 | msleep(1000); |
2502 | qla4_82xx_idc_lock(ha); | 2502 | qla4_82xx_idc_lock(ha); |
2503 | break; | 2503 | break; |
2504 | case QLA82XX_DEV_NEED_RESET: | 2504 | case QLA8XXX_DEV_NEED_RESET: |
2505 | if (!ql4xdontresethba) { | 2505 | if (!ql4xdontresethba) { |
2506 | qla4_82xx_need_reset_handler(ha); | 2506 | qla4_82xx_need_reset_handler(ha); |
2507 | /* Update timeout value after need | 2507 | /* Update timeout value after need |
@@ -2514,16 +2514,16 @@ int qla4_8xxx_device_state_handler(struct scsi_qla_host *ha) | |||
2514 | qla4_82xx_idc_lock(ha); | 2514 | qla4_82xx_idc_lock(ha); |
2515 | } | 2515 | } |
2516 | break; | 2516 | break; |
2517 | case QLA82XX_DEV_NEED_QUIESCENT: | 2517 | case QLA8XXX_DEV_NEED_QUIESCENT: |
2518 | /* idc locked/unlocked in handler */ | 2518 | /* idc locked/unlocked in handler */ |
2519 | qla4_8xxx_need_qsnt_handler(ha); | 2519 | qla4_8xxx_need_qsnt_handler(ha); |
2520 | break; | 2520 | break; |
2521 | case QLA82XX_DEV_QUIESCENT: | 2521 | case QLA8XXX_DEV_QUIESCENT: |
2522 | qla4_82xx_idc_unlock(ha); | 2522 | qla4_82xx_idc_unlock(ha); |
2523 | msleep(1000); | 2523 | msleep(1000); |
2524 | qla4_82xx_idc_lock(ha); | 2524 | qla4_82xx_idc_lock(ha); |
2525 | break; | 2525 | break; |
2526 | case QLA82XX_DEV_FAILED: | 2526 | case QLA8XXX_DEV_FAILED: |
2527 | qla4_82xx_idc_unlock(ha); | 2527 | qla4_82xx_idc_unlock(ha); |
2528 | qla4xxx_dead_adapter_cleanup(ha); | 2528 | qla4xxx_dead_adapter_cleanup(ha); |
2529 | rval = QLA_ERROR; | 2529 | rval = QLA_ERROR; |
@@ -2884,11 +2884,11 @@ qla4_82xx_isp_reset(struct scsi_qla_host *ha) | |||
2884 | qla4_82xx_idc_lock(ha); | 2884 | qla4_82xx_idc_lock(ha); |
2885 | dev_state = qla4_82xx_rd_32(ha, QLA82XX_CRB_DEV_STATE); | 2885 | dev_state = qla4_82xx_rd_32(ha, QLA82XX_CRB_DEV_STATE); |
2886 | 2886 | ||
2887 | if (dev_state == QLA82XX_DEV_READY) { | 2887 | if (dev_state == QLA8XXX_DEV_READY) { |
2888 | ql4_printk(KERN_INFO, ha, "HW State: NEED RESET\n"); | 2888 | ql4_printk(KERN_INFO, ha, "HW State: NEED RESET\n"); |
2889 | qla4_82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE, | 2889 | qla4_82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE, |
2890 | QLA82XX_DEV_NEED_RESET); | 2890 | QLA8XXX_DEV_NEED_RESET); |
2891 | set_bit(AF_82XX_RST_OWNER, &ha->flags); | 2891 | set_bit(AF_8XXX_RST_OWNER, &ha->flags); |
2892 | } else | 2892 | } else |
2893 | ql4_printk(KERN_INFO, ha, "HW State: DEVICE INITIALIZING\n"); | 2893 | ql4_printk(KERN_INFO, ha, "HW State: DEVICE INITIALIZING\n"); |
2894 | 2894 | ||
diff --git a/drivers/scsi/qla4xxx/ql4_nx.h b/drivers/scsi/qla4xxx/ql4_nx.h index e7a9cc4fe231..1936c8168332 100644 --- a/drivers/scsi/qla4xxx/ql4_nx.h +++ b/drivers/scsi/qla4xxx/ql4_nx.h | |||
@@ -490,8 +490,8 @@ enum { | |||
490 | * Base addresses of major components on-chip. | 490 | * Base addresses of major components on-chip. |
491 | * ====================== BASE ADDRESSES ON-CHIP ====================== | 491 | * ====================== BASE ADDRESSES ON-CHIP ====================== |
492 | */ | 492 | */ |
493 | #define QLA82XX_ADDR_DDR_NET (0x0000000000000000ULL) | 493 | #define QLA8XXX_ADDR_DDR_NET (0x0000000000000000ULL) |
494 | #define QLA82XX_ADDR_DDR_NET_MAX (0x000000000fffffffULL) | 494 | #define QLA8XXX_ADDR_DDR_NET_MAX (0x000000000fffffffULL) |
495 | 495 | ||
496 | /* Imbus address bit used to indicate a host address. This bit is | 496 | /* Imbus address bit used to indicate a host address. This bit is |
497 | * eliminated by the pcie bar and bar select before presentation | 497 | * eliminated by the pcie bar and bar select before presentation |
@@ -500,11 +500,11 @@ enum { | |||
500 | #define QLA82XX_P2_ADDR_PCIE (0x0000000800000000ULL) | 500 | #define QLA82XX_P2_ADDR_PCIE (0x0000000800000000ULL) |
501 | #define QLA82XX_P3_ADDR_PCIE (0x0000008000000000ULL) | 501 | #define QLA82XX_P3_ADDR_PCIE (0x0000008000000000ULL) |
502 | #define QLA82XX_ADDR_PCIE_MAX (0x0000000FFFFFFFFFULL) | 502 | #define QLA82XX_ADDR_PCIE_MAX (0x0000000FFFFFFFFFULL) |
503 | #define QLA82XX_ADDR_OCM0 (0x0000000200000000ULL) | 503 | #define QLA8XXX_ADDR_OCM0 (0x0000000200000000ULL) |
504 | #define QLA82XX_ADDR_OCM0_MAX (0x00000002000fffffULL) | 504 | #define QLA8XXX_ADDR_OCM0_MAX (0x00000002000fffffULL) |
505 | #define QLA82XX_ADDR_OCM1 (0x0000000200400000ULL) | 505 | #define QLA8XXX_ADDR_OCM1 (0x0000000200400000ULL) |
506 | #define QLA82XX_ADDR_OCM1_MAX (0x00000002004fffffULL) | 506 | #define QLA8XXX_ADDR_OCM1_MAX (0x00000002004fffffULL) |
507 | #define QLA82XX_ADDR_QDR_NET (0x0000000300000000ULL) | 507 | #define QLA8XXX_ADDR_QDR_NET (0x0000000300000000ULL) |
508 | 508 | ||
509 | #define QLA82XX_P2_ADDR_QDR_NET_MAX (0x00000003001fffffULL) | 509 | #define QLA82XX_P2_ADDR_QDR_NET_MAX (0x00000003001fffffULL) |
510 | #define QLA82XX_P3_ADDR_QDR_NET_MAX (0x0000000303ffffffULL) | 510 | #define QLA82XX_P3_ADDR_QDR_NET_MAX (0x0000000303ffffffULL) |
@@ -572,13 +572,13 @@ enum { | |||
572 | #define QLA82XX_CRB_DEV_PART_INFO (QLA82XX_CAM_RAM(0x14c)) | 572 | #define QLA82XX_CRB_DEV_PART_INFO (QLA82XX_CAM_RAM(0x14c)) |
573 | 573 | ||
574 | /* Every driver should use these Device State */ | 574 | /* Every driver should use these Device State */ |
575 | #define QLA82XX_DEV_COLD 1 | 575 | #define QLA8XXX_DEV_COLD 1 |
576 | #define QLA82XX_DEV_INITIALIZING 2 | 576 | #define QLA8XXX_DEV_INITIALIZING 2 |
577 | #define QLA82XX_DEV_READY 3 | 577 | #define QLA8XXX_DEV_READY 3 |
578 | #define QLA82XX_DEV_NEED_RESET 4 | 578 | #define QLA8XXX_DEV_NEED_RESET 4 |
579 | #define QLA82XX_DEV_NEED_QUIESCENT 5 | 579 | #define QLA8XXX_DEV_NEED_QUIESCENT 5 |
580 | #define QLA82XX_DEV_FAILED 6 | 580 | #define QLA8XXX_DEV_FAILED 6 |
581 | #define QLA82XX_DEV_QUIESCENT 7 | 581 | #define QLA8XXX_DEV_QUIESCENT 7 |
582 | #define MAX_STATES 8 /* Increment if new state added */ | 582 | #define MAX_STATES 8 /* Increment if new state added */ |
583 | 583 | ||
584 | #define QLA82XX_IDC_VERSION 0x1 | 584 | #define QLA82XX_IDC_VERSION 0x1 |
@@ -795,41 +795,41 @@ struct crb_addr_pair { | |||
795 | /* Minidump related */ | 795 | /* Minidump related */ |
796 | 796 | ||
797 | /* Entry Type Defines */ | 797 | /* Entry Type Defines */ |
798 | #define QLA82XX_RDNOP 0 | 798 | #define QLA8XXX_RDNOP 0 |
799 | #define QLA82XX_RDCRB 1 | 799 | #define QLA8XXX_RDCRB 1 |
800 | #define QLA82XX_RDMUX 2 | 800 | #define QLA8XXX_RDMUX 2 |
801 | #define QLA82XX_QUEUE 3 | 801 | #define QLA8XXX_QUEUE 3 |
802 | #define QLA82XX_BOARD 4 | 802 | #define QLA8XXX_BOARD 4 |
803 | #define QLA82XX_RDOCM 6 | 803 | #define QLA8XXX_RDOCM 6 |
804 | #define QLA82XX_PREGS 7 | 804 | #define QLA8XXX_PREGS 7 |
805 | #define QLA82XX_L1DTG 8 | 805 | #define QLA8XXX_L1DTG 8 |
806 | #define QLA82XX_L1ITG 9 | 806 | #define QLA8XXX_L1ITG 9 |
807 | #define QLA82XX_L1DAT 11 | 807 | #define QLA8XXX_L1DAT 11 |
808 | #define QLA82XX_L1INS 12 | 808 | #define QLA8XXX_L1INS 12 |
809 | #define QLA82XX_L2DTG 21 | 809 | #define QLA8XXX_L2DTG 21 |
810 | #define QLA82XX_L2ITG 22 | 810 | #define QLA8XXX_L2ITG 22 |
811 | #define QLA82XX_L2DAT 23 | 811 | #define QLA8XXX_L2DAT 23 |
812 | #define QLA82XX_L2INS 24 | 812 | #define QLA8XXX_L2INS 24 |
813 | #define QLA82XX_RDROM 71 | 813 | #define QLA8XXX_RDROM 71 |
814 | #define QLA82XX_RDMEM 72 | 814 | #define QLA8XXX_RDMEM 72 |
815 | #define QLA82XX_CNTRL 98 | 815 | #define QLA8XXX_CNTRL 98 |
816 | #define QLA82XX_RDEND 255 | 816 | #define QLA8XXX_RDEND 255 |
817 | 817 | ||
818 | /* Opcodes for Control Entries. | 818 | /* Opcodes for Control Entries. |
819 | * These Flags are bit fields. | 819 | * These Flags are bit fields. |
820 | */ | 820 | */ |
821 | #define QLA82XX_DBG_OPCODE_WR 0x01 | 821 | #define QLA8XXX_DBG_OPCODE_WR 0x01 |
822 | #define QLA82XX_DBG_OPCODE_RW 0x02 | 822 | #define QLA8XXX_DBG_OPCODE_RW 0x02 |
823 | #define QLA82XX_DBG_OPCODE_AND 0x04 | 823 | #define QLA8XXX_DBG_OPCODE_AND 0x04 |
824 | #define QLA82XX_DBG_OPCODE_OR 0x08 | 824 | #define QLA8XXX_DBG_OPCODE_OR 0x08 |
825 | #define QLA82XX_DBG_OPCODE_POLL 0x10 | 825 | #define QLA8XXX_DBG_OPCODE_POLL 0x10 |
826 | #define QLA82XX_DBG_OPCODE_RDSTATE 0x20 | 826 | #define QLA8XXX_DBG_OPCODE_RDSTATE 0x20 |
827 | #define QLA82XX_DBG_OPCODE_WRSTATE 0x40 | 827 | #define QLA8XXX_DBG_OPCODE_WRSTATE 0x40 |
828 | #define QLA82XX_DBG_OPCODE_MDSTATE 0x80 | 828 | #define QLA8XXX_DBG_OPCODE_MDSTATE 0x80 |
829 | 829 | ||
830 | /* Driver Flags */ | 830 | /* Driver Flags */ |
831 | #define QLA82XX_DBG_SKIPPED_FLAG 0x80 /* driver skipped this entry */ | 831 | #define QLA8XXX_DBG_SKIPPED_FLAG 0x80 /* driver skipped this entry */ |
832 | #define QLA82XX_DBG_SIZE_ERR_FLAG 0x40 /* Entry vs Capture size | 832 | #define QLA8XXX_DBG_SIZE_ERR_FLAG 0x40 /* Entry vs Capture size |
833 | * mismatch */ | 833 | * mismatch */ |
834 | 834 | ||
835 | /* Driver_code is for driver to write some info about the entry | 835 | /* Driver_code is for driver to write some info about the entry |
diff --git a/drivers/scsi/qla4xxx/ql4_os.c b/drivers/scsi/qla4xxx/ql4_os.c index 89c2576ea828..6aa508c5e4c6 100644 --- a/drivers/scsi/qla4xxx/ql4_os.c +++ b/drivers/scsi/qla4xxx/ql4_os.c | |||
@@ -2525,7 +2525,7 @@ void qla4_8xxx_watchdog(struct scsi_qla_host *ha) | |||
2525 | CRB_NIU_XG_PAUSE_CTL_P1); | 2525 | CRB_NIU_XG_PAUSE_CTL_P1); |
2526 | set_bit(DPC_HA_UNRECOVERABLE, &ha->dpc_flags); | 2526 | set_bit(DPC_HA_UNRECOVERABLE, &ha->dpc_flags); |
2527 | qla4xxx_wake_dpc(ha); | 2527 | qla4xxx_wake_dpc(ha); |
2528 | } else if (dev_state == QLA82XX_DEV_NEED_RESET && | 2528 | } else if (dev_state == QLA8XXX_DEV_NEED_RESET && |
2529 | !test_bit(DPC_RESET_HA, &ha->dpc_flags)) { | 2529 | !test_bit(DPC_RESET_HA, &ha->dpc_flags)) { |
2530 | if (!ql4xdontresethba) { | 2530 | if (!ql4xdontresethba) { |
2531 | ql4_printk(KERN_INFO, ha, "%s: HW State: " | 2531 | ql4_printk(KERN_INFO, ha, "%s: HW State: " |
@@ -2533,7 +2533,7 @@ void qla4_8xxx_watchdog(struct scsi_qla_host *ha) | |||
2533 | set_bit(DPC_RESET_HA, &ha->dpc_flags); | 2533 | set_bit(DPC_RESET_HA, &ha->dpc_flags); |
2534 | qla4xxx_wake_dpc(ha); | 2534 | qla4xxx_wake_dpc(ha); |
2535 | } | 2535 | } |
2536 | } else if (dev_state == QLA82XX_DEV_NEED_QUIESCENT && | 2536 | } else if (dev_state == QLA8XXX_DEV_NEED_QUIESCENT && |
2537 | !test_bit(DPC_HA_NEED_QUIESCENT, &ha->dpc_flags)) { | 2537 | !test_bit(DPC_HA_NEED_QUIESCENT, &ha->dpc_flags)) { |
2538 | ql4_printk(KERN_INFO, ha, "%s: HW State: NEED QUIES!\n", | 2538 | ql4_printk(KERN_INFO, ha, "%s: HW State: NEED QUIES!\n", |
2539 | __func__); | 2539 | __func__); |
@@ -3043,7 +3043,7 @@ recover_ha_init_adapter: | |||
3043 | qla4_82xx_idc_lock(ha); | 3043 | qla4_82xx_idc_lock(ha); |
3044 | dev_state = qla4_82xx_rd_32(ha, QLA82XX_CRB_DEV_STATE); | 3044 | dev_state = qla4_82xx_rd_32(ha, QLA82XX_CRB_DEV_STATE); |
3045 | qla4_82xx_idc_unlock(ha); | 3045 | qla4_82xx_idc_unlock(ha); |
3046 | if (dev_state == QLA82XX_DEV_FAILED) { | 3046 | if (dev_state == QLA8XXX_DEV_FAILED) { |
3047 | ql4_printk(KERN_INFO, ha, "%s: don't retry " | 3047 | ql4_printk(KERN_INFO, ha, "%s: don't retry " |
3048 | "recover adapter. H/W is in Failed " | 3048 | "recover adapter. H/W is in Failed " |
3049 | "state\n", __func__); | 3049 | "state\n", __func__); |
@@ -3387,7 +3387,7 @@ static void qla4xxx_do_dpc(struct work_struct *work) | |||
3387 | if (test_bit(DPC_HA_UNRECOVERABLE, &ha->dpc_flags)) { | 3387 | if (test_bit(DPC_HA_UNRECOVERABLE, &ha->dpc_flags)) { |
3388 | qla4_82xx_idc_lock(ha); | 3388 | qla4_82xx_idc_lock(ha); |
3389 | qla4_82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE, | 3389 | qla4_82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE, |
3390 | QLA82XX_DEV_FAILED); | 3390 | QLA8XXX_DEV_FAILED); |
3391 | qla4_82xx_idc_unlock(ha); | 3391 | qla4_82xx_idc_unlock(ha); |
3392 | ql4_printk(KERN_INFO, ha, "HW State: FAILED\n"); | 3392 | ql4_printk(KERN_INFO, ha, "HW State: FAILED\n"); |
3393 | qla4_8xxx_device_state_handler(ha); | 3393 | qla4_8xxx_device_state_handler(ha); |
@@ -5164,7 +5164,7 @@ static int __devinit qla4xxx_probe_adapter(struct pci_dev *pdev, | |||
5164 | qla4_82xx_idc_lock(ha); | 5164 | qla4_82xx_idc_lock(ha); |
5165 | dev_state = qla4_82xx_rd_32(ha, QLA82XX_CRB_DEV_STATE); | 5165 | dev_state = qla4_82xx_rd_32(ha, QLA82XX_CRB_DEV_STATE); |
5166 | qla4_82xx_idc_unlock(ha); | 5166 | qla4_82xx_idc_unlock(ha); |
5167 | if (dev_state == QLA82XX_DEV_FAILED) { | 5167 | if (dev_state == QLA8XXX_DEV_FAILED) { |
5168 | ql4_printk(KERN_WARNING, ha, "%s: don't retry " | 5168 | ql4_printk(KERN_WARNING, ha, "%s: don't retry " |
5169 | "initialize adapter. H/W is in failed state\n", | 5169 | "initialize adapter. H/W is in failed state\n", |
5170 | __func__); | 5170 | __func__); |
@@ -5188,7 +5188,7 @@ static int __devinit qla4xxx_probe_adapter(struct pci_dev *pdev, | |||
5188 | DEBUG2(printk(KERN_ERR "HW STATE: FAILED\n")); | 5188 | DEBUG2(printk(KERN_ERR "HW STATE: FAILED\n")); |
5189 | qla4_82xx_idc_lock(ha); | 5189 | qla4_82xx_idc_lock(ha); |
5190 | qla4_82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE, | 5190 | qla4_82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE, |
5191 | QLA82XX_DEV_FAILED); | 5191 | QLA8XXX_DEV_FAILED); |
5192 | qla4_82xx_idc_unlock(ha); | 5192 | qla4_82xx_idc_unlock(ha); |
5193 | } | 5193 | } |
5194 | ret = -ENODEV; | 5194 | ret = -ENODEV; |
@@ -6035,7 +6035,7 @@ static uint32_t qla4_8xxx_error_recovery(struct scsi_qla_host *ha) | |||
6035 | 6035 | ||
6036 | qla4_82xx_idc_lock(ha); | 6036 | qla4_82xx_idc_lock(ha); |
6037 | qla4_82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE, | 6037 | qla4_82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE, |
6038 | QLA82XX_DEV_COLD); | 6038 | QLA8XXX_DEV_COLD); |
6039 | 6039 | ||
6040 | qla4_82xx_wr_32(ha, QLA82XX_CRB_DRV_IDC_VERSION, | 6040 | qla4_82xx_wr_32(ha, QLA82XX_CRB_DRV_IDC_VERSION, |
6041 | QLA82XX_IDC_VERSION); | 6041 | QLA82XX_IDC_VERSION); |
@@ -6050,12 +6050,12 @@ static uint32_t qla4_8xxx_error_recovery(struct scsi_qla_host *ha) | |||
6050 | "FAILED\n", ha->host_no, __func__); | 6050 | "FAILED\n", ha->host_no, __func__); |
6051 | qla4_8xxx_clear_drv_active(ha); | 6051 | qla4_8xxx_clear_drv_active(ha); |
6052 | qla4_82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE, | 6052 | qla4_82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE, |
6053 | QLA82XX_DEV_FAILED); | 6053 | QLA8XXX_DEV_FAILED); |
6054 | } else { | 6054 | } else { |
6055 | ql4_printk(KERN_INFO, ha, "scsi%ld: %s: HW State: " | 6055 | ql4_printk(KERN_INFO, ha, "scsi%ld: %s: HW State: " |
6056 | "READY\n", ha->host_no, __func__); | 6056 | "READY\n", ha->host_no, __func__); |
6057 | qla4_82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE, | 6057 | qla4_82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE, |
6058 | QLA82XX_DEV_READY); | 6058 | QLA8XXX_DEV_READY); |
6059 | /* Clear driver state register */ | 6059 | /* Clear driver state register */ |
6060 | qla4_82xx_wr_32(ha, QLA82XX_CRB_DRV_STATE, 0); | 6060 | qla4_82xx_wr_32(ha, QLA82XX_CRB_DRV_STATE, 0); |
6061 | qla4_8xxx_set_drv_active(ha); | 6061 | qla4_8xxx_set_drv_active(ha); |
@@ -6076,7 +6076,7 @@ static uint32_t qla4_8xxx_error_recovery(struct scsi_qla_host *ha) | |||
6076 | "the reset owner\n", ha->host_no, __func__, | 6076 | "the reset owner\n", ha->host_no, __func__, |
6077 | ha->pdev->devfn); | 6077 | ha->pdev->devfn); |
6078 | if ((qla4_82xx_rd_32(ha, QLA82XX_CRB_DEV_STATE) == | 6078 | if ((qla4_82xx_rd_32(ha, QLA82XX_CRB_DEV_STATE) == |
6079 | QLA82XX_DEV_READY)) { | 6079 | QLA8XXX_DEV_READY)) { |
6080 | clear_bit(AF_FW_RECOVERY, &ha->flags); | 6080 | clear_bit(AF_FW_RECOVERY, &ha->flags); |
6081 | rval = qla4xxx_initialize_adapter(ha, RESET_ADAPTER); | 6081 | rval = qla4xxx_initialize_adapter(ha, RESET_ADAPTER); |
6082 | if (rval == QLA_SUCCESS) { | 6082 | if (rval == QLA_SUCCESS) { |