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authorSwapnil Nagle <swapnil.nagle@qlogic.com>2010-12-03 01:12:15 -0500
committerJames Bottomley <James.Bottomley@suse.de>2010-12-21 13:24:36 -0500
commita1fc26baae41e00a3ecfd99bbe91aa2435045625 (patch)
treeec64a8ce29fedcc2df0f5ebaecb9910019d9879b /drivers/scsi/qla4xxx/ql4_nx.c
parent61391d314e856030b2b40b5d6ea22b93de0f1fed (diff)
[SCSI] qla4xxx: memory wedge with peg_halt test in loop
Signed-off-by: Swapnil Nagle <swapnil.nagle@qlogic.com> Signed-off-by: Vikas Chaudhary <vikas.chaudhary@qlogic.com> Signed-off-by: Ravi Anand <ravi.anand@qlogic.com> Signed-off-by: James Bottomley <James.Bottomley@suse.de>
Diffstat (limited to 'drivers/scsi/qla4xxx/ql4_nx.c')
-rw-r--r--drivers/scsi/qla4xxx/ql4_nx.c43
1 files changed, 43 insertions, 0 deletions
diff --git a/drivers/scsi/qla4xxx/ql4_nx.c b/drivers/scsi/qla4xxx/ql4_nx.c
index 474b10d71364..2d95ef20d07d 100644
--- a/drivers/scsi/qla4xxx/ql4_nx.c
+++ b/drivers/scsi/qla4xxx/ql4_nx.c
@@ -942,12 +942,55 @@ qla4_8xxx_pinit_from_rom(struct scsi_qla_host *ha, int verbose)
942 942
943 /* Halt all the indiviual PEGs and other blocks of the ISP */ 943 /* Halt all the indiviual PEGs and other blocks of the ISP */
944 qla4_8xxx_rom_lock(ha); 944 qla4_8xxx_rom_lock(ha);
945
946 /* mask all niu interrupts */
947 qla4_8xxx_wr_32(ha, QLA82XX_CRB_NIU + 0x40, 0xff);
948 /* disable xge rx/tx */
949 qla4_8xxx_wr_32(ha, QLA82XX_CRB_NIU + 0x70000, 0x00);
950 /* disable xg1 rx/tx */
951 qla4_8xxx_wr_32(ha, QLA82XX_CRB_NIU + 0x80000, 0x00);
952
953 /* halt sre */
954 val = qla4_8xxx_rd_32(ha, QLA82XX_CRB_SRE + 0x1000);
955 qla4_8xxx_wr_32(ha, QLA82XX_CRB_SRE + 0x1000, val & (~(0x1)));
956
957 /* halt epg */
958 qla4_8xxx_wr_32(ha, QLA82XX_CRB_EPG + 0x1300, 0x1);
959
960 /* halt timers */
961 qla4_8xxx_wr_32(ha, QLA82XX_CRB_TIMER + 0x0, 0x0);
962 qla4_8xxx_wr_32(ha, QLA82XX_CRB_TIMER + 0x8, 0x0);
963 qla4_8xxx_wr_32(ha, QLA82XX_CRB_TIMER + 0x10, 0x0);
964 qla4_8xxx_wr_32(ha, QLA82XX_CRB_TIMER + 0x18, 0x0);
965 qla4_8xxx_wr_32(ha, QLA82XX_CRB_TIMER + 0x100, 0x0);
966
967 /* halt pegs */
968 qla4_8xxx_wr_32(ha, QLA82XX_CRB_PEG_NET_0 + 0x3c, 1);
969 qla4_8xxx_wr_32(ha, QLA82XX_CRB_PEG_NET_1 + 0x3c, 1);
970 qla4_8xxx_wr_32(ha, QLA82XX_CRB_PEG_NET_2 + 0x3c, 1);
971 qla4_8xxx_wr_32(ha, QLA82XX_CRB_PEG_NET_3 + 0x3c, 1);
972 qla4_8xxx_wr_32(ha, QLA82XX_CRB_PEG_NET_4 + 0x3c, 1);
973
974 /* big hammer */
975 msleep(1000);
945 if (test_bit(DPC_RESET_HA, &ha->dpc_flags)) 976 if (test_bit(DPC_RESET_HA, &ha->dpc_flags))
946 /* don't reset CAM block on reset */ 977 /* don't reset CAM block on reset */
947 qla4_8xxx_wr_32(ha, QLA82XX_ROMUSB_GLB_SW_RESET, 0xfeffffff); 978 qla4_8xxx_wr_32(ha, QLA82XX_ROMUSB_GLB_SW_RESET, 0xfeffffff);
948 else 979 else
949 qla4_8xxx_wr_32(ha, QLA82XX_ROMUSB_GLB_SW_RESET, 0xffffffff); 980 qla4_8xxx_wr_32(ha, QLA82XX_ROMUSB_GLB_SW_RESET, 0xffffffff);
950 981
982 /* reset ms */
983 val = qla4_8xxx_rd_32(ha, QLA82XX_CRB_QDR_NET + 0xe4);
984 val |= (1 << 1);
985 qla4_8xxx_wr_32(ha, QLA82XX_CRB_QDR_NET + 0xe4, val);
986
987 msleep(20);
988 /* unreset ms */
989 val = qla4_8xxx_rd_32(ha, QLA82XX_CRB_QDR_NET + 0xe4);
990 val &= ~(1 << 1);
991 qla4_8xxx_wr_32(ha, QLA82XX_CRB_QDR_NET + 0xe4, val);
992 msleep(20);
993
951 qla4_8xxx_rom_unlock(ha); 994 qla4_8xxx_rom_unlock(ha);
952 995
953 /* Read the signature value from the flash. 996 /* Read the signature value from the flash.