diff options
author | Tej Parkash <tej.parkash@qlogic.com> | 2012-09-20 07:35:12 -0400 |
---|---|---|
committer | James Bottomley <JBottomley@Parallels.com> | 2012-09-24 04:49:00 -0400 |
commit | 546fef27c3a798fbcece2705c1eda9e249e22226 (patch) | |
tree | 3e10b8a6f7daeff5ecc0fddc8985e5da09ce730f /drivers/scsi/qla4xxx/ql4_83xx.h | |
parent | 48a859d29f3d7a855093819633abcc9c877108ef (diff) |
[SCSI] qla4xxx: Disable generating pause frames for ISP83XX
In case of FW hung ISP83XX generates continuous pause frames
which causes switch to disable port.
Added fix to disable generating pause frames in case of
FW hung
Signed-off-by: Tej Parkash <tej.parkash@qlogic.com>
Signed-off-by: Vikas Chaudhary <vikas.chaudhary@qlogic.com>
Signed-off-by: James Bottomley <JBottomley@Parallels.com>
Diffstat (limited to 'drivers/scsi/qla4xxx/ql4_83xx.h')
-rw-r--r-- | drivers/scsi/qla4xxx/ql4_83xx.h | 13 |
1 files changed, 13 insertions, 0 deletions
diff --git a/drivers/scsi/qla4xxx/ql4_83xx.h b/drivers/scsi/qla4xxx/ql4_83xx.h index 18d86abbf276..6a00f903f2a6 100644 --- a/drivers/scsi/qla4xxx/ql4_83xx.h +++ b/drivers/scsi/qla4xxx/ql4_83xx.h | |||
@@ -41,6 +41,19 @@ | |||
41 | #define QLA83XX_CRB_IDC_VER_MINOR 0x3798 | 41 | #define QLA83XX_CRB_IDC_VER_MINOR 0x3798 |
42 | #define QLA83XX_IDC_DRV_CTRL 0x3790 | 42 | #define QLA83XX_IDC_DRV_CTRL 0x3790 |
43 | #define QLA83XX_IDC_DRV_AUDIT 0x3794 | 43 | #define QLA83XX_IDC_DRV_AUDIT 0x3794 |
44 | #define QLA83XX_SRE_SHIM_CONTROL 0x0D200284 | ||
45 | #define QLA83XX_PORT0_RXB_PAUSE_THRS 0x0B2003A4 | ||
46 | #define QLA83XX_PORT1_RXB_PAUSE_THRS 0x0B2013A4 | ||
47 | #define QLA83XX_PORT0_RXB_TC_MAX_CELL 0x0B200388 | ||
48 | #define QLA83XX_PORT1_RXB_TC_MAX_CELL 0x0B201388 | ||
49 | #define QLA83XX_PORT0_RXB_TC_STATS 0x0B20039C | ||
50 | #define QLA83XX_PORT1_RXB_TC_STATS 0x0B20139C | ||
51 | #define QLA83XX_PORT2_IFB_PAUSE_THRS 0x0B200704 | ||
52 | #define QLA83XX_PORT3_IFB_PAUSE_THRS 0x0B201704 | ||
53 | |||
54 | /* set value to pause threshold value */ | ||
55 | #define QLA83XX_SET_PAUSE_VAL 0x0 | ||
56 | #define QLA83XX_SET_TC_MAX_CELL_VAL 0x03FF03FF | ||
44 | 57 | ||
45 | /* qla_83xx_reg_tbl registers */ | 58 | /* qla_83xx_reg_tbl registers */ |
46 | #define QLA83XX_PEG_HALT_STATUS1 0x34A8 | 59 | #define QLA83XX_PEG_HALT_STATUS1 0x34A8 |