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authorJoe Carnuccio <joe.carnuccio@qlogic.com>2014-04-11 16:54:36 -0400
committerChristoph Hellwig <hch@lst.de>2014-05-19 07:31:04 -0400
commitc04964017ac418d8d559aa32fd2ad6876fa162f7 (patch)
tree2cecfda1880f9259702f4cec4b6725c1db25915d /drivers/scsi/qla2xxx
parent478c3b03cb1ead4be1b68345b38f3a2eba7494e7 (diff)
qla2xxx: ISP27xx firmware dump template spec updates (including T274).
Signed-off-by: Joe Carnuccio <joe.carnuccio@qlogic.com> Signed-off-by: Saurav Kashyap <saurav.kashyap@qlogic.com> Signed-off-by: Christoph Hellwig <hch@lst.de>
Diffstat (limited to 'drivers/scsi/qla2xxx')
-rw-r--r--drivers/scsi/qla2xxx/qla_dbg.c6
-rw-r--r--drivers/scsi/qla2xxx/qla_tmpl.c90
-rw-r--r--drivers/scsi/qla2xxx/qla_tmpl.h15
3 files changed, 78 insertions, 33 deletions
diff --git a/drivers/scsi/qla2xxx/qla_dbg.c b/drivers/scsi/qla2xxx/qla_dbg.c
index 85646820af32..cdff3aa380cb 100644
--- a/drivers/scsi/qla2xxx/qla_dbg.c
+++ b/drivers/scsi/qla2xxx/qla_dbg.c
@@ -61,11 +61,11 @@
61 * | | | 0xb13c-0xb140 | 61 * | | | 0xb13c-0xb140 |
62 * | | | 0xb149 | 62 * | | | 0xb149 |
63 * | MultiQ | 0xc00c | | 63 * | MultiQ | 0xc00c | |
64 * | Misc | 0xd300 | 0xd017-0xd019 | 64 * | Misc | 0xd212 | 0xd017-0xd019 |
65 * | | | 0xd020 | 65 * | | | 0xd020 |
66 * | | | 0xd02e-0xd0ff | 66 * | | | 0xd030-0xd0ff |
67 * | | | 0xd101-0xd1fe | 67 * | | | 0xd101-0xd1fe |
68 * | | | 0xd212-0xd2fe | 68 * | | | 0xd213-0xd2fe |
69 * | Target Mode | 0xe070 | 0xe021 | 69 * | Target Mode | 0xe070 | 0xe021 |
70 * | Target Mode Management | 0xf072 | 0xf002-0xf003 | 70 * | Target Mode Management | 0xf072 | 0xf002-0xf003 |
71 * | | | 0xf046-0xf049 | 71 * | | | 0xf046-0xf049 |
diff --git a/drivers/scsi/qla2xxx/qla_tmpl.c b/drivers/scsi/qla2xxx/qla_tmpl.c
index 872ec7e17062..a9fa9b72b31a 100644
--- a/drivers/scsi/qla2xxx/qla_tmpl.c
+++ b/drivers/scsi/qla2xxx/qla_tmpl.c
@@ -192,19 +192,6 @@ static inline void (*qla27xx_read_vector(uint width))(void *, void *, ulong *)
192} 192}
193 193
194static inline void 194static inline void
195qla27xx_read_off(__iomem struct device_reg_24xx *reg,
196 uint offset, void *buf, ulong *len)
197{
198 void *window = (void *)reg + offset;
199
200 if (buf) {
201 ql_dbg(ql_dbg_misc, NULL, 0xd300,
202 "%s: @%x\n", __func__, offset);
203 }
204 qla27xx_read32(window, buf, len);
205}
206
207static inline void
208qla27xx_read_reg(__iomem struct device_reg_24xx *reg, 195qla27xx_read_reg(__iomem struct device_reg_24xx *reg,
209 uint offset, void *buf, ulong *len) 196 uint offset, void *buf, ulong *len)
210{ 197{
@@ -214,7 +201,6 @@ qla27xx_read_reg(__iomem struct device_reg_24xx *reg,
214 ql_dbg(ql_dbg_misc, NULL, 0xd014, 201 ql_dbg(ql_dbg_misc, NULL, 0xd014,
215 "%s: @%x\n", __func__, offset); 202 "%s: @%x\n", __func__, offset);
216 } 203 }
217 qla27xx_insert32(offset, buf, len);
218 qla27xx_read32(window, buf, len); 204 qla27xx_read32(window, buf, len);
219} 205}
220 206
@@ -233,7 +219,7 @@ qla27xx_write_reg(__iomem struct device_reg_24xx *reg,
233 219
234static inline void 220static inline void
235qla27xx_read_window(__iomem struct device_reg_24xx *reg, 221qla27xx_read_window(__iomem struct device_reg_24xx *reg,
236 uint32_t base, uint offset, uint count, uint width, void *buf, 222 uint32_t addr, uint offset, uint count, uint width, void *buf,
237 ulong *len) 223 ulong *len)
238{ 224{
239 void *window = (void *)reg + offset; 225 void *window = (void *)reg + offset;
@@ -242,14 +228,14 @@ qla27xx_read_window(__iomem struct device_reg_24xx *reg,
242 if (buf) { 228 if (buf) {
243 ql_dbg(ql_dbg_misc, NULL, 0xd016, 229 ql_dbg(ql_dbg_misc, NULL, 0xd016,
244 "%s: base=%x offset=%x count=%x width=%x\n", 230 "%s: base=%x offset=%x count=%x width=%x\n",
245 __func__, base, offset, count, width); 231 __func__, addr, offset, count, width);
246 } 232 }
247 qla27xx_write_reg(reg, IOBASE_ADDR, base, buf); 233 qla27xx_write_reg(reg, IOBASE_ADDR, addr, buf);
248 while (count--) { 234 while (count--) {
249 qla27xx_insert32(base, buf, len); 235 qla27xx_insert32(addr, buf, len);
250 readn(window, buf, len); 236 readn(window, buf, len);
251 window += width; 237 window += width;
252 base++; 238 addr++;
253 } 239 }
254} 240}
255 241
@@ -349,7 +335,8 @@ qla27xx_fwdt_entry_t260(struct scsi_qla_host *vha,
349 335
350 ql_dbg(ql_dbg_misc, vha, 0xd204, 336 ql_dbg(ql_dbg_misc, vha, 0xd204,
351 "%s: rdpci [%lx]\n", __func__, *len); 337 "%s: rdpci [%lx]\n", __func__, *len);
352 qla27xx_read_reg(reg, ent->t260.pci_addr, buf, len); 338 qla27xx_insert32(ent->t260.pci_offset, buf, len);
339 qla27xx_read_reg(reg, ent->t260.pci_offset, buf, len);
353 340
354 return false; 341 return false;
355} 342}
@@ -362,7 +349,7 @@ qla27xx_fwdt_entry_t261(struct scsi_qla_host *vha,
362 349
363 ql_dbg(ql_dbg_misc, vha, 0xd205, 350 ql_dbg(ql_dbg_misc, vha, 0xd205,
364 "%s: wrpci [%lx]\n", __func__, *len); 351 "%s: wrpci [%lx]\n", __func__, *len);
365 qla27xx_write_reg(reg, ent->t261.pci_addr, ent->t261.write_data, buf); 352 qla27xx_write_reg(reg, ent->t261.pci_offset, ent->t261.write_data, buf);
366 353
367 return false; 354 return false;
368} 355}
@@ -405,9 +392,9 @@ qla27xx_fwdt_entry_t262(struct scsi_qla_host *vha,
405 goto done; 392 goto done;
406 } 393 }
407 394
408 if (end < start) { 395 if (end < start || end == 0) {
409 ql_dbg(ql_dbg_misc, vha, 0xd023, 396 ql_dbg(ql_dbg_misc, vha, 0xd023,
410 "%s: bad range (start=%x end=%x)\n", __func__, 397 "%s: unusable range (start=%x end=%x)\n", __func__,
411 ent->t262.end_addr, ent->t262.start_addr); 398 ent->t262.end_addr, ent->t262.start_addr);
412 qla27xx_skip_entry(ent, buf); 399 qla27xx_skip_entry(ent, buf);
413 goto done; 400 goto done;
@@ -465,17 +452,15 @@ qla27xx_fwdt_entry_t263(struct scsi_qla_host *vha,
465 ql_dbg(ql_dbg_misc, vha, 0xd025, 452 ql_dbg(ql_dbg_misc, vha, 0xd025,
466 "%s: unsupported atio queue\n", __func__); 453 "%s: unsupported atio queue\n", __func__);
467 qla27xx_skip_entry(ent, buf); 454 qla27xx_skip_entry(ent, buf);
468 goto done;
469 } else { 455 } else {
470 ql_dbg(ql_dbg_misc, vha, 0xd026, 456 ql_dbg(ql_dbg_misc, vha, 0xd026,
471 "%s: unknown queue %u\n", __func__, ent->t263.queue_type); 457 "%s: unknown queue %u\n", __func__, ent->t263.queue_type);
472 qla27xx_skip_entry(ent, buf); 458 qla27xx_skip_entry(ent, buf);
473 goto done;
474 } 459 }
475 460
476 if (buf) 461 if (buf)
477 ent->t263.num_queues = count; 462 ent->t263.num_queues = count;
478done: 463
479 return false; 464 return false;
480} 465}
481 466
@@ -612,7 +597,7 @@ qla27xx_fwdt_entry_t270(struct scsi_qla_host *vha,
612 while (dwords--) { 597 while (dwords--) {
613 qla27xx_write_reg(reg, 0xc0, addr|0x80000000, buf); 598 qla27xx_write_reg(reg, 0xc0, addr|0x80000000, buf);
614 qla27xx_insert32(addr, buf, len); 599 qla27xx_insert32(addr, buf, len);
615 qla27xx_read_off(reg, 0xc4, buf, len); 600 qla27xx_read_reg(reg, 0xc4, buf, len);
616 addr += sizeof(uint32_t); 601 addr += sizeof(uint32_t);
617 } 602 }
618 603
@@ -673,9 +658,57 @@ qla27xx_fwdt_entry_t273(struct scsi_qla_host *vha,
673 "%s: failed pcicfg read at %lx\n", __func__, addr); 658 "%s: failed pcicfg read at %lx\n", __func__, addr);
674 qla27xx_insert32(addr, buf, len); 659 qla27xx_insert32(addr, buf, len);
675 qla27xx_insert32(value, buf, len); 660 qla27xx_insert32(value, buf, len);
676 addr += 4; 661 addr += sizeof(uint32_t);
662 }
663
664 return false;
665}
666
667static int
668qla27xx_fwdt_entry_t274(struct scsi_qla_host *vha,
669 struct qla27xx_fwdt_entry *ent, void *buf, ulong *len)
670{
671 uint count = 0;
672 uint i;
673
674 ql_dbg(ql_dbg_misc, vha, 0xd212,
675 "%s: getqsh(%x) [%lx]\n", __func__, ent->t274.queue_type, *len);
676 if (ent->t274.queue_type == T274_QUEUE_TYPE_REQ_SHAD) {
677 for (i = 0; i < vha->hw->max_req_queues; i++) {
678 struct req_que *req = vha->hw->req_q_map[i];
679 if (req || !buf) {
680 qla27xx_insert16(i, buf, len);
681 qla27xx_insert16(1, buf, len);
682 qla27xx_insert32(0, buf, len);
683 count++;
684 }
685 }
686 } else if (ent->t274.queue_type == T274_QUEUE_TYPE_RSP_SHAD) {
687 for (i = 0; i < vha->hw->max_rsp_queues; i++) {
688 struct rsp_que *rsp = vha->hw->rsp_q_map[i];
689 if (rsp || !buf) {
690 qla27xx_insert16(i, buf, len);
691 qla27xx_insert16(1, buf, len);
692 qla27xx_insert32(0, buf, len);
693 count++;
694 }
695 }
696 } else if (ent->t274.queue_type == T274_QUEUE_TYPE_ATIO_SHAD) {
697 ql_dbg(ql_dbg_misc, vha, 0xd02e,
698 "%s: unsupported atio queue\n", __func__);
699 qla27xx_skip_entry(ent, buf);
700 } else {
701 ql_dbg(ql_dbg_misc, vha, 0xd02f,
702 "%s: unknown queue %u\n", __func__, ent->t274.queue_type);
703 qla27xx_skip_entry(ent, buf);
677 } 704 }
678 705
706 if (buf)
707 ent->t274.num_queues = count;
708
709 if (!count)
710 qla27xx_skip_entry(ent, buf);
711
679 return false; 712 return false;
680} 713}
681 714
@@ -720,6 +753,7 @@ static struct qla27xx_fwdt_entry_call ql27xx_fwdt_entry_call_list[] = {
720 { ENTRY_TYPE_WRREMREG , qla27xx_fwdt_entry_t271 } , 753 { ENTRY_TYPE_WRREMREG , qla27xx_fwdt_entry_t271 } ,
721 { ENTRY_TYPE_RDREMRAM , qla27xx_fwdt_entry_t272 } , 754 { ENTRY_TYPE_RDREMRAM , qla27xx_fwdt_entry_t272 } ,
722 { ENTRY_TYPE_PCICFG , qla27xx_fwdt_entry_t273 } , 755 { ENTRY_TYPE_PCICFG , qla27xx_fwdt_entry_t273 } ,
756 { ENTRY_TYPE_GET_SHADOW , qla27xx_fwdt_entry_t274 } ,
723 { -1 , qla27xx_fwdt_entry_other } 757 { -1 , qla27xx_fwdt_entry_other }
724}; 758};
725 759
diff --git a/drivers/scsi/qla2xxx/qla_tmpl.h b/drivers/scsi/qla2xxx/qla_tmpl.h
index ce1593c80f6a..1967424c8e64 100644
--- a/drivers/scsi/qla2xxx/qla_tmpl.h
+++ b/drivers/scsi/qla2xxx/qla_tmpl.h
@@ -52,6 +52,7 @@ struct __packed qla27xx_fwdt_template {
52#define ENTRY_TYPE_WRREMREG 271 52#define ENTRY_TYPE_WRREMREG 271
53#define ENTRY_TYPE_RDREMRAM 272 53#define ENTRY_TYPE_RDREMRAM 272
54#define ENTRY_TYPE_PCICFG 273 54#define ENTRY_TYPE_PCICFG 273
55#define ENTRY_TYPE_GET_SHADOW 274
55 56
56#define CAPTURE_FLAG_PHYS_ONLY BIT_0 57#define CAPTURE_FLAG_PHYS_ONLY BIT_0
57#define CAPTURE_FLAG_PHYS_VIRT BIT_1 58#define CAPTURE_FLAG_PHYS_VIRT BIT_1
@@ -109,12 +110,12 @@ struct __packed qla27xx_fwdt_entry {
109 } t259; 110 } t259;
110 111
111 struct __packed { 112 struct __packed {
112 uint8_t pci_addr; 113 uint8_t pci_offset;
113 uint8_t reserved[3]; 114 uint8_t reserved[3];
114 } t260; 115 } t260;
115 116
116 struct __packed { 117 struct __packed {
117 uint8_t pci_addr; 118 uint8_t pci_offset;
118 uint8_t reserved[3]; 119 uint8_t reserved[3];
119 uint32_t write_data; 120 uint32_t write_data;
120 } t261; 121 } t261;
@@ -186,6 +187,12 @@ struct __packed qla27xx_fwdt_entry {
186 uint32_t addr; 187 uint32_t addr;
187 uint32_t count; 188 uint32_t count;
188 } t273; 189 } t273;
190
191 struct __packed {
192 uint32_t num_queues;
193 uint8_t queue_type;
194 uint8_t reserved[3];
195 } t274;
189 }; 196 };
190}; 197};
191 198
@@ -202,4 +209,8 @@ struct __packed qla27xx_fwdt_entry {
202#define T268_BUF_TYPE_EXCH_BUFOFF 2 209#define T268_BUF_TYPE_EXCH_BUFOFF 2
203#define T268_BUF_TYPE_EXTD_LOGIN 3 210#define T268_BUF_TYPE_EXTD_LOGIN 3
204 211
212#define T274_QUEUE_TYPE_REQ_SHAD 1
213#define T274_QUEUE_TYPE_RSP_SHAD 2
214#define T274_QUEUE_TYPE_ATIO_SHAD 3
215
205#endif 216#endif