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authorAndrea Bastoni <bastoni@cs.unc.edu>2010-05-30 19:16:45 -0400
committerAndrea Bastoni <bastoni@cs.unc.edu>2010-05-30 19:16:45 -0400
commitada47b5fe13d89735805b566185f4885f5a3f750 (patch)
tree644b88f8a71896307d71438e9b3af49126ffb22b /drivers/scsi/pm8001
parent43e98717ad40a4ae64545b5ba047c7b86aa44f4f (diff)
parent3280f21d43ee541f97f8cda5792150d2dbec20d5 (diff)
Merge branch 'wip-2.6.34' into old-private-masterarchived-private-master
Diffstat (limited to 'drivers/scsi/pm8001')
-rw-r--r--drivers/scsi/pm8001/Makefile12
-rw-r--r--drivers/scsi/pm8001/pm8001_chips.h89
-rw-r--r--drivers/scsi/pm8001/pm8001_ctl.c574
-rw-r--r--drivers/scsi/pm8001/pm8001_ctl.h57
-rw-r--r--drivers/scsi/pm8001/pm8001_defs.h112
-rw-r--r--drivers/scsi/pm8001/pm8001_hwi.c4494
-rw-r--r--drivers/scsi/pm8001/pm8001_hwi.h1029
-rw-r--r--drivers/scsi/pm8001/pm8001_init.c901
-rw-r--r--drivers/scsi/pm8001/pm8001_sas.c1153
-rw-r--r--drivers/scsi/pm8001/pm8001_sas.h497
10 files changed, 8918 insertions, 0 deletions
diff --git a/drivers/scsi/pm8001/Makefile b/drivers/scsi/pm8001/Makefile
new file mode 100644
index 000000000000..52f04296171c
--- /dev/null
+++ b/drivers/scsi/pm8001/Makefile
@@ -0,0 +1,12 @@
1#
2# Kernel configuration file for the PM8001 SAS/SATA 8x6G based HBA driver
3#
4# Copyright (C) 2008-2009 USI Co., Ltd.
5
6
7obj-$(CONFIG_SCSI_PM8001) += pm8001.o
8pm8001-y += pm8001_init.o \
9 pm8001_sas.o \
10 pm8001_ctl.o \
11 pm8001_hwi.o
12
diff --git a/drivers/scsi/pm8001/pm8001_chips.h b/drivers/scsi/pm8001/pm8001_chips.h
new file mode 100644
index 000000000000..4efa4d0950e5
--- /dev/null
+++ b/drivers/scsi/pm8001/pm8001_chips.h
@@ -0,0 +1,89 @@
1/*
2 * PMC-Sierra SPC 8001 SAS/SATA based host adapters driver
3 *
4 * Copyright (c) 2008-2009 USI Co., Ltd.
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions, and the following disclaimer,
12 * without modification.
13 * 2. Redistributions in binary form must reproduce at minimum a disclaimer
14 * substantially similar to the "NO WARRANTY" disclaimer below
15 * ("Disclaimer") and any redistribution must be conditioned upon
16 * including a substantially similar Disclaimer requirement for further
17 * binary redistribution.
18 * 3. Neither the names of the above-listed copyright holders nor the names
19 * of any contributors may be used to endorse or promote products derived
20 * from this software without specific prior written permission.
21 *
22 * Alternatively, this software may be distributed under the terms of the
23 * GNU General Public License ("GPL") version 2 as published by the Free
24 * Software Foundation.
25 *
26 * NO WARRANTY
27 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
28 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
29 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR
30 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
31 * HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
32 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
33 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
34 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
35 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
36 * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
37 * POSSIBILITY OF SUCH DAMAGES.
38 *
39 */
40
41#ifndef _PM8001_CHIPS_H_
42#define _PM8001_CHIPS_H_
43
44static inline u32 pm8001_read_32(void *virt_addr)
45{
46 return *((u32 *)virt_addr);
47}
48
49static inline void pm8001_write_32(void *addr, u32 offset, u32 val)
50{
51 *((u32 *)(addr + offset)) = val;
52}
53
54static inline u32 pm8001_cr32(struct pm8001_hba_info *pm8001_ha, u32 bar,
55 u32 offset)
56{
57 return readl(pm8001_ha->io_mem[bar].memvirtaddr + offset);
58}
59
60static inline void pm8001_cw32(struct pm8001_hba_info *pm8001_ha, u32 bar,
61 u32 addr, u32 val)
62{
63 writel(val, pm8001_ha->io_mem[bar].memvirtaddr + addr);
64}
65static inline u32 pm8001_mr32(void __iomem *addr, u32 offset)
66{
67 return readl(addr + offset);
68}
69static inline void pm8001_mw32(void __iomem *addr, u32 offset, u32 val)
70{
71 writel(val, addr + offset);
72}
73static inline u32 get_pci_bar_index(u32 pcibar)
74{
75 switch (pcibar) {
76 case 0x18:
77 case 0x1C:
78 return 1;
79 case 0x20:
80 return 2;
81 case 0x24:
82 return 3;
83 default:
84 return 0;
85 }
86}
87
88#endif /* _PM8001_CHIPS_H_ */
89
diff --git a/drivers/scsi/pm8001/pm8001_ctl.c b/drivers/scsi/pm8001/pm8001_ctl.c
new file mode 100644
index 000000000000..45bc197bc22f
--- /dev/null
+++ b/drivers/scsi/pm8001/pm8001_ctl.c
@@ -0,0 +1,574 @@
1/*
2 * PMC-Sierra SPC 8001 SAS/SATA based host adapters driver
3 *
4 * Copyright (c) 2008-2009 USI Co., Ltd.
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions, and the following disclaimer,
12 * without modification.
13 * 2. Redistributions in binary form must reproduce at minimum a disclaimer
14 * substantially similar to the "NO WARRANTY" disclaimer below
15 * ("Disclaimer") and any redistribution must be conditioned upon
16 * including a substantially similar Disclaimer requirement for further
17 * binary redistribution.
18 * 3. Neither the names of the above-listed copyright holders nor the names
19 * of any contributors may be used to endorse or promote products derived
20 * from this software without specific prior written permission.
21 *
22 * Alternatively, this software may be distributed under the terms of the
23 * GNU General Public License ("GPL") version 2 as published by the Free
24 * Software Foundation.
25 *
26 * NO WARRANTY
27 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
28 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
29 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR
30 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
31 * HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
32 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
33 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
34 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
35 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
36 * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
37 * POSSIBILITY OF SUCH DAMAGES.
38 *
39 */
40#include <linux/firmware.h>
41#include <linux/slab.h>
42#include "pm8001_sas.h"
43#include "pm8001_ctl.h"
44
45/* scsi host attributes */
46
47/**
48 * pm8001_ctl_mpi_interface_rev_show - MPI interface revision number
49 * @cdev: pointer to embedded class device
50 * @buf: the buffer returned
51 *
52 * A sysfs 'read-only' shost attribute.
53 */
54static ssize_t pm8001_ctl_mpi_interface_rev_show(struct device *cdev,
55 struct device_attribute *attr, char *buf)
56{
57 struct Scsi_Host *shost = class_to_shost(cdev);
58 struct sas_ha_struct *sha = SHOST_TO_SAS_HA(shost);
59 struct pm8001_hba_info *pm8001_ha = sha->lldd_ha;
60
61 return snprintf(buf, PAGE_SIZE, "%d\n",
62 pm8001_ha->main_cfg_tbl.interface_rev);
63}
64static
65DEVICE_ATTR(interface_rev, S_IRUGO, pm8001_ctl_mpi_interface_rev_show, NULL);
66
67/**
68 * pm8001_ctl_fw_version_show - firmware version
69 * @cdev: pointer to embedded class device
70 * @buf: the buffer returned
71 *
72 * A sysfs 'read-only' shost attribute.
73 */
74static ssize_t pm8001_ctl_fw_version_show(struct device *cdev,
75 struct device_attribute *attr, char *buf)
76{
77 struct Scsi_Host *shost = class_to_shost(cdev);
78 struct sas_ha_struct *sha = SHOST_TO_SAS_HA(shost);
79 struct pm8001_hba_info *pm8001_ha = sha->lldd_ha;
80
81 return snprintf(buf, PAGE_SIZE, "%02x.%02x.%02x.%02x\n",
82 (u8)(pm8001_ha->main_cfg_tbl.firmware_rev >> 24),
83 (u8)(pm8001_ha->main_cfg_tbl.firmware_rev >> 16),
84 (u8)(pm8001_ha->main_cfg_tbl.firmware_rev >> 8),
85 (u8)(pm8001_ha->main_cfg_tbl.firmware_rev));
86}
87static DEVICE_ATTR(fw_version, S_IRUGO, pm8001_ctl_fw_version_show, NULL);
88/**
89 * pm8001_ctl_max_out_io_show - max outstanding io supported
90 * @cdev: pointer to embedded class device
91 * @buf: the buffer returned
92 *
93 * A sysfs 'read-only' shost attribute.
94 */
95static ssize_t pm8001_ctl_max_out_io_show(struct device *cdev,
96 struct device_attribute *attr, char *buf)
97{
98 struct Scsi_Host *shost = class_to_shost(cdev);
99 struct sas_ha_struct *sha = SHOST_TO_SAS_HA(shost);
100 struct pm8001_hba_info *pm8001_ha = sha->lldd_ha;
101
102 return snprintf(buf, PAGE_SIZE, "%d\n",
103 pm8001_ha->main_cfg_tbl.max_out_io);
104}
105static DEVICE_ATTR(max_out_io, S_IRUGO, pm8001_ctl_max_out_io_show, NULL);
106/**
107 * pm8001_ctl_max_devices_show - max devices support
108 * @cdev: pointer to embedded class device
109 * @buf: the buffer returned
110 *
111 * A sysfs 'read-only' shost attribute.
112 */
113static ssize_t pm8001_ctl_max_devices_show(struct device *cdev,
114 struct device_attribute *attr, char *buf)
115{
116 struct Scsi_Host *shost = class_to_shost(cdev);
117 struct sas_ha_struct *sha = SHOST_TO_SAS_HA(shost);
118 struct pm8001_hba_info *pm8001_ha = sha->lldd_ha;
119
120 return snprintf(buf, PAGE_SIZE, "%04d\n",
121 (u16)(pm8001_ha->main_cfg_tbl.max_sgl >> 16));
122}
123static DEVICE_ATTR(max_devices, S_IRUGO, pm8001_ctl_max_devices_show, NULL);
124/**
125 * pm8001_ctl_max_sg_list_show - max sg list supported iff not 0.0 for no
126 * hardware limitation
127 * @cdev: pointer to embedded class device
128 * @buf: the buffer returned
129 *
130 * A sysfs 'read-only' shost attribute.
131 */
132static ssize_t pm8001_ctl_max_sg_list_show(struct device *cdev,
133 struct device_attribute *attr, char *buf)
134{
135 struct Scsi_Host *shost = class_to_shost(cdev);
136 struct sas_ha_struct *sha = SHOST_TO_SAS_HA(shost);
137 struct pm8001_hba_info *pm8001_ha = sha->lldd_ha;
138
139 return snprintf(buf, PAGE_SIZE, "%04d\n",
140 pm8001_ha->main_cfg_tbl.max_sgl & 0x0000FFFF);
141}
142static DEVICE_ATTR(max_sg_list, S_IRUGO, pm8001_ctl_max_sg_list_show, NULL);
143
144#define SAS_1_0 0x1
145#define SAS_1_1 0x2
146#define SAS_2_0 0x4
147
148static ssize_t
149show_sas_spec_support_status(unsigned int mode, char *buf)
150{
151 ssize_t len = 0;
152
153 if (mode & SAS_1_1)
154 len = sprintf(buf, "%s", "SAS1.1");
155 if (mode & SAS_2_0)
156 len += sprintf(buf + len, "%s%s", len ? ", " : "", "SAS2.0");
157 len += sprintf(buf + len, "\n");
158
159 return len;
160}
161
162/**
163 * pm8001_ctl_sas_spec_support_show - sas spec supported
164 * @cdev: pointer to embedded class device
165 * @buf: the buffer returned
166 *
167 * A sysfs 'read-only' shost attribute.
168 */
169static ssize_t pm8001_ctl_sas_spec_support_show(struct device *cdev,
170 struct device_attribute *attr, char *buf)
171{
172 unsigned int mode;
173 struct Scsi_Host *shost = class_to_shost(cdev);
174 struct sas_ha_struct *sha = SHOST_TO_SAS_HA(shost);
175 struct pm8001_hba_info *pm8001_ha = sha->lldd_ha;
176 mode = (pm8001_ha->main_cfg_tbl.ctrl_cap_flag & 0xfe000000)>>25;
177 return show_sas_spec_support_status(mode, buf);
178}
179static DEVICE_ATTR(sas_spec_support, S_IRUGO,
180 pm8001_ctl_sas_spec_support_show, NULL);
181
182/**
183 * pm8001_ctl_sas_address_show - sas address
184 * @cdev: pointer to embedded class device
185 * @buf: the buffer returned
186 *
187 * This is the controller sas address
188 *
189 * A sysfs 'read-only' shost attribute.
190 */
191static ssize_t pm8001_ctl_host_sas_address_show(struct device *cdev,
192 struct device_attribute *attr, char *buf)
193{
194 struct Scsi_Host *shost = class_to_shost(cdev);
195 struct sas_ha_struct *sha = SHOST_TO_SAS_HA(shost);
196 struct pm8001_hba_info *pm8001_ha = sha->lldd_ha;
197 return snprintf(buf, PAGE_SIZE, "0x%016llx\n",
198 be64_to_cpu(*(__be64 *)pm8001_ha->sas_addr));
199}
200static DEVICE_ATTR(host_sas_address, S_IRUGO,
201 pm8001_ctl_host_sas_address_show, NULL);
202
203/**
204 * pm8001_ctl_logging_level_show - logging level
205 * @cdev: pointer to embedded class device
206 * @buf: the buffer returned
207 *
208 * A sysfs 'read/write' shost attribute.
209 */
210static ssize_t pm8001_ctl_logging_level_show(struct device *cdev,
211 struct device_attribute *attr, char *buf)
212{
213 struct Scsi_Host *shost = class_to_shost(cdev);
214 struct sas_ha_struct *sha = SHOST_TO_SAS_HA(shost);
215 struct pm8001_hba_info *pm8001_ha = sha->lldd_ha;
216
217 return snprintf(buf, PAGE_SIZE, "%08xh\n", pm8001_ha->logging_level);
218}
219static ssize_t pm8001_ctl_logging_level_store(struct device *cdev,
220 struct device_attribute *attr, const char *buf, size_t count)
221{
222 struct Scsi_Host *shost = class_to_shost(cdev);
223 struct sas_ha_struct *sha = SHOST_TO_SAS_HA(shost);
224 struct pm8001_hba_info *pm8001_ha = sha->lldd_ha;
225 int val = 0;
226
227 if (sscanf(buf, "%x", &val) != 1)
228 return -EINVAL;
229
230 pm8001_ha->logging_level = val;
231 return strlen(buf);
232}
233
234static DEVICE_ATTR(logging_level, S_IRUGO | S_IWUSR,
235 pm8001_ctl_logging_level_show, pm8001_ctl_logging_level_store);
236/**
237 * pm8001_ctl_aap_log_show - aap1 event log
238 * @cdev: pointer to embedded class device
239 * @buf: the buffer returned
240 *
241 * A sysfs 'read-only' shost attribute.
242 */
243static ssize_t pm8001_ctl_aap_log_show(struct device *cdev,
244 struct device_attribute *attr, char *buf)
245{
246 struct Scsi_Host *shost = class_to_shost(cdev);
247 struct sas_ha_struct *sha = SHOST_TO_SAS_HA(shost);
248 struct pm8001_hba_info *pm8001_ha = sha->lldd_ha;
249 int i;
250#define AAP1_MEMMAP(r, c) \
251 (*(u32 *)((u8*)pm8001_ha->memoryMap.region[AAP1].virt_ptr + (r) * 32 \
252 + (c)))
253
254 char *str = buf;
255 int max = 2;
256 for (i = 0; i < max; i++) {
257 str += sprintf(str, "0x%08x 0x%08x 0x%08x 0x%08x 0x%08x 0x%08x"
258 "0x%08x 0x%08x\n",
259 AAP1_MEMMAP(i, 0),
260 AAP1_MEMMAP(i, 4),
261 AAP1_MEMMAP(i, 8),
262 AAP1_MEMMAP(i, 12),
263 AAP1_MEMMAP(i, 16),
264 AAP1_MEMMAP(i, 20),
265 AAP1_MEMMAP(i, 24),
266 AAP1_MEMMAP(i, 28));
267 }
268
269 return str - buf;
270}
271static DEVICE_ATTR(aap_log, S_IRUGO, pm8001_ctl_aap_log_show, NULL);
272/**
273 * pm8001_ctl_aap_log_show - IOP event log
274 * @cdev: pointer to embedded class device
275 * @buf: the buffer returned
276 *
277 * A sysfs 'read-only' shost attribute.
278 */
279static ssize_t pm8001_ctl_iop_log_show(struct device *cdev,
280 struct device_attribute *attr, char *buf)
281{
282 struct Scsi_Host *shost = class_to_shost(cdev);
283 struct sas_ha_struct *sha = SHOST_TO_SAS_HA(shost);
284 struct pm8001_hba_info *pm8001_ha = sha->lldd_ha;
285#define IOP_MEMMAP(r, c) \
286 (*(u32 *)((u8*)pm8001_ha->memoryMap.region[IOP].virt_ptr + (r) * 32 \
287 + (c)))
288 int i;
289 char *str = buf;
290 int max = 2;
291 for (i = 0; i < max; i++) {
292 str += sprintf(str, "0x%08x 0x%08x 0x%08x 0x%08x 0x%08x 0x%08x"
293 "0x%08x 0x%08x\n",
294 IOP_MEMMAP(i, 0),
295 IOP_MEMMAP(i, 4),
296 IOP_MEMMAP(i, 8),
297 IOP_MEMMAP(i, 12),
298 IOP_MEMMAP(i, 16),
299 IOP_MEMMAP(i, 20),
300 IOP_MEMMAP(i, 24),
301 IOP_MEMMAP(i, 28));
302 }
303
304 return str - buf;
305}
306static DEVICE_ATTR(iop_log, S_IRUGO, pm8001_ctl_iop_log_show, NULL);
307
308#define FLASH_CMD_NONE 0x00
309#define FLASH_CMD_UPDATE 0x01
310#define FLASH_CMD_SET_NVMD 0x02
311
312struct flash_command {
313 u8 command[8];
314 int code;
315};
316
317static struct flash_command flash_command_table[] =
318{
319 {"set_nvmd", FLASH_CMD_SET_NVMD},
320 {"update", FLASH_CMD_UPDATE},
321 {"", FLASH_CMD_NONE} /* Last entry should be NULL. */
322};
323
324struct error_fw {
325 char *reason;
326 int err_code;
327};
328
329static struct error_fw flash_error_table[] =
330{
331 {"Failed to open fw image file", FAIL_OPEN_BIOS_FILE},
332 {"image header mismatch", FLASH_UPDATE_HDR_ERR},
333 {"image offset mismatch", FLASH_UPDATE_OFFSET_ERR},
334 {"image CRC Error", FLASH_UPDATE_CRC_ERR},
335 {"image length Error.", FLASH_UPDATE_LENGTH_ERR},
336 {"Failed to program flash chip", FLASH_UPDATE_HW_ERR},
337 {"Flash chip not supported.", FLASH_UPDATE_DNLD_NOT_SUPPORTED},
338 {"Flash update disabled.", FLASH_UPDATE_DISABLED},
339 {"Flash in progress", FLASH_IN_PROGRESS},
340 {"Image file size Error", FAIL_FILE_SIZE},
341 {"Input parameter error", FAIL_PARAMETERS},
342 {"Out of memory", FAIL_OUT_MEMORY},
343 {"OK", 0} /* Last entry err_code = 0. */
344};
345
346static int pm8001_set_nvmd(struct pm8001_hba_info *pm8001_ha)
347{
348 struct pm8001_ioctl_payload *payload;
349 DECLARE_COMPLETION_ONSTACK(completion);
350 u8 *ioctlbuffer = NULL;
351 u32 length = 0;
352 u32 ret = 0;
353
354 length = 1024 * 5 + sizeof(*payload) - 1;
355 ioctlbuffer = kzalloc(length, GFP_KERNEL);
356 if (!ioctlbuffer)
357 return -ENOMEM;
358 if ((pm8001_ha->fw_image->size <= 0) ||
359 (pm8001_ha->fw_image->size > 4096)) {
360 ret = FAIL_FILE_SIZE;
361 goto out;
362 }
363 payload = (struct pm8001_ioctl_payload *)ioctlbuffer;
364 memcpy((u8 *)payload->func_specific, (u8 *)pm8001_ha->fw_image->data,
365 pm8001_ha->fw_image->size);
366 payload->length = pm8001_ha->fw_image->size;
367 payload->id = 0;
368 pm8001_ha->nvmd_completion = &completion;
369 ret = PM8001_CHIP_DISP->set_nvmd_req(pm8001_ha, payload);
370 wait_for_completion(&completion);
371out:
372 kfree(ioctlbuffer);
373 return ret;
374}
375
376static int pm8001_update_flash(struct pm8001_hba_info *pm8001_ha)
377{
378 struct pm8001_ioctl_payload *payload;
379 DECLARE_COMPLETION_ONSTACK(completion);
380 u8 *ioctlbuffer = NULL;
381 u32 length = 0;
382 struct fw_control_info *fwControl;
383 u32 loopNumber, loopcount = 0;
384 u32 sizeRead = 0;
385 u32 partitionSize, partitionSizeTmp;
386 u32 ret = 0;
387 u32 partitionNumber = 0;
388 struct pm8001_fw_image_header *image_hdr;
389
390 length = 1024 * 16 + sizeof(*payload) - 1;
391 ioctlbuffer = kzalloc(length, GFP_KERNEL);
392 image_hdr = (struct pm8001_fw_image_header *)pm8001_ha->fw_image->data;
393 if (!ioctlbuffer)
394 return -ENOMEM;
395 if (pm8001_ha->fw_image->size < 28) {
396 ret = FAIL_FILE_SIZE;
397 goto out;
398 }
399
400 while (sizeRead < pm8001_ha->fw_image->size) {
401 partitionSizeTmp =
402 *(u32 *)((u8 *)&image_hdr->image_length + sizeRead);
403 partitionSize = be32_to_cpu(partitionSizeTmp);
404 loopcount = (partitionSize + HEADER_LEN)/IOCTL_BUF_SIZE;
405 if (loopcount % IOCTL_BUF_SIZE)
406 loopcount++;
407 if (loopcount == 0)
408 loopcount++;
409 for (loopNumber = 0; loopNumber < loopcount; loopNumber++) {
410 payload = (struct pm8001_ioctl_payload *)ioctlbuffer;
411 payload->length = 1024*16;
412 payload->id = 0;
413 fwControl =
414 (struct fw_control_info *)payload->func_specific;
415 fwControl->len = IOCTL_BUF_SIZE; /* IN */
416 fwControl->size = partitionSize + HEADER_LEN;/* IN */
417 fwControl->retcode = 0;/* OUT */
418 fwControl->offset = loopNumber * IOCTL_BUF_SIZE;/*OUT */
419
420 /* for the last chunk of data in case file size is not even with
421 4k, load only the rest*/
422 if (((loopcount-loopNumber) == 1) &&
423 ((partitionSize + HEADER_LEN) % IOCTL_BUF_SIZE)) {
424 fwControl->len =
425 (partitionSize + HEADER_LEN) % IOCTL_BUF_SIZE;
426 memcpy((u8 *)fwControl->buffer,
427 (u8 *)pm8001_ha->fw_image->data + sizeRead,
428 (partitionSize + HEADER_LEN) % IOCTL_BUF_SIZE);
429 sizeRead +=
430 (partitionSize + HEADER_LEN) % IOCTL_BUF_SIZE;
431 } else {
432 memcpy((u8 *)fwControl->buffer,
433 (u8 *)pm8001_ha->fw_image->data + sizeRead,
434 IOCTL_BUF_SIZE);
435 sizeRead += IOCTL_BUF_SIZE;
436 }
437
438 pm8001_ha->nvmd_completion = &completion;
439 ret = PM8001_CHIP_DISP->fw_flash_update_req(pm8001_ha, payload);
440 wait_for_completion(&completion);
441 if (ret || (fwControl->retcode > FLASH_UPDATE_IN_PROGRESS)) {
442 ret = fwControl->retcode;
443 kfree(ioctlbuffer);
444 ioctlbuffer = NULL;
445 break;
446 }
447 }
448 if (ret)
449 break;
450 partitionNumber++;
451}
452out:
453 kfree(ioctlbuffer);
454 return ret;
455}
456static ssize_t pm8001_store_update_fw(struct device *cdev,
457 struct device_attribute *attr,
458 const char *buf, size_t count)
459{
460 struct Scsi_Host *shost = class_to_shost(cdev);
461 struct sas_ha_struct *sha = SHOST_TO_SAS_HA(shost);
462 struct pm8001_hba_info *pm8001_ha = sha->lldd_ha;
463 char *cmd_ptr, *filename_ptr;
464 int res, i;
465 int flash_command = FLASH_CMD_NONE;
466 int err = 0;
467 if (!capable(CAP_SYS_ADMIN))
468 return -EACCES;
469
470 cmd_ptr = kzalloc(count*2, GFP_KERNEL);
471
472 if (!cmd_ptr) {
473 err = FAIL_OUT_MEMORY;
474 goto out;
475 }
476
477 filename_ptr = cmd_ptr + count;
478 res = sscanf(buf, "%s %s", cmd_ptr, filename_ptr);
479 if (res != 2) {
480 err = FAIL_PARAMETERS;
481 goto out1;
482 }
483
484 for (i = 0; flash_command_table[i].code != FLASH_CMD_NONE; i++) {
485 if (!memcmp(flash_command_table[i].command,
486 cmd_ptr, strlen(cmd_ptr))) {
487 flash_command = flash_command_table[i].code;
488 break;
489 }
490 }
491 if (flash_command == FLASH_CMD_NONE) {
492 err = FAIL_PARAMETERS;
493 goto out1;
494 }
495
496 if (pm8001_ha->fw_status == FLASH_IN_PROGRESS) {
497 err = FLASH_IN_PROGRESS;
498 goto out1;
499 }
500 err = request_firmware(&pm8001_ha->fw_image,
501 filename_ptr,
502 pm8001_ha->dev);
503
504 if (err) {
505 PM8001_FAIL_DBG(pm8001_ha,
506 pm8001_printk("Failed to load firmware image file %s,"
507 " error %d\n", filename_ptr, err));
508 err = FAIL_OPEN_BIOS_FILE;
509 goto out1;
510 }
511
512 switch (flash_command) {
513 case FLASH_CMD_UPDATE:
514 pm8001_ha->fw_status = FLASH_IN_PROGRESS;
515 err = pm8001_update_flash(pm8001_ha);
516 break;
517 case FLASH_CMD_SET_NVMD:
518 pm8001_ha->fw_status = FLASH_IN_PROGRESS;
519 err = pm8001_set_nvmd(pm8001_ha);
520 break;
521 default:
522 pm8001_ha->fw_status = FAIL_PARAMETERS;
523 err = FAIL_PARAMETERS;
524 break;
525 }
526 release_firmware(pm8001_ha->fw_image);
527out1:
528 kfree(cmd_ptr);
529out:
530 pm8001_ha->fw_status = err;
531
532 if (!err)
533 return count;
534 else
535 return -err;
536}
537
538static ssize_t pm8001_show_update_fw(struct device *cdev,
539 struct device_attribute *attr, char *buf)
540{
541 int i;
542 struct Scsi_Host *shost = class_to_shost(cdev);
543 struct sas_ha_struct *sha = SHOST_TO_SAS_HA(shost);
544 struct pm8001_hba_info *pm8001_ha = sha->lldd_ha;
545
546 for (i = 0; flash_error_table[i].err_code != 0; i++) {
547 if (flash_error_table[i].err_code == pm8001_ha->fw_status)
548 break;
549 }
550 if (pm8001_ha->fw_status != FLASH_IN_PROGRESS)
551 pm8001_ha->fw_status = FLASH_OK;
552
553 return snprintf(buf, PAGE_SIZE, "status=%x %s\n",
554 flash_error_table[i].err_code,
555 flash_error_table[i].reason);
556}
557
558static DEVICE_ATTR(update_fw, S_IRUGO|S_IWUGO,
559 pm8001_show_update_fw, pm8001_store_update_fw);
560struct device_attribute *pm8001_host_attrs[] = {
561 &dev_attr_interface_rev,
562 &dev_attr_fw_version,
563 &dev_attr_update_fw,
564 &dev_attr_aap_log,
565 &dev_attr_iop_log,
566 &dev_attr_max_out_io,
567 &dev_attr_max_devices,
568 &dev_attr_max_sg_list,
569 &dev_attr_sas_spec_support,
570 &dev_attr_logging_level,
571 &dev_attr_host_sas_address,
572 NULL,
573};
574
diff --git a/drivers/scsi/pm8001/pm8001_ctl.h b/drivers/scsi/pm8001/pm8001_ctl.h
new file mode 100644
index 000000000000..63ad4aa0c422
--- /dev/null
+++ b/drivers/scsi/pm8001/pm8001_ctl.h
@@ -0,0 +1,57 @@
1 /*
2 * PMC-Sierra SPC 8001 SAS/SATA based host adapters driver
3 *
4 * Copyright (c) 2008-2009 USI Co., Ltd.
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions, and the following disclaimer,
12 * without modification.
13 * 2. Redistributions in binary form must reproduce at minimum a disclaimer
14 * substantially similar to the "NO WARRANTY" disclaimer below
15 * ("Disclaimer") and any redistribution must be conditioned upon
16 * including a substantially similar Disclaimer requirement for further
17 * binary redistribution.
18 * 3. Neither the names of the above-listed copyright holders nor the names
19 * of any contributors may be used to endorse or promote products derived
20 * from this software without specific prior written permission.
21 *
22 * Alternatively, this software may be distributed under the terms of the
23 * GNU General Public License ("GPL") version 2 as published by the Free
24 * Software Foundation.
25 *
26 * NO WARRANTY
27 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
28 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
29 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR
30 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
31 * HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
32 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
33 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
34 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
35 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
36 * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
37 * POSSIBILITY OF SUCH DAMAGES.
38 *
39 */
40
41#ifndef PM8001_CTL_H_INCLUDED
42#define PM8001_CTL_H_INCLUDED
43
44#define IOCTL_BUF_SIZE 4096
45#define HEADER_LEN 28
46#define SIZE_OFFSET 16
47
48
49#define FLASH_OK 0x000000
50#define FAIL_OPEN_BIOS_FILE 0x000100
51#define FAIL_FILE_SIZE 0x000a00
52#define FAIL_PARAMETERS 0x000b00
53#define FAIL_OUT_MEMORY 0x000c00
54#define FLASH_IN_PROGRESS 0x001000
55
56#endif /* PM8001_CTL_H_INCLUDED */
57
diff --git a/drivers/scsi/pm8001/pm8001_defs.h b/drivers/scsi/pm8001/pm8001_defs.h
new file mode 100644
index 000000000000..944afada61ee
--- /dev/null
+++ b/drivers/scsi/pm8001/pm8001_defs.h
@@ -0,0 +1,112 @@
1/*
2 * PMC-Sierra SPC 8001 SAS/SATA based host adapters driver
3 *
4 * Copyright (c) 2008-2009 USI Co., Ltd.
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions, and the following disclaimer,
12 * without modification.
13 * 2. Redistributions in binary form must reproduce at minimum a disclaimer
14 * substantially similar to the "NO WARRANTY" disclaimer below
15 * ("Disclaimer") and any redistribution must be conditioned upon
16 * including a substantially similar Disclaimer requirement for further
17 * binary redistribution.
18 * 3. Neither the names of the above-listed copyright holders nor the names
19 * of any contributors may be used to endorse or promote products derived
20 * from this software without specific prior written permission.
21 *
22 * Alternatively, this software may be distributed under the terms of the
23 * GNU General Public License ("GPL") version 2 as published by the Free
24 * Software Foundation.
25 *
26 * NO WARRANTY
27 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
28 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
29 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR
30 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
31 * HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
32 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
33 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
34 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
35 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
36 * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
37 * POSSIBILITY OF SUCH DAMAGES.
38 *
39 */
40
41#ifndef _PM8001_DEFS_H_
42#define _PM8001_DEFS_H_
43
44enum chip_flavors {
45 chip_8001,
46};
47#define USI_MAX_MEMCNT 9
48#define PM8001_MAX_DMA_SG SG_ALL
49enum phy_speed {
50 PHY_SPEED_15 = 0x01,
51 PHY_SPEED_30 = 0x02,
52 PHY_SPEED_60 = 0x04,
53};
54
55enum data_direction {
56 DATA_DIR_NONE = 0x0, /* NO TRANSFER */
57 DATA_DIR_IN = 0x01, /* INBOUND */
58 DATA_DIR_OUT = 0x02, /* OUTBOUND */
59 DATA_DIR_BYRECIPIENT = 0x04, /* UNSPECIFIED */
60};
61
62enum port_type {
63 PORT_TYPE_SAS = (1L << 1),
64 PORT_TYPE_SATA = (1L << 0),
65};
66
67/* driver compile-time configuration */
68#define PM8001_MAX_CCB 512 /* max ccbs supported */
69#define PM8001_MAX_INB_NUM 1
70#define PM8001_MAX_OUTB_NUM 1
71#define PM8001_CAN_QUEUE 128 /* SCSI Queue depth */
72
73/* unchangeable hardware details */
74#define PM8001_MAX_PHYS 8 /* max. possible phys */
75#define PM8001_MAX_PORTS 8 /* max. possible ports */
76#define PM8001_MAX_DEVICES 1024 /* max supported device */
77
78enum memory_region_num {
79 AAP1 = 0x0, /* application acceleration processor */
80 IOP, /* IO processor */
81 CI, /* consumer index */
82 PI, /* producer index */
83 IB, /* inbound queue */
84 OB, /* outbound queue */
85 NVMD, /* NVM device */
86 DEV_MEM, /* memory for devices */
87 CCB_MEM, /* memory for command control block */
88};
89#define PM8001_EVENT_LOG_SIZE (128 * 1024)
90
91/*error code*/
92enum mpi_err {
93 MPI_IO_STATUS_SUCCESS = 0x0,
94 MPI_IO_STATUS_BUSY = 0x01,
95 MPI_IO_STATUS_FAIL = 0x02,
96};
97
98/**
99 * Phy Control constants
100 */
101enum phy_control_type {
102 PHY_LINK_RESET = 0x01,
103 PHY_HARD_RESET = 0x02,
104 PHY_NOTIFY_ENABLE_SPINUP = 0x10,
105};
106
107enum pm8001_hba_info_flags {
108 PM8001F_INIT_TIME = (1U << 0),
109 PM8001F_RUN_TIME = (1U << 1),
110};
111
112#endif
diff --git a/drivers/scsi/pm8001/pm8001_hwi.c b/drivers/scsi/pm8001/pm8001_hwi.c
new file mode 100644
index 000000000000..909c00ec044f
--- /dev/null
+++ b/drivers/scsi/pm8001/pm8001_hwi.c
@@ -0,0 +1,4494 @@
1/*
2 * PMC-Sierra SPC 8001 SAS/SATA based host adapters driver
3 *
4 * Copyright (c) 2008-2009 USI Co., Ltd.
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions, and the following disclaimer,
12 * without modification.
13 * 2. Redistributions in binary form must reproduce at minimum a disclaimer
14 * substantially similar to the "NO WARRANTY" disclaimer below
15 * ("Disclaimer") and any redistribution must be conditioned upon
16 * including a substantially similar Disclaimer requirement for further
17 * binary redistribution.
18 * 3. Neither the names of the above-listed copyright holders nor the names
19 * of any contributors may be used to endorse or promote products derived
20 * from this software without specific prior written permission.
21 *
22 * Alternatively, this software may be distributed under the terms of the
23 * GNU General Public License ("GPL") version 2 as published by the Free
24 * Software Foundation.
25 *
26 * NO WARRANTY
27 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
28 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
29 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR
30 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
31 * HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
32 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
33 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
34 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
35 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
36 * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
37 * POSSIBILITY OF SUCH DAMAGES.
38 *
39 */
40 #include <linux/slab.h>
41 #include "pm8001_sas.h"
42 #include "pm8001_hwi.h"
43 #include "pm8001_chips.h"
44 #include "pm8001_ctl.h"
45
46/**
47 * read_main_config_table - read the configure table and save it.
48 * @pm8001_ha: our hba card information
49 */
50static void __devinit read_main_config_table(struct pm8001_hba_info *pm8001_ha)
51{
52 void __iomem *address = pm8001_ha->main_cfg_tbl_addr;
53 pm8001_ha->main_cfg_tbl.signature = pm8001_mr32(address, 0x00);
54 pm8001_ha->main_cfg_tbl.interface_rev = pm8001_mr32(address, 0x04);
55 pm8001_ha->main_cfg_tbl.firmware_rev = pm8001_mr32(address, 0x08);
56 pm8001_ha->main_cfg_tbl.max_out_io = pm8001_mr32(address, 0x0C);
57 pm8001_ha->main_cfg_tbl.max_sgl = pm8001_mr32(address, 0x10);
58 pm8001_ha->main_cfg_tbl.ctrl_cap_flag = pm8001_mr32(address, 0x14);
59 pm8001_ha->main_cfg_tbl.gst_offset = pm8001_mr32(address, 0x18);
60 pm8001_ha->main_cfg_tbl.inbound_queue_offset =
61 pm8001_mr32(address, MAIN_IBQ_OFFSET);
62 pm8001_ha->main_cfg_tbl.outbound_queue_offset =
63 pm8001_mr32(address, MAIN_OBQ_OFFSET);
64 pm8001_ha->main_cfg_tbl.hda_mode_flag =
65 pm8001_mr32(address, MAIN_HDA_FLAGS_OFFSET);
66
67 /* read analog Setting offset from the configuration table */
68 pm8001_ha->main_cfg_tbl.anolog_setup_table_offset =
69 pm8001_mr32(address, MAIN_ANALOG_SETUP_OFFSET);
70
71 /* read Error Dump Offset and Length */
72 pm8001_ha->main_cfg_tbl.fatal_err_dump_offset0 =
73 pm8001_mr32(address, MAIN_FATAL_ERROR_RDUMP0_OFFSET);
74 pm8001_ha->main_cfg_tbl.fatal_err_dump_length0 =
75 pm8001_mr32(address, MAIN_FATAL_ERROR_RDUMP0_LENGTH);
76 pm8001_ha->main_cfg_tbl.fatal_err_dump_offset1 =
77 pm8001_mr32(address, MAIN_FATAL_ERROR_RDUMP1_OFFSET);
78 pm8001_ha->main_cfg_tbl.fatal_err_dump_length1 =
79 pm8001_mr32(address, MAIN_FATAL_ERROR_RDUMP1_LENGTH);
80}
81
82/**
83 * read_general_status_table - read the general status table and save it.
84 * @pm8001_ha: our hba card information
85 */
86static void __devinit
87read_general_status_table(struct pm8001_hba_info *pm8001_ha)
88{
89 void __iomem *address = pm8001_ha->general_stat_tbl_addr;
90 pm8001_ha->gs_tbl.gst_len_mpistate = pm8001_mr32(address, 0x00);
91 pm8001_ha->gs_tbl.iq_freeze_state0 = pm8001_mr32(address, 0x04);
92 pm8001_ha->gs_tbl.iq_freeze_state1 = pm8001_mr32(address, 0x08);
93 pm8001_ha->gs_tbl.msgu_tcnt = pm8001_mr32(address, 0x0C);
94 pm8001_ha->gs_tbl.iop_tcnt = pm8001_mr32(address, 0x10);
95 pm8001_ha->gs_tbl.reserved = pm8001_mr32(address, 0x14);
96 pm8001_ha->gs_tbl.phy_state[0] = pm8001_mr32(address, 0x18);
97 pm8001_ha->gs_tbl.phy_state[1] = pm8001_mr32(address, 0x1C);
98 pm8001_ha->gs_tbl.phy_state[2] = pm8001_mr32(address, 0x20);
99 pm8001_ha->gs_tbl.phy_state[3] = pm8001_mr32(address, 0x24);
100 pm8001_ha->gs_tbl.phy_state[4] = pm8001_mr32(address, 0x28);
101 pm8001_ha->gs_tbl.phy_state[5] = pm8001_mr32(address, 0x2C);
102 pm8001_ha->gs_tbl.phy_state[6] = pm8001_mr32(address, 0x30);
103 pm8001_ha->gs_tbl.phy_state[7] = pm8001_mr32(address, 0x34);
104 pm8001_ha->gs_tbl.reserved1 = pm8001_mr32(address, 0x38);
105 pm8001_ha->gs_tbl.reserved2 = pm8001_mr32(address, 0x3C);
106 pm8001_ha->gs_tbl.reserved3 = pm8001_mr32(address, 0x40);
107 pm8001_ha->gs_tbl.recover_err_info[0] = pm8001_mr32(address, 0x44);
108 pm8001_ha->gs_tbl.recover_err_info[1] = pm8001_mr32(address, 0x48);
109 pm8001_ha->gs_tbl.recover_err_info[2] = pm8001_mr32(address, 0x4C);
110 pm8001_ha->gs_tbl.recover_err_info[3] = pm8001_mr32(address, 0x50);
111 pm8001_ha->gs_tbl.recover_err_info[4] = pm8001_mr32(address, 0x54);
112 pm8001_ha->gs_tbl.recover_err_info[5] = pm8001_mr32(address, 0x58);
113 pm8001_ha->gs_tbl.recover_err_info[6] = pm8001_mr32(address, 0x5C);
114 pm8001_ha->gs_tbl.recover_err_info[7] = pm8001_mr32(address, 0x60);
115}
116
117/**
118 * read_inbnd_queue_table - read the inbound queue table and save it.
119 * @pm8001_ha: our hba card information
120 */
121static void __devinit
122read_inbnd_queue_table(struct pm8001_hba_info *pm8001_ha)
123{
124 int inbQ_num = 1;
125 int i;
126 void __iomem *address = pm8001_ha->inbnd_q_tbl_addr;
127 for (i = 0; i < inbQ_num; i++) {
128 u32 offset = i * 0x20;
129 pm8001_ha->inbnd_q_tbl[i].pi_pci_bar =
130 get_pci_bar_index(pm8001_mr32(address, (offset + 0x14)));
131 pm8001_ha->inbnd_q_tbl[i].pi_offset =
132 pm8001_mr32(address, (offset + 0x18));
133 }
134}
135
136/**
137 * read_outbnd_queue_table - read the outbound queue table and save it.
138 * @pm8001_ha: our hba card information
139 */
140static void __devinit
141read_outbnd_queue_table(struct pm8001_hba_info *pm8001_ha)
142{
143 int outbQ_num = 1;
144 int i;
145 void __iomem *address = pm8001_ha->outbnd_q_tbl_addr;
146 for (i = 0; i < outbQ_num; i++) {
147 u32 offset = i * 0x24;
148 pm8001_ha->outbnd_q_tbl[i].ci_pci_bar =
149 get_pci_bar_index(pm8001_mr32(address, (offset + 0x14)));
150 pm8001_ha->outbnd_q_tbl[i].ci_offset =
151 pm8001_mr32(address, (offset + 0x18));
152 }
153}
154
155/**
156 * init_default_table_values - init the default table.
157 * @pm8001_ha: our hba card information
158 */
159static void __devinit
160init_default_table_values(struct pm8001_hba_info *pm8001_ha)
161{
162 int qn = 1;
163 int i;
164 u32 offsetib, offsetob;
165 void __iomem *addressib = pm8001_ha->inbnd_q_tbl_addr;
166 void __iomem *addressob = pm8001_ha->outbnd_q_tbl_addr;
167
168 pm8001_ha->main_cfg_tbl.inbound_q_nppd_hppd = 0;
169 pm8001_ha->main_cfg_tbl.outbound_hw_event_pid0_3 = 0;
170 pm8001_ha->main_cfg_tbl.outbound_hw_event_pid4_7 = 0;
171 pm8001_ha->main_cfg_tbl.outbound_ncq_event_pid0_3 = 0;
172 pm8001_ha->main_cfg_tbl.outbound_ncq_event_pid4_7 = 0;
173 pm8001_ha->main_cfg_tbl.outbound_tgt_ITNexus_event_pid0_3 = 0;
174 pm8001_ha->main_cfg_tbl.outbound_tgt_ITNexus_event_pid4_7 = 0;
175 pm8001_ha->main_cfg_tbl.outbound_tgt_ssp_event_pid0_3 = 0;
176 pm8001_ha->main_cfg_tbl.outbound_tgt_ssp_event_pid4_7 = 0;
177 pm8001_ha->main_cfg_tbl.outbound_tgt_smp_event_pid0_3 = 0;
178 pm8001_ha->main_cfg_tbl.outbound_tgt_smp_event_pid4_7 = 0;
179
180 pm8001_ha->main_cfg_tbl.upper_event_log_addr =
181 pm8001_ha->memoryMap.region[AAP1].phys_addr_hi;
182 pm8001_ha->main_cfg_tbl.lower_event_log_addr =
183 pm8001_ha->memoryMap.region[AAP1].phys_addr_lo;
184 pm8001_ha->main_cfg_tbl.event_log_size = PM8001_EVENT_LOG_SIZE;
185 pm8001_ha->main_cfg_tbl.event_log_option = 0x01;
186 pm8001_ha->main_cfg_tbl.upper_iop_event_log_addr =
187 pm8001_ha->memoryMap.region[IOP].phys_addr_hi;
188 pm8001_ha->main_cfg_tbl.lower_iop_event_log_addr =
189 pm8001_ha->memoryMap.region[IOP].phys_addr_lo;
190 pm8001_ha->main_cfg_tbl.iop_event_log_size = PM8001_EVENT_LOG_SIZE;
191 pm8001_ha->main_cfg_tbl.iop_event_log_option = 0x01;
192 pm8001_ha->main_cfg_tbl.fatal_err_interrupt = 0x01;
193 for (i = 0; i < qn; i++) {
194 pm8001_ha->inbnd_q_tbl[i].element_pri_size_cnt =
195 0x00000100 | (0x00000040 << 16) | (0x00<<30);
196 pm8001_ha->inbnd_q_tbl[i].upper_base_addr =
197 pm8001_ha->memoryMap.region[IB].phys_addr_hi;
198 pm8001_ha->inbnd_q_tbl[i].lower_base_addr =
199 pm8001_ha->memoryMap.region[IB].phys_addr_lo;
200 pm8001_ha->inbnd_q_tbl[i].base_virt =
201 (u8 *)pm8001_ha->memoryMap.region[IB].virt_ptr;
202 pm8001_ha->inbnd_q_tbl[i].total_length =
203 pm8001_ha->memoryMap.region[IB].total_len;
204 pm8001_ha->inbnd_q_tbl[i].ci_upper_base_addr =
205 pm8001_ha->memoryMap.region[CI].phys_addr_hi;
206 pm8001_ha->inbnd_q_tbl[i].ci_lower_base_addr =
207 pm8001_ha->memoryMap.region[CI].phys_addr_lo;
208 pm8001_ha->inbnd_q_tbl[i].ci_virt =
209 pm8001_ha->memoryMap.region[CI].virt_ptr;
210 offsetib = i * 0x20;
211 pm8001_ha->inbnd_q_tbl[i].pi_pci_bar =
212 get_pci_bar_index(pm8001_mr32(addressib,
213 (offsetib + 0x14)));
214 pm8001_ha->inbnd_q_tbl[i].pi_offset =
215 pm8001_mr32(addressib, (offsetib + 0x18));
216 pm8001_ha->inbnd_q_tbl[i].producer_idx = 0;
217 pm8001_ha->inbnd_q_tbl[i].consumer_index = 0;
218 }
219 for (i = 0; i < qn; i++) {
220 pm8001_ha->outbnd_q_tbl[i].element_size_cnt =
221 256 | (64 << 16) | (1<<30);
222 pm8001_ha->outbnd_q_tbl[i].upper_base_addr =
223 pm8001_ha->memoryMap.region[OB].phys_addr_hi;
224 pm8001_ha->outbnd_q_tbl[i].lower_base_addr =
225 pm8001_ha->memoryMap.region[OB].phys_addr_lo;
226 pm8001_ha->outbnd_q_tbl[i].base_virt =
227 (u8 *)pm8001_ha->memoryMap.region[OB].virt_ptr;
228 pm8001_ha->outbnd_q_tbl[i].total_length =
229 pm8001_ha->memoryMap.region[OB].total_len;
230 pm8001_ha->outbnd_q_tbl[i].pi_upper_base_addr =
231 pm8001_ha->memoryMap.region[PI].phys_addr_hi;
232 pm8001_ha->outbnd_q_tbl[i].pi_lower_base_addr =
233 pm8001_ha->memoryMap.region[PI].phys_addr_lo;
234 pm8001_ha->outbnd_q_tbl[i].interrup_vec_cnt_delay =
235 0 | (10 << 16) | (0 << 24);
236 pm8001_ha->outbnd_q_tbl[i].pi_virt =
237 pm8001_ha->memoryMap.region[PI].virt_ptr;
238 offsetob = i * 0x24;
239 pm8001_ha->outbnd_q_tbl[i].ci_pci_bar =
240 get_pci_bar_index(pm8001_mr32(addressob,
241 offsetob + 0x14));
242 pm8001_ha->outbnd_q_tbl[i].ci_offset =
243 pm8001_mr32(addressob, (offsetob + 0x18));
244 pm8001_ha->outbnd_q_tbl[i].consumer_idx = 0;
245 pm8001_ha->outbnd_q_tbl[i].producer_index = 0;
246 }
247}
248
249/**
250 * update_main_config_table - update the main default table to the HBA.
251 * @pm8001_ha: our hba card information
252 */
253static void __devinit
254update_main_config_table(struct pm8001_hba_info *pm8001_ha)
255{
256 void __iomem *address = pm8001_ha->main_cfg_tbl_addr;
257 pm8001_mw32(address, 0x24,
258 pm8001_ha->main_cfg_tbl.inbound_q_nppd_hppd);
259 pm8001_mw32(address, 0x28,
260 pm8001_ha->main_cfg_tbl.outbound_hw_event_pid0_3);
261 pm8001_mw32(address, 0x2C,
262 pm8001_ha->main_cfg_tbl.outbound_hw_event_pid4_7);
263 pm8001_mw32(address, 0x30,
264 pm8001_ha->main_cfg_tbl.outbound_ncq_event_pid0_3);
265 pm8001_mw32(address, 0x34,
266 pm8001_ha->main_cfg_tbl.outbound_ncq_event_pid4_7);
267 pm8001_mw32(address, 0x38,
268 pm8001_ha->main_cfg_tbl.outbound_tgt_ITNexus_event_pid0_3);
269 pm8001_mw32(address, 0x3C,
270 pm8001_ha->main_cfg_tbl.outbound_tgt_ITNexus_event_pid4_7);
271 pm8001_mw32(address, 0x40,
272 pm8001_ha->main_cfg_tbl.outbound_tgt_ssp_event_pid0_3);
273 pm8001_mw32(address, 0x44,
274 pm8001_ha->main_cfg_tbl.outbound_tgt_ssp_event_pid4_7);
275 pm8001_mw32(address, 0x48,
276 pm8001_ha->main_cfg_tbl.outbound_tgt_smp_event_pid0_3);
277 pm8001_mw32(address, 0x4C,
278 pm8001_ha->main_cfg_tbl.outbound_tgt_smp_event_pid4_7);
279 pm8001_mw32(address, 0x50,
280 pm8001_ha->main_cfg_tbl.upper_event_log_addr);
281 pm8001_mw32(address, 0x54,
282 pm8001_ha->main_cfg_tbl.lower_event_log_addr);
283 pm8001_mw32(address, 0x58, pm8001_ha->main_cfg_tbl.event_log_size);
284 pm8001_mw32(address, 0x5C, pm8001_ha->main_cfg_tbl.event_log_option);
285 pm8001_mw32(address, 0x60,
286 pm8001_ha->main_cfg_tbl.upper_iop_event_log_addr);
287 pm8001_mw32(address, 0x64,
288 pm8001_ha->main_cfg_tbl.lower_iop_event_log_addr);
289 pm8001_mw32(address, 0x68, pm8001_ha->main_cfg_tbl.iop_event_log_size);
290 pm8001_mw32(address, 0x6C,
291 pm8001_ha->main_cfg_tbl.iop_event_log_option);
292 pm8001_mw32(address, 0x70,
293 pm8001_ha->main_cfg_tbl.fatal_err_interrupt);
294}
295
296/**
297 * update_inbnd_queue_table - update the inbound queue table to the HBA.
298 * @pm8001_ha: our hba card information
299 */
300static void __devinit
301update_inbnd_queue_table(struct pm8001_hba_info *pm8001_ha, int number)
302{
303 void __iomem *address = pm8001_ha->inbnd_q_tbl_addr;
304 u16 offset = number * 0x20;
305 pm8001_mw32(address, offset + 0x00,
306 pm8001_ha->inbnd_q_tbl[number].element_pri_size_cnt);
307 pm8001_mw32(address, offset + 0x04,
308 pm8001_ha->inbnd_q_tbl[number].upper_base_addr);
309 pm8001_mw32(address, offset + 0x08,
310 pm8001_ha->inbnd_q_tbl[number].lower_base_addr);
311 pm8001_mw32(address, offset + 0x0C,
312 pm8001_ha->inbnd_q_tbl[number].ci_upper_base_addr);
313 pm8001_mw32(address, offset + 0x10,
314 pm8001_ha->inbnd_q_tbl[number].ci_lower_base_addr);
315}
316
317/**
318 * update_outbnd_queue_table - update the outbound queue table to the HBA.
319 * @pm8001_ha: our hba card information
320 */
321static void __devinit
322update_outbnd_queue_table(struct pm8001_hba_info *pm8001_ha, int number)
323{
324 void __iomem *address = pm8001_ha->outbnd_q_tbl_addr;
325 u16 offset = number * 0x24;
326 pm8001_mw32(address, offset + 0x00,
327 pm8001_ha->outbnd_q_tbl[number].element_size_cnt);
328 pm8001_mw32(address, offset + 0x04,
329 pm8001_ha->outbnd_q_tbl[number].upper_base_addr);
330 pm8001_mw32(address, offset + 0x08,
331 pm8001_ha->outbnd_q_tbl[number].lower_base_addr);
332 pm8001_mw32(address, offset + 0x0C,
333 pm8001_ha->outbnd_q_tbl[number].pi_upper_base_addr);
334 pm8001_mw32(address, offset + 0x10,
335 pm8001_ha->outbnd_q_tbl[number].pi_lower_base_addr);
336 pm8001_mw32(address, offset + 0x1C,
337 pm8001_ha->outbnd_q_tbl[number].interrup_vec_cnt_delay);
338}
339
340/**
341 * bar4_shift - function is called to shift BAR base address
342 * @pm8001_ha : our hba card infomation
343 * @shiftValue : shifting value in memory bar.
344 */
345static int bar4_shift(struct pm8001_hba_info *pm8001_ha, u32 shiftValue)
346{
347 u32 regVal;
348 u32 max_wait_count;
349
350 /* program the inbound AXI translation Lower Address */
351 pm8001_cw32(pm8001_ha, 1, SPC_IBW_AXI_TRANSLATION_LOW, shiftValue);
352
353 /* confirm the setting is written */
354 max_wait_count = 1 * 1000 * 1000; /* 1 sec */
355 do {
356 udelay(1);
357 regVal = pm8001_cr32(pm8001_ha, 1, SPC_IBW_AXI_TRANSLATION_LOW);
358 } while ((regVal != shiftValue) && (--max_wait_count));
359
360 if (!max_wait_count) {
361 PM8001_INIT_DBG(pm8001_ha,
362 pm8001_printk("TIMEOUT:SPC_IBW_AXI_TRANSLATION_LOW"
363 " = 0x%x\n", regVal));
364 return -1;
365 }
366 return 0;
367}
368
369/**
370 * mpi_set_phys_g3_with_ssc
371 * @pm8001_ha: our hba card information
372 * @SSCbit: set SSCbit to 0 to disable all phys ssc; 1 to enable all phys ssc.
373 */
374static void __devinit
375mpi_set_phys_g3_with_ssc(struct pm8001_hba_info *pm8001_ha, u32 SSCbit)
376{
377 u32 value, offset, i;
378
379#define SAS2_SETTINGS_LOCAL_PHY_0_3_SHIFT_ADDR 0x00030000
380#define SAS2_SETTINGS_LOCAL_PHY_4_7_SHIFT_ADDR 0x00040000
381#define SAS2_SETTINGS_LOCAL_PHY_0_3_OFFSET 0x1074
382#define SAS2_SETTINGS_LOCAL_PHY_4_7_OFFSET 0x1074
383#define PHY_G3_WITHOUT_SSC_BIT_SHIFT 12
384#define PHY_G3_WITH_SSC_BIT_SHIFT 13
385#define SNW3_PHY_CAPABILITIES_PARITY 31
386
387 /*
388 * Using shifted destination address 0x3_0000:0x1074 + 0x4000*N (N=0:3)
389 * Using shifted destination address 0x4_0000:0x1074 + 0x4000*(N-4) (N=4:7)
390 */
391 if (-1 == bar4_shift(pm8001_ha, SAS2_SETTINGS_LOCAL_PHY_0_3_SHIFT_ADDR))
392 return;
393
394 for (i = 0; i < 4; i++) {
395 offset = SAS2_SETTINGS_LOCAL_PHY_0_3_OFFSET + 0x4000 * i;
396 pm8001_cw32(pm8001_ha, 2, offset, 0x80001501);
397 }
398 /* shift membase 3 for SAS2_SETTINGS_LOCAL_PHY 4 - 7 */
399 if (-1 == bar4_shift(pm8001_ha, SAS2_SETTINGS_LOCAL_PHY_4_7_SHIFT_ADDR))
400 return;
401 for (i = 4; i < 8; i++) {
402 offset = SAS2_SETTINGS_LOCAL_PHY_4_7_OFFSET + 0x4000 * (i-4);
403 pm8001_cw32(pm8001_ha, 2, offset, 0x80001501);
404 }
405 /*************************************************************
406 Change the SSC upspreading value to 0x0 so that upspreading is disabled.
407 Device MABC SMOD0 Controls
408 Address: (via MEMBASE-III):
409 Using shifted destination address 0x0_0000: with Offset 0xD8
410
411 31:28 R/W Reserved Do not change
412 27:24 R/W SAS_SMOD_SPRDUP 0000
413 23:20 R/W SAS_SMOD_SPRDDN 0000
414 19:0 R/W Reserved Do not change
415 Upon power-up this register will read as 0x8990c016,
416 and I would like you to change the SAS_SMOD_SPRDUP bits to 0b0000
417 so that the written value will be 0x8090c016.
418 This will ensure only down-spreading SSC is enabled on the SPC.
419 *************************************************************/
420 value = pm8001_cr32(pm8001_ha, 2, 0xd8);
421 pm8001_cw32(pm8001_ha, 2, 0xd8, 0x8000C016);
422
423 /*set the shifted destination address to 0x0 to avoid error operation */
424 bar4_shift(pm8001_ha, 0x0);
425 return;
426}
427
428/**
429 * mpi_set_open_retry_interval_reg
430 * @pm8001_ha: our hba card information
431 * @interval - interval time for each OPEN_REJECT (RETRY). The units are in 1us.
432 */
433static void __devinit
434mpi_set_open_retry_interval_reg(struct pm8001_hba_info *pm8001_ha,
435 u32 interval)
436{
437 u32 offset;
438 u32 value;
439 u32 i;
440
441#define OPEN_RETRY_INTERVAL_PHY_0_3_SHIFT_ADDR 0x00030000
442#define OPEN_RETRY_INTERVAL_PHY_4_7_SHIFT_ADDR 0x00040000
443#define OPEN_RETRY_INTERVAL_PHY_0_3_OFFSET 0x30B4
444#define OPEN_RETRY_INTERVAL_PHY_4_7_OFFSET 0x30B4
445#define OPEN_RETRY_INTERVAL_REG_MASK 0x0000FFFF
446
447 value = interval & OPEN_RETRY_INTERVAL_REG_MASK;
448 /* shift bar and set the OPEN_REJECT(RETRY) interval time of PHY 0 -3.*/
449 if (-1 == bar4_shift(pm8001_ha,
450 OPEN_RETRY_INTERVAL_PHY_0_3_SHIFT_ADDR))
451 return;
452 for (i = 0; i < 4; i++) {
453 offset = OPEN_RETRY_INTERVAL_PHY_0_3_OFFSET + 0x4000 * i;
454 pm8001_cw32(pm8001_ha, 2, offset, value);
455 }
456
457 if (-1 == bar4_shift(pm8001_ha,
458 OPEN_RETRY_INTERVAL_PHY_4_7_SHIFT_ADDR))
459 return;
460 for (i = 4; i < 8; i++) {
461 offset = OPEN_RETRY_INTERVAL_PHY_4_7_OFFSET + 0x4000 * (i-4);
462 pm8001_cw32(pm8001_ha, 2, offset, value);
463 }
464 /*set the shifted destination address to 0x0 to avoid error operation */
465 bar4_shift(pm8001_ha, 0x0);
466 return;
467}
468
469/**
470 * mpi_init_check - check firmware initialization status.
471 * @pm8001_ha: our hba card information
472 */
473static int mpi_init_check(struct pm8001_hba_info *pm8001_ha)
474{
475 u32 max_wait_count;
476 u32 value;
477 u32 gst_len_mpistate;
478 /* Write bit0=1 to Inbound DoorBell Register to tell the SPC FW the
479 table is updated */
480 pm8001_cw32(pm8001_ha, 0, MSGU_IBDB_SET, SPC_MSGU_CFG_TABLE_UPDATE);
481 /* wait until Inbound DoorBell Clear Register toggled */
482 max_wait_count = 1 * 1000 * 1000;/* 1 sec */
483 do {
484 udelay(1);
485 value = pm8001_cr32(pm8001_ha, 0, MSGU_IBDB_SET);
486 value &= SPC_MSGU_CFG_TABLE_UPDATE;
487 } while ((value != 0) && (--max_wait_count));
488
489 if (!max_wait_count)
490 return -1;
491 /* check the MPI-State for initialization */
492 gst_len_mpistate =
493 pm8001_mr32(pm8001_ha->general_stat_tbl_addr,
494 GST_GSTLEN_MPIS_OFFSET);
495 if (GST_MPI_STATE_INIT != (gst_len_mpistate & GST_MPI_STATE_MASK))
496 return -1;
497 /* check MPI Initialization error */
498 gst_len_mpistate = gst_len_mpistate >> 16;
499 if (0x0000 != gst_len_mpistate)
500 return -1;
501 return 0;
502}
503
504/**
505 * check_fw_ready - The LLDD check if the FW is ready, if not, return error.
506 * @pm8001_ha: our hba card information
507 */
508static int check_fw_ready(struct pm8001_hba_info *pm8001_ha)
509{
510 u32 value, value1;
511 u32 max_wait_count;
512 /* check error state */
513 value = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_1);
514 value1 = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_2);
515 /* check AAP error */
516 if (SCRATCH_PAD1_ERR == (value & SCRATCH_PAD_STATE_MASK)) {
517 /* error state */
518 value = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_0);
519 return -1;
520 }
521
522 /* check IOP error */
523 if (SCRATCH_PAD2_ERR == (value1 & SCRATCH_PAD_STATE_MASK)) {
524 /* error state */
525 value1 = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_3);
526 return -1;
527 }
528
529 /* bit 4-31 of scratch pad1 should be zeros if it is not
530 in error state*/
531 if (value & SCRATCH_PAD1_STATE_MASK) {
532 /* error case */
533 pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_0);
534 return -1;
535 }
536
537 /* bit 2, 4-31 of scratch pad2 should be zeros if it is not
538 in error state */
539 if (value1 & SCRATCH_PAD2_STATE_MASK) {
540 /* error case */
541 return -1;
542 }
543
544 max_wait_count = 1 * 1000 * 1000;/* 1 sec timeout */
545
546 /* wait until scratch pad 1 and 2 registers in ready state */
547 do {
548 udelay(1);
549 value = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_1)
550 & SCRATCH_PAD1_RDY;
551 value1 = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_2)
552 & SCRATCH_PAD2_RDY;
553 if ((--max_wait_count) == 0)
554 return -1;
555 } while ((value != SCRATCH_PAD1_RDY) || (value1 != SCRATCH_PAD2_RDY));
556 return 0;
557}
558
559static void init_pci_device_addresses(struct pm8001_hba_info *pm8001_ha)
560{
561 void __iomem *base_addr;
562 u32 value;
563 u32 offset;
564 u32 pcibar;
565 u32 pcilogic;
566
567 value = pm8001_cr32(pm8001_ha, 0, 0x44);
568 offset = value & 0x03FFFFFF;
569 PM8001_INIT_DBG(pm8001_ha,
570 pm8001_printk("Scratchpad 0 Offset: %x \n", offset));
571 pcilogic = (value & 0xFC000000) >> 26;
572 pcibar = get_pci_bar_index(pcilogic);
573 PM8001_INIT_DBG(pm8001_ha,
574 pm8001_printk("Scratchpad 0 PCI BAR: %d \n", pcibar));
575 pm8001_ha->main_cfg_tbl_addr = base_addr =
576 pm8001_ha->io_mem[pcibar].memvirtaddr + offset;
577 pm8001_ha->general_stat_tbl_addr =
578 base_addr + pm8001_cr32(pm8001_ha, pcibar, offset + 0x18);
579 pm8001_ha->inbnd_q_tbl_addr =
580 base_addr + pm8001_cr32(pm8001_ha, pcibar, offset + 0x1C);
581 pm8001_ha->outbnd_q_tbl_addr =
582 base_addr + pm8001_cr32(pm8001_ha, pcibar, offset + 0x20);
583}
584
585/**
586 * pm8001_chip_init - the main init function that initialize whole PM8001 chip.
587 * @pm8001_ha: our hba card information
588 */
589static int __devinit pm8001_chip_init(struct pm8001_hba_info *pm8001_ha)
590{
591 /* check the firmware status */
592 if (-1 == check_fw_ready(pm8001_ha)) {
593 PM8001_FAIL_DBG(pm8001_ha,
594 pm8001_printk("Firmware is not ready!\n"));
595 return -EBUSY;
596 }
597
598 /* Initialize pci space address eg: mpi offset */
599 init_pci_device_addresses(pm8001_ha);
600 init_default_table_values(pm8001_ha);
601 read_main_config_table(pm8001_ha);
602 read_general_status_table(pm8001_ha);
603 read_inbnd_queue_table(pm8001_ha);
604 read_outbnd_queue_table(pm8001_ha);
605 /* update main config table ,inbound table and outbound table */
606 update_main_config_table(pm8001_ha);
607 update_inbnd_queue_table(pm8001_ha, 0);
608 update_outbnd_queue_table(pm8001_ha, 0);
609 mpi_set_phys_g3_with_ssc(pm8001_ha, 0);
610 mpi_set_open_retry_interval_reg(pm8001_ha, 7);
611 /* notify firmware update finished and check initialization status */
612 if (0 == mpi_init_check(pm8001_ha)) {
613 PM8001_INIT_DBG(pm8001_ha,
614 pm8001_printk("MPI initialize successful!\n"));
615 } else
616 return -EBUSY;
617 /*This register is a 16-bit timer with a resolution of 1us. This is the
618 timer used for interrupt delay/coalescing in the PCIe Application Layer.
619 Zero is not a valid value. A value of 1 in the register will cause the
620 interrupts to be normal. A value greater than 1 will cause coalescing
621 delays.*/
622 pm8001_cw32(pm8001_ha, 1, 0x0033c0, 0x1);
623 pm8001_cw32(pm8001_ha, 1, 0x0033c4, 0x0);
624 return 0;
625}
626
627static int mpi_uninit_check(struct pm8001_hba_info *pm8001_ha)
628{
629 u32 max_wait_count;
630 u32 value;
631 u32 gst_len_mpistate;
632 init_pci_device_addresses(pm8001_ha);
633 /* Write bit1=1 to Inbound DoorBell Register to tell the SPC FW the
634 table is stop */
635 pm8001_cw32(pm8001_ha, 0, MSGU_IBDB_SET, SPC_MSGU_CFG_TABLE_RESET);
636
637 /* wait until Inbound DoorBell Clear Register toggled */
638 max_wait_count = 1 * 1000 * 1000;/* 1 sec */
639 do {
640 udelay(1);
641 value = pm8001_cr32(pm8001_ha, 0, MSGU_IBDB_SET);
642 value &= SPC_MSGU_CFG_TABLE_RESET;
643 } while ((value != 0) && (--max_wait_count));
644
645 if (!max_wait_count) {
646 PM8001_FAIL_DBG(pm8001_ha,
647 pm8001_printk("TIMEOUT:IBDB value/=0x%x\n", value));
648 return -1;
649 }
650
651 /* check the MPI-State for termination in progress */
652 /* wait until Inbound DoorBell Clear Register toggled */
653 max_wait_count = 1 * 1000 * 1000; /* 1 sec */
654 do {
655 udelay(1);
656 gst_len_mpistate =
657 pm8001_mr32(pm8001_ha->general_stat_tbl_addr,
658 GST_GSTLEN_MPIS_OFFSET);
659 if (GST_MPI_STATE_UNINIT ==
660 (gst_len_mpistate & GST_MPI_STATE_MASK))
661 break;
662 } while (--max_wait_count);
663 if (!max_wait_count) {
664 PM8001_FAIL_DBG(pm8001_ha,
665 pm8001_printk(" TIME OUT MPI State = 0x%x\n",
666 gst_len_mpistate & GST_MPI_STATE_MASK));
667 return -1;
668 }
669 return 0;
670}
671
672/**
673 * soft_reset_ready_check - Function to check FW is ready for soft reset.
674 * @pm8001_ha: our hba card information
675 */
676static u32 soft_reset_ready_check(struct pm8001_hba_info *pm8001_ha)
677{
678 u32 regVal, regVal1, regVal2;
679 if (mpi_uninit_check(pm8001_ha) != 0) {
680 PM8001_FAIL_DBG(pm8001_ha,
681 pm8001_printk("MPI state is not ready\n"));
682 return -1;
683 }
684 /* read the scratch pad 2 register bit 2 */
685 regVal = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_2)
686 & SCRATCH_PAD2_FWRDY_RST;
687 if (regVal == SCRATCH_PAD2_FWRDY_RST) {
688 PM8001_INIT_DBG(pm8001_ha,
689 pm8001_printk("Firmware is ready for reset .\n"));
690 } else {
691 /* Trigger NMI twice via RB6 */
692 if (-1 == bar4_shift(pm8001_ha, RB6_ACCESS_REG)) {
693 PM8001_FAIL_DBG(pm8001_ha,
694 pm8001_printk("Shift Bar4 to 0x%x failed\n",
695 RB6_ACCESS_REG));
696 return -1;
697 }
698 pm8001_cw32(pm8001_ha, 2, SPC_RB6_OFFSET,
699 RB6_MAGIC_NUMBER_RST);
700 pm8001_cw32(pm8001_ha, 2, SPC_RB6_OFFSET, RB6_MAGIC_NUMBER_RST);
701 /* wait for 100 ms */
702 mdelay(100);
703 regVal = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_2) &
704 SCRATCH_PAD2_FWRDY_RST;
705 if (regVal != SCRATCH_PAD2_FWRDY_RST) {
706 regVal1 = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_1);
707 regVal2 = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_2);
708 PM8001_FAIL_DBG(pm8001_ha,
709 pm8001_printk("TIMEOUT:MSGU_SCRATCH_PAD1"
710 "=0x%x, MSGU_SCRATCH_PAD2=0x%x\n",
711 regVal1, regVal2));
712 PM8001_FAIL_DBG(pm8001_ha,
713 pm8001_printk("SCRATCH_PAD0 value = 0x%x\n",
714 pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_0)));
715 PM8001_FAIL_DBG(pm8001_ha,
716 pm8001_printk("SCRATCH_PAD3 value = 0x%x\n",
717 pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_3)));
718 return -1;
719 }
720 }
721 return 0;
722}
723
724/**
725 * pm8001_chip_soft_rst - soft reset the PM8001 chip, so that the clear all
726 * the FW register status to the originated status.
727 * @pm8001_ha: our hba card information
728 * @signature: signature in host scratch pad0 register.
729 */
730static int
731pm8001_chip_soft_rst(struct pm8001_hba_info *pm8001_ha, u32 signature)
732{
733 u32 regVal, toggleVal;
734 u32 max_wait_count;
735 u32 regVal1, regVal2, regVal3;
736
737 /* step1: Check FW is ready for soft reset */
738 if (soft_reset_ready_check(pm8001_ha) != 0) {
739 PM8001_FAIL_DBG(pm8001_ha, pm8001_printk("FW is not ready\n"));
740 return -1;
741 }
742
743 /* step 2: clear NMI status register on AAP1 and IOP, write the same
744 value to clear */
745 /* map 0x60000 to BAR4(0x20), BAR2(win) */
746 if (-1 == bar4_shift(pm8001_ha, MBIC_AAP1_ADDR_BASE)) {
747 PM8001_FAIL_DBG(pm8001_ha,
748 pm8001_printk("Shift Bar4 to 0x%x failed\n",
749 MBIC_AAP1_ADDR_BASE));
750 return -1;
751 }
752 regVal = pm8001_cr32(pm8001_ha, 2, MBIC_NMI_ENABLE_VPE0_IOP);
753 PM8001_INIT_DBG(pm8001_ha,
754 pm8001_printk("MBIC - NMI Enable VPE0 (IOP)= 0x%x\n", regVal));
755 pm8001_cw32(pm8001_ha, 2, MBIC_NMI_ENABLE_VPE0_IOP, 0x0);
756 /* map 0x70000 to BAR4(0x20), BAR2(win) */
757 if (-1 == bar4_shift(pm8001_ha, MBIC_IOP_ADDR_BASE)) {
758 PM8001_FAIL_DBG(pm8001_ha,
759 pm8001_printk("Shift Bar4 to 0x%x failed\n",
760 MBIC_IOP_ADDR_BASE));
761 return -1;
762 }
763 regVal = pm8001_cr32(pm8001_ha, 2, MBIC_NMI_ENABLE_VPE0_AAP1);
764 PM8001_INIT_DBG(pm8001_ha,
765 pm8001_printk("MBIC - NMI Enable VPE0 (AAP1)= 0x%x\n", regVal));
766 pm8001_cw32(pm8001_ha, 2, MBIC_NMI_ENABLE_VPE0_AAP1, 0x0);
767
768 regVal = pm8001_cr32(pm8001_ha, 1, PCIE_EVENT_INTERRUPT_ENABLE);
769 PM8001_INIT_DBG(pm8001_ha,
770 pm8001_printk("PCIE -Event Interrupt Enable = 0x%x\n", regVal));
771 pm8001_cw32(pm8001_ha, 1, PCIE_EVENT_INTERRUPT_ENABLE, 0x0);
772
773 regVal = pm8001_cr32(pm8001_ha, 1, PCIE_EVENT_INTERRUPT);
774 PM8001_INIT_DBG(pm8001_ha,
775 pm8001_printk("PCIE - Event Interrupt = 0x%x\n", regVal));
776 pm8001_cw32(pm8001_ha, 1, PCIE_EVENT_INTERRUPT, regVal);
777
778 regVal = pm8001_cr32(pm8001_ha, 1, PCIE_ERROR_INTERRUPT_ENABLE);
779 PM8001_INIT_DBG(pm8001_ha,
780 pm8001_printk("PCIE -Error Interrupt Enable = 0x%x\n", regVal));
781 pm8001_cw32(pm8001_ha, 1, PCIE_ERROR_INTERRUPT_ENABLE, 0x0);
782
783 regVal = pm8001_cr32(pm8001_ha, 1, PCIE_ERROR_INTERRUPT);
784 PM8001_INIT_DBG(pm8001_ha,
785 pm8001_printk("PCIE - Error Interrupt = 0x%x\n", regVal));
786 pm8001_cw32(pm8001_ha, 1, PCIE_ERROR_INTERRUPT, regVal);
787
788 /* read the scratch pad 1 register bit 2 */
789 regVal = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_1)
790 & SCRATCH_PAD1_RST;
791 toggleVal = regVal ^ SCRATCH_PAD1_RST;
792
793 /* set signature in host scratch pad0 register to tell SPC that the
794 host performs the soft reset */
795 pm8001_cw32(pm8001_ha, 0, MSGU_HOST_SCRATCH_PAD_0, signature);
796
797 /* read required registers for confirmming */
798 /* map 0x0700000 to BAR4(0x20), BAR2(win) */
799 if (-1 == bar4_shift(pm8001_ha, GSM_ADDR_BASE)) {
800 PM8001_FAIL_DBG(pm8001_ha,
801 pm8001_printk("Shift Bar4 to 0x%x failed\n",
802 GSM_ADDR_BASE));
803 return -1;
804 }
805 PM8001_INIT_DBG(pm8001_ha,
806 pm8001_printk("GSM 0x0(0x00007b88)-GSM Configuration and"
807 " Reset = 0x%x\n",
808 pm8001_cr32(pm8001_ha, 2, GSM_CONFIG_RESET)));
809
810 /* step 3: host read GSM Configuration and Reset register */
811 regVal = pm8001_cr32(pm8001_ha, 2, GSM_CONFIG_RESET);
812 /* Put those bits to low */
813 /* GSM XCBI offset = 0x70 0000
814 0x00 Bit 13 COM_SLV_SW_RSTB 1
815 0x00 Bit 12 QSSP_SW_RSTB 1
816 0x00 Bit 11 RAAE_SW_RSTB 1
817 0x00 Bit 9 RB_1_SW_RSTB 1
818 0x00 Bit 8 SM_SW_RSTB 1
819 */
820 regVal &= ~(0x00003b00);
821 /* host write GSM Configuration and Reset register */
822 pm8001_cw32(pm8001_ha, 2, GSM_CONFIG_RESET, regVal);
823 PM8001_INIT_DBG(pm8001_ha,
824 pm8001_printk("GSM 0x0 (0x00007b88 ==> 0x00004088) - GSM "
825 "Configuration and Reset is set to = 0x%x\n",
826 pm8001_cr32(pm8001_ha, 2, GSM_CONFIG_RESET)));
827
828 /* step 4: */
829 /* disable GSM - Read Address Parity Check */
830 regVal1 = pm8001_cr32(pm8001_ha, 2, GSM_READ_ADDR_PARITY_CHECK);
831 PM8001_INIT_DBG(pm8001_ha,
832 pm8001_printk("GSM 0x700038 - Read Address Parity Check "
833 "Enable = 0x%x\n", regVal1));
834 pm8001_cw32(pm8001_ha, 2, GSM_READ_ADDR_PARITY_CHECK, 0x0);
835 PM8001_INIT_DBG(pm8001_ha,
836 pm8001_printk("GSM 0x700038 - Read Address Parity Check Enable"
837 "is set to = 0x%x\n",
838 pm8001_cr32(pm8001_ha, 2, GSM_READ_ADDR_PARITY_CHECK)));
839
840 /* disable GSM - Write Address Parity Check */
841 regVal2 = pm8001_cr32(pm8001_ha, 2, GSM_WRITE_ADDR_PARITY_CHECK);
842 PM8001_INIT_DBG(pm8001_ha,
843 pm8001_printk("GSM 0x700040 - Write Address Parity Check"
844 " Enable = 0x%x\n", regVal2));
845 pm8001_cw32(pm8001_ha, 2, GSM_WRITE_ADDR_PARITY_CHECK, 0x0);
846 PM8001_INIT_DBG(pm8001_ha,
847 pm8001_printk("GSM 0x700040 - Write Address Parity Check "
848 "Enable is set to = 0x%x\n",
849 pm8001_cr32(pm8001_ha, 2, GSM_WRITE_ADDR_PARITY_CHECK)));
850
851 /* disable GSM - Write Data Parity Check */
852 regVal3 = pm8001_cr32(pm8001_ha, 2, GSM_WRITE_DATA_PARITY_CHECK);
853 PM8001_INIT_DBG(pm8001_ha,
854 pm8001_printk("GSM 0x300048 - Write Data Parity Check"
855 " Enable = 0x%x\n", regVal3));
856 pm8001_cw32(pm8001_ha, 2, GSM_WRITE_DATA_PARITY_CHECK, 0x0);
857 PM8001_INIT_DBG(pm8001_ha,
858 pm8001_printk("GSM 0x300048 - Write Data Parity Check Enable"
859 "is set to = 0x%x\n",
860 pm8001_cr32(pm8001_ha, 2, GSM_WRITE_DATA_PARITY_CHECK)));
861
862 /* step 5: delay 10 usec */
863 udelay(10);
864 /* step 5-b: set GPIO-0 output control to tristate anyway */
865 if (-1 == bar4_shift(pm8001_ha, GPIO_ADDR_BASE)) {
866 PM8001_INIT_DBG(pm8001_ha,
867 pm8001_printk("Shift Bar4 to 0x%x failed\n",
868 GPIO_ADDR_BASE));
869 return -1;
870 }
871 regVal = pm8001_cr32(pm8001_ha, 2, GPIO_GPIO_0_0UTPUT_CTL_OFFSET);
872 PM8001_INIT_DBG(pm8001_ha,
873 pm8001_printk("GPIO Output Control Register:"
874 " = 0x%x\n", regVal));
875 /* set GPIO-0 output control to tri-state */
876 regVal &= 0xFFFFFFFC;
877 pm8001_cw32(pm8001_ha, 2, GPIO_GPIO_0_0UTPUT_CTL_OFFSET, regVal);
878
879 /* Step 6: Reset the IOP and AAP1 */
880 /* map 0x00000 to BAR4(0x20), BAR2(win) */
881 if (-1 == bar4_shift(pm8001_ha, SPC_TOP_LEVEL_ADDR_BASE)) {
882 PM8001_FAIL_DBG(pm8001_ha,
883 pm8001_printk("SPC Shift Bar4 to 0x%x failed\n",
884 SPC_TOP_LEVEL_ADDR_BASE));
885 return -1;
886 }
887 regVal = pm8001_cr32(pm8001_ha, 2, SPC_REG_RESET);
888 PM8001_INIT_DBG(pm8001_ha,
889 pm8001_printk("Top Register before resetting IOP/AAP1"
890 ":= 0x%x\n", regVal));
891 regVal &= ~(SPC_REG_RESET_PCS_IOP_SS | SPC_REG_RESET_PCS_AAP1_SS);
892 pm8001_cw32(pm8001_ha, 2, SPC_REG_RESET, regVal);
893
894 /* step 7: Reset the BDMA/OSSP */
895 regVal = pm8001_cr32(pm8001_ha, 2, SPC_REG_RESET);
896 PM8001_INIT_DBG(pm8001_ha,
897 pm8001_printk("Top Register before resetting BDMA/OSSP"
898 ": = 0x%x\n", regVal));
899 regVal &= ~(SPC_REG_RESET_BDMA_CORE | SPC_REG_RESET_OSSP);
900 pm8001_cw32(pm8001_ha, 2, SPC_REG_RESET, regVal);
901
902 /* step 8: delay 10 usec */
903 udelay(10);
904
905 /* step 9: bring the BDMA and OSSP out of reset */
906 regVal = pm8001_cr32(pm8001_ha, 2, SPC_REG_RESET);
907 PM8001_INIT_DBG(pm8001_ha,
908 pm8001_printk("Top Register before bringing up BDMA/OSSP"
909 ":= 0x%x\n", regVal));
910 regVal |= (SPC_REG_RESET_BDMA_CORE | SPC_REG_RESET_OSSP);
911 pm8001_cw32(pm8001_ha, 2, SPC_REG_RESET, regVal);
912
913 /* step 10: delay 10 usec */
914 udelay(10);
915
916 /* step 11: reads and sets the GSM Configuration and Reset Register */
917 /* map 0x0700000 to BAR4(0x20), BAR2(win) */
918 if (-1 == bar4_shift(pm8001_ha, GSM_ADDR_BASE)) {
919 PM8001_FAIL_DBG(pm8001_ha,
920 pm8001_printk("SPC Shift Bar4 to 0x%x failed\n",
921 GSM_ADDR_BASE));
922 return -1;
923 }
924 PM8001_INIT_DBG(pm8001_ha,
925 pm8001_printk("GSM 0x0 (0x00007b88)-GSM Configuration and "
926 "Reset = 0x%x\n", pm8001_cr32(pm8001_ha, 2, GSM_CONFIG_RESET)));
927 regVal = pm8001_cr32(pm8001_ha, 2, GSM_CONFIG_RESET);
928 /* Put those bits to high */
929 /* GSM XCBI offset = 0x70 0000
930 0x00 Bit 13 COM_SLV_SW_RSTB 1
931 0x00 Bit 12 QSSP_SW_RSTB 1
932 0x00 Bit 11 RAAE_SW_RSTB 1
933 0x00 Bit 9 RB_1_SW_RSTB 1
934 0x00 Bit 8 SM_SW_RSTB 1
935 */
936 regVal |= (GSM_CONFIG_RESET_VALUE);
937 pm8001_cw32(pm8001_ha, 2, GSM_CONFIG_RESET, regVal);
938 PM8001_INIT_DBG(pm8001_ha,
939 pm8001_printk("GSM (0x00004088 ==> 0x00007b88) - GSM"
940 " Configuration and Reset is set to = 0x%x\n",
941 pm8001_cr32(pm8001_ha, 2, GSM_CONFIG_RESET)));
942
943 /* step 12: Restore GSM - Read Address Parity Check */
944 regVal = pm8001_cr32(pm8001_ha, 2, GSM_READ_ADDR_PARITY_CHECK);
945 /* just for debugging */
946 PM8001_INIT_DBG(pm8001_ha,
947 pm8001_printk("GSM 0x700038 - Read Address Parity Check Enable"
948 " = 0x%x\n", regVal));
949 pm8001_cw32(pm8001_ha, 2, GSM_READ_ADDR_PARITY_CHECK, regVal1);
950 PM8001_INIT_DBG(pm8001_ha,
951 pm8001_printk("GSM 0x700038 - Read Address Parity"
952 " Check Enable is set to = 0x%x\n",
953 pm8001_cr32(pm8001_ha, 2, GSM_READ_ADDR_PARITY_CHECK)));
954 /* Restore GSM - Write Address Parity Check */
955 regVal = pm8001_cr32(pm8001_ha, 2, GSM_WRITE_ADDR_PARITY_CHECK);
956 pm8001_cw32(pm8001_ha, 2, GSM_WRITE_ADDR_PARITY_CHECK, regVal2);
957 PM8001_INIT_DBG(pm8001_ha,
958 pm8001_printk("GSM 0x700040 - Write Address Parity Check"
959 " Enable is set to = 0x%x\n",
960 pm8001_cr32(pm8001_ha, 2, GSM_WRITE_ADDR_PARITY_CHECK)));
961 /* Restore GSM - Write Data Parity Check */
962 regVal = pm8001_cr32(pm8001_ha, 2, GSM_WRITE_DATA_PARITY_CHECK);
963 pm8001_cw32(pm8001_ha, 2, GSM_WRITE_DATA_PARITY_CHECK, regVal3);
964 PM8001_INIT_DBG(pm8001_ha,
965 pm8001_printk("GSM 0x700048 - Write Data Parity Check Enable"
966 "is set to = 0x%x\n",
967 pm8001_cr32(pm8001_ha, 2, GSM_WRITE_DATA_PARITY_CHECK)));
968
969 /* step 13: bring the IOP and AAP1 out of reset */
970 /* map 0x00000 to BAR4(0x20), BAR2(win) */
971 if (-1 == bar4_shift(pm8001_ha, SPC_TOP_LEVEL_ADDR_BASE)) {
972 PM8001_FAIL_DBG(pm8001_ha,
973 pm8001_printk("Shift Bar4 to 0x%x failed\n",
974 SPC_TOP_LEVEL_ADDR_BASE));
975 return -1;
976 }
977 regVal = pm8001_cr32(pm8001_ha, 2, SPC_REG_RESET);
978 regVal |= (SPC_REG_RESET_PCS_IOP_SS | SPC_REG_RESET_PCS_AAP1_SS);
979 pm8001_cw32(pm8001_ha, 2, SPC_REG_RESET, regVal);
980
981 /* step 14: delay 10 usec - Normal Mode */
982 udelay(10);
983 /* check Soft Reset Normal mode or Soft Reset HDA mode */
984 if (signature == SPC_SOFT_RESET_SIGNATURE) {
985 /* step 15 (Normal Mode): wait until scratch pad1 register
986 bit 2 toggled */
987 max_wait_count = 2 * 1000 * 1000;/* 2 sec */
988 do {
989 udelay(1);
990 regVal = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_1) &
991 SCRATCH_PAD1_RST;
992 } while ((regVal != toggleVal) && (--max_wait_count));
993
994 if (!max_wait_count) {
995 regVal = pm8001_cr32(pm8001_ha, 0,
996 MSGU_SCRATCH_PAD_1);
997 PM8001_FAIL_DBG(pm8001_ha,
998 pm8001_printk("TIMEOUT : ToggleVal 0x%x,"
999 "MSGU_SCRATCH_PAD1 = 0x%x\n",
1000 toggleVal, regVal));
1001 PM8001_FAIL_DBG(pm8001_ha,
1002 pm8001_printk("SCRATCH_PAD0 value = 0x%x\n",
1003 pm8001_cr32(pm8001_ha, 0,
1004 MSGU_SCRATCH_PAD_0)));
1005 PM8001_FAIL_DBG(pm8001_ha,
1006 pm8001_printk("SCRATCH_PAD2 value = 0x%x\n",
1007 pm8001_cr32(pm8001_ha, 0,
1008 MSGU_SCRATCH_PAD_2)));
1009 PM8001_FAIL_DBG(pm8001_ha,
1010 pm8001_printk("SCRATCH_PAD3 value = 0x%x\n",
1011 pm8001_cr32(pm8001_ha, 0,
1012 MSGU_SCRATCH_PAD_3)));
1013 return -1;
1014 }
1015
1016 /* step 16 (Normal) - Clear ODMR and ODCR */
1017 pm8001_cw32(pm8001_ha, 0, MSGU_ODCR, ODCR_CLEAR_ALL);
1018 pm8001_cw32(pm8001_ha, 0, MSGU_ODMR, ODMR_CLEAR_ALL);
1019
1020 /* step 17 (Normal Mode): wait for the FW and IOP to get
1021 ready - 1 sec timeout */
1022 /* Wait for the SPC Configuration Table to be ready */
1023 if (check_fw_ready(pm8001_ha) == -1) {
1024 regVal = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_1);
1025 /* return error if MPI Configuration Table not ready */
1026 PM8001_INIT_DBG(pm8001_ha,
1027 pm8001_printk("FW not ready SCRATCH_PAD1"
1028 " = 0x%x\n", regVal));
1029 regVal = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_2);
1030 /* return error if MPI Configuration Table not ready */
1031 PM8001_INIT_DBG(pm8001_ha,
1032 pm8001_printk("FW not ready SCRATCH_PAD2"
1033 " = 0x%x\n", regVal));
1034 PM8001_INIT_DBG(pm8001_ha,
1035 pm8001_printk("SCRATCH_PAD0 value = 0x%x\n",
1036 pm8001_cr32(pm8001_ha, 0,
1037 MSGU_SCRATCH_PAD_0)));
1038 PM8001_INIT_DBG(pm8001_ha,
1039 pm8001_printk("SCRATCH_PAD3 value = 0x%x\n",
1040 pm8001_cr32(pm8001_ha, 0,
1041 MSGU_SCRATCH_PAD_3)));
1042 return -1;
1043 }
1044 }
1045
1046 PM8001_INIT_DBG(pm8001_ha,
1047 pm8001_printk("SPC soft reset Complete\n"));
1048 return 0;
1049}
1050
1051static void pm8001_hw_chip_rst(struct pm8001_hba_info *pm8001_ha)
1052{
1053 u32 i;
1054 u32 regVal;
1055 PM8001_INIT_DBG(pm8001_ha,
1056 pm8001_printk("chip reset start\n"));
1057
1058 /* do SPC chip reset. */
1059 regVal = pm8001_cr32(pm8001_ha, 1, SPC_REG_RESET);
1060 regVal &= ~(SPC_REG_RESET_DEVICE);
1061 pm8001_cw32(pm8001_ha, 1, SPC_REG_RESET, regVal);
1062
1063 /* delay 10 usec */
1064 udelay(10);
1065
1066 /* bring chip reset out of reset */
1067 regVal = pm8001_cr32(pm8001_ha, 1, SPC_REG_RESET);
1068 regVal |= SPC_REG_RESET_DEVICE;
1069 pm8001_cw32(pm8001_ha, 1, SPC_REG_RESET, regVal);
1070
1071 /* delay 10 usec */
1072 udelay(10);
1073
1074 /* wait for 20 msec until the firmware gets reloaded */
1075 i = 20;
1076 do {
1077 mdelay(1);
1078 } while ((--i) != 0);
1079
1080 PM8001_INIT_DBG(pm8001_ha,
1081 pm8001_printk("chip reset finished\n"));
1082}
1083
1084/**
1085 * pm8001_chip_iounmap - which maped when initilized.
1086 * @pm8001_ha: our hba card information
1087 */
1088static void pm8001_chip_iounmap(struct pm8001_hba_info *pm8001_ha)
1089{
1090 s8 bar, logical = 0;
1091 for (bar = 0; bar < 6; bar++) {
1092 /*
1093 ** logical BARs for SPC:
1094 ** bar 0 and 1 - logical BAR0
1095 ** bar 2 and 3 - logical BAR1
1096 ** bar4 - logical BAR2
1097 ** bar5 - logical BAR3
1098 ** Skip the appropriate assignments:
1099 */
1100 if ((bar == 1) || (bar == 3))
1101 continue;
1102 if (pm8001_ha->io_mem[logical].memvirtaddr) {
1103 iounmap(pm8001_ha->io_mem[logical].memvirtaddr);
1104 logical++;
1105 }
1106 }
1107}
1108
1109/**
1110 * pm8001_chip_interrupt_enable - enable PM8001 chip interrupt
1111 * @pm8001_ha: our hba card information
1112 */
1113static void
1114pm8001_chip_intx_interrupt_enable(struct pm8001_hba_info *pm8001_ha)
1115{
1116 pm8001_cw32(pm8001_ha, 0, MSGU_ODMR, ODMR_CLEAR_ALL);
1117 pm8001_cw32(pm8001_ha, 0, MSGU_ODCR, ODCR_CLEAR_ALL);
1118}
1119
1120 /**
1121 * pm8001_chip_intx_interrupt_disable- disable PM8001 chip interrupt
1122 * @pm8001_ha: our hba card information
1123 */
1124static void
1125pm8001_chip_intx_interrupt_disable(struct pm8001_hba_info *pm8001_ha)
1126{
1127 pm8001_cw32(pm8001_ha, 0, MSGU_ODMR, ODMR_MASK_ALL);
1128}
1129
1130/**
1131 * pm8001_chip_msix_interrupt_enable - enable PM8001 chip interrupt
1132 * @pm8001_ha: our hba card information
1133 */
1134static void
1135pm8001_chip_msix_interrupt_enable(struct pm8001_hba_info *pm8001_ha,
1136 u32 int_vec_idx)
1137{
1138 u32 msi_index;
1139 u32 value;
1140 msi_index = int_vec_idx * MSIX_TABLE_ELEMENT_SIZE;
1141 msi_index += MSIX_TABLE_BASE;
1142 pm8001_cw32(pm8001_ha, 0, msi_index, MSIX_INTERRUPT_ENABLE);
1143 value = (1 << int_vec_idx);
1144 pm8001_cw32(pm8001_ha, 0, MSGU_ODCR, value);
1145
1146}
1147
1148/**
1149 * pm8001_chip_msix_interrupt_disable - disable PM8001 chip interrupt
1150 * @pm8001_ha: our hba card information
1151 */
1152static void
1153pm8001_chip_msix_interrupt_disable(struct pm8001_hba_info *pm8001_ha,
1154 u32 int_vec_idx)
1155{
1156 u32 msi_index;
1157 msi_index = int_vec_idx * MSIX_TABLE_ELEMENT_SIZE;
1158 msi_index += MSIX_TABLE_BASE;
1159 pm8001_cw32(pm8001_ha, 0, msi_index, MSIX_INTERRUPT_DISABLE);
1160
1161}
1162/**
1163 * pm8001_chip_interrupt_enable - enable PM8001 chip interrupt
1164 * @pm8001_ha: our hba card information
1165 */
1166static void
1167pm8001_chip_interrupt_enable(struct pm8001_hba_info *pm8001_ha)
1168{
1169#ifdef PM8001_USE_MSIX
1170 pm8001_chip_msix_interrupt_enable(pm8001_ha, 0);
1171 return;
1172#endif
1173 pm8001_chip_intx_interrupt_enable(pm8001_ha);
1174
1175}
1176
1177/**
1178 * pm8001_chip_intx_interrupt_disable- disable PM8001 chip interrupt
1179 * @pm8001_ha: our hba card information
1180 */
1181static void
1182pm8001_chip_interrupt_disable(struct pm8001_hba_info *pm8001_ha)
1183{
1184#ifdef PM8001_USE_MSIX
1185 pm8001_chip_msix_interrupt_disable(pm8001_ha, 0);
1186 return;
1187#endif
1188 pm8001_chip_intx_interrupt_disable(pm8001_ha);
1189
1190}
1191
1192/**
1193 * mpi_msg_free_get- get the free message buffer for transfer inbound queue.
1194 * @circularQ: the inbound queue we want to transfer to HBA.
1195 * @messageSize: the message size of this transfer, normally it is 64 bytes
1196 * @messagePtr: the pointer to message.
1197 */
1198static int mpi_msg_free_get(struct inbound_queue_table *circularQ,
1199 u16 messageSize, void **messagePtr)
1200{
1201 u32 offset, consumer_index;
1202 struct mpi_msg_hdr *msgHeader;
1203 u8 bcCount = 1; /* only support single buffer */
1204
1205 /* Checks is the requested message size can be allocated in this queue*/
1206 if (messageSize > 64) {
1207 *messagePtr = NULL;
1208 return -1;
1209 }
1210
1211 /* Stores the new consumer index */
1212 consumer_index = pm8001_read_32(circularQ->ci_virt);
1213 circularQ->consumer_index = cpu_to_le32(consumer_index);
1214 if (((circularQ->producer_idx + bcCount) % 256) ==
1215 circularQ->consumer_index) {
1216 *messagePtr = NULL;
1217 return -1;
1218 }
1219 /* get memory IOMB buffer address */
1220 offset = circularQ->producer_idx * 64;
1221 /* increment to next bcCount element */
1222 circularQ->producer_idx = (circularQ->producer_idx + bcCount) % 256;
1223 /* Adds that distance to the base of the region virtual address plus
1224 the message header size*/
1225 msgHeader = (struct mpi_msg_hdr *)(circularQ->base_virt + offset);
1226 *messagePtr = ((void *)msgHeader) + sizeof(struct mpi_msg_hdr);
1227 return 0;
1228}
1229
1230/**
1231 * mpi_build_cmd- build the message queue for transfer, update the PI to FW
1232 * to tell the fw to get this message from IOMB.
1233 * @pm8001_ha: our hba card information
1234 * @circularQ: the inbound queue we want to transfer to HBA.
1235 * @opCode: the operation code represents commands which LLDD and fw recognized.
1236 * @payload: the command payload of each operation command.
1237 */
1238static int mpi_build_cmd(struct pm8001_hba_info *pm8001_ha,
1239 struct inbound_queue_table *circularQ,
1240 u32 opCode, void *payload)
1241{
1242 u32 Header = 0, hpriority = 0, bc = 1, category = 0x02;
1243 u32 responseQueue = 0;
1244 void *pMessage;
1245
1246 if (mpi_msg_free_get(circularQ, 64, &pMessage) < 0) {
1247 PM8001_IO_DBG(pm8001_ha,
1248 pm8001_printk("No free mpi buffer \n"));
1249 return -1;
1250 }
1251 BUG_ON(!payload);
1252 /*Copy to the payload*/
1253 memcpy(pMessage, payload, (64 - sizeof(struct mpi_msg_hdr)));
1254
1255 /*Build the header*/
1256 Header = ((1 << 31) | (hpriority << 30) | ((bc & 0x1f) << 24)
1257 | ((responseQueue & 0x3F) << 16)
1258 | ((category & 0xF) << 12) | (opCode & 0xFFF));
1259
1260 pm8001_write_32((pMessage - 4), 0, cpu_to_le32(Header));
1261 /*Update the PI to the firmware*/
1262 pm8001_cw32(pm8001_ha, circularQ->pi_pci_bar,
1263 circularQ->pi_offset, circularQ->producer_idx);
1264 PM8001_IO_DBG(pm8001_ha,
1265 pm8001_printk("after PI= %d CI= %d \n", circularQ->producer_idx,
1266 circularQ->consumer_index));
1267 return 0;
1268}
1269
1270static u32 mpi_msg_free_set(struct pm8001_hba_info *pm8001_ha, void *pMsg,
1271 struct outbound_queue_table *circularQ, u8 bc)
1272{
1273 u32 producer_index;
1274 struct mpi_msg_hdr *msgHeader;
1275 struct mpi_msg_hdr *pOutBoundMsgHeader;
1276
1277 msgHeader = (struct mpi_msg_hdr *)(pMsg - sizeof(struct mpi_msg_hdr));
1278 pOutBoundMsgHeader = (struct mpi_msg_hdr *)(circularQ->base_virt +
1279 circularQ->consumer_idx * 64);
1280 if (pOutBoundMsgHeader != msgHeader) {
1281 PM8001_FAIL_DBG(pm8001_ha,
1282 pm8001_printk("consumer_idx = %d msgHeader = %p\n",
1283 circularQ->consumer_idx, msgHeader));
1284
1285 /* Update the producer index from SPC */
1286 producer_index = pm8001_read_32(circularQ->pi_virt);
1287 circularQ->producer_index = cpu_to_le32(producer_index);
1288 PM8001_FAIL_DBG(pm8001_ha,
1289 pm8001_printk("consumer_idx = %d producer_index = %d"
1290 "msgHeader = %p\n", circularQ->consumer_idx,
1291 circularQ->producer_index, msgHeader));
1292 return 0;
1293 }
1294 /* free the circular queue buffer elements associated with the message*/
1295 circularQ->consumer_idx = (circularQ->consumer_idx + bc) % 256;
1296 /* update the CI of outbound queue */
1297 pm8001_cw32(pm8001_ha, circularQ->ci_pci_bar, circularQ->ci_offset,
1298 circularQ->consumer_idx);
1299 /* Update the producer index from SPC*/
1300 producer_index = pm8001_read_32(circularQ->pi_virt);
1301 circularQ->producer_index = cpu_to_le32(producer_index);
1302 PM8001_IO_DBG(pm8001_ha,
1303 pm8001_printk(" CI=%d PI=%d\n", circularQ->consumer_idx,
1304 circularQ->producer_index));
1305 return 0;
1306}
1307
1308/**
1309 * mpi_msg_consume- get the MPI message from outbound queue message table.
1310 * @pm8001_ha: our hba card information
1311 * @circularQ: the outbound queue table.
1312 * @messagePtr1: the message contents of this outbound message.
1313 * @pBC: the message size.
1314 */
1315static u32 mpi_msg_consume(struct pm8001_hba_info *pm8001_ha,
1316 struct outbound_queue_table *circularQ,
1317 void **messagePtr1, u8 *pBC)
1318{
1319 struct mpi_msg_hdr *msgHeader;
1320 __le32 msgHeader_tmp;
1321 u32 header_tmp;
1322 do {
1323 /* If there are not-yet-delivered messages ... */
1324 if (circularQ->producer_index != circularQ->consumer_idx) {
1325 /*Get the pointer to the circular queue buffer element*/
1326 msgHeader = (struct mpi_msg_hdr *)
1327 (circularQ->base_virt +
1328 circularQ->consumer_idx * 64);
1329 /* read header */
1330 header_tmp = pm8001_read_32(msgHeader);
1331 msgHeader_tmp = cpu_to_le32(header_tmp);
1332 if (0 != (msgHeader_tmp & 0x80000000)) {
1333 if (OPC_OUB_SKIP_ENTRY !=
1334 (msgHeader_tmp & 0xfff)) {
1335 *messagePtr1 =
1336 ((u8 *)msgHeader) +
1337 sizeof(struct mpi_msg_hdr);
1338 *pBC = (u8)((msgHeader_tmp >> 24) &
1339 0x1f);
1340 PM8001_IO_DBG(pm8001_ha,
1341 pm8001_printk(": CI=%d PI=%d "
1342 "msgHeader=%x\n",
1343 circularQ->consumer_idx,
1344 circularQ->producer_index,
1345 msgHeader_tmp));
1346 return MPI_IO_STATUS_SUCCESS;
1347 } else {
1348 circularQ->consumer_idx =
1349 (circularQ->consumer_idx +
1350 ((msgHeader_tmp >> 24) & 0x1f))
1351 % 256;
1352 msgHeader_tmp = 0;
1353 pm8001_write_32(msgHeader, 0, 0);
1354 /* update the CI of outbound queue */
1355 pm8001_cw32(pm8001_ha,
1356 circularQ->ci_pci_bar,
1357 circularQ->ci_offset,
1358 circularQ->consumer_idx);
1359 }
1360 } else {
1361 circularQ->consumer_idx =
1362 (circularQ->consumer_idx +
1363 ((msgHeader_tmp >> 24) & 0x1f)) % 256;
1364 msgHeader_tmp = 0;
1365 pm8001_write_32(msgHeader, 0, 0);
1366 /* update the CI of outbound queue */
1367 pm8001_cw32(pm8001_ha, circularQ->ci_pci_bar,
1368 circularQ->ci_offset,
1369 circularQ->consumer_idx);
1370 return MPI_IO_STATUS_FAIL;
1371 }
1372 } else {
1373 u32 producer_index;
1374 void *pi_virt = circularQ->pi_virt;
1375 /* Update the producer index from SPC */
1376 producer_index = pm8001_read_32(pi_virt);
1377 circularQ->producer_index = cpu_to_le32(producer_index);
1378 }
1379 } while (circularQ->producer_index != circularQ->consumer_idx);
1380 /* while we don't have any more not-yet-delivered message */
1381 /* report empty */
1382 return MPI_IO_STATUS_BUSY;
1383}
1384
1385static void pm8001_work_queue(struct work_struct *work)
1386{
1387 struct delayed_work *dw = container_of(work, struct delayed_work, work);
1388 struct pm8001_wq *wq = container_of(dw, struct pm8001_wq, work_q);
1389 struct pm8001_device *pm8001_dev;
1390 struct domain_device *dev;
1391
1392 switch (wq->handler) {
1393 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS:
1394 pm8001_dev = wq->data;
1395 dev = pm8001_dev->sas_device;
1396 pm8001_I_T_nexus_reset(dev);
1397 break;
1398 case IO_OPEN_CNX_ERROR_STP_RESOURCES_BUSY:
1399 pm8001_dev = wq->data;
1400 dev = pm8001_dev->sas_device;
1401 pm8001_I_T_nexus_reset(dev);
1402 break;
1403 case IO_DS_IN_ERROR:
1404 pm8001_dev = wq->data;
1405 dev = pm8001_dev->sas_device;
1406 pm8001_I_T_nexus_reset(dev);
1407 break;
1408 case IO_DS_NON_OPERATIONAL:
1409 pm8001_dev = wq->data;
1410 dev = pm8001_dev->sas_device;
1411 pm8001_I_T_nexus_reset(dev);
1412 break;
1413 }
1414 list_del(&wq->entry);
1415 kfree(wq);
1416}
1417
1418static int pm8001_handle_event(struct pm8001_hba_info *pm8001_ha, void *data,
1419 int handler)
1420{
1421 struct pm8001_wq *wq;
1422 int ret = 0;
1423
1424 wq = kmalloc(sizeof(struct pm8001_wq), GFP_ATOMIC);
1425 if (wq) {
1426 wq->pm8001_ha = pm8001_ha;
1427 wq->data = data;
1428 wq->handler = handler;
1429 INIT_DELAYED_WORK(&wq->work_q, pm8001_work_queue);
1430 list_add_tail(&wq->entry, &pm8001_ha->wq_list);
1431 schedule_delayed_work(&wq->work_q, 0);
1432 } else
1433 ret = -ENOMEM;
1434
1435 return ret;
1436}
1437
1438/**
1439 * mpi_ssp_completion- process the event that FW response to the SSP request.
1440 * @pm8001_ha: our hba card information
1441 * @piomb: the message contents of this outbound message.
1442 *
1443 * When FW has completed a ssp request for example a IO request, after it has
1444 * filled the SG data with the data, it will trigger this event represent
1445 * that he has finished the job,please check the coresponding buffer.
1446 * So we will tell the caller who maybe waiting the result to tell upper layer
1447 * that the task has been finished.
1448 */
1449static void
1450mpi_ssp_completion(struct pm8001_hba_info *pm8001_ha , void *piomb)
1451{
1452 struct sas_task *t;
1453 struct pm8001_ccb_info *ccb;
1454 unsigned long flags;
1455 u32 status;
1456 u32 param;
1457 u32 tag;
1458 struct ssp_completion_resp *psspPayload;
1459 struct task_status_struct *ts;
1460 struct ssp_response_iu *iu;
1461 struct pm8001_device *pm8001_dev;
1462 psspPayload = (struct ssp_completion_resp *)(piomb + 4);
1463 status = le32_to_cpu(psspPayload->status);
1464 tag = le32_to_cpu(psspPayload->tag);
1465 ccb = &pm8001_ha->ccb_info[tag];
1466 pm8001_dev = ccb->device;
1467 param = le32_to_cpu(psspPayload->param);
1468
1469 t = ccb->task;
1470
1471 if (status && status != IO_UNDERFLOW)
1472 PM8001_FAIL_DBG(pm8001_ha,
1473 pm8001_printk("sas IO status 0x%x\n", status));
1474 if (unlikely(!t || !t->lldd_task || !t->dev))
1475 return;
1476 ts = &t->task_status;
1477 switch (status) {
1478 case IO_SUCCESS:
1479 PM8001_IO_DBG(pm8001_ha, pm8001_printk("IO_SUCCESS"
1480 ",param = %d \n", param));
1481 if (param == 0) {
1482 ts->resp = SAS_TASK_COMPLETE;
1483 ts->stat = SAM_GOOD;
1484 } else {
1485 ts->resp = SAS_TASK_COMPLETE;
1486 ts->stat = SAS_PROTO_RESPONSE;
1487 ts->residual = param;
1488 iu = &psspPayload->ssp_resp_iu;
1489 sas_ssp_task_response(pm8001_ha->dev, t, iu);
1490 }
1491 if (pm8001_dev)
1492 pm8001_dev->running_req--;
1493 break;
1494 case IO_ABORTED:
1495 PM8001_IO_DBG(pm8001_ha,
1496 pm8001_printk("IO_ABORTED IOMB Tag \n"));
1497 ts->resp = SAS_TASK_COMPLETE;
1498 ts->stat = SAS_ABORTED_TASK;
1499 break;
1500 case IO_UNDERFLOW:
1501 /* SSP Completion with error */
1502 PM8001_IO_DBG(pm8001_ha, pm8001_printk("IO_UNDERFLOW"
1503 ",param = %d \n", param));
1504 ts->resp = SAS_TASK_COMPLETE;
1505 ts->stat = SAS_DATA_UNDERRUN;
1506 ts->residual = param;
1507 if (pm8001_dev)
1508 pm8001_dev->running_req--;
1509 break;
1510 case IO_NO_DEVICE:
1511 PM8001_IO_DBG(pm8001_ha,
1512 pm8001_printk("IO_NO_DEVICE\n"));
1513 ts->resp = SAS_TASK_UNDELIVERED;
1514 ts->stat = SAS_PHY_DOWN;
1515 break;
1516 case IO_XFER_ERROR_BREAK:
1517 PM8001_IO_DBG(pm8001_ha,
1518 pm8001_printk("IO_XFER_ERROR_BREAK\n"));
1519 ts->resp = SAS_TASK_COMPLETE;
1520 ts->stat = SAS_OPEN_REJECT;
1521 break;
1522 case IO_XFER_ERROR_PHY_NOT_READY:
1523 PM8001_IO_DBG(pm8001_ha,
1524 pm8001_printk("IO_XFER_ERROR_PHY_NOT_READY\n"));
1525 ts->resp = SAS_TASK_COMPLETE;
1526 ts->stat = SAS_OPEN_REJECT;
1527 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
1528 break;
1529 case IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED:
1530 PM8001_IO_DBG(pm8001_ha,
1531 pm8001_printk("IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED\n"));
1532 ts->resp = SAS_TASK_COMPLETE;
1533 ts->stat = SAS_OPEN_REJECT;
1534 ts->open_rej_reason = SAS_OREJ_EPROTO;
1535 break;
1536 case IO_OPEN_CNX_ERROR_ZONE_VIOLATION:
1537 PM8001_IO_DBG(pm8001_ha,
1538 pm8001_printk("IO_OPEN_CNX_ERROR_ZONE_VIOLATION\n"));
1539 ts->resp = SAS_TASK_COMPLETE;
1540 ts->stat = SAS_OPEN_REJECT;
1541 ts->open_rej_reason = SAS_OREJ_UNKNOWN;
1542 break;
1543 case IO_OPEN_CNX_ERROR_BREAK:
1544 PM8001_IO_DBG(pm8001_ha,
1545 pm8001_printk("IO_OPEN_CNX_ERROR_BREAK\n"));
1546 ts->resp = SAS_TASK_COMPLETE;
1547 ts->stat = SAS_OPEN_REJECT;
1548 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
1549 break;
1550 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS:
1551 PM8001_IO_DBG(pm8001_ha,
1552 pm8001_printk("IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS\n"));
1553 ts->resp = SAS_TASK_COMPLETE;
1554 ts->stat = SAS_OPEN_REJECT;
1555 ts->open_rej_reason = SAS_OREJ_UNKNOWN;
1556 if (!t->uldd_task)
1557 pm8001_handle_event(pm8001_ha,
1558 pm8001_dev,
1559 IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS);
1560 break;
1561 case IO_OPEN_CNX_ERROR_BAD_DESTINATION:
1562 PM8001_IO_DBG(pm8001_ha,
1563 pm8001_printk("IO_OPEN_CNX_ERROR_BAD_DESTINATION\n"));
1564 ts->resp = SAS_TASK_COMPLETE;
1565 ts->stat = SAS_OPEN_REJECT;
1566 ts->open_rej_reason = SAS_OREJ_BAD_DEST;
1567 break;
1568 case IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED:
1569 PM8001_IO_DBG(pm8001_ha,
1570 pm8001_printk("IO_OPEN_CNX_ERROR_CONNECTION_RATE_"
1571 "NOT_SUPPORTED\n"));
1572 ts->resp = SAS_TASK_COMPLETE;
1573 ts->stat = SAS_OPEN_REJECT;
1574 ts->open_rej_reason = SAS_OREJ_CONN_RATE;
1575 break;
1576 case IO_OPEN_CNX_ERROR_WRONG_DESTINATION:
1577 PM8001_IO_DBG(pm8001_ha,
1578 pm8001_printk("IO_OPEN_CNX_ERROR_WRONG_DESTINATION\n"));
1579 ts->resp = SAS_TASK_UNDELIVERED;
1580 ts->stat = SAS_OPEN_REJECT;
1581 ts->open_rej_reason = SAS_OREJ_WRONG_DEST;
1582 break;
1583 case IO_XFER_ERROR_NAK_RECEIVED:
1584 PM8001_IO_DBG(pm8001_ha,
1585 pm8001_printk("IO_XFER_ERROR_NAK_RECEIVED\n"));
1586 ts->resp = SAS_TASK_COMPLETE;
1587 ts->stat = SAS_OPEN_REJECT;
1588 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
1589 break;
1590 case IO_XFER_ERROR_ACK_NAK_TIMEOUT:
1591 PM8001_IO_DBG(pm8001_ha,
1592 pm8001_printk("IO_XFER_ERROR_ACK_NAK_TIMEOUT\n"));
1593 ts->resp = SAS_TASK_COMPLETE;
1594 ts->stat = SAS_NAK_R_ERR;
1595 break;
1596 case IO_XFER_ERROR_DMA:
1597 PM8001_IO_DBG(pm8001_ha,
1598 pm8001_printk("IO_XFER_ERROR_DMA\n"));
1599 ts->resp = SAS_TASK_COMPLETE;
1600 ts->stat = SAS_OPEN_REJECT;
1601 break;
1602 case IO_XFER_OPEN_RETRY_TIMEOUT:
1603 PM8001_IO_DBG(pm8001_ha,
1604 pm8001_printk("IO_XFER_OPEN_RETRY_TIMEOUT\n"));
1605 ts->resp = SAS_TASK_COMPLETE;
1606 ts->stat = SAS_OPEN_REJECT;
1607 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
1608 break;
1609 case IO_XFER_ERROR_OFFSET_MISMATCH:
1610 PM8001_IO_DBG(pm8001_ha,
1611 pm8001_printk("IO_XFER_ERROR_OFFSET_MISMATCH\n"));
1612 ts->resp = SAS_TASK_COMPLETE;
1613 ts->stat = SAS_OPEN_REJECT;
1614 break;
1615 case IO_PORT_IN_RESET:
1616 PM8001_IO_DBG(pm8001_ha,
1617 pm8001_printk("IO_PORT_IN_RESET\n"));
1618 ts->resp = SAS_TASK_COMPLETE;
1619 ts->stat = SAS_OPEN_REJECT;
1620 break;
1621 case IO_DS_NON_OPERATIONAL:
1622 PM8001_IO_DBG(pm8001_ha,
1623 pm8001_printk("IO_DS_NON_OPERATIONAL\n"));
1624 ts->resp = SAS_TASK_COMPLETE;
1625 ts->stat = SAS_OPEN_REJECT;
1626 if (!t->uldd_task)
1627 pm8001_handle_event(pm8001_ha,
1628 pm8001_dev,
1629 IO_DS_NON_OPERATIONAL);
1630 break;
1631 case IO_DS_IN_RECOVERY:
1632 PM8001_IO_DBG(pm8001_ha,
1633 pm8001_printk("IO_DS_IN_RECOVERY\n"));
1634 ts->resp = SAS_TASK_COMPLETE;
1635 ts->stat = SAS_OPEN_REJECT;
1636 break;
1637 case IO_TM_TAG_NOT_FOUND:
1638 PM8001_IO_DBG(pm8001_ha,
1639 pm8001_printk("IO_TM_TAG_NOT_FOUND\n"));
1640 ts->resp = SAS_TASK_COMPLETE;
1641 ts->stat = SAS_OPEN_REJECT;
1642 break;
1643 case IO_SSP_EXT_IU_ZERO_LEN_ERROR:
1644 PM8001_IO_DBG(pm8001_ha,
1645 pm8001_printk("IO_SSP_EXT_IU_ZERO_LEN_ERROR\n"));
1646 ts->resp = SAS_TASK_COMPLETE;
1647 ts->stat = SAS_OPEN_REJECT;
1648 break;
1649 case IO_OPEN_CNX_ERROR_HW_RESOURCE_BUSY:
1650 PM8001_IO_DBG(pm8001_ha,
1651 pm8001_printk("IO_OPEN_CNX_ERROR_HW_RESOURCE_BUSY\n"));
1652 ts->resp = SAS_TASK_COMPLETE;
1653 ts->stat = SAS_OPEN_REJECT;
1654 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
1655 default:
1656 PM8001_IO_DBG(pm8001_ha,
1657 pm8001_printk("Unknown status 0x%x\n", status));
1658 /* not allowed case. Therefore, return failed status */
1659 ts->resp = SAS_TASK_COMPLETE;
1660 ts->stat = SAS_OPEN_REJECT;
1661 break;
1662 }
1663 PM8001_IO_DBG(pm8001_ha,
1664 pm8001_printk("scsi_status = %x \n ",
1665 psspPayload->ssp_resp_iu.status));
1666 spin_lock_irqsave(&t->task_state_lock, flags);
1667 t->task_state_flags &= ~SAS_TASK_STATE_PENDING;
1668 t->task_state_flags &= ~SAS_TASK_AT_INITIATOR;
1669 t->task_state_flags |= SAS_TASK_STATE_DONE;
1670 if (unlikely((t->task_state_flags & SAS_TASK_STATE_ABORTED))) {
1671 spin_unlock_irqrestore(&t->task_state_lock, flags);
1672 PM8001_FAIL_DBG(pm8001_ha, pm8001_printk("task 0x%p done with"
1673 " io_status 0x%x resp 0x%x "
1674 "stat 0x%x but aborted by upper layer!\n",
1675 t, status, ts->resp, ts->stat));
1676 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
1677 } else {
1678 spin_unlock_irqrestore(&t->task_state_lock, flags);
1679 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
1680 mb();/* in order to force CPU ordering */
1681 t->task_done(t);
1682 }
1683}
1684
1685/*See the comments for mpi_ssp_completion */
1686static void mpi_ssp_event(struct pm8001_hba_info *pm8001_ha , void *piomb)
1687{
1688 struct sas_task *t;
1689 unsigned long flags;
1690 struct task_status_struct *ts;
1691 struct pm8001_ccb_info *ccb;
1692 struct pm8001_device *pm8001_dev;
1693 struct ssp_event_resp *psspPayload =
1694 (struct ssp_event_resp *)(piomb + 4);
1695 u32 event = le32_to_cpu(psspPayload->event);
1696 u32 tag = le32_to_cpu(psspPayload->tag);
1697 u32 port_id = le32_to_cpu(psspPayload->port_id);
1698 u32 dev_id = le32_to_cpu(psspPayload->device_id);
1699
1700 ccb = &pm8001_ha->ccb_info[tag];
1701 t = ccb->task;
1702 pm8001_dev = ccb->device;
1703 if (event)
1704 PM8001_FAIL_DBG(pm8001_ha,
1705 pm8001_printk("sas IO status 0x%x\n", event));
1706 if (unlikely(!t || !t->lldd_task || !t->dev))
1707 return;
1708 ts = &t->task_status;
1709 PM8001_IO_DBG(pm8001_ha,
1710 pm8001_printk("port_id = %x,device_id = %x\n",
1711 port_id, dev_id));
1712 switch (event) {
1713 case IO_OVERFLOW:
1714 PM8001_IO_DBG(pm8001_ha, pm8001_printk("IO_UNDERFLOW\n");)
1715 ts->resp = SAS_TASK_COMPLETE;
1716 ts->stat = SAS_DATA_OVERRUN;
1717 ts->residual = 0;
1718 if (pm8001_dev)
1719 pm8001_dev->running_req--;
1720 break;
1721 case IO_XFER_ERROR_BREAK:
1722 PM8001_IO_DBG(pm8001_ha,
1723 pm8001_printk("IO_XFER_ERROR_BREAK\n"));
1724 ts->resp = SAS_TASK_COMPLETE;
1725 ts->stat = SAS_INTERRUPTED;
1726 break;
1727 case IO_XFER_ERROR_PHY_NOT_READY:
1728 PM8001_IO_DBG(pm8001_ha,
1729 pm8001_printk("IO_XFER_ERROR_PHY_NOT_READY\n"));
1730 ts->resp = SAS_TASK_COMPLETE;
1731 ts->stat = SAS_OPEN_REJECT;
1732 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
1733 break;
1734 case IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED:
1735 PM8001_IO_DBG(pm8001_ha,
1736 pm8001_printk("IO_OPEN_CNX_ERROR_PROTOCOL_NOT"
1737 "_SUPPORTED\n"));
1738 ts->resp = SAS_TASK_COMPLETE;
1739 ts->stat = SAS_OPEN_REJECT;
1740 ts->open_rej_reason = SAS_OREJ_EPROTO;
1741 break;
1742 case IO_OPEN_CNX_ERROR_ZONE_VIOLATION:
1743 PM8001_IO_DBG(pm8001_ha,
1744 pm8001_printk("IO_OPEN_CNX_ERROR_ZONE_VIOLATION\n"));
1745 ts->resp = SAS_TASK_COMPLETE;
1746 ts->stat = SAS_OPEN_REJECT;
1747 ts->open_rej_reason = SAS_OREJ_UNKNOWN;
1748 break;
1749 case IO_OPEN_CNX_ERROR_BREAK:
1750 PM8001_IO_DBG(pm8001_ha,
1751 pm8001_printk("IO_OPEN_CNX_ERROR_BREAK\n"));
1752 ts->resp = SAS_TASK_COMPLETE;
1753 ts->stat = SAS_OPEN_REJECT;
1754 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
1755 break;
1756 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS:
1757 PM8001_IO_DBG(pm8001_ha,
1758 pm8001_printk("IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS\n"));
1759 ts->resp = SAS_TASK_COMPLETE;
1760 ts->stat = SAS_OPEN_REJECT;
1761 ts->open_rej_reason = SAS_OREJ_UNKNOWN;
1762 if (!t->uldd_task)
1763 pm8001_handle_event(pm8001_ha,
1764 pm8001_dev,
1765 IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS);
1766 break;
1767 case IO_OPEN_CNX_ERROR_BAD_DESTINATION:
1768 PM8001_IO_DBG(pm8001_ha,
1769 pm8001_printk("IO_OPEN_CNX_ERROR_BAD_DESTINATION\n"));
1770 ts->resp = SAS_TASK_COMPLETE;
1771 ts->stat = SAS_OPEN_REJECT;
1772 ts->open_rej_reason = SAS_OREJ_BAD_DEST;
1773 break;
1774 case IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED:
1775 PM8001_IO_DBG(pm8001_ha,
1776 pm8001_printk("IO_OPEN_CNX_ERROR_CONNECTION_RATE_"
1777 "NOT_SUPPORTED\n"));
1778 ts->resp = SAS_TASK_COMPLETE;
1779 ts->stat = SAS_OPEN_REJECT;
1780 ts->open_rej_reason = SAS_OREJ_CONN_RATE;
1781 break;
1782 case IO_OPEN_CNX_ERROR_WRONG_DESTINATION:
1783 PM8001_IO_DBG(pm8001_ha,
1784 pm8001_printk("IO_OPEN_CNX_ERROR_WRONG_DESTINATION\n"));
1785 ts->resp = SAS_TASK_COMPLETE;
1786 ts->stat = SAS_OPEN_REJECT;
1787 ts->open_rej_reason = SAS_OREJ_WRONG_DEST;
1788 break;
1789 case IO_XFER_ERROR_NAK_RECEIVED:
1790 PM8001_IO_DBG(pm8001_ha,
1791 pm8001_printk("IO_XFER_ERROR_NAK_RECEIVED\n"));
1792 ts->resp = SAS_TASK_COMPLETE;
1793 ts->stat = SAS_OPEN_REJECT;
1794 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
1795 break;
1796 case IO_XFER_ERROR_ACK_NAK_TIMEOUT:
1797 PM8001_IO_DBG(pm8001_ha,
1798 pm8001_printk("IO_XFER_ERROR_ACK_NAK_TIMEOUT\n"));
1799 ts->resp = SAS_TASK_COMPLETE;
1800 ts->stat = SAS_NAK_R_ERR;
1801 break;
1802 case IO_XFER_OPEN_RETRY_TIMEOUT:
1803 PM8001_IO_DBG(pm8001_ha,
1804 pm8001_printk("IO_XFER_OPEN_RETRY_TIMEOUT\n"));
1805 ts->resp = SAS_TASK_COMPLETE;
1806 ts->stat = SAS_OPEN_REJECT;
1807 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
1808 break;
1809 case IO_XFER_ERROR_UNEXPECTED_PHASE:
1810 PM8001_IO_DBG(pm8001_ha,
1811 pm8001_printk("IO_XFER_ERROR_UNEXPECTED_PHASE\n"));
1812 ts->resp = SAS_TASK_COMPLETE;
1813 ts->stat = SAS_DATA_OVERRUN;
1814 break;
1815 case IO_XFER_ERROR_XFER_RDY_OVERRUN:
1816 PM8001_IO_DBG(pm8001_ha,
1817 pm8001_printk("IO_XFER_ERROR_XFER_RDY_OVERRUN\n"));
1818 ts->resp = SAS_TASK_COMPLETE;
1819 ts->stat = SAS_DATA_OVERRUN;
1820 break;
1821 case IO_XFER_ERROR_XFER_RDY_NOT_EXPECTED:
1822 PM8001_IO_DBG(pm8001_ha,
1823 pm8001_printk("IO_XFER_ERROR_XFER_RDY_NOT_EXPECTED\n"));
1824 ts->resp = SAS_TASK_COMPLETE;
1825 ts->stat = SAS_DATA_OVERRUN;
1826 break;
1827 case IO_XFER_ERROR_CMD_ISSUE_ACK_NAK_TIMEOUT:
1828 PM8001_IO_DBG(pm8001_ha,
1829 pm8001_printk("IO_XFER_ERROR_CMD_ISSUE_ACK_NAK_TIMEOUT\n"));
1830 ts->resp = SAS_TASK_COMPLETE;
1831 ts->stat = SAS_DATA_OVERRUN;
1832 break;
1833 case IO_XFER_ERROR_OFFSET_MISMATCH:
1834 PM8001_IO_DBG(pm8001_ha,
1835 pm8001_printk("IO_XFER_ERROR_OFFSET_MISMATCH\n"));
1836 ts->resp = SAS_TASK_COMPLETE;
1837 ts->stat = SAS_DATA_OVERRUN;
1838 break;
1839 case IO_XFER_ERROR_XFER_ZERO_DATA_LEN:
1840 PM8001_IO_DBG(pm8001_ha,
1841 pm8001_printk("IO_XFER_ERROR_XFER_ZERO_DATA_LEN\n"));
1842 ts->resp = SAS_TASK_COMPLETE;
1843 ts->stat = SAS_DATA_OVERRUN;
1844 break;
1845 case IO_XFER_CMD_FRAME_ISSUED:
1846 PM8001_IO_DBG(pm8001_ha,
1847 pm8001_printk(" IO_XFER_CMD_FRAME_ISSUED\n"));
1848 return;
1849 default:
1850 PM8001_IO_DBG(pm8001_ha,
1851 pm8001_printk("Unknown status 0x%x\n", event));
1852 /* not allowed case. Therefore, return failed status */
1853 ts->resp = SAS_TASK_COMPLETE;
1854 ts->stat = SAS_DATA_OVERRUN;
1855 break;
1856 }
1857 spin_lock_irqsave(&t->task_state_lock, flags);
1858 t->task_state_flags &= ~SAS_TASK_STATE_PENDING;
1859 t->task_state_flags &= ~SAS_TASK_AT_INITIATOR;
1860 t->task_state_flags |= SAS_TASK_STATE_DONE;
1861 if (unlikely((t->task_state_flags & SAS_TASK_STATE_ABORTED))) {
1862 spin_unlock_irqrestore(&t->task_state_lock, flags);
1863 PM8001_FAIL_DBG(pm8001_ha, pm8001_printk("task 0x%p done with"
1864 " event 0x%x resp 0x%x "
1865 "stat 0x%x but aborted by upper layer!\n",
1866 t, event, ts->resp, ts->stat));
1867 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
1868 } else {
1869 spin_unlock_irqrestore(&t->task_state_lock, flags);
1870 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
1871 mb();/* in order to force CPU ordering */
1872 t->task_done(t);
1873 }
1874}
1875
1876/*See the comments for mpi_ssp_completion */
1877static void
1878mpi_sata_completion(struct pm8001_hba_info *pm8001_ha, void *piomb)
1879{
1880 struct sas_task *t;
1881 struct pm8001_ccb_info *ccb;
1882 unsigned long flags = 0;
1883 u32 param;
1884 u32 status;
1885 u32 tag;
1886 struct sata_completion_resp *psataPayload;
1887 struct task_status_struct *ts;
1888 struct ata_task_resp *resp ;
1889 u32 *sata_resp;
1890 struct pm8001_device *pm8001_dev;
1891
1892 psataPayload = (struct sata_completion_resp *)(piomb + 4);
1893 status = le32_to_cpu(psataPayload->status);
1894 tag = le32_to_cpu(psataPayload->tag);
1895
1896 ccb = &pm8001_ha->ccb_info[tag];
1897 param = le32_to_cpu(psataPayload->param);
1898 t = ccb->task;
1899 ts = &t->task_status;
1900 pm8001_dev = ccb->device;
1901 if (status)
1902 PM8001_FAIL_DBG(pm8001_ha,
1903 pm8001_printk("sata IO status 0x%x\n", status));
1904 if (unlikely(!t || !t->lldd_task || !t->dev))
1905 return;
1906
1907 switch (status) {
1908 case IO_SUCCESS:
1909 PM8001_IO_DBG(pm8001_ha, pm8001_printk("IO_SUCCESS\n"));
1910 if (param == 0) {
1911 ts->resp = SAS_TASK_COMPLETE;
1912 ts->stat = SAM_GOOD;
1913 } else {
1914 u8 len;
1915 ts->resp = SAS_TASK_COMPLETE;
1916 ts->stat = SAS_PROTO_RESPONSE;
1917 ts->residual = param;
1918 PM8001_IO_DBG(pm8001_ha,
1919 pm8001_printk("SAS_PROTO_RESPONSE len = %d\n",
1920 param));
1921 sata_resp = &psataPayload->sata_resp[0];
1922 resp = (struct ata_task_resp *)ts->buf;
1923 if (t->ata_task.dma_xfer == 0 &&
1924 t->data_dir == PCI_DMA_FROMDEVICE) {
1925 len = sizeof(struct pio_setup_fis);
1926 PM8001_IO_DBG(pm8001_ha,
1927 pm8001_printk("PIO read len = %d\n", len));
1928 } else if (t->ata_task.use_ncq) {
1929 len = sizeof(struct set_dev_bits_fis);
1930 PM8001_IO_DBG(pm8001_ha,
1931 pm8001_printk("FPDMA len = %d\n", len));
1932 } else {
1933 len = sizeof(struct dev_to_host_fis);
1934 PM8001_IO_DBG(pm8001_ha,
1935 pm8001_printk("other len = %d\n", len));
1936 }
1937 if (SAS_STATUS_BUF_SIZE >= sizeof(*resp)) {
1938 resp->frame_len = len;
1939 memcpy(&resp->ending_fis[0], sata_resp, len);
1940 ts->buf_valid_size = sizeof(*resp);
1941 } else
1942 PM8001_IO_DBG(pm8001_ha,
1943 pm8001_printk("response to large \n"));
1944 }
1945 if (pm8001_dev)
1946 pm8001_dev->running_req--;
1947 break;
1948 case IO_ABORTED:
1949 PM8001_IO_DBG(pm8001_ha,
1950 pm8001_printk("IO_ABORTED IOMB Tag \n"));
1951 ts->resp = SAS_TASK_COMPLETE;
1952 ts->stat = SAS_ABORTED_TASK;
1953 if (pm8001_dev)
1954 pm8001_dev->running_req--;
1955 break;
1956 /* following cases are to do cases */
1957 case IO_UNDERFLOW:
1958 /* SATA Completion with error */
1959 PM8001_IO_DBG(pm8001_ha,
1960 pm8001_printk("IO_UNDERFLOW param = %d\n", param));
1961 ts->resp = SAS_TASK_COMPLETE;
1962 ts->stat = SAS_DATA_UNDERRUN;
1963 ts->residual = param;
1964 if (pm8001_dev)
1965 pm8001_dev->running_req--;
1966 break;
1967 case IO_NO_DEVICE:
1968 PM8001_IO_DBG(pm8001_ha,
1969 pm8001_printk("IO_NO_DEVICE\n"));
1970 ts->resp = SAS_TASK_UNDELIVERED;
1971 ts->stat = SAS_PHY_DOWN;
1972 break;
1973 case IO_XFER_ERROR_BREAK:
1974 PM8001_IO_DBG(pm8001_ha,
1975 pm8001_printk("IO_XFER_ERROR_BREAK\n"));
1976 ts->resp = SAS_TASK_COMPLETE;
1977 ts->stat = SAS_INTERRUPTED;
1978 break;
1979 case IO_XFER_ERROR_PHY_NOT_READY:
1980 PM8001_IO_DBG(pm8001_ha,
1981 pm8001_printk("IO_XFER_ERROR_PHY_NOT_READY\n"));
1982 ts->resp = SAS_TASK_COMPLETE;
1983 ts->stat = SAS_OPEN_REJECT;
1984 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
1985 break;
1986 case IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED:
1987 PM8001_IO_DBG(pm8001_ha,
1988 pm8001_printk("IO_OPEN_CNX_ERROR_PROTOCOL_NOT"
1989 "_SUPPORTED\n"));
1990 ts->resp = SAS_TASK_COMPLETE;
1991 ts->stat = SAS_OPEN_REJECT;
1992 ts->open_rej_reason = SAS_OREJ_EPROTO;
1993 break;
1994 case IO_OPEN_CNX_ERROR_ZONE_VIOLATION:
1995 PM8001_IO_DBG(pm8001_ha,
1996 pm8001_printk("IO_OPEN_CNX_ERROR_ZONE_VIOLATION\n"));
1997 ts->resp = SAS_TASK_COMPLETE;
1998 ts->stat = SAS_OPEN_REJECT;
1999 ts->open_rej_reason = SAS_OREJ_UNKNOWN;
2000 break;
2001 case IO_OPEN_CNX_ERROR_BREAK:
2002 PM8001_IO_DBG(pm8001_ha,
2003 pm8001_printk("IO_OPEN_CNX_ERROR_BREAK\n"));
2004 ts->resp = SAS_TASK_COMPLETE;
2005 ts->stat = SAS_OPEN_REJECT;
2006 ts->open_rej_reason = SAS_OREJ_RSVD_CONT0;
2007 break;
2008 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS:
2009 PM8001_IO_DBG(pm8001_ha,
2010 pm8001_printk("IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS\n"));
2011 ts->resp = SAS_TASK_COMPLETE;
2012 ts->stat = SAS_DEV_NO_RESPONSE;
2013 if (!t->uldd_task) {
2014 pm8001_handle_event(pm8001_ha,
2015 pm8001_dev,
2016 IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS);
2017 ts->resp = SAS_TASK_UNDELIVERED;
2018 ts->stat = SAS_QUEUE_FULL;
2019 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
2020 mb();/*in order to force CPU ordering*/
2021 spin_unlock_irqrestore(&pm8001_ha->lock, flags);
2022 t->task_done(t);
2023 spin_lock_irqsave(&pm8001_ha->lock, flags);
2024 return;
2025 }
2026 break;
2027 case IO_OPEN_CNX_ERROR_BAD_DESTINATION:
2028 PM8001_IO_DBG(pm8001_ha,
2029 pm8001_printk("IO_OPEN_CNX_ERROR_BAD_DESTINATION\n"));
2030 ts->resp = SAS_TASK_UNDELIVERED;
2031 ts->stat = SAS_OPEN_REJECT;
2032 ts->open_rej_reason = SAS_OREJ_BAD_DEST;
2033 if (!t->uldd_task) {
2034 pm8001_handle_event(pm8001_ha,
2035 pm8001_dev,
2036 IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS);
2037 ts->resp = SAS_TASK_UNDELIVERED;
2038 ts->stat = SAS_QUEUE_FULL;
2039 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
2040 mb();/*ditto*/
2041 spin_unlock_irqrestore(&pm8001_ha->lock, flags);
2042 t->task_done(t);
2043 spin_lock_irqsave(&pm8001_ha->lock, flags);
2044 return;
2045 }
2046 break;
2047 case IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED:
2048 PM8001_IO_DBG(pm8001_ha,
2049 pm8001_printk("IO_OPEN_CNX_ERROR_CONNECTION_RATE_"
2050 "NOT_SUPPORTED\n"));
2051 ts->resp = SAS_TASK_COMPLETE;
2052 ts->stat = SAS_OPEN_REJECT;
2053 ts->open_rej_reason = SAS_OREJ_CONN_RATE;
2054 break;
2055 case IO_OPEN_CNX_ERROR_STP_RESOURCES_BUSY:
2056 PM8001_IO_DBG(pm8001_ha,
2057 pm8001_printk("IO_OPEN_CNX_ERROR_STP_RESOURCES"
2058 "_BUSY\n"));
2059 ts->resp = SAS_TASK_COMPLETE;
2060 ts->stat = SAS_DEV_NO_RESPONSE;
2061 if (!t->uldd_task) {
2062 pm8001_handle_event(pm8001_ha,
2063 pm8001_dev,
2064 IO_OPEN_CNX_ERROR_STP_RESOURCES_BUSY);
2065 ts->resp = SAS_TASK_UNDELIVERED;
2066 ts->stat = SAS_QUEUE_FULL;
2067 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
2068 mb();/* ditto*/
2069 spin_unlock_irqrestore(&pm8001_ha->lock, flags);
2070 t->task_done(t);
2071 spin_lock_irqsave(&pm8001_ha->lock, flags);
2072 return;
2073 }
2074 break;
2075 case IO_OPEN_CNX_ERROR_WRONG_DESTINATION:
2076 PM8001_IO_DBG(pm8001_ha,
2077 pm8001_printk("IO_OPEN_CNX_ERROR_WRONG_DESTINATION\n"));
2078 ts->resp = SAS_TASK_COMPLETE;
2079 ts->stat = SAS_OPEN_REJECT;
2080 ts->open_rej_reason = SAS_OREJ_WRONG_DEST;
2081 break;
2082 case IO_XFER_ERROR_NAK_RECEIVED:
2083 PM8001_IO_DBG(pm8001_ha,
2084 pm8001_printk("IO_XFER_ERROR_NAK_RECEIVED\n"));
2085 ts->resp = SAS_TASK_COMPLETE;
2086 ts->stat = SAS_NAK_R_ERR;
2087 break;
2088 case IO_XFER_ERROR_ACK_NAK_TIMEOUT:
2089 PM8001_IO_DBG(pm8001_ha,
2090 pm8001_printk("IO_XFER_ERROR_ACK_NAK_TIMEOUT\n"));
2091 ts->resp = SAS_TASK_COMPLETE;
2092 ts->stat = SAS_NAK_R_ERR;
2093 break;
2094 case IO_XFER_ERROR_DMA:
2095 PM8001_IO_DBG(pm8001_ha,
2096 pm8001_printk("IO_XFER_ERROR_DMA\n"));
2097 ts->resp = SAS_TASK_COMPLETE;
2098 ts->stat = SAS_ABORTED_TASK;
2099 break;
2100 case IO_XFER_ERROR_SATA_LINK_TIMEOUT:
2101 PM8001_IO_DBG(pm8001_ha,
2102 pm8001_printk("IO_XFER_ERROR_SATA_LINK_TIMEOUT\n"));
2103 ts->resp = SAS_TASK_UNDELIVERED;
2104 ts->stat = SAS_DEV_NO_RESPONSE;
2105 break;
2106 case IO_XFER_ERROR_REJECTED_NCQ_MODE:
2107 PM8001_IO_DBG(pm8001_ha,
2108 pm8001_printk("IO_XFER_ERROR_REJECTED_NCQ_MODE\n"));
2109 ts->resp = SAS_TASK_COMPLETE;
2110 ts->stat = SAS_DATA_UNDERRUN;
2111 break;
2112 case IO_XFER_OPEN_RETRY_TIMEOUT:
2113 PM8001_IO_DBG(pm8001_ha,
2114 pm8001_printk("IO_XFER_OPEN_RETRY_TIMEOUT\n"));
2115 ts->resp = SAS_TASK_COMPLETE;
2116 ts->stat = SAS_OPEN_TO;
2117 break;
2118 case IO_PORT_IN_RESET:
2119 PM8001_IO_DBG(pm8001_ha,
2120 pm8001_printk("IO_PORT_IN_RESET\n"));
2121 ts->resp = SAS_TASK_COMPLETE;
2122 ts->stat = SAS_DEV_NO_RESPONSE;
2123 break;
2124 case IO_DS_NON_OPERATIONAL:
2125 PM8001_IO_DBG(pm8001_ha,
2126 pm8001_printk("IO_DS_NON_OPERATIONAL\n"));
2127 ts->resp = SAS_TASK_COMPLETE;
2128 ts->stat = SAS_DEV_NO_RESPONSE;
2129 if (!t->uldd_task) {
2130 pm8001_handle_event(pm8001_ha, pm8001_dev,
2131 IO_DS_NON_OPERATIONAL);
2132 ts->resp = SAS_TASK_UNDELIVERED;
2133 ts->stat = SAS_QUEUE_FULL;
2134 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
2135 mb();/*ditto*/
2136 spin_unlock_irqrestore(&pm8001_ha->lock, flags);
2137 t->task_done(t);
2138 spin_lock_irqsave(&pm8001_ha->lock, flags);
2139 return;
2140 }
2141 break;
2142 case IO_DS_IN_RECOVERY:
2143 PM8001_IO_DBG(pm8001_ha,
2144 pm8001_printk(" IO_DS_IN_RECOVERY\n"));
2145 ts->resp = SAS_TASK_COMPLETE;
2146 ts->stat = SAS_DEV_NO_RESPONSE;
2147 break;
2148 case IO_DS_IN_ERROR:
2149 PM8001_IO_DBG(pm8001_ha,
2150 pm8001_printk("IO_DS_IN_ERROR\n"));
2151 ts->resp = SAS_TASK_COMPLETE;
2152 ts->stat = SAS_DEV_NO_RESPONSE;
2153 if (!t->uldd_task) {
2154 pm8001_handle_event(pm8001_ha, pm8001_dev,
2155 IO_DS_IN_ERROR);
2156 ts->resp = SAS_TASK_UNDELIVERED;
2157 ts->stat = SAS_QUEUE_FULL;
2158 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
2159 mb();/*ditto*/
2160 spin_unlock_irqrestore(&pm8001_ha->lock, flags);
2161 t->task_done(t);
2162 spin_lock_irqsave(&pm8001_ha->lock, flags);
2163 return;
2164 }
2165 break;
2166 case IO_OPEN_CNX_ERROR_HW_RESOURCE_BUSY:
2167 PM8001_IO_DBG(pm8001_ha,
2168 pm8001_printk("IO_OPEN_CNX_ERROR_HW_RESOURCE_BUSY\n"));
2169 ts->resp = SAS_TASK_COMPLETE;
2170 ts->stat = SAS_OPEN_REJECT;
2171 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
2172 default:
2173 PM8001_IO_DBG(pm8001_ha,
2174 pm8001_printk("Unknown status 0x%x\n", status));
2175 /* not allowed case. Therefore, return failed status */
2176 ts->resp = SAS_TASK_COMPLETE;
2177 ts->stat = SAS_DEV_NO_RESPONSE;
2178 break;
2179 }
2180 spin_lock_irqsave(&t->task_state_lock, flags);
2181 t->task_state_flags &= ~SAS_TASK_STATE_PENDING;
2182 t->task_state_flags &= ~SAS_TASK_AT_INITIATOR;
2183 t->task_state_flags |= SAS_TASK_STATE_DONE;
2184 if (unlikely((t->task_state_flags & SAS_TASK_STATE_ABORTED))) {
2185 spin_unlock_irqrestore(&t->task_state_lock, flags);
2186 PM8001_FAIL_DBG(pm8001_ha,
2187 pm8001_printk("task 0x%p done with io_status 0x%x"
2188 " resp 0x%x stat 0x%x but aborted by upper layer!\n",
2189 t, status, ts->resp, ts->stat));
2190 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
2191 } else if (t->uldd_task) {
2192 spin_unlock_irqrestore(&t->task_state_lock, flags);
2193 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
2194 mb();/* ditto */
2195 spin_unlock_irqrestore(&pm8001_ha->lock, flags);
2196 t->task_done(t);
2197 spin_lock_irqsave(&pm8001_ha->lock, flags);
2198 } else if (!t->uldd_task) {
2199 spin_unlock_irqrestore(&t->task_state_lock, flags);
2200 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
2201 mb();/*ditto*/
2202 spin_unlock_irqrestore(&pm8001_ha->lock, flags);
2203 t->task_done(t);
2204 spin_lock_irqsave(&pm8001_ha->lock, flags);
2205 }
2206}
2207
2208/*See the comments for mpi_ssp_completion */
2209static void mpi_sata_event(struct pm8001_hba_info *pm8001_ha , void *piomb)
2210{
2211 struct sas_task *t;
2212 unsigned long flags = 0;
2213 struct task_status_struct *ts;
2214 struct pm8001_ccb_info *ccb;
2215 struct pm8001_device *pm8001_dev;
2216 struct sata_event_resp *psataPayload =
2217 (struct sata_event_resp *)(piomb + 4);
2218 u32 event = le32_to_cpu(psataPayload->event);
2219 u32 tag = le32_to_cpu(psataPayload->tag);
2220 u32 port_id = le32_to_cpu(psataPayload->port_id);
2221 u32 dev_id = le32_to_cpu(psataPayload->device_id);
2222
2223 ccb = &pm8001_ha->ccb_info[tag];
2224 t = ccb->task;
2225 pm8001_dev = ccb->device;
2226 if (event)
2227 PM8001_FAIL_DBG(pm8001_ha,
2228 pm8001_printk("sata IO status 0x%x\n", event));
2229 if (unlikely(!t || !t->lldd_task || !t->dev))
2230 return;
2231 ts = &t->task_status;
2232 PM8001_IO_DBG(pm8001_ha,
2233 pm8001_printk("port_id = %x,device_id = %x\n",
2234 port_id, dev_id));
2235 switch (event) {
2236 case IO_OVERFLOW:
2237 PM8001_IO_DBG(pm8001_ha, pm8001_printk("IO_UNDERFLOW\n"));
2238 ts->resp = SAS_TASK_COMPLETE;
2239 ts->stat = SAS_DATA_OVERRUN;
2240 ts->residual = 0;
2241 if (pm8001_dev)
2242 pm8001_dev->running_req--;
2243 break;
2244 case IO_XFER_ERROR_BREAK:
2245 PM8001_IO_DBG(pm8001_ha,
2246 pm8001_printk("IO_XFER_ERROR_BREAK\n"));
2247 ts->resp = SAS_TASK_COMPLETE;
2248 ts->stat = SAS_INTERRUPTED;
2249 break;
2250 case IO_XFER_ERROR_PHY_NOT_READY:
2251 PM8001_IO_DBG(pm8001_ha,
2252 pm8001_printk("IO_XFER_ERROR_PHY_NOT_READY\n"));
2253 ts->resp = SAS_TASK_COMPLETE;
2254 ts->stat = SAS_OPEN_REJECT;
2255 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
2256 break;
2257 case IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED:
2258 PM8001_IO_DBG(pm8001_ha,
2259 pm8001_printk("IO_OPEN_CNX_ERROR_PROTOCOL_NOT"
2260 "_SUPPORTED\n"));
2261 ts->resp = SAS_TASK_COMPLETE;
2262 ts->stat = SAS_OPEN_REJECT;
2263 ts->open_rej_reason = SAS_OREJ_EPROTO;
2264 break;
2265 case IO_OPEN_CNX_ERROR_ZONE_VIOLATION:
2266 PM8001_IO_DBG(pm8001_ha,
2267 pm8001_printk("IO_OPEN_CNX_ERROR_ZONE_VIOLATION\n"));
2268 ts->resp = SAS_TASK_COMPLETE;
2269 ts->stat = SAS_OPEN_REJECT;
2270 ts->open_rej_reason = SAS_OREJ_UNKNOWN;
2271 break;
2272 case IO_OPEN_CNX_ERROR_BREAK:
2273 PM8001_IO_DBG(pm8001_ha,
2274 pm8001_printk("IO_OPEN_CNX_ERROR_BREAK\n"));
2275 ts->resp = SAS_TASK_COMPLETE;
2276 ts->stat = SAS_OPEN_REJECT;
2277 ts->open_rej_reason = SAS_OREJ_RSVD_CONT0;
2278 break;
2279 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS:
2280 PM8001_IO_DBG(pm8001_ha,
2281 pm8001_printk("IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS\n"));
2282 ts->resp = SAS_TASK_UNDELIVERED;
2283 ts->stat = SAS_DEV_NO_RESPONSE;
2284 if (!t->uldd_task) {
2285 pm8001_handle_event(pm8001_ha,
2286 pm8001_dev,
2287 IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS);
2288 ts->resp = SAS_TASK_COMPLETE;
2289 ts->stat = SAS_QUEUE_FULL;
2290 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
2291 mb();/*ditto*/
2292 spin_unlock_irqrestore(&pm8001_ha->lock, flags);
2293 t->task_done(t);
2294 spin_lock_irqsave(&pm8001_ha->lock, flags);
2295 return;
2296 }
2297 break;
2298 case IO_OPEN_CNX_ERROR_BAD_DESTINATION:
2299 PM8001_IO_DBG(pm8001_ha,
2300 pm8001_printk("IO_OPEN_CNX_ERROR_BAD_DESTINATION\n"));
2301 ts->resp = SAS_TASK_UNDELIVERED;
2302 ts->stat = SAS_OPEN_REJECT;
2303 ts->open_rej_reason = SAS_OREJ_BAD_DEST;
2304 break;
2305 case IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED:
2306 PM8001_IO_DBG(pm8001_ha,
2307 pm8001_printk("IO_OPEN_CNX_ERROR_CONNECTION_RATE_"
2308 "NOT_SUPPORTED\n"));
2309 ts->resp = SAS_TASK_COMPLETE;
2310 ts->stat = SAS_OPEN_REJECT;
2311 ts->open_rej_reason = SAS_OREJ_CONN_RATE;
2312 break;
2313 case IO_OPEN_CNX_ERROR_WRONG_DESTINATION:
2314 PM8001_IO_DBG(pm8001_ha,
2315 pm8001_printk("IO_OPEN_CNX_ERROR_WRONG_DESTINATION\n"));
2316 ts->resp = SAS_TASK_COMPLETE;
2317 ts->stat = SAS_OPEN_REJECT;
2318 ts->open_rej_reason = SAS_OREJ_WRONG_DEST;
2319 break;
2320 case IO_XFER_ERROR_NAK_RECEIVED:
2321 PM8001_IO_DBG(pm8001_ha,
2322 pm8001_printk("IO_XFER_ERROR_NAK_RECEIVED\n"));
2323 ts->resp = SAS_TASK_COMPLETE;
2324 ts->stat = SAS_NAK_R_ERR;
2325 break;
2326 case IO_XFER_ERROR_PEER_ABORTED:
2327 PM8001_IO_DBG(pm8001_ha,
2328 pm8001_printk("IO_XFER_ERROR_PEER_ABORTED\n"));
2329 ts->resp = SAS_TASK_COMPLETE;
2330 ts->stat = SAS_NAK_R_ERR;
2331 break;
2332 case IO_XFER_ERROR_REJECTED_NCQ_MODE:
2333 PM8001_IO_DBG(pm8001_ha,
2334 pm8001_printk("IO_XFER_ERROR_REJECTED_NCQ_MODE\n"));
2335 ts->resp = SAS_TASK_COMPLETE;
2336 ts->stat = SAS_DATA_UNDERRUN;
2337 break;
2338 case IO_XFER_OPEN_RETRY_TIMEOUT:
2339 PM8001_IO_DBG(pm8001_ha,
2340 pm8001_printk("IO_XFER_OPEN_RETRY_TIMEOUT\n"));
2341 ts->resp = SAS_TASK_COMPLETE;
2342 ts->stat = SAS_OPEN_TO;
2343 break;
2344 case IO_XFER_ERROR_UNEXPECTED_PHASE:
2345 PM8001_IO_DBG(pm8001_ha,
2346 pm8001_printk("IO_XFER_ERROR_UNEXPECTED_PHASE\n"));
2347 ts->resp = SAS_TASK_COMPLETE;
2348 ts->stat = SAS_OPEN_TO;
2349 break;
2350 case IO_XFER_ERROR_XFER_RDY_OVERRUN:
2351 PM8001_IO_DBG(pm8001_ha,
2352 pm8001_printk("IO_XFER_ERROR_XFER_RDY_OVERRUN\n"));
2353 ts->resp = SAS_TASK_COMPLETE;
2354 ts->stat = SAS_OPEN_TO;
2355 break;
2356 case IO_XFER_ERROR_XFER_RDY_NOT_EXPECTED:
2357 PM8001_IO_DBG(pm8001_ha,
2358 pm8001_printk("IO_XFER_ERROR_XFER_RDY_NOT_EXPECTED\n"));
2359 ts->resp = SAS_TASK_COMPLETE;
2360 ts->stat = SAS_OPEN_TO;
2361 break;
2362 case IO_XFER_ERROR_OFFSET_MISMATCH:
2363 PM8001_IO_DBG(pm8001_ha,
2364 pm8001_printk("IO_XFER_ERROR_OFFSET_MISMATCH\n"));
2365 ts->resp = SAS_TASK_COMPLETE;
2366 ts->stat = SAS_OPEN_TO;
2367 break;
2368 case IO_XFER_ERROR_XFER_ZERO_DATA_LEN:
2369 PM8001_IO_DBG(pm8001_ha,
2370 pm8001_printk("IO_XFER_ERROR_XFER_ZERO_DATA_LEN\n"));
2371 ts->resp = SAS_TASK_COMPLETE;
2372 ts->stat = SAS_OPEN_TO;
2373 break;
2374 case IO_XFER_CMD_FRAME_ISSUED:
2375 PM8001_IO_DBG(pm8001_ha,
2376 pm8001_printk("IO_XFER_CMD_FRAME_ISSUED\n"));
2377 break;
2378 case IO_XFER_PIO_SETUP_ERROR:
2379 PM8001_IO_DBG(pm8001_ha,
2380 pm8001_printk("IO_XFER_PIO_SETUP_ERROR\n"));
2381 ts->resp = SAS_TASK_COMPLETE;
2382 ts->stat = SAS_OPEN_TO;
2383 break;
2384 default:
2385 PM8001_IO_DBG(pm8001_ha,
2386 pm8001_printk("Unknown status 0x%x\n", event));
2387 /* not allowed case. Therefore, return failed status */
2388 ts->resp = SAS_TASK_COMPLETE;
2389 ts->stat = SAS_OPEN_TO;
2390 break;
2391 }
2392 spin_lock_irqsave(&t->task_state_lock, flags);
2393 t->task_state_flags &= ~SAS_TASK_STATE_PENDING;
2394 t->task_state_flags &= ~SAS_TASK_AT_INITIATOR;
2395 t->task_state_flags |= SAS_TASK_STATE_DONE;
2396 if (unlikely((t->task_state_flags & SAS_TASK_STATE_ABORTED))) {
2397 spin_unlock_irqrestore(&t->task_state_lock, flags);
2398 PM8001_FAIL_DBG(pm8001_ha,
2399 pm8001_printk("task 0x%p done with io_status 0x%x"
2400 " resp 0x%x stat 0x%x but aborted by upper layer!\n",
2401 t, event, ts->resp, ts->stat));
2402 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
2403 } else if (t->uldd_task) {
2404 spin_unlock_irqrestore(&t->task_state_lock, flags);
2405 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
2406 mb();/* ditto */
2407 spin_unlock_irqrestore(&pm8001_ha->lock, flags);
2408 t->task_done(t);
2409 spin_lock_irqsave(&pm8001_ha->lock, flags);
2410 } else if (!t->uldd_task) {
2411 spin_unlock_irqrestore(&t->task_state_lock, flags);
2412 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
2413 mb();/*ditto*/
2414 spin_unlock_irqrestore(&pm8001_ha->lock, flags);
2415 t->task_done(t);
2416 spin_lock_irqsave(&pm8001_ha->lock, flags);
2417 }
2418}
2419
2420/*See the comments for mpi_ssp_completion */
2421static void
2422mpi_smp_completion(struct pm8001_hba_info *pm8001_ha, void *piomb)
2423{
2424 u32 param;
2425 struct sas_task *t;
2426 struct pm8001_ccb_info *ccb;
2427 unsigned long flags;
2428 u32 status;
2429 u32 tag;
2430 struct smp_completion_resp *psmpPayload;
2431 struct task_status_struct *ts;
2432 struct pm8001_device *pm8001_dev;
2433
2434 psmpPayload = (struct smp_completion_resp *)(piomb + 4);
2435 status = le32_to_cpu(psmpPayload->status);
2436 tag = le32_to_cpu(psmpPayload->tag);
2437
2438 ccb = &pm8001_ha->ccb_info[tag];
2439 param = le32_to_cpu(psmpPayload->param);
2440 t = ccb->task;
2441 ts = &t->task_status;
2442 pm8001_dev = ccb->device;
2443 if (status)
2444 PM8001_FAIL_DBG(pm8001_ha,
2445 pm8001_printk("smp IO status 0x%x\n", status));
2446 if (unlikely(!t || !t->lldd_task || !t->dev))
2447 return;
2448
2449 switch (status) {
2450 case IO_SUCCESS:
2451 PM8001_IO_DBG(pm8001_ha, pm8001_printk("IO_SUCCESS\n"));
2452 ts->resp = SAS_TASK_COMPLETE;
2453 ts->stat = SAM_GOOD;
2454 if (pm8001_dev)
2455 pm8001_dev->running_req--;
2456 break;
2457 case IO_ABORTED:
2458 PM8001_IO_DBG(pm8001_ha,
2459 pm8001_printk("IO_ABORTED IOMB\n"));
2460 ts->resp = SAS_TASK_COMPLETE;
2461 ts->stat = SAS_ABORTED_TASK;
2462 if (pm8001_dev)
2463 pm8001_dev->running_req--;
2464 break;
2465 case IO_OVERFLOW:
2466 PM8001_IO_DBG(pm8001_ha, pm8001_printk("IO_UNDERFLOW\n"));
2467 ts->resp = SAS_TASK_COMPLETE;
2468 ts->stat = SAS_DATA_OVERRUN;
2469 ts->residual = 0;
2470 if (pm8001_dev)
2471 pm8001_dev->running_req--;
2472 break;
2473 case IO_NO_DEVICE:
2474 PM8001_IO_DBG(pm8001_ha, pm8001_printk("IO_NO_DEVICE\n"));
2475 ts->resp = SAS_TASK_COMPLETE;
2476 ts->stat = SAS_PHY_DOWN;
2477 break;
2478 case IO_ERROR_HW_TIMEOUT:
2479 PM8001_IO_DBG(pm8001_ha,
2480 pm8001_printk("IO_ERROR_HW_TIMEOUT\n"));
2481 ts->resp = SAS_TASK_COMPLETE;
2482 ts->stat = SAM_BUSY;
2483 break;
2484 case IO_XFER_ERROR_BREAK:
2485 PM8001_IO_DBG(pm8001_ha,
2486 pm8001_printk("IO_XFER_ERROR_BREAK\n"));
2487 ts->resp = SAS_TASK_COMPLETE;
2488 ts->stat = SAM_BUSY;
2489 break;
2490 case IO_XFER_ERROR_PHY_NOT_READY:
2491 PM8001_IO_DBG(pm8001_ha,
2492 pm8001_printk("IO_XFER_ERROR_PHY_NOT_READY\n"));
2493 ts->resp = SAS_TASK_COMPLETE;
2494 ts->stat = SAM_BUSY;
2495 break;
2496 case IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED:
2497 PM8001_IO_DBG(pm8001_ha,
2498 pm8001_printk("IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED\n"));
2499 ts->resp = SAS_TASK_COMPLETE;
2500 ts->stat = SAS_OPEN_REJECT;
2501 ts->open_rej_reason = SAS_OREJ_UNKNOWN;
2502 break;
2503 case IO_OPEN_CNX_ERROR_ZONE_VIOLATION:
2504 PM8001_IO_DBG(pm8001_ha,
2505 pm8001_printk("IO_OPEN_CNX_ERROR_ZONE_VIOLATION\n"));
2506 ts->resp = SAS_TASK_COMPLETE;
2507 ts->stat = SAS_OPEN_REJECT;
2508 ts->open_rej_reason = SAS_OREJ_UNKNOWN;
2509 break;
2510 case IO_OPEN_CNX_ERROR_BREAK:
2511 PM8001_IO_DBG(pm8001_ha,
2512 pm8001_printk("IO_OPEN_CNX_ERROR_BREAK\n"));
2513 ts->resp = SAS_TASK_COMPLETE;
2514 ts->stat = SAS_OPEN_REJECT;
2515 ts->open_rej_reason = SAS_OREJ_RSVD_CONT0;
2516 break;
2517 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS:
2518 PM8001_IO_DBG(pm8001_ha,
2519 pm8001_printk("IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS\n"));
2520 ts->resp = SAS_TASK_COMPLETE;
2521 ts->stat = SAS_OPEN_REJECT;
2522 ts->open_rej_reason = SAS_OREJ_UNKNOWN;
2523 pm8001_handle_event(pm8001_ha,
2524 pm8001_dev,
2525 IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS);
2526 break;
2527 case IO_OPEN_CNX_ERROR_BAD_DESTINATION:
2528 PM8001_IO_DBG(pm8001_ha,
2529 pm8001_printk("IO_OPEN_CNX_ERROR_BAD_DESTINATION\n"));
2530 ts->resp = SAS_TASK_COMPLETE;
2531 ts->stat = SAS_OPEN_REJECT;
2532 ts->open_rej_reason = SAS_OREJ_BAD_DEST;
2533 break;
2534 case IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED:
2535 PM8001_IO_DBG(pm8001_ha,
2536 pm8001_printk("IO_OPEN_CNX_ERROR_CONNECTION_RATE_"
2537 "NOT_SUPPORTED\n"));
2538 ts->resp = SAS_TASK_COMPLETE;
2539 ts->stat = SAS_OPEN_REJECT;
2540 ts->open_rej_reason = SAS_OREJ_CONN_RATE;
2541 break;
2542 case IO_OPEN_CNX_ERROR_WRONG_DESTINATION:
2543 PM8001_IO_DBG(pm8001_ha,
2544 pm8001_printk("IO_OPEN_CNX_ERROR_WRONG_DESTINATION\n"));
2545 ts->resp = SAS_TASK_COMPLETE;
2546 ts->stat = SAS_OPEN_REJECT;
2547 ts->open_rej_reason = SAS_OREJ_WRONG_DEST;
2548 break;
2549 case IO_XFER_ERROR_RX_FRAME:
2550 PM8001_IO_DBG(pm8001_ha,
2551 pm8001_printk("IO_XFER_ERROR_RX_FRAME\n"));
2552 ts->resp = SAS_TASK_COMPLETE;
2553 ts->stat = SAS_DEV_NO_RESPONSE;
2554 break;
2555 case IO_XFER_OPEN_RETRY_TIMEOUT:
2556 PM8001_IO_DBG(pm8001_ha,
2557 pm8001_printk("IO_XFER_OPEN_RETRY_TIMEOUT\n"));
2558 ts->resp = SAS_TASK_COMPLETE;
2559 ts->stat = SAS_OPEN_REJECT;
2560 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
2561 break;
2562 case IO_ERROR_INTERNAL_SMP_RESOURCE:
2563 PM8001_IO_DBG(pm8001_ha,
2564 pm8001_printk("IO_ERROR_INTERNAL_SMP_RESOURCE\n"));
2565 ts->resp = SAS_TASK_COMPLETE;
2566 ts->stat = SAS_QUEUE_FULL;
2567 break;
2568 case IO_PORT_IN_RESET:
2569 PM8001_IO_DBG(pm8001_ha,
2570 pm8001_printk("IO_PORT_IN_RESET\n"));
2571 ts->resp = SAS_TASK_COMPLETE;
2572 ts->stat = SAS_OPEN_REJECT;
2573 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
2574 break;
2575 case IO_DS_NON_OPERATIONAL:
2576 PM8001_IO_DBG(pm8001_ha,
2577 pm8001_printk("IO_DS_NON_OPERATIONAL\n"));
2578 ts->resp = SAS_TASK_COMPLETE;
2579 ts->stat = SAS_DEV_NO_RESPONSE;
2580 break;
2581 case IO_DS_IN_RECOVERY:
2582 PM8001_IO_DBG(pm8001_ha,
2583 pm8001_printk("IO_DS_IN_RECOVERY\n"));
2584 ts->resp = SAS_TASK_COMPLETE;
2585 ts->stat = SAS_OPEN_REJECT;
2586 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
2587 break;
2588 case IO_OPEN_CNX_ERROR_HW_RESOURCE_BUSY:
2589 PM8001_IO_DBG(pm8001_ha,
2590 pm8001_printk("IO_OPEN_CNX_ERROR_HW_RESOURCE_BUSY\n"));
2591 ts->resp = SAS_TASK_COMPLETE;
2592 ts->stat = SAS_OPEN_REJECT;
2593 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
2594 break;
2595 default:
2596 PM8001_IO_DBG(pm8001_ha,
2597 pm8001_printk("Unknown status 0x%x\n", status));
2598 ts->resp = SAS_TASK_COMPLETE;
2599 ts->stat = SAS_DEV_NO_RESPONSE;
2600 /* not allowed case. Therefore, return failed status */
2601 break;
2602 }
2603 spin_lock_irqsave(&t->task_state_lock, flags);
2604 t->task_state_flags &= ~SAS_TASK_STATE_PENDING;
2605 t->task_state_flags &= ~SAS_TASK_AT_INITIATOR;
2606 t->task_state_flags |= SAS_TASK_STATE_DONE;
2607 if (unlikely((t->task_state_flags & SAS_TASK_STATE_ABORTED))) {
2608 spin_unlock_irqrestore(&t->task_state_lock, flags);
2609 PM8001_FAIL_DBG(pm8001_ha, pm8001_printk("task 0x%p done with"
2610 " io_status 0x%x resp 0x%x "
2611 "stat 0x%x but aborted by upper layer!\n",
2612 t, status, ts->resp, ts->stat));
2613 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
2614 } else {
2615 spin_unlock_irqrestore(&t->task_state_lock, flags);
2616 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
2617 mb();/* in order to force CPU ordering */
2618 t->task_done(t);
2619 }
2620}
2621
2622static void
2623mpi_set_dev_state_resp(struct pm8001_hba_info *pm8001_ha, void *piomb)
2624{
2625 struct set_dev_state_resp *pPayload =
2626 (struct set_dev_state_resp *)(piomb + 4);
2627 u32 tag = le32_to_cpu(pPayload->tag);
2628 struct pm8001_ccb_info *ccb = &pm8001_ha->ccb_info[tag];
2629 struct pm8001_device *pm8001_dev = ccb->device;
2630 u32 status = le32_to_cpu(pPayload->status);
2631 u32 device_id = le32_to_cpu(pPayload->device_id);
2632 u8 pds = le32_to_cpu(pPayload->pds_nds) | PDS_BITS;
2633 u8 nds = le32_to_cpu(pPayload->pds_nds) | NDS_BITS;
2634 PM8001_MSG_DBG(pm8001_ha, pm8001_printk("Set device id = 0x%x state "
2635 "from 0x%x to 0x%x status = 0x%x!\n",
2636 device_id, pds, nds, status));
2637 complete(pm8001_dev->setds_completion);
2638 ccb->task = NULL;
2639 ccb->ccb_tag = 0xFFFFFFFF;
2640 pm8001_ccb_free(pm8001_ha, tag);
2641}
2642
2643static void
2644mpi_set_nvmd_resp(struct pm8001_hba_info *pm8001_ha, void *piomb)
2645{
2646 struct get_nvm_data_resp *pPayload =
2647 (struct get_nvm_data_resp *)(piomb + 4);
2648 u32 tag = le32_to_cpu(pPayload->tag);
2649 struct pm8001_ccb_info *ccb = &pm8001_ha->ccb_info[tag];
2650 u32 dlen_status = le32_to_cpu(pPayload->dlen_status);
2651 complete(pm8001_ha->nvmd_completion);
2652 PM8001_MSG_DBG(pm8001_ha, pm8001_printk("Set nvm data complete!\n"));
2653 if ((dlen_status & NVMD_STAT) != 0) {
2654 PM8001_FAIL_DBG(pm8001_ha,
2655 pm8001_printk("Set nvm data error!\n"));
2656 return;
2657 }
2658 ccb->task = NULL;
2659 ccb->ccb_tag = 0xFFFFFFFF;
2660 pm8001_ccb_free(pm8001_ha, tag);
2661}
2662
2663static void
2664mpi_get_nvmd_resp(struct pm8001_hba_info *pm8001_ha, void *piomb)
2665{
2666 struct fw_control_ex *fw_control_context;
2667 struct get_nvm_data_resp *pPayload =
2668 (struct get_nvm_data_resp *)(piomb + 4);
2669 u32 tag = le32_to_cpu(pPayload->tag);
2670 struct pm8001_ccb_info *ccb = &pm8001_ha->ccb_info[tag];
2671 u32 dlen_status = le32_to_cpu(pPayload->dlen_status);
2672 u32 ir_tds_bn_dps_das_nvm =
2673 le32_to_cpu(pPayload->ir_tda_bn_dps_das_nvm);
2674 void *virt_addr = pm8001_ha->memoryMap.region[NVMD].virt_ptr;
2675 fw_control_context = ccb->fw_control_context;
2676
2677 PM8001_MSG_DBG(pm8001_ha, pm8001_printk("Get nvm data complete!\n"));
2678 if ((dlen_status & NVMD_STAT) != 0) {
2679 PM8001_FAIL_DBG(pm8001_ha,
2680 pm8001_printk("Get nvm data error!\n"));
2681 complete(pm8001_ha->nvmd_completion);
2682 return;
2683 }
2684
2685 if (ir_tds_bn_dps_das_nvm & IPMode) {
2686 /* indirect mode - IR bit set */
2687 PM8001_MSG_DBG(pm8001_ha,
2688 pm8001_printk("Get NVMD success, IR=1\n"));
2689 if ((ir_tds_bn_dps_das_nvm & NVMD_TYPE) == TWI_DEVICE) {
2690 if (ir_tds_bn_dps_das_nvm == 0x80a80200) {
2691 memcpy(pm8001_ha->sas_addr,
2692 ((u8 *)virt_addr + 4),
2693 SAS_ADDR_SIZE);
2694 PM8001_MSG_DBG(pm8001_ha,
2695 pm8001_printk("Get SAS address"
2696 " from VPD successfully!\n"));
2697 }
2698 } else if (((ir_tds_bn_dps_das_nvm & NVMD_TYPE) == C_SEEPROM)
2699 || ((ir_tds_bn_dps_das_nvm & NVMD_TYPE) == VPD_FLASH) ||
2700 ((ir_tds_bn_dps_das_nvm & NVMD_TYPE) == EXPAN_ROM)) {
2701 ;
2702 } else if (((ir_tds_bn_dps_das_nvm & NVMD_TYPE) == AAP1_RDUMP)
2703 || ((ir_tds_bn_dps_das_nvm & NVMD_TYPE) == IOP_RDUMP)) {
2704 ;
2705 } else {
2706 /* Should not be happened*/
2707 PM8001_MSG_DBG(pm8001_ha,
2708 pm8001_printk("(IR=1)Wrong Device type 0x%x\n",
2709 ir_tds_bn_dps_das_nvm));
2710 }
2711 } else /* direct mode */{
2712 PM8001_MSG_DBG(pm8001_ha,
2713 pm8001_printk("Get NVMD success, IR=0, dataLen=%d\n",
2714 (dlen_status & NVMD_LEN) >> 24));
2715 }
2716 memcpy(fw_control_context->usrAddr,
2717 pm8001_ha->memoryMap.region[NVMD].virt_ptr,
2718 fw_control_context->len);
2719 complete(pm8001_ha->nvmd_completion);
2720 ccb->task = NULL;
2721 ccb->ccb_tag = 0xFFFFFFFF;
2722 pm8001_ccb_free(pm8001_ha, tag);
2723}
2724
2725static int mpi_local_phy_ctl(struct pm8001_hba_info *pm8001_ha, void *piomb)
2726{
2727 struct local_phy_ctl_resp *pPayload =
2728 (struct local_phy_ctl_resp *)(piomb + 4);
2729 u32 status = le32_to_cpu(pPayload->status);
2730 u32 phy_id = le32_to_cpu(pPayload->phyop_phyid) & ID_BITS;
2731 u32 phy_op = le32_to_cpu(pPayload->phyop_phyid) & OP_BITS;
2732 if (status != 0) {
2733 PM8001_MSG_DBG(pm8001_ha,
2734 pm8001_printk("%x phy execute %x phy op failed! \n",
2735 phy_id, phy_op));
2736 } else
2737 PM8001_MSG_DBG(pm8001_ha,
2738 pm8001_printk("%x phy execute %x phy op success! \n",
2739 phy_id, phy_op));
2740 return 0;
2741}
2742
2743/**
2744 * pm8001_bytes_dmaed - one of the interface function communication with libsas
2745 * @pm8001_ha: our hba card information
2746 * @i: which phy that received the event.
2747 *
2748 * when HBA driver received the identify done event or initiate FIS received
2749 * event(for SATA), it will invoke this function to notify the sas layer that
2750 * the sas toplogy has formed, please discover the the whole sas domain,
2751 * while receive a broadcast(change) primitive just tell the sas
2752 * layer to discover the changed domain rather than the whole domain.
2753 */
2754static void pm8001_bytes_dmaed(struct pm8001_hba_info *pm8001_ha, int i)
2755{
2756 struct pm8001_phy *phy = &pm8001_ha->phy[i];
2757 struct asd_sas_phy *sas_phy = &phy->sas_phy;
2758 struct sas_ha_struct *sas_ha;
2759 if (!phy->phy_attached)
2760 return;
2761
2762 sas_ha = pm8001_ha->sas;
2763 if (sas_phy->phy) {
2764 struct sas_phy *sphy = sas_phy->phy;
2765 sphy->negotiated_linkrate = sas_phy->linkrate;
2766 sphy->minimum_linkrate = phy->minimum_linkrate;
2767 sphy->minimum_linkrate_hw = SAS_LINK_RATE_1_5_GBPS;
2768 sphy->maximum_linkrate = phy->maximum_linkrate;
2769 sphy->maximum_linkrate_hw = phy->maximum_linkrate;
2770 }
2771
2772 if (phy->phy_type & PORT_TYPE_SAS) {
2773 struct sas_identify_frame *id;
2774 id = (struct sas_identify_frame *)phy->frame_rcvd;
2775 id->dev_type = phy->identify.device_type;
2776 id->initiator_bits = SAS_PROTOCOL_ALL;
2777 id->target_bits = phy->identify.target_port_protocols;
2778 } else if (phy->phy_type & PORT_TYPE_SATA) {
2779 /*Nothing*/
2780 }
2781 PM8001_MSG_DBG(pm8001_ha, pm8001_printk("phy %d byte dmaded.\n", i));
2782
2783 sas_phy->frame_rcvd_size = phy->frame_rcvd_size;
2784 pm8001_ha->sas->notify_port_event(sas_phy, PORTE_BYTES_DMAED);
2785}
2786
2787/* Get the link rate speed */
2788static void get_lrate_mode(struct pm8001_phy *phy, u8 link_rate)
2789{
2790 struct sas_phy *sas_phy = phy->sas_phy.phy;
2791
2792 switch (link_rate) {
2793 case PHY_SPEED_60:
2794 phy->sas_phy.linkrate = SAS_LINK_RATE_6_0_GBPS;
2795 phy->sas_phy.phy->negotiated_linkrate = SAS_LINK_RATE_6_0_GBPS;
2796 break;
2797 case PHY_SPEED_30:
2798 phy->sas_phy.linkrate = SAS_LINK_RATE_3_0_GBPS;
2799 phy->sas_phy.phy->negotiated_linkrate = SAS_LINK_RATE_3_0_GBPS;
2800 break;
2801 case PHY_SPEED_15:
2802 phy->sas_phy.linkrate = SAS_LINK_RATE_1_5_GBPS;
2803 phy->sas_phy.phy->negotiated_linkrate = SAS_LINK_RATE_1_5_GBPS;
2804 break;
2805 }
2806 sas_phy->negotiated_linkrate = phy->sas_phy.linkrate;
2807 sas_phy->maximum_linkrate_hw = SAS_LINK_RATE_6_0_GBPS;
2808 sas_phy->minimum_linkrate_hw = SAS_LINK_RATE_1_5_GBPS;
2809 sas_phy->maximum_linkrate = SAS_LINK_RATE_6_0_GBPS;
2810 sas_phy->minimum_linkrate = SAS_LINK_RATE_1_5_GBPS;
2811}
2812
2813/**
2814 * asd_get_attached_sas_addr -- extract/generate attached SAS address
2815 * @phy: pointer to asd_phy
2816 * @sas_addr: pointer to buffer where the SAS address is to be written
2817 *
2818 * This function extracts the SAS address from an IDENTIFY frame
2819 * received. If OOB is SATA, then a SAS address is generated from the
2820 * HA tables.
2821 *
2822 * LOCKING: the frame_rcvd_lock needs to be held since this parses the frame
2823 * buffer.
2824 */
2825static void pm8001_get_attached_sas_addr(struct pm8001_phy *phy,
2826 u8 *sas_addr)
2827{
2828 if (phy->sas_phy.frame_rcvd[0] == 0x34
2829 && phy->sas_phy.oob_mode == SATA_OOB_MODE) {
2830 struct pm8001_hba_info *pm8001_ha = phy->sas_phy.ha->lldd_ha;
2831 /* FIS device-to-host */
2832 u64 addr = be64_to_cpu(*(__be64 *)pm8001_ha->sas_addr);
2833 addr += phy->sas_phy.id;
2834 *(__be64 *)sas_addr = cpu_to_be64(addr);
2835 } else {
2836 struct sas_identify_frame *idframe =
2837 (void *) phy->sas_phy.frame_rcvd;
2838 memcpy(sas_addr, idframe->sas_addr, SAS_ADDR_SIZE);
2839 }
2840}
2841
2842/**
2843 * pm8001_hw_event_ack_req- For PM8001,some events need to acknowage to FW.
2844 * @pm8001_ha: our hba card information
2845 * @Qnum: the outbound queue message number.
2846 * @SEA: source of event to ack
2847 * @port_id: port id.
2848 * @phyId: phy id.
2849 * @param0: parameter 0.
2850 * @param1: parameter 1.
2851 */
2852static void pm8001_hw_event_ack_req(struct pm8001_hba_info *pm8001_ha,
2853 u32 Qnum, u32 SEA, u32 port_id, u32 phyId, u32 param0, u32 param1)
2854{
2855 struct hw_event_ack_req payload;
2856 u32 opc = OPC_INB_SAS_HW_EVENT_ACK;
2857
2858 struct inbound_queue_table *circularQ;
2859
2860 memset((u8 *)&payload, 0, sizeof(payload));
2861 circularQ = &pm8001_ha->inbnd_q_tbl[Qnum];
2862 payload.tag = 1;
2863 payload.sea_phyid_portid = cpu_to_le32(((SEA & 0xFFFF) << 8) |
2864 ((phyId & 0x0F) << 4) | (port_id & 0x0F));
2865 payload.param0 = cpu_to_le32(param0);
2866 payload.param1 = cpu_to_le32(param1);
2867 mpi_build_cmd(pm8001_ha, circularQ, opc, &payload);
2868}
2869
2870static int pm8001_chip_phy_ctl_req(struct pm8001_hba_info *pm8001_ha,
2871 u32 phyId, u32 phy_op);
2872
2873/**
2874 * hw_event_sas_phy_up -FW tells me a SAS phy up event.
2875 * @pm8001_ha: our hba card information
2876 * @piomb: IO message buffer
2877 */
2878static void
2879hw_event_sas_phy_up(struct pm8001_hba_info *pm8001_ha, void *piomb)
2880{
2881 struct hw_event_resp *pPayload =
2882 (struct hw_event_resp *)(piomb + 4);
2883 u32 lr_evt_status_phyid_portid =
2884 le32_to_cpu(pPayload->lr_evt_status_phyid_portid);
2885 u8 link_rate =
2886 (u8)((lr_evt_status_phyid_portid & 0xF0000000) >> 28);
2887 u8 port_id = (u8)(lr_evt_status_phyid_portid & 0x0000000F);
2888 u8 phy_id =
2889 (u8)((lr_evt_status_phyid_portid & 0x000000F0) >> 4);
2890 u32 npip_portstate = le32_to_cpu(pPayload->npip_portstate);
2891 u8 portstate = (u8)(npip_portstate & 0x0000000F);
2892 struct pm8001_port *port = &pm8001_ha->port[port_id];
2893 struct sas_ha_struct *sas_ha = pm8001_ha->sas;
2894 struct pm8001_phy *phy = &pm8001_ha->phy[phy_id];
2895 unsigned long flags;
2896 u8 deviceType = pPayload->sas_identify.dev_type;
2897 port->port_state = portstate;
2898 PM8001_MSG_DBG(pm8001_ha,
2899 pm8001_printk("HW_EVENT_SAS_PHY_UP port id = %d, phy id = %d\n",
2900 port_id, phy_id));
2901
2902 switch (deviceType) {
2903 case SAS_PHY_UNUSED:
2904 PM8001_MSG_DBG(pm8001_ha,
2905 pm8001_printk("device type no device.\n"));
2906 break;
2907 case SAS_END_DEVICE:
2908 PM8001_MSG_DBG(pm8001_ha, pm8001_printk("end device.\n"));
2909 pm8001_chip_phy_ctl_req(pm8001_ha, phy_id,
2910 PHY_NOTIFY_ENABLE_SPINUP);
2911 port->port_attached = 1;
2912 get_lrate_mode(phy, link_rate);
2913 break;
2914 case SAS_EDGE_EXPANDER_DEVICE:
2915 PM8001_MSG_DBG(pm8001_ha,
2916 pm8001_printk("expander device.\n"));
2917 port->port_attached = 1;
2918 get_lrate_mode(phy, link_rate);
2919 break;
2920 case SAS_FANOUT_EXPANDER_DEVICE:
2921 PM8001_MSG_DBG(pm8001_ha,
2922 pm8001_printk("fanout expander device.\n"));
2923 port->port_attached = 1;
2924 get_lrate_mode(phy, link_rate);
2925 break;
2926 default:
2927 PM8001_MSG_DBG(pm8001_ha,
2928 pm8001_printk("unknown device type(%x)\n", deviceType));
2929 break;
2930 }
2931 phy->phy_type |= PORT_TYPE_SAS;
2932 phy->identify.device_type = deviceType;
2933 phy->phy_attached = 1;
2934 if (phy->identify.device_type == SAS_END_DEV)
2935 phy->identify.target_port_protocols = SAS_PROTOCOL_SSP;
2936 else if (phy->identify.device_type != NO_DEVICE)
2937 phy->identify.target_port_protocols = SAS_PROTOCOL_SMP;
2938 phy->sas_phy.oob_mode = SAS_OOB_MODE;
2939 sas_ha->notify_phy_event(&phy->sas_phy, PHYE_OOB_DONE);
2940 spin_lock_irqsave(&phy->sas_phy.frame_rcvd_lock, flags);
2941 memcpy(phy->frame_rcvd, &pPayload->sas_identify,
2942 sizeof(struct sas_identify_frame)-4);
2943 phy->frame_rcvd_size = sizeof(struct sas_identify_frame) - 4;
2944 pm8001_get_attached_sas_addr(phy, phy->sas_phy.attached_sas_addr);
2945 spin_unlock_irqrestore(&phy->sas_phy.frame_rcvd_lock, flags);
2946 if (pm8001_ha->flags == PM8001F_RUN_TIME)
2947 mdelay(200);/*delay a moment to wait disk to spinup*/
2948 pm8001_bytes_dmaed(pm8001_ha, phy_id);
2949}
2950
2951/**
2952 * hw_event_sata_phy_up -FW tells me a SATA phy up event.
2953 * @pm8001_ha: our hba card information
2954 * @piomb: IO message buffer
2955 */
2956static void
2957hw_event_sata_phy_up(struct pm8001_hba_info *pm8001_ha, void *piomb)
2958{
2959 struct hw_event_resp *pPayload =
2960 (struct hw_event_resp *)(piomb + 4);
2961 u32 lr_evt_status_phyid_portid =
2962 le32_to_cpu(pPayload->lr_evt_status_phyid_portid);
2963 u8 link_rate =
2964 (u8)((lr_evt_status_phyid_portid & 0xF0000000) >> 28);
2965 u8 port_id = (u8)(lr_evt_status_phyid_portid & 0x0000000F);
2966 u8 phy_id =
2967 (u8)((lr_evt_status_phyid_portid & 0x000000F0) >> 4);
2968 u32 npip_portstate = le32_to_cpu(pPayload->npip_portstate);
2969 u8 portstate = (u8)(npip_portstate & 0x0000000F);
2970 struct pm8001_port *port = &pm8001_ha->port[port_id];
2971 struct sas_ha_struct *sas_ha = pm8001_ha->sas;
2972 struct pm8001_phy *phy = &pm8001_ha->phy[phy_id];
2973 unsigned long flags;
2974 PM8001_MSG_DBG(pm8001_ha,
2975 pm8001_printk("HW_EVENT_SATA_PHY_UP port id = %d,"
2976 " phy id = %d\n", port_id, phy_id));
2977 port->port_state = portstate;
2978 port->port_attached = 1;
2979 get_lrate_mode(phy, link_rate);
2980 phy->phy_type |= PORT_TYPE_SATA;
2981 phy->phy_attached = 1;
2982 phy->sas_phy.oob_mode = SATA_OOB_MODE;
2983 sas_ha->notify_phy_event(&phy->sas_phy, PHYE_OOB_DONE);
2984 spin_lock_irqsave(&phy->sas_phy.frame_rcvd_lock, flags);
2985 memcpy(phy->frame_rcvd, ((u8 *)&pPayload->sata_fis - 4),
2986 sizeof(struct dev_to_host_fis));
2987 phy->frame_rcvd_size = sizeof(struct dev_to_host_fis);
2988 phy->identify.target_port_protocols = SAS_PROTOCOL_SATA;
2989 phy->identify.device_type = SATA_DEV;
2990 pm8001_get_attached_sas_addr(phy, phy->sas_phy.attached_sas_addr);
2991 spin_unlock_irqrestore(&phy->sas_phy.frame_rcvd_lock, flags);
2992 pm8001_bytes_dmaed(pm8001_ha, phy_id);
2993}
2994
2995/**
2996 * hw_event_phy_down -we should notify the libsas the phy is down.
2997 * @pm8001_ha: our hba card information
2998 * @piomb: IO message buffer
2999 */
3000static void
3001hw_event_phy_down(struct pm8001_hba_info *pm8001_ha, void *piomb)
3002{
3003 struct hw_event_resp *pPayload =
3004 (struct hw_event_resp *)(piomb + 4);
3005 u32 lr_evt_status_phyid_portid =
3006 le32_to_cpu(pPayload->lr_evt_status_phyid_portid);
3007 u8 port_id = (u8)(lr_evt_status_phyid_portid & 0x0000000F);
3008 u8 phy_id =
3009 (u8)((lr_evt_status_phyid_portid & 0x000000F0) >> 4);
3010 u32 npip_portstate = le32_to_cpu(pPayload->npip_portstate);
3011 u8 portstate = (u8)(npip_portstate & 0x0000000F);
3012 struct pm8001_port *port = &pm8001_ha->port[port_id];
3013 struct pm8001_phy *phy = &pm8001_ha->phy[phy_id];
3014 port->port_state = portstate;
3015 phy->phy_type = 0;
3016 phy->identify.device_type = 0;
3017 phy->phy_attached = 0;
3018 memset(&phy->dev_sas_addr, 0, SAS_ADDR_SIZE);
3019 switch (portstate) {
3020 case PORT_VALID:
3021 break;
3022 case PORT_INVALID:
3023 PM8001_MSG_DBG(pm8001_ha,
3024 pm8001_printk(" PortInvalid portID %d \n", port_id));
3025 PM8001_MSG_DBG(pm8001_ha,
3026 pm8001_printk(" Last phy Down and port invalid\n"));
3027 port->port_attached = 0;
3028 pm8001_hw_event_ack_req(pm8001_ha, 0, HW_EVENT_PHY_DOWN,
3029 port_id, phy_id, 0, 0);
3030 break;
3031 case PORT_IN_RESET:
3032 PM8001_MSG_DBG(pm8001_ha,
3033 pm8001_printk(" Port In Reset portID %d \n", port_id));
3034 break;
3035 case PORT_NOT_ESTABLISHED:
3036 PM8001_MSG_DBG(pm8001_ha,
3037 pm8001_printk(" phy Down and PORT_NOT_ESTABLISHED\n"));
3038 port->port_attached = 0;
3039 break;
3040 case PORT_LOSTCOMM:
3041 PM8001_MSG_DBG(pm8001_ha,
3042 pm8001_printk(" phy Down and PORT_LOSTCOMM\n"));
3043 PM8001_MSG_DBG(pm8001_ha,
3044 pm8001_printk(" Last phy Down and port invalid\n"));
3045 port->port_attached = 0;
3046 pm8001_hw_event_ack_req(pm8001_ha, 0, HW_EVENT_PHY_DOWN,
3047 port_id, phy_id, 0, 0);
3048 break;
3049 default:
3050 port->port_attached = 0;
3051 PM8001_MSG_DBG(pm8001_ha,
3052 pm8001_printk(" phy Down and(default) = %x\n",
3053 portstate));
3054 break;
3055
3056 }
3057}
3058
3059/**
3060 * mpi_reg_resp -process register device ID response.
3061 * @pm8001_ha: our hba card information
3062 * @piomb: IO message buffer
3063 *
3064 * when sas layer find a device it will notify LLDD, then the driver register
3065 * the domain device to FW, this event is the return device ID which the FW
3066 * has assigned, from now,inter-communication with FW is no longer using the
3067 * SAS address, use device ID which FW assigned.
3068 */
3069static int mpi_reg_resp(struct pm8001_hba_info *pm8001_ha, void *piomb)
3070{
3071 u32 status;
3072 u32 device_id;
3073 u32 htag;
3074 struct pm8001_ccb_info *ccb;
3075 struct pm8001_device *pm8001_dev;
3076 struct dev_reg_resp *registerRespPayload =
3077 (struct dev_reg_resp *)(piomb + 4);
3078
3079 htag = le32_to_cpu(registerRespPayload->tag);
3080 ccb = &pm8001_ha->ccb_info[registerRespPayload->tag];
3081 pm8001_dev = ccb->device;
3082 status = le32_to_cpu(registerRespPayload->status);
3083 device_id = le32_to_cpu(registerRespPayload->device_id);
3084 PM8001_MSG_DBG(pm8001_ha,
3085 pm8001_printk(" register device is status = %d\n", status));
3086 switch (status) {
3087 case DEVREG_SUCCESS:
3088 PM8001_MSG_DBG(pm8001_ha, pm8001_printk("DEVREG_SUCCESS\n"));
3089 pm8001_dev->device_id = device_id;
3090 break;
3091 case DEVREG_FAILURE_OUT_OF_RESOURCE:
3092 PM8001_MSG_DBG(pm8001_ha,
3093 pm8001_printk("DEVREG_FAILURE_OUT_OF_RESOURCE\n"));
3094 break;
3095 case DEVREG_FAILURE_DEVICE_ALREADY_REGISTERED:
3096 PM8001_MSG_DBG(pm8001_ha,
3097 pm8001_printk("DEVREG_FAILURE_DEVICE_ALREADY_REGISTERED\n"));
3098 break;
3099 case DEVREG_FAILURE_INVALID_PHY_ID:
3100 PM8001_MSG_DBG(pm8001_ha,
3101 pm8001_printk("DEVREG_FAILURE_INVALID_PHY_ID\n"));
3102 break;
3103 case DEVREG_FAILURE_PHY_ID_ALREADY_REGISTERED:
3104 PM8001_MSG_DBG(pm8001_ha,
3105 pm8001_printk("DEVREG_FAILURE_PHY_ID_ALREADY_REGISTERED\n"));
3106 break;
3107 case DEVREG_FAILURE_PORT_ID_OUT_OF_RANGE:
3108 PM8001_MSG_DBG(pm8001_ha,
3109 pm8001_printk("DEVREG_FAILURE_PORT_ID_OUT_OF_RANGE\n"));
3110 break;
3111 case DEVREG_FAILURE_PORT_NOT_VALID_STATE:
3112 PM8001_MSG_DBG(pm8001_ha,
3113 pm8001_printk("DEVREG_FAILURE_PORT_NOT_VALID_STATE\n"));
3114 break;
3115 case DEVREG_FAILURE_DEVICE_TYPE_NOT_VALID:
3116 PM8001_MSG_DBG(pm8001_ha,
3117 pm8001_printk("DEVREG_FAILURE_DEVICE_TYPE_NOT_VALID\n"));
3118 break;
3119 default:
3120 PM8001_MSG_DBG(pm8001_ha,
3121 pm8001_printk("DEVREG_FAILURE_DEVICE_TYPE_NOT_UNSORPORTED\n"));
3122 break;
3123 }
3124 complete(pm8001_dev->dcompletion);
3125 ccb->task = NULL;
3126 ccb->ccb_tag = 0xFFFFFFFF;
3127 pm8001_ccb_free(pm8001_ha, htag);
3128 return 0;
3129}
3130
3131static int mpi_dereg_resp(struct pm8001_hba_info *pm8001_ha, void *piomb)
3132{
3133 u32 status;
3134 u32 device_id;
3135 struct dev_reg_resp *registerRespPayload =
3136 (struct dev_reg_resp *)(piomb + 4);
3137
3138 status = le32_to_cpu(registerRespPayload->status);
3139 device_id = le32_to_cpu(registerRespPayload->device_id);
3140 if (status != 0)
3141 PM8001_MSG_DBG(pm8001_ha,
3142 pm8001_printk(" deregister device failed ,status = %x"
3143 ", device_id = %x\n", status, device_id));
3144 return 0;
3145}
3146
3147static int
3148mpi_fw_flash_update_resp(struct pm8001_hba_info *pm8001_ha, void *piomb)
3149{
3150 u32 status;
3151 struct fw_control_ex fw_control_context;
3152 struct fw_flash_Update_resp *ppayload =
3153 (struct fw_flash_Update_resp *)(piomb + 4);
3154 u32 tag = le32_to_cpu(ppayload->tag);
3155 struct pm8001_ccb_info *ccb = &pm8001_ha->ccb_info[tag];
3156 status = le32_to_cpu(ppayload->status);
3157 memcpy(&fw_control_context,
3158 ccb->fw_control_context,
3159 sizeof(fw_control_context));
3160 switch (status) {
3161 case FLASH_UPDATE_COMPLETE_PENDING_REBOOT:
3162 PM8001_MSG_DBG(pm8001_ha,
3163 pm8001_printk(": FLASH_UPDATE_COMPLETE_PENDING_REBOOT\n"));
3164 break;
3165 case FLASH_UPDATE_IN_PROGRESS:
3166 PM8001_MSG_DBG(pm8001_ha,
3167 pm8001_printk(": FLASH_UPDATE_IN_PROGRESS\n"));
3168 break;
3169 case FLASH_UPDATE_HDR_ERR:
3170 PM8001_MSG_DBG(pm8001_ha,
3171 pm8001_printk(": FLASH_UPDATE_HDR_ERR\n"));
3172 break;
3173 case FLASH_UPDATE_OFFSET_ERR:
3174 PM8001_MSG_DBG(pm8001_ha,
3175 pm8001_printk(": FLASH_UPDATE_OFFSET_ERR\n"));
3176 break;
3177 case FLASH_UPDATE_CRC_ERR:
3178 PM8001_MSG_DBG(pm8001_ha,
3179 pm8001_printk(": FLASH_UPDATE_CRC_ERR\n"));
3180 break;
3181 case FLASH_UPDATE_LENGTH_ERR:
3182 PM8001_MSG_DBG(pm8001_ha,
3183 pm8001_printk(": FLASH_UPDATE_LENGTH_ERR\n"));
3184 break;
3185 case FLASH_UPDATE_HW_ERR:
3186 PM8001_MSG_DBG(pm8001_ha,
3187 pm8001_printk(": FLASH_UPDATE_HW_ERR\n"));
3188 break;
3189 case FLASH_UPDATE_DNLD_NOT_SUPPORTED:
3190 PM8001_MSG_DBG(pm8001_ha,
3191 pm8001_printk(": FLASH_UPDATE_DNLD_NOT_SUPPORTED\n"));
3192 break;
3193 case FLASH_UPDATE_DISABLED:
3194 PM8001_MSG_DBG(pm8001_ha,
3195 pm8001_printk(": FLASH_UPDATE_DISABLED\n"));
3196 break;
3197 default:
3198 PM8001_MSG_DBG(pm8001_ha,
3199 pm8001_printk("No matched status = %d\n", status));
3200 break;
3201 }
3202 ccb->fw_control_context->fw_control->retcode = status;
3203 pci_free_consistent(pm8001_ha->pdev,
3204 fw_control_context.len,
3205 fw_control_context.virtAddr,
3206 fw_control_context.phys_addr);
3207 complete(pm8001_ha->nvmd_completion);
3208 ccb->task = NULL;
3209 ccb->ccb_tag = 0xFFFFFFFF;
3210 pm8001_ccb_free(pm8001_ha, tag);
3211 return 0;
3212}
3213
3214static int
3215mpi_general_event(struct pm8001_hba_info *pm8001_ha , void *piomb)
3216{
3217 u32 status;
3218 int i;
3219 struct general_event_resp *pPayload =
3220 (struct general_event_resp *)(piomb + 4);
3221 status = le32_to_cpu(pPayload->status);
3222 PM8001_MSG_DBG(pm8001_ha,
3223 pm8001_printk(" status = 0x%x\n", status));
3224 for (i = 0; i < GENERAL_EVENT_PAYLOAD; i++)
3225 PM8001_MSG_DBG(pm8001_ha,
3226 pm8001_printk("inb_IOMB_payload[0x%x] 0x%x, \n", i,
3227 pPayload->inb_IOMB_payload[i]));
3228 return 0;
3229}
3230
3231static int
3232mpi_task_abort_resp(struct pm8001_hba_info *pm8001_ha, void *piomb)
3233{
3234 struct sas_task *t;
3235 struct pm8001_ccb_info *ccb;
3236 unsigned long flags;
3237 u32 status ;
3238 u32 tag, scp;
3239 struct task_status_struct *ts;
3240
3241 struct task_abort_resp *pPayload =
3242 (struct task_abort_resp *)(piomb + 4);
3243 ccb = &pm8001_ha->ccb_info[pPayload->tag];
3244 t = ccb->task;
3245
3246
3247 status = le32_to_cpu(pPayload->status);
3248 tag = le32_to_cpu(pPayload->tag);
3249 scp = le32_to_cpu(pPayload->scp);
3250 PM8001_IO_DBG(pm8001_ha,
3251 pm8001_printk(" status = 0x%x\n", status));
3252 if (t == NULL)
3253 return -1;
3254 ts = &t->task_status;
3255 if (status != 0)
3256 PM8001_FAIL_DBG(pm8001_ha,
3257 pm8001_printk("task abort failed status 0x%x ,"
3258 "tag = 0x%x, scp= 0x%x\n", status, tag, scp));
3259 switch (status) {
3260 case IO_SUCCESS:
3261 PM8001_EH_DBG(pm8001_ha, pm8001_printk("IO_SUCCESS\n"));
3262 ts->resp = SAS_TASK_COMPLETE;
3263 ts->stat = SAM_GOOD;
3264 break;
3265 case IO_NOT_VALID:
3266 PM8001_EH_DBG(pm8001_ha, pm8001_printk("IO_NOT_VALID\n"));
3267 ts->resp = TMF_RESP_FUNC_FAILED;
3268 break;
3269 }
3270 spin_lock_irqsave(&t->task_state_lock, flags);
3271 t->task_state_flags &= ~SAS_TASK_STATE_PENDING;
3272 t->task_state_flags &= ~SAS_TASK_AT_INITIATOR;
3273 t->task_state_flags |= SAS_TASK_STATE_DONE;
3274 spin_unlock_irqrestore(&t->task_state_lock, flags);
3275 pm8001_ccb_task_free(pm8001_ha, t, ccb, pPayload->tag);
3276 mb();
3277 t->task_done(t);
3278 return 0;
3279}
3280
3281/**
3282 * mpi_hw_event -The hw event has come.
3283 * @pm8001_ha: our hba card information
3284 * @piomb: IO message buffer
3285 */
3286static int mpi_hw_event(struct pm8001_hba_info *pm8001_ha, void* piomb)
3287{
3288 unsigned long flags;
3289 struct hw_event_resp *pPayload =
3290 (struct hw_event_resp *)(piomb + 4);
3291 u32 lr_evt_status_phyid_portid =
3292 le32_to_cpu(pPayload->lr_evt_status_phyid_portid);
3293 u8 port_id = (u8)(lr_evt_status_phyid_portid & 0x0000000F);
3294 u8 phy_id =
3295 (u8)((lr_evt_status_phyid_portid & 0x000000F0) >> 4);
3296 u16 eventType =
3297 (u16)((lr_evt_status_phyid_portid & 0x00FFFF00) >> 8);
3298 u8 status =
3299 (u8)((lr_evt_status_phyid_portid & 0x0F000000) >> 24);
3300 struct sas_ha_struct *sas_ha = pm8001_ha->sas;
3301 struct pm8001_phy *phy = &pm8001_ha->phy[phy_id];
3302 struct asd_sas_phy *sas_phy = sas_ha->sas_phy[phy_id];
3303 PM8001_MSG_DBG(pm8001_ha,
3304 pm8001_printk("outbound queue HW event & event type : "));
3305 switch (eventType) {
3306 case HW_EVENT_PHY_START_STATUS:
3307 PM8001_MSG_DBG(pm8001_ha,
3308 pm8001_printk("HW_EVENT_PHY_START_STATUS"
3309 " status = %x\n", status));
3310 if (status == 0) {
3311 phy->phy_state = 1;
3312 if (pm8001_ha->flags == PM8001F_RUN_TIME)
3313 complete(phy->enable_completion);
3314 }
3315 break;
3316 case HW_EVENT_SAS_PHY_UP:
3317 PM8001_MSG_DBG(pm8001_ha,
3318 pm8001_printk("HW_EVENT_PHY_START_STATUS \n"));
3319 hw_event_sas_phy_up(pm8001_ha, piomb);
3320 break;
3321 case HW_EVENT_SATA_PHY_UP:
3322 PM8001_MSG_DBG(pm8001_ha,
3323 pm8001_printk("HW_EVENT_SATA_PHY_UP \n"));
3324 hw_event_sata_phy_up(pm8001_ha, piomb);
3325 break;
3326 case HW_EVENT_PHY_STOP_STATUS:
3327 PM8001_MSG_DBG(pm8001_ha,
3328 pm8001_printk("HW_EVENT_PHY_STOP_STATUS "
3329 "status = %x\n", status));
3330 if (status == 0)
3331 phy->phy_state = 0;
3332 break;
3333 case HW_EVENT_SATA_SPINUP_HOLD:
3334 PM8001_MSG_DBG(pm8001_ha,
3335 pm8001_printk("HW_EVENT_SATA_SPINUP_HOLD \n"));
3336 sas_ha->notify_phy_event(&phy->sas_phy, PHYE_SPINUP_HOLD);
3337 break;
3338 case HW_EVENT_PHY_DOWN:
3339 PM8001_MSG_DBG(pm8001_ha,
3340 pm8001_printk("HW_EVENT_PHY_DOWN \n"));
3341 sas_ha->notify_phy_event(&phy->sas_phy, PHYE_LOSS_OF_SIGNAL);
3342 phy->phy_attached = 0;
3343 phy->phy_state = 0;
3344 hw_event_phy_down(pm8001_ha, piomb);
3345 break;
3346 case HW_EVENT_PORT_INVALID:
3347 PM8001_MSG_DBG(pm8001_ha,
3348 pm8001_printk("HW_EVENT_PORT_INVALID\n"));
3349 sas_phy_disconnected(sas_phy);
3350 phy->phy_attached = 0;
3351 sas_ha->notify_port_event(sas_phy, PORTE_LINK_RESET_ERR);
3352 break;
3353 /* the broadcast change primitive received, tell the LIBSAS this event
3354 to revalidate the sas domain*/
3355 case HW_EVENT_BROADCAST_CHANGE:
3356 PM8001_MSG_DBG(pm8001_ha,
3357 pm8001_printk("HW_EVENT_BROADCAST_CHANGE\n"));
3358 pm8001_hw_event_ack_req(pm8001_ha, 0, HW_EVENT_BROADCAST_CHANGE,
3359 port_id, phy_id, 1, 0);
3360 spin_lock_irqsave(&sas_phy->sas_prim_lock, flags);
3361 sas_phy->sas_prim = HW_EVENT_BROADCAST_CHANGE;
3362 spin_unlock_irqrestore(&sas_phy->sas_prim_lock, flags);
3363 sas_ha->notify_port_event(sas_phy, PORTE_BROADCAST_RCVD);
3364 break;
3365 case HW_EVENT_PHY_ERROR:
3366 PM8001_MSG_DBG(pm8001_ha,
3367 pm8001_printk("HW_EVENT_PHY_ERROR\n"));
3368 sas_phy_disconnected(&phy->sas_phy);
3369 phy->phy_attached = 0;
3370 sas_ha->notify_phy_event(&phy->sas_phy, PHYE_OOB_ERROR);
3371 break;
3372 case HW_EVENT_BROADCAST_EXP:
3373 PM8001_MSG_DBG(pm8001_ha,
3374 pm8001_printk("HW_EVENT_BROADCAST_EXP\n"));
3375 spin_lock_irqsave(&sas_phy->sas_prim_lock, flags);
3376 sas_phy->sas_prim = HW_EVENT_BROADCAST_EXP;
3377 spin_unlock_irqrestore(&sas_phy->sas_prim_lock, flags);
3378 sas_ha->notify_port_event(sas_phy, PORTE_BROADCAST_RCVD);
3379 break;
3380 case HW_EVENT_LINK_ERR_INVALID_DWORD:
3381 PM8001_MSG_DBG(pm8001_ha,
3382 pm8001_printk("HW_EVENT_LINK_ERR_INVALID_DWORD\n"));
3383 pm8001_hw_event_ack_req(pm8001_ha, 0,
3384 HW_EVENT_LINK_ERR_INVALID_DWORD, port_id, phy_id, 0, 0);
3385 sas_phy_disconnected(sas_phy);
3386 phy->phy_attached = 0;
3387 sas_ha->notify_port_event(sas_phy, PORTE_LINK_RESET_ERR);
3388 break;
3389 case HW_EVENT_LINK_ERR_DISPARITY_ERROR:
3390 PM8001_MSG_DBG(pm8001_ha,
3391 pm8001_printk("HW_EVENT_LINK_ERR_DISPARITY_ERROR\n"));
3392 pm8001_hw_event_ack_req(pm8001_ha, 0,
3393 HW_EVENT_LINK_ERR_DISPARITY_ERROR,
3394 port_id, phy_id, 0, 0);
3395 sas_phy_disconnected(sas_phy);
3396 phy->phy_attached = 0;
3397 sas_ha->notify_port_event(sas_phy, PORTE_LINK_RESET_ERR);
3398 break;
3399 case HW_EVENT_LINK_ERR_CODE_VIOLATION:
3400 PM8001_MSG_DBG(pm8001_ha,
3401 pm8001_printk("HW_EVENT_LINK_ERR_CODE_VIOLATION\n"));
3402 pm8001_hw_event_ack_req(pm8001_ha, 0,
3403 HW_EVENT_LINK_ERR_CODE_VIOLATION,
3404 port_id, phy_id, 0, 0);
3405 sas_phy_disconnected(sas_phy);
3406 phy->phy_attached = 0;
3407 sas_ha->notify_port_event(sas_phy, PORTE_LINK_RESET_ERR);
3408 break;
3409 case HW_EVENT_LINK_ERR_LOSS_OF_DWORD_SYNCH:
3410 PM8001_MSG_DBG(pm8001_ha,
3411 pm8001_printk("HW_EVENT_LINK_ERR_LOSS_OF_DWORD_SYNCH\n"));
3412 pm8001_hw_event_ack_req(pm8001_ha, 0,
3413 HW_EVENT_LINK_ERR_LOSS_OF_DWORD_SYNCH,
3414 port_id, phy_id, 0, 0);
3415 sas_phy_disconnected(sas_phy);
3416 phy->phy_attached = 0;
3417 sas_ha->notify_port_event(sas_phy, PORTE_LINK_RESET_ERR);
3418 break;
3419 case HW_EVENT_MALFUNCTION:
3420 PM8001_MSG_DBG(pm8001_ha,
3421 pm8001_printk("HW_EVENT_MALFUNCTION\n"));
3422 break;
3423 case HW_EVENT_BROADCAST_SES:
3424 PM8001_MSG_DBG(pm8001_ha,
3425 pm8001_printk("HW_EVENT_BROADCAST_SES\n"));
3426 spin_lock_irqsave(&sas_phy->sas_prim_lock, flags);
3427 sas_phy->sas_prim = HW_EVENT_BROADCAST_SES;
3428 spin_unlock_irqrestore(&sas_phy->sas_prim_lock, flags);
3429 sas_ha->notify_port_event(sas_phy, PORTE_BROADCAST_RCVD);
3430 break;
3431 case HW_EVENT_INBOUND_CRC_ERROR:
3432 PM8001_MSG_DBG(pm8001_ha,
3433 pm8001_printk("HW_EVENT_INBOUND_CRC_ERROR\n"));
3434 pm8001_hw_event_ack_req(pm8001_ha, 0,
3435 HW_EVENT_INBOUND_CRC_ERROR,
3436 port_id, phy_id, 0, 0);
3437 break;
3438 case HW_EVENT_HARD_RESET_RECEIVED:
3439 PM8001_MSG_DBG(pm8001_ha,
3440 pm8001_printk("HW_EVENT_HARD_RESET_RECEIVED\n"));
3441 sas_ha->notify_port_event(sas_phy, PORTE_HARD_RESET);
3442 break;
3443 case HW_EVENT_ID_FRAME_TIMEOUT:
3444 PM8001_MSG_DBG(pm8001_ha,
3445 pm8001_printk("HW_EVENT_ID_FRAME_TIMEOUT\n"));
3446 sas_phy_disconnected(sas_phy);
3447 phy->phy_attached = 0;
3448 sas_ha->notify_port_event(sas_phy, PORTE_LINK_RESET_ERR);
3449 break;
3450 case HW_EVENT_LINK_ERR_PHY_RESET_FAILED:
3451 PM8001_MSG_DBG(pm8001_ha,
3452 pm8001_printk("HW_EVENT_LINK_ERR_PHY_RESET_FAILED \n"));
3453 pm8001_hw_event_ack_req(pm8001_ha, 0,
3454 HW_EVENT_LINK_ERR_PHY_RESET_FAILED,
3455 port_id, phy_id, 0, 0);
3456 sas_phy_disconnected(sas_phy);
3457 phy->phy_attached = 0;
3458 sas_ha->notify_port_event(sas_phy, PORTE_LINK_RESET_ERR);
3459 break;
3460 case HW_EVENT_PORT_RESET_TIMER_TMO:
3461 PM8001_MSG_DBG(pm8001_ha,
3462 pm8001_printk("HW_EVENT_PORT_RESET_TIMER_TMO \n"));
3463 sas_phy_disconnected(sas_phy);
3464 phy->phy_attached = 0;
3465 sas_ha->notify_port_event(sas_phy, PORTE_LINK_RESET_ERR);
3466 break;
3467 case HW_EVENT_PORT_RECOVERY_TIMER_TMO:
3468 PM8001_MSG_DBG(pm8001_ha,
3469 pm8001_printk("HW_EVENT_PORT_RECOVERY_TIMER_TMO \n"));
3470 sas_phy_disconnected(sas_phy);
3471 phy->phy_attached = 0;
3472 sas_ha->notify_port_event(sas_phy, PORTE_LINK_RESET_ERR);
3473 break;
3474 case HW_EVENT_PORT_RECOVER:
3475 PM8001_MSG_DBG(pm8001_ha,
3476 pm8001_printk("HW_EVENT_PORT_RECOVER \n"));
3477 break;
3478 case HW_EVENT_PORT_RESET_COMPLETE:
3479 PM8001_MSG_DBG(pm8001_ha,
3480 pm8001_printk("HW_EVENT_PORT_RESET_COMPLETE \n"));
3481 break;
3482 case EVENT_BROADCAST_ASYNCH_EVENT:
3483 PM8001_MSG_DBG(pm8001_ha,
3484 pm8001_printk("EVENT_BROADCAST_ASYNCH_EVENT\n"));
3485 break;
3486 default:
3487 PM8001_MSG_DBG(pm8001_ha,
3488 pm8001_printk("Unknown event type = %x\n", eventType));
3489 break;
3490 }
3491 return 0;
3492}
3493
3494/**
3495 * process_one_iomb - process one outbound Queue memory block
3496 * @pm8001_ha: our hba card information
3497 * @piomb: IO message buffer
3498 */
3499static void process_one_iomb(struct pm8001_hba_info *pm8001_ha, void *piomb)
3500{
3501 u32 pHeader = (u32)*(u32 *)piomb;
3502 u8 opc = (u8)((le32_to_cpu(pHeader)) & 0xFFF);
3503
3504 PM8001_MSG_DBG(pm8001_ha, pm8001_printk("process_one_iomb:"));
3505
3506 switch (opc) {
3507 case OPC_OUB_ECHO:
3508 PM8001_MSG_DBG(pm8001_ha, pm8001_printk("OPC_OUB_ECHO \n"));
3509 break;
3510 case OPC_OUB_HW_EVENT:
3511 PM8001_MSG_DBG(pm8001_ha,
3512 pm8001_printk("OPC_OUB_HW_EVENT \n"));
3513 mpi_hw_event(pm8001_ha, piomb);
3514 break;
3515 case OPC_OUB_SSP_COMP:
3516 PM8001_MSG_DBG(pm8001_ha,
3517 pm8001_printk("OPC_OUB_SSP_COMP \n"));
3518 mpi_ssp_completion(pm8001_ha, piomb);
3519 break;
3520 case OPC_OUB_SMP_COMP:
3521 PM8001_MSG_DBG(pm8001_ha,
3522 pm8001_printk("OPC_OUB_SMP_COMP \n"));
3523 mpi_smp_completion(pm8001_ha, piomb);
3524 break;
3525 case OPC_OUB_LOCAL_PHY_CNTRL:
3526 PM8001_MSG_DBG(pm8001_ha,
3527 pm8001_printk("OPC_OUB_LOCAL_PHY_CNTRL\n"));
3528 mpi_local_phy_ctl(pm8001_ha, piomb);
3529 break;
3530 case OPC_OUB_DEV_REGIST:
3531 PM8001_MSG_DBG(pm8001_ha,
3532 pm8001_printk("OPC_OUB_DEV_REGIST \n"));
3533 mpi_reg_resp(pm8001_ha, piomb);
3534 break;
3535 case OPC_OUB_DEREG_DEV:
3536 PM8001_MSG_DBG(pm8001_ha,
3537 pm8001_printk("unresgister the deviece \n"));
3538 mpi_dereg_resp(pm8001_ha, piomb);
3539 break;
3540 case OPC_OUB_GET_DEV_HANDLE:
3541 PM8001_MSG_DBG(pm8001_ha,
3542 pm8001_printk("OPC_OUB_GET_DEV_HANDLE \n"));
3543 break;
3544 case OPC_OUB_SATA_COMP:
3545 PM8001_MSG_DBG(pm8001_ha,
3546 pm8001_printk("OPC_OUB_SATA_COMP \n"));
3547 mpi_sata_completion(pm8001_ha, piomb);
3548 break;
3549 case OPC_OUB_SATA_EVENT:
3550 PM8001_MSG_DBG(pm8001_ha,
3551 pm8001_printk("OPC_OUB_SATA_EVENT \n"));
3552 mpi_sata_event(pm8001_ha, piomb);
3553 break;
3554 case OPC_OUB_SSP_EVENT:
3555 PM8001_MSG_DBG(pm8001_ha,
3556 pm8001_printk("OPC_OUB_SSP_EVENT\n"));
3557 mpi_ssp_event(pm8001_ha, piomb);
3558 break;
3559 case OPC_OUB_DEV_HANDLE_ARRIV:
3560 PM8001_MSG_DBG(pm8001_ha,
3561 pm8001_printk("OPC_OUB_DEV_HANDLE_ARRIV\n"));
3562 /*This is for target*/
3563 break;
3564 case OPC_OUB_SSP_RECV_EVENT:
3565 PM8001_MSG_DBG(pm8001_ha,
3566 pm8001_printk("OPC_OUB_SSP_RECV_EVENT\n"));
3567 /*This is for target*/
3568 break;
3569 case OPC_OUB_DEV_INFO:
3570 PM8001_MSG_DBG(pm8001_ha,
3571 pm8001_printk("OPC_OUB_DEV_INFO\n"));
3572 break;
3573 case OPC_OUB_FW_FLASH_UPDATE:
3574 PM8001_MSG_DBG(pm8001_ha,
3575 pm8001_printk("OPC_OUB_FW_FLASH_UPDATE\n"));
3576 mpi_fw_flash_update_resp(pm8001_ha, piomb);
3577 break;
3578 case OPC_OUB_GPIO_RESPONSE:
3579 PM8001_MSG_DBG(pm8001_ha,
3580 pm8001_printk("OPC_OUB_GPIO_RESPONSE\n"));
3581 break;
3582 case OPC_OUB_GPIO_EVENT:
3583 PM8001_MSG_DBG(pm8001_ha,
3584 pm8001_printk("OPC_OUB_GPIO_EVENT\n"));
3585 break;
3586 case OPC_OUB_GENERAL_EVENT:
3587 PM8001_MSG_DBG(pm8001_ha,
3588 pm8001_printk("OPC_OUB_GENERAL_EVENT\n"));
3589 mpi_general_event(pm8001_ha, piomb);
3590 break;
3591 case OPC_OUB_SSP_ABORT_RSP:
3592 PM8001_MSG_DBG(pm8001_ha,
3593 pm8001_printk("OPC_OUB_SSP_ABORT_RSP\n"));
3594 mpi_task_abort_resp(pm8001_ha, piomb);
3595 break;
3596 case OPC_OUB_SATA_ABORT_RSP:
3597 PM8001_MSG_DBG(pm8001_ha,
3598 pm8001_printk("OPC_OUB_SATA_ABORT_RSP\n"));
3599 mpi_task_abort_resp(pm8001_ha, piomb);
3600 break;
3601 case OPC_OUB_SAS_DIAG_MODE_START_END:
3602 PM8001_MSG_DBG(pm8001_ha,
3603 pm8001_printk("OPC_OUB_SAS_DIAG_MODE_START_END\n"));
3604 break;
3605 case OPC_OUB_SAS_DIAG_EXECUTE:
3606 PM8001_MSG_DBG(pm8001_ha,
3607 pm8001_printk("OPC_OUB_SAS_DIAG_EXECUTE\n"));
3608 break;
3609 case OPC_OUB_GET_TIME_STAMP:
3610 PM8001_MSG_DBG(pm8001_ha,
3611 pm8001_printk("OPC_OUB_GET_TIME_STAMP\n"));
3612 break;
3613 case OPC_OUB_SAS_HW_EVENT_ACK:
3614 PM8001_MSG_DBG(pm8001_ha,
3615 pm8001_printk("OPC_OUB_SAS_HW_EVENT_ACK\n"));
3616 break;
3617 case OPC_OUB_PORT_CONTROL:
3618 PM8001_MSG_DBG(pm8001_ha,
3619 pm8001_printk("OPC_OUB_PORT_CONTROL\n"));
3620 break;
3621 case OPC_OUB_SMP_ABORT_RSP:
3622 PM8001_MSG_DBG(pm8001_ha,
3623 pm8001_printk("OPC_OUB_SMP_ABORT_RSP\n"));
3624 mpi_task_abort_resp(pm8001_ha, piomb);
3625 break;
3626 case OPC_OUB_GET_NVMD_DATA:
3627 PM8001_MSG_DBG(pm8001_ha,
3628 pm8001_printk("OPC_OUB_GET_NVMD_DATA\n"));
3629 mpi_get_nvmd_resp(pm8001_ha, piomb);
3630 break;
3631 case OPC_OUB_SET_NVMD_DATA:
3632 PM8001_MSG_DBG(pm8001_ha,
3633 pm8001_printk("OPC_OUB_SET_NVMD_DATA\n"));
3634 mpi_set_nvmd_resp(pm8001_ha, piomb);
3635 break;
3636 case OPC_OUB_DEVICE_HANDLE_REMOVAL:
3637 PM8001_MSG_DBG(pm8001_ha,
3638 pm8001_printk("OPC_OUB_DEVICE_HANDLE_REMOVAL\n"));
3639 break;
3640 case OPC_OUB_SET_DEVICE_STATE:
3641 PM8001_MSG_DBG(pm8001_ha,
3642 pm8001_printk("OPC_OUB_SET_DEVICE_STATE\n"));
3643 mpi_set_dev_state_resp(pm8001_ha, piomb);
3644 break;
3645 case OPC_OUB_GET_DEVICE_STATE:
3646 PM8001_MSG_DBG(pm8001_ha,
3647 pm8001_printk("OPC_OUB_GET_DEVICE_STATE\n"));
3648 break;
3649 case OPC_OUB_SET_DEV_INFO:
3650 PM8001_MSG_DBG(pm8001_ha,
3651 pm8001_printk("OPC_OUB_SET_DEV_INFO\n"));
3652 break;
3653 case OPC_OUB_SAS_RE_INITIALIZE:
3654 PM8001_MSG_DBG(pm8001_ha,
3655 pm8001_printk("OPC_OUB_SAS_RE_INITIALIZE\n"));
3656 break;
3657 default:
3658 PM8001_MSG_DBG(pm8001_ha,
3659 pm8001_printk("Unknown outbound Queue IOMB OPC = %x\n",
3660 opc));
3661 break;
3662 }
3663}
3664
3665static int process_oq(struct pm8001_hba_info *pm8001_ha)
3666{
3667 struct outbound_queue_table *circularQ;
3668 void *pMsg1 = NULL;
3669 u8 bc = 0;
3670 u32 ret = MPI_IO_STATUS_FAIL;
3671
3672 circularQ = &pm8001_ha->outbnd_q_tbl[0];
3673 do {
3674 ret = mpi_msg_consume(pm8001_ha, circularQ, &pMsg1, &bc);
3675 if (MPI_IO_STATUS_SUCCESS == ret) {
3676 /* process the outbound message */
3677 process_one_iomb(pm8001_ha, (void *)(pMsg1 - 4));
3678 /* free the message from the outbound circular buffer */
3679 mpi_msg_free_set(pm8001_ha, pMsg1, circularQ, bc);
3680 }
3681 if (MPI_IO_STATUS_BUSY == ret) {
3682 u32 producer_idx;
3683 /* Update the producer index from SPC */
3684 producer_idx = pm8001_read_32(circularQ->pi_virt);
3685 circularQ->producer_index = cpu_to_le32(producer_idx);
3686 if (circularQ->producer_index ==
3687 circularQ->consumer_idx)
3688 /* OQ is empty */
3689 break;
3690 }
3691 } while (1);
3692 return ret;
3693}
3694
3695/* PCI_DMA_... to our direction translation. */
3696static const u8 data_dir_flags[] = {
3697 [PCI_DMA_BIDIRECTIONAL] = DATA_DIR_BYRECIPIENT,/* UNSPECIFIED */
3698 [PCI_DMA_TODEVICE] = DATA_DIR_OUT,/* OUTBOUND */
3699 [PCI_DMA_FROMDEVICE] = DATA_DIR_IN,/* INBOUND */
3700 [PCI_DMA_NONE] = DATA_DIR_NONE,/* NO TRANSFER */
3701};
3702static void
3703pm8001_chip_make_sg(struct scatterlist *scatter, int nr, void *prd)
3704{
3705 int i;
3706 struct scatterlist *sg;
3707 struct pm8001_prd *buf_prd = prd;
3708
3709 for_each_sg(scatter, sg, nr, i) {
3710 buf_prd->addr = cpu_to_le64(sg_dma_address(sg));
3711 buf_prd->im_len.len = cpu_to_le32(sg_dma_len(sg));
3712 buf_prd->im_len.e = 0;
3713 buf_prd++;
3714 }
3715}
3716
3717static void build_smp_cmd(u32 deviceID, u32 hTag, struct smp_req *psmp_cmd)
3718{
3719 psmp_cmd->tag = cpu_to_le32(hTag);
3720 psmp_cmd->device_id = cpu_to_le32(deviceID);
3721 psmp_cmd->len_ip_ir = cpu_to_le32(1|(1 << 1));
3722}
3723
3724/**
3725 * pm8001_chip_smp_req - send a SMP task to FW
3726 * @pm8001_ha: our hba card information.
3727 * @ccb: the ccb information this request used.
3728 */
3729static int pm8001_chip_smp_req(struct pm8001_hba_info *pm8001_ha,
3730 struct pm8001_ccb_info *ccb)
3731{
3732 int elem, rc;
3733 struct sas_task *task = ccb->task;
3734 struct domain_device *dev = task->dev;
3735 struct pm8001_device *pm8001_dev = dev->lldd_dev;
3736 struct scatterlist *sg_req, *sg_resp;
3737 u32 req_len, resp_len;
3738 struct smp_req smp_cmd;
3739 u32 opc;
3740 struct inbound_queue_table *circularQ;
3741
3742 memset(&smp_cmd, 0, sizeof(smp_cmd));
3743 /*
3744 * DMA-map SMP request, response buffers
3745 */
3746 sg_req = &task->smp_task.smp_req;
3747 elem = dma_map_sg(pm8001_ha->dev, sg_req, 1, PCI_DMA_TODEVICE);
3748 if (!elem)
3749 return -ENOMEM;
3750 req_len = sg_dma_len(sg_req);
3751
3752 sg_resp = &task->smp_task.smp_resp;
3753 elem = dma_map_sg(pm8001_ha->dev, sg_resp, 1, PCI_DMA_FROMDEVICE);
3754 if (!elem) {
3755 rc = -ENOMEM;
3756 goto err_out;
3757 }
3758 resp_len = sg_dma_len(sg_resp);
3759 /* must be in dwords */
3760 if ((req_len & 0x3) || (resp_len & 0x3)) {
3761 rc = -EINVAL;
3762 goto err_out_2;
3763 }
3764
3765 opc = OPC_INB_SMP_REQUEST;
3766 circularQ = &pm8001_ha->inbnd_q_tbl[0];
3767 smp_cmd.tag = cpu_to_le32(ccb->ccb_tag);
3768 smp_cmd.long_smp_req.long_req_addr =
3769 cpu_to_le64((u64)sg_dma_address(&task->smp_task.smp_req));
3770 smp_cmd.long_smp_req.long_req_size =
3771 cpu_to_le32((u32)sg_dma_len(&task->smp_task.smp_req)-4);
3772 smp_cmd.long_smp_req.long_resp_addr =
3773 cpu_to_le64((u64)sg_dma_address(&task->smp_task.smp_resp));
3774 smp_cmd.long_smp_req.long_resp_size =
3775 cpu_to_le32((u32)sg_dma_len(&task->smp_task.smp_resp)-4);
3776 build_smp_cmd(pm8001_dev->device_id, smp_cmd.tag, &smp_cmd);
3777 mpi_build_cmd(pm8001_ha, circularQ, opc, (u32 *)&smp_cmd);
3778 return 0;
3779
3780err_out_2:
3781 dma_unmap_sg(pm8001_ha->dev, &ccb->task->smp_task.smp_resp, 1,
3782 PCI_DMA_FROMDEVICE);
3783err_out:
3784 dma_unmap_sg(pm8001_ha->dev, &ccb->task->smp_task.smp_req, 1,
3785 PCI_DMA_TODEVICE);
3786 return rc;
3787}
3788
3789/**
3790 * pm8001_chip_ssp_io_req - send a SSP task to FW
3791 * @pm8001_ha: our hba card information.
3792 * @ccb: the ccb information this request used.
3793 */
3794static int pm8001_chip_ssp_io_req(struct pm8001_hba_info *pm8001_ha,
3795 struct pm8001_ccb_info *ccb)
3796{
3797 struct sas_task *task = ccb->task;
3798 struct domain_device *dev = task->dev;
3799 struct pm8001_device *pm8001_dev = dev->lldd_dev;
3800 struct ssp_ini_io_start_req ssp_cmd;
3801 u32 tag = ccb->ccb_tag;
3802 int ret;
3803 __le64 phys_addr;
3804 struct inbound_queue_table *circularQ;
3805 u32 opc = OPC_INB_SSPINIIOSTART;
3806 memset(&ssp_cmd, 0, sizeof(ssp_cmd));
3807 memcpy(ssp_cmd.ssp_iu.lun, task->ssp_task.LUN, 8);
3808 ssp_cmd.dir_m_tlr =
3809 cpu_to_le32(data_dir_flags[task->data_dir] << 8 | 0x0);/*0 for
3810 SAS 1.1 compatible TLR*/
3811 ssp_cmd.data_len = cpu_to_le32(task->total_xfer_len);
3812 ssp_cmd.device_id = cpu_to_le32(pm8001_dev->device_id);
3813 ssp_cmd.tag = cpu_to_le32(tag);
3814 if (task->ssp_task.enable_first_burst)
3815 ssp_cmd.ssp_iu.efb_prio_attr |= 0x80;
3816 ssp_cmd.ssp_iu.efb_prio_attr |= (task->ssp_task.task_prio << 3);
3817 ssp_cmd.ssp_iu.efb_prio_attr |= (task->ssp_task.task_attr & 7);
3818 memcpy(ssp_cmd.ssp_iu.cdb, task->ssp_task.cdb, 16);
3819 circularQ = &pm8001_ha->inbnd_q_tbl[0];
3820
3821 /* fill in PRD (scatter/gather) table, if any */
3822 if (task->num_scatter > 1) {
3823 pm8001_chip_make_sg(task->scatter, ccb->n_elem, ccb->buf_prd);
3824 phys_addr = cpu_to_le64(ccb->ccb_dma_handle +
3825 offsetof(struct pm8001_ccb_info, buf_prd[0]));
3826 ssp_cmd.addr_low = lower_32_bits(phys_addr);
3827 ssp_cmd.addr_high = upper_32_bits(phys_addr);
3828 ssp_cmd.esgl = cpu_to_le32(1<<31);
3829 } else if (task->num_scatter == 1) {
3830 __le64 dma_addr = cpu_to_le64(sg_dma_address(task->scatter));
3831 ssp_cmd.addr_low = lower_32_bits(dma_addr);
3832 ssp_cmd.addr_high = upper_32_bits(dma_addr);
3833 ssp_cmd.len = cpu_to_le32(task->total_xfer_len);
3834 ssp_cmd.esgl = 0;
3835 } else if (task->num_scatter == 0) {
3836 ssp_cmd.addr_low = 0;
3837 ssp_cmd.addr_high = 0;
3838 ssp_cmd.len = cpu_to_le32(task->total_xfer_len);
3839 ssp_cmd.esgl = 0;
3840 }
3841 ret = mpi_build_cmd(pm8001_ha, circularQ, opc, &ssp_cmd);
3842 return ret;
3843}
3844
3845static int pm8001_chip_sata_req(struct pm8001_hba_info *pm8001_ha,
3846 struct pm8001_ccb_info *ccb)
3847{
3848 struct sas_task *task = ccb->task;
3849 struct domain_device *dev = task->dev;
3850 struct pm8001_device *pm8001_ha_dev = dev->lldd_dev;
3851 u32 tag = ccb->ccb_tag;
3852 int ret;
3853 struct sata_start_req sata_cmd;
3854 u32 hdr_tag, ncg_tag = 0;
3855 __le64 phys_addr;
3856 u32 ATAP = 0x0;
3857 u32 dir;
3858 struct inbound_queue_table *circularQ;
3859 u32 opc = OPC_INB_SATA_HOST_OPSTART;
3860 memset(&sata_cmd, 0, sizeof(sata_cmd));
3861 circularQ = &pm8001_ha->inbnd_q_tbl[0];
3862 if (task->data_dir == PCI_DMA_NONE) {
3863 ATAP = 0x04; /* no data*/
3864 PM8001_IO_DBG(pm8001_ha, pm8001_printk("no data \n"));
3865 } else if (likely(!task->ata_task.device_control_reg_update)) {
3866 if (task->ata_task.dma_xfer) {
3867 ATAP = 0x06; /* DMA */
3868 PM8001_IO_DBG(pm8001_ha, pm8001_printk("DMA \n"));
3869 } else {
3870 ATAP = 0x05; /* PIO*/
3871 PM8001_IO_DBG(pm8001_ha, pm8001_printk("PIO \n"));
3872 }
3873 if (task->ata_task.use_ncq &&
3874 dev->sata_dev.command_set != ATAPI_COMMAND_SET) {
3875 ATAP = 0x07; /* FPDMA */
3876 PM8001_IO_DBG(pm8001_ha, pm8001_printk("FPDMA \n"));
3877 }
3878 }
3879 if (task->ata_task.use_ncq && pm8001_get_ncq_tag(task, &hdr_tag))
3880 ncg_tag = hdr_tag;
3881 dir = data_dir_flags[task->data_dir] << 8;
3882 sata_cmd.tag = cpu_to_le32(tag);
3883 sata_cmd.device_id = cpu_to_le32(pm8001_ha_dev->device_id);
3884 sata_cmd.data_len = cpu_to_le32(task->total_xfer_len);
3885 sata_cmd.ncqtag_atap_dir_m =
3886 cpu_to_le32(((ncg_tag & 0xff)<<16)|((ATAP & 0x3f) << 10) | dir);
3887 sata_cmd.sata_fis = task->ata_task.fis;
3888 if (likely(!task->ata_task.device_control_reg_update))
3889 sata_cmd.sata_fis.flags |= 0x80;/* C=1: update ATA cmd reg */
3890 sata_cmd.sata_fis.flags &= 0xF0;/* PM_PORT field shall be 0 */
3891 /* fill in PRD (scatter/gather) table, if any */
3892 if (task->num_scatter > 1) {
3893 pm8001_chip_make_sg(task->scatter, ccb->n_elem, ccb->buf_prd);
3894 phys_addr = cpu_to_le64(ccb->ccb_dma_handle +
3895 offsetof(struct pm8001_ccb_info, buf_prd[0]));
3896 sata_cmd.addr_low = lower_32_bits(phys_addr);
3897 sata_cmd.addr_high = upper_32_bits(phys_addr);
3898 sata_cmd.esgl = cpu_to_le32(1 << 31);
3899 } else if (task->num_scatter == 1) {
3900 __le64 dma_addr = cpu_to_le64(sg_dma_address(task->scatter));
3901 sata_cmd.addr_low = lower_32_bits(dma_addr);
3902 sata_cmd.addr_high = upper_32_bits(dma_addr);
3903 sata_cmd.len = cpu_to_le32(task->total_xfer_len);
3904 sata_cmd.esgl = 0;
3905 } else if (task->num_scatter == 0) {
3906 sata_cmd.addr_low = 0;
3907 sata_cmd.addr_high = 0;
3908 sata_cmd.len = cpu_to_le32(task->total_xfer_len);
3909 sata_cmd.esgl = 0;
3910 }
3911 ret = mpi_build_cmd(pm8001_ha, circularQ, opc, &sata_cmd);
3912 return ret;
3913}
3914
3915/**
3916 * pm8001_chip_phy_start_req - start phy via PHY_START COMMAND
3917 * @pm8001_ha: our hba card information.
3918 * @num: the inbound queue number
3919 * @phy_id: the phy id which we wanted to start up.
3920 */
3921static int
3922pm8001_chip_phy_start_req(struct pm8001_hba_info *pm8001_ha, u8 phy_id)
3923{
3924 struct phy_start_req payload;
3925 struct inbound_queue_table *circularQ;
3926 int ret;
3927 u32 tag = 0x01;
3928 u32 opcode = OPC_INB_PHYSTART;
3929 circularQ = &pm8001_ha->inbnd_q_tbl[0];
3930 memset(&payload, 0, sizeof(payload));
3931 payload.tag = cpu_to_le32(tag);
3932 /*
3933 ** [0:7] PHY Identifier
3934 ** [8:11] link rate 1.5G, 3G, 6G
3935 ** [12:13] link mode 01b SAS mode; 10b SATA mode; 11b both
3936 ** [14] 0b disable spin up hold; 1b enable spin up hold
3937 */
3938 payload.ase_sh_lm_slr_phyid = cpu_to_le32(SPINHOLD_DISABLE |
3939 LINKMODE_AUTO | LINKRATE_15 |
3940 LINKRATE_30 | LINKRATE_60 | phy_id);
3941 payload.sas_identify.dev_type = SAS_END_DEV;
3942 payload.sas_identify.initiator_bits = SAS_PROTOCOL_ALL;
3943 memcpy(payload.sas_identify.sas_addr,
3944 pm8001_ha->sas_addr, SAS_ADDR_SIZE);
3945 payload.sas_identify.phy_id = phy_id;
3946 ret = mpi_build_cmd(pm8001_ha, circularQ, opcode, &payload);
3947 return ret;
3948}
3949
3950/**
3951 * pm8001_chip_phy_stop_req - start phy via PHY_STOP COMMAND
3952 * @pm8001_ha: our hba card information.
3953 * @num: the inbound queue number
3954 * @phy_id: the phy id which we wanted to start up.
3955 */
3956static int pm8001_chip_phy_stop_req(struct pm8001_hba_info *pm8001_ha,
3957 u8 phy_id)
3958{
3959 struct phy_stop_req payload;
3960 struct inbound_queue_table *circularQ;
3961 int ret;
3962 u32 tag = 0x01;
3963 u32 opcode = OPC_INB_PHYSTOP;
3964 circularQ = &pm8001_ha->inbnd_q_tbl[0];
3965 memset(&payload, 0, sizeof(payload));
3966 payload.tag = cpu_to_le32(tag);
3967 payload.phy_id = cpu_to_le32(phy_id);
3968 ret = mpi_build_cmd(pm8001_ha, circularQ, opcode, &payload);
3969 return ret;
3970}
3971
3972/**
3973 * see comments on mpi_reg_resp.
3974 */
3975static int pm8001_chip_reg_dev_req(struct pm8001_hba_info *pm8001_ha,
3976 struct pm8001_device *pm8001_dev, u32 flag)
3977{
3978 struct reg_dev_req payload;
3979 u32 opc;
3980 u32 stp_sspsmp_sata = 0x4;
3981 struct inbound_queue_table *circularQ;
3982 u32 linkrate, phy_id;
3983 int rc, tag = 0xdeadbeef;
3984 struct pm8001_ccb_info *ccb;
3985 u8 retryFlag = 0x1;
3986 u16 firstBurstSize = 0;
3987 u16 ITNT = 2000;
3988 struct domain_device *dev = pm8001_dev->sas_device;
3989 struct domain_device *parent_dev = dev->parent;
3990 circularQ = &pm8001_ha->inbnd_q_tbl[0];
3991
3992 memset(&payload, 0, sizeof(payload));
3993 rc = pm8001_tag_alloc(pm8001_ha, &tag);
3994 if (rc)
3995 return rc;
3996 ccb = &pm8001_ha->ccb_info[tag];
3997 ccb->device = pm8001_dev;
3998 ccb->ccb_tag = tag;
3999 payload.tag = cpu_to_le32(tag);
4000 if (flag == 1)
4001 stp_sspsmp_sata = 0x02; /*direct attached sata */
4002 else {
4003 if (pm8001_dev->dev_type == SATA_DEV)
4004 stp_sspsmp_sata = 0x00; /* stp*/
4005 else if (pm8001_dev->dev_type == SAS_END_DEV ||
4006 pm8001_dev->dev_type == EDGE_DEV ||
4007 pm8001_dev->dev_type == FANOUT_DEV)
4008 stp_sspsmp_sata = 0x01; /*ssp or smp*/
4009 }
4010 if (parent_dev && DEV_IS_EXPANDER(parent_dev->dev_type))
4011 phy_id = parent_dev->ex_dev.ex_phy->phy_id;
4012 else
4013 phy_id = pm8001_dev->attached_phy;
4014 opc = OPC_INB_REG_DEV;
4015 linkrate = (pm8001_dev->sas_device->linkrate < dev->port->linkrate) ?
4016 pm8001_dev->sas_device->linkrate : dev->port->linkrate;
4017 payload.phyid_portid =
4018 cpu_to_le32(((pm8001_dev->sas_device->port->id) & 0x0F) |
4019 ((phy_id & 0x0F) << 4));
4020 payload.dtype_dlr_retry = cpu_to_le32((retryFlag & 0x01) |
4021 ((linkrate & 0x0F) * 0x1000000) |
4022 ((stp_sspsmp_sata & 0x03) * 0x10000000));
4023 payload.firstburstsize_ITNexustimeout =
4024 cpu_to_le32(ITNT | (firstBurstSize * 0x10000));
4025 memcpy(payload.sas_addr, pm8001_dev->sas_device->sas_addr,
4026 SAS_ADDR_SIZE);
4027 rc = mpi_build_cmd(pm8001_ha, circularQ, opc, &payload);
4028 return rc;
4029}
4030
4031/**
4032 * see comments on mpi_reg_resp.
4033 */
4034static int pm8001_chip_dereg_dev_req(struct pm8001_hba_info *pm8001_ha,
4035 u32 device_id)
4036{
4037 struct dereg_dev_req payload;
4038 u32 opc = OPC_INB_DEREG_DEV_HANDLE;
4039 int ret;
4040 struct inbound_queue_table *circularQ;
4041
4042 circularQ = &pm8001_ha->inbnd_q_tbl[0];
4043 memset(&payload, 0, sizeof(payload));
4044 payload.tag = 1;
4045 payload.device_id = cpu_to_le32(device_id);
4046 PM8001_MSG_DBG(pm8001_ha,
4047 pm8001_printk("unregister device device_id = %d\n", device_id));
4048 ret = mpi_build_cmd(pm8001_ha, circularQ, opc, &payload);
4049 return ret;
4050}
4051
4052/**
4053 * pm8001_chip_phy_ctl_req - support the local phy operation
4054 * @pm8001_ha: our hba card information.
4055 * @num: the inbound queue number
4056 * @phy_id: the phy id which we wanted to operate
4057 * @phy_op:
4058 */
4059static int pm8001_chip_phy_ctl_req(struct pm8001_hba_info *pm8001_ha,
4060 u32 phyId, u32 phy_op)
4061{
4062 struct local_phy_ctl_req payload;
4063 struct inbound_queue_table *circularQ;
4064 int ret;
4065 u32 opc = OPC_INB_LOCAL_PHY_CONTROL;
4066 memset(&payload, 0, sizeof(payload));
4067 circularQ = &pm8001_ha->inbnd_q_tbl[0];
4068 payload.tag = 1;
4069 payload.phyop_phyid =
4070 cpu_to_le32(((phy_op & 0xff) << 8) | (phyId & 0x0F));
4071 ret = mpi_build_cmd(pm8001_ha, circularQ, opc, &payload);
4072 return ret;
4073}
4074
4075static u32 pm8001_chip_is_our_interupt(struct pm8001_hba_info *pm8001_ha)
4076{
4077 u32 value;
4078#ifdef PM8001_USE_MSIX
4079 return 1;
4080#endif
4081 value = pm8001_cr32(pm8001_ha, 0, MSGU_ODR);
4082 if (value)
4083 return 1;
4084 return 0;
4085
4086}
4087
4088/**
4089 * pm8001_chip_isr - PM8001 isr handler.
4090 * @pm8001_ha: our hba card information.
4091 * @irq: irq number.
4092 * @stat: stat.
4093 */
4094static irqreturn_t
4095pm8001_chip_isr(struct pm8001_hba_info *pm8001_ha)
4096{
4097 unsigned long flags;
4098 spin_lock_irqsave(&pm8001_ha->lock, flags);
4099 pm8001_chip_interrupt_disable(pm8001_ha);
4100 process_oq(pm8001_ha);
4101 pm8001_chip_interrupt_enable(pm8001_ha);
4102 spin_unlock_irqrestore(&pm8001_ha->lock, flags);
4103 return IRQ_HANDLED;
4104}
4105
4106static int send_task_abort(struct pm8001_hba_info *pm8001_ha, u32 opc,
4107 u32 dev_id, u8 flag, u32 task_tag, u32 cmd_tag)
4108{
4109 struct task_abort_req task_abort;
4110 struct inbound_queue_table *circularQ;
4111 int ret;
4112 circularQ = &pm8001_ha->inbnd_q_tbl[0];
4113 memset(&task_abort, 0, sizeof(task_abort));
4114 if (ABORT_SINGLE == (flag & ABORT_MASK)) {
4115 task_abort.abort_all = 0;
4116 task_abort.device_id = cpu_to_le32(dev_id);
4117 task_abort.tag_to_abort = cpu_to_le32(task_tag);
4118 task_abort.tag = cpu_to_le32(cmd_tag);
4119 } else if (ABORT_ALL == (flag & ABORT_MASK)) {
4120 task_abort.abort_all = cpu_to_le32(1);
4121 task_abort.device_id = cpu_to_le32(dev_id);
4122 task_abort.tag = cpu_to_le32(cmd_tag);
4123 }
4124 ret = mpi_build_cmd(pm8001_ha, circularQ, opc, &task_abort);
4125 return ret;
4126}
4127
4128/**
4129 * pm8001_chip_abort_task - SAS abort task when error or exception happened.
4130 * @task: the task we wanted to aborted.
4131 * @flag: the abort flag.
4132 */
4133static int pm8001_chip_abort_task(struct pm8001_hba_info *pm8001_ha,
4134 struct pm8001_device *pm8001_dev, u8 flag, u32 task_tag, u32 cmd_tag)
4135{
4136 u32 opc, device_id;
4137 int rc = TMF_RESP_FUNC_FAILED;
4138 PM8001_EH_DBG(pm8001_ha, pm8001_printk("cmd_tag = %x, abort task tag"
4139 " = %x", cmd_tag, task_tag));
4140 if (pm8001_dev->dev_type == SAS_END_DEV)
4141 opc = OPC_INB_SSP_ABORT;
4142 else if (pm8001_dev->dev_type == SATA_DEV)
4143 opc = OPC_INB_SATA_ABORT;
4144 else
4145 opc = OPC_INB_SMP_ABORT;/* SMP */
4146 device_id = pm8001_dev->device_id;
4147 rc = send_task_abort(pm8001_ha, opc, device_id, flag,
4148 task_tag, cmd_tag);
4149 if (rc != TMF_RESP_FUNC_COMPLETE)
4150 PM8001_EH_DBG(pm8001_ha, pm8001_printk("rc= %d\n", rc));
4151 return rc;
4152}
4153
4154/**
4155 * pm8001_chip_ssp_tm_req - built the task managment command.
4156 * @pm8001_ha: our hba card information.
4157 * @ccb: the ccb information.
4158 * @tmf: task management function.
4159 */
4160static int pm8001_chip_ssp_tm_req(struct pm8001_hba_info *pm8001_ha,
4161 struct pm8001_ccb_info *ccb, struct pm8001_tmf_task *tmf)
4162{
4163 struct sas_task *task = ccb->task;
4164 struct domain_device *dev = task->dev;
4165 struct pm8001_device *pm8001_dev = dev->lldd_dev;
4166 u32 opc = OPC_INB_SSPINITMSTART;
4167 struct inbound_queue_table *circularQ;
4168 struct ssp_ini_tm_start_req sspTMCmd;
4169 int ret;
4170
4171 memset(&sspTMCmd, 0, sizeof(sspTMCmd));
4172 sspTMCmd.device_id = cpu_to_le32(pm8001_dev->device_id);
4173 sspTMCmd.relate_tag = cpu_to_le32(tmf->tag_of_task_to_be_managed);
4174 sspTMCmd.tmf = cpu_to_le32(tmf->tmf);
4175 memcpy(sspTMCmd.lun, task->ssp_task.LUN, 8);
4176 sspTMCmd.tag = cpu_to_le32(ccb->ccb_tag);
4177 circularQ = &pm8001_ha->inbnd_q_tbl[0];
4178 ret = mpi_build_cmd(pm8001_ha, circularQ, opc, &sspTMCmd);
4179 return ret;
4180}
4181
4182static int pm8001_chip_get_nvmd_req(struct pm8001_hba_info *pm8001_ha,
4183 void *payload)
4184{
4185 u32 opc = OPC_INB_GET_NVMD_DATA;
4186 u32 nvmd_type;
4187 int rc;
4188 u32 tag;
4189 struct pm8001_ccb_info *ccb;
4190 struct inbound_queue_table *circularQ;
4191 struct get_nvm_data_req nvmd_req;
4192 struct fw_control_ex *fw_control_context;
4193 struct pm8001_ioctl_payload *ioctl_payload = payload;
4194
4195 nvmd_type = ioctl_payload->minor_function;
4196 fw_control_context = kzalloc(sizeof(struct fw_control_ex), GFP_KERNEL);
4197 fw_control_context->usrAddr = (u8 *)&ioctl_payload->func_specific[0];
4198 fw_control_context->len = ioctl_payload->length;
4199 circularQ = &pm8001_ha->inbnd_q_tbl[0];
4200 memset(&nvmd_req, 0, sizeof(nvmd_req));
4201 rc = pm8001_tag_alloc(pm8001_ha, &tag);
4202 if (rc)
4203 return rc;
4204 ccb = &pm8001_ha->ccb_info[tag];
4205 ccb->ccb_tag = tag;
4206 ccb->fw_control_context = fw_control_context;
4207 nvmd_req.tag = cpu_to_le32(tag);
4208
4209 switch (nvmd_type) {
4210 case TWI_DEVICE: {
4211 u32 twi_addr, twi_page_size;
4212 twi_addr = 0xa8;
4213 twi_page_size = 2;
4214
4215 nvmd_req.len_ir_vpdd = cpu_to_le32(IPMode | twi_addr << 16 |
4216 twi_page_size << 8 | TWI_DEVICE);
4217 nvmd_req.resp_len = cpu_to_le32(ioctl_payload->length);
4218 nvmd_req.resp_addr_hi =
4219 cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_hi);
4220 nvmd_req.resp_addr_lo =
4221 cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_lo);
4222 break;
4223 }
4224 case C_SEEPROM: {
4225 nvmd_req.len_ir_vpdd = cpu_to_le32(IPMode | C_SEEPROM);
4226 nvmd_req.resp_len = cpu_to_le32(ioctl_payload->length);
4227 nvmd_req.resp_addr_hi =
4228 cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_hi);
4229 nvmd_req.resp_addr_lo =
4230 cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_lo);
4231 break;
4232 }
4233 case VPD_FLASH: {
4234 nvmd_req.len_ir_vpdd = cpu_to_le32(IPMode | VPD_FLASH);
4235 nvmd_req.resp_len = cpu_to_le32(ioctl_payload->length);
4236 nvmd_req.resp_addr_hi =
4237 cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_hi);
4238 nvmd_req.resp_addr_lo =
4239 cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_lo);
4240 break;
4241 }
4242 case EXPAN_ROM: {
4243 nvmd_req.len_ir_vpdd = cpu_to_le32(IPMode | EXPAN_ROM);
4244 nvmd_req.resp_len = cpu_to_le32(ioctl_payload->length);
4245 nvmd_req.resp_addr_hi =
4246 cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_hi);
4247 nvmd_req.resp_addr_lo =
4248 cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_lo);
4249 break;
4250 }
4251 default:
4252 break;
4253 }
4254 rc = mpi_build_cmd(pm8001_ha, circularQ, opc, &nvmd_req);
4255 return rc;
4256}
4257
4258static int pm8001_chip_set_nvmd_req(struct pm8001_hba_info *pm8001_ha,
4259 void *payload)
4260{
4261 u32 opc = OPC_INB_SET_NVMD_DATA;
4262 u32 nvmd_type;
4263 int rc;
4264 u32 tag;
4265 struct pm8001_ccb_info *ccb;
4266 struct inbound_queue_table *circularQ;
4267 struct set_nvm_data_req nvmd_req;
4268 struct fw_control_ex *fw_control_context;
4269 struct pm8001_ioctl_payload *ioctl_payload = payload;
4270
4271 nvmd_type = ioctl_payload->minor_function;
4272 fw_control_context = kzalloc(sizeof(struct fw_control_ex), GFP_KERNEL);
4273 circularQ = &pm8001_ha->inbnd_q_tbl[0];
4274 memcpy(pm8001_ha->memoryMap.region[NVMD].virt_ptr,
4275 ioctl_payload->func_specific,
4276 ioctl_payload->length);
4277 memset(&nvmd_req, 0, sizeof(nvmd_req));
4278 rc = pm8001_tag_alloc(pm8001_ha, &tag);
4279 if (rc)
4280 return rc;
4281 ccb = &pm8001_ha->ccb_info[tag];
4282 ccb->fw_control_context = fw_control_context;
4283 ccb->ccb_tag = tag;
4284 nvmd_req.tag = cpu_to_le32(tag);
4285 switch (nvmd_type) {
4286 case TWI_DEVICE: {
4287 u32 twi_addr, twi_page_size;
4288 twi_addr = 0xa8;
4289 twi_page_size = 2;
4290 nvmd_req.reserved[0] = cpu_to_le32(0xFEDCBA98);
4291 nvmd_req.len_ir_vpdd = cpu_to_le32(IPMode | twi_addr << 16 |
4292 twi_page_size << 8 | TWI_DEVICE);
4293 nvmd_req.resp_len = cpu_to_le32(ioctl_payload->length);
4294 nvmd_req.resp_addr_hi =
4295 cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_hi);
4296 nvmd_req.resp_addr_lo =
4297 cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_lo);
4298 break;
4299 }
4300 case C_SEEPROM:
4301 nvmd_req.len_ir_vpdd = cpu_to_le32(IPMode | C_SEEPROM);
4302 nvmd_req.resp_len = cpu_to_le32(ioctl_payload->length);
4303 nvmd_req.reserved[0] = cpu_to_le32(0xFEDCBA98);
4304 nvmd_req.resp_addr_hi =
4305 cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_hi);
4306 nvmd_req.resp_addr_lo =
4307 cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_lo);
4308 break;
4309 case VPD_FLASH:
4310 nvmd_req.len_ir_vpdd = cpu_to_le32(IPMode | VPD_FLASH);
4311 nvmd_req.resp_len = cpu_to_le32(ioctl_payload->length);
4312 nvmd_req.reserved[0] = cpu_to_le32(0xFEDCBA98);
4313 nvmd_req.resp_addr_hi =
4314 cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_hi);
4315 nvmd_req.resp_addr_lo =
4316 cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_lo);
4317 break;
4318 case EXPAN_ROM:
4319 nvmd_req.len_ir_vpdd = cpu_to_le32(IPMode | EXPAN_ROM);
4320 nvmd_req.resp_len = cpu_to_le32(ioctl_payload->length);
4321 nvmd_req.reserved[0] = cpu_to_le32(0xFEDCBA98);
4322 nvmd_req.resp_addr_hi =
4323 cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_hi);
4324 nvmd_req.resp_addr_lo =
4325 cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_lo);
4326 break;
4327 default:
4328 break;
4329 }
4330 rc = mpi_build_cmd(pm8001_ha, circularQ, opc, &nvmd_req);
4331 return rc;
4332}
4333
4334/**
4335 * pm8001_chip_fw_flash_update_build - support the firmware update operation
4336 * @pm8001_ha: our hba card information.
4337 * @fw_flash_updata_info: firmware flash update param
4338 */
4339static int
4340pm8001_chip_fw_flash_update_build(struct pm8001_hba_info *pm8001_ha,
4341 void *fw_flash_updata_info, u32 tag)
4342{
4343 struct fw_flash_Update_req payload;
4344 struct fw_flash_updata_info *info;
4345 struct inbound_queue_table *circularQ;
4346 int ret;
4347 u32 opc = OPC_INB_FW_FLASH_UPDATE;
4348
4349 memset(&payload, 0, sizeof(struct fw_flash_Update_req));
4350 circularQ = &pm8001_ha->inbnd_q_tbl[0];
4351 info = fw_flash_updata_info;
4352 payload.tag = cpu_to_le32(tag);
4353 payload.cur_image_len = cpu_to_le32(info->cur_image_len);
4354 payload.cur_image_offset = cpu_to_le32(info->cur_image_offset);
4355 payload.total_image_len = cpu_to_le32(info->total_image_len);
4356 payload.len = info->sgl.im_len.len ;
4357 payload.sgl_addr_lo = lower_32_bits(info->sgl.addr);
4358 payload.sgl_addr_hi = upper_32_bits(info->sgl.addr);
4359 ret = mpi_build_cmd(pm8001_ha, circularQ, opc, &payload);
4360 return ret;
4361}
4362
4363static int
4364pm8001_chip_fw_flash_update_req(struct pm8001_hba_info *pm8001_ha,
4365 void *payload)
4366{
4367 struct fw_flash_updata_info flash_update_info;
4368 struct fw_control_info *fw_control;
4369 struct fw_control_ex *fw_control_context;
4370 int rc;
4371 u32 tag;
4372 struct pm8001_ccb_info *ccb;
4373 void *buffer = NULL;
4374 dma_addr_t phys_addr;
4375 u32 phys_addr_hi;
4376 u32 phys_addr_lo;
4377 struct pm8001_ioctl_payload *ioctl_payload = payload;
4378
4379 fw_control_context = kzalloc(sizeof(struct fw_control_ex), GFP_KERNEL);
4380 fw_control = (struct fw_control_info *)&ioctl_payload->func_specific[0];
4381 if (fw_control->len != 0) {
4382 if (pm8001_mem_alloc(pm8001_ha->pdev,
4383 (void **)&buffer,
4384 &phys_addr,
4385 &phys_addr_hi,
4386 &phys_addr_lo,
4387 fw_control->len, 0) != 0) {
4388 PM8001_FAIL_DBG(pm8001_ha,
4389 pm8001_printk("Mem alloc failure\n"));
4390 return -ENOMEM;
4391 }
4392 }
4393 memset(buffer, 0, fw_control->len);
4394 memcpy(buffer, fw_control->buffer, fw_control->len);
4395 flash_update_info.sgl.addr = cpu_to_le64(phys_addr);
4396 flash_update_info.sgl.im_len.len = cpu_to_le32(fw_control->len);
4397 flash_update_info.sgl.im_len.e = 0;
4398 flash_update_info.cur_image_offset = fw_control->offset;
4399 flash_update_info.cur_image_len = fw_control->len;
4400 flash_update_info.total_image_len = fw_control->size;
4401 fw_control_context->fw_control = fw_control;
4402 fw_control_context->virtAddr = buffer;
4403 fw_control_context->len = fw_control->len;
4404 rc = pm8001_tag_alloc(pm8001_ha, &tag);
4405 if (rc)
4406 return rc;
4407 ccb = &pm8001_ha->ccb_info[tag];
4408 ccb->fw_control_context = fw_control_context;
4409 ccb->ccb_tag = tag;
4410 rc = pm8001_chip_fw_flash_update_build(pm8001_ha, &flash_update_info,
4411 tag);
4412 return rc;
4413}
4414
4415static int
4416pm8001_chip_set_dev_state_req(struct pm8001_hba_info *pm8001_ha,
4417 struct pm8001_device *pm8001_dev, u32 state)
4418{
4419 struct set_dev_state_req payload;
4420 struct inbound_queue_table *circularQ;
4421 struct pm8001_ccb_info *ccb;
4422 int rc;
4423 u32 tag;
4424 u32 opc = OPC_INB_SET_DEVICE_STATE;
4425 memset(&payload, 0, sizeof(payload));
4426 rc = pm8001_tag_alloc(pm8001_ha, &tag);
4427 if (rc)
4428 return -1;
4429 ccb = &pm8001_ha->ccb_info[tag];
4430 ccb->ccb_tag = tag;
4431 ccb->device = pm8001_dev;
4432 circularQ = &pm8001_ha->inbnd_q_tbl[0];
4433 payload.tag = cpu_to_le32(tag);
4434 payload.device_id = cpu_to_le32(pm8001_dev->device_id);
4435 payload.nds = cpu_to_le32(state);
4436 rc = mpi_build_cmd(pm8001_ha, circularQ, opc, &payload);
4437 return rc;
4438
4439}
4440
4441static int
4442pm8001_chip_sas_re_initialization(struct pm8001_hba_info *pm8001_ha)
4443{
4444 struct sas_re_initialization_req payload;
4445 struct inbound_queue_table *circularQ;
4446 struct pm8001_ccb_info *ccb;
4447 int rc;
4448 u32 tag;
4449 u32 opc = OPC_INB_SAS_RE_INITIALIZE;
4450 memset(&payload, 0, sizeof(payload));
4451 rc = pm8001_tag_alloc(pm8001_ha, &tag);
4452 if (rc)
4453 return -1;
4454 ccb = &pm8001_ha->ccb_info[tag];
4455 ccb->ccb_tag = tag;
4456 circularQ = &pm8001_ha->inbnd_q_tbl[0];
4457 payload.tag = cpu_to_le32(tag);
4458 payload.SSAHOLT = cpu_to_le32(0xd << 25);
4459 payload.sata_hol_tmo = cpu_to_le32(80);
4460 payload.open_reject_cmdretries_data_retries = cpu_to_le32(0xff00ff);
4461 rc = mpi_build_cmd(pm8001_ha, circularQ, opc, &payload);
4462 return rc;
4463
4464}
4465
4466const struct pm8001_dispatch pm8001_8001_dispatch = {
4467 .name = "pmc8001",
4468 .chip_init = pm8001_chip_init,
4469 .chip_soft_rst = pm8001_chip_soft_rst,
4470 .chip_rst = pm8001_hw_chip_rst,
4471 .chip_iounmap = pm8001_chip_iounmap,
4472 .isr = pm8001_chip_isr,
4473 .is_our_interupt = pm8001_chip_is_our_interupt,
4474 .isr_process_oq = process_oq,
4475 .interrupt_enable = pm8001_chip_interrupt_enable,
4476 .interrupt_disable = pm8001_chip_interrupt_disable,
4477 .make_prd = pm8001_chip_make_sg,
4478 .smp_req = pm8001_chip_smp_req,
4479 .ssp_io_req = pm8001_chip_ssp_io_req,
4480 .sata_req = pm8001_chip_sata_req,
4481 .phy_start_req = pm8001_chip_phy_start_req,
4482 .phy_stop_req = pm8001_chip_phy_stop_req,
4483 .reg_dev_req = pm8001_chip_reg_dev_req,
4484 .dereg_dev_req = pm8001_chip_dereg_dev_req,
4485 .phy_ctl_req = pm8001_chip_phy_ctl_req,
4486 .task_abort = pm8001_chip_abort_task,
4487 .ssp_tm_req = pm8001_chip_ssp_tm_req,
4488 .get_nvmd_req = pm8001_chip_get_nvmd_req,
4489 .set_nvmd_req = pm8001_chip_set_nvmd_req,
4490 .fw_flash_update_req = pm8001_chip_fw_flash_update_req,
4491 .set_dev_state_req = pm8001_chip_set_dev_state_req,
4492 .sas_re_init_req = pm8001_chip_sas_re_initialization,
4493};
4494
diff --git a/drivers/scsi/pm8001/pm8001_hwi.h b/drivers/scsi/pm8001/pm8001_hwi.h
new file mode 100644
index 000000000000..833a5201eda4
--- /dev/null
+++ b/drivers/scsi/pm8001/pm8001_hwi.h
@@ -0,0 +1,1029 @@
1/*
2 * PMC-Sierra SPC 8001 SAS/SATA based host adapters driver
3 *
4 * Copyright (c) 2008-2009 USI Co., Ltd.
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions, and the following disclaimer,
12 * without modification.
13 * 2. Redistributions in binary form must reproduce at minimum a disclaimer
14 * substantially similar to the "NO WARRANTY" disclaimer below
15 * ("Disclaimer") and any redistribution must be conditioned upon
16 * including a substantially similar Disclaimer requirement for further
17 * binary redistribution.
18 * 3. Neither the names of the above-listed copyright holders nor the names
19 * of any contributors may be used to endorse or promote products derived
20 * from this software without specific prior written permission.
21 *
22 * Alternatively, this software may be distributed under the terms of the
23 * GNU General Public License ("GPL") version 2 as published by the Free
24 * Software Foundation.
25 *
26 * NO WARRANTY
27 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
28 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
29 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR
30 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
31 * HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
32 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
33 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
34 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
35 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
36 * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
37 * POSSIBILITY OF SUCH DAMAGES.
38 *
39 */
40#ifndef _PMC8001_REG_H_
41#define _PMC8001_REG_H_
42
43#include <linux/types.h>
44#include <scsi/libsas.h>
45
46
47/* for Request Opcode of IOMB */
48#define OPC_INB_ECHO 1 /* 0x000 */
49#define OPC_INB_PHYSTART 4 /* 0x004 */
50#define OPC_INB_PHYSTOP 5 /* 0x005 */
51#define OPC_INB_SSPINIIOSTART 6 /* 0x006 */
52#define OPC_INB_SSPINITMSTART 7 /* 0x007 */
53#define OPC_INB_SSPINIEXTIOSTART 8 /* 0x008 */
54#define OPC_INB_DEV_HANDLE_ACCEPT 9 /* 0x009 */
55#define OPC_INB_SSPTGTIOSTART 10 /* 0x00A */
56#define OPC_INB_SSPTGTRSPSTART 11 /* 0x00B */
57#define OPC_INB_SSPINIEDCIOSTART 12 /* 0x00C */
58#define OPC_INB_SSPINIEXTEDCIOSTART 13 /* 0x00D */
59#define OPC_INB_SSPTGTEDCIOSTART 14 /* 0x00E */
60#define OPC_INB_SSP_ABORT 15 /* 0x00F */
61#define OPC_INB_DEREG_DEV_HANDLE 16 /* 0x010 */
62#define OPC_INB_GET_DEV_HANDLE 17 /* 0x011 */
63#define OPC_INB_SMP_REQUEST 18 /* 0x012 */
64/* SMP_RESPONSE is removed */
65#define OPC_INB_SMP_RESPONSE 19 /* 0x013 */
66#define OPC_INB_SMP_ABORT 20 /* 0x014 */
67#define OPC_INB_REG_DEV 22 /* 0x016 */
68#define OPC_INB_SATA_HOST_OPSTART 23 /* 0x017 */
69#define OPC_INB_SATA_ABORT 24 /* 0x018 */
70#define OPC_INB_LOCAL_PHY_CONTROL 25 /* 0x019 */
71#define OPC_INB_GET_DEV_INFO 26 /* 0x01A */
72#define OPC_INB_FW_FLASH_UPDATE 32 /* 0x020 */
73#define OPC_INB_GPIO 34 /* 0x022 */
74#define OPC_INB_SAS_DIAG_MODE_START_END 35 /* 0x023 */
75#define OPC_INB_SAS_DIAG_EXECUTE 36 /* 0x024 */
76#define OPC_INB_SAS_HW_EVENT_ACK 37 /* 0x025 */
77#define OPC_INB_GET_TIME_STAMP 38 /* 0x026 */
78#define OPC_INB_PORT_CONTROL 39 /* 0x027 */
79#define OPC_INB_GET_NVMD_DATA 40 /* 0x028 */
80#define OPC_INB_SET_NVMD_DATA 41 /* 0x029 */
81#define OPC_INB_SET_DEVICE_STATE 42 /* 0x02A */
82#define OPC_INB_GET_DEVICE_STATE 43 /* 0x02B */
83#define OPC_INB_SET_DEV_INFO 44 /* 0x02C */
84#define OPC_INB_SAS_RE_INITIALIZE 45 /* 0x02D */
85
86/* for Response Opcode of IOMB */
87#define OPC_OUB_ECHO 1 /* 0x001 */
88#define OPC_OUB_HW_EVENT 4 /* 0x004 */
89#define OPC_OUB_SSP_COMP 5 /* 0x005 */
90#define OPC_OUB_SMP_COMP 6 /* 0x006 */
91#define OPC_OUB_LOCAL_PHY_CNTRL 7 /* 0x007 */
92#define OPC_OUB_DEV_REGIST 10 /* 0x00A */
93#define OPC_OUB_DEREG_DEV 11 /* 0x00B */
94#define OPC_OUB_GET_DEV_HANDLE 12 /* 0x00C */
95#define OPC_OUB_SATA_COMP 13 /* 0x00D */
96#define OPC_OUB_SATA_EVENT 14 /* 0x00E */
97#define OPC_OUB_SSP_EVENT 15 /* 0x00F */
98#define OPC_OUB_DEV_HANDLE_ARRIV 16 /* 0x010 */
99/* SMP_RECEIVED Notification is removed */
100#define OPC_OUB_SMP_RECV_EVENT 17 /* 0x011 */
101#define OPC_OUB_SSP_RECV_EVENT 18 /* 0x012 */
102#define OPC_OUB_DEV_INFO 19 /* 0x013 */
103#define OPC_OUB_FW_FLASH_UPDATE 20 /* 0x014 */
104#define OPC_OUB_GPIO_RESPONSE 22 /* 0x016 */
105#define OPC_OUB_GPIO_EVENT 23 /* 0x017 */
106#define OPC_OUB_GENERAL_EVENT 24 /* 0x018 */
107#define OPC_OUB_SSP_ABORT_RSP 26 /* 0x01A */
108#define OPC_OUB_SATA_ABORT_RSP 27 /* 0x01B */
109#define OPC_OUB_SAS_DIAG_MODE_START_END 28 /* 0x01C */
110#define OPC_OUB_SAS_DIAG_EXECUTE 29 /* 0x01D */
111#define OPC_OUB_GET_TIME_STAMP 30 /* 0x01E */
112#define OPC_OUB_SAS_HW_EVENT_ACK 31 /* 0x01F */
113#define OPC_OUB_PORT_CONTROL 32 /* 0x020 */
114#define OPC_OUB_SKIP_ENTRY 33 /* 0x021 */
115#define OPC_OUB_SMP_ABORT_RSP 34 /* 0x022 */
116#define OPC_OUB_GET_NVMD_DATA 35 /* 0x023 */
117#define OPC_OUB_SET_NVMD_DATA 36 /* 0x024 */
118#define OPC_OUB_DEVICE_HANDLE_REMOVAL 37 /* 0x025 */
119#define OPC_OUB_SET_DEVICE_STATE 38 /* 0x026 */
120#define OPC_OUB_GET_DEVICE_STATE 39 /* 0x027 */
121#define OPC_OUB_SET_DEV_INFO 40 /* 0x028 */
122#define OPC_OUB_SAS_RE_INITIALIZE 41 /* 0x029 */
123
124/* for phy start*/
125#define SPINHOLD_DISABLE (0x00 << 14)
126#define SPINHOLD_ENABLE (0x01 << 14)
127#define LINKMODE_SAS (0x01 << 12)
128#define LINKMODE_DSATA (0x02 << 12)
129#define LINKMODE_AUTO (0x03 << 12)
130#define LINKRATE_15 (0x01 << 8)
131#define LINKRATE_30 (0x02 << 8)
132#define LINKRATE_60 (0x04 << 8)
133
134struct mpi_msg_hdr{
135 __le32 header; /* Bits [11:0] - Message operation code */
136 /* Bits [15:12] - Message Category */
137 /* Bits [21:16] - Outboundqueue ID for the
138 operation completion message */
139 /* Bits [23:22] - Reserved */
140 /* Bits [28:24] - Buffer Count, indicates how
141 many buffer are allocated for the massage */
142 /* Bits [30:29] - Reserved */
143 /* Bits [31] - Message Valid bit */
144} __attribute__((packed, aligned(4)));
145
146
147/*
148 * brief the data structure of PHY Start Command
149 * use to describe enable the phy (64 bytes)
150 */
151struct phy_start_req {
152 __le32 tag;
153 __le32 ase_sh_lm_slr_phyid;
154 struct sas_identify_frame sas_identify;
155 u32 reserved[5];
156} __attribute__((packed, aligned(4)));
157
158
159/*
160 * brief the data structure of PHY Start Command
161 * use to disable the phy (64 bytes)
162 */
163struct phy_stop_req {
164 __le32 tag;
165 __le32 phy_id;
166 u32 reserved[13];
167} __attribute__((packed, aligned(4)));
168
169
170/* set device bits fis - device to host */
171struct set_dev_bits_fis {
172 u8 fis_type; /* 0xA1*/
173 u8 n_i_pmport;
174 /* b7 : n Bit. Notification bit. If set device needs attention. */
175 /* b6 : i Bit. Interrupt Bit */
176 /* b5-b4: reserved2 */
177 /* b3-b0: PM Port */
178 u8 status;
179 u8 error;
180 u32 _r_a;
181} __attribute__ ((packed));
182/* PIO setup FIS - device to host */
183struct pio_setup_fis {
184 u8 fis_type; /* 0x5f */
185 u8 i_d_pmPort;
186 /* b7 : reserved */
187 /* b6 : i bit. Interrupt bit */
188 /* b5 : d bit. data transfer direction. set to 1 for device to host
189 xfer */
190 /* b4 : reserved */
191 /* b3-b0: PM Port */
192 u8 status;
193 u8 error;
194 u8 lbal;
195 u8 lbam;
196 u8 lbah;
197 u8 device;
198 u8 lbal_exp;
199 u8 lbam_exp;
200 u8 lbah_exp;
201 u8 _r_a;
202 u8 sector_count;
203 u8 sector_count_exp;
204 u8 _r_b;
205 u8 e_status;
206 u8 _r_c[2];
207 u8 transfer_count;
208} __attribute__ ((packed));
209
210/*
211 * brief the data structure of SATA Completion Response
212 * use to discribe the sata task response (64 bytes)
213 */
214struct sata_completion_resp {
215 __le32 tag;
216 __le32 status;
217 __le32 param;
218 u32 sata_resp[12];
219} __attribute__((packed, aligned(4)));
220
221
222/*
223 * brief the data structure of SAS HW Event Notification
224 * use to alert the host about the hardware event(64 bytes)
225 */
226struct hw_event_resp {
227 __le32 lr_evt_status_phyid_portid;
228 __le32 evt_param;
229 __le32 npip_portstate;
230 struct sas_identify_frame sas_identify;
231 struct dev_to_host_fis sata_fis;
232} __attribute__((packed, aligned(4)));
233
234
235/*
236 * brief the data structure of REGISTER DEVICE Command
237 * use to describe MPI REGISTER DEVICE Command (64 bytes)
238 */
239
240struct reg_dev_req {
241 __le32 tag;
242 __le32 phyid_portid;
243 __le32 dtype_dlr_retry;
244 __le32 firstburstsize_ITNexustimeout;
245 u8 sas_addr[SAS_ADDR_SIZE];
246 __le32 upper_device_id;
247 u32 reserved[8];
248} __attribute__((packed, aligned(4)));
249
250
251/*
252 * brief the data structure of DEREGISTER DEVICE Command
253 * use to request spc to remove all internal resources associated
254 * with the device id (64 bytes)
255 */
256
257struct dereg_dev_req {
258 __le32 tag;
259 __le32 device_id;
260 u32 reserved[13];
261} __attribute__((packed, aligned(4)));
262
263
264/*
265 * brief the data structure of DEVICE_REGISTRATION Response
266 * use to notify the completion of the device registration (64 bytes)
267 */
268
269struct dev_reg_resp {
270 __le32 tag;
271 __le32 status;
272 __le32 device_id;
273 u32 reserved[12];
274} __attribute__((packed, aligned(4)));
275
276
277/*
278 * brief the data structure of Local PHY Control Command
279 * use to issue PHY CONTROL to local phy (64 bytes)
280 */
281struct local_phy_ctl_req {
282 __le32 tag;
283 __le32 phyop_phyid;
284 u32 reserved1[13];
285} __attribute__((packed, aligned(4)));
286
287
288/**
289 * brief the data structure of Local Phy Control Response
290 * use to describe MPI Local Phy Control Response (64 bytes)
291 */
292struct local_phy_ctl_resp {
293 __le32 tag;
294 __le32 phyop_phyid;
295 __le32 status;
296 u32 reserved[12];
297} __attribute__((packed, aligned(4)));
298
299
300#define OP_BITS 0x0000FF00
301#define ID_BITS 0x0000000F
302
303/*
304 * brief the data structure of PORT Control Command
305 * use to control port properties (64 bytes)
306 */
307
308struct port_ctl_req {
309 __le32 tag;
310 __le32 portop_portid;
311 __le32 param0;
312 __le32 param1;
313 u32 reserved1[11];
314} __attribute__((packed, aligned(4)));
315
316
317/*
318 * brief the data structure of HW Event Ack Command
319 * use to acknowledge receive HW event (64 bytes)
320 */
321
322struct hw_event_ack_req {
323 __le32 tag;
324 __le32 sea_phyid_portid;
325 __le32 param0;
326 __le32 param1;
327 u32 reserved1[11];
328} __attribute__((packed, aligned(4)));
329
330
331/*
332 * brief the data structure of SSP Completion Response
333 * use to indicate a SSP Completion (n bytes)
334 */
335struct ssp_completion_resp {
336 __le32 tag;
337 __le32 status;
338 __le32 param;
339 __le32 ssptag_rescv_rescpad;
340 struct ssp_response_iu ssp_resp_iu;
341 __le32 residual_count;
342} __attribute__((packed, aligned(4)));
343
344
345#define SSP_RESCV_BIT 0x00010000
346
347/*
348 * brief the data structure of SATA EVNET esponse
349 * use to indicate a SATA Completion (64 bytes)
350 */
351
352struct sata_event_resp {
353 __le32 tag;
354 __le32 event;
355 __le32 port_id;
356 __le32 device_id;
357 u32 reserved[11];
358} __attribute__((packed, aligned(4)));
359
360/*
361 * brief the data structure of SSP EVNET esponse
362 * use to indicate a SSP Completion (64 bytes)
363 */
364
365struct ssp_event_resp {
366 __le32 tag;
367 __le32 event;
368 __le32 port_id;
369 __le32 device_id;
370 u32 reserved[11];
371} __attribute__((packed, aligned(4)));
372
373/**
374 * brief the data structure of General Event Notification Response
375 * use to describe MPI General Event Notification Response (64 bytes)
376 */
377struct general_event_resp {
378 __le32 status;
379 __le32 inb_IOMB_payload[14];
380} __attribute__((packed, aligned(4)));
381
382
383#define GENERAL_EVENT_PAYLOAD 14
384#define OPCODE_BITS 0x00000fff
385
386/*
387 * brief the data structure of SMP Request Command
388 * use to describe MPI SMP REQUEST Command (64 bytes)
389 */
390struct smp_req {
391 __le32 tag;
392 __le32 device_id;
393 __le32 len_ip_ir;
394 /* Bits [0] - Indirect response */
395 /* Bits [1] - Indirect Payload */
396 /* Bits [15:2] - Reserved */
397 /* Bits [23:16] - direct payload Len */
398 /* Bits [31:24] - Reserved */
399 u8 smp_req16[16];
400 union {
401 u8 smp_req[32];
402 struct {
403 __le64 long_req_addr;/* sg dma address, LE */
404 __le32 long_req_size;/* LE */
405 u32 _r_a;
406 __le64 long_resp_addr;/* sg dma address, LE */
407 __le32 long_resp_size;/* LE */
408 u32 _r_b;
409 } long_smp_req;/* sequencer extension */
410 };
411} __attribute__((packed, aligned(4)));
412/*
413 * brief the data structure of SMP Completion Response
414 * use to describe MPI SMP Completion Response (64 bytes)
415 */
416struct smp_completion_resp {
417 __le32 tag;
418 __le32 status;
419 __le32 param;
420 __le32 _r_a[12];
421} __attribute__((packed, aligned(4)));
422
423/*
424 *brief the data structure of SSP SMP SATA Abort Command
425 * use to describe MPI SSP SMP & SATA Abort Command (64 bytes)
426 */
427struct task_abort_req {
428 __le32 tag;
429 __le32 device_id;
430 __le32 tag_to_abort;
431 __le32 abort_all;
432 u32 reserved[11];
433} __attribute__((packed, aligned(4)));
434
435/* These flags used for SSP SMP & SATA Abort */
436#define ABORT_MASK 0x3
437#define ABORT_SINGLE 0x0
438#define ABORT_ALL 0x1
439
440/**
441 * brief the data structure of SSP SATA SMP Abort Response
442 * use to describe SSP SMP & SATA Abort Response ( 64 bytes)
443 */
444struct task_abort_resp {
445 __le32 tag;
446 __le32 status;
447 __le32 scp;
448 u32 reserved[12];
449} __attribute__((packed, aligned(4)));
450
451
452/**
453 * brief the data structure of SAS Diagnostic Start/End Command
454 * use to describe MPI SAS Diagnostic Start/End Command (64 bytes)
455 */
456struct sas_diag_start_end_req {
457 __le32 tag;
458 __le32 operation_phyid;
459 u32 reserved[13];
460} __attribute__((packed, aligned(4)));
461
462
463/**
464 * brief the data structure of SAS Diagnostic Execute Command
465 * use to describe MPI SAS Diagnostic Execute Command (64 bytes)
466 */
467struct sas_diag_execute_req{
468 __le32 tag;
469 __le32 cmdtype_cmddesc_phyid;
470 __le32 pat1_pat2;
471 __le32 threshold;
472 __le32 codepat_errmsk;
473 __le32 pmon;
474 __le32 pERF1CTL;
475 u32 reserved[8];
476} __attribute__((packed, aligned(4)));
477
478
479#define SAS_DIAG_PARAM_BYTES 24
480
481/*
482 * brief the data structure of Set Device State Command
483 * use to describe MPI Set Device State Command (64 bytes)
484 */
485struct set_dev_state_req {
486 __le32 tag;
487 __le32 device_id;
488 __le32 nds;
489 u32 reserved[12];
490} __attribute__((packed, aligned(4)));
491
492/*
493 * brief the data structure of sas_re_initialization
494 */
495struct sas_re_initialization_req {
496
497 __le32 tag;
498 __le32 SSAHOLT;/* bit29-set max port;
499 ** bit28-set open reject cmd retries.
500 ** bit27-set open reject data retries.
501 ** bit26-set open reject option, remap:1 or not:0.
502 ** bit25-set sata head of line time out.
503 */
504 __le32 reserved_maxPorts;
505 __le32 open_reject_cmdretries_data_retries;/* cmd retries: 31-bit16;
506 * data retries: bit15-bit0.
507 */
508 __le32 sata_hol_tmo;
509 u32 reserved1[10];
510} __attribute__((packed, aligned(4)));
511
512/*
513 * brief the data structure of SATA Start Command
514 * use to describe MPI SATA IO Start Command (64 bytes)
515 */
516
517struct sata_start_req {
518 __le32 tag;
519 __le32 device_id;
520 __le32 data_len;
521 __le32 ncqtag_atap_dir_m;
522 struct host_to_dev_fis sata_fis;
523 u32 reserved1;
524 u32 reserved2;
525 u32 addr_low;
526 u32 addr_high;
527 __le32 len;
528 __le32 esgl;
529} __attribute__((packed, aligned(4)));
530
531/**
532 * brief the data structure of SSP INI TM Start Command
533 * use to describe MPI SSP INI TM Start Command (64 bytes)
534 */
535struct ssp_ini_tm_start_req {
536 __le32 tag;
537 __le32 device_id;
538 __le32 relate_tag;
539 __le32 tmf;
540 u8 lun[8];
541 __le32 ds_ads_m;
542 u32 reserved[8];
543} __attribute__((packed, aligned(4)));
544
545
546struct ssp_info_unit {
547 u8 lun[8];/* SCSI Logical Unit Number */
548 u8 reserved1;/* reserved */
549 u8 efb_prio_attr;
550 /* B7 : enabledFirstBurst */
551 /* B6-3 : taskPriority */
552 /* B2-0 : taskAttribute */
553 u8 reserved2; /* reserved */
554 u8 additional_cdb_len;
555 /* B7-2 : additional_cdb_len */
556 /* B1-0 : reserved */
557 u8 cdb[16];/* The SCSI CDB up to 16 bytes length */
558} __attribute__((packed, aligned(4)));
559
560
561/**
562 * brief the data structure of SSP INI IO Start Command
563 * use to describe MPI SSP INI IO Start Command (64 bytes)
564 */
565struct ssp_ini_io_start_req {
566 __le32 tag;
567 __le32 device_id;
568 __le32 data_len;
569 __le32 dir_m_tlr;
570 struct ssp_info_unit ssp_iu;
571 __le32 addr_low;
572 __le32 addr_high;
573 __le32 len;
574 __le32 esgl;
575} __attribute__((packed, aligned(4)));
576
577
578/**
579 * brief the data structure of Firmware download
580 * use to describe MPI FW DOWNLOAD Command (64 bytes)
581 */
582struct fw_flash_Update_req {
583 __le32 tag;
584 __le32 cur_image_offset;
585 __le32 cur_image_len;
586 __le32 total_image_len;
587 u32 reserved0[7];
588 __le32 sgl_addr_lo;
589 __le32 sgl_addr_hi;
590 __le32 len;
591 __le32 ext_reserved;
592} __attribute__((packed, aligned(4)));
593
594
595#define FWFLASH_IOMB_RESERVED_LEN 0x07
596/**
597 * brief the data structure of FW_FLASH_UPDATE Response
598 * use to describe MPI FW_FLASH_UPDATE Response (64 bytes)
599 *
600 */
601struct fw_flash_Update_resp {
602 dma_addr_t tag;
603 __le32 status;
604 u32 reserved[13];
605} __attribute__((packed, aligned(4)));
606
607
608/**
609 * brief the data structure of Get NVM Data Command
610 * use to get data from NVM in HBA(64 bytes)
611 */
612struct get_nvm_data_req {
613 __le32 tag;
614 __le32 len_ir_vpdd;
615 __le32 vpd_offset;
616 u32 reserved[8];
617 __le32 resp_addr_lo;
618 __le32 resp_addr_hi;
619 __le32 resp_len;
620 u32 reserved1;
621} __attribute__((packed, aligned(4)));
622
623
624struct set_nvm_data_req {
625 __le32 tag;
626 __le32 len_ir_vpdd;
627 __le32 vpd_offset;
628 u32 reserved[8];
629 __le32 resp_addr_lo;
630 __le32 resp_addr_hi;
631 __le32 resp_len;
632 u32 reserved1;
633} __attribute__((packed, aligned(4)));
634
635
636#define TWI_DEVICE 0x0
637#define C_SEEPROM 0x1
638#define VPD_FLASH 0x4
639#define AAP1_RDUMP 0x5
640#define IOP_RDUMP 0x6
641#define EXPAN_ROM 0x7
642
643#define IPMode 0x80000000
644#define NVMD_TYPE 0x0000000F
645#define NVMD_STAT 0x0000FFFF
646#define NVMD_LEN 0xFF000000
647/**
648 * brief the data structure of Get NVMD Data Response
649 * use to describe MPI Get NVMD Data Response (64 bytes)
650 */
651struct get_nvm_data_resp {
652 __le32 tag;
653 __le32 ir_tda_bn_dps_das_nvm;
654 __le32 dlen_status;
655 __le32 nvm_data[12];
656} __attribute__((packed, aligned(4)));
657
658
659/**
660 * brief the data structure of SAS Diagnostic Start/End Response
661 * use to describe MPI SAS Diagnostic Start/End Response (64 bytes)
662 *
663 */
664struct sas_diag_start_end_resp {
665 __le32 tag;
666 __le32 status;
667 u32 reserved[13];
668} __attribute__((packed, aligned(4)));
669
670
671/**
672 * brief the data structure of SAS Diagnostic Execute Response
673 * use to describe MPI SAS Diagnostic Execute Response (64 bytes)
674 *
675 */
676struct sas_diag_execute_resp {
677 __le32 tag;
678 __le32 cmdtype_cmddesc_phyid;
679 __le32 Status;
680 __le32 ReportData;
681 u32 reserved[11];
682} __attribute__((packed, aligned(4)));
683
684
685/**
686 * brief the data structure of Set Device State Response
687 * use to describe MPI Set Device State Response (64 bytes)
688 *
689 */
690struct set_dev_state_resp {
691 __le32 tag;
692 __le32 status;
693 __le32 device_id;
694 __le32 pds_nds;
695 u32 reserved[11];
696} __attribute__((packed, aligned(4)));
697
698
699#define NDS_BITS 0x0F
700#define PDS_BITS 0xF0
701
702/*
703 * HW Events type
704 */
705
706#define HW_EVENT_RESET_START 0x01
707#define HW_EVENT_CHIP_RESET_COMPLETE 0x02
708#define HW_EVENT_PHY_STOP_STATUS 0x03
709#define HW_EVENT_SAS_PHY_UP 0x04
710#define HW_EVENT_SATA_PHY_UP 0x05
711#define HW_EVENT_SATA_SPINUP_HOLD 0x06
712#define HW_EVENT_PHY_DOWN 0x07
713#define HW_EVENT_PORT_INVALID 0x08
714#define HW_EVENT_BROADCAST_CHANGE 0x09
715#define HW_EVENT_PHY_ERROR 0x0A
716#define HW_EVENT_BROADCAST_SES 0x0B
717#define HW_EVENT_INBOUND_CRC_ERROR 0x0C
718#define HW_EVENT_HARD_RESET_RECEIVED 0x0D
719#define HW_EVENT_MALFUNCTION 0x0E
720#define HW_EVENT_ID_FRAME_TIMEOUT 0x0F
721#define HW_EVENT_BROADCAST_EXP 0x10
722#define HW_EVENT_PHY_START_STATUS 0x11
723#define HW_EVENT_LINK_ERR_INVALID_DWORD 0x12
724#define HW_EVENT_LINK_ERR_DISPARITY_ERROR 0x13
725#define HW_EVENT_LINK_ERR_CODE_VIOLATION 0x14
726#define HW_EVENT_LINK_ERR_LOSS_OF_DWORD_SYNCH 0x15
727#define HW_EVENT_LINK_ERR_PHY_RESET_FAILED 0x16
728#define HW_EVENT_PORT_RECOVERY_TIMER_TMO 0x17
729#define HW_EVENT_PORT_RECOVER 0x18
730#define HW_EVENT_PORT_RESET_TIMER_TMO 0x19
731#define HW_EVENT_PORT_RESET_COMPLETE 0x20
732#define EVENT_BROADCAST_ASYNCH_EVENT 0x21
733
734/* port state */
735#define PORT_NOT_ESTABLISHED 0x00
736#define PORT_VALID 0x01
737#define PORT_LOSTCOMM 0x02
738#define PORT_IN_RESET 0x04
739#define PORT_INVALID 0x08
740
741/*
742 * SSP/SMP/SATA IO Completion Status values
743 */
744
745#define IO_SUCCESS 0x00
746#define IO_ABORTED 0x01
747#define IO_OVERFLOW 0x02
748#define IO_UNDERFLOW 0x03
749#define IO_FAILED 0x04
750#define IO_ABORT_RESET 0x05
751#define IO_NOT_VALID 0x06
752#define IO_NO_DEVICE 0x07
753#define IO_ILLEGAL_PARAMETER 0x08
754#define IO_LINK_FAILURE 0x09
755#define IO_PROG_ERROR 0x0A
756#define IO_EDC_IN_ERROR 0x0B
757#define IO_EDC_OUT_ERROR 0x0C
758#define IO_ERROR_HW_TIMEOUT 0x0D
759#define IO_XFER_ERROR_BREAK 0x0E
760#define IO_XFER_ERROR_PHY_NOT_READY 0x0F
761#define IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED 0x10
762#define IO_OPEN_CNX_ERROR_ZONE_VIOLATION 0x11
763#define IO_OPEN_CNX_ERROR_BREAK 0x12
764#define IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS 0x13
765#define IO_OPEN_CNX_ERROR_BAD_DESTINATION 0x14
766#define IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED 0x15
767#define IO_OPEN_CNX_ERROR_STP_RESOURCES_BUSY 0x16
768#define IO_OPEN_CNX_ERROR_WRONG_DESTINATION 0x17
769#define IO_OPEN_CNX_ERROR_UNKNOWN_ERROR 0x18
770#define IO_XFER_ERROR_NAK_RECEIVED 0x19
771#define IO_XFER_ERROR_ACK_NAK_TIMEOUT 0x1A
772#define IO_XFER_ERROR_PEER_ABORTED 0x1B
773#define IO_XFER_ERROR_RX_FRAME 0x1C
774#define IO_XFER_ERROR_DMA 0x1D
775#define IO_XFER_ERROR_CREDIT_TIMEOUT 0x1E
776#define IO_XFER_ERROR_SATA_LINK_TIMEOUT 0x1F
777#define IO_XFER_ERROR_SATA 0x20
778#define IO_XFER_ERROR_ABORTED_DUE_TO_SRST 0x22
779#define IO_XFER_ERROR_REJECTED_NCQ_MODE 0x21
780#define IO_XFER_ERROR_ABORTED_NCQ_MODE 0x23
781#define IO_XFER_OPEN_RETRY_TIMEOUT 0x24
782#define IO_XFER_SMP_RESP_CONNECTION_ERROR 0x25
783#define IO_XFER_ERROR_UNEXPECTED_PHASE 0x26
784#define IO_XFER_ERROR_XFER_RDY_OVERRUN 0x27
785#define IO_XFER_ERROR_XFER_RDY_NOT_EXPECTED 0x28
786
787#define IO_XFER_ERROR_CMD_ISSUE_ACK_NAK_TIMEOUT 0x30
788#define IO_XFER_ERROR_CMD_ISSUE_BREAK_BEFORE_ACK_NAK 0x31
789#define IO_XFER_ERROR_CMD_ISSUE_PHY_DOWN_BEFORE_ACK_NAK 0x32
790
791#define IO_XFER_ERROR_OFFSET_MISMATCH 0x34
792#define IO_XFER_ERROR_XFER_ZERO_DATA_LEN 0x35
793#define IO_XFER_CMD_FRAME_ISSUED 0x36
794#define IO_ERROR_INTERNAL_SMP_RESOURCE 0x37
795#define IO_PORT_IN_RESET 0x38
796#define IO_DS_NON_OPERATIONAL 0x39
797#define IO_DS_IN_RECOVERY 0x3A
798#define IO_TM_TAG_NOT_FOUND 0x3B
799#define IO_XFER_PIO_SETUP_ERROR 0x3C
800#define IO_SSP_EXT_IU_ZERO_LEN_ERROR 0x3D
801#define IO_DS_IN_ERROR 0x3E
802#define IO_OPEN_CNX_ERROR_HW_RESOURCE_BUSY 0x3F
803#define IO_ABORT_IN_PROGRESS 0x40
804#define IO_ABORT_DELAYED 0x41
805#define IO_INVALID_LENGTH 0x42
806
807/* WARNING: This error code must always be the last number.
808 * If you add error code, modify this code also
809 * It is used as an index
810 */
811#define IO_ERROR_UNKNOWN_GENERIC 0x43
812
813/* MSGU CONFIGURATION TABLE*/
814
815#define SPC_MSGU_CFG_TABLE_UPDATE 0x01/* Inbound doorbell bit0 */
816#define SPC_MSGU_CFG_TABLE_RESET 0x02/* Inbound doorbell bit1 */
817#define SPC_MSGU_CFG_TABLE_FREEZE 0x04/* Inbound doorbell bit2 */
818#define SPC_MSGU_CFG_TABLE_UNFREEZE 0x08/* Inbound doorbell bit4 */
819#define MSGU_IBDB_SET 0x04
820#define MSGU_HOST_INT_STATUS 0x08
821#define MSGU_HOST_INT_MASK 0x0C
822#define MSGU_IOPIB_INT_STATUS 0x18
823#define MSGU_IOPIB_INT_MASK 0x1C
824#define MSGU_IBDB_CLEAR 0x20/* RevB - Host not use */
825#define MSGU_MSGU_CONTROL 0x24
826#define MSGU_ODR 0x3C/* RevB */
827#define MSGU_ODCR 0x40/* RevB */
828#define MSGU_SCRATCH_PAD_0 0x44
829#define MSGU_SCRATCH_PAD_1 0x48
830#define MSGU_SCRATCH_PAD_2 0x4C
831#define MSGU_SCRATCH_PAD_3 0x50
832#define MSGU_HOST_SCRATCH_PAD_0 0x54
833#define MSGU_HOST_SCRATCH_PAD_1 0x58
834#define MSGU_HOST_SCRATCH_PAD_2 0x5C
835#define MSGU_HOST_SCRATCH_PAD_3 0x60
836#define MSGU_HOST_SCRATCH_PAD_4 0x64
837#define MSGU_HOST_SCRATCH_PAD_5 0x68
838#define MSGU_HOST_SCRATCH_PAD_6 0x6C
839#define MSGU_HOST_SCRATCH_PAD_7 0x70
840#define MSGU_ODMR 0x74/* RevB */
841
842/* bit definition for ODMR register */
843#define ODMR_MASK_ALL 0xFFFFFFFF/* mask all
844 interrupt vector */
845#define ODMR_CLEAR_ALL 0/* clear all
846 interrupt vector */
847/* bit definition for ODCR register */
848#define ODCR_CLEAR_ALL 0xFFFFFFFF /* mask all
849 interrupt vector*/
850/* MSIX Interupts */
851#define MSIX_TABLE_OFFSET 0x2000
852#define MSIX_TABLE_ELEMENT_SIZE 0x10
853#define MSIX_INTERRUPT_CONTROL_OFFSET 0xC
854#define MSIX_TABLE_BASE (MSIX_TABLE_OFFSET + MSIX_INTERRUPT_CONTROL_OFFSET)
855#define MSIX_INTERRUPT_DISABLE 0x1
856#define MSIX_INTERRUPT_ENABLE 0x0
857
858
859/* state definition for Scratch Pad1 register */
860#define SCRATCH_PAD1_POR 0x00 /* power on reset state */
861#define SCRATCH_PAD1_SFR 0x01 /* soft reset state */
862#define SCRATCH_PAD1_ERR 0x02 /* error state */
863#define SCRATCH_PAD1_RDY 0x03 /* ready state */
864#define SCRATCH_PAD1_RST 0x04 /* soft reset toggle flag */
865#define SCRATCH_PAD1_AAP1RDY_RST 0x08 /* AAP1 ready for soft reset */
866#define SCRATCH_PAD1_STATE_MASK 0xFFFFFFF0 /* ScratchPad1
867 Mask, bit1-0 State, bit2 Soft Reset, bit3 FW RDY for Soft Reset */
868#define SCRATCH_PAD1_RESERVED 0x000003F8 /* Scratch Pad1
869 Reserved bit 3 to 9 */
870
871 /* state definition for Scratch Pad2 register */
872#define SCRATCH_PAD2_POR 0x00 /* power on state */
873#define SCRATCH_PAD2_SFR 0x01 /* soft reset state */
874#define SCRATCH_PAD2_ERR 0x02 /* error state */
875#define SCRATCH_PAD2_RDY 0x03 /* ready state */
876#define SCRATCH_PAD2_FWRDY_RST 0x04 /* FW ready for soft reset flag*/
877#define SCRATCH_PAD2_IOPRDY_RST 0x08 /* IOP ready for soft reset */
878#define SCRATCH_PAD2_STATE_MASK 0xFFFFFFF4 /* ScratchPad 2
879 Mask, bit1-0 State */
880#define SCRATCH_PAD2_RESERVED 0x000003FC /* Scratch Pad1
881 Reserved bit 2 to 9 */
882
883#define SCRATCH_PAD_ERROR_MASK 0xFFFFFC00 /* Error mask bits */
884#define SCRATCH_PAD_STATE_MASK 0x00000003 /* State Mask bits */
885
886/* main configuration offset - byte offset */
887#define MAIN_SIGNATURE_OFFSET 0x00/* DWORD 0x00 */
888#define MAIN_INTERFACE_REVISION 0x04/* DWORD 0x01 */
889#define MAIN_FW_REVISION 0x08/* DWORD 0x02 */
890#define MAIN_MAX_OUTSTANDING_IO_OFFSET 0x0C/* DWORD 0x03 */
891#define MAIN_MAX_SGL_OFFSET 0x10/* DWORD 0x04 */
892#define MAIN_CNTRL_CAP_OFFSET 0x14/* DWORD 0x05 */
893#define MAIN_GST_OFFSET 0x18/* DWORD 0x06 */
894#define MAIN_IBQ_OFFSET 0x1C/* DWORD 0x07 */
895#define MAIN_OBQ_OFFSET 0x20/* DWORD 0x08 */
896#define MAIN_IQNPPD_HPPD_OFFSET 0x24/* DWORD 0x09 */
897#define MAIN_OB_HW_EVENT_PID03_OFFSET 0x28/* DWORD 0x0A */
898#define MAIN_OB_HW_EVENT_PID47_OFFSET 0x2C/* DWORD 0x0B */
899#define MAIN_OB_NCQ_EVENT_PID03_OFFSET 0x30/* DWORD 0x0C */
900#define MAIN_OB_NCQ_EVENT_PID47_OFFSET 0x34/* DWORD 0x0D */
901#define MAIN_TITNX_EVENT_PID03_OFFSET 0x38/* DWORD 0x0E */
902#define MAIN_TITNX_EVENT_PID47_OFFSET 0x3C/* DWORD 0x0F */
903#define MAIN_OB_SSP_EVENT_PID03_OFFSET 0x40/* DWORD 0x10 */
904#define MAIN_OB_SSP_EVENT_PID47_OFFSET 0x44/* DWORD 0x11 */
905#define MAIN_OB_SMP_EVENT_PID03_OFFSET 0x48/* DWORD 0x12 */
906#define MAIN_OB_SMP_EVENT_PID47_OFFSET 0x4C/* DWORD 0x13 */
907#define MAIN_EVENT_LOG_ADDR_HI 0x50/* DWORD 0x14 */
908#define MAIN_EVENT_LOG_ADDR_LO 0x54/* DWORD 0x15 */
909#define MAIN_EVENT_LOG_BUFF_SIZE 0x58/* DWORD 0x16 */
910#define MAIN_EVENT_LOG_OPTION 0x5C/* DWORD 0x17 */
911#define MAIN_IOP_EVENT_LOG_ADDR_HI 0x60/* DWORD 0x18 */
912#define MAIN_IOP_EVENT_LOG_ADDR_LO 0x64/* DWORD 0x19 */
913#define MAIN_IOP_EVENT_LOG_BUFF_SIZE 0x68/* DWORD 0x1A */
914#define MAIN_IOP_EVENT_LOG_OPTION 0x6C/* DWORD 0x1B */
915#define MAIN_FATAL_ERROR_INTERRUPT 0x70/* DWORD 0x1C */
916#define MAIN_FATAL_ERROR_RDUMP0_OFFSET 0x74/* DWORD 0x1D */
917#define MAIN_FATAL_ERROR_RDUMP0_LENGTH 0x78/* DWORD 0x1E */
918#define MAIN_FATAL_ERROR_RDUMP1_OFFSET 0x7C/* DWORD 0x1F */
919#define MAIN_FATAL_ERROR_RDUMP1_LENGTH 0x80/* DWORD 0x20 */
920#define MAIN_HDA_FLAGS_OFFSET 0x84/* DWORD 0x21 */
921#define MAIN_ANALOG_SETUP_OFFSET 0x88/* DWORD 0x22 */
922
923/* Gereral Status Table offset - byte offset */
924#define GST_GSTLEN_MPIS_OFFSET 0x00
925#define GST_IQ_FREEZE_STATE0_OFFSET 0x04
926#define GST_IQ_FREEZE_STATE1_OFFSET 0x08
927#define GST_MSGUTCNT_OFFSET 0x0C
928#define GST_IOPTCNT_OFFSET 0x10
929#define GST_PHYSTATE_OFFSET 0x18
930#define GST_PHYSTATE0_OFFSET 0x18
931#define GST_PHYSTATE1_OFFSET 0x1C
932#define GST_PHYSTATE2_OFFSET 0x20
933#define GST_PHYSTATE3_OFFSET 0x24
934#define GST_PHYSTATE4_OFFSET 0x28
935#define GST_PHYSTATE5_OFFSET 0x2C
936#define GST_PHYSTATE6_OFFSET 0x30
937#define GST_PHYSTATE7_OFFSET 0x34
938#define GST_RERRINFO_OFFSET 0x44
939
940/* General Status Table - MPI state */
941#define GST_MPI_STATE_UNINIT 0x00
942#define GST_MPI_STATE_INIT 0x01
943#define GST_MPI_STATE_TERMINATION 0x02
944#define GST_MPI_STATE_ERROR 0x03
945#define GST_MPI_STATE_MASK 0x07
946
947#define MBIC_NMI_ENABLE_VPE0_IOP 0x000418
948#define MBIC_NMI_ENABLE_VPE0_AAP1 0x000418
949/* PCIE registers - BAR2(0x18), BAR1(win) 0x010000 */
950#define PCIE_EVENT_INTERRUPT_ENABLE 0x003040
951#define PCIE_EVENT_INTERRUPT 0x003044
952#define PCIE_ERROR_INTERRUPT_ENABLE 0x003048
953#define PCIE_ERROR_INTERRUPT 0x00304C
954/* signature defintion for host scratch pad0 register */
955#define SPC_SOFT_RESET_SIGNATURE 0x252acbcd
956/* Signature for Soft Reset */
957
958/* SPC Reset register - BAR4(0x20), BAR2(win) (need dynamic mapping) */
959#define SPC_REG_RESET 0x000000/* reset register */
960
961/* bit difination for SPC_RESET register */
962#define SPC_REG_RESET_OSSP 0x00000001
963#define SPC_REG_RESET_RAAE 0x00000002
964#define SPC_REG_RESET_PCS_SPBC 0x00000004
965#define SPC_REG_RESET_PCS_IOP_SS 0x00000008
966#define SPC_REG_RESET_PCS_AAP1_SS 0x00000010
967#define SPC_REG_RESET_PCS_AAP2_SS 0x00000020
968#define SPC_REG_RESET_PCS_LM 0x00000040
969#define SPC_REG_RESET_PCS 0x00000080
970#define SPC_REG_RESET_GSM 0x00000100
971#define SPC_REG_RESET_DDR2 0x00010000
972#define SPC_REG_RESET_BDMA_CORE 0x00020000
973#define SPC_REG_RESET_BDMA_SXCBI 0x00040000
974#define SPC_REG_RESET_PCIE_AL_SXCBI 0x00080000
975#define SPC_REG_RESET_PCIE_PWR 0x00100000
976#define SPC_REG_RESET_PCIE_SFT 0x00200000
977#define SPC_REG_RESET_PCS_SXCBI 0x00400000
978#define SPC_REG_RESET_LMS_SXCBI 0x00800000
979#define SPC_REG_RESET_PMIC_SXCBI 0x01000000
980#define SPC_REG_RESET_PMIC_CORE 0x02000000
981#define SPC_REG_RESET_PCIE_PC_SXCBI 0x04000000
982#define SPC_REG_RESET_DEVICE 0x80000000
983
984/* registers for BAR Shifting - BAR2(0x18), BAR1(win) */
985#define SPC_IBW_AXI_TRANSLATION_LOW 0x003258
986
987#define MBIC_AAP1_ADDR_BASE 0x060000
988#define MBIC_IOP_ADDR_BASE 0x070000
989#define GSM_ADDR_BASE 0x0700000
990/* Dynamic map through Bar4 - 0x00700000 */
991#define GSM_CONFIG_RESET 0x00000000
992#define RAM_ECC_DB_ERR 0x00000018
993#define GSM_READ_ADDR_PARITY_INDIC 0x00000058
994#define GSM_WRITE_ADDR_PARITY_INDIC 0x00000060
995#define GSM_WRITE_DATA_PARITY_INDIC 0x00000068
996#define GSM_READ_ADDR_PARITY_CHECK 0x00000038
997#define GSM_WRITE_ADDR_PARITY_CHECK 0x00000040
998#define GSM_WRITE_DATA_PARITY_CHECK 0x00000048
999
1000#define RB6_ACCESS_REG 0x6A0000
1001#define HDAC_EXEC_CMD 0x0002
1002#define HDA_C_PA 0xcb
1003#define HDA_SEQ_ID_BITS 0x00ff0000
1004#define HDA_GSM_OFFSET_BITS 0x00FFFFFF
1005#define MBIC_AAP1_ADDR_BASE 0x060000
1006#define MBIC_IOP_ADDR_BASE 0x070000
1007#define GSM_ADDR_BASE 0x0700000
1008#define SPC_TOP_LEVEL_ADDR_BASE 0x000000
1009#define GSM_CONFIG_RESET_VALUE 0x00003b00
1010#define GPIO_ADDR_BASE 0x00090000
1011#define GPIO_GPIO_0_0UTPUT_CTL_OFFSET 0x0000010c
1012
1013/* RB6 offset */
1014#define SPC_RB6_OFFSET 0x80C0
1015/* Magic number of soft reset for RB6 */
1016#define RB6_MAGIC_NUMBER_RST 0x1234
1017
1018/* Device Register status */
1019#define DEVREG_SUCCESS 0x00
1020#define DEVREG_FAILURE_OUT_OF_RESOURCE 0x01
1021#define DEVREG_FAILURE_DEVICE_ALREADY_REGISTERED 0x02
1022#define DEVREG_FAILURE_INVALID_PHY_ID 0x03
1023#define DEVREG_FAILURE_PHY_ID_ALREADY_REGISTERED 0x04
1024#define DEVREG_FAILURE_PORT_ID_OUT_OF_RANGE 0x05
1025#define DEVREG_FAILURE_PORT_NOT_VALID_STATE 0x06
1026#define DEVREG_FAILURE_DEVICE_TYPE_NOT_VALID 0x07
1027
1028#endif
1029
diff --git a/drivers/scsi/pm8001/pm8001_init.c b/drivers/scsi/pm8001/pm8001_init.c
new file mode 100644
index 000000000000..f8c86b28f03f
--- /dev/null
+++ b/drivers/scsi/pm8001/pm8001_init.c
@@ -0,0 +1,901 @@
1/*
2 * PMC-Sierra SPC 8001 SAS/SATA based host adapters driver
3 *
4 * Copyright (c) 2008-2009 USI Co., Ltd.
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions, and the following disclaimer,
12 * without modification.
13 * 2. Redistributions in binary form must reproduce at minimum a disclaimer
14 * substantially similar to the "NO WARRANTY" disclaimer below
15 * ("Disclaimer") and any redistribution must be conditioned upon
16 * including a substantially similar Disclaimer requirement for further
17 * binary redistribution.
18 * 3. Neither the names of the above-listed copyright holders nor the names
19 * of any contributors may be used to endorse or promote products derived
20 * from this software without specific prior written permission.
21 *
22 * Alternatively, this software may be distributed under the terms of the
23 * GNU General Public License ("GPL") version 2 as published by the Free
24 * Software Foundation.
25 *
26 * NO WARRANTY
27 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
28 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
29 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR
30 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
31 * HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
32 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
33 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
34 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
35 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
36 * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
37 * POSSIBILITY OF SUCH DAMAGES.
38 *
39 */
40
41#include <linux/slab.h>
42#include "pm8001_sas.h"
43#include "pm8001_chips.h"
44
45static struct scsi_transport_template *pm8001_stt;
46
47static const struct pm8001_chip_info pm8001_chips[] = {
48 [chip_8001] = { 8, &pm8001_8001_dispatch,},
49};
50static int pm8001_id;
51
52LIST_HEAD(hba_list);
53
54/**
55 * The main structure which LLDD must register for scsi core.
56 */
57static struct scsi_host_template pm8001_sht = {
58 .module = THIS_MODULE,
59 .name = DRV_NAME,
60 .queuecommand = sas_queuecommand,
61 .target_alloc = sas_target_alloc,
62 .slave_configure = pm8001_slave_configure,
63 .slave_destroy = sas_slave_destroy,
64 .scan_finished = pm8001_scan_finished,
65 .scan_start = pm8001_scan_start,
66 .change_queue_depth = sas_change_queue_depth,
67 .change_queue_type = sas_change_queue_type,
68 .bios_param = sas_bios_param,
69 .can_queue = 1,
70 .cmd_per_lun = 1,
71 .this_id = -1,
72 .sg_tablesize = SG_ALL,
73 .max_sectors = SCSI_DEFAULT_MAX_SECTORS,
74 .use_clustering = ENABLE_CLUSTERING,
75 .eh_device_reset_handler = sas_eh_device_reset_handler,
76 .eh_bus_reset_handler = sas_eh_bus_reset_handler,
77 .slave_alloc = pm8001_slave_alloc,
78 .target_destroy = sas_target_destroy,
79 .ioctl = sas_ioctl,
80 .shost_attrs = pm8001_host_attrs,
81};
82
83/**
84 * Sas layer call this function to execute specific task.
85 */
86static struct sas_domain_function_template pm8001_transport_ops = {
87 .lldd_dev_found = pm8001_dev_found,
88 .lldd_dev_gone = pm8001_dev_gone,
89
90 .lldd_execute_task = pm8001_queue_command,
91 .lldd_control_phy = pm8001_phy_control,
92
93 .lldd_abort_task = pm8001_abort_task,
94 .lldd_abort_task_set = pm8001_abort_task_set,
95 .lldd_clear_aca = pm8001_clear_aca,
96 .lldd_clear_task_set = pm8001_clear_task_set,
97 .lldd_I_T_nexus_reset = pm8001_I_T_nexus_reset,
98 .lldd_lu_reset = pm8001_lu_reset,
99 .lldd_query_task = pm8001_query_task,
100};
101
102/**
103 *pm8001_phy_init - initiate our adapter phys
104 *@pm8001_ha: our hba structure.
105 *@phy_id: phy id.
106 */
107static void __devinit pm8001_phy_init(struct pm8001_hba_info *pm8001_ha,
108 int phy_id)
109{
110 struct pm8001_phy *phy = &pm8001_ha->phy[phy_id];
111 struct asd_sas_phy *sas_phy = &phy->sas_phy;
112 phy->phy_state = 0;
113 phy->pm8001_ha = pm8001_ha;
114 sas_phy->enabled = (phy_id < pm8001_ha->chip->n_phy) ? 1 : 0;
115 sas_phy->class = SAS;
116 sas_phy->iproto = SAS_PROTOCOL_ALL;
117 sas_phy->tproto = 0;
118 sas_phy->type = PHY_TYPE_PHYSICAL;
119 sas_phy->role = PHY_ROLE_INITIATOR;
120 sas_phy->oob_mode = OOB_NOT_CONNECTED;
121 sas_phy->linkrate = SAS_LINK_RATE_UNKNOWN;
122 sas_phy->id = phy_id;
123 sas_phy->sas_addr = &pm8001_ha->sas_addr[0];
124 sas_phy->frame_rcvd = &phy->frame_rcvd[0];
125 sas_phy->ha = (struct sas_ha_struct *)pm8001_ha->shost->hostdata;
126 sas_phy->lldd_phy = phy;
127}
128
129/**
130 *pm8001_free - free hba
131 *@pm8001_ha: our hba structure.
132 *
133 */
134static void pm8001_free(struct pm8001_hba_info *pm8001_ha)
135{
136 int i;
137 struct pm8001_wq *wq;
138
139 if (!pm8001_ha)
140 return;
141
142 for (i = 0; i < USI_MAX_MEMCNT; i++) {
143 if (pm8001_ha->memoryMap.region[i].virt_ptr != NULL) {
144 pci_free_consistent(pm8001_ha->pdev,
145 pm8001_ha->memoryMap.region[i].element_size,
146 pm8001_ha->memoryMap.region[i].virt_ptr,
147 pm8001_ha->memoryMap.region[i].phys_addr);
148 }
149 }
150 PM8001_CHIP_DISP->chip_iounmap(pm8001_ha);
151 if (pm8001_ha->shost)
152 scsi_host_put(pm8001_ha->shost);
153 list_for_each_entry(wq, &pm8001_ha->wq_list, entry)
154 cancel_delayed_work(&wq->work_q);
155 kfree(pm8001_ha->tags);
156 kfree(pm8001_ha);
157}
158
159#ifdef PM8001_USE_TASKLET
160static void pm8001_tasklet(unsigned long opaque)
161{
162 struct pm8001_hba_info *pm8001_ha;
163 pm8001_ha = (struct pm8001_hba_info *)opaque;;
164 if (unlikely(!pm8001_ha))
165 BUG_ON(1);
166 PM8001_CHIP_DISP->isr(pm8001_ha);
167}
168#endif
169
170
171 /**
172 * pm8001_interrupt - when HBA originate a interrupt,we should invoke this
173 * dispatcher to handle each case.
174 * @irq: irq number.
175 * @opaque: the passed general host adapter struct
176 */
177static irqreturn_t pm8001_interrupt(int irq, void *opaque)
178{
179 struct pm8001_hba_info *pm8001_ha;
180 irqreturn_t ret = IRQ_HANDLED;
181 struct sas_ha_struct *sha = opaque;
182 pm8001_ha = sha->lldd_ha;
183 if (unlikely(!pm8001_ha))
184 return IRQ_NONE;
185 if (!PM8001_CHIP_DISP->is_our_interupt(pm8001_ha))
186 return IRQ_NONE;
187#ifdef PM8001_USE_TASKLET
188 tasklet_schedule(&pm8001_ha->tasklet);
189#else
190 ret = PM8001_CHIP_DISP->isr(pm8001_ha);
191#endif
192 return ret;
193}
194
195/**
196 * pm8001_alloc - initiate our hba structure and 6 DMAs area.
197 * @pm8001_ha:our hba structure.
198 *
199 */
200static int __devinit pm8001_alloc(struct pm8001_hba_info *pm8001_ha)
201{
202 int i;
203 spin_lock_init(&pm8001_ha->lock);
204 for (i = 0; i < pm8001_ha->chip->n_phy; i++) {
205 pm8001_phy_init(pm8001_ha, i);
206 pm8001_ha->port[i].wide_port_phymap = 0;
207 pm8001_ha->port[i].port_attached = 0;
208 pm8001_ha->port[i].port_state = 0;
209 INIT_LIST_HEAD(&pm8001_ha->port[i].list);
210 }
211
212 pm8001_ha->tags = kzalloc(PM8001_MAX_CCB, GFP_KERNEL);
213 if (!pm8001_ha->tags)
214 goto err_out;
215 /* MPI Memory region 1 for AAP Event Log for fw */
216 pm8001_ha->memoryMap.region[AAP1].num_elements = 1;
217 pm8001_ha->memoryMap.region[AAP1].element_size = PM8001_EVENT_LOG_SIZE;
218 pm8001_ha->memoryMap.region[AAP1].total_len = PM8001_EVENT_LOG_SIZE;
219 pm8001_ha->memoryMap.region[AAP1].alignment = 32;
220
221 /* MPI Memory region 2 for IOP Event Log for fw */
222 pm8001_ha->memoryMap.region[IOP].num_elements = 1;
223 pm8001_ha->memoryMap.region[IOP].element_size = PM8001_EVENT_LOG_SIZE;
224 pm8001_ha->memoryMap.region[IOP].total_len = PM8001_EVENT_LOG_SIZE;
225 pm8001_ha->memoryMap.region[IOP].alignment = 32;
226
227 /* MPI Memory region 3 for consumer Index of inbound queues */
228 pm8001_ha->memoryMap.region[CI].num_elements = 1;
229 pm8001_ha->memoryMap.region[CI].element_size = 4;
230 pm8001_ha->memoryMap.region[CI].total_len = 4;
231 pm8001_ha->memoryMap.region[CI].alignment = 4;
232
233 /* MPI Memory region 4 for producer Index of outbound queues */
234 pm8001_ha->memoryMap.region[PI].num_elements = 1;
235 pm8001_ha->memoryMap.region[PI].element_size = 4;
236 pm8001_ha->memoryMap.region[PI].total_len = 4;
237 pm8001_ha->memoryMap.region[PI].alignment = 4;
238
239 /* MPI Memory region 5 inbound queues */
240 pm8001_ha->memoryMap.region[IB].num_elements = 256;
241 pm8001_ha->memoryMap.region[IB].element_size = 64;
242 pm8001_ha->memoryMap.region[IB].total_len = 256 * 64;
243 pm8001_ha->memoryMap.region[IB].alignment = 64;
244
245 /* MPI Memory region 6 inbound queues */
246 pm8001_ha->memoryMap.region[OB].num_elements = 256;
247 pm8001_ha->memoryMap.region[OB].element_size = 64;
248 pm8001_ha->memoryMap.region[OB].total_len = 256 * 64;
249 pm8001_ha->memoryMap.region[OB].alignment = 64;
250
251 /* Memory region write DMA*/
252 pm8001_ha->memoryMap.region[NVMD].num_elements = 1;
253 pm8001_ha->memoryMap.region[NVMD].element_size = 4096;
254 pm8001_ha->memoryMap.region[NVMD].total_len = 4096;
255 /* Memory region for devices*/
256 pm8001_ha->memoryMap.region[DEV_MEM].num_elements = 1;
257 pm8001_ha->memoryMap.region[DEV_MEM].element_size = PM8001_MAX_DEVICES *
258 sizeof(struct pm8001_device);
259 pm8001_ha->memoryMap.region[DEV_MEM].total_len = PM8001_MAX_DEVICES *
260 sizeof(struct pm8001_device);
261
262 /* Memory region for ccb_info*/
263 pm8001_ha->memoryMap.region[CCB_MEM].num_elements = 1;
264 pm8001_ha->memoryMap.region[CCB_MEM].element_size = PM8001_MAX_CCB *
265 sizeof(struct pm8001_ccb_info);
266 pm8001_ha->memoryMap.region[CCB_MEM].total_len = PM8001_MAX_CCB *
267 sizeof(struct pm8001_ccb_info);
268
269 for (i = 0; i < USI_MAX_MEMCNT; i++) {
270 if (pm8001_mem_alloc(pm8001_ha->pdev,
271 &pm8001_ha->memoryMap.region[i].virt_ptr,
272 &pm8001_ha->memoryMap.region[i].phys_addr,
273 &pm8001_ha->memoryMap.region[i].phys_addr_hi,
274 &pm8001_ha->memoryMap.region[i].phys_addr_lo,
275 pm8001_ha->memoryMap.region[i].total_len,
276 pm8001_ha->memoryMap.region[i].alignment) != 0) {
277 PM8001_FAIL_DBG(pm8001_ha,
278 pm8001_printk("Mem%d alloc failed\n",
279 i));
280 goto err_out;
281 }
282 }
283
284 pm8001_ha->devices = pm8001_ha->memoryMap.region[DEV_MEM].virt_ptr;
285 for (i = 0; i < PM8001_MAX_DEVICES; i++) {
286 pm8001_ha->devices[i].dev_type = NO_DEVICE;
287 pm8001_ha->devices[i].id = i;
288 pm8001_ha->devices[i].device_id = PM8001_MAX_DEVICES;
289 pm8001_ha->devices[i].running_req = 0;
290 }
291 pm8001_ha->ccb_info = pm8001_ha->memoryMap.region[CCB_MEM].virt_ptr;
292 for (i = 0; i < PM8001_MAX_CCB; i++) {
293 pm8001_ha->ccb_info[i].ccb_dma_handle =
294 pm8001_ha->memoryMap.region[CCB_MEM].phys_addr +
295 i * sizeof(struct pm8001_ccb_info);
296 pm8001_ha->ccb_info[i].task = NULL;
297 pm8001_ha->ccb_info[i].ccb_tag = 0xffffffff;
298 pm8001_ha->ccb_info[i].device = NULL;
299 ++pm8001_ha->tags_num;
300 }
301 pm8001_ha->flags = PM8001F_INIT_TIME;
302 /* Initialize tags */
303 pm8001_tag_init(pm8001_ha);
304 return 0;
305err_out:
306 return 1;
307}
308
309/**
310 * pm8001_ioremap - remap the pci high physical address to kernal virtual
311 * address so that we can access them.
312 * @pm8001_ha:our hba structure.
313 */
314static int pm8001_ioremap(struct pm8001_hba_info *pm8001_ha)
315{
316 u32 bar;
317 u32 logicalBar = 0;
318 struct pci_dev *pdev;
319
320 pdev = pm8001_ha->pdev;
321 /* map pci mem (PMC pci base 0-3)*/
322 for (bar = 0; bar < 6; bar++) {
323 /*
324 ** logical BARs for SPC:
325 ** bar 0 and 1 - logical BAR0
326 ** bar 2 and 3 - logical BAR1
327 ** bar4 - logical BAR2
328 ** bar5 - logical BAR3
329 ** Skip the appropriate assignments:
330 */
331 if ((bar == 1) || (bar == 3))
332 continue;
333 if (pci_resource_flags(pdev, bar) & IORESOURCE_MEM) {
334 pm8001_ha->io_mem[logicalBar].membase =
335 pci_resource_start(pdev, bar);
336 pm8001_ha->io_mem[logicalBar].membase &=
337 (u32)PCI_BASE_ADDRESS_MEM_MASK;
338 pm8001_ha->io_mem[logicalBar].memsize =
339 pci_resource_len(pdev, bar);
340 pm8001_ha->io_mem[logicalBar].memvirtaddr =
341 ioremap(pm8001_ha->io_mem[logicalBar].membase,
342 pm8001_ha->io_mem[logicalBar].memsize);
343 PM8001_INIT_DBG(pm8001_ha,
344 pm8001_printk("PCI: bar %d, logicalBar %d "
345 "virt_addr=%lx,len=%d\n", bar, logicalBar,
346 (unsigned long)
347 pm8001_ha->io_mem[logicalBar].memvirtaddr,
348 pm8001_ha->io_mem[logicalBar].memsize));
349 } else {
350 pm8001_ha->io_mem[logicalBar].membase = 0;
351 pm8001_ha->io_mem[logicalBar].memsize = 0;
352 pm8001_ha->io_mem[logicalBar].memvirtaddr = 0;
353 }
354 logicalBar++;
355 }
356 return 0;
357}
358
359/**
360 * pm8001_pci_alloc - initialize our ha card structure
361 * @pdev: pci device.
362 * @ent: ent
363 * @shost: scsi host struct which has been initialized before.
364 */
365static struct pm8001_hba_info *__devinit
366pm8001_pci_alloc(struct pci_dev *pdev, u32 chip_id, struct Scsi_Host *shost)
367{
368 struct pm8001_hba_info *pm8001_ha;
369 struct sas_ha_struct *sha = SHOST_TO_SAS_HA(shost);
370
371
372 pm8001_ha = sha->lldd_ha;
373 if (!pm8001_ha)
374 return NULL;
375
376 pm8001_ha->pdev = pdev;
377 pm8001_ha->dev = &pdev->dev;
378 pm8001_ha->chip_id = chip_id;
379 pm8001_ha->chip = &pm8001_chips[pm8001_ha->chip_id];
380 pm8001_ha->irq = pdev->irq;
381 pm8001_ha->sas = sha;
382 pm8001_ha->shost = shost;
383 pm8001_ha->id = pm8001_id++;
384 INIT_LIST_HEAD(&pm8001_ha->wq_list);
385 pm8001_ha->logging_level = 0x01;
386 sprintf(pm8001_ha->name, "%s%d", DRV_NAME, pm8001_ha->id);
387#ifdef PM8001_USE_TASKLET
388 tasklet_init(&pm8001_ha->tasklet, pm8001_tasklet,
389 (unsigned long)pm8001_ha);
390#endif
391 pm8001_ioremap(pm8001_ha);
392 if (!pm8001_alloc(pm8001_ha))
393 return pm8001_ha;
394 pm8001_free(pm8001_ha);
395 return NULL;
396}
397
398/**
399 * pci_go_44 - pm8001 specified, its DMA is 44 bit rather than 64 bit
400 * @pdev: pci device.
401 */
402static int pci_go_44(struct pci_dev *pdev)
403{
404 int rc;
405
406 if (!pci_set_dma_mask(pdev, DMA_BIT_MASK(44))) {
407 rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(44));
408 if (rc) {
409 rc = pci_set_consistent_dma_mask(pdev,
410 DMA_BIT_MASK(32));
411 if (rc) {
412 dev_printk(KERN_ERR, &pdev->dev,
413 "44-bit DMA enable failed\n");
414 return rc;
415 }
416 }
417 } else {
418 rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
419 if (rc) {
420 dev_printk(KERN_ERR, &pdev->dev,
421 "32-bit DMA enable failed\n");
422 return rc;
423 }
424 rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
425 if (rc) {
426 dev_printk(KERN_ERR, &pdev->dev,
427 "32-bit consistent DMA enable failed\n");
428 return rc;
429 }
430 }
431 return rc;
432}
433
434/**
435 * pm8001_prep_sas_ha_init - allocate memory in general hba struct && init them.
436 * @shost: scsi host which has been allocated outside.
437 * @chip_info: our ha struct.
438 */
439static int __devinit pm8001_prep_sas_ha_init(struct Scsi_Host * shost,
440 const struct pm8001_chip_info *chip_info)
441{
442 int phy_nr, port_nr;
443 struct asd_sas_phy **arr_phy;
444 struct asd_sas_port **arr_port;
445 struct sas_ha_struct *sha = SHOST_TO_SAS_HA(shost);
446
447 phy_nr = chip_info->n_phy;
448 port_nr = phy_nr;
449 memset(sha, 0x00, sizeof(*sha));
450 arr_phy = kcalloc(phy_nr, sizeof(void *), GFP_KERNEL);
451 if (!arr_phy)
452 goto exit;
453 arr_port = kcalloc(port_nr, sizeof(void *), GFP_KERNEL);
454 if (!arr_port)
455 goto exit_free2;
456
457 sha->sas_phy = arr_phy;
458 sha->sas_port = arr_port;
459 sha->lldd_ha = kzalloc(sizeof(struct pm8001_hba_info), GFP_KERNEL);
460 if (!sha->lldd_ha)
461 goto exit_free1;
462
463 shost->transportt = pm8001_stt;
464 shost->max_id = PM8001_MAX_DEVICES;
465 shost->max_lun = 8;
466 shost->max_channel = 0;
467 shost->unique_id = pm8001_id;
468 shost->max_cmd_len = 16;
469 shost->can_queue = PM8001_CAN_QUEUE;
470 shost->cmd_per_lun = 32;
471 return 0;
472exit_free1:
473 kfree(arr_port);
474exit_free2:
475 kfree(arr_phy);
476exit:
477 return -1;
478}
479
480/**
481 * pm8001_post_sas_ha_init - initialize general hba struct defined in libsas
482 * @shost: scsi host which has been allocated outside
483 * @chip_info: our ha struct.
484 */
485static void __devinit pm8001_post_sas_ha_init(struct Scsi_Host *shost,
486 const struct pm8001_chip_info *chip_info)
487{
488 int i = 0;
489 struct pm8001_hba_info *pm8001_ha;
490 struct sas_ha_struct *sha = SHOST_TO_SAS_HA(shost);
491
492 pm8001_ha = sha->lldd_ha;
493 for (i = 0; i < chip_info->n_phy; i++) {
494 sha->sas_phy[i] = &pm8001_ha->phy[i].sas_phy;
495 sha->sas_port[i] = &pm8001_ha->port[i].sas_port;
496 }
497 sha->sas_ha_name = DRV_NAME;
498 sha->dev = pm8001_ha->dev;
499
500 sha->lldd_module = THIS_MODULE;
501 sha->sas_addr = &pm8001_ha->sas_addr[0];
502 sha->num_phys = chip_info->n_phy;
503 sha->lldd_max_execute_num = 1;
504 sha->lldd_queue_size = PM8001_CAN_QUEUE;
505 sha->core.shost = shost;
506}
507
508/**
509 * pm8001_init_sas_add - initialize sas address
510 * @chip_info: our ha struct.
511 *
512 * Currently we just set the fixed SAS address to our HBA,for manufacture,
513 * it should read from the EEPROM
514 */
515static void pm8001_init_sas_add(struct pm8001_hba_info *pm8001_ha)
516{
517 u8 i;
518#ifdef PM8001_READ_VPD
519 DECLARE_COMPLETION_ONSTACK(completion);
520 struct pm8001_ioctl_payload payload;
521 pm8001_ha->nvmd_completion = &completion;
522 payload.minor_function = 0;
523 payload.length = 128;
524 payload.func_specific = kzalloc(128, GFP_KERNEL);
525 PM8001_CHIP_DISP->get_nvmd_req(pm8001_ha, &payload);
526 wait_for_completion(&completion);
527 for (i = 0; i < pm8001_ha->chip->n_phy; i++) {
528 memcpy(&pm8001_ha->phy[i].dev_sas_addr, pm8001_ha->sas_addr,
529 SAS_ADDR_SIZE);
530 PM8001_INIT_DBG(pm8001_ha,
531 pm8001_printk("phy %d sas_addr = %016llx \n", i,
532 pm8001_ha->phy[i].dev_sas_addr));
533 }
534#else
535 for (i = 0; i < pm8001_ha->chip->n_phy; i++) {
536 pm8001_ha->phy[i].dev_sas_addr = 0x50010c600047f9d0ULL;
537 pm8001_ha->phy[i].dev_sas_addr =
538 cpu_to_be64((u64)
539 (*(u64 *)&pm8001_ha->phy[i].dev_sas_addr));
540 }
541 memcpy(pm8001_ha->sas_addr, &pm8001_ha->phy[0].dev_sas_addr,
542 SAS_ADDR_SIZE);
543#endif
544}
545
546#ifdef PM8001_USE_MSIX
547/**
548 * pm8001_setup_msix - enable MSI-X interrupt
549 * @chip_info: our ha struct.
550 * @irq_handler: irq_handler
551 */
552static u32 pm8001_setup_msix(struct pm8001_hba_info *pm8001_ha,
553 irq_handler_t irq_handler)
554{
555 u32 i = 0, j = 0;
556 u32 number_of_intr = 1;
557 int flag = 0;
558 u32 max_entry;
559 int rc;
560 max_entry = sizeof(pm8001_ha->msix_entries) /
561 sizeof(pm8001_ha->msix_entries[0]);
562 flag |= IRQF_DISABLED;
563 for (i = 0; i < max_entry ; i++)
564 pm8001_ha->msix_entries[i].entry = i;
565 rc = pci_enable_msix(pm8001_ha->pdev, pm8001_ha->msix_entries,
566 number_of_intr);
567 pm8001_ha->number_of_intr = number_of_intr;
568 if (!rc) {
569 for (i = 0; i < number_of_intr; i++) {
570 if (request_irq(pm8001_ha->msix_entries[i].vector,
571 irq_handler, flag, DRV_NAME,
572 SHOST_TO_SAS_HA(pm8001_ha->shost))) {
573 for (j = 0; j < i; j++)
574 free_irq(
575 pm8001_ha->msix_entries[j].vector,
576 SHOST_TO_SAS_HA(pm8001_ha->shost));
577 pci_disable_msix(pm8001_ha->pdev);
578 break;
579 }
580 }
581 }
582 return rc;
583}
584#endif
585
586/**
587 * pm8001_request_irq - register interrupt
588 * @chip_info: our ha struct.
589 */
590static u32 pm8001_request_irq(struct pm8001_hba_info *pm8001_ha)
591{
592 struct pci_dev *pdev;
593 irq_handler_t irq_handler = pm8001_interrupt;
594 int rc;
595
596 pdev = pm8001_ha->pdev;
597
598#ifdef PM8001_USE_MSIX
599 if (pci_find_capability(pdev, PCI_CAP_ID_MSIX))
600 return pm8001_setup_msix(pm8001_ha, irq_handler);
601 else
602 goto intx;
603#endif
604
605intx:
606 /* intialize the INT-X interrupt */
607 rc = request_irq(pdev->irq, irq_handler, IRQF_SHARED, DRV_NAME,
608 SHOST_TO_SAS_HA(pm8001_ha->shost));
609 return rc;
610}
611
612/**
613 * pm8001_pci_probe - probe supported device
614 * @pdev: pci device which kernel has been prepared for.
615 * @ent: pci device id
616 *
617 * This function is the main initialization function, when register a new
618 * pci driver it is invoked, all struct an hardware initilization should be done
619 * here, also, register interrupt
620 */
621static int __devinit pm8001_pci_probe(struct pci_dev *pdev,
622 const struct pci_device_id *ent)
623{
624 unsigned int rc;
625 u32 pci_reg;
626 struct pm8001_hba_info *pm8001_ha;
627 struct Scsi_Host *shost = NULL;
628 const struct pm8001_chip_info *chip;
629
630 dev_printk(KERN_INFO, &pdev->dev,
631 "pm8001: driver version %s\n", DRV_VERSION);
632 rc = pci_enable_device(pdev);
633 if (rc)
634 goto err_out_enable;
635 pci_set_master(pdev);
636 /*
637 * Enable pci slot busmaster by setting pci command register.
638 * This is required by FW for Cyclone card.
639 */
640
641 pci_read_config_dword(pdev, PCI_COMMAND, &pci_reg);
642 pci_reg |= 0x157;
643 pci_write_config_dword(pdev, PCI_COMMAND, pci_reg);
644 rc = pci_request_regions(pdev, DRV_NAME);
645 if (rc)
646 goto err_out_disable;
647 rc = pci_go_44(pdev);
648 if (rc)
649 goto err_out_regions;
650
651 shost = scsi_host_alloc(&pm8001_sht, sizeof(void *));
652 if (!shost) {
653 rc = -ENOMEM;
654 goto err_out_regions;
655 }
656 chip = &pm8001_chips[ent->driver_data];
657 SHOST_TO_SAS_HA(shost) =
658 kzalloc(sizeof(struct sas_ha_struct), GFP_KERNEL);
659 if (!SHOST_TO_SAS_HA(shost)) {
660 rc = -ENOMEM;
661 goto err_out_free_host;
662 }
663
664 rc = pm8001_prep_sas_ha_init(shost, chip);
665 if (rc) {
666 rc = -ENOMEM;
667 goto err_out_free;
668 }
669 pci_set_drvdata(pdev, SHOST_TO_SAS_HA(shost));
670 pm8001_ha = pm8001_pci_alloc(pdev, chip_8001, shost);
671 if (!pm8001_ha) {
672 rc = -ENOMEM;
673 goto err_out_free;
674 }
675 list_add_tail(&pm8001_ha->list, &hba_list);
676 PM8001_CHIP_DISP->chip_soft_rst(pm8001_ha, 0x252acbcd);
677 rc = PM8001_CHIP_DISP->chip_init(pm8001_ha);
678 if (rc)
679 goto err_out_ha_free;
680
681 rc = scsi_add_host(shost, &pdev->dev);
682 if (rc)
683 goto err_out_ha_free;
684 rc = pm8001_request_irq(pm8001_ha);
685 if (rc)
686 goto err_out_shost;
687
688 PM8001_CHIP_DISP->interrupt_enable(pm8001_ha);
689 pm8001_init_sas_add(pm8001_ha);
690 pm8001_post_sas_ha_init(shost, chip);
691 rc = sas_register_ha(SHOST_TO_SAS_HA(shost));
692 if (rc)
693 goto err_out_shost;
694 scsi_scan_host(pm8001_ha->shost);
695 return 0;
696
697err_out_shost:
698 scsi_remove_host(pm8001_ha->shost);
699err_out_ha_free:
700 pm8001_free(pm8001_ha);
701err_out_free:
702 kfree(SHOST_TO_SAS_HA(shost));
703err_out_free_host:
704 kfree(shost);
705err_out_regions:
706 pci_release_regions(pdev);
707err_out_disable:
708 pci_disable_device(pdev);
709err_out_enable:
710 return rc;
711}
712
713static void __devexit pm8001_pci_remove(struct pci_dev *pdev)
714{
715 struct sas_ha_struct *sha = pci_get_drvdata(pdev);
716 struct pm8001_hba_info *pm8001_ha;
717 int i;
718 pm8001_ha = sha->lldd_ha;
719 pci_set_drvdata(pdev, NULL);
720 sas_unregister_ha(sha);
721 sas_remove_host(pm8001_ha->shost);
722 list_del(&pm8001_ha->list);
723 scsi_remove_host(pm8001_ha->shost);
724 PM8001_CHIP_DISP->interrupt_disable(pm8001_ha);
725 PM8001_CHIP_DISP->chip_soft_rst(pm8001_ha, 0x252acbcd);
726
727#ifdef PM8001_USE_MSIX
728 for (i = 0; i < pm8001_ha->number_of_intr; i++)
729 synchronize_irq(pm8001_ha->msix_entries[i].vector);
730 for (i = 0; i < pm8001_ha->number_of_intr; i++)
731 free_irq(pm8001_ha->msix_entries[i].vector, sha);
732 pci_disable_msix(pdev);
733#else
734 free_irq(pm8001_ha->irq, sha);
735#endif
736#ifdef PM8001_USE_TASKLET
737 tasklet_kill(&pm8001_ha->tasklet);
738#endif
739 pm8001_free(pm8001_ha);
740 kfree(sha->sas_phy);
741 kfree(sha->sas_port);
742 kfree(sha);
743 pci_release_regions(pdev);
744 pci_disable_device(pdev);
745}
746
747/**
748 * pm8001_pci_suspend - power management suspend main entry point
749 * @pdev: PCI device struct
750 * @state: PM state change to (usually PCI_D3)
751 *
752 * Returns 0 success, anything else error.
753 */
754static int pm8001_pci_suspend(struct pci_dev *pdev, pm_message_t state)
755{
756 struct sas_ha_struct *sha = pci_get_drvdata(pdev);
757 struct pm8001_hba_info *pm8001_ha;
758 int i , pos;
759 u32 device_state;
760 pm8001_ha = sha->lldd_ha;
761 flush_scheduled_work();
762 scsi_block_requests(pm8001_ha->shost);
763 pos = pci_find_capability(pdev, PCI_CAP_ID_PM);
764 if (pos == 0) {
765 printk(KERN_ERR " PCI PM not supported\n");
766 return -ENODEV;
767 }
768 PM8001_CHIP_DISP->interrupt_disable(pm8001_ha);
769 PM8001_CHIP_DISP->chip_soft_rst(pm8001_ha, 0x252acbcd);
770#ifdef PM8001_USE_MSIX
771 for (i = 0; i < pm8001_ha->number_of_intr; i++)
772 synchronize_irq(pm8001_ha->msix_entries[i].vector);
773 for (i = 0; i < pm8001_ha->number_of_intr; i++)
774 free_irq(pm8001_ha->msix_entries[i].vector, sha);
775 pci_disable_msix(pdev);
776#else
777 free_irq(pm8001_ha->irq, sha);
778#endif
779#ifdef PM8001_USE_TASKLET
780 tasklet_kill(&pm8001_ha->tasklet);
781#endif
782 device_state = pci_choose_state(pdev, state);
783 pm8001_printk("pdev=0x%p, slot=%s, entering "
784 "operating state [D%d]\n", pdev,
785 pm8001_ha->name, device_state);
786 pci_save_state(pdev);
787 pci_disable_device(pdev);
788 pci_set_power_state(pdev, device_state);
789 return 0;
790}
791
792/**
793 * pm8001_pci_resume - power management resume main entry point
794 * @pdev: PCI device struct
795 *
796 * Returns 0 success, anything else error.
797 */
798static int pm8001_pci_resume(struct pci_dev *pdev)
799{
800 struct sas_ha_struct *sha = pci_get_drvdata(pdev);
801 struct pm8001_hba_info *pm8001_ha;
802 int rc;
803 u32 device_state;
804 pm8001_ha = sha->lldd_ha;
805 device_state = pdev->current_state;
806
807 pm8001_printk("pdev=0x%p, slot=%s, resuming from previous "
808 "operating state [D%d]\n", pdev, pm8001_ha->name, device_state);
809
810 pci_set_power_state(pdev, PCI_D0);
811 pci_enable_wake(pdev, PCI_D0, 0);
812 pci_restore_state(pdev);
813 rc = pci_enable_device(pdev);
814 if (rc) {
815 pm8001_printk("slot=%s Enable device failed during resume\n",
816 pm8001_ha->name);
817 goto err_out_enable;
818 }
819
820 pci_set_master(pdev);
821 rc = pci_go_44(pdev);
822 if (rc)
823 goto err_out_disable;
824
825 PM8001_CHIP_DISP->chip_soft_rst(pm8001_ha, 0x252acbcd);
826 rc = PM8001_CHIP_DISP->chip_init(pm8001_ha);
827 if (rc)
828 goto err_out_disable;
829 PM8001_CHIP_DISP->interrupt_disable(pm8001_ha);
830 rc = pm8001_request_irq(pm8001_ha);
831 if (rc)
832 goto err_out_disable;
833 #ifdef PM8001_USE_TASKLET
834 tasklet_init(&pm8001_ha->tasklet, pm8001_tasklet,
835 (unsigned long)pm8001_ha);
836 #endif
837 PM8001_CHIP_DISP->interrupt_enable(pm8001_ha);
838 scsi_unblock_requests(pm8001_ha->shost);
839 return 0;
840
841err_out_disable:
842 scsi_remove_host(pm8001_ha->shost);
843 pci_disable_device(pdev);
844err_out_enable:
845 return rc;
846}
847
848static struct pci_device_id __devinitdata pm8001_pci_table[] = {
849 {
850 PCI_VDEVICE(PMC_Sierra, 0x8001), chip_8001
851 },
852 {
853 PCI_DEVICE(0x117c, 0x0042),
854 .driver_data = chip_8001
855 },
856 {} /* terminate list */
857};
858
859static struct pci_driver pm8001_pci_driver = {
860 .name = DRV_NAME,
861 .id_table = pm8001_pci_table,
862 .probe = pm8001_pci_probe,
863 .remove = __devexit_p(pm8001_pci_remove),
864 .suspend = pm8001_pci_suspend,
865 .resume = pm8001_pci_resume,
866};
867
868/**
869 * pm8001_init - initialize scsi transport template
870 */
871static int __init pm8001_init(void)
872{
873 int rc;
874 pm8001_id = 0;
875 pm8001_stt = sas_domain_attach_transport(&pm8001_transport_ops);
876 if (!pm8001_stt)
877 return -ENOMEM;
878 rc = pci_register_driver(&pm8001_pci_driver);
879 if (rc)
880 goto err_out;
881 return 0;
882err_out:
883 sas_release_transport(pm8001_stt);
884 return rc;
885}
886
887static void __exit pm8001_exit(void)
888{
889 pci_unregister_driver(&pm8001_pci_driver);
890 sas_release_transport(pm8001_stt);
891}
892
893module_init(pm8001_init);
894module_exit(pm8001_exit);
895
896MODULE_AUTHOR("Jack Wang <jack_wang@usish.com>");
897MODULE_DESCRIPTION("PMC-Sierra PM8001 SAS/SATA controller driver");
898MODULE_VERSION(DRV_VERSION);
899MODULE_LICENSE("GPL");
900MODULE_DEVICE_TABLE(pci, pm8001_pci_table);
901
diff --git a/drivers/scsi/pm8001/pm8001_sas.c b/drivers/scsi/pm8001/pm8001_sas.c
new file mode 100644
index 000000000000..bff4f5139b9c
--- /dev/null
+++ b/drivers/scsi/pm8001/pm8001_sas.c
@@ -0,0 +1,1153 @@
1/*
2 * PMC-Sierra SPC 8001 SAS/SATA based host adapters driver
3 *
4 * Copyright (c) 2008-2009 USI Co., Ltd.
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions, and the following disclaimer,
12 * without modification.
13 * 2. Redistributions in binary form must reproduce at minimum a disclaimer
14 * substantially similar to the "NO WARRANTY" disclaimer below
15 * ("Disclaimer") and any redistribution must be conditioned upon
16 * including a substantially similar Disclaimer requirement for further
17 * binary redistribution.
18 * 3. Neither the names of the above-listed copyright holders nor the names
19 * of any contributors may be used to endorse or promote products derived
20 * from this software without specific prior written permission.
21 *
22 * Alternatively, this software may be distributed under the terms of the
23 * GNU General Public License ("GPL") version 2 as published by the Free
24 * Software Foundation.
25 *
26 * NO WARRANTY
27 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
28 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
29 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR
30 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
31 * HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
32 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
33 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
34 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
35 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
36 * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
37 * POSSIBILITY OF SUCH DAMAGES.
38 *
39 */
40
41#include <linux/slab.h>
42#include "pm8001_sas.h"
43
44/**
45 * pm8001_find_tag - from sas task to find out tag that belongs to this task
46 * @task: the task sent to the LLDD
47 * @tag: the found tag associated with the task
48 */
49static int pm8001_find_tag(struct sas_task *task, u32 *tag)
50{
51 if (task->lldd_task) {
52 struct pm8001_ccb_info *ccb;
53 ccb = task->lldd_task;
54 *tag = ccb->ccb_tag;
55 return 1;
56 }
57 return 0;
58}
59
60/**
61 * pm8001_tag_clear - clear the tags bitmap
62 * @pm8001_ha: our hba struct
63 * @tag: the found tag associated with the task
64 */
65static void pm8001_tag_clear(struct pm8001_hba_info *pm8001_ha, u32 tag)
66{
67 void *bitmap = pm8001_ha->tags;
68 clear_bit(tag, bitmap);
69}
70
71static void pm8001_tag_free(struct pm8001_hba_info *pm8001_ha, u32 tag)
72{
73 pm8001_tag_clear(pm8001_ha, tag);
74}
75
76static void pm8001_tag_set(struct pm8001_hba_info *pm8001_ha, u32 tag)
77{
78 void *bitmap = pm8001_ha->tags;
79 set_bit(tag, bitmap);
80}
81
82/**
83 * pm8001_tag_alloc - allocate a empty tag for task used.
84 * @pm8001_ha: our hba struct
85 * @tag_out: the found empty tag .
86 */
87inline int pm8001_tag_alloc(struct pm8001_hba_info *pm8001_ha, u32 *tag_out)
88{
89 unsigned int index, tag;
90 void *bitmap = pm8001_ha->tags;
91
92 index = find_first_zero_bit(bitmap, pm8001_ha->tags_num);
93 tag = index;
94 if (tag >= pm8001_ha->tags_num)
95 return -SAS_QUEUE_FULL;
96 pm8001_tag_set(pm8001_ha, tag);
97 *tag_out = tag;
98 return 0;
99}
100
101void pm8001_tag_init(struct pm8001_hba_info *pm8001_ha)
102{
103 int i;
104 for (i = 0; i < pm8001_ha->tags_num; ++i)
105 pm8001_tag_clear(pm8001_ha, i);
106}
107
108 /**
109 * pm8001_mem_alloc - allocate memory for pm8001.
110 * @pdev: pci device.
111 * @virt_addr: the allocated virtual address
112 * @pphys_addr_hi: the physical address high byte address.
113 * @pphys_addr_lo: the physical address low byte address.
114 * @mem_size: memory size.
115 */
116int pm8001_mem_alloc(struct pci_dev *pdev, void **virt_addr,
117 dma_addr_t *pphys_addr, u32 *pphys_addr_hi,
118 u32 *pphys_addr_lo, u32 mem_size, u32 align)
119{
120 caddr_t mem_virt_alloc;
121 dma_addr_t mem_dma_handle;
122 u64 phys_align;
123 u64 align_offset = 0;
124 if (align)
125 align_offset = (dma_addr_t)align - 1;
126 mem_virt_alloc =
127 pci_alloc_consistent(pdev, mem_size + align, &mem_dma_handle);
128 if (!mem_virt_alloc) {
129 pm8001_printk("memory allocation error\n");
130 return -1;
131 }
132 memset((void *)mem_virt_alloc, 0, mem_size+align);
133 *pphys_addr = mem_dma_handle;
134 phys_align = (*pphys_addr + align_offset) & ~align_offset;
135 *virt_addr = (void *)mem_virt_alloc + phys_align - *pphys_addr;
136 *pphys_addr_hi = upper_32_bits(phys_align);
137 *pphys_addr_lo = lower_32_bits(phys_align);
138 return 0;
139}
140/**
141 * pm8001_find_ha_by_dev - from domain device which come from sas layer to
142 * find out our hba struct.
143 * @dev: the domain device which from sas layer.
144 */
145static
146struct pm8001_hba_info *pm8001_find_ha_by_dev(struct domain_device *dev)
147{
148 struct sas_ha_struct *sha = dev->port->ha;
149 struct pm8001_hba_info *pm8001_ha = sha->lldd_ha;
150 return pm8001_ha;
151}
152
153/**
154 * pm8001_phy_control - this function should be registered to
155 * sas_domain_function_template to provide libsas used, note: this is just
156 * control the HBA phy rather than other expander phy if you want control
157 * other phy, you should use SMP command.
158 * @sas_phy: which phy in HBA phys.
159 * @func: the operation.
160 * @funcdata: always NULL.
161 */
162int pm8001_phy_control(struct asd_sas_phy *sas_phy, enum phy_func func,
163 void *funcdata)
164{
165 int rc = 0, phy_id = sas_phy->id;
166 struct pm8001_hba_info *pm8001_ha = NULL;
167 struct sas_phy_linkrates *rates;
168 DECLARE_COMPLETION_ONSTACK(completion);
169 pm8001_ha = sas_phy->ha->lldd_ha;
170 pm8001_ha->phy[phy_id].enable_completion = &completion;
171 switch (func) {
172 case PHY_FUNC_SET_LINK_RATE:
173 rates = funcdata;
174 if (rates->minimum_linkrate) {
175 pm8001_ha->phy[phy_id].minimum_linkrate =
176 rates->minimum_linkrate;
177 }
178 if (rates->maximum_linkrate) {
179 pm8001_ha->phy[phy_id].maximum_linkrate =
180 rates->maximum_linkrate;
181 }
182 if (pm8001_ha->phy[phy_id].phy_state == 0) {
183 PM8001_CHIP_DISP->phy_start_req(pm8001_ha, phy_id);
184 wait_for_completion(&completion);
185 }
186 PM8001_CHIP_DISP->phy_ctl_req(pm8001_ha, phy_id,
187 PHY_LINK_RESET);
188 break;
189 case PHY_FUNC_HARD_RESET:
190 if (pm8001_ha->phy[phy_id].phy_state == 0) {
191 PM8001_CHIP_DISP->phy_start_req(pm8001_ha, phy_id);
192 wait_for_completion(&completion);
193 }
194 PM8001_CHIP_DISP->phy_ctl_req(pm8001_ha, phy_id,
195 PHY_HARD_RESET);
196 break;
197 case PHY_FUNC_LINK_RESET:
198 if (pm8001_ha->phy[phy_id].phy_state == 0) {
199 PM8001_CHIP_DISP->phy_start_req(pm8001_ha, phy_id);
200 wait_for_completion(&completion);
201 }
202 PM8001_CHIP_DISP->phy_ctl_req(pm8001_ha, phy_id,
203 PHY_LINK_RESET);
204 break;
205 case PHY_FUNC_RELEASE_SPINUP_HOLD:
206 PM8001_CHIP_DISP->phy_ctl_req(pm8001_ha, phy_id,
207 PHY_LINK_RESET);
208 break;
209 case PHY_FUNC_DISABLE:
210 PM8001_CHIP_DISP->phy_stop_req(pm8001_ha, phy_id);
211 break;
212 default:
213 rc = -EOPNOTSUPP;
214 }
215 msleep(300);
216 return rc;
217}
218
219int pm8001_slave_alloc(struct scsi_device *scsi_dev)
220{
221 struct domain_device *dev = sdev_to_domain_dev(scsi_dev);
222 if (dev_is_sata(dev)) {
223 /* We don't need to rescan targets
224 * if REPORT_LUNS request is failed
225 */
226 if (scsi_dev->lun > 0)
227 return -ENXIO;
228 scsi_dev->tagged_supported = 1;
229 }
230 return sas_slave_alloc(scsi_dev);
231}
232
233/**
234 * pm8001_scan_start - we should enable all HBA phys by sending the phy_start
235 * command to HBA.
236 * @shost: the scsi host data.
237 */
238void pm8001_scan_start(struct Scsi_Host *shost)
239{
240 int i;
241 struct pm8001_hba_info *pm8001_ha;
242 struct sas_ha_struct *sha = SHOST_TO_SAS_HA(shost);
243 pm8001_ha = sha->lldd_ha;
244 PM8001_CHIP_DISP->sas_re_init_req(pm8001_ha);
245 for (i = 0; i < pm8001_ha->chip->n_phy; ++i)
246 PM8001_CHIP_DISP->phy_start_req(pm8001_ha, i);
247}
248
249int pm8001_scan_finished(struct Scsi_Host *shost, unsigned long time)
250{
251 /* give the phy enabling interrupt event time to come in (1s
252 * is empirically about all it takes) */
253 if (time < HZ)
254 return 0;
255 /* Wait for discovery to finish */
256 scsi_flush_work(shost);
257 return 1;
258}
259
260/**
261 * pm8001_task_prep_smp - the dispatcher function, prepare data for smp task
262 * @pm8001_ha: our hba card information
263 * @ccb: the ccb which attached to smp task
264 */
265static int pm8001_task_prep_smp(struct pm8001_hba_info *pm8001_ha,
266 struct pm8001_ccb_info *ccb)
267{
268 return PM8001_CHIP_DISP->smp_req(pm8001_ha, ccb);
269}
270
271u32 pm8001_get_ncq_tag(struct sas_task *task, u32 *tag)
272{
273 struct ata_queued_cmd *qc = task->uldd_task;
274 if (qc) {
275 if (qc->tf.command == ATA_CMD_FPDMA_WRITE ||
276 qc->tf.command == ATA_CMD_FPDMA_READ) {
277 *tag = qc->tag;
278 return 1;
279 }
280 }
281 return 0;
282}
283
284/**
285 * pm8001_task_prep_ata - the dispatcher function, prepare data for sata task
286 * @pm8001_ha: our hba card information
287 * @ccb: the ccb which attached to sata task
288 */
289static int pm8001_task_prep_ata(struct pm8001_hba_info *pm8001_ha,
290 struct pm8001_ccb_info *ccb)
291{
292 return PM8001_CHIP_DISP->sata_req(pm8001_ha, ccb);
293}
294
295/**
296 * pm8001_task_prep_ssp_tm - the dispatcher function, prepare task management data
297 * @pm8001_ha: our hba card information
298 * @ccb: the ccb which attached to TM
299 * @tmf: the task management IU
300 */
301static int pm8001_task_prep_ssp_tm(struct pm8001_hba_info *pm8001_ha,
302 struct pm8001_ccb_info *ccb, struct pm8001_tmf_task *tmf)
303{
304 return PM8001_CHIP_DISP->ssp_tm_req(pm8001_ha, ccb, tmf);
305}
306
307/**
308 * pm8001_task_prep_ssp - the dispatcher function,prepare ssp data for ssp task
309 * @pm8001_ha: our hba card information
310 * @ccb: the ccb which attached to ssp task
311 */
312static int pm8001_task_prep_ssp(struct pm8001_hba_info *pm8001_ha,
313 struct pm8001_ccb_info *ccb)
314{
315 return PM8001_CHIP_DISP->ssp_io_req(pm8001_ha, ccb);
316}
317int pm8001_slave_configure(struct scsi_device *sdev)
318{
319 struct domain_device *dev = sdev_to_domain_dev(sdev);
320 int ret = sas_slave_configure(sdev);
321 if (ret)
322 return ret;
323 if (dev_is_sata(dev)) {
324 #ifdef PM8001_DISABLE_NCQ
325 struct ata_port *ap = dev->sata_dev.ap;
326 struct ata_device *adev = ap->link.device;
327 adev->flags |= ATA_DFLAG_NCQ_OFF;
328 scsi_adjust_queue_depth(sdev, MSG_SIMPLE_TAG, 1);
329 #endif
330 }
331 return 0;
332}
333 /* Find the local port id that's attached to this device */
334static int sas_find_local_port_id(struct domain_device *dev)
335{
336 struct domain_device *pdev = dev->parent;
337
338 /* Directly attached device */
339 if (!pdev)
340 return dev->port->id;
341 while (pdev) {
342 struct domain_device *pdev_p = pdev->parent;
343 if (!pdev_p)
344 return pdev->port->id;
345 pdev = pdev->parent;
346 }
347 return 0;
348}
349
350/**
351 * pm8001_task_exec - queue the task(ssp, smp && ata) to the hardware.
352 * @task: the task to be execute.
353 * @num: if can_queue great than 1, the task can be queued up. for SMP task,
354 * we always execute one one time.
355 * @gfp_flags: gfp_flags.
356 * @is_tmf: if it is task management task.
357 * @tmf: the task management IU
358 */
359#define DEV_IS_GONE(pm8001_dev) \
360 ((!pm8001_dev || (pm8001_dev->dev_type == NO_DEVICE)))
361static int pm8001_task_exec(struct sas_task *task, const int num,
362 gfp_t gfp_flags, int is_tmf, struct pm8001_tmf_task *tmf)
363{
364 struct domain_device *dev = task->dev;
365 struct pm8001_hba_info *pm8001_ha;
366 struct pm8001_device *pm8001_dev;
367 struct pm8001_port *port = NULL;
368 struct sas_task *t = task;
369 struct pm8001_ccb_info *ccb;
370 u32 tag = 0xdeadbeef, rc, n_elem = 0;
371 u32 n = num;
372 unsigned long flags = 0, flags_libsas = 0;
373
374 if (!dev->port) {
375 struct task_status_struct *tsm = &t->task_status;
376 tsm->resp = SAS_TASK_UNDELIVERED;
377 tsm->stat = SAS_PHY_DOWN;
378 if (dev->dev_type != SATA_DEV)
379 t->task_done(t);
380 return 0;
381 }
382 pm8001_ha = pm8001_find_ha_by_dev(task->dev);
383 PM8001_IO_DBG(pm8001_ha, pm8001_printk("pm8001_task_exec device \n "));
384 spin_lock_irqsave(&pm8001_ha->lock, flags);
385 do {
386 dev = t->dev;
387 pm8001_dev = dev->lldd_dev;
388 if (DEV_IS_GONE(pm8001_dev)) {
389 if (pm8001_dev) {
390 PM8001_IO_DBG(pm8001_ha,
391 pm8001_printk("device %d not ready.\n",
392 pm8001_dev->device_id));
393 } else {
394 PM8001_IO_DBG(pm8001_ha,
395 pm8001_printk("device %016llx not "
396 "ready.\n", SAS_ADDR(dev->sas_addr)));
397 }
398 rc = SAS_PHY_DOWN;
399 goto out_done;
400 }
401 port = &pm8001_ha->port[sas_find_local_port_id(dev)];
402 if (!port->port_attached) {
403 if (sas_protocol_ata(t->task_proto)) {
404 struct task_status_struct *ts = &t->task_status;
405 ts->resp = SAS_TASK_UNDELIVERED;
406 ts->stat = SAS_PHY_DOWN;
407
408 spin_unlock_irqrestore(&pm8001_ha->lock, flags);
409 spin_unlock_irqrestore(dev->sata_dev.ap->lock,
410 flags_libsas);
411 t->task_done(t);
412 spin_lock_irqsave(dev->sata_dev.ap->lock,
413 flags_libsas);
414 spin_lock_irqsave(&pm8001_ha->lock, flags);
415 if (n > 1)
416 t = list_entry(t->list.next,
417 struct sas_task, list);
418 continue;
419 } else {
420 struct task_status_struct *ts = &t->task_status;
421 ts->resp = SAS_TASK_UNDELIVERED;
422 ts->stat = SAS_PHY_DOWN;
423 t->task_done(t);
424 if (n > 1)
425 t = list_entry(t->list.next,
426 struct sas_task, list);
427 continue;
428 }
429 }
430 rc = pm8001_tag_alloc(pm8001_ha, &tag);
431 if (rc)
432 goto err_out;
433 ccb = &pm8001_ha->ccb_info[tag];
434
435 if (!sas_protocol_ata(t->task_proto)) {
436 if (t->num_scatter) {
437 n_elem = dma_map_sg(pm8001_ha->dev,
438 t->scatter,
439 t->num_scatter,
440 t->data_dir);
441 if (!n_elem) {
442 rc = -ENOMEM;
443 goto err_out_tag;
444 }
445 }
446 } else {
447 n_elem = t->num_scatter;
448 }
449
450 t->lldd_task = ccb;
451 ccb->n_elem = n_elem;
452 ccb->ccb_tag = tag;
453 ccb->task = t;
454 switch (t->task_proto) {
455 case SAS_PROTOCOL_SMP:
456 rc = pm8001_task_prep_smp(pm8001_ha, ccb);
457 break;
458 case SAS_PROTOCOL_SSP:
459 if (is_tmf)
460 rc = pm8001_task_prep_ssp_tm(pm8001_ha,
461 ccb, tmf);
462 else
463 rc = pm8001_task_prep_ssp(pm8001_ha, ccb);
464 break;
465 case SAS_PROTOCOL_SATA:
466 case SAS_PROTOCOL_STP:
467 case SAS_PROTOCOL_SATA | SAS_PROTOCOL_STP:
468 rc = pm8001_task_prep_ata(pm8001_ha, ccb);
469 break;
470 default:
471 dev_printk(KERN_ERR, pm8001_ha->dev,
472 "unknown sas_task proto: 0x%x\n",
473 t->task_proto);
474 rc = -EINVAL;
475 break;
476 }
477
478 if (rc) {
479 PM8001_IO_DBG(pm8001_ha,
480 pm8001_printk("rc is %x\n", rc));
481 goto err_out_tag;
482 }
483 /* TODO: select normal or high priority */
484 spin_lock(&t->task_state_lock);
485 t->task_state_flags |= SAS_TASK_AT_INITIATOR;
486 spin_unlock(&t->task_state_lock);
487 pm8001_dev->running_req++;
488 if (n > 1)
489 t = list_entry(t->list.next, struct sas_task, list);
490 } while (--n);
491 rc = 0;
492 goto out_done;
493
494err_out_tag:
495 pm8001_tag_free(pm8001_ha, tag);
496err_out:
497 dev_printk(KERN_ERR, pm8001_ha->dev, "pm8001 exec failed[%d]!\n", rc);
498 if (!sas_protocol_ata(t->task_proto))
499 if (n_elem)
500 dma_unmap_sg(pm8001_ha->dev, t->scatter, n_elem,
501 t->data_dir);
502out_done:
503 spin_unlock_irqrestore(&pm8001_ha->lock, flags);
504 return rc;
505}
506
507/**
508 * pm8001_queue_command - register for upper layer used, all IO commands sent
509 * to HBA are from this interface.
510 * @task: the task to be execute.
511 * @num: if can_queue great than 1, the task can be queued up. for SMP task,
512 * we always execute one one time
513 * @gfp_flags: gfp_flags
514 */
515int pm8001_queue_command(struct sas_task *task, const int num,
516 gfp_t gfp_flags)
517{
518 return pm8001_task_exec(task, num, gfp_flags, 0, NULL);
519}
520
521void pm8001_ccb_free(struct pm8001_hba_info *pm8001_ha, u32 ccb_idx)
522{
523 pm8001_tag_clear(pm8001_ha, ccb_idx);
524}
525
526/**
527 * pm8001_ccb_task_free - free the sg for ssp and smp command, free the ccb.
528 * @pm8001_ha: our hba card information
529 * @ccb: the ccb which attached to ssp task
530 * @task: the task to be free.
531 * @ccb_idx: ccb index.
532 */
533void pm8001_ccb_task_free(struct pm8001_hba_info *pm8001_ha,
534 struct sas_task *task, struct pm8001_ccb_info *ccb, u32 ccb_idx)
535{
536 if (!ccb->task)
537 return;
538 if (!sas_protocol_ata(task->task_proto))
539 if (ccb->n_elem)
540 dma_unmap_sg(pm8001_ha->dev, task->scatter,
541 task->num_scatter, task->data_dir);
542
543 switch (task->task_proto) {
544 case SAS_PROTOCOL_SMP:
545 dma_unmap_sg(pm8001_ha->dev, &task->smp_task.smp_resp, 1,
546 PCI_DMA_FROMDEVICE);
547 dma_unmap_sg(pm8001_ha->dev, &task->smp_task.smp_req, 1,
548 PCI_DMA_TODEVICE);
549 break;
550
551 case SAS_PROTOCOL_SATA:
552 case SAS_PROTOCOL_STP:
553 case SAS_PROTOCOL_SSP:
554 default:
555 /* do nothing */
556 break;
557 }
558 task->lldd_task = NULL;
559 ccb->task = NULL;
560 ccb->ccb_tag = 0xFFFFFFFF;
561 pm8001_ccb_free(pm8001_ha, ccb_idx);
562}
563
564 /**
565 * pm8001_alloc_dev - find a empty pm8001_device
566 * @pm8001_ha: our hba card information
567 */
568struct pm8001_device *pm8001_alloc_dev(struct pm8001_hba_info *pm8001_ha)
569{
570 u32 dev;
571 for (dev = 0; dev < PM8001_MAX_DEVICES; dev++) {
572 if (pm8001_ha->devices[dev].dev_type == NO_DEVICE) {
573 pm8001_ha->devices[dev].id = dev;
574 return &pm8001_ha->devices[dev];
575 }
576 }
577 if (dev == PM8001_MAX_DEVICES) {
578 PM8001_FAIL_DBG(pm8001_ha,
579 pm8001_printk("max support %d devices, ignore ..\n",
580 PM8001_MAX_DEVICES));
581 }
582 return NULL;
583}
584
585static void pm8001_free_dev(struct pm8001_device *pm8001_dev)
586{
587 u32 id = pm8001_dev->id;
588 memset(pm8001_dev, 0, sizeof(*pm8001_dev));
589 pm8001_dev->id = id;
590 pm8001_dev->dev_type = NO_DEVICE;
591 pm8001_dev->device_id = PM8001_MAX_DEVICES;
592 pm8001_dev->sas_device = NULL;
593}
594
595/**
596 * pm8001_dev_found_notify - libsas notify a device is found.
597 * @dev: the device structure which sas layer used.
598 *
599 * when libsas find a sas domain device, it should tell the LLDD that
600 * device is found, and then LLDD register this device to HBA firmware
601 * by the command "OPC_INB_REG_DEV", after that the HBA will assign a
602 * device ID(according to device's sas address) and returned it to LLDD. From
603 * now on, we communicate with HBA FW with the device ID which HBA assigned
604 * rather than sas address. it is the necessary step for our HBA but it is
605 * the optional for other HBA driver.
606 */
607static int pm8001_dev_found_notify(struct domain_device *dev)
608{
609 unsigned long flags = 0;
610 int res = 0;
611 struct pm8001_hba_info *pm8001_ha = NULL;
612 struct domain_device *parent_dev = dev->parent;
613 struct pm8001_device *pm8001_device;
614 DECLARE_COMPLETION_ONSTACK(completion);
615 u32 flag = 0;
616 pm8001_ha = pm8001_find_ha_by_dev(dev);
617 spin_lock_irqsave(&pm8001_ha->lock, flags);
618
619 pm8001_device = pm8001_alloc_dev(pm8001_ha);
620 if (!pm8001_device) {
621 res = -1;
622 goto found_out;
623 }
624 pm8001_device->sas_device = dev;
625 dev->lldd_dev = pm8001_device;
626 pm8001_device->dev_type = dev->dev_type;
627 pm8001_device->dcompletion = &completion;
628 if (parent_dev && DEV_IS_EXPANDER(parent_dev->dev_type)) {
629 int phy_id;
630 struct ex_phy *phy;
631 for (phy_id = 0; phy_id < parent_dev->ex_dev.num_phys;
632 phy_id++) {
633 phy = &parent_dev->ex_dev.ex_phy[phy_id];
634 if (SAS_ADDR(phy->attached_sas_addr)
635 == SAS_ADDR(dev->sas_addr)) {
636 pm8001_device->attached_phy = phy_id;
637 break;
638 }
639 }
640 if (phy_id == parent_dev->ex_dev.num_phys) {
641 PM8001_FAIL_DBG(pm8001_ha,
642 pm8001_printk("Error: no attached dev:%016llx"
643 " at ex:%016llx.\n", SAS_ADDR(dev->sas_addr),
644 SAS_ADDR(parent_dev->sas_addr)));
645 res = -1;
646 }
647 } else {
648 if (dev->dev_type == SATA_DEV) {
649 pm8001_device->attached_phy =
650 dev->rphy->identify.phy_identifier;
651 flag = 1; /* directly sata*/
652 }
653 } /*register this device to HBA*/
654 PM8001_DISC_DBG(pm8001_ha, pm8001_printk("Found device \n"));
655 PM8001_CHIP_DISP->reg_dev_req(pm8001_ha, pm8001_device, flag);
656 spin_unlock_irqrestore(&pm8001_ha->lock, flags);
657 wait_for_completion(&completion);
658 if (dev->dev_type == SAS_END_DEV)
659 msleep(50);
660 pm8001_ha->flags |= PM8001F_RUN_TIME ;
661 return 0;
662found_out:
663 spin_unlock_irqrestore(&pm8001_ha->lock, flags);
664 return res;
665}
666
667int pm8001_dev_found(struct domain_device *dev)
668{
669 return pm8001_dev_found_notify(dev);
670}
671
672/**
673 * pm8001_alloc_task - allocate a task structure for TMF
674 */
675static struct sas_task *pm8001_alloc_task(void)
676{
677 struct sas_task *task = kzalloc(sizeof(*task), GFP_KERNEL);
678 if (task) {
679 INIT_LIST_HEAD(&task->list);
680 spin_lock_init(&task->task_state_lock);
681 task->task_state_flags = SAS_TASK_STATE_PENDING;
682 init_timer(&task->timer);
683 init_completion(&task->completion);
684 }
685 return task;
686}
687
688static void pm8001_free_task(struct sas_task *task)
689{
690 if (task) {
691 BUG_ON(!list_empty(&task->list));
692 kfree(task);
693 }
694}
695
696static void pm8001_task_done(struct sas_task *task)
697{
698 if (!del_timer(&task->timer))
699 return;
700 complete(&task->completion);
701}
702
703static void pm8001_tmf_timedout(unsigned long data)
704{
705 struct sas_task *task = (struct sas_task *)data;
706
707 task->task_state_flags |= SAS_TASK_STATE_ABORTED;
708 complete(&task->completion);
709}
710
711#define PM8001_TASK_TIMEOUT 20
712/**
713 * pm8001_exec_internal_tmf_task - execute some task management commands.
714 * @dev: the wanted device.
715 * @tmf: which task management wanted to be take.
716 * @para_len: para_len.
717 * @parameter: ssp task parameter.
718 *
719 * when errors or exception happened, we may want to do something, for example
720 * abort the issued task which result in this execption, it is done by calling
721 * this function, note it is also with the task execute interface.
722 */
723static int pm8001_exec_internal_tmf_task(struct domain_device *dev,
724 void *parameter, u32 para_len, struct pm8001_tmf_task *tmf)
725{
726 int res, retry;
727 struct sas_task *task = NULL;
728 struct pm8001_hba_info *pm8001_ha = pm8001_find_ha_by_dev(dev);
729
730 for (retry = 0; retry < 3; retry++) {
731 task = pm8001_alloc_task();
732 if (!task)
733 return -ENOMEM;
734
735 task->dev = dev;
736 task->task_proto = dev->tproto;
737 memcpy(&task->ssp_task, parameter, para_len);
738 task->task_done = pm8001_task_done;
739 task->timer.data = (unsigned long)task;
740 task->timer.function = pm8001_tmf_timedout;
741 task->timer.expires = jiffies + PM8001_TASK_TIMEOUT*HZ;
742 add_timer(&task->timer);
743
744 res = pm8001_task_exec(task, 1, GFP_KERNEL, 1, tmf);
745
746 if (res) {
747 del_timer(&task->timer);
748 PM8001_FAIL_DBG(pm8001_ha,
749 pm8001_printk("Executing internal task "
750 "failed\n"));
751 goto ex_err;
752 }
753 wait_for_completion(&task->completion);
754 res = -TMF_RESP_FUNC_FAILED;
755 /* Even TMF timed out, return direct. */
756 if ((task->task_state_flags & SAS_TASK_STATE_ABORTED)) {
757 if (!(task->task_state_flags & SAS_TASK_STATE_DONE)) {
758 PM8001_FAIL_DBG(pm8001_ha,
759 pm8001_printk("TMF task[%x]timeout.\n",
760 tmf->tmf));
761 goto ex_err;
762 }
763 }
764
765 if (task->task_status.resp == SAS_TASK_COMPLETE &&
766 task->task_status.stat == SAM_GOOD) {
767 res = TMF_RESP_FUNC_COMPLETE;
768 break;
769 }
770
771 if (task->task_status.resp == SAS_TASK_COMPLETE &&
772 task->task_status.stat == SAS_DATA_UNDERRUN) {
773 /* no error, but return the number of bytes of
774 * underrun */
775 res = task->task_status.residual;
776 break;
777 }
778
779 if (task->task_status.resp == SAS_TASK_COMPLETE &&
780 task->task_status.stat == SAS_DATA_OVERRUN) {
781 PM8001_FAIL_DBG(pm8001_ha,
782 pm8001_printk("Blocked task error.\n"));
783 res = -EMSGSIZE;
784 break;
785 } else {
786 PM8001_EH_DBG(pm8001_ha,
787 pm8001_printk(" Task to dev %016llx response:"
788 "0x%x status 0x%x\n",
789 SAS_ADDR(dev->sas_addr),
790 task->task_status.resp,
791 task->task_status.stat));
792 pm8001_free_task(task);
793 task = NULL;
794 }
795 }
796ex_err:
797 BUG_ON(retry == 3 && task != NULL);
798 if (task != NULL)
799 pm8001_free_task(task);
800 return res;
801}
802
803static int
804pm8001_exec_internal_task_abort(struct pm8001_hba_info *pm8001_ha,
805 struct pm8001_device *pm8001_dev, struct domain_device *dev, u32 flag,
806 u32 task_tag)
807{
808 int res, retry;
809 u32 ccb_tag;
810 struct pm8001_ccb_info *ccb;
811 struct sas_task *task = NULL;
812
813 for (retry = 0; retry < 3; retry++) {
814 task = pm8001_alloc_task();
815 if (!task)
816 return -ENOMEM;
817
818 task->dev = dev;
819 task->task_proto = dev->tproto;
820 task->task_done = pm8001_task_done;
821 task->timer.data = (unsigned long)task;
822 task->timer.function = pm8001_tmf_timedout;
823 task->timer.expires = jiffies + PM8001_TASK_TIMEOUT * HZ;
824 add_timer(&task->timer);
825
826 res = pm8001_tag_alloc(pm8001_ha, &ccb_tag);
827 if (res)
828 return res;
829 ccb = &pm8001_ha->ccb_info[ccb_tag];
830 ccb->device = pm8001_dev;
831 ccb->ccb_tag = ccb_tag;
832 ccb->task = task;
833
834 res = PM8001_CHIP_DISP->task_abort(pm8001_ha,
835 pm8001_dev, flag, task_tag, ccb_tag);
836
837 if (res) {
838 del_timer(&task->timer);
839 PM8001_FAIL_DBG(pm8001_ha,
840 pm8001_printk("Executing internal task "
841 "failed\n"));
842 goto ex_err;
843 }
844 wait_for_completion(&task->completion);
845 res = TMF_RESP_FUNC_FAILED;
846 /* Even TMF timed out, return direct. */
847 if ((task->task_state_flags & SAS_TASK_STATE_ABORTED)) {
848 if (!(task->task_state_flags & SAS_TASK_STATE_DONE)) {
849 PM8001_FAIL_DBG(pm8001_ha,
850 pm8001_printk("TMF task timeout.\n"));
851 goto ex_err;
852 }
853 }
854
855 if (task->task_status.resp == SAS_TASK_COMPLETE &&
856 task->task_status.stat == SAM_GOOD) {
857 res = TMF_RESP_FUNC_COMPLETE;
858 break;
859
860 } else {
861 PM8001_EH_DBG(pm8001_ha,
862 pm8001_printk(" Task to dev %016llx response: "
863 "0x%x status 0x%x\n",
864 SAS_ADDR(dev->sas_addr),
865 task->task_status.resp,
866 task->task_status.stat));
867 pm8001_free_task(task);
868 task = NULL;
869 }
870 }
871ex_err:
872 BUG_ON(retry == 3 && task != NULL);
873 if (task != NULL)
874 pm8001_free_task(task);
875 return res;
876}
877
878/**
879 * pm8001_dev_gone_notify - see the comments for "pm8001_dev_found_notify"
880 * @dev: the device structure which sas layer used.
881 */
882static void pm8001_dev_gone_notify(struct domain_device *dev)
883{
884 unsigned long flags = 0;
885 u32 tag;
886 struct pm8001_hba_info *pm8001_ha;
887 struct pm8001_device *pm8001_dev = dev->lldd_dev;
888 u32 device_id = pm8001_dev->device_id;
889 pm8001_ha = pm8001_find_ha_by_dev(dev);
890 spin_lock_irqsave(&pm8001_ha->lock, flags);
891 pm8001_tag_alloc(pm8001_ha, &tag);
892 if (pm8001_dev) {
893 PM8001_DISC_DBG(pm8001_ha,
894 pm8001_printk("found dev[%d:%x] is gone.\n",
895 pm8001_dev->device_id, pm8001_dev->dev_type));
896 if (pm8001_dev->running_req) {
897 spin_unlock_irqrestore(&pm8001_ha->lock, flags);
898 pm8001_exec_internal_task_abort(pm8001_ha, pm8001_dev ,
899 dev, 1, 0);
900 spin_lock_irqsave(&pm8001_ha->lock, flags);
901 }
902 PM8001_CHIP_DISP->dereg_dev_req(pm8001_ha, device_id);
903 pm8001_free_dev(pm8001_dev);
904 } else {
905 PM8001_DISC_DBG(pm8001_ha,
906 pm8001_printk("Found dev has gone.\n"));
907 }
908 dev->lldd_dev = NULL;
909 spin_unlock_irqrestore(&pm8001_ha->lock, flags);
910}
911
912void pm8001_dev_gone(struct domain_device *dev)
913{
914 pm8001_dev_gone_notify(dev);
915}
916
917static int pm8001_issue_ssp_tmf(struct domain_device *dev,
918 u8 *lun, struct pm8001_tmf_task *tmf)
919{
920 struct sas_ssp_task ssp_task;
921 if (!(dev->tproto & SAS_PROTOCOL_SSP))
922 return TMF_RESP_FUNC_ESUPP;
923
924 strncpy((u8 *)&ssp_task.LUN, lun, 8);
925 return pm8001_exec_internal_tmf_task(dev, &ssp_task, sizeof(ssp_task),
926 tmf);
927}
928
929/**
930 * Standard mandates link reset for ATA (type 0) and hard reset for
931 * SSP (type 1) , only for RECOVERY
932 */
933int pm8001_I_T_nexus_reset(struct domain_device *dev)
934{
935 int rc = TMF_RESP_FUNC_FAILED;
936 struct pm8001_device *pm8001_dev;
937 struct pm8001_hba_info *pm8001_ha;
938 struct sas_phy *phy;
939 if (!dev || !dev->lldd_dev)
940 return -1;
941
942 pm8001_dev = dev->lldd_dev;
943 pm8001_ha = pm8001_find_ha_by_dev(dev);
944 phy = sas_find_local_phy(dev);
945
946 if (dev_is_sata(dev)) {
947 DECLARE_COMPLETION_ONSTACK(completion_setstate);
948 if (scsi_is_sas_phy_local(phy))
949 return 0;
950 rc = sas_phy_reset(phy, 1);
951 msleep(2000);
952 rc = pm8001_exec_internal_task_abort(pm8001_ha, pm8001_dev ,
953 dev, 1, 0);
954 pm8001_dev->setds_completion = &completion_setstate;
955 rc = PM8001_CHIP_DISP->set_dev_state_req(pm8001_ha,
956 pm8001_dev, 0x01);
957 wait_for_completion(&completion_setstate);
958 } else{
959 rc = sas_phy_reset(phy, 1);
960 msleep(2000);
961 }
962 PM8001_EH_DBG(pm8001_ha, pm8001_printk(" for device[%x]:rc=%d\n",
963 pm8001_dev->device_id, rc));
964 return rc;
965}
966
967/* mandatory SAM-3, the task reset the specified LUN*/
968int pm8001_lu_reset(struct domain_device *dev, u8 *lun)
969{
970 int rc = TMF_RESP_FUNC_FAILED;
971 struct pm8001_tmf_task tmf_task;
972 struct pm8001_device *pm8001_dev = dev->lldd_dev;
973 struct pm8001_hba_info *pm8001_ha = pm8001_find_ha_by_dev(dev);
974 if (dev_is_sata(dev)) {
975 struct sas_phy *phy = sas_find_local_phy(dev);
976 rc = pm8001_exec_internal_task_abort(pm8001_ha, pm8001_dev ,
977 dev, 1, 0);
978 rc = sas_phy_reset(phy, 1);
979 rc = PM8001_CHIP_DISP->set_dev_state_req(pm8001_ha,
980 pm8001_dev, 0x01);
981 msleep(2000);
982 } else {
983 tmf_task.tmf = TMF_LU_RESET;
984 rc = pm8001_issue_ssp_tmf(dev, lun, &tmf_task);
985 }
986 /* If failed, fall-through I_T_Nexus reset */
987 PM8001_EH_DBG(pm8001_ha, pm8001_printk("for device[%x]:rc=%d\n",
988 pm8001_dev->device_id, rc));
989 return rc;
990}
991
992/* optional SAM-3 */
993int pm8001_query_task(struct sas_task *task)
994{
995 u32 tag = 0xdeadbeef;
996 int i = 0;
997 struct scsi_lun lun;
998 struct pm8001_tmf_task tmf_task;
999 int rc = TMF_RESP_FUNC_FAILED;
1000 if (unlikely(!task || !task->lldd_task || !task->dev))
1001 return rc;
1002
1003 if (task->task_proto & SAS_PROTOCOL_SSP) {
1004 struct scsi_cmnd *cmnd = task->uldd_task;
1005 struct domain_device *dev = task->dev;
1006 struct pm8001_hba_info *pm8001_ha =
1007 pm8001_find_ha_by_dev(dev);
1008
1009 int_to_scsilun(cmnd->device->lun, &lun);
1010 rc = pm8001_find_tag(task, &tag);
1011 if (rc == 0) {
1012 rc = TMF_RESP_FUNC_FAILED;
1013 return rc;
1014 }
1015 PM8001_EH_DBG(pm8001_ha, pm8001_printk("Query:["));
1016 for (i = 0; i < 16; i++)
1017 printk(KERN_INFO "%02x ", cmnd->cmnd[i]);
1018 printk(KERN_INFO "]\n");
1019 tmf_task.tmf = TMF_QUERY_TASK;
1020 tmf_task.tag_of_task_to_be_managed = tag;
1021
1022 rc = pm8001_issue_ssp_tmf(dev, lun.scsi_lun, &tmf_task);
1023 switch (rc) {
1024 /* The task is still in Lun, release it then */
1025 case TMF_RESP_FUNC_SUCC:
1026 PM8001_EH_DBG(pm8001_ha,
1027 pm8001_printk("The task is still in Lun \n"));
1028 /* The task is not in Lun or failed, reset the phy */
1029 case TMF_RESP_FUNC_FAILED:
1030 case TMF_RESP_FUNC_COMPLETE:
1031 PM8001_EH_DBG(pm8001_ha,
1032 pm8001_printk("The task is not in Lun or failed,"
1033 " reset the phy \n"));
1034 break;
1035 }
1036 }
1037 pm8001_printk(":rc= %d\n", rc);
1038 return rc;
1039}
1040
1041/* mandatory SAM-3, still need free task/ccb info, abord the specified task */
1042int pm8001_abort_task(struct sas_task *task)
1043{
1044 unsigned long flags;
1045 u32 tag = 0xdeadbeef;
1046 u32 device_id;
1047 struct domain_device *dev ;
1048 struct pm8001_hba_info *pm8001_ha = NULL;
1049 struct pm8001_ccb_info *ccb;
1050 struct scsi_lun lun;
1051 struct pm8001_device *pm8001_dev;
1052 struct pm8001_tmf_task tmf_task;
1053 int rc = TMF_RESP_FUNC_FAILED;
1054 if (unlikely(!task || !task->lldd_task || !task->dev))
1055 return rc;
1056 spin_lock_irqsave(&task->task_state_lock, flags);
1057 if (task->task_state_flags & SAS_TASK_STATE_DONE) {
1058 spin_unlock_irqrestore(&task->task_state_lock, flags);
1059 rc = TMF_RESP_FUNC_COMPLETE;
1060 goto out;
1061 }
1062 spin_unlock_irqrestore(&task->task_state_lock, flags);
1063 if (task->task_proto & SAS_PROTOCOL_SSP) {
1064 struct scsi_cmnd *cmnd = task->uldd_task;
1065 dev = task->dev;
1066 ccb = task->lldd_task;
1067 pm8001_dev = dev->lldd_dev;
1068 pm8001_ha = pm8001_find_ha_by_dev(dev);
1069 int_to_scsilun(cmnd->device->lun, &lun);
1070 rc = pm8001_find_tag(task, &tag);
1071 if (rc == 0) {
1072 printk(KERN_INFO "No such tag in %s\n", __func__);
1073 rc = TMF_RESP_FUNC_FAILED;
1074 return rc;
1075 }
1076 device_id = pm8001_dev->device_id;
1077 PM8001_EH_DBG(pm8001_ha,
1078 pm8001_printk("abort io to deviceid= %d\n", device_id));
1079 tmf_task.tmf = TMF_ABORT_TASK;
1080 tmf_task.tag_of_task_to_be_managed = tag;
1081 rc = pm8001_issue_ssp_tmf(dev, lun.scsi_lun, &tmf_task);
1082 pm8001_exec_internal_task_abort(pm8001_ha, pm8001_dev,
1083 pm8001_dev->sas_device, 0, tag);
1084 } else if (task->task_proto & SAS_PROTOCOL_SATA ||
1085 task->task_proto & SAS_PROTOCOL_STP) {
1086 dev = task->dev;
1087 pm8001_dev = dev->lldd_dev;
1088 pm8001_ha = pm8001_find_ha_by_dev(dev);
1089 rc = pm8001_find_tag(task, &tag);
1090 if (rc == 0) {
1091 printk(KERN_INFO "No such tag in %s\n", __func__);
1092 rc = TMF_RESP_FUNC_FAILED;
1093 return rc;
1094 }
1095 rc = pm8001_exec_internal_task_abort(pm8001_ha, pm8001_dev,
1096 pm8001_dev->sas_device, 0, tag);
1097 } else if (task->task_proto & SAS_PROTOCOL_SMP) {
1098 /* SMP */
1099 dev = task->dev;
1100 pm8001_dev = dev->lldd_dev;
1101 pm8001_ha = pm8001_find_ha_by_dev(dev);
1102 rc = pm8001_find_tag(task, &tag);
1103 if (rc == 0) {
1104 printk(KERN_INFO "No such tag in %s\n", __func__);
1105 rc = TMF_RESP_FUNC_FAILED;
1106 return rc;
1107 }
1108 rc = pm8001_exec_internal_task_abort(pm8001_ha, pm8001_dev,
1109 pm8001_dev->sas_device, 0, tag);
1110
1111 }
1112out:
1113 if (rc != TMF_RESP_FUNC_COMPLETE)
1114 pm8001_printk("rc= %d\n", rc);
1115 return rc;
1116}
1117
1118int pm8001_abort_task_set(struct domain_device *dev, u8 *lun)
1119{
1120 int rc = TMF_RESP_FUNC_FAILED;
1121 struct pm8001_tmf_task tmf_task;
1122
1123 tmf_task.tmf = TMF_ABORT_TASK_SET;
1124 rc = pm8001_issue_ssp_tmf(dev, lun, &tmf_task);
1125 return rc;
1126}
1127
1128int pm8001_clear_aca(struct domain_device *dev, u8 *lun)
1129{
1130 int rc = TMF_RESP_FUNC_FAILED;
1131 struct pm8001_tmf_task tmf_task;
1132
1133 tmf_task.tmf = TMF_CLEAR_ACA;
1134 rc = pm8001_issue_ssp_tmf(dev, lun, &tmf_task);
1135
1136 return rc;
1137}
1138
1139int pm8001_clear_task_set(struct domain_device *dev, u8 *lun)
1140{
1141 int rc = TMF_RESP_FUNC_FAILED;
1142 struct pm8001_tmf_task tmf_task;
1143 struct pm8001_device *pm8001_dev = dev->lldd_dev;
1144 struct pm8001_hba_info *pm8001_ha = pm8001_find_ha_by_dev(dev);
1145
1146 PM8001_EH_DBG(pm8001_ha,
1147 pm8001_printk("I_T_L_Q clear task set[%x]\n",
1148 pm8001_dev->device_id));
1149 tmf_task.tmf = TMF_CLEAR_TASK_SET;
1150 rc = pm8001_issue_ssp_tmf(dev, lun, &tmf_task);
1151 return rc;
1152}
1153
diff --git a/drivers/scsi/pm8001/pm8001_sas.h b/drivers/scsi/pm8001/pm8001_sas.h
new file mode 100644
index 000000000000..8e38ca8cd101
--- /dev/null
+++ b/drivers/scsi/pm8001/pm8001_sas.h
@@ -0,0 +1,497 @@
1/*
2 * PMC-Sierra SPC 8001 SAS/SATA based host adapters driver
3 *
4 * Copyright (c) 2008-2009 USI Co., Ltd.
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions, and the following disclaimer,
12 * without modification.
13 * 2. Redistributions in binary form must reproduce at minimum a disclaimer
14 * substantially similar to the "NO WARRANTY" disclaimer below
15 * ("Disclaimer") and any redistribution must be conditioned upon
16 * including a substantially similar Disclaimer requirement for further
17 * binary redistribution.
18 * 3. Neither the names of the above-listed copyright holders nor the names
19 * of any contributors may be used to endorse or promote products derived
20 * from this software without specific prior written permission.
21 *
22 * Alternatively, this software may be distributed under the terms of the
23 * GNU General Public License ("GPL") version 2 as published by the Free
24 * Software Foundation.
25 *
26 * NO WARRANTY
27 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
28 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
29 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR
30 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
31 * HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
32 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
33 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
34 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
35 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
36 * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
37 * POSSIBILITY OF SUCH DAMAGES.
38 *
39 */
40
41#ifndef _PM8001_SAS_H_
42#define _PM8001_SAS_H_
43
44#include <linux/kernel.h>
45#include <linux/module.h>
46#include <linux/spinlock.h>
47#include <linux/delay.h>
48#include <linux/types.h>
49#include <linux/ctype.h>
50#include <linux/dma-mapping.h>
51#include <linux/pci.h>
52#include <linux/interrupt.h>
53#include <linux/smp_lock.h>
54#include <scsi/libsas.h>
55#include <scsi/scsi_tcq.h>
56#include <scsi/sas_ata.h>
57#include <asm/atomic.h>
58#include "pm8001_defs.h"
59
60#define DRV_NAME "pm8001"
61#define DRV_VERSION "0.1.36"
62#define PM8001_FAIL_LOGGING 0x01 /* Error message logging */
63#define PM8001_INIT_LOGGING 0x02 /* driver init logging */
64#define PM8001_DISC_LOGGING 0x04 /* discovery layer logging */
65#define PM8001_IO_LOGGING 0x08 /* I/O path logging */
66#define PM8001_EH_LOGGING 0x10 /* libsas EH function logging*/
67#define PM8001_IOCTL_LOGGING 0x20 /* IOCTL message logging */
68#define PM8001_MSG_LOGGING 0x40 /* misc message logging */
69#define pm8001_printk(format, arg...) printk(KERN_INFO "%s %d:" format,\
70 __func__, __LINE__, ## arg)
71#define PM8001_CHECK_LOGGING(HBA, LEVEL, CMD) \
72do { \
73 if (unlikely(HBA->logging_level & LEVEL)) \
74 do { \
75 CMD; \
76 } while (0); \
77} while (0);
78
79#define PM8001_EH_DBG(HBA, CMD) \
80 PM8001_CHECK_LOGGING(HBA, PM8001_EH_LOGGING, CMD)
81
82#define PM8001_INIT_DBG(HBA, CMD) \
83 PM8001_CHECK_LOGGING(HBA, PM8001_INIT_LOGGING, CMD)
84
85#define PM8001_DISC_DBG(HBA, CMD) \
86 PM8001_CHECK_LOGGING(HBA, PM8001_DISC_LOGGING, CMD)
87
88#define PM8001_IO_DBG(HBA, CMD) \
89 PM8001_CHECK_LOGGING(HBA, PM8001_IO_LOGGING, CMD)
90
91#define PM8001_FAIL_DBG(HBA, CMD) \
92 PM8001_CHECK_LOGGING(HBA, PM8001_FAIL_LOGGING, CMD)
93
94#define PM8001_IOCTL_DBG(HBA, CMD) \
95 PM8001_CHECK_LOGGING(HBA, PM8001_IOCTL_LOGGING, CMD)
96
97#define PM8001_MSG_DBG(HBA, CMD) \
98 PM8001_CHECK_LOGGING(HBA, PM8001_MSG_LOGGING, CMD)
99
100
101#define PM8001_USE_TASKLET
102#define PM8001_USE_MSIX
103#define PM8001_READ_VPD
104
105
106#define DEV_IS_EXPANDER(type) ((type == EDGE_DEV) || (type == FANOUT_DEV))
107
108#define PM8001_NAME_LENGTH 32/* generic length of strings */
109extern struct list_head hba_list;
110extern const struct pm8001_dispatch pm8001_8001_dispatch;
111
112struct pm8001_hba_info;
113struct pm8001_ccb_info;
114struct pm8001_device;
115/* define task management IU */
116struct pm8001_tmf_task {
117 u8 tmf;
118 u32 tag_of_task_to_be_managed;
119};
120struct pm8001_ioctl_payload {
121 u32 signature;
122 u16 major_function;
123 u16 minor_function;
124 u16 length;
125 u16 status;
126 u16 offset;
127 u16 id;
128 u8 *func_specific;
129};
130
131struct pm8001_dispatch {
132 char *name;
133 int (*chip_init)(struct pm8001_hba_info *pm8001_ha);
134 int (*chip_soft_rst)(struct pm8001_hba_info *pm8001_ha, u32 signature);
135 void (*chip_rst)(struct pm8001_hba_info *pm8001_ha);
136 int (*chip_ioremap)(struct pm8001_hba_info *pm8001_ha);
137 void (*chip_iounmap)(struct pm8001_hba_info *pm8001_ha);
138 irqreturn_t (*isr)(struct pm8001_hba_info *pm8001_ha);
139 u32 (*is_our_interupt)(struct pm8001_hba_info *pm8001_ha);
140 int (*isr_process_oq)(struct pm8001_hba_info *pm8001_ha);
141 void (*interrupt_enable)(struct pm8001_hba_info *pm8001_ha);
142 void (*interrupt_disable)(struct pm8001_hba_info *pm8001_ha);
143 void (*make_prd)(struct scatterlist *scatter, int nr, void *prd);
144 int (*smp_req)(struct pm8001_hba_info *pm8001_ha,
145 struct pm8001_ccb_info *ccb);
146 int (*ssp_io_req)(struct pm8001_hba_info *pm8001_ha,
147 struct pm8001_ccb_info *ccb);
148 int (*sata_req)(struct pm8001_hba_info *pm8001_ha,
149 struct pm8001_ccb_info *ccb);
150 int (*phy_start_req)(struct pm8001_hba_info *pm8001_ha, u8 phy_id);
151 int (*phy_stop_req)(struct pm8001_hba_info *pm8001_ha, u8 phy_id);
152 int (*reg_dev_req)(struct pm8001_hba_info *pm8001_ha,
153 struct pm8001_device *pm8001_dev, u32 flag);
154 int (*dereg_dev_req)(struct pm8001_hba_info *pm8001_ha, u32 device_id);
155 int (*phy_ctl_req)(struct pm8001_hba_info *pm8001_ha,
156 u32 phy_id, u32 phy_op);
157 int (*task_abort)(struct pm8001_hba_info *pm8001_ha,
158 struct pm8001_device *pm8001_dev, u8 flag, u32 task_tag,
159 u32 cmd_tag);
160 int (*ssp_tm_req)(struct pm8001_hba_info *pm8001_ha,
161 struct pm8001_ccb_info *ccb, struct pm8001_tmf_task *tmf);
162 int (*get_nvmd_req)(struct pm8001_hba_info *pm8001_ha, void *payload);
163 int (*set_nvmd_req)(struct pm8001_hba_info *pm8001_ha, void *payload);
164 int (*fw_flash_update_req)(struct pm8001_hba_info *pm8001_ha,
165 void *payload);
166 int (*set_dev_state_req)(struct pm8001_hba_info *pm8001_ha,
167 struct pm8001_device *pm8001_dev, u32 state);
168 int (*sas_diag_start_end_req)(struct pm8001_hba_info *pm8001_ha,
169 u32 state);
170 int (*sas_diag_execute_req)(struct pm8001_hba_info *pm8001_ha,
171 u32 state);
172 int (*sas_re_init_req)(struct pm8001_hba_info *pm8001_ha);
173};
174
175struct pm8001_chip_info {
176 u32 n_phy;
177 const struct pm8001_dispatch *dispatch;
178};
179#define PM8001_CHIP_DISP (pm8001_ha->chip->dispatch)
180
181struct pm8001_port {
182 struct asd_sas_port sas_port;
183 u8 port_attached;
184 u8 wide_port_phymap;
185 u8 port_state;
186 struct list_head list;
187};
188
189struct pm8001_phy {
190 struct pm8001_hba_info *pm8001_ha;
191 struct pm8001_port *port;
192 struct asd_sas_phy sas_phy;
193 struct sas_identify identify;
194 struct scsi_device *sdev;
195 u64 dev_sas_addr;
196 u32 phy_type;
197 struct completion *enable_completion;
198 u32 frame_rcvd_size;
199 u8 frame_rcvd[32];
200 u8 phy_attached;
201 u8 phy_state;
202 enum sas_linkrate minimum_linkrate;
203 enum sas_linkrate maximum_linkrate;
204};
205
206struct pm8001_device {
207 enum sas_dev_type dev_type;
208 struct domain_device *sas_device;
209 u32 attached_phy;
210 u32 id;
211 struct completion *dcompletion;
212 struct completion *setds_completion;
213 u32 device_id;
214 u32 running_req;
215};
216
217struct pm8001_prd_imt {
218 __le32 len;
219 __le32 e;
220};
221
222struct pm8001_prd {
223 __le64 addr; /* 64-bit buffer address */
224 struct pm8001_prd_imt im_len; /* 64-bit length */
225} __attribute__ ((packed));
226/*
227 * CCB(Command Control Block)
228 */
229struct pm8001_ccb_info {
230 struct list_head entry;
231 struct sas_task *task;
232 u32 n_elem;
233 u32 ccb_tag;
234 dma_addr_t ccb_dma_handle;
235 struct pm8001_device *device;
236 struct pm8001_prd buf_prd[PM8001_MAX_DMA_SG];
237 struct fw_control_ex *fw_control_context;
238};
239
240struct mpi_mem {
241 void *virt_ptr;
242 dma_addr_t phys_addr;
243 u32 phys_addr_hi;
244 u32 phys_addr_lo;
245 u32 total_len;
246 u32 num_elements;
247 u32 element_size;
248 u32 alignment;
249};
250
251struct mpi_mem_req {
252 /* The number of element in the mpiMemory array */
253 u32 count;
254 /* The array of structures that define memroy regions*/
255 struct mpi_mem region[USI_MAX_MEMCNT];
256};
257
258struct main_cfg_table {
259 u32 signature;
260 u32 interface_rev;
261 u32 firmware_rev;
262 u32 max_out_io;
263 u32 max_sgl;
264 u32 ctrl_cap_flag;
265 u32 gst_offset;
266 u32 inbound_queue_offset;
267 u32 outbound_queue_offset;
268 u32 inbound_q_nppd_hppd;
269 u32 outbound_hw_event_pid0_3;
270 u32 outbound_hw_event_pid4_7;
271 u32 outbound_ncq_event_pid0_3;
272 u32 outbound_ncq_event_pid4_7;
273 u32 outbound_tgt_ITNexus_event_pid0_3;
274 u32 outbound_tgt_ITNexus_event_pid4_7;
275 u32 outbound_tgt_ssp_event_pid0_3;
276 u32 outbound_tgt_ssp_event_pid4_7;
277 u32 outbound_tgt_smp_event_pid0_3;
278 u32 outbound_tgt_smp_event_pid4_7;
279 u32 upper_event_log_addr;
280 u32 lower_event_log_addr;
281 u32 event_log_size;
282 u32 event_log_option;
283 u32 upper_iop_event_log_addr;
284 u32 lower_iop_event_log_addr;
285 u32 iop_event_log_size;
286 u32 iop_event_log_option;
287 u32 fatal_err_interrupt;
288 u32 fatal_err_dump_offset0;
289 u32 fatal_err_dump_length0;
290 u32 fatal_err_dump_offset1;
291 u32 fatal_err_dump_length1;
292 u32 hda_mode_flag;
293 u32 anolog_setup_table_offset;
294};
295struct general_status_table {
296 u32 gst_len_mpistate;
297 u32 iq_freeze_state0;
298 u32 iq_freeze_state1;
299 u32 msgu_tcnt;
300 u32 iop_tcnt;
301 u32 reserved;
302 u32 phy_state[8];
303 u32 reserved1;
304 u32 reserved2;
305 u32 reserved3;
306 u32 recover_err_info[8];
307};
308struct inbound_queue_table {
309 u32 element_pri_size_cnt;
310 u32 upper_base_addr;
311 u32 lower_base_addr;
312 u32 ci_upper_base_addr;
313 u32 ci_lower_base_addr;
314 u32 pi_pci_bar;
315 u32 pi_offset;
316 u32 total_length;
317 void *base_virt;
318 void *ci_virt;
319 u32 reserved;
320 __le32 consumer_index;
321 u32 producer_idx;
322};
323struct outbound_queue_table {
324 u32 element_size_cnt;
325 u32 upper_base_addr;
326 u32 lower_base_addr;
327 void *base_virt;
328 u32 pi_upper_base_addr;
329 u32 pi_lower_base_addr;
330 u32 ci_pci_bar;
331 u32 ci_offset;
332 u32 total_length;
333 void *pi_virt;
334 u32 interrup_vec_cnt_delay;
335 u32 dinterrup_to_pci_offset;
336 __le32 producer_index;
337 u32 consumer_idx;
338};
339struct pm8001_hba_memspace {
340 void __iomem *memvirtaddr;
341 u64 membase;
342 u32 memsize;
343};
344struct pm8001_hba_info {
345 char name[PM8001_NAME_LENGTH];
346 struct list_head list;
347 unsigned long flags;
348 spinlock_t lock;/* host-wide lock */
349 struct pci_dev *pdev;/* our device */
350 struct device *dev;
351 struct pm8001_hba_memspace io_mem[6];
352 struct mpi_mem_req memoryMap;
353 void __iomem *msg_unit_tbl_addr;/*Message Unit Table Addr*/
354 void __iomem *main_cfg_tbl_addr;/*Main Config Table Addr*/
355 void __iomem *general_stat_tbl_addr;/*General Status Table Addr*/
356 void __iomem *inbnd_q_tbl_addr;/*Inbound Queue Config Table Addr*/
357 void __iomem *outbnd_q_tbl_addr;/*Outbound Queue Config Table Addr*/
358 struct main_cfg_table main_cfg_tbl;
359 struct general_status_table gs_tbl;
360 struct inbound_queue_table inbnd_q_tbl[PM8001_MAX_INB_NUM];
361 struct outbound_queue_table outbnd_q_tbl[PM8001_MAX_OUTB_NUM];
362 u8 sas_addr[SAS_ADDR_SIZE];
363 struct sas_ha_struct *sas;/* SCSI/SAS glue */
364 struct Scsi_Host *shost;
365 u32 chip_id;
366 const struct pm8001_chip_info *chip;
367 struct completion *nvmd_completion;
368 int tags_num;
369 unsigned long *tags;
370 struct pm8001_phy phy[PM8001_MAX_PHYS];
371 struct pm8001_port port[PM8001_MAX_PHYS];
372 u32 id;
373 u32 irq;
374 struct pm8001_device *devices;
375 struct pm8001_ccb_info *ccb_info;
376#ifdef PM8001_USE_MSIX
377 struct msix_entry msix_entries[16];/*for msi-x interrupt*/
378 int number_of_intr;/*will be used in remove()*/
379#endif
380#ifdef PM8001_USE_TASKLET
381 struct tasklet_struct tasklet;
382#endif
383 struct list_head wq_list;
384 u32 logging_level;
385 u32 fw_status;
386 const struct firmware *fw_image;
387};
388
389struct pm8001_wq {
390 struct delayed_work work_q;
391 struct pm8001_hba_info *pm8001_ha;
392 void *data;
393 int handler;
394 struct list_head entry;
395};
396
397struct pm8001_fw_image_header {
398 u8 vender_id[8];
399 u8 product_id;
400 u8 hardware_rev;
401 u8 dest_partition;
402 u8 reserved;
403 u8 fw_rev[4];
404 __be32 image_length;
405 __be32 image_crc;
406 __be32 startup_entry;
407} __attribute__((packed, aligned(4)));
408
409
410/**
411 * FW Flash Update status values
412 */
413#define FLASH_UPDATE_COMPLETE_PENDING_REBOOT 0x00
414#define FLASH_UPDATE_IN_PROGRESS 0x01
415#define FLASH_UPDATE_HDR_ERR 0x02
416#define FLASH_UPDATE_OFFSET_ERR 0x03
417#define FLASH_UPDATE_CRC_ERR 0x04
418#define FLASH_UPDATE_LENGTH_ERR 0x05
419#define FLASH_UPDATE_HW_ERR 0x06
420#define FLASH_UPDATE_DNLD_NOT_SUPPORTED 0x10
421#define FLASH_UPDATE_DISABLED 0x11
422
423/**
424 * brief param structure for firmware flash update.
425 */
426struct fw_flash_updata_info {
427 u32 cur_image_offset;
428 u32 cur_image_len;
429 u32 total_image_len;
430 struct pm8001_prd sgl;
431};
432
433struct fw_control_info {
434 u32 retcode;/*ret code (status)*/
435 u32 phase;/*ret code phase*/
436 u32 phaseCmplt;/*percent complete for the current
437 update phase */
438 u32 version;/*Hex encoded firmware version number*/
439 u32 offset;/*Used for downloading firmware */
440 u32 len; /*len of buffer*/
441 u32 size;/* Used in OS VPD and Trace get size
442 operations.*/
443 u32 reserved;/* padding required for 64 bit
444 alignment */
445 u8 buffer[1];/* Start of buffer */
446};
447struct fw_control_ex {
448 struct fw_control_info *fw_control;
449 void *buffer;/* keep buffer pointer to be
450 freed when the responce comes*/
451 void *virtAddr;/* keep virtual address of the data */
452 void *usrAddr;/* keep virtual address of the
453 user data */
454 dma_addr_t phys_addr;
455 u32 len; /* len of buffer */
456 void *payload; /* pointer to IOCTL Payload */
457 u8 inProgress;/*if 1 - the IOCTL request is in
458 progress */
459 void *param1;
460 void *param2;
461 void *param3;
462};
463
464/******************** function prototype *********************/
465int pm8001_tag_alloc(struct pm8001_hba_info *pm8001_ha, u32 *tag_out);
466void pm8001_tag_init(struct pm8001_hba_info *pm8001_ha);
467u32 pm8001_get_ncq_tag(struct sas_task *task, u32 *tag);
468void pm8001_ccb_free(struct pm8001_hba_info *pm8001_ha, u32 ccb_idx);
469void pm8001_ccb_task_free(struct pm8001_hba_info *pm8001_ha,
470 struct sas_task *task, struct pm8001_ccb_info *ccb, u32 ccb_idx);
471int pm8001_phy_control(struct asd_sas_phy *sas_phy, enum phy_func func,
472 void *funcdata);
473int pm8001_slave_alloc(struct scsi_device *scsi_dev);
474int pm8001_slave_configure(struct scsi_device *sdev);
475void pm8001_scan_start(struct Scsi_Host *shost);
476int pm8001_scan_finished(struct Scsi_Host *shost, unsigned long time);
477int pm8001_queue_command(struct sas_task *task, const int num,
478 gfp_t gfp_flags);
479int pm8001_abort_task(struct sas_task *task);
480int pm8001_abort_task_set(struct domain_device *dev, u8 *lun);
481int pm8001_clear_aca(struct domain_device *dev, u8 *lun);
482int pm8001_clear_task_set(struct domain_device *dev, u8 *lun);
483int pm8001_dev_found(struct domain_device *dev);
484void pm8001_dev_gone(struct domain_device *dev);
485int pm8001_lu_reset(struct domain_device *dev, u8 *lun);
486int pm8001_I_T_nexus_reset(struct domain_device *dev);
487int pm8001_query_task(struct sas_task *task);
488int pm8001_mem_alloc(struct pci_dev *pdev, void **virt_addr,
489 dma_addr_t *pphys_addr, u32 *pphys_addr_hi, u32 *pphys_addr_lo,
490 u32 mem_size, u32 align);
491
492
493/* ctl shared API */
494extern struct device_attribute *pm8001_host_attrs[];
495
496#endif
497