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authorDan Williams <dan.j.williams@intel.com>2011-06-30 20:38:32 -0400
committerDan Williams <dan.j.williams@intel.com>2011-07-03 07:04:52 -0400
commitd9dcb4ba791de2a06b19ac47cd61601cf3d4e208 (patch)
tree4b818b5b14c078703c034489c92e74975be6c06f /drivers/scsi/isci/host.c
parent78a6f06e0e82125787d7aa308fe28c2c8381540c (diff)
isci: unify isci_host and scic_sds_controller
Remove the distinction between these two implementations and unify on isci_host (local instances named ihost). Hmmm, we had two 'oem_parameters' instances, one was unused... nice. Reported-by: Christoph Hellwig <hch@lst.de> Signed-off-by: Dan Williams <dan.j.williams@intel.com>
Diffstat (limited to 'drivers/scsi/isci/host.c')
-rw-r--r--drivers/scsi/isci/host.c1000
1 files changed, 489 insertions, 511 deletions
diff --git a/drivers/scsi/isci/host.c b/drivers/scsi/isci/host.c
index 45d7f71c609a..bb298f8f609a 100644
--- a/drivers/scsi/isci/host.c
+++ b/drivers/scsi/isci/host.c
@@ -181,35 +181,35 @@ void sci_change_state(struct sci_base_state_machine *sm, u32 next_state)
181} 181}
182 182
183static bool scic_sds_controller_completion_queue_has_entries( 183static bool scic_sds_controller_completion_queue_has_entries(
184 struct scic_sds_controller *scic) 184 struct isci_host *ihost)
185{ 185{
186 u32 get_value = scic->completion_queue_get; 186 u32 get_value = ihost->completion_queue_get;
187 u32 get_index = get_value & SMU_COMPLETION_QUEUE_GET_POINTER_MASK; 187 u32 get_index = get_value & SMU_COMPLETION_QUEUE_GET_POINTER_MASK;
188 188
189 if (NORMALIZE_GET_POINTER_CYCLE_BIT(get_value) == 189 if (NORMALIZE_GET_POINTER_CYCLE_BIT(get_value) ==
190 COMPLETION_QUEUE_CYCLE_BIT(scic->completion_queue[get_index])) 190 COMPLETION_QUEUE_CYCLE_BIT(ihost->completion_queue[get_index]))
191 return true; 191 return true;
192 192
193 return false; 193 return false;
194} 194}
195 195
196static bool scic_sds_controller_isr(struct scic_sds_controller *scic) 196static bool scic_sds_controller_isr(struct isci_host *ihost)
197{ 197{
198 if (scic_sds_controller_completion_queue_has_entries(scic)) { 198 if (scic_sds_controller_completion_queue_has_entries(ihost)) {
199 return true; 199 return true;
200 } else { 200 } else {
201 /* 201 /*
202 * we have a spurious interrupt it could be that we have already 202 * we have a spurious interrupt it could be that we have already
203 * emptied the completion queue from a previous interrupt */ 203 * emptied the completion queue from a previous interrupt */
204 writel(SMU_ISR_COMPLETION, &scic->smu_registers->interrupt_status); 204 writel(SMU_ISR_COMPLETION, &ihost->smu_registers->interrupt_status);
205 205
206 /* 206 /*
207 * There is a race in the hardware that could cause us not to be notified 207 * There is a race in the hardware that could cause us not to be notified
208 * of an interrupt completion if we do not take this step. We will mask 208 * of an interrupt completion if we do not take this step. We will mask
209 * then unmask the interrupts so if there is another interrupt pending 209 * then unmask the interrupts so if there is another interrupt pending
210 * the clearing of the interrupt source we get the next interrupt message. */ 210 * the clearing of the interrupt source we get the next interrupt message. */
211 writel(0xFF000000, &scic->smu_registers->interrupt_mask); 211 writel(0xFF000000, &ihost->smu_registers->interrupt_mask);
212 writel(0, &scic->smu_registers->interrupt_mask); 212 writel(0, &ihost->smu_registers->interrupt_mask);
213 } 213 }
214 214
215 return false; 215 return false;
@@ -219,18 +219,18 @@ irqreturn_t isci_msix_isr(int vec, void *data)
219{ 219{
220 struct isci_host *ihost = data; 220 struct isci_host *ihost = data;
221 221
222 if (scic_sds_controller_isr(&ihost->sci)) 222 if (scic_sds_controller_isr(ihost))
223 tasklet_schedule(&ihost->completion_tasklet); 223 tasklet_schedule(&ihost->completion_tasklet);
224 224
225 return IRQ_HANDLED; 225 return IRQ_HANDLED;
226} 226}
227 227
228static bool scic_sds_controller_error_isr(struct scic_sds_controller *scic) 228static bool scic_sds_controller_error_isr(struct isci_host *ihost)
229{ 229{
230 u32 interrupt_status; 230 u32 interrupt_status;
231 231
232 interrupt_status = 232 interrupt_status =
233 readl(&scic->smu_registers->interrupt_status); 233 readl(&ihost->smu_registers->interrupt_status);
234 interrupt_status &= (SMU_ISR_QUEUE_ERROR | SMU_ISR_QUEUE_SUSPEND); 234 interrupt_status &= (SMU_ISR_QUEUE_ERROR | SMU_ISR_QUEUE_SUSPEND);
235 235
236 if (interrupt_status != 0) { 236 if (interrupt_status != 0) {
@@ -246,28 +246,27 @@ static bool scic_sds_controller_error_isr(struct scic_sds_controller *scic)
246 * then unmask the error interrupts so if there was another interrupt 246 * then unmask the error interrupts so if there was another interrupt
247 * pending we will be notified. 247 * pending we will be notified.
248 * Could we write the value of (SMU_ISR_QUEUE_ERROR | SMU_ISR_QUEUE_SUSPEND)? */ 248 * Could we write the value of (SMU_ISR_QUEUE_ERROR | SMU_ISR_QUEUE_SUSPEND)? */
249 writel(0xff, &scic->smu_registers->interrupt_mask); 249 writel(0xff, &ihost->smu_registers->interrupt_mask);
250 writel(0, &scic->smu_registers->interrupt_mask); 250 writel(0, &ihost->smu_registers->interrupt_mask);
251 251
252 return false; 252 return false;
253} 253}
254 254
255static void scic_sds_controller_task_completion(struct scic_sds_controller *scic, 255static void scic_sds_controller_task_completion(struct isci_host *ihost,
256 u32 completion_entry) 256 u32 completion_entry)
257{ 257{
258 u32 index = SCU_GET_COMPLETION_INDEX(completion_entry); 258 u32 index = SCU_GET_COMPLETION_INDEX(completion_entry);
259 struct isci_host *ihost = scic_to_ihost(scic);
260 struct isci_request *ireq = ihost->reqs[index]; 259 struct isci_request *ireq = ihost->reqs[index];
261 260
262 /* Make sure that we really want to process this IO request */ 261 /* Make sure that we really want to process this IO request */
263 if (test_bit(IREQ_ACTIVE, &ireq->flags) && 262 if (test_bit(IREQ_ACTIVE, &ireq->flags) &&
264 ireq->io_tag != SCI_CONTROLLER_INVALID_IO_TAG && 263 ireq->io_tag != SCI_CONTROLLER_INVALID_IO_TAG &&
265 ISCI_TAG_SEQ(ireq->io_tag) == scic->io_request_sequence[index]) 264 ISCI_TAG_SEQ(ireq->io_tag) == ihost->io_request_sequence[index])
266 /* Yep this is a valid io request pass it along to the io request handler */ 265 /* Yep this is a valid io request pass it along to the io request handler */
267 scic_sds_io_request_tc_completion(ireq, completion_entry); 266 scic_sds_io_request_tc_completion(ireq, completion_entry);
268} 267}
269 268
270static void scic_sds_controller_sdma_completion(struct scic_sds_controller *scic, 269static void scic_sds_controller_sdma_completion(struct isci_host *ihost,
271 u32 completion_entry) 270 u32 completion_entry)
272{ 271{
273 u32 index; 272 u32 index;
@@ -279,8 +278,8 @@ static void scic_sds_controller_sdma_completion(struct scic_sds_controller *scic
279 switch (scu_get_command_request_type(completion_entry)) { 278 switch (scu_get_command_request_type(completion_entry)) {
280 case SCU_CONTEXT_COMMAND_REQUEST_TYPE_POST_TC: 279 case SCU_CONTEXT_COMMAND_REQUEST_TYPE_POST_TC:
281 case SCU_CONTEXT_COMMAND_REQUEST_TYPE_DUMP_TC: 280 case SCU_CONTEXT_COMMAND_REQUEST_TYPE_DUMP_TC:
282 ireq = scic_to_ihost(scic)->reqs[index]; 281 ireq = ihost->reqs[index];
283 dev_warn(scic_to_dev(scic), "%s: %x for io request %p\n", 282 dev_warn(&ihost->pdev->dev, "%s: %x for io request %p\n",
284 __func__, completion_entry, ireq); 283 __func__, completion_entry, ireq);
285 /* @todo For a post TC operation we need to fail the IO 284 /* @todo For a post TC operation we need to fail the IO
286 * request 285 * request
@@ -289,27 +288,26 @@ static void scic_sds_controller_sdma_completion(struct scic_sds_controller *scic
289 case SCU_CONTEXT_COMMAND_REQUEST_TYPE_DUMP_RNC: 288 case SCU_CONTEXT_COMMAND_REQUEST_TYPE_DUMP_RNC:
290 case SCU_CONTEXT_COMMAND_REQUEST_TYPE_OTHER_RNC: 289 case SCU_CONTEXT_COMMAND_REQUEST_TYPE_OTHER_RNC:
291 case SCU_CONTEXT_COMMAND_REQUEST_TYPE_POST_RNC: 290 case SCU_CONTEXT_COMMAND_REQUEST_TYPE_POST_RNC:
292 idev = scic->device_table[index]; 291 idev = ihost->device_table[index];
293 dev_warn(scic_to_dev(scic), "%s: %x for device %p\n", 292 dev_warn(&ihost->pdev->dev, "%s: %x for device %p\n",
294 __func__, completion_entry, idev); 293 __func__, completion_entry, idev);
295 /* @todo For a port RNC operation we need to fail the 294 /* @todo For a port RNC operation we need to fail the
296 * device 295 * device
297 */ 296 */
298 break; 297 break;
299 default: 298 default:
300 dev_warn(scic_to_dev(scic), "%s: unknown completion type %x\n", 299 dev_warn(&ihost->pdev->dev, "%s: unknown completion type %x\n",
301 __func__, completion_entry); 300 __func__, completion_entry);
302 break; 301 break;
303 } 302 }
304} 303}
305 304
306static void scic_sds_controller_unsolicited_frame(struct scic_sds_controller *scic, 305static void scic_sds_controller_unsolicited_frame(struct isci_host *ihost,
307 u32 completion_entry) 306 u32 completion_entry)
308{ 307{
309 u32 index; 308 u32 index;
310 u32 frame_index; 309 u32 frame_index;
311 310
312 struct isci_host *ihost = scic_to_ihost(scic);
313 struct scu_unsolicited_frame_header *frame_header; 311 struct scu_unsolicited_frame_header *frame_header;
314 struct isci_phy *iphy; 312 struct isci_phy *iphy;
315 struct isci_remote_device *idev; 313 struct isci_remote_device *idev;
@@ -318,15 +316,15 @@ static void scic_sds_controller_unsolicited_frame(struct scic_sds_controller *sc
318 316
319 frame_index = SCU_GET_FRAME_INDEX(completion_entry); 317 frame_index = SCU_GET_FRAME_INDEX(completion_entry);
320 318
321 frame_header = scic->uf_control.buffers.array[frame_index].header; 319 frame_header = ihost->uf_control.buffers.array[frame_index].header;
322 scic->uf_control.buffers.array[frame_index].state = UNSOLICITED_FRAME_IN_USE; 320 ihost->uf_control.buffers.array[frame_index].state = UNSOLICITED_FRAME_IN_USE;
323 321
324 if (SCU_GET_FRAME_ERROR(completion_entry)) { 322 if (SCU_GET_FRAME_ERROR(completion_entry)) {
325 /* 323 /*
326 * / @todo If the IAF frame or SIGNATURE FIS frame has an error will 324 * / @todo If the IAF frame or SIGNATURE FIS frame has an error will
327 * / this cause a problem? We expect the phy initialization will 325 * / this cause a problem? We expect the phy initialization will
328 * / fail if there is an error in the frame. */ 326 * / fail if there is an error in the frame. */
329 scic_sds_controller_release_frame(scic, frame_index); 327 scic_sds_controller_release_frame(ihost, frame_index);
330 return; 328 return;
331 } 329 }
332 330
@@ -347,15 +345,15 @@ static void scic_sds_controller_unsolicited_frame(struct scic_sds_controller *sc
347 iphy = &ihost->phys[index]; 345 iphy = &ihost->phys[index];
348 result = scic_sds_phy_frame_handler(iphy, frame_index); 346 result = scic_sds_phy_frame_handler(iphy, frame_index);
349 } else { 347 } else {
350 if (index < scic->remote_node_entries) 348 if (index < ihost->remote_node_entries)
351 idev = scic->device_table[index]; 349 idev = ihost->device_table[index];
352 else 350 else
353 idev = NULL; 351 idev = NULL;
354 352
355 if (idev != NULL) 353 if (idev != NULL)
356 result = scic_sds_remote_device_frame_handler(idev, frame_index); 354 result = scic_sds_remote_device_frame_handler(idev, frame_index);
357 else 355 else
358 scic_sds_controller_release_frame(scic, frame_index); 356 scic_sds_controller_release_frame(ihost, frame_index);
359 } 357 }
360 } 358 }
361 359
@@ -366,10 +364,9 @@ static void scic_sds_controller_unsolicited_frame(struct scic_sds_controller *sc
366 } 364 }
367} 365}
368 366
369static void scic_sds_controller_event_completion(struct scic_sds_controller *scic, 367static void scic_sds_controller_event_completion(struct isci_host *ihost,
370 u32 completion_entry) 368 u32 completion_entry)
371{ 369{
372 struct isci_host *ihost = scic_to_ihost(scic);
373 struct isci_remote_device *idev; 370 struct isci_remote_device *idev;
374 struct isci_request *ireq; 371 struct isci_request *ireq;
375 struct isci_phy *iphy; 372 struct isci_phy *iphy;
@@ -380,11 +377,11 @@ static void scic_sds_controller_event_completion(struct scic_sds_controller *sci
380 switch (scu_get_event_type(completion_entry)) { 377 switch (scu_get_event_type(completion_entry)) {
381 case SCU_EVENT_TYPE_SMU_COMMAND_ERROR: 378 case SCU_EVENT_TYPE_SMU_COMMAND_ERROR:
382 /* / @todo The driver did something wrong and we need to fix the condtion. */ 379 /* / @todo The driver did something wrong and we need to fix the condtion. */
383 dev_err(scic_to_dev(scic), 380 dev_err(&ihost->pdev->dev,
384 "%s: SCIC Controller 0x%p received SMU command error " 381 "%s: SCIC Controller 0x%p received SMU command error "
385 "0x%x\n", 382 "0x%x\n",
386 __func__, 383 __func__,
387 scic, 384 ihost,
388 completion_entry); 385 completion_entry);
389 break; 386 break;
390 387
@@ -394,11 +391,11 @@ static void scic_sds_controller_event_completion(struct scic_sds_controller *sci
394 /* 391 /*
395 * / @todo This is a hardware failure and its likely that we want to 392 * / @todo This is a hardware failure and its likely that we want to
396 * / reset the controller. */ 393 * / reset the controller. */
397 dev_err(scic_to_dev(scic), 394 dev_err(&ihost->pdev->dev,
398 "%s: SCIC Controller 0x%p received fatal controller " 395 "%s: SCIC Controller 0x%p received fatal controller "
399 "event 0x%x\n", 396 "event 0x%x\n",
400 __func__, 397 __func__,
401 scic, 398 ihost,
402 completion_entry); 399 completion_entry);
403 break; 400 break;
404 401
@@ -415,27 +412,27 @@ static void scic_sds_controller_event_completion(struct scic_sds_controller *sci
415 if (ireq != NULL) 412 if (ireq != NULL)
416 scic_sds_io_request_event_handler(ireq, completion_entry); 413 scic_sds_io_request_event_handler(ireq, completion_entry);
417 else 414 else
418 dev_warn(scic_to_dev(scic), 415 dev_warn(&ihost->pdev->dev,
419 "%s: SCIC Controller 0x%p received " 416 "%s: SCIC Controller 0x%p received "
420 "event 0x%x for io request object " 417 "event 0x%x for io request object "
421 "that doesnt exist.\n", 418 "that doesnt exist.\n",
422 __func__, 419 __func__,
423 scic, 420 ihost,
424 completion_entry); 421 completion_entry);
425 422
426 break; 423 break;
427 424
428 case SCU_EVENT_SPECIFIC_IT_NEXUS_TIMEOUT: 425 case SCU_EVENT_SPECIFIC_IT_NEXUS_TIMEOUT:
429 idev = scic->device_table[index]; 426 idev = ihost->device_table[index];
430 if (idev != NULL) 427 if (idev != NULL)
431 scic_sds_remote_device_event_handler(idev, completion_entry); 428 scic_sds_remote_device_event_handler(idev, completion_entry);
432 else 429 else
433 dev_warn(scic_to_dev(scic), 430 dev_warn(&ihost->pdev->dev,
434 "%s: SCIC Controller 0x%p received " 431 "%s: SCIC Controller 0x%p received "
435 "event 0x%x for remote device object " 432 "event 0x%x for remote device object "
436 "that doesnt exist.\n", 433 "that doesnt exist.\n",
437 __func__, 434 __func__,
438 scic, 435 ihost,
439 completion_entry); 436 completion_entry);
440 437
441 break; 438 break;
@@ -459,25 +456,25 @@ static void scic_sds_controller_event_completion(struct scic_sds_controller *sci
459 case SCU_EVENT_TYPE_RNC_SUSPEND_TX: 456 case SCU_EVENT_TYPE_RNC_SUSPEND_TX:
460 case SCU_EVENT_TYPE_RNC_SUSPEND_TX_RX: 457 case SCU_EVENT_TYPE_RNC_SUSPEND_TX_RX:
461 case SCU_EVENT_TYPE_RNC_OPS_MISC: 458 case SCU_EVENT_TYPE_RNC_OPS_MISC:
462 if (index < scic->remote_node_entries) { 459 if (index < ihost->remote_node_entries) {
463 idev = scic->device_table[index]; 460 idev = ihost->device_table[index];
464 461
465 if (idev != NULL) 462 if (idev != NULL)
466 scic_sds_remote_device_event_handler(idev, completion_entry); 463 scic_sds_remote_device_event_handler(idev, completion_entry);
467 } else 464 } else
468 dev_err(scic_to_dev(scic), 465 dev_err(&ihost->pdev->dev,
469 "%s: SCIC Controller 0x%p received event 0x%x " 466 "%s: SCIC Controller 0x%p received event 0x%x "
470 "for remote device object 0x%0x that doesnt " 467 "for remote device object 0x%0x that doesnt "
471 "exist.\n", 468 "exist.\n",
472 __func__, 469 __func__,
473 scic, 470 ihost,
474 completion_entry, 471 completion_entry,
475 index); 472 index);
476 473
477 break; 474 break;
478 475
479 default: 476 default:
480 dev_warn(scic_to_dev(scic), 477 dev_warn(&ihost->pdev->dev,
481 "%s: SCIC Controller received unknown event code %x\n", 478 "%s: SCIC Controller received unknown event code %x\n",
482 __func__, 479 __func__,
483 completion_entry); 480 completion_entry);
@@ -485,7 +482,7 @@ static void scic_sds_controller_event_completion(struct scic_sds_controller *sci
485 } 482 }
486} 483}
487 484
488static void scic_sds_controller_process_completions(struct scic_sds_controller *scic) 485static void scic_sds_controller_process_completions(struct isci_host *ihost)
489{ 486{
490 u32 completion_count = 0; 487 u32 completion_count = 0;
491 u32 completion_entry; 488 u32 completion_entry;
@@ -494,47 +491,47 @@ static void scic_sds_controller_process_completions(struct scic_sds_controller *
494 u32 event_get; 491 u32 event_get;
495 u32 event_cycle; 492 u32 event_cycle;
496 493
497 dev_dbg(scic_to_dev(scic), 494 dev_dbg(&ihost->pdev->dev,
498 "%s: completion queue begining get:0x%08x\n", 495 "%s: completion queue begining get:0x%08x\n",
499 __func__, 496 __func__,
500 scic->completion_queue_get); 497 ihost->completion_queue_get);
501 498
502 /* Get the component parts of the completion queue */ 499 /* Get the component parts of the completion queue */
503 get_index = NORMALIZE_GET_POINTER(scic->completion_queue_get); 500 get_index = NORMALIZE_GET_POINTER(ihost->completion_queue_get);
504 get_cycle = SMU_CQGR_CYCLE_BIT & scic->completion_queue_get; 501 get_cycle = SMU_CQGR_CYCLE_BIT & ihost->completion_queue_get;
505 502
506 event_get = NORMALIZE_EVENT_POINTER(scic->completion_queue_get); 503 event_get = NORMALIZE_EVENT_POINTER(ihost->completion_queue_get);
507 event_cycle = SMU_CQGR_EVENT_CYCLE_BIT & scic->completion_queue_get; 504 event_cycle = SMU_CQGR_EVENT_CYCLE_BIT & ihost->completion_queue_get;
508 505
509 while ( 506 while (
510 NORMALIZE_GET_POINTER_CYCLE_BIT(get_cycle) 507 NORMALIZE_GET_POINTER_CYCLE_BIT(get_cycle)
511 == COMPLETION_QUEUE_CYCLE_BIT(scic->completion_queue[get_index]) 508 == COMPLETION_QUEUE_CYCLE_BIT(ihost->completion_queue[get_index])
512 ) { 509 ) {
513 completion_count++; 510 completion_count++;
514 511
515 completion_entry = scic->completion_queue[get_index]; 512 completion_entry = ihost->completion_queue[get_index];
516 513
517 /* increment the get pointer and check for rollover to toggle the cycle bit */ 514 /* increment the get pointer and check for rollover to toggle the cycle bit */
518 get_cycle ^= ((get_index+1) & SCU_MAX_COMPLETION_QUEUE_ENTRIES) << 515 get_cycle ^= ((get_index+1) & SCU_MAX_COMPLETION_QUEUE_ENTRIES) <<
519 (SMU_COMPLETION_QUEUE_GET_CYCLE_BIT_SHIFT - SCU_MAX_COMPLETION_QUEUE_SHIFT); 516 (SMU_COMPLETION_QUEUE_GET_CYCLE_BIT_SHIFT - SCU_MAX_COMPLETION_QUEUE_SHIFT);
520 get_index = (get_index+1) & (SCU_MAX_COMPLETION_QUEUE_ENTRIES-1); 517 get_index = (get_index+1) & (SCU_MAX_COMPLETION_QUEUE_ENTRIES-1);
521 518
522 dev_dbg(scic_to_dev(scic), 519 dev_dbg(&ihost->pdev->dev,
523 "%s: completion queue entry:0x%08x\n", 520 "%s: completion queue entry:0x%08x\n",
524 __func__, 521 __func__,
525 completion_entry); 522 completion_entry);
526 523
527 switch (SCU_GET_COMPLETION_TYPE(completion_entry)) { 524 switch (SCU_GET_COMPLETION_TYPE(completion_entry)) {
528 case SCU_COMPLETION_TYPE_TASK: 525 case SCU_COMPLETION_TYPE_TASK:
529 scic_sds_controller_task_completion(scic, completion_entry); 526 scic_sds_controller_task_completion(ihost, completion_entry);
530 break; 527 break;
531 528
532 case SCU_COMPLETION_TYPE_SDMA: 529 case SCU_COMPLETION_TYPE_SDMA:
533 scic_sds_controller_sdma_completion(scic, completion_entry); 530 scic_sds_controller_sdma_completion(ihost, completion_entry);
534 break; 531 break;
535 532
536 case SCU_COMPLETION_TYPE_UFI: 533 case SCU_COMPLETION_TYPE_UFI:
537 scic_sds_controller_unsolicited_frame(scic, completion_entry); 534 scic_sds_controller_unsolicited_frame(ihost, completion_entry);
538 break; 535 break;
539 536
540 case SCU_COMPLETION_TYPE_EVENT: 537 case SCU_COMPLETION_TYPE_EVENT:
@@ -543,11 +540,11 @@ static void scic_sds_controller_process_completions(struct scic_sds_controller *
543 (SMU_COMPLETION_QUEUE_GET_EVENT_CYCLE_BIT_SHIFT - SCU_MAX_EVENTS_SHIFT); 540 (SMU_COMPLETION_QUEUE_GET_EVENT_CYCLE_BIT_SHIFT - SCU_MAX_EVENTS_SHIFT);
544 event_get = (event_get+1) & (SCU_MAX_EVENTS-1); 541 event_get = (event_get+1) & (SCU_MAX_EVENTS-1);
545 542
546 scic_sds_controller_event_completion(scic, completion_entry); 543 scic_sds_controller_event_completion(ihost, completion_entry);
547 break; 544 break;
548 } 545 }
549 default: 546 default:
550 dev_warn(scic_to_dev(scic), 547 dev_warn(&ihost->pdev->dev,
551 "%s: SCIC Controller received unknown " 548 "%s: SCIC Controller received unknown "
552 "completion type %x\n", 549 "completion type %x\n",
553 __func__, 550 __func__,
@@ -558,7 +555,7 @@ static void scic_sds_controller_process_completions(struct scic_sds_controller *
558 555
559 /* Update the get register if we completed one or more entries */ 556 /* Update the get register if we completed one or more entries */
560 if (completion_count > 0) { 557 if (completion_count > 0) {
561 scic->completion_queue_get = 558 ihost->completion_queue_get =
562 SMU_CQGR_GEN_BIT(ENABLE) | 559 SMU_CQGR_GEN_BIT(ENABLE) |
563 SMU_CQGR_GEN_BIT(EVENT_ENABLE) | 560 SMU_CQGR_GEN_BIT(EVENT_ENABLE) |
564 event_cycle | 561 event_cycle |
@@ -566,35 +563,35 @@ static void scic_sds_controller_process_completions(struct scic_sds_controller *
566 get_cycle | 563 get_cycle |
567 SMU_CQGR_GEN_VAL(POINTER, get_index); 564 SMU_CQGR_GEN_VAL(POINTER, get_index);
568 565
569 writel(scic->completion_queue_get, 566 writel(ihost->completion_queue_get,
570 &scic->smu_registers->completion_queue_get); 567 &ihost->smu_registers->completion_queue_get);
571 568
572 } 569 }
573 570
574 dev_dbg(scic_to_dev(scic), 571 dev_dbg(&ihost->pdev->dev,
575 "%s: completion queue ending get:0x%08x\n", 572 "%s: completion queue ending get:0x%08x\n",
576 __func__, 573 __func__,
577 scic->completion_queue_get); 574 ihost->completion_queue_get);
578 575
579} 576}
580 577
581static void scic_sds_controller_error_handler(struct scic_sds_controller *scic) 578static void scic_sds_controller_error_handler(struct isci_host *ihost)
582{ 579{
583 u32 interrupt_status; 580 u32 interrupt_status;
584 581
585 interrupt_status = 582 interrupt_status =
586 readl(&scic->smu_registers->interrupt_status); 583 readl(&ihost->smu_registers->interrupt_status);
587 584
588 if ((interrupt_status & SMU_ISR_QUEUE_SUSPEND) && 585 if ((interrupt_status & SMU_ISR_QUEUE_SUSPEND) &&
589 scic_sds_controller_completion_queue_has_entries(scic)) { 586 scic_sds_controller_completion_queue_has_entries(ihost)) {
590 587
591 scic_sds_controller_process_completions(scic); 588 scic_sds_controller_process_completions(ihost);
592 writel(SMU_ISR_QUEUE_SUSPEND, &scic->smu_registers->interrupt_status); 589 writel(SMU_ISR_QUEUE_SUSPEND, &ihost->smu_registers->interrupt_status);
593 } else { 590 } else {
594 dev_err(scic_to_dev(scic), "%s: status: %#x\n", __func__, 591 dev_err(&ihost->pdev->dev, "%s: status: %#x\n", __func__,
595 interrupt_status); 592 interrupt_status);
596 593
597 sci_change_state(&scic->sm, SCIC_FAILED); 594 sci_change_state(&ihost->sm, SCIC_FAILED);
598 595
599 return; 596 return;
600 } 597 }
@@ -602,22 +599,21 @@ static void scic_sds_controller_error_handler(struct scic_sds_controller *scic)
602 /* If we dont process any completions I am not sure that we want to do this. 599 /* If we dont process any completions I am not sure that we want to do this.
603 * We are in the middle of a hardware fault and should probably be reset. 600 * We are in the middle of a hardware fault and should probably be reset.
604 */ 601 */
605 writel(0, &scic->smu_registers->interrupt_mask); 602 writel(0, &ihost->smu_registers->interrupt_mask);
606} 603}
607 604
608irqreturn_t isci_intx_isr(int vec, void *data) 605irqreturn_t isci_intx_isr(int vec, void *data)
609{ 606{
610 irqreturn_t ret = IRQ_NONE; 607 irqreturn_t ret = IRQ_NONE;
611 struct isci_host *ihost = data; 608 struct isci_host *ihost = data;
612 struct scic_sds_controller *scic = &ihost->sci;
613 609
614 if (scic_sds_controller_isr(scic)) { 610 if (scic_sds_controller_isr(ihost)) {
615 writel(SMU_ISR_COMPLETION, &scic->smu_registers->interrupt_status); 611 writel(SMU_ISR_COMPLETION, &ihost->smu_registers->interrupt_status);
616 tasklet_schedule(&ihost->completion_tasklet); 612 tasklet_schedule(&ihost->completion_tasklet);
617 ret = IRQ_HANDLED; 613 ret = IRQ_HANDLED;
618 } else if (scic_sds_controller_error_isr(scic)) { 614 } else if (scic_sds_controller_error_isr(ihost)) {
619 spin_lock(&ihost->scic_lock); 615 spin_lock(&ihost->scic_lock);
620 scic_sds_controller_error_handler(scic); 616 scic_sds_controller_error_handler(ihost);
621 spin_unlock(&ihost->scic_lock); 617 spin_unlock(&ihost->scic_lock);
622 ret = IRQ_HANDLED; 618 ret = IRQ_HANDLED;
623 } 619 }
@@ -629,8 +625,8 @@ irqreturn_t isci_error_isr(int vec, void *data)
629{ 625{
630 struct isci_host *ihost = data; 626 struct isci_host *ihost = data;
631 627
632 if (scic_sds_controller_error_isr(&ihost->sci)) 628 if (scic_sds_controller_error_isr(ihost))
633 scic_sds_controller_error_handler(&ihost->sci); 629 scic_sds_controller_error_handler(ihost);
634 630
635 return IRQ_HANDLED; 631 return IRQ_HANDLED;
636} 632}
@@ -685,11 +681,10 @@ int isci_host_scan_finished(struct Scsi_Host *shost, unsigned long time)
685 * This method returns the number of milliseconds for the suggested start 681 * This method returns the number of milliseconds for the suggested start
686 * operation timeout. 682 * operation timeout.
687 */ 683 */
688static u32 scic_controller_get_suggested_start_timeout( 684static u32 scic_controller_get_suggested_start_timeout(struct isci_host *ihost)
689 struct scic_sds_controller *sc)
690{ 685{
691 /* Validate the user supplied parameters. */ 686 /* Validate the user supplied parameters. */
692 if (sc == NULL) 687 if (!ihost)
693 return 0; 688 return 0;
694 689
695 /* 690 /*
@@ -711,35 +706,32 @@ static u32 scic_controller_get_suggested_start_timeout(
711 + ((SCI_MAX_PHYS - 1) * SCIC_SDS_CONTROLLER_POWER_CONTROL_INTERVAL); 706 + ((SCI_MAX_PHYS - 1) * SCIC_SDS_CONTROLLER_POWER_CONTROL_INTERVAL);
712} 707}
713 708
714static void scic_controller_enable_interrupts( 709static void scic_controller_enable_interrupts(struct isci_host *ihost)
715 struct scic_sds_controller *scic)
716{ 710{
717 BUG_ON(scic->smu_registers == NULL); 711 BUG_ON(ihost->smu_registers == NULL);
718 writel(0, &scic->smu_registers->interrupt_mask); 712 writel(0, &ihost->smu_registers->interrupt_mask);
719} 713}
720 714
721void scic_controller_disable_interrupts( 715void scic_controller_disable_interrupts(struct isci_host *ihost)
722 struct scic_sds_controller *scic)
723{ 716{
724 BUG_ON(scic->smu_registers == NULL); 717 BUG_ON(ihost->smu_registers == NULL);
725 writel(0xffffffff, &scic->smu_registers->interrupt_mask); 718 writel(0xffffffff, &ihost->smu_registers->interrupt_mask);
726} 719}
727 720
728static void scic_sds_controller_enable_port_task_scheduler( 721static void scic_sds_controller_enable_port_task_scheduler(struct isci_host *ihost)
729 struct scic_sds_controller *scic)
730{ 722{
731 u32 port_task_scheduler_value; 723 u32 port_task_scheduler_value;
732 724
733 port_task_scheduler_value = 725 port_task_scheduler_value =
734 readl(&scic->scu_registers->peg0.ptsg.control); 726 readl(&ihost->scu_registers->peg0.ptsg.control);
735 port_task_scheduler_value |= 727 port_task_scheduler_value |=
736 (SCU_PTSGCR_GEN_BIT(ETM_ENABLE) | 728 (SCU_PTSGCR_GEN_BIT(ETM_ENABLE) |
737 SCU_PTSGCR_GEN_BIT(PTSG_ENABLE)); 729 SCU_PTSGCR_GEN_BIT(PTSG_ENABLE));
738 writel(port_task_scheduler_value, 730 writel(port_task_scheduler_value,
739 &scic->scu_registers->peg0.ptsg.control); 731 &ihost->scu_registers->peg0.ptsg.control);
740} 732}
741 733
742static void scic_sds_controller_assign_task_entries(struct scic_sds_controller *scic) 734static void scic_sds_controller_assign_task_entries(struct isci_host *ihost)
743{ 735{
744 u32 task_assignment; 736 u32 task_assignment;
745 737
@@ -749,32 +741,32 @@ static void scic_sds_controller_assign_task_entries(struct scic_sds_controller *
749 */ 741 */
750 742
751 task_assignment = 743 task_assignment =
752 readl(&scic->smu_registers->task_context_assignment[0]); 744 readl(&ihost->smu_registers->task_context_assignment[0]);
753 745
754 task_assignment |= (SMU_TCA_GEN_VAL(STARTING, 0)) | 746 task_assignment |= (SMU_TCA_GEN_VAL(STARTING, 0)) |
755 (SMU_TCA_GEN_VAL(ENDING, scic->task_context_entries - 1)) | 747 (SMU_TCA_GEN_VAL(ENDING, ihost->task_context_entries - 1)) |
756 (SMU_TCA_GEN_BIT(RANGE_CHECK_ENABLE)); 748 (SMU_TCA_GEN_BIT(RANGE_CHECK_ENABLE));
757 749
758 writel(task_assignment, 750 writel(task_assignment,
759 &scic->smu_registers->task_context_assignment[0]); 751 &ihost->smu_registers->task_context_assignment[0]);
760 752
761} 753}
762 754
763static void scic_sds_controller_initialize_completion_queue(struct scic_sds_controller *scic) 755static void scic_sds_controller_initialize_completion_queue(struct isci_host *ihost)
764{ 756{
765 u32 index; 757 u32 index;
766 u32 completion_queue_control_value; 758 u32 completion_queue_control_value;
767 u32 completion_queue_get_value; 759 u32 completion_queue_get_value;
768 u32 completion_queue_put_value; 760 u32 completion_queue_put_value;
769 761
770 scic->completion_queue_get = 0; 762 ihost->completion_queue_get = 0;
771 763
772 completion_queue_control_value = 764 completion_queue_control_value =
773 (SMU_CQC_QUEUE_LIMIT_SET(SCU_MAX_COMPLETION_QUEUE_ENTRIES - 1) | 765 (SMU_CQC_QUEUE_LIMIT_SET(SCU_MAX_COMPLETION_QUEUE_ENTRIES - 1) |
774 SMU_CQC_EVENT_LIMIT_SET(SCU_MAX_EVENTS - 1)); 766 SMU_CQC_EVENT_LIMIT_SET(SCU_MAX_EVENTS - 1));
775 767
776 writel(completion_queue_control_value, 768 writel(completion_queue_control_value,
777 &scic->smu_registers->completion_queue_control); 769 &ihost->smu_registers->completion_queue_control);
778 770
779 771
780 /* Set the completion queue get pointer and enable the queue */ 772 /* Set the completion queue get pointer and enable the queue */
@@ -786,7 +778,7 @@ static void scic_sds_controller_initialize_completion_queue(struct scic_sds_cont
786 ); 778 );
787 779
788 writel(completion_queue_get_value, 780 writel(completion_queue_get_value,
789 &scic->smu_registers->completion_queue_get); 781 &ihost->smu_registers->completion_queue_get);
790 782
791 /* Set the completion queue put pointer */ 783 /* Set the completion queue put pointer */
792 completion_queue_put_value = ( 784 completion_queue_put_value = (
@@ -795,7 +787,7 @@ static void scic_sds_controller_initialize_completion_queue(struct scic_sds_cont
795 ); 787 );
796 788
797 writel(completion_queue_put_value, 789 writel(completion_queue_put_value,
798 &scic->smu_registers->completion_queue_put); 790 &ihost->smu_registers->completion_queue_put);
799 791
800 /* Initialize the cycle bit of the completion queue entries */ 792 /* Initialize the cycle bit of the completion queue entries */
801 for (index = 0; index < SCU_MAX_COMPLETION_QUEUE_ENTRIES; index++) { 793 for (index = 0; index < SCU_MAX_COMPLETION_QUEUE_ENTRIES; index++) {
@@ -803,11 +795,11 @@ static void scic_sds_controller_initialize_completion_queue(struct scic_sds_cont
803 * If get.cycle_bit != completion_queue.cycle_bit 795 * If get.cycle_bit != completion_queue.cycle_bit
804 * its not a valid completion queue entry 796 * its not a valid completion queue entry
805 * so at system start all entries are invalid */ 797 * so at system start all entries are invalid */
806 scic->completion_queue[index] = 0x80000000; 798 ihost->completion_queue[index] = 0x80000000;
807 } 799 }
808} 800}
809 801
810static void scic_sds_controller_initialize_unsolicited_frame_queue(struct scic_sds_controller *scic) 802static void scic_sds_controller_initialize_unsolicited_frame_queue(struct isci_host *ihost)
811{ 803{
812 u32 frame_queue_control_value; 804 u32 frame_queue_control_value;
813 u32 frame_queue_get_value; 805 u32 frame_queue_get_value;
@@ -818,7 +810,7 @@ static void scic_sds_controller_initialize_unsolicited_frame_queue(struct scic_s
818 SCU_UFQC_GEN_VAL(QUEUE_SIZE, SCU_MAX_UNSOLICITED_FRAMES); 810 SCU_UFQC_GEN_VAL(QUEUE_SIZE, SCU_MAX_UNSOLICITED_FRAMES);
819 811
820 writel(frame_queue_control_value, 812 writel(frame_queue_control_value,
821 &scic->scu_registers->sdma.unsolicited_frame_queue_control); 813 &ihost->scu_registers->sdma.unsolicited_frame_queue_control);
822 814
823 /* Setup the get pointer for the unsolicited frame queue */ 815 /* Setup the get pointer for the unsolicited frame queue */
824 frame_queue_get_value = ( 816 frame_queue_get_value = (
@@ -827,11 +819,11 @@ static void scic_sds_controller_initialize_unsolicited_frame_queue(struct scic_s
827 ); 819 );
828 820
829 writel(frame_queue_get_value, 821 writel(frame_queue_get_value,
830 &scic->scu_registers->sdma.unsolicited_frame_get_pointer); 822 &ihost->scu_registers->sdma.unsolicited_frame_get_pointer);
831 /* Setup the put pointer for the unsolicited frame queue */ 823 /* Setup the put pointer for the unsolicited frame queue */
832 frame_queue_put_value = SCU_UFQPP_GEN_VAL(POINTER, 0); 824 frame_queue_put_value = SCU_UFQPP_GEN_VAL(POINTER, 0);
833 writel(frame_queue_put_value, 825 writel(frame_queue_put_value,
834 &scic->scu_registers->sdma.unsolicited_frame_put_pointer); 826 &ihost->scu_registers->sdma.unsolicited_frame_put_pointer);
835} 827}
836 828
837/** 829/**
@@ -846,17 +838,16 @@ static void scic_sds_controller_initialize_unsolicited_frame_queue(struct scic_s
846 * none. 838 * none.
847 */ 839 */
848static void scic_sds_controller_transition_to_ready( 840static void scic_sds_controller_transition_to_ready(
849 struct scic_sds_controller *scic, 841 struct isci_host *ihost,
850 enum sci_status status) 842 enum sci_status status)
851{ 843{
852 struct isci_host *ihost = scic_to_ihost(scic);
853 844
854 if (scic->sm.current_state_id == SCIC_STARTING) { 845 if (ihost->sm.current_state_id == SCIC_STARTING) {
855 /* 846 /*
856 * We move into the ready state, because some of the phys/ports 847 * We move into the ready state, because some of the phys/ports
857 * may be up and operational. 848 * may be up and operational.
858 */ 849 */
859 sci_change_state(&scic->sm, SCIC_READY); 850 sci_change_state(&ihost->sm, SCIC_READY);
860 851
861 isci_host_start_complete(ihost, status); 852 isci_host_start_complete(ihost, status);
862 } 853 }
@@ -892,19 +883,18 @@ static bool is_phy_starting(struct isci_phy *iphy)
892 * controller to the READY state and inform the user 883 * controller to the READY state and inform the user
893 * (scic_cb_controller_start_complete()). 884 * (scic_cb_controller_start_complete()).
894 */ 885 */
895static enum sci_status scic_sds_controller_start_next_phy(struct scic_sds_controller *scic) 886static enum sci_status scic_sds_controller_start_next_phy(struct isci_host *ihost)
896{ 887{
897 struct isci_host *ihost = scic_to_ihost(scic); 888 struct scic_sds_oem_params *oem = &ihost->oem_parameters.sds1;
898 struct scic_sds_oem_params *oem = &scic->oem_parameters.sds1;
899 struct isci_phy *iphy; 889 struct isci_phy *iphy;
900 enum sci_status status; 890 enum sci_status status;
901 891
902 status = SCI_SUCCESS; 892 status = SCI_SUCCESS;
903 893
904 if (scic->phy_startup_timer_pending) 894 if (ihost->phy_startup_timer_pending)
905 return status; 895 return status;
906 896
907 if (scic->next_phy_to_start >= SCI_MAX_PHYS) { 897 if (ihost->next_phy_to_start >= SCI_MAX_PHYS) {
908 bool is_controller_start_complete = true; 898 bool is_controller_start_complete = true;
909 u32 state; 899 u32 state;
910 u8 index; 900 u8 index;
@@ -934,16 +924,16 @@ static enum sci_status scic_sds_controller_start_next_phy(struct scic_sds_contro
934 * The controller has successfully finished the start process. 924 * The controller has successfully finished the start process.
935 * Inform the SCI Core user and transition to the READY state. */ 925 * Inform the SCI Core user and transition to the READY state. */
936 if (is_controller_start_complete == true) { 926 if (is_controller_start_complete == true) {
937 scic_sds_controller_transition_to_ready(scic, SCI_SUCCESS); 927 scic_sds_controller_transition_to_ready(ihost, SCI_SUCCESS);
938 sci_del_timer(&scic->phy_timer); 928 sci_del_timer(&ihost->phy_timer);
939 scic->phy_startup_timer_pending = false; 929 ihost->phy_startup_timer_pending = false;
940 } 930 }
941 } else { 931 } else {
942 iphy = &ihost->phys[scic->next_phy_to_start]; 932 iphy = &ihost->phys[ihost->next_phy_to_start];
943 933
944 if (oem->controller.mode_type == SCIC_PORT_MANUAL_CONFIGURATION_MODE) { 934 if (oem->controller.mode_type == SCIC_PORT_MANUAL_CONFIGURATION_MODE) {
945 if (phy_get_non_dummy_port(iphy) == NULL) { 935 if (phy_get_non_dummy_port(iphy) == NULL) {
946 scic->next_phy_to_start++; 936 ihost->next_phy_to_start++;
947 937
948 /* Caution recursion ahead be forwarned 938 /* Caution recursion ahead be forwarned
949 * 939 *
@@ -954,27 +944,27 @@ static enum sci_status scic_sds_controller_start_next_phy(struct scic_sds_contro
954 * incorrectly for the PORT or it was never 944 * incorrectly for the PORT or it was never
955 * assigned to a PORT 945 * assigned to a PORT
956 */ 946 */
957 return scic_sds_controller_start_next_phy(scic); 947 return scic_sds_controller_start_next_phy(ihost);
958 } 948 }
959 } 949 }
960 950
961 status = scic_sds_phy_start(iphy); 951 status = scic_sds_phy_start(iphy);
962 952
963 if (status == SCI_SUCCESS) { 953 if (status == SCI_SUCCESS) {
964 sci_mod_timer(&scic->phy_timer, 954 sci_mod_timer(&ihost->phy_timer,
965 SCIC_SDS_CONTROLLER_PHY_START_TIMEOUT); 955 SCIC_SDS_CONTROLLER_PHY_START_TIMEOUT);
966 scic->phy_startup_timer_pending = true; 956 ihost->phy_startup_timer_pending = true;
967 } else { 957 } else {
968 dev_warn(scic_to_dev(scic), 958 dev_warn(&ihost->pdev->dev,
969 "%s: Controller stop operation failed " 959 "%s: Controller stop operation failed "
970 "to stop phy %d because of status " 960 "to stop phy %d because of status "
971 "%d.\n", 961 "%d.\n",
972 __func__, 962 __func__,
973 ihost->phys[scic->next_phy_to_start].phy_index, 963 ihost->phys[ihost->next_phy_to_start].phy_index,
974 status); 964 status);
975 } 965 }
976 966
977 scic->next_phy_to_start++; 967 ihost->next_phy_to_start++;
978 } 968 }
979 969
980 return status; 970 return status;
@@ -983,8 +973,7 @@ static enum sci_status scic_sds_controller_start_next_phy(struct scic_sds_contro
983static void phy_startup_timeout(unsigned long data) 973static void phy_startup_timeout(unsigned long data)
984{ 974{
985 struct sci_timer *tmr = (struct sci_timer *)data; 975 struct sci_timer *tmr = (struct sci_timer *)data;
986 struct scic_sds_controller *scic = container_of(tmr, typeof(*scic), phy_timer); 976 struct isci_host *ihost = container_of(tmr, typeof(*ihost), phy_timer);
987 struct isci_host *ihost = scic_to_ihost(scic);
988 unsigned long flags; 977 unsigned long flags;
989 enum sci_status status; 978 enum sci_status status;
990 979
@@ -993,10 +982,10 @@ static void phy_startup_timeout(unsigned long data)
993 if (tmr->cancel) 982 if (tmr->cancel)
994 goto done; 983 goto done;
995 984
996 scic->phy_startup_timer_pending = false; 985 ihost->phy_startup_timer_pending = false;
997 986
998 do { 987 do {
999 status = scic_sds_controller_start_next_phy(scic); 988 status = scic_sds_controller_start_next_phy(ihost);
1000 } while (status != SCI_SUCCESS); 989 } while (status != SCI_SUCCESS);
1001 990
1002done: 991done:
@@ -1008,15 +997,14 @@ static u16 isci_tci_active(struct isci_host *ihost)
1008 return CIRC_CNT(ihost->tci_head, ihost->tci_tail, SCI_MAX_IO_REQUESTS); 997 return CIRC_CNT(ihost->tci_head, ihost->tci_tail, SCI_MAX_IO_REQUESTS);
1009} 998}
1010 999
1011static enum sci_status scic_controller_start(struct scic_sds_controller *scic, 1000static enum sci_status scic_controller_start(struct isci_host *ihost,
1012 u32 timeout) 1001 u32 timeout)
1013{ 1002{
1014 struct isci_host *ihost = scic_to_ihost(scic);
1015 enum sci_status result; 1003 enum sci_status result;
1016 u16 index; 1004 u16 index;
1017 1005
1018 if (scic->sm.current_state_id != SCIC_INITIALIZED) { 1006 if (ihost->sm.current_state_id != SCIC_INITIALIZED) {
1019 dev_warn(scic_to_dev(scic), 1007 dev_warn(&ihost->pdev->dev,
1020 "SCIC Controller start operation requested in " 1008 "SCIC Controller start operation requested in "
1021 "invalid state\n"); 1009 "invalid state\n");
1022 return SCI_FAILURE_INVALID_STATE; 1010 return SCI_FAILURE_INVALID_STATE;
@@ -1026,34 +1014,34 @@ static enum sci_status scic_controller_start(struct scic_sds_controller *scic,
1026 BUILD_BUG_ON(SCI_MAX_IO_REQUESTS > 1 << sizeof(ihost->tci_pool[0]) * 8); 1014 BUILD_BUG_ON(SCI_MAX_IO_REQUESTS > 1 << sizeof(ihost->tci_pool[0]) * 8);
1027 ihost->tci_head = 0; 1015 ihost->tci_head = 0;
1028 ihost->tci_tail = 0; 1016 ihost->tci_tail = 0;
1029 for (index = 0; index < scic->task_context_entries; index++) 1017 for (index = 0; index < ihost->task_context_entries; index++)
1030 isci_tci_free(ihost, index); 1018 isci_tci_free(ihost, index);
1031 1019
1032 /* Build the RNi free pool */ 1020 /* Build the RNi free pool */
1033 scic_sds_remote_node_table_initialize( 1021 scic_sds_remote_node_table_initialize(
1034 &scic->available_remote_nodes, 1022 &ihost->available_remote_nodes,
1035 scic->remote_node_entries); 1023 ihost->remote_node_entries);
1036 1024
1037 /* 1025 /*
1038 * Before anything else lets make sure we will not be 1026 * Before anything else lets make sure we will not be
1039 * interrupted by the hardware. 1027 * interrupted by the hardware.
1040 */ 1028 */
1041 scic_controller_disable_interrupts(scic); 1029 scic_controller_disable_interrupts(ihost);
1042 1030
1043 /* Enable the port task scheduler */ 1031 /* Enable the port task scheduler */
1044 scic_sds_controller_enable_port_task_scheduler(scic); 1032 scic_sds_controller_enable_port_task_scheduler(ihost);
1045 1033
1046 /* Assign all the task entries to scic physical function */ 1034 /* Assign all the task entries to ihost physical function */
1047 scic_sds_controller_assign_task_entries(scic); 1035 scic_sds_controller_assign_task_entries(ihost);
1048 1036
1049 /* Now initialize the completion queue */ 1037 /* Now initialize the completion queue */
1050 scic_sds_controller_initialize_completion_queue(scic); 1038 scic_sds_controller_initialize_completion_queue(ihost);
1051 1039
1052 /* Initialize the unsolicited frame queue for use */ 1040 /* Initialize the unsolicited frame queue for use */
1053 scic_sds_controller_initialize_unsolicited_frame_queue(scic); 1041 scic_sds_controller_initialize_unsolicited_frame_queue(ihost);
1054 1042
1055 /* Start all of the ports on this controller */ 1043 /* Start all of the ports on this controller */
1056 for (index = 0; index < scic->logical_port_entries; index++) { 1044 for (index = 0; index < ihost->logical_port_entries; index++) {
1057 struct isci_port *iport = &ihost->ports[index]; 1045 struct isci_port *iport = &ihost->ports[index];
1058 1046
1059 result = scic_sds_port_start(iport); 1047 result = scic_sds_port_start(iport);
@@ -1061,11 +1049,11 @@ static enum sci_status scic_controller_start(struct scic_sds_controller *scic,
1061 return result; 1049 return result;
1062 } 1050 }
1063 1051
1064 scic_sds_controller_start_next_phy(scic); 1052 scic_sds_controller_start_next_phy(ihost);
1065 1053
1066 sci_mod_timer(&scic->timer, timeout); 1054 sci_mod_timer(&ihost->timer, timeout);
1067 1055
1068 sci_change_state(&scic->sm, SCIC_STARTING); 1056 sci_change_state(&ihost->sm, SCIC_STARTING);
1069 1057
1070 return SCI_SUCCESS; 1058 return SCI_SUCCESS;
1071} 1059}
@@ -1073,35 +1061,35 @@ static enum sci_status scic_controller_start(struct scic_sds_controller *scic,
1073void isci_host_scan_start(struct Scsi_Host *shost) 1061void isci_host_scan_start(struct Scsi_Host *shost)
1074{ 1062{
1075 struct isci_host *ihost = SHOST_TO_SAS_HA(shost)->lldd_ha; 1063 struct isci_host *ihost = SHOST_TO_SAS_HA(shost)->lldd_ha;
1076 unsigned long tmo = scic_controller_get_suggested_start_timeout(&ihost->sci); 1064 unsigned long tmo = scic_controller_get_suggested_start_timeout(ihost);
1077 1065
1078 set_bit(IHOST_START_PENDING, &ihost->flags); 1066 set_bit(IHOST_START_PENDING, &ihost->flags);
1079 1067
1080 spin_lock_irq(&ihost->scic_lock); 1068 spin_lock_irq(&ihost->scic_lock);
1081 scic_controller_start(&ihost->sci, tmo); 1069 scic_controller_start(ihost, tmo);
1082 scic_controller_enable_interrupts(&ihost->sci); 1070 scic_controller_enable_interrupts(ihost);
1083 spin_unlock_irq(&ihost->scic_lock); 1071 spin_unlock_irq(&ihost->scic_lock);
1084} 1072}
1085 1073
1086static void isci_host_stop_complete(struct isci_host *ihost, enum sci_status completion_status) 1074static void isci_host_stop_complete(struct isci_host *ihost, enum sci_status completion_status)
1087{ 1075{
1088 isci_host_change_state(ihost, isci_stopped); 1076 isci_host_change_state(ihost, isci_stopped);
1089 scic_controller_disable_interrupts(&ihost->sci); 1077 scic_controller_disable_interrupts(ihost);
1090 clear_bit(IHOST_STOP_PENDING, &ihost->flags); 1078 clear_bit(IHOST_STOP_PENDING, &ihost->flags);
1091 wake_up(&ihost->eventq); 1079 wake_up(&ihost->eventq);
1092} 1080}
1093 1081
1094static void scic_sds_controller_completion_handler(struct scic_sds_controller *scic) 1082static void scic_sds_controller_completion_handler(struct isci_host *ihost)
1095{ 1083{
1096 /* Empty out the completion queue */ 1084 /* Empty out the completion queue */
1097 if (scic_sds_controller_completion_queue_has_entries(scic)) 1085 if (scic_sds_controller_completion_queue_has_entries(ihost))
1098 scic_sds_controller_process_completions(scic); 1086 scic_sds_controller_process_completions(ihost);
1099 1087
1100 /* Clear the interrupt and enable all interrupts again */ 1088 /* Clear the interrupt and enable all interrupts again */
1101 writel(SMU_ISR_COMPLETION, &scic->smu_registers->interrupt_status); 1089 writel(SMU_ISR_COMPLETION, &ihost->smu_registers->interrupt_status);
1102 /* Could we write the value of SMU_ISR_COMPLETION? */ 1090 /* Could we write the value of SMU_ISR_COMPLETION? */
1103 writel(0xFF000000, &scic->smu_registers->interrupt_mask); 1091 writel(0xFF000000, &ihost->smu_registers->interrupt_mask);
1104 writel(0, &scic->smu_registers->interrupt_mask); 1092 writel(0, &ihost->smu_registers->interrupt_mask);
1105} 1093}
1106 1094
1107/** 1095/**
@@ -1114,7 +1102,7 @@ static void scic_sds_controller_completion_handler(struct scic_sds_controller *s
1114 */ 1102 */
1115static void isci_host_completion_routine(unsigned long data) 1103static void isci_host_completion_routine(unsigned long data)
1116{ 1104{
1117 struct isci_host *isci_host = (struct isci_host *)data; 1105 struct isci_host *ihost = (struct isci_host *)data;
1118 struct list_head completed_request_list; 1106 struct list_head completed_request_list;
1119 struct list_head errored_request_list; 1107 struct list_head errored_request_list;
1120 struct list_head *current_position; 1108 struct list_head *current_position;
@@ -1126,20 +1114,20 @@ static void isci_host_completion_routine(unsigned long data)
1126 INIT_LIST_HEAD(&completed_request_list); 1114 INIT_LIST_HEAD(&completed_request_list);
1127 INIT_LIST_HEAD(&errored_request_list); 1115 INIT_LIST_HEAD(&errored_request_list);
1128 1116
1129 spin_lock_irq(&isci_host->scic_lock); 1117 spin_lock_irq(&ihost->scic_lock);
1130 1118
1131 scic_sds_controller_completion_handler(&isci_host->sci); 1119 scic_sds_controller_completion_handler(ihost);
1132 1120
1133 /* Take the lists of completed I/Os from the host. */ 1121 /* Take the lists of completed I/Os from the host. */
1134 1122
1135 list_splice_init(&isci_host->requests_to_complete, 1123 list_splice_init(&ihost->requests_to_complete,
1136 &completed_request_list); 1124 &completed_request_list);
1137 1125
1138 /* Take the list of errored I/Os from the host. */ 1126 /* Take the list of errored I/Os from the host. */
1139 list_splice_init(&isci_host->requests_to_errorback, 1127 list_splice_init(&ihost->requests_to_errorback,
1140 &errored_request_list); 1128 &errored_request_list);
1141 1129
1142 spin_unlock_irq(&isci_host->scic_lock); 1130 spin_unlock_irq(&ihost->scic_lock);
1143 1131
1144 /* Process any completions in the lists. */ 1132 /* Process any completions in the lists. */
1145 list_for_each_safe(current_position, next_position, 1133 list_for_each_safe(current_position, next_position,
@@ -1150,7 +1138,7 @@ static void isci_host_completion_routine(unsigned long data)
1150 task = isci_request_access_task(request); 1138 task = isci_request_access_task(request);
1151 1139
1152 /* Normal notification (task_done) */ 1140 /* Normal notification (task_done) */
1153 dev_dbg(&isci_host->pdev->dev, 1141 dev_dbg(&ihost->pdev->dev,
1154 "%s: Normal - request/task = %p/%p\n", 1142 "%s: Normal - request/task = %p/%p\n",
1155 __func__, 1143 __func__,
1156 request, 1144 request,
@@ -1169,9 +1157,9 @@ static void isci_host_completion_routine(unsigned long data)
1169 } 1157 }
1170 } 1158 }
1171 1159
1172 spin_lock_irq(&isci_host->scic_lock); 1160 spin_lock_irq(&ihost->scic_lock);
1173 isci_free_tag(isci_host, request->io_tag); 1161 isci_free_tag(ihost, request->io_tag);
1174 spin_unlock_irq(&isci_host->scic_lock); 1162 spin_unlock_irq(&ihost->scic_lock);
1175 } 1163 }
1176 list_for_each_entry_safe(request, next_request, &errored_request_list, 1164 list_for_each_entry_safe(request, next_request, &errored_request_list,
1177 completed_node) { 1165 completed_node) {
@@ -1179,7 +1167,7 @@ static void isci_host_completion_routine(unsigned long data)
1179 task = isci_request_access_task(request); 1167 task = isci_request_access_task(request);
1180 1168
1181 /* Use sas_task_abort */ 1169 /* Use sas_task_abort */
1182 dev_warn(&isci_host->pdev->dev, 1170 dev_warn(&ihost->pdev->dev,
1183 "%s: Error - request/task = %p/%p\n", 1171 "%s: Error - request/task = %p/%p\n",
1184 __func__, 1172 __func__,
1185 request, 1173 request,
@@ -1202,13 +1190,13 @@ static void isci_host_completion_routine(unsigned long data)
1202 * it. 1190 * it.
1203 */ 1191 */
1204 1192
1205 spin_lock_irq(&isci_host->scic_lock); 1193 spin_lock_irq(&ihost->scic_lock);
1206 /* Remove the request from the remote device's list 1194 /* Remove the request from the remote device's list
1207 * of pending requests. 1195 * of pending requests.
1208 */ 1196 */
1209 list_del_init(&request->dev_node); 1197 list_del_init(&request->dev_node);
1210 isci_free_tag(isci_host, request->io_tag); 1198 isci_free_tag(ihost, request->io_tag);
1211 spin_unlock_irq(&isci_host->scic_lock); 1199 spin_unlock_irq(&ihost->scic_lock);
1212 } 1200 }
1213 } 1201 }
1214 1202
@@ -1232,18 +1220,18 @@ static void isci_host_completion_routine(unsigned long data)
1232 * controller is already in the STOPPED state. SCI_FAILURE_INVALID_STATE if the 1220 * controller is already in the STOPPED state. SCI_FAILURE_INVALID_STATE if the
1233 * controller is not either in the STARTED or STOPPED states. 1221 * controller is not either in the STARTED or STOPPED states.
1234 */ 1222 */
1235static enum sci_status scic_controller_stop(struct scic_sds_controller *scic, 1223static enum sci_status scic_controller_stop(struct isci_host *ihost,
1236 u32 timeout) 1224 u32 timeout)
1237{ 1225{
1238 if (scic->sm.current_state_id != SCIC_READY) { 1226 if (ihost->sm.current_state_id != SCIC_READY) {
1239 dev_warn(scic_to_dev(scic), 1227 dev_warn(&ihost->pdev->dev,
1240 "SCIC Controller stop operation requested in " 1228 "SCIC Controller stop operation requested in "
1241 "invalid state\n"); 1229 "invalid state\n");
1242 return SCI_FAILURE_INVALID_STATE; 1230 return SCI_FAILURE_INVALID_STATE;
1243 } 1231 }
1244 1232
1245 sci_mod_timer(&scic->timer, timeout); 1233 sci_mod_timer(&ihost->timer, timeout);
1246 sci_change_state(&scic->sm, SCIC_STOPPING); 1234 sci_change_state(&ihost->sm, SCIC_STOPPING);
1247 return SCI_SUCCESS; 1235 return SCI_SUCCESS;
1248} 1236}
1249 1237
@@ -1259,9 +1247,9 @@ static enum sci_status scic_controller_stop(struct scic_sds_controller *scic,
1259 * SCI_SUCCESS if the reset operation successfully started. SCI_FATAL_ERROR if 1247 * SCI_SUCCESS if the reset operation successfully started. SCI_FATAL_ERROR if
1260 * the controller reset operation is unable to complete. 1248 * the controller reset operation is unable to complete.
1261 */ 1249 */
1262static enum sci_status scic_controller_reset(struct scic_sds_controller *scic) 1250static enum sci_status scic_controller_reset(struct isci_host *ihost)
1263{ 1251{
1264 switch (scic->sm.current_state_id) { 1252 switch (ihost->sm.current_state_id) {
1265 case SCIC_RESET: 1253 case SCIC_RESET:
1266 case SCIC_READY: 1254 case SCIC_READY:
1267 case SCIC_STOPPED: 1255 case SCIC_STOPPED:
@@ -1270,10 +1258,10 @@ static enum sci_status scic_controller_reset(struct scic_sds_controller *scic)
1270 * The reset operation is not a graceful cleanup, just 1258 * The reset operation is not a graceful cleanup, just
1271 * perform the state transition. 1259 * perform the state transition.
1272 */ 1260 */
1273 sci_change_state(&scic->sm, SCIC_RESETTING); 1261 sci_change_state(&ihost->sm, SCIC_RESETTING);
1274 return SCI_SUCCESS; 1262 return SCI_SUCCESS;
1275 default: 1263 default:
1276 dev_warn(scic_to_dev(scic), 1264 dev_warn(&ihost->pdev->dev,
1277 "SCIC Controller reset operation requested in " 1265 "SCIC Controller reset operation requested in "
1278 "invalid state\n"); 1266 "invalid state\n");
1279 return SCI_FAILURE_INVALID_STATE; 1267 return SCI_FAILURE_INVALID_STATE;
@@ -1298,14 +1286,14 @@ void isci_host_deinit(struct isci_host *ihost)
1298 set_bit(IHOST_STOP_PENDING, &ihost->flags); 1286 set_bit(IHOST_STOP_PENDING, &ihost->flags);
1299 1287
1300 spin_lock_irq(&ihost->scic_lock); 1288 spin_lock_irq(&ihost->scic_lock);
1301 scic_controller_stop(&ihost->sci, SCIC_CONTROLLER_STOP_TIMEOUT); 1289 scic_controller_stop(ihost, SCIC_CONTROLLER_STOP_TIMEOUT);
1302 spin_unlock_irq(&ihost->scic_lock); 1290 spin_unlock_irq(&ihost->scic_lock);
1303 1291
1304 wait_for_stop(ihost); 1292 wait_for_stop(ihost);
1305 scic_controller_reset(&ihost->sci); 1293 scic_controller_reset(ihost);
1306 1294
1307 /* Cancel any/all outstanding port timers */ 1295 /* Cancel any/all outstanding port timers */
1308 for (i = 0; i < ihost->sci.logical_port_entries; i++) { 1296 for (i = 0; i < ihost->logical_port_entries; i++) {
1309 struct isci_port *iport = &ihost->ports[i]; 1297 struct isci_port *iport = &ihost->ports[i];
1310 del_timer_sync(&iport->timer.timer); 1298 del_timer_sync(&iport->timer.timer);
1311 } 1299 }
@@ -1316,13 +1304,13 @@ void isci_host_deinit(struct isci_host *ihost)
1316 del_timer_sync(&iphy->sata_timer.timer); 1304 del_timer_sync(&iphy->sata_timer.timer);
1317 } 1305 }
1318 1306
1319 del_timer_sync(&ihost->sci.port_agent.timer.timer); 1307 del_timer_sync(&ihost->port_agent.timer.timer);
1320 1308
1321 del_timer_sync(&ihost->sci.power_control.timer.timer); 1309 del_timer_sync(&ihost->power_control.timer.timer);
1322 1310
1323 del_timer_sync(&ihost->sci.timer.timer); 1311 del_timer_sync(&ihost->timer.timer);
1324 1312
1325 del_timer_sync(&ihost->sci.phy_timer.timer); 1313 del_timer_sync(&ihost->phy_timer.timer);
1326} 1314}
1327 1315
1328static void __iomem *scu_base(struct isci_host *isci_host) 1316static void __iomem *scu_base(struct isci_host *isci_host)
@@ -1369,16 +1357,16 @@ static void isci_user_parameters_get(
1369 1357
1370static void scic_sds_controller_initial_state_enter(struct sci_base_state_machine *sm) 1358static void scic_sds_controller_initial_state_enter(struct sci_base_state_machine *sm)
1371{ 1359{
1372 struct scic_sds_controller *scic = container_of(sm, typeof(*scic), sm); 1360 struct isci_host *ihost = container_of(sm, typeof(*ihost), sm);
1373 1361
1374 sci_change_state(&scic->sm, SCIC_RESET); 1362 sci_change_state(&ihost->sm, SCIC_RESET);
1375} 1363}
1376 1364
1377static inline void scic_sds_controller_starting_state_exit(struct sci_base_state_machine *sm) 1365static inline void scic_sds_controller_starting_state_exit(struct sci_base_state_machine *sm)
1378{ 1366{
1379 struct scic_sds_controller *scic = container_of(sm, typeof(*scic), sm); 1367 struct isci_host *ihost = container_of(sm, typeof(*ihost), sm);
1380 1368
1381 sci_del_timer(&scic->timer); 1369 sci_del_timer(&ihost->timer);
1382} 1370}
1383 1371
1384#define INTERRUPT_COALESCE_TIMEOUT_BASE_RANGE_LOWER_BOUND_NS 853 1372#define INTERRUPT_COALESCE_TIMEOUT_BASE_RANGE_LOWER_BOUND_NS 853
@@ -1405,10 +1393,10 @@ static inline void scic_sds_controller_starting_state_exit(struct sci_base_state
1405 * SCI_SUCCESS The user successfully updated the interrutp coalescence. 1393 * SCI_SUCCESS The user successfully updated the interrutp coalescence.
1406 * SCI_FAILURE_INVALID_PARAMETER_VALUE The user input value is out of range. 1394 * SCI_FAILURE_INVALID_PARAMETER_VALUE The user input value is out of range.
1407 */ 1395 */
1408static enum sci_status scic_controller_set_interrupt_coalescence( 1396static enum sci_status
1409 struct scic_sds_controller *scic_controller, 1397scic_controller_set_interrupt_coalescence(struct isci_host *ihost,
1410 u32 coalesce_number, 1398 u32 coalesce_number,
1411 u32 coalesce_timeout) 1399 u32 coalesce_timeout)
1412{ 1400{
1413 u8 timeout_encode = 0; 1401 u8 timeout_encode = 0;
1414 u32 min = 0; 1402 u32 min = 0;
@@ -1491,11 +1479,11 @@ static enum sci_status scic_controller_set_interrupt_coalescence(
1491 1479
1492 writel(SMU_ICC_GEN_VAL(NUMBER, coalesce_number) | 1480 writel(SMU_ICC_GEN_VAL(NUMBER, coalesce_number) |
1493 SMU_ICC_GEN_VAL(TIMER, timeout_encode), 1481 SMU_ICC_GEN_VAL(TIMER, timeout_encode),
1494 &scic_controller->smu_registers->interrupt_coalesce_control); 1482 &ihost->smu_registers->interrupt_coalesce_control);
1495 1483
1496 1484
1497 scic_controller->interrupt_coalesce_number = (u16)coalesce_number; 1485 ihost->interrupt_coalesce_number = (u16)coalesce_number;
1498 scic_controller->interrupt_coalesce_timeout = coalesce_timeout / 100; 1486 ihost->interrupt_coalesce_timeout = coalesce_timeout / 100;
1499 1487
1500 return SCI_SUCCESS; 1488 return SCI_SUCCESS;
1501} 1489}
@@ -1503,26 +1491,25 @@ static enum sci_status scic_controller_set_interrupt_coalescence(
1503 1491
1504static void scic_sds_controller_ready_state_enter(struct sci_base_state_machine *sm) 1492static void scic_sds_controller_ready_state_enter(struct sci_base_state_machine *sm)
1505{ 1493{
1506 struct scic_sds_controller *scic = container_of(sm, typeof(*scic), sm); 1494 struct isci_host *ihost = container_of(sm, typeof(*ihost), sm);
1507 1495
1508 /* set the default interrupt coalescence number and timeout value. */ 1496 /* set the default interrupt coalescence number and timeout value. */
1509 scic_controller_set_interrupt_coalescence(scic, 0x10, 250); 1497 scic_controller_set_interrupt_coalescence(ihost, 0x10, 250);
1510} 1498}
1511 1499
1512static void scic_sds_controller_ready_state_exit(struct sci_base_state_machine *sm) 1500static void scic_sds_controller_ready_state_exit(struct sci_base_state_machine *sm)
1513{ 1501{
1514 struct scic_sds_controller *scic = container_of(sm, typeof(*scic), sm); 1502 struct isci_host *ihost = container_of(sm, typeof(*ihost), sm);
1515 1503
1516 /* disable interrupt coalescence. */ 1504 /* disable interrupt coalescence. */
1517 scic_controller_set_interrupt_coalescence(scic, 0, 0); 1505 scic_controller_set_interrupt_coalescence(ihost, 0, 0);
1518} 1506}
1519 1507
1520static enum sci_status scic_sds_controller_stop_phys(struct scic_sds_controller *scic) 1508static enum sci_status scic_sds_controller_stop_phys(struct isci_host *ihost)
1521{ 1509{
1522 u32 index; 1510 u32 index;
1523 enum sci_status status; 1511 enum sci_status status;
1524 enum sci_status phy_status; 1512 enum sci_status phy_status;
1525 struct isci_host *ihost = scic_to_ihost(scic);
1526 1513
1527 status = SCI_SUCCESS; 1514 status = SCI_SUCCESS;
1528 1515
@@ -1533,7 +1520,7 @@ static enum sci_status scic_sds_controller_stop_phys(struct scic_sds_controller
1533 phy_status != SCI_FAILURE_INVALID_STATE) { 1520 phy_status != SCI_FAILURE_INVALID_STATE) {
1534 status = SCI_FAILURE; 1521 status = SCI_FAILURE;
1535 1522
1536 dev_warn(scic_to_dev(scic), 1523 dev_warn(&ihost->pdev->dev,
1537 "%s: Controller stop operation failed to stop " 1524 "%s: Controller stop operation failed to stop "
1538 "phy %d because of status %d.\n", 1525 "phy %d because of status %d.\n",
1539 __func__, 1526 __func__,
@@ -1544,14 +1531,13 @@ static enum sci_status scic_sds_controller_stop_phys(struct scic_sds_controller
1544 return status; 1531 return status;
1545} 1532}
1546 1533
1547static enum sci_status scic_sds_controller_stop_ports(struct scic_sds_controller *scic) 1534static enum sci_status scic_sds_controller_stop_ports(struct isci_host *ihost)
1548{ 1535{
1549 u32 index; 1536 u32 index;
1550 enum sci_status port_status; 1537 enum sci_status port_status;
1551 enum sci_status status = SCI_SUCCESS; 1538 enum sci_status status = SCI_SUCCESS;
1552 struct isci_host *ihost = scic_to_ihost(scic);
1553 1539
1554 for (index = 0; index < scic->logical_port_entries; index++) { 1540 for (index = 0; index < ihost->logical_port_entries; index++) {
1555 struct isci_port *iport = &ihost->ports[index]; 1541 struct isci_port *iport = &ihost->ports[index];
1556 1542
1557 port_status = scic_sds_port_stop(iport); 1543 port_status = scic_sds_port_stop(iport);
@@ -1560,7 +1546,7 @@ static enum sci_status scic_sds_controller_stop_ports(struct scic_sds_controller
1560 (port_status != SCI_FAILURE_INVALID_STATE)) { 1546 (port_status != SCI_FAILURE_INVALID_STATE)) {
1561 status = SCI_FAILURE; 1547 status = SCI_FAILURE;
1562 1548
1563 dev_warn(scic_to_dev(scic), 1549 dev_warn(&ihost->pdev->dev,
1564 "%s: Controller stop operation failed to " 1550 "%s: Controller stop operation failed to "
1565 "stop port %d because of status %d.\n", 1551 "stop port %d because of status %d.\n",
1566 __func__, 1552 __func__,
@@ -1572,7 +1558,7 @@ static enum sci_status scic_sds_controller_stop_ports(struct scic_sds_controller
1572 return status; 1558 return status;
1573} 1559}
1574 1560
1575static enum sci_status scic_sds_controller_stop_devices(struct scic_sds_controller *scic) 1561static enum sci_status scic_sds_controller_stop_devices(struct isci_host *ihost)
1576{ 1562{
1577 u32 index; 1563 u32 index;
1578 enum sci_status status; 1564 enum sci_status status;
@@ -1580,19 +1566,19 @@ static enum sci_status scic_sds_controller_stop_devices(struct scic_sds_controll
1580 1566
1581 status = SCI_SUCCESS; 1567 status = SCI_SUCCESS;
1582 1568
1583 for (index = 0; index < scic->remote_node_entries; index++) { 1569 for (index = 0; index < ihost->remote_node_entries; index++) {
1584 if (scic->device_table[index] != NULL) { 1570 if (ihost->device_table[index] != NULL) {
1585 /* / @todo What timeout value do we want to provide to this request? */ 1571 /* / @todo What timeout value do we want to provide to this request? */
1586 device_status = scic_remote_device_stop(scic->device_table[index], 0); 1572 device_status = scic_remote_device_stop(ihost->device_table[index], 0);
1587 1573
1588 if ((device_status != SCI_SUCCESS) && 1574 if ((device_status != SCI_SUCCESS) &&
1589 (device_status != SCI_FAILURE_INVALID_STATE)) { 1575 (device_status != SCI_FAILURE_INVALID_STATE)) {
1590 dev_warn(scic_to_dev(scic), 1576 dev_warn(&ihost->pdev->dev,
1591 "%s: Controller stop operation failed " 1577 "%s: Controller stop operation failed "
1592 "to stop device 0x%p because of " 1578 "to stop device 0x%p because of "
1593 "status %d.\n", 1579 "status %d.\n",
1594 __func__, 1580 __func__,
1595 scic->device_table[index], device_status); 1581 ihost->device_table[index], device_status);
1596 } 1582 }
1597 } 1583 }
1598 } 1584 }
@@ -1602,19 +1588,19 @@ static enum sci_status scic_sds_controller_stop_devices(struct scic_sds_controll
1602 1588
1603static void scic_sds_controller_stopping_state_enter(struct sci_base_state_machine *sm) 1589static void scic_sds_controller_stopping_state_enter(struct sci_base_state_machine *sm)
1604{ 1590{
1605 struct scic_sds_controller *scic = container_of(sm, typeof(*scic), sm); 1591 struct isci_host *ihost = container_of(sm, typeof(*ihost), sm);
1606 1592
1607 /* Stop all of the components for this controller */ 1593 /* Stop all of the components for this controller */
1608 scic_sds_controller_stop_phys(scic); 1594 scic_sds_controller_stop_phys(ihost);
1609 scic_sds_controller_stop_ports(scic); 1595 scic_sds_controller_stop_ports(ihost);
1610 scic_sds_controller_stop_devices(scic); 1596 scic_sds_controller_stop_devices(ihost);
1611} 1597}
1612 1598
1613static void scic_sds_controller_stopping_state_exit(struct sci_base_state_machine *sm) 1599static void scic_sds_controller_stopping_state_exit(struct sci_base_state_machine *sm)
1614{ 1600{
1615 struct scic_sds_controller *scic = container_of(sm, typeof(*scic), sm); 1601 struct isci_host *ihost = container_of(sm, typeof(*ihost), sm);
1616 1602
1617 sci_del_timer(&scic->timer); 1603 sci_del_timer(&ihost->timer);
1618} 1604}
1619 1605
1620 1606
@@ -1623,30 +1609,30 @@ static void scic_sds_controller_stopping_state_exit(struct sci_base_state_machin
1623 * 1609 *
1624 * This method will reset the controller hardware. 1610 * This method will reset the controller hardware.
1625 */ 1611 */
1626static void scic_sds_controller_reset_hardware(struct scic_sds_controller *scic) 1612static void scic_sds_controller_reset_hardware(struct isci_host *ihost)
1627{ 1613{
1628 /* Disable interrupts so we dont take any spurious interrupts */ 1614 /* Disable interrupts so we dont take any spurious interrupts */
1629 scic_controller_disable_interrupts(scic); 1615 scic_controller_disable_interrupts(ihost);
1630 1616
1631 /* Reset the SCU */ 1617 /* Reset the SCU */
1632 writel(0xFFFFFFFF, &scic->smu_registers->soft_reset_control); 1618 writel(0xFFFFFFFF, &ihost->smu_registers->soft_reset_control);
1633 1619
1634 /* Delay for 1ms to before clearing the CQP and UFQPR. */ 1620 /* Delay for 1ms to before clearing the CQP and UFQPR. */
1635 udelay(1000); 1621 udelay(1000);
1636 1622
1637 /* The write to the CQGR clears the CQP */ 1623 /* The write to the CQGR clears the CQP */
1638 writel(0x00000000, &scic->smu_registers->completion_queue_get); 1624 writel(0x00000000, &ihost->smu_registers->completion_queue_get);
1639 1625
1640 /* The write to the UFQGP clears the UFQPR */ 1626 /* The write to the UFQGP clears the UFQPR */
1641 writel(0, &scic->scu_registers->sdma.unsolicited_frame_get_pointer); 1627 writel(0, &ihost->scu_registers->sdma.unsolicited_frame_get_pointer);
1642} 1628}
1643 1629
1644static void scic_sds_controller_resetting_state_enter(struct sci_base_state_machine *sm) 1630static void scic_sds_controller_resetting_state_enter(struct sci_base_state_machine *sm)
1645{ 1631{
1646 struct scic_sds_controller *scic = container_of(sm, typeof(*scic), sm); 1632 struct isci_host *ihost = container_of(sm, typeof(*ihost), sm);
1647 1633
1648 scic_sds_controller_reset_hardware(scic); 1634 scic_sds_controller_reset_hardware(ihost);
1649 sci_change_state(&scic->sm, SCIC_RESET); 1635 sci_change_state(&ihost->sm, SCIC_RESET);
1650} 1636}
1651 1637
1652static const struct sci_base_state scic_sds_controller_state_table[] = { 1638static const struct sci_base_state scic_sds_controller_state_table[] = {
@@ -1674,58 +1660,56 @@ static const struct sci_base_state scic_sds_controller_state_table[] = {
1674 [SCIC_FAILED] = {} 1660 [SCIC_FAILED] = {}
1675}; 1661};
1676 1662
1677static void scic_sds_controller_set_default_config_parameters(struct scic_sds_controller *scic) 1663static void scic_sds_controller_set_default_config_parameters(struct isci_host *ihost)
1678{ 1664{
1679 /* these defaults are overridden by the platform / firmware */ 1665 /* these defaults are overridden by the platform / firmware */
1680 struct isci_host *ihost = scic_to_ihost(scic);
1681 u16 index; 1666 u16 index;
1682 1667
1683 /* Default to APC mode. */ 1668 /* Default to APC mode. */
1684 scic->oem_parameters.sds1.controller.mode_type = SCIC_PORT_AUTOMATIC_CONFIGURATION_MODE; 1669 ihost->oem_parameters.sds1.controller.mode_type = SCIC_PORT_AUTOMATIC_CONFIGURATION_MODE;
1685 1670
1686 /* Default to APC mode. */ 1671 /* Default to APC mode. */
1687 scic->oem_parameters.sds1.controller.max_concurrent_dev_spin_up = 1; 1672 ihost->oem_parameters.sds1.controller.max_concurrent_dev_spin_up = 1;
1688 1673
1689 /* Default to no SSC operation. */ 1674 /* Default to no SSC operation. */
1690 scic->oem_parameters.sds1.controller.do_enable_ssc = false; 1675 ihost->oem_parameters.sds1.controller.do_enable_ssc = false;
1691 1676
1692 /* Initialize all of the port parameter information to narrow ports. */ 1677 /* Initialize all of the port parameter information to narrow ports. */
1693 for (index = 0; index < SCI_MAX_PORTS; index++) { 1678 for (index = 0; index < SCI_MAX_PORTS; index++) {
1694 scic->oem_parameters.sds1.ports[index].phy_mask = 0; 1679 ihost->oem_parameters.sds1.ports[index].phy_mask = 0;
1695 } 1680 }
1696 1681
1697 /* Initialize all of the phy parameter information. */ 1682 /* Initialize all of the phy parameter information. */
1698 for (index = 0; index < SCI_MAX_PHYS; index++) { 1683 for (index = 0; index < SCI_MAX_PHYS; index++) {
1699 /* Default to 6G (i.e. Gen 3) for now. */ 1684 /* Default to 6G (i.e. Gen 3) for now. */
1700 scic->user_parameters.sds1.phys[index].max_speed_generation = 3; 1685 ihost->user_parameters.sds1.phys[index].max_speed_generation = 3;
1701 1686
1702 /* the frequencies cannot be 0 */ 1687 /* the frequencies cannot be 0 */
1703 scic->user_parameters.sds1.phys[index].align_insertion_frequency = 0x7f; 1688 ihost->user_parameters.sds1.phys[index].align_insertion_frequency = 0x7f;
1704 scic->user_parameters.sds1.phys[index].in_connection_align_insertion_frequency = 0xff; 1689 ihost->user_parameters.sds1.phys[index].in_connection_align_insertion_frequency = 0xff;
1705 scic->user_parameters.sds1.phys[index].notify_enable_spin_up_insertion_frequency = 0x33; 1690 ihost->user_parameters.sds1.phys[index].notify_enable_spin_up_insertion_frequency = 0x33;
1706 1691
1707 /* 1692 /*
1708 * Previous Vitesse based expanders had a arbitration issue that 1693 * Previous Vitesse based expanders had a arbitration issue that
1709 * is worked around by having the upper 32-bits of SAS address 1694 * is worked around by having the upper 32-bits of SAS address
1710 * with a value greater then the Vitesse company identifier. 1695 * with a value greater then the Vitesse company identifier.
1711 * Hence, usage of 0x5FCFFFFF. */ 1696 * Hence, usage of 0x5FCFFFFF. */
1712 scic->oem_parameters.sds1.phys[index].sas_address.low = 0x1 + ihost->id; 1697 ihost->oem_parameters.sds1.phys[index].sas_address.low = 0x1 + ihost->id;
1713 scic->oem_parameters.sds1.phys[index].sas_address.high = 0x5FCFFFFF; 1698 ihost->oem_parameters.sds1.phys[index].sas_address.high = 0x5FCFFFFF;
1714 } 1699 }
1715 1700
1716 scic->user_parameters.sds1.stp_inactivity_timeout = 5; 1701 ihost->user_parameters.sds1.stp_inactivity_timeout = 5;
1717 scic->user_parameters.sds1.ssp_inactivity_timeout = 5; 1702 ihost->user_parameters.sds1.ssp_inactivity_timeout = 5;
1718 scic->user_parameters.sds1.stp_max_occupancy_timeout = 5; 1703 ihost->user_parameters.sds1.stp_max_occupancy_timeout = 5;
1719 scic->user_parameters.sds1.ssp_max_occupancy_timeout = 20; 1704 ihost->user_parameters.sds1.ssp_max_occupancy_timeout = 20;
1720 scic->user_parameters.sds1.no_outbound_task_timeout = 20; 1705 ihost->user_parameters.sds1.no_outbound_task_timeout = 20;
1721} 1706}
1722 1707
1723static void controller_timeout(unsigned long data) 1708static void controller_timeout(unsigned long data)
1724{ 1709{
1725 struct sci_timer *tmr = (struct sci_timer *)data; 1710 struct sci_timer *tmr = (struct sci_timer *)data;
1726 struct scic_sds_controller *scic = container_of(tmr, typeof(*scic), timer); 1711 struct isci_host *ihost = container_of(tmr, typeof(*ihost), timer);
1727 struct isci_host *ihost = scic_to_ihost(scic); 1712 struct sci_base_state_machine *sm = &ihost->sm;
1728 struct sci_base_state_machine *sm = &scic->sm;
1729 unsigned long flags; 1713 unsigned long flags;
1730 1714
1731 spin_lock_irqsave(&ihost->scic_lock, flags); 1715 spin_lock_irqsave(&ihost->scic_lock, flags);
@@ -1734,12 +1718,12 @@ static void controller_timeout(unsigned long data)
1734 goto done; 1718 goto done;
1735 1719
1736 if (sm->current_state_id == SCIC_STARTING) 1720 if (sm->current_state_id == SCIC_STARTING)
1737 scic_sds_controller_transition_to_ready(scic, SCI_FAILURE_TIMEOUT); 1721 scic_sds_controller_transition_to_ready(ihost, SCI_FAILURE_TIMEOUT);
1738 else if (sm->current_state_id == SCIC_STOPPING) { 1722 else if (sm->current_state_id == SCIC_STOPPING) {
1739 sci_change_state(sm, SCIC_FAILED); 1723 sci_change_state(sm, SCIC_FAILED);
1740 isci_host_stop_complete(ihost, SCI_FAILURE_TIMEOUT); 1724 isci_host_stop_complete(ihost, SCI_FAILURE_TIMEOUT);
1741 } else /* / @todo Now what do we want to do in this case? */ 1725 } else /* / @todo Now what do we want to do in this case? */
1742 dev_err(scic_to_dev(scic), 1726 dev_err(&ihost->pdev->dev,
1743 "%s: Controller timer fired when controller was not " 1727 "%s: Controller timer fired when controller was not "
1744 "in a state being timed.\n", 1728 "in a state being timed.\n",
1745 __func__); 1729 __func__);
@@ -1764,24 +1748,23 @@ done:
1764 * SCI_FAILURE_UNSUPPORTED_INIT_DATA_VERSION This value is returned if the 1748 * SCI_FAILURE_UNSUPPORTED_INIT_DATA_VERSION This value is returned if the
1765 * controller does not support the supplied initialization data version. 1749 * controller does not support the supplied initialization data version.
1766 */ 1750 */
1767static enum sci_status scic_controller_construct(struct scic_sds_controller *scic, 1751static enum sci_status scic_controller_construct(struct isci_host *ihost,
1768 void __iomem *scu_base, 1752 void __iomem *scu_base,
1769 void __iomem *smu_base) 1753 void __iomem *smu_base)
1770{ 1754{
1771 struct isci_host *ihost = scic_to_ihost(scic);
1772 u8 i; 1755 u8 i;
1773 1756
1774 sci_init_sm(&scic->sm, scic_sds_controller_state_table, SCIC_INITIAL); 1757 sci_init_sm(&ihost->sm, scic_sds_controller_state_table, SCIC_INITIAL);
1775 1758
1776 scic->scu_registers = scu_base; 1759 ihost->scu_registers = scu_base;
1777 scic->smu_registers = smu_base; 1760 ihost->smu_registers = smu_base;
1778 1761
1779 scic_sds_port_configuration_agent_construct(&scic->port_agent); 1762 scic_sds_port_configuration_agent_construct(&ihost->port_agent);
1780 1763
1781 /* Construct the ports for this controller */ 1764 /* Construct the ports for this controller */
1782 for (i = 0; i < SCI_MAX_PORTS; i++) 1765 for (i = 0; i < SCI_MAX_PORTS; i++)
1783 scic_sds_port_construct(&ihost->ports[i], i, scic); 1766 scic_sds_port_construct(&ihost->ports[i], i, ihost);
1784 scic_sds_port_construct(&ihost->ports[i], SCIC_SDS_DUMMY_PORT, scic); 1767 scic_sds_port_construct(&ihost->ports[i], SCIC_SDS_DUMMY_PORT, ihost);
1785 1768
1786 /* Construct the phys for this controller */ 1769 /* Construct the phys for this controller */
1787 for (i = 0; i < SCI_MAX_PHYS; i++) { 1770 for (i = 0; i < SCI_MAX_PHYS; i++) {
@@ -1790,14 +1773,14 @@ static enum sci_status scic_controller_construct(struct scic_sds_controller *sci
1790 &ihost->ports[SCI_MAX_PORTS], i); 1773 &ihost->ports[SCI_MAX_PORTS], i);
1791 } 1774 }
1792 1775
1793 scic->invalid_phy_mask = 0; 1776 ihost->invalid_phy_mask = 0;
1794 1777
1795 sci_init_timer(&scic->timer, controller_timeout); 1778 sci_init_timer(&ihost->timer, controller_timeout);
1796 1779
1797 /* Initialize the User and OEM parameters to default values. */ 1780 /* Initialize the User and OEM parameters to default values. */
1798 scic_sds_controller_set_default_config_parameters(scic); 1781 scic_sds_controller_set_default_config_parameters(ihost);
1799 1782
1800 return scic_controller_reset(scic); 1783 return scic_controller_reset(ihost);
1801} 1784}
1802 1785
1803int scic_oem_parameters_validate(struct scic_sds_oem_params *oem) 1786int scic_oem_parameters_validate(struct scic_sds_oem_params *oem)
@@ -1834,10 +1817,10 @@ int scic_oem_parameters_validate(struct scic_sds_oem_params *oem)
1834 return 0; 1817 return 0;
1835} 1818}
1836 1819
1837static enum sci_status scic_oem_parameters_set(struct scic_sds_controller *scic, 1820static enum sci_status scic_oem_parameters_set(struct isci_host *ihost,
1838 union scic_oem_parameters *scic_parms) 1821 union scic_oem_parameters *scic_parms)
1839{ 1822{
1840 u32 state = scic->sm.current_state_id; 1823 u32 state = ihost->sm.current_state_id;
1841 1824
1842 if (state == SCIC_RESET || 1825 if (state == SCIC_RESET ||
1843 state == SCIC_INITIALIZING || 1826 state == SCIC_INITIALIZING ||
@@ -1845,7 +1828,7 @@ static enum sci_status scic_oem_parameters_set(struct scic_sds_controller *scic,
1845 1828
1846 if (scic_oem_parameters_validate(&scic_parms->sds1)) 1829 if (scic_oem_parameters_validate(&scic_parms->sds1))
1847 return SCI_FAILURE_INVALID_PARAMETER_VALUE; 1830 return SCI_FAILURE_INVALID_PARAMETER_VALUE;
1848 scic->oem_parameters.sds1 = scic_parms->sds1; 1831 ihost->oem_parameters.sds1 = scic_parms->sds1;
1849 1832
1850 return SCI_SUCCESS; 1833 return SCI_SUCCESS;
1851 } 1834 }
@@ -1854,17 +1837,16 @@ static enum sci_status scic_oem_parameters_set(struct scic_sds_controller *scic,
1854} 1837}
1855 1838
1856void scic_oem_parameters_get( 1839void scic_oem_parameters_get(
1857 struct scic_sds_controller *scic, 1840 struct isci_host *ihost,
1858 union scic_oem_parameters *scic_parms) 1841 union scic_oem_parameters *scic_parms)
1859{ 1842{
1860 memcpy(scic_parms, (&scic->oem_parameters), sizeof(*scic_parms)); 1843 memcpy(scic_parms, (&ihost->oem_parameters), sizeof(*scic_parms));
1861} 1844}
1862 1845
1863static void power_control_timeout(unsigned long data) 1846static void power_control_timeout(unsigned long data)
1864{ 1847{
1865 struct sci_timer *tmr = (struct sci_timer *)data; 1848 struct sci_timer *tmr = (struct sci_timer *)data;
1866 struct scic_sds_controller *scic = container_of(tmr, typeof(*scic), power_control.timer); 1849 struct isci_host *ihost = container_of(tmr, typeof(*ihost), power_control.timer);
1867 struct isci_host *ihost = scic_to_ihost(scic);
1868 struct isci_phy *iphy; 1850 struct isci_phy *iphy;
1869 unsigned long flags; 1851 unsigned long flags;
1870 u8 i; 1852 u8 i;
@@ -1874,29 +1856,29 @@ static void power_control_timeout(unsigned long data)
1874 if (tmr->cancel) 1856 if (tmr->cancel)
1875 goto done; 1857 goto done;
1876 1858
1877 scic->power_control.phys_granted_power = 0; 1859 ihost->power_control.phys_granted_power = 0;
1878 1860
1879 if (scic->power_control.phys_waiting == 0) { 1861 if (ihost->power_control.phys_waiting == 0) {
1880 scic->power_control.timer_started = false; 1862 ihost->power_control.timer_started = false;
1881 goto done; 1863 goto done;
1882 } 1864 }
1883 1865
1884 for (i = 0; i < SCI_MAX_PHYS; i++) { 1866 for (i = 0; i < SCI_MAX_PHYS; i++) {
1885 1867
1886 if (scic->power_control.phys_waiting == 0) 1868 if (ihost->power_control.phys_waiting == 0)
1887 break; 1869 break;
1888 1870
1889 iphy = scic->power_control.requesters[i]; 1871 iphy = ihost->power_control.requesters[i];
1890 if (iphy == NULL) 1872 if (iphy == NULL)
1891 continue; 1873 continue;
1892 1874
1893 if (scic->power_control.phys_granted_power >= 1875 if (ihost->power_control.phys_granted_power >=
1894 scic->oem_parameters.sds1.controller.max_concurrent_dev_spin_up) 1876 ihost->oem_parameters.sds1.controller.max_concurrent_dev_spin_up)
1895 break; 1877 break;
1896 1878
1897 scic->power_control.requesters[i] = NULL; 1879 ihost->power_control.requesters[i] = NULL;
1898 scic->power_control.phys_waiting--; 1880 ihost->power_control.phys_waiting--;
1899 scic->power_control.phys_granted_power++; 1881 ihost->power_control.phys_granted_power++;
1900 scic_sds_phy_consume_power_handler(iphy); 1882 scic_sds_phy_consume_power_handler(iphy);
1901 } 1883 }
1902 1884
@@ -1905,7 +1887,7 @@ static void power_control_timeout(unsigned long data)
1905 * timer in case another phy becomes ready. 1887 * timer in case another phy becomes ready.
1906 */ 1888 */
1907 sci_mod_timer(tmr, SCIC_SDS_CONTROLLER_POWER_CONTROL_INTERVAL); 1889 sci_mod_timer(tmr, SCIC_SDS_CONTROLLER_POWER_CONTROL_INTERVAL);
1908 scic->power_control.timer_started = true; 1890 ihost->power_control.timer_started = true;
1909 1891
1910done: 1892done:
1911 spin_unlock_irqrestore(&ihost->scic_lock, flags); 1893 spin_unlock_irqrestore(&ihost->scic_lock, flags);
@@ -1918,31 +1900,31 @@ done:
1918 * 1900 *
1919 */ 1901 */
1920void scic_sds_controller_power_control_queue_insert( 1902void scic_sds_controller_power_control_queue_insert(
1921 struct scic_sds_controller *scic, 1903 struct isci_host *ihost,
1922 struct isci_phy *iphy) 1904 struct isci_phy *iphy)
1923{ 1905{
1924 BUG_ON(iphy == NULL); 1906 BUG_ON(iphy == NULL);
1925 1907
1926 if (scic->power_control.phys_granted_power < 1908 if (ihost->power_control.phys_granted_power <
1927 scic->oem_parameters.sds1.controller.max_concurrent_dev_spin_up) { 1909 ihost->oem_parameters.sds1.controller.max_concurrent_dev_spin_up) {
1928 scic->power_control.phys_granted_power++; 1910 ihost->power_control.phys_granted_power++;
1929 scic_sds_phy_consume_power_handler(iphy); 1911 scic_sds_phy_consume_power_handler(iphy);
1930 1912
1931 /* 1913 /*
1932 * stop and start the power_control timer. When the timer fires, the 1914 * stop and start the power_control timer. When the timer fires, the
1933 * no_of_phys_granted_power will be set to 0 1915 * no_of_phys_granted_power will be set to 0
1934 */ 1916 */
1935 if (scic->power_control.timer_started) 1917 if (ihost->power_control.timer_started)
1936 sci_del_timer(&scic->power_control.timer); 1918 sci_del_timer(&ihost->power_control.timer);
1937 1919
1938 sci_mod_timer(&scic->power_control.timer, 1920 sci_mod_timer(&ihost->power_control.timer,
1939 SCIC_SDS_CONTROLLER_POWER_CONTROL_INTERVAL); 1921 SCIC_SDS_CONTROLLER_POWER_CONTROL_INTERVAL);
1940 scic->power_control.timer_started = true; 1922 ihost->power_control.timer_started = true;
1941 1923
1942 } else { 1924 } else {
1943 /* Add the phy in the waiting list */ 1925 /* Add the phy in the waiting list */
1944 scic->power_control.requesters[iphy->phy_index] = iphy; 1926 ihost->power_control.requesters[iphy->phy_index] = iphy;
1945 scic->power_control.phys_waiting++; 1927 ihost->power_control.phys_waiting++;
1946 } 1928 }
1947} 1929}
1948 1930
@@ -1953,16 +1935,16 @@ void scic_sds_controller_power_control_queue_insert(
1953 * 1935 *
1954 */ 1936 */
1955void scic_sds_controller_power_control_queue_remove( 1937void scic_sds_controller_power_control_queue_remove(
1956 struct scic_sds_controller *scic, 1938 struct isci_host *ihost,
1957 struct isci_phy *iphy) 1939 struct isci_phy *iphy)
1958{ 1940{
1959 BUG_ON(iphy == NULL); 1941 BUG_ON(iphy == NULL);
1960 1942
1961 if (scic->power_control.requesters[iphy->phy_index] != NULL) { 1943 if (ihost->power_control.requesters[iphy->phy_index] != NULL) {
1962 scic->power_control.phys_waiting--; 1944 ihost->power_control.phys_waiting--;
1963 } 1945 }
1964 1946
1965 scic->power_control.requesters[iphy->phy_index] = NULL; 1947 ihost->power_control.requesters[iphy->phy_index] = NULL;
1966} 1948}
1967 1949
1968#define AFE_REGISTER_WRITE_DELAY 10 1950#define AFE_REGISTER_WRITE_DELAY 10
@@ -1970,50 +1952,50 @@ void scic_sds_controller_power_control_queue_remove(
1970/* Initialize the AFE for this phy index. We need to read the AFE setup from 1952/* Initialize the AFE for this phy index. We need to read the AFE setup from
1971 * the OEM parameters 1953 * the OEM parameters
1972 */ 1954 */
1973static void scic_sds_controller_afe_initialization(struct scic_sds_controller *scic) 1955static void scic_sds_controller_afe_initialization(struct isci_host *ihost)
1974{ 1956{
1975 const struct scic_sds_oem_params *oem = &scic->oem_parameters.sds1; 1957 const struct scic_sds_oem_params *oem = &ihost->oem_parameters.sds1;
1976 u32 afe_status; 1958 u32 afe_status;
1977 u32 phy_id; 1959 u32 phy_id;
1978 1960
1979 /* Clear DFX Status registers */ 1961 /* Clear DFX Status registers */
1980 writel(0x0081000f, &scic->scu_registers->afe.afe_dfx_master_control0); 1962 writel(0x0081000f, &ihost->scu_registers->afe.afe_dfx_master_control0);
1981 udelay(AFE_REGISTER_WRITE_DELAY); 1963 udelay(AFE_REGISTER_WRITE_DELAY);
1982 1964
1983 if (is_b0()) { 1965 if (is_b0()) {
1984 /* PM Rx Equalization Save, PM SPhy Rx Acknowledgement 1966 /* PM Rx Equalization Save, PM SPhy Rx Acknowledgement
1985 * Timer, PM Stagger Timer */ 1967 * Timer, PM Stagger Timer */
1986 writel(0x0007BFFF, &scic->scu_registers->afe.afe_pmsn_master_control2); 1968 writel(0x0007BFFF, &ihost->scu_registers->afe.afe_pmsn_master_control2);
1987 udelay(AFE_REGISTER_WRITE_DELAY); 1969 udelay(AFE_REGISTER_WRITE_DELAY);
1988 } 1970 }
1989 1971
1990 /* Configure bias currents to normal */ 1972 /* Configure bias currents to normal */
1991 if (is_a0()) 1973 if (is_a0())
1992 writel(0x00005500, &scic->scu_registers->afe.afe_bias_control); 1974 writel(0x00005500, &ihost->scu_registers->afe.afe_bias_control);
1993 else if (is_a2()) 1975 else if (is_a2())
1994 writel(0x00005A00, &scic->scu_registers->afe.afe_bias_control); 1976 writel(0x00005A00, &ihost->scu_registers->afe.afe_bias_control);
1995 else if (is_b0() || is_c0()) 1977 else if (is_b0() || is_c0())
1996 writel(0x00005F00, &scic->scu_registers->afe.afe_bias_control); 1978 writel(0x00005F00, &ihost->scu_registers->afe.afe_bias_control);
1997 1979
1998 udelay(AFE_REGISTER_WRITE_DELAY); 1980 udelay(AFE_REGISTER_WRITE_DELAY);
1999 1981
2000 /* Enable PLL */ 1982 /* Enable PLL */
2001 if (is_b0() || is_c0()) 1983 if (is_b0() || is_c0())
2002 writel(0x80040A08, &scic->scu_registers->afe.afe_pll_control0); 1984 writel(0x80040A08, &ihost->scu_registers->afe.afe_pll_control0);
2003 else 1985 else
2004 writel(0x80040908, &scic->scu_registers->afe.afe_pll_control0); 1986 writel(0x80040908, &ihost->scu_registers->afe.afe_pll_control0);
2005 1987
2006 udelay(AFE_REGISTER_WRITE_DELAY); 1988 udelay(AFE_REGISTER_WRITE_DELAY);
2007 1989
2008 /* Wait for the PLL to lock */ 1990 /* Wait for the PLL to lock */
2009 do { 1991 do {
2010 afe_status = readl(&scic->scu_registers->afe.afe_common_block_status); 1992 afe_status = readl(&ihost->scu_registers->afe.afe_common_block_status);
2011 udelay(AFE_REGISTER_WRITE_DELAY); 1993 udelay(AFE_REGISTER_WRITE_DELAY);
2012 } while ((afe_status & 0x00001000) == 0); 1994 } while ((afe_status & 0x00001000) == 0);
2013 1995
2014 if (is_a0() || is_a2()) { 1996 if (is_a0() || is_a2()) {
2015 /* Shorten SAS SNW lock time (RxLock timer value from 76 us to 50 us) */ 1997 /* Shorten SAS SNW lock time (RxLock timer value from 76 us to 50 us) */
2016 writel(0x7bcc96ad, &scic->scu_registers->afe.afe_pmsn_master_control0); 1998 writel(0x7bcc96ad, &ihost->scu_registers->afe.afe_pmsn_master_control0);
2017 udelay(AFE_REGISTER_WRITE_DELAY); 1999 udelay(AFE_REGISTER_WRITE_DELAY);
2018 } 2000 }
2019 2001
@@ -2022,26 +2004,26 @@ static void scic_sds_controller_afe_initialization(struct scic_sds_controller *s
2022 2004
2023 if (is_b0()) { 2005 if (is_b0()) {
2024 /* Configure transmitter SSC parameters */ 2006 /* Configure transmitter SSC parameters */
2025 writel(0x00030000, &scic->scu_registers->afe.scu_afe_xcvr[phy_id].afe_tx_ssc_control); 2007 writel(0x00030000, &ihost->scu_registers->afe.scu_afe_xcvr[phy_id].afe_tx_ssc_control);
2026 udelay(AFE_REGISTER_WRITE_DELAY); 2008 udelay(AFE_REGISTER_WRITE_DELAY);
2027 } else if (is_c0()) { 2009 } else if (is_c0()) {
2028 /* Configure transmitter SSC parameters */ 2010 /* Configure transmitter SSC parameters */
2029 writel(0x0003000, &scic->scu_registers->afe.scu_afe_xcvr[phy_id].afe_tx_ssc_control); 2011 writel(0x0003000, &ihost->scu_registers->afe.scu_afe_xcvr[phy_id].afe_tx_ssc_control);
2030 udelay(AFE_REGISTER_WRITE_DELAY); 2012 udelay(AFE_REGISTER_WRITE_DELAY);
2031 2013
2032 /* 2014 /*
2033 * All defaults, except the Receive Word Alignament/Comma Detect 2015 * All defaults, except the Receive Word Alignament/Comma Detect
2034 * Enable....(0xe800) */ 2016 * Enable....(0xe800) */
2035 writel(0x00004500, &scic->scu_registers->afe.scu_afe_xcvr[phy_id].afe_xcvr_control0); 2017 writel(0x00004500, &ihost->scu_registers->afe.scu_afe_xcvr[phy_id].afe_xcvr_control0);
2036 udelay(AFE_REGISTER_WRITE_DELAY); 2018 udelay(AFE_REGISTER_WRITE_DELAY);
2037 } else { 2019 } else {
2038 /* 2020 /*
2039 * All defaults, except the Receive Word Alignament/Comma Detect 2021 * All defaults, except the Receive Word Alignament/Comma Detect
2040 * Enable....(0xe800) */ 2022 * Enable....(0xe800) */
2041 writel(0x00004512, &scic->scu_registers->afe.scu_afe_xcvr[phy_id].afe_xcvr_control0); 2023 writel(0x00004512, &ihost->scu_registers->afe.scu_afe_xcvr[phy_id].afe_xcvr_control0);
2042 udelay(AFE_REGISTER_WRITE_DELAY); 2024 udelay(AFE_REGISTER_WRITE_DELAY);
2043 2025
2044 writel(0x0050100F, &scic->scu_registers->afe.scu_afe_xcvr[phy_id].afe_xcvr_control1); 2026 writel(0x0050100F, &ihost->scu_registers->afe.scu_afe_xcvr[phy_id].afe_xcvr_control1);
2045 udelay(AFE_REGISTER_WRITE_DELAY); 2027 udelay(AFE_REGISTER_WRITE_DELAY);
2046 } 2028 }
2047 2029
@@ -2049,106 +2031,105 @@ static void scic_sds_controller_afe_initialization(struct scic_sds_controller *s
2049 * Power up TX and RX out from power down (PWRDNTX and PWRDNRX) 2031 * Power up TX and RX out from power down (PWRDNTX and PWRDNRX)
2050 * & increase TX int & ext bias 20%....(0xe85c) */ 2032 * & increase TX int & ext bias 20%....(0xe85c) */
2051 if (is_a0()) 2033 if (is_a0())
2052 writel(0x000003D4, &scic->scu_registers->afe.scu_afe_xcvr[phy_id].afe_channel_control); 2034 writel(0x000003D4, &ihost->scu_registers->afe.scu_afe_xcvr[phy_id].afe_channel_control);
2053 else if (is_a2()) 2035 else if (is_a2())
2054 writel(0x000003F0, &scic->scu_registers->afe.scu_afe_xcvr[phy_id].afe_channel_control); 2036 writel(0x000003F0, &ihost->scu_registers->afe.scu_afe_xcvr[phy_id].afe_channel_control);
2055 else if (is_b0()) { 2037 else if (is_b0()) {
2056 /* Power down TX and RX (PWRDNTX and PWRDNRX) */ 2038 /* Power down TX and RX (PWRDNTX and PWRDNRX) */
2057 writel(0x000003D7, &scic->scu_registers->afe.scu_afe_xcvr[phy_id].afe_channel_control); 2039 writel(0x000003D7, &ihost->scu_registers->afe.scu_afe_xcvr[phy_id].afe_channel_control);
2058 udelay(AFE_REGISTER_WRITE_DELAY); 2040 udelay(AFE_REGISTER_WRITE_DELAY);
2059 2041
2060 /* 2042 /*
2061 * Power up TX and RX out from power down (PWRDNTX and PWRDNRX) 2043 * Power up TX and RX out from power down (PWRDNTX and PWRDNRX)
2062 * & increase TX int & ext bias 20%....(0xe85c) */ 2044 * & increase TX int & ext bias 20%....(0xe85c) */
2063 writel(0x000003D4, &scic->scu_registers->afe.scu_afe_xcvr[phy_id].afe_channel_control); 2045 writel(0x000003D4, &ihost->scu_registers->afe.scu_afe_xcvr[phy_id].afe_channel_control);
2064 } else { 2046 } else {
2065 writel(0x000001E7, &scic->scu_registers->afe.scu_afe_xcvr[phy_id].afe_channel_control); 2047 writel(0x000001E7, &ihost->scu_registers->afe.scu_afe_xcvr[phy_id].afe_channel_control);
2066 udelay(AFE_REGISTER_WRITE_DELAY); 2048 udelay(AFE_REGISTER_WRITE_DELAY);
2067 2049
2068 /* 2050 /*
2069 * Power up TX and RX out from power down (PWRDNTX and PWRDNRX) 2051 * Power up TX and RX out from power down (PWRDNTX and PWRDNRX)
2070 * & increase TX int & ext bias 20%....(0xe85c) */ 2052 * & increase TX int & ext bias 20%....(0xe85c) */
2071 writel(0x000001E4, &scic->scu_registers->afe.scu_afe_xcvr[phy_id].afe_channel_control); 2053 writel(0x000001E4, &ihost->scu_registers->afe.scu_afe_xcvr[phy_id].afe_channel_control);
2072 } 2054 }
2073 udelay(AFE_REGISTER_WRITE_DELAY); 2055 udelay(AFE_REGISTER_WRITE_DELAY);
2074 2056
2075 if (is_a0() || is_a2()) { 2057 if (is_a0() || is_a2()) {
2076 /* Enable TX equalization (0xe824) */ 2058 /* Enable TX equalization (0xe824) */
2077 writel(0x00040000, &scic->scu_registers->afe.scu_afe_xcvr[phy_id].afe_tx_control); 2059 writel(0x00040000, &ihost->scu_registers->afe.scu_afe_xcvr[phy_id].afe_tx_control);
2078 udelay(AFE_REGISTER_WRITE_DELAY); 2060 udelay(AFE_REGISTER_WRITE_DELAY);
2079 } 2061 }
2080 2062
2081 /* 2063 /*
2082 * RDPI=0x0(RX Power On), RXOOBDETPDNC=0x0, TPD=0x0(TX Power On), 2064 * RDPI=0x0(RX Power On), RXOOBDETPDNC=0x0, TPD=0x0(TX Power On),
2083 * RDD=0x0(RX Detect Enabled) ....(0xe800) */ 2065 * RDD=0x0(RX Detect Enabled) ....(0xe800) */
2084 writel(0x00004100, &scic->scu_registers->afe.scu_afe_xcvr[phy_id].afe_xcvr_control0); 2066 writel(0x00004100, &ihost->scu_registers->afe.scu_afe_xcvr[phy_id].afe_xcvr_control0);
2085 udelay(AFE_REGISTER_WRITE_DELAY); 2067 udelay(AFE_REGISTER_WRITE_DELAY);
2086 2068
2087 /* Leave DFE/FFE on */ 2069 /* Leave DFE/FFE on */
2088 if (is_a0()) 2070 if (is_a0())
2089 writel(0x3F09983F, &scic->scu_registers->afe.scu_afe_xcvr[phy_id].afe_rx_ssc_control0); 2071 writel(0x3F09983F, &ihost->scu_registers->afe.scu_afe_xcvr[phy_id].afe_rx_ssc_control0);
2090 else if (is_a2()) 2072 else if (is_a2())
2091 writel(0x3F11103F, &scic->scu_registers->afe.scu_afe_xcvr[phy_id].afe_rx_ssc_control0); 2073 writel(0x3F11103F, &ihost->scu_registers->afe.scu_afe_xcvr[phy_id].afe_rx_ssc_control0);
2092 else if (is_b0()) { 2074 else if (is_b0()) {
2093 writel(0x3F11103F, &scic->scu_registers->afe.scu_afe_xcvr[phy_id].afe_rx_ssc_control0); 2075 writel(0x3F11103F, &ihost->scu_registers->afe.scu_afe_xcvr[phy_id].afe_rx_ssc_control0);
2094 udelay(AFE_REGISTER_WRITE_DELAY); 2076 udelay(AFE_REGISTER_WRITE_DELAY);
2095 /* Enable TX equalization (0xe824) */ 2077 /* Enable TX equalization (0xe824) */
2096 writel(0x00040000, &scic->scu_registers->afe.scu_afe_xcvr[phy_id].afe_tx_control); 2078 writel(0x00040000, &ihost->scu_registers->afe.scu_afe_xcvr[phy_id].afe_tx_control);
2097 } else { 2079 } else {
2098 writel(0x0140DF0F, &scic->scu_registers->afe.scu_afe_xcvr[phy_id].afe_rx_ssc_control1); 2080 writel(0x0140DF0F, &ihost->scu_registers->afe.scu_afe_xcvr[phy_id].afe_rx_ssc_control1);
2099 udelay(AFE_REGISTER_WRITE_DELAY); 2081 udelay(AFE_REGISTER_WRITE_DELAY);
2100 2082
2101 writel(0x3F6F103F, &scic->scu_registers->afe.scu_afe_xcvr[phy_id].afe_rx_ssc_control0); 2083 writel(0x3F6F103F, &ihost->scu_registers->afe.scu_afe_xcvr[phy_id].afe_rx_ssc_control0);
2102 udelay(AFE_REGISTER_WRITE_DELAY); 2084 udelay(AFE_REGISTER_WRITE_DELAY);
2103 2085
2104 /* Enable TX equalization (0xe824) */ 2086 /* Enable TX equalization (0xe824) */
2105 writel(0x00040000, &scic->scu_registers->afe.scu_afe_xcvr[phy_id].afe_tx_control); 2087 writel(0x00040000, &ihost->scu_registers->afe.scu_afe_xcvr[phy_id].afe_tx_control);
2106 } 2088 }
2107 2089
2108 udelay(AFE_REGISTER_WRITE_DELAY); 2090 udelay(AFE_REGISTER_WRITE_DELAY);
2109 2091
2110 writel(oem_phy->afe_tx_amp_control0, 2092 writel(oem_phy->afe_tx_amp_control0,
2111 &scic->scu_registers->afe.scu_afe_xcvr[phy_id].afe_tx_amp_control0); 2093 &ihost->scu_registers->afe.scu_afe_xcvr[phy_id].afe_tx_amp_control0);
2112 udelay(AFE_REGISTER_WRITE_DELAY); 2094 udelay(AFE_REGISTER_WRITE_DELAY);
2113 2095
2114 writel(oem_phy->afe_tx_amp_control1, 2096 writel(oem_phy->afe_tx_amp_control1,
2115 &scic->scu_registers->afe.scu_afe_xcvr[phy_id].afe_tx_amp_control1); 2097 &ihost->scu_registers->afe.scu_afe_xcvr[phy_id].afe_tx_amp_control1);
2116 udelay(AFE_REGISTER_WRITE_DELAY); 2098 udelay(AFE_REGISTER_WRITE_DELAY);
2117 2099
2118 writel(oem_phy->afe_tx_amp_control2, 2100 writel(oem_phy->afe_tx_amp_control2,
2119 &scic->scu_registers->afe.scu_afe_xcvr[phy_id].afe_tx_amp_control2); 2101 &ihost->scu_registers->afe.scu_afe_xcvr[phy_id].afe_tx_amp_control2);
2120 udelay(AFE_REGISTER_WRITE_DELAY); 2102 udelay(AFE_REGISTER_WRITE_DELAY);
2121 2103
2122 writel(oem_phy->afe_tx_amp_control3, 2104 writel(oem_phy->afe_tx_amp_control3,
2123 &scic->scu_registers->afe.scu_afe_xcvr[phy_id].afe_tx_amp_control3); 2105 &ihost->scu_registers->afe.scu_afe_xcvr[phy_id].afe_tx_amp_control3);
2124 udelay(AFE_REGISTER_WRITE_DELAY); 2106 udelay(AFE_REGISTER_WRITE_DELAY);
2125 } 2107 }
2126 2108
2127 /* Transfer control to the PEs */ 2109 /* Transfer control to the PEs */
2128 writel(0x00010f00, &scic->scu_registers->afe.afe_dfx_master_control0); 2110 writel(0x00010f00, &ihost->scu_registers->afe.afe_dfx_master_control0);
2129 udelay(AFE_REGISTER_WRITE_DELAY); 2111 udelay(AFE_REGISTER_WRITE_DELAY);
2130} 2112}
2131 2113
2132static void scic_sds_controller_initialize_power_control(struct scic_sds_controller *scic) 2114static void scic_sds_controller_initialize_power_control(struct isci_host *ihost)
2133{ 2115{
2134 sci_init_timer(&scic->power_control.timer, power_control_timeout); 2116 sci_init_timer(&ihost->power_control.timer, power_control_timeout);
2135 2117
2136 memset(scic->power_control.requesters, 0, 2118 memset(ihost->power_control.requesters, 0,
2137 sizeof(scic->power_control.requesters)); 2119 sizeof(ihost->power_control.requesters));
2138 2120
2139 scic->power_control.phys_waiting = 0; 2121 ihost->power_control.phys_waiting = 0;
2140 scic->power_control.phys_granted_power = 0; 2122 ihost->power_control.phys_granted_power = 0;
2141} 2123}
2142 2124
2143static enum sci_status scic_controller_initialize(struct scic_sds_controller *scic) 2125static enum sci_status scic_controller_initialize(struct isci_host *ihost)
2144{ 2126{
2145 struct sci_base_state_machine *sm = &scic->sm; 2127 struct sci_base_state_machine *sm = &ihost->sm;
2146 struct isci_host *ihost = scic_to_ihost(scic);
2147 enum sci_status result = SCI_FAILURE; 2128 enum sci_status result = SCI_FAILURE;
2148 unsigned long i, state, val; 2129 unsigned long i, state, val;
2149 2130
2150 if (scic->sm.current_state_id != SCIC_RESET) { 2131 if (ihost->sm.current_state_id != SCIC_RESET) {
2151 dev_warn(scic_to_dev(scic), 2132 dev_warn(&ihost->pdev->dev,
2152 "SCIC Controller initialize operation requested " 2133 "SCIC Controller initialize operation requested "
2153 "in invalid state\n"); 2134 "in invalid state\n");
2154 return SCI_FAILURE_INVALID_STATE; 2135 return SCI_FAILURE_INVALID_STATE;
@@ -2156,23 +2137,23 @@ static enum sci_status scic_controller_initialize(struct scic_sds_controller *sc
2156 2137
2157 sci_change_state(sm, SCIC_INITIALIZING); 2138 sci_change_state(sm, SCIC_INITIALIZING);
2158 2139
2159 sci_init_timer(&scic->phy_timer, phy_startup_timeout); 2140 sci_init_timer(&ihost->phy_timer, phy_startup_timeout);
2160 2141
2161 scic->next_phy_to_start = 0; 2142 ihost->next_phy_to_start = 0;
2162 scic->phy_startup_timer_pending = false; 2143 ihost->phy_startup_timer_pending = false;
2163 2144
2164 scic_sds_controller_initialize_power_control(scic); 2145 scic_sds_controller_initialize_power_control(ihost);
2165 2146
2166 /* 2147 /*
2167 * There is nothing to do here for B0 since we do not have to 2148 * There is nothing to do here for B0 since we do not have to
2168 * program the AFE registers. 2149 * program the AFE registers.
2169 * / @todo The AFE settings are supposed to be correct for the B0 but 2150 * / @todo The AFE settings are supposed to be correct for the B0 but
2170 * / presently they seem to be wrong. */ 2151 * / presently they seem to be wrong. */
2171 scic_sds_controller_afe_initialization(scic); 2152 scic_sds_controller_afe_initialization(ihost);
2172 2153
2173 2154
2174 /* Take the hardware out of reset */ 2155 /* Take the hardware out of reset */
2175 writel(0, &scic->smu_registers->soft_reset_control); 2156 writel(0, &ihost->smu_registers->soft_reset_control);
2176 2157
2177 /* 2158 /*
2178 * / @todo Provide meaningfull error code for hardware failure 2159 * / @todo Provide meaningfull error code for hardware failure
@@ -2182,7 +2163,7 @@ static enum sci_status scic_controller_initialize(struct scic_sds_controller *sc
2182 2163
2183 /* Loop until the hardware reports success */ 2164 /* Loop until the hardware reports success */
2184 udelay(SCU_CONTEXT_RAM_INIT_STALL_TIME); 2165 udelay(SCU_CONTEXT_RAM_INIT_STALL_TIME);
2185 status = readl(&scic->smu_registers->control_status); 2166 status = readl(&ihost->smu_registers->control_status);
2186 2167
2187 if ((status & SCU_RAM_INIT_COMPLETED) == SCU_RAM_INIT_COMPLETED) 2168 if ((status & SCU_RAM_INIT_COMPLETED) == SCU_RAM_INIT_COMPLETED)
2188 break; 2169 break;
@@ -2193,32 +2174,32 @@ static enum sci_status scic_controller_initialize(struct scic_sds_controller *sc
2193 /* 2174 /*
2194 * Determine what are the actaul device capacities that the 2175 * Determine what are the actaul device capacities that the
2195 * hardware will support */ 2176 * hardware will support */
2196 val = readl(&scic->smu_registers->device_context_capacity); 2177 val = readl(&ihost->smu_registers->device_context_capacity);
2197 2178
2198 /* Record the smaller of the two capacity values */ 2179 /* Record the smaller of the two capacity values */
2199 scic->logical_port_entries = min(smu_max_ports(val), SCI_MAX_PORTS); 2180 ihost->logical_port_entries = min(smu_max_ports(val), SCI_MAX_PORTS);
2200 scic->task_context_entries = min(smu_max_task_contexts(val), SCI_MAX_IO_REQUESTS); 2181 ihost->task_context_entries = min(smu_max_task_contexts(val), SCI_MAX_IO_REQUESTS);
2201 scic->remote_node_entries = min(smu_max_rncs(val), SCI_MAX_REMOTE_DEVICES); 2182 ihost->remote_node_entries = min(smu_max_rncs(val), SCI_MAX_REMOTE_DEVICES);
2202 2183
2203 /* 2184 /*
2204 * Make all PEs that are unassigned match up with the 2185 * Make all PEs that are unassigned match up with the
2205 * logical ports 2186 * logical ports
2206 */ 2187 */
2207 for (i = 0; i < scic->logical_port_entries; i++) { 2188 for (i = 0; i < ihost->logical_port_entries; i++) {
2208 struct scu_port_task_scheduler_group_registers __iomem 2189 struct scu_port_task_scheduler_group_registers __iomem
2209 *ptsg = &scic->scu_registers->peg0.ptsg; 2190 *ptsg = &ihost->scu_registers->peg0.ptsg;
2210 2191
2211 writel(i, &ptsg->protocol_engine[i]); 2192 writel(i, &ptsg->protocol_engine[i]);
2212 } 2193 }
2213 2194
2214 /* Initialize hardware PCI Relaxed ordering in DMA engines */ 2195 /* Initialize hardware PCI Relaxed ordering in DMA engines */
2215 val = readl(&scic->scu_registers->sdma.pdma_configuration); 2196 val = readl(&ihost->scu_registers->sdma.pdma_configuration);
2216 val |= SCU_PDMACR_GEN_BIT(PCI_RELAXED_ORDERING_ENABLE); 2197 val |= SCU_PDMACR_GEN_BIT(PCI_RELAXED_ORDERING_ENABLE);
2217 writel(val, &scic->scu_registers->sdma.pdma_configuration); 2198 writel(val, &ihost->scu_registers->sdma.pdma_configuration);
2218 2199
2219 val = readl(&scic->scu_registers->sdma.cdma_configuration); 2200 val = readl(&ihost->scu_registers->sdma.cdma_configuration);
2220 val |= SCU_CDMACR_GEN_BIT(PCI_RELAXED_ORDERING_ENABLE); 2201 val |= SCU_CDMACR_GEN_BIT(PCI_RELAXED_ORDERING_ENABLE);
2221 writel(val, &scic->scu_registers->sdma.cdma_configuration); 2202 writel(val, &ihost->scu_registers->sdma.cdma_configuration);
2222 2203
2223 /* 2204 /*
2224 * Initialize the PHYs before the PORTs because the PHY registers 2205 * Initialize the PHYs before the PORTs because the PHY registers
@@ -2226,23 +2207,23 @@ static enum sci_status scic_controller_initialize(struct scic_sds_controller *sc
2226 */ 2207 */
2227 for (i = 0; i < SCI_MAX_PHYS; i++) { 2208 for (i = 0; i < SCI_MAX_PHYS; i++) {
2228 result = scic_sds_phy_initialize(&ihost->phys[i], 2209 result = scic_sds_phy_initialize(&ihost->phys[i],
2229 &scic->scu_registers->peg0.pe[i].tl, 2210 &ihost->scu_registers->peg0.pe[i].tl,
2230 &scic->scu_registers->peg0.pe[i].ll); 2211 &ihost->scu_registers->peg0.pe[i].ll);
2231 if (result != SCI_SUCCESS) 2212 if (result != SCI_SUCCESS)
2232 goto out; 2213 goto out;
2233 } 2214 }
2234 2215
2235 for (i = 0; i < scic->logical_port_entries; i++) { 2216 for (i = 0; i < ihost->logical_port_entries; i++) {
2236 result = scic_sds_port_initialize(&ihost->ports[i], 2217 result = scic_sds_port_initialize(&ihost->ports[i],
2237 &scic->scu_registers->peg0.ptsg.port[i], 2218 &ihost->scu_registers->peg0.ptsg.port[i],
2238 &scic->scu_registers->peg0.ptsg.protocol_engine, 2219 &ihost->scu_registers->peg0.ptsg.protocol_engine,
2239 &scic->scu_registers->peg0.viit[i]); 2220 &ihost->scu_registers->peg0.viit[i]);
2240 2221
2241 if (result != SCI_SUCCESS) 2222 if (result != SCI_SUCCESS)
2242 goto out; 2223 goto out;
2243 } 2224 }
2244 2225
2245 result = scic_sds_port_configuration_agent_initialize(scic, &scic->port_agent); 2226 result = scic_sds_port_configuration_agent_initialize(ihost, &ihost->port_agent);
2246 2227
2247 out: 2228 out:
2248 /* Advance the controller state machine */ 2229 /* Advance the controller state machine */
@@ -2256,10 +2237,10 @@ static enum sci_status scic_controller_initialize(struct scic_sds_controller *sc
2256} 2237}
2257 2238
2258static enum sci_status scic_user_parameters_set( 2239static enum sci_status scic_user_parameters_set(
2259 struct scic_sds_controller *scic, 2240 struct isci_host *ihost,
2260 union scic_user_parameters *scic_parms) 2241 union scic_user_parameters *scic_parms)
2261{ 2242{
2262 u32 state = scic->sm.current_state_id; 2243 u32 state = ihost->sm.current_state_id;
2263 2244
2264 if (state == SCIC_RESET || 2245 if (state == SCIC_RESET ||
2265 state == SCIC_INITIALIZING || 2246 state == SCIC_INITIALIZING ||
@@ -2301,7 +2282,7 @@ static enum sci_status scic_user_parameters_set(
2301 (scic_parms->sds1.no_outbound_task_timeout == 0)) 2282 (scic_parms->sds1.no_outbound_task_timeout == 0))
2302 return SCI_FAILURE_INVALID_PARAMETER_VALUE; 2283 return SCI_FAILURE_INVALID_PARAMETER_VALUE;
2303 2284
2304 memcpy(&scic->user_parameters, scic_parms, sizeof(*scic_parms)); 2285 memcpy(&ihost->user_parameters, scic_parms, sizeof(*scic_parms));
2305 2286
2306 return SCI_SUCCESS; 2287 return SCI_SUCCESS;
2307 } 2288 }
@@ -2309,40 +2290,40 @@ static enum sci_status scic_user_parameters_set(
2309 return SCI_FAILURE_INVALID_STATE; 2290 return SCI_FAILURE_INVALID_STATE;
2310} 2291}
2311 2292
2312static int scic_controller_mem_init(struct scic_sds_controller *scic) 2293static int scic_controller_mem_init(struct isci_host *ihost)
2313{ 2294{
2314 struct device *dev = scic_to_dev(scic); 2295 struct device *dev = &ihost->pdev->dev;
2315 dma_addr_t dma; 2296 dma_addr_t dma;
2316 size_t size; 2297 size_t size;
2317 int err; 2298 int err;
2318 2299
2319 size = SCU_MAX_COMPLETION_QUEUE_ENTRIES * sizeof(u32); 2300 size = SCU_MAX_COMPLETION_QUEUE_ENTRIES * sizeof(u32);
2320 scic->completion_queue = dmam_alloc_coherent(dev, size, &dma, GFP_KERNEL); 2301 ihost->completion_queue = dmam_alloc_coherent(dev, size, &dma, GFP_KERNEL);
2321 if (!scic->completion_queue) 2302 if (!ihost->completion_queue)
2322 return -ENOMEM; 2303 return -ENOMEM;
2323 2304
2324 writel(lower_32_bits(dma), &scic->smu_registers->completion_queue_lower); 2305 writel(lower_32_bits(dma), &ihost->smu_registers->completion_queue_lower);
2325 writel(upper_32_bits(dma), &scic->smu_registers->completion_queue_upper); 2306 writel(upper_32_bits(dma), &ihost->smu_registers->completion_queue_upper);
2326 2307
2327 size = scic->remote_node_entries * sizeof(union scu_remote_node_context); 2308 size = ihost->remote_node_entries * sizeof(union scu_remote_node_context);
2328 scic->remote_node_context_table = dmam_alloc_coherent(dev, size, &dma, 2309 ihost->remote_node_context_table = dmam_alloc_coherent(dev, size, &dma,
2329 GFP_KERNEL); 2310 GFP_KERNEL);
2330 if (!scic->remote_node_context_table) 2311 if (!ihost->remote_node_context_table)
2331 return -ENOMEM; 2312 return -ENOMEM;
2332 2313
2333 writel(lower_32_bits(dma), &scic->smu_registers->remote_node_context_lower); 2314 writel(lower_32_bits(dma), &ihost->smu_registers->remote_node_context_lower);
2334 writel(upper_32_bits(dma), &scic->smu_registers->remote_node_context_upper); 2315 writel(upper_32_bits(dma), &ihost->smu_registers->remote_node_context_upper);
2335 2316
2336 size = scic->task_context_entries * sizeof(struct scu_task_context), 2317 size = ihost->task_context_entries * sizeof(struct scu_task_context),
2337 scic->task_context_table = dmam_alloc_coherent(dev, size, &dma, GFP_KERNEL); 2318 ihost->task_context_table = dmam_alloc_coherent(dev, size, &dma, GFP_KERNEL);
2338 if (!scic->task_context_table) 2319 if (!ihost->task_context_table)
2339 return -ENOMEM; 2320 return -ENOMEM;
2340 2321
2341 scic->task_context_dma = dma; 2322 ihost->task_context_dma = dma;
2342 writel(lower_32_bits(dma), &scic->smu_registers->host_task_table_lower); 2323 writel(lower_32_bits(dma), &ihost->smu_registers->host_task_table_lower);
2343 writel(upper_32_bits(dma), &scic->smu_registers->host_task_table_upper); 2324 writel(upper_32_bits(dma), &ihost->smu_registers->host_task_table_upper);
2344 2325
2345 err = scic_sds_unsolicited_frame_control_construct(scic); 2326 err = scic_sds_unsolicited_frame_control_construct(ihost);
2346 if (err) 2327 if (err)
2347 return err; 2328 return err;
2348 2329
@@ -2350,112 +2331,112 @@ static int scic_controller_mem_init(struct scic_sds_controller *scic)
2350 * Inform the silicon as to the location of the UF headers and 2331 * Inform the silicon as to the location of the UF headers and
2351 * address table. 2332 * address table.
2352 */ 2333 */
2353 writel(lower_32_bits(scic->uf_control.headers.physical_address), 2334 writel(lower_32_bits(ihost->uf_control.headers.physical_address),
2354 &scic->scu_registers->sdma.uf_header_base_address_lower); 2335 &ihost->scu_registers->sdma.uf_header_base_address_lower);
2355 writel(upper_32_bits(scic->uf_control.headers.physical_address), 2336 writel(upper_32_bits(ihost->uf_control.headers.physical_address),
2356 &scic->scu_registers->sdma.uf_header_base_address_upper); 2337 &ihost->scu_registers->sdma.uf_header_base_address_upper);
2357 2338
2358 writel(lower_32_bits(scic->uf_control.address_table.physical_address), 2339 writel(lower_32_bits(ihost->uf_control.address_table.physical_address),
2359 &scic->scu_registers->sdma.uf_address_table_lower); 2340 &ihost->scu_registers->sdma.uf_address_table_lower);
2360 writel(upper_32_bits(scic->uf_control.address_table.physical_address), 2341 writel(upper_32_bits(ihost->uf_control.address_table.physical_address),
2361 &scic->scu_registers->sdma.uf_address_table_upper); 2342 &ihost->scu_registers->sdma.uf_address_table_upper);
2362 2343
2363 return 0; 2344 return 0;
2364} 2345}
2365 2346
2366int isci_host_init(struct isci_host *isci_host) 2347int isci_host_init(struct isci_host *ihost)
2367{ 2348{
2368 int err = 0, i; 2349 int err = 0, i;
2369 enum sci_status status; 2350 enum sci_status status;
2370 union scic_oem_parameters oem; 2351 union scic_oem_parameters oem;
2371 union scic_user_parameters scic_user_params; 2352 union scic_user_parameters scic_user_params;
2372 struct isci_pci_info *pci_info = to_pci_info(isci_host->pdev); 2353 struct isci_pci_info *pci_info = to_pci_info(ihost->pdev);
2373 2354
2374 spin_lock_init(&isci_host->state_lock); 2355 spin_lock_init(&ihost->state_lock);
2375 spin_lock_init(&isci_host->scic_lock); 2356 spin_lock_init(&ihost->scic_lock);
2376 init_waitqueue_head(&isci_host->eventq); 2357 init_waitqueue_head(&ihost->eventq);
2377 2358
2378 isci_host_change_state(isci_host, isci_starting); 2359 isci_host_change_state(ihost, isci_starting);
2379 2360
2380 status = scic_controller_construct(&isci_host->sci, scu_base(isci_host), 2361 status = scic_controller_construct(ihost, scu_base(ihost),
2381 smu_base(isci_host)); 2362 smu_base(ihost));
2382 2363
2383 if (status != SCI_SUCCESS) { 2364 if (status != SCI_SUCCESS) {
2384 dev_err(&isci_host->pdev->dev, 2365 dev_err(&ihost->pdev->dev,
2385 "%s: scic_controller_construct failed - status = %x\n", 2366 "%s: scic_controller_construct failed - status = %x\n",
2386 __func__, 2367 __func__,
2387 status); 2368 status);
2388 return -ENODEV; 2369 return -ENODEV;
2389 } 2370 }
2390 2371
2391 isci_host->sas_ha.dev = &isci_host->pdev->dev; 2372 ihost->sas_ha.dev = &ihost->pdev->dev;
2392 isci_host->sas_ha.lldd_ha = isci_host; 2373 ihost->sas_ha.lldd_ha = ihost;
2393 2374
2394 /* 2375 /*
2395 * grab initial values stored in the controller object for OEM and USER 2376 * grab initial values stored in the controller object for OEM and USER
2396 * parameters 2377 * parameters
2397 */ 2378 */
2398 isci_user_parameters_get(isci_host, &scic_user_params); 2379 isci_user_parameters_get(ihost, &scic_user_params);
2399 status = scic_user_parameters_set(&isci_host->sci, 2380 status = scic_user_parameters_set(ihost,
2400 &scic_user_params); 2381 &scic_user_params);
2401 if (status != SCI_SUCCESS) { 2382 if (status != SCI_SUCCESS) {
2402 dev_warn(&isci_host->pdev->dev, 2383 dev_warn(&ihost->pdev->dev,
2403 "%s: scic_user_parameters_set failed\n", 2384 "%s: scic_user_parameters_set failed\n",
2404 __func__); 2385 __func__);
2405 return -ENODEV; 2386 return -ENODEV;
2406 } 2387 }
2407 2388
2408 scic_oem_parameters_get(&isci_host->sci, &oem); 2389 scic_oem_parameters_get(ihost, &oem);
2409 2390
2410 /* grab any OEM parameters specified in orom */ 2391 /* grab any OEM parameters specified in orom */
2411 if (pci_info->orom) { 2392 if (pci_info->orom) {
2412 status = isci_parse_oem_parameters(&oem, 2393 status = isci_parse_oem_parameters(&oem,
2413 pci_info->orom, 2394 pci_info->orom,
2414 isci_host->id); 2395 ihost->id);
2415 if (status != SCI_SUCCESS) { 2396 if (status != SCI_SUCCESS) {
2416 dev_warn(&isci_host->pdev->dev, 2397 dev_warn(&ihost->pdev->dev,
2417 "parsing firmware oem parameters failed\n"); 2398 "parsing firmware oem parameters failed\n");
2418 return -EINVAL; 2399 return -EINVAL;
2419 } 2400 }
2420 } 2401 }
2421 2402
2422 status = scic_oem_parameters_set(&isci_host->sci, &oem); 2403 status = scic_oem_parameters_set(ihost, &oem);
2423 if (status != SCI_SUCCESS) { 2404 if (status != SCI_SUCCESS) {
2424 dev_warn(&isci_host->pdev->dev, 2405 dev_warn(&ihost->pdev->dev,
2425 "%s: scic_oem_parameters_set failed\n", 2406 "%s: scic_oem_parameters_set failed\n",
2426 __func__); 2407 __func__);
2427 return -ENODEV; 2408 return -ENODEV;
2428 } 2409 }
2429 2410
2430 tasklet_init(&isci_host->completion_tasklet, 2411 tasklet_init(&ihost->completion_tasklet,
2431 isci_host_completion_routine, (unsigned long)isci_host); 2412 isci_host_completion_routine, (unsigned long)ihost);
2432 2413
2433 INIT_LIST_HEAD(&isci_host->requests_to_complete); 2414 INIT_LIST_HEAD(&ihost->requests_to_complete);
2434 INIT_LIST_HEAD(&isci_host->requests_to_errorback); 2415 INIT_LIST_HEAD(&ihost->requests_to_errorback);
2435 2416
2436 spin_lock_irq(&isci_host->scic_lock); 2417 spin_lock_irq(&ihost->scic_lock);
2437 status = scic_controller_initialize(&isci_host->sci); 2418 status = scic_controller_initialize(ihost);
2438 spin_unlock_irq(&isci_host->scic_lock); 2419 spin_unlock_irq(&ihost->scic_lock);
2439 if (status != SCI_SUCCESS) { 2420 if (status != SCI_SUCCESS) {
2440 dev_warn(&isci_host->pdev->dev, 2421 dev_warn(&ihost->pdev->dev,
2441 "%s: scic_controller_initialize failed -" 2422 "%s: scic_controller_initialize failed -"
2442 " status = 0x%x\n", 2423 " status = 0x%x\n",
2443 __func__, status); 2424 __func__, status);
2444 return -ENODEV; 2425 return -ENODEV;
2445 } 2426 }
2446 2427
2447 err = scic_controller_mem_init(&isci_host->sci); 2428 err = scic_controller_mem_init(ihost);
2448 if (err) 2429 if (err)
2449 return err; 2430 return err;
2450 2431
2451 for (i = 0; i < SCI_MAX_PORTS; i++) 2432 for (i = 0; i < SCI_MAX_PORTS; i++)
2452 isci_port_init(&isci_host->ports[i], isci_host, i); 2433 isci_port_init(&ihost->ports[i], ihost, i);
2453 2434
2454 for (i = 0; i < SCI_MAX_PHYS; i++) 2435 for (i = 0; i < SCI_MAX_PHYS; i++)
2455 isci_phy_init(&isci_host->phys[i], isci_host, i); 2436 isci_phy_init(&ihost->phys[i], ihost, i);
2456 2437
2457 for (i = 0; i < SCI_MAX_REMOTE_DEVICES; i++) { 2438 for (i = 0; i < SCI_MAX_REMOTE_DEVICES; i++) {
2458 struct isci_remote_device *idev = &isci_host->devices[i]; 2439 struct isci_remote_device *idev = &ihost->devices[i];
2459 2440
2460 INIT_LIST_HEAD(&idev->reqs_in_process); 2441 INIT_LIST_HEAD(&idev->reqs_in_process);
2461 INIT_LIST_HEAD(&idev->node); 2442 INIT_LIST_HEAD(&idev->node);
@@ -2465,63 +2446,62 @@ int isci_host_init(struct isci_host *isci_host)
2465 struct isci_request *ireq; 2446 struct isci_request *ireq;
2466 dma_addr_t dma; 2447 dma_addr_t dma;
2467 2448
2468 ireq = dmam_alloc_coherent(&isci_host->pdev->dev, 2449 ireq = dmam_alloc_coherent(&ihost->pdev->dev,
2469 sizeof(struct isci_request), &dma, 2450 sizeof(struct isci_request), &dma,
2470 GFP_KERNEL); 2451 GFP_KERNEL);
2471 if (!ireq) 2452 if (!ireq)
2472 return -ENOMEM; 2453 return -ENOMEM;
2473 2454
2474 ireq->tc = &isci_host->sci.task_context_table[i]; 2455 ireq->tc = &ihost->task_context_table[i];
2475 ireq->owning_controller = &isci_host->sci; 2456 ireq->owning_controller = ihost;
2476 spin_lock_init(&ireq->state_lock); 2457 spin_lock_init(&ireq->state_lock);
2477 ireq->request_daddr = dma; 2458 ireq->request_daddr = dma;
2478 ireq->isci_host = isci_host; 2459 ireq->isci_host = ihost;
2479 2460 ihost->reqs[i] = ireq;
2480 isci_host->reqs[i] = ireq;
2481 } 2461 }
2482 2462
2483 return 0; 2463 return 0;
2484} 2464}
2485 2465
2486void scic_sds_controller_link_up(struct scic_sds_controller *scic, 2466void scic_sds_controller_link_up(struct isci_host *ihost,
2487 struct isci_port *iport, struct isci_phy *iphy) 2467 struct isci_port *iport, struct isci_phy *iphy)
2488{ 2468{
2489 switch (scic->sm.current_state_id) { 2469 switch (ihost->sm.current_state_id) {
2490 case SCIC_STARTING: 2470 case SCIC_STARTING:
2491 sci_del_timer(&scic->phy_timer); 2471 sci_del_timer(&ihost->phy_timer);
2492 scic->phy_startup_timer_pending = false; 2472 ihost->phy_startup_timer_pending = false;
2493 scic->port_agent.link_up_handler(scic, &scic->port_agent, 2473 ihost->port_agent.link_up_handler(ihost, &ihost->port_agent,
2494 iport, iphy); 2474 iport, iphy);
2495 scic_sds_controller_start_next_phy(scic); 2475 scic_sds_controller_start_next_phy(ihost);
2496 break; 2476 break;
2497 case SCIC_READY: 2477 case SCIC_READY:
2498 scic->port_agent.link_up_handler(scic, &scic->port_agent, 2478 ihost->port_agent.link_up_handler(ihost, &ihost->port_agent,
2499 iport, iphy); 2479 iport, iphy);
2500 break; 2480 break;
2501 default: 2481 default:
2502 dev_dbg(scic_to_dev(scic), 2482 dev_dbg(&ihost->pdev->dev,
2503 "%s: SCIC Controller linkup event from phy %d in " 2483 "%s: SCIC Controller linkup event from phy %d in "
2504 "unexpected state %d\n", __func__, iphy->phy_index, 2484 "unexpected state %d\n", __func__, iphy->phy_index,
2505 scic->sm.current_state_id); 2485 ihost->sm.current_state_id);
2506 } 2486 }
2507} 2487}
2508 2488
2509void scic_sds_controller_link_down(struct scic_sds_controller *scic, 2489void scic_sds_controller_link_down(struct isci_host *ihost,
2510 struct isci_port *iport, struct isci_phy *iphy) 2490 struct isci_port *iport, struct isci_phy *iphy)
2511{ 2491{
2512 switch (scic->sm.current_state_id) { 2492 switch (ihost->sm.current_state_id) {
2513 case SCIC_STARTING: 2493 case SCIC_STARTING:
2514 case SCIC_READY: 2494 case SCIC_READY:
2515 scic->port_agent.link_down_handler(scic, &scic->port_agent, 2495 ihost->port_agent.link_down_handler(ihost, &ihost->port_agent,
2516 iport, iphy); 2496 iport, iphy);
2517 break; 2497 break;
2518 default: 2498 default:
2519 dev_dbg(scic_to_dev(scic), 2499 dev_dbg(&ihost->pdev->dev,
2520 "%s: SCIC Controller linkdown event from phy %d in " 2500 "%s: SCIC Controller linkdown event from phy %d in "
2521 "unexpected state %d\n", 2501 "unexpected state %d\n",
2522 __func__, 2502 __func__,
2523 iphy->phy_index, 2503 iphy->phy_index,
2524 scic->sm.current_state_id); 2504 ihost->sm.current_state_id);
2525 } 2505 }
2526} 2506}
2527 2507
@@ -2530,14 +2510,13 @@ void scic_sds_controller_link_down(struct scic_sds_controller *scic,
2530 * controller are still in the stopping state. 2510 * controller are still in the stopping state.
2531 * 2511 *
2532 */ 2512 */
2533static bool scic_sds_controller_has_remote_devices_stopping( 2513static bool scic_sds_controller_has_remote_devices_stopping(struct isci_host *ihost)
2534 struct scic_sds_controller *controller)
2535{ 2514{
2536 u32 index; 2515 u32 index;
2537 2516
2538 for (index = 0; index < controller->remote_node_entries; index++) { 2517 for (index = 0; index < ihost->remote_node_entries; index++) {
2539 if ((controller->device_table[index] != NULL) && 2518 if ((ihost->device_table[index] != NULL) &&
2540 (controller->device_table[index]->sm.current_state_id == SCI_DEV_STOPPING)) 2519 (ihost->device_table[index]->sm.current_state_id == SCI_DEV_STOPPING))
2541 return true; 2520 return true;
2542 } 2521 }
2543 2522
@@ -2548,20 +2527,20 @@ static bool scic_sds_controller_has_remote_devices_stopping(
2548 * This method is called by the remote device to inform the controller 2527 * This method is called by the remote device to inform the controller
2549 * object that the remote device has stopped. 2528 * object that the remote device has stopped.
2550 */ 2529 */
2551void scic_sds_controller_remote_device_stopped(struct scic_sds_controller *scic, 2530void scic_sds_controller_remote_device_stopped(struct isci_host *ihost,
2552 struct isci_remote_device *idev) 2531 struct isci_remote_device *idev)
2553{ 2532{
2554 if (scic->sm.current_state_id != SCIC_STOPPING) { 2533 if (ihost->sm.current_state_id != SCIC_STOPPING) {
2555 dev_dbg(scic_to_dev(scic), 2534 dev_dbg(&ihost->pdev->dev,
2556 "SCIC Controller 0x%p remote device stopped event " 2535 "SCIC Controller 0x%p remote device stopped event "
2557 "from device 0x%p in unexpected state %d\n", 2536 "from device 0x%p in unexpected state %d\n",
2558 scic, idev, 2537 ihost, idev,
2559 scic->sm.current_state_id); 2538 ihost->sm.current_state_id);
2560 return; 2539 return;
2561 } 2540 }
2562 2541
2563 if (!scic_sds_controller_has_remote_devices_stopping(scic)) { 2542 if (!scic_sds_controller_has_remote_devices_stopping(ihost)) {
2564 sci_change_state(&scic->sm, SCIC_STOPPED); 2543 sci_change_state(&ihost->sm, SCIC_STOPPED);
2565 } 2544 }
2566} 2545}
2567 2546
@@ -2573,32 +2552,32 @@ void scic_sds_controller_remote_device_stopped(struct scic_sds_controller *scic,
2573 * 2552 *
2574 */ 2553 */
2575void scic_sds_controller_post_request( 2554void scic_sds_controller_post_request(
2576 struct scic_sds_controller *scic, 2555 struct isci_host *ihost,
2577 u32 request) 2556 u32 request)
2578{ 2557{
2579 dev_dbg(scic_to_dev(scic), 2558 dev_dbg(&ihost->pdev->dev,
2580 "%s: SCIC Controller 0x%p post request 0x%08x\n", 2559 "%s: SCIC Controller 0x%p post request 0x%08x\n",
2581 __func__, 2560 __func__,
2582 scic, 2561 ihost,
2583 request); 2562 request);
2584 2563
2585 writel(request, &scic->smu_registers->post_context_port); 2564 writel(request, &ihost->smu_registers->post_context_port);
2586} 2565}
2587 2566
2588struct isci_request *scic_request_by_tag(struct scic_sds_controller *scic, u16 io_tag) 2567struct isci_request *scic_request_by_tag(struct isci_host *ihost, u16 io_tag)
2589{ 2568{
2590 u16 task_index; 2569 u16 task_index;
2591 u16 task_sequence; 2570 u16 task_sequence;
2592 2571
2593 task_index = ISCI_TAG_TCI(io_tag); 2572 task_index = ISCI_TAG_TCI(io_tag);
2594 2573
2595 if (task_index < scic->task_context_entries) { 2574 if (task_index < ihost->task_context_entries) {
2596 struct isci_request *ireq = scic_to_ihost(scic)->reqs[task_index]; 2575 struct isci_request *ireq = ihost->reqs[task_index];
2597 2576
2598 if (test_bit(IREQ_ACTIVE, &ireq->flags)) { 2577 if (test_bit(IREQ_ACTIVE, &ireq->flags)) {
2599 task_sequence = ISCI_TAG_SEQ(io_tag); 2578 task_sequence = ISCI_TAG_SEQ(io_tag);
2600 2579
2601 if (task_sequence == scic->io_request_sequence[task_index]) 2580 if (task_sequence == ihost->io_request_sequence[task_index])
2602 return ireq; 2581 return ireq;
2603 } 2582 }
2604 } 2583 }
@@ -2621,7 +2600,7 @@ struct isci_request *scic_request_by_tag(struct scic_sds_controller *scic, u16 i
2621 * node index available. 2600 * node index available.
2622 */ 2601 */
2623enum sci_status scic_sds_controller_allocate_remote_node_context( 2602enum sci_status scic_sds_controller_allocate_remote_node_context(
2624 struct scic_sds_controller *scic, 2603 struct isci_host *ihost,
2625 struct isci_remote_device *idev, 2604 struct isci_remote_device *idev,
2626 u16 *node_id) 2605 u16 *node_id)
2627{ 2606{
@@ -2629,11 +2608,11 @@ enum sci_status scic_sds_controller_allocate_remote_node_context(
2629 u32 remote_node_count = scic_sds_remote_device_node_count(idev); 2608 u32 remote_node_count = scic_sds_remote_device_node_count(idev);
2630 2609
2631 node_index = scic_sds_remote_node_table_allocate_remote_node( 2610 node_index = scic_sds_remote_node_table_allocate_remote_node(
2632 &scic->available_remote_nodes, remote_node_count 2611 &ihost->available_remote_nodes, remote_node_count
2633 ); 2612 );
2634 2613
2635 if (node_index != SCIC_SDS_REMOTE_NODE_CONTEXT_INVALID_INDEX) { 2614 if (node_index != SCIC_SDS_REMOTE_NODE_CONTEXT_INVALID_INDEX) {
2636 scic->device_table[node_index] = idev; 2615 ihost->device_table[node_index] = idev;
2637 2616
2638 *node_id = node_index; 2617 *node_id = node_index;
2639 2618
@@ -2653,17 +2632,17 @@ enum sci_status scic_sds_controller_allocate_remote_node_context(
2653 * 2632 *
2654 */ 2633 */
2655void scic_sds_controller_free_remote_node_context( 2634void scic_sds_controller_free_remote_node_context(
2656 struct scic_sds_controller *scic, 2635 struct isci_host *ihost,
2657 struct isci_remote_device *idev, 2636 struct isci_remote_device *idev,
2658 u16 node_id) 2637 u16 node_id)
2659{ 2638{
2660 u32 remote_node_count = scic_sds_remote_device_node_count(idev); 2639 u32 remote_node_count = scic_sds_remote_device_node_count(idev);
2661 2640
2662 if (scic->device_table[node_id] == idev) { 2641 if (ihost->device_table[node_id] == idev) {
2663 scic->device_table[node_id] = NULL; 2642 ihost->device_table[node_id] = NULL;
2664 2643
2665 scic_sds_remote_node_table_release_remote_node_index( 2644 scic_sds_remote_node_table_release_remote_node_index(
2666 &scic->available_remote_nodes, remote_node_count, node_id 2645 &ihost->available_remote_nodes, remote_node_count, node_id
2667 ); 2646 );
2668 } 2647 }
2669} 2648}
@@ -2677,14 +2656,14 @@ void scic_sds_controller_free_remote_node_context(
2677 * union scu_remote_node_context* 2656 * union scu_remote_node_context*
2678 */ 2657 */
2679union scu_remote_node_context *scic_sds_controller_get_remote_node_context_buffer( 2658union scu_remote_node_context *scic_sds_controller_get_remote_node_context_buffer(
2680 struct scic_sds_controller *scic, 2659 struct isci_host *ihost,
2681 u16 node_id 2660 u16 node_id
2682 ) { 2661 ) {
2683 if ( 2662 if (
2684 (node_id < scic->remote_node_entries) 2663 (node_id < ihost->remote_node_entries)
2685 && (scic->device_table[node_id] != NULL) 2664 && (ihost->device_table[node_id] != NULL)
2686 ) { 2665 ) {
2687 return &scic->remote_node_context_table[node_id]; 2666 return &ihost->remote_node_context_table[node_id];
2688 } 2667 }
2689 2668
2690 return NULL; 2669 return NULL;
@@ -2722,13 +2701,13 @@ void scic_sds_controller_copy_sata_response(
2722 * 2701 *
2723 */ 2702 */
2724void scic_sds_controller_release_frame( 2703void scic_sds_controller_release_frame(
2725 struct scic_sds_controller *scic, 2704 struct isci_host *ihost,
2726 u32 frame_index) 2705 u32 frame_index)
2727{ 2706{
2728 if (scic_sds_unsolicited_frame_control_release_frame( 2707 if (scic_sds_unsolicited_frame_control_release_frame(
2729 &scic->uf_control, frame_index) == true) 2708 &ihost->uf_control, frame_index) == true)
2730 writel(scic->uf_control.get, 2709 writel(ihost->uf_control.get,
2731 &scic->scu_registers->sdma.unsolicited_frame_get_pointer); 2710 &ihost->scu_registers->sdma.unsolicited_frame_get_pointer);
2732} 2711}
2733 2712
2734void isci_tci_free(struct isci_host *ihost, u16 tci) 2713void isci_tci_free(struct isci_host *ihost, u16 tci)
@@ -2757,7 +2736,7 @@ u16 isci_alloc_tag(struct isci_host *ihost)
2757{ 2736{
2758 if (isci_tci_space(ihost)) { 2737 if (isci_tci_space(ihost)) {
2759 u16 tci = isci_tci_alloc(ihost); 2738 u16 tci = isci_tci_alloc(ihost);
2760 u8 seq = ihost->sci.io_request_sequence[tci]; 2739 u8 seq = ihost->io_request_sequence[tci];
2761 2740
2762 return ISCI_TAG(seq, tci); 2741 return ISCI_TAG(seq, tci);
2763 } 2742 }
@@ -2767,7 +2746,6 @@ u16 isci_alloc_tag(struct isci_host *ihost)
2767 2746
2768enum sci_status isci_free_tag(struct isci_host *ihost, u16 io_tag) 2747enum sci_status isci_free_tag(struct isci_host *ihost, u16 io_tag)
2769{ 2748{
2770 struct scic_sds_controller *scic = &ihost->sci;
2771 u16 tci = ISCI_TAG_TCI(io_tag); 2749 u16 tci = ISCI_TAG_TCI(io_tag);
2772 u16 seq = ISCI_TAG_SEQ(io_tag); 2750 u16 seq = ISCI_TAG_SEQ(io_tag);
2773 2751
@@ -2775,8 +2753,8 @@ enum sci_status isci_free_tag(struct isci_host *ihost, u16 io_tag)
2775 if (isci_tci_active(ihost) == 0) 2753 if (isci_tci_active(ihost) == 0)
2776 return SCI_FAILURE_INVALID_IO_TAG; 2754 return SCI_FAILURE_INVALID_IO_TAG;
2777 2755
2778 if (seq == scic->io_request_sequence[tci]) { 2756 if (seq == ihost->io_request_sequence[tci]) {
2779 scic->io_request_sequence[tci] = (seq+1) & (SCI_MAX_SEQ-1); 2757 ihost->io_request_sequence[tci] = (seq+1) & (SCI_MAX_SEQ-1);
2780 2758
2781 isci_tci_free(ihost, tci); 2759 isci_tci_free(ihost, tci);
2782 2760
@@ -2797,23 +2775,23 @@ enum sci_status isci_free_tag(struct isci_host *ihost, u16 io_tag)
2797 * @io_tag: This parameter specifies a previously allocated IO tag that the 2775 * @io_tag: This parameter specifies a previously allocated IO tag that the
2798 * user desires to be utilized for this request. 2776 * user desires to be utilized for this request.
2799 */ 2777 */
2800enum sci_status scic_controller_start_io(struct scic_sds_controller *scic, 2778enum sci_status scic_controller_start_io(struct isci_host *ihost,
2801 struct isci_remote_device *idev, 2779 struct isci_remote_device *idev,
2802 struct isci_request *ireq) 2780 struct isci_request *ireq)
2803{ 2781{
2804 enum sci_status status; 2782 enum sci_status status;
2805 2783
2806 if (scic->sm.current_state_id != SCIC_READY) { 2784 if (ihost->sm.current_state_id != SCIC_READY) {
2807 dev_warn(scic_to_dev(scic), "invalid state to start I/O"); 2785 dev_warn(&ihost->pdev->dev, "invalid state to start I/O");
2808 return SCI_FAILURE_INVALID_STATE; 2786 return SCI_FAILURE_INVALID_STATE;
2809 } 2787 }
2810 2788
2811 status = scic_sds_remote_device_start_io(scic, idev, ireq); 2789 status = scic_sds_remote_device_start_io(ihost, idev, ireq);
2812 if (status != SCI_SUCCESS) 2790 if (status != SCI_SUCCESS)
2813 return status; 2791 return status;
2814 2792
2815 set_bit(IREQ_ACTIVE, &ireq->flags); 2793 set_bit(IREQ_ACTIVE, &ireq->flags);
2816 scic_sds_controller_post_request(scic, scic_sds_request_get_post_context(ireq)); 2794 scic_sds_controller_post_request(ihost, scic_sds_request_get_post_context(ireq));
2817 return SCI_SUCCESS; 2795 return SCI_SUCCESS;
2818} 2796}
2819 2797
@@ -2834,14 +2812,14 @@ enum sci_status scic_controller_start_io(struct scic_sds_controller *scic,
2834 * for the request. Determine the failure situations and return values. 2812 * for the request. Determine the failure situations and return values.
2835 */ 2813 */
2836enum sci_status scic_controller_terminate_request( 2814enum sci_status scic_controller_terminate_request(
2837 struct scic_sds_controller *scic, 2815 struct isci_host *ihost,
2838 struct isci_remote_device *idev, 2816 struct isci_remote_device *idev,
2839 struct isci_request *ireq) 2817 struct isci_request *ireq)
2840{ 2818{
2841 enum sci_status status; 2819 enum sci_status status;
2842 2820
2843 if (scic->sm.current_state_id != SCIC_READY) { 2821 if (ihost->sm.current_state_id != SCIC_READY) {
2844 dev_warn(scic_to_dev(scic), 2822 dev_warn(&ihost->pdev->dev,
2845 "invalid state to terminate request\n"); 2823 "invalid state to terminate request\n");
2846 return SCI_FAILURE_INVALID_STATE; 2824 return SCI_FAILURE_INVALID_STATE;
2847 } 2825 }
@@ -2854,7 +2832,7 @@ enum sci_status scic_controller_terminate_request(
2854 * Utilize the original post context command and or in the POST_TC_ABORT 2832 * Utilize the original post context command and or in the POST_TC_ABORT
2855 * request sub-type. 2833 * request sub-type.
2856 */ 2834 */
2857 scic_sds_controller_post_request(scic, 2835 scic_sds_controller_post_request(ihost,
2858 scic_sds_request_get_post_context(ireq) | 2836 scic_sds_request_get_post_context(ireq) |
2859 SCU_CONTEXT_COMMAND_REQUEST_POST_TC_ABORT); 2837 SCU_CONTEXT_COMMAND_REQUEST_POST_TC_ABORT);
2860 return SCI_SUCCESS; 2838 return SCI_SUCCESS;
@@ -2872,19 +2850,19 @@ enum sci_status scic_controller_terminate_request(
2872 * @io_request: the handle to the io request object to complete. 2850 * @io_request: the handle to the io request object to complete.
2873 */ 2851 */
2874enum sci_status scic_controller_complete_io( 2852enum sci_status scic_controller_complete_io(
2875 struct scic_sds_controller *scic, 2853 struct isci_host *ihost,
2876 struct isci_remote_device *idev, 2854 struct isci_remote_device *idev,
2877 struct isci_request *ireq) 2855 struct isci_request *ireq)
2878{ 2856{
2879 enum sci_status status; 2857 enum sci_status status;
2880 u16 index; 2858 u16 index;
2881 2859
2882 switch (scic->sm.current_state_id) { 2860 switch (ihost->sm.current_state_id) {
2883 case SCIC_STOPPING: 2861 case SCIC_STOPPING:
2884 /* XXX: Implement this function */ 2862 /* XXX: Implement this function */
2885 return SCI_FAILURE; 2863 return SCI_FAILURE;
2886 case SCIC_READY: 2864 case SCIC_READY:
2887 status = scic_sds_remote_device_complete_io(scic, idev, ireq); 2865 status = scic_sds_remote_device_complete_io(ihost, idev, ireq);
2888 if (status != SCI_SUCCESS) 2866 if (status != SCI_SUCCESS)
2889 return status; 2867 return status;
2890 2868
@@ -2892,7 +2870,7 @@ enum sci_status scic_controller_complete_io(
2892 clear_bit(IREQ_ACTIVE, &ireq->flags); 2870 clear_bit(IREQ_ACTIVE, &ireq->flags);
2893 return SCI_SUCCESS; 2871 return SCI_SUCCESS;
2894 default: 2872 default:
2895 dev_warn(scic_to_dev(scic), "invalid state to complete I/O"); 2873 dev_warn(&ihost->pdev->dev, "invalid state to complete I/O");
2896 return SCI_FAILURE_INVALID_STATE; 2874 return SCI_FAILURE_INVALID_STATE;
2897 } 2875 }
2898 2876
@@ -2900,15 +2878,15 @@ enum sci_status scic_controller_complete_io(
2900 2878
2901enum sci_status scic_controller_continue_io(struct isci_request *ireq) 2879enum sci_status scic_controller_continue_io(struct isci_request *ireq)
2902{ 2880{
2903 struct scic_sds_controller *scic = ireq->owning_controller; 2881 struct isci_host *ihost = ireq->owning_controller;
2904 2882
2905 if (scic->sm.current_state_id != SCIC_READY) { 2883 if (ihost->sm.current_state_id != SCIC_READY) {
2906 dev_warn(scic_to_dev(scic), "invalid state to continue I/O"); 2884 dev_warn(&ihost->pdev->dev, "invalid state to continue I/O");
2907 return SCI_FAILURE_INVALID_STATE; 2885 return SCI_FAILURE_INVALID_STATE;
2908 } 2886 }
2909 2887
2910 set_bit(IREQ_ACTIVE, &ireq->flags); 2888 set_bit(IREQ_ACTIVE, &ireq->flags);
2911 scic_sds_controller_post_request(scic, scic_sds_request_get_post_context(ireq)); 2889 scic_sds_controller_post_request(ihost, scic_sds_request_get_post_context(ireq));
2912 return SCI_SUCCESS; 2890 return SCI_SUCCESS;
2913} 2891}
2914 2892
@@ -2922,21 +2900,21 @@ enum sci_status scic_controller_continue_io(struct isci_request *ireq)
2922 * @task_request: the handle to the task request object to start. 2900 * @task_request: the handle to the task request object to start.
2923 */ 2901 */
2924enum sci_task_status scic_controller_start_task( 2902enum sci_task_status scic_controller_start_task(
2925 struct scic_sds_controller *scic, 2903 struct isci_host *ihost,
2926 struct isci_remote_device *idev, 2904 struct isci_remote_device *idev,
2927 struct isci_request *ireq) 2905 struct isci_request *ireq)
2928{ 2906{
2929 enum sci_status status; 2907 enum sci_status status;
2930 2908
2931 if (scic->sm.current_state_id != SCIC_READY) { 2909 if (ihost->sm.current_state_id != SCIC_READY) {
2932 dev_warn(scic_to_dev(scic), 2910 dev_warn(&ihost->pdev->dev,
2933 "%s: SCIC Controller starting task from invalid " 2911 "%s: SCIC Controller starting task from invalid "
2934 "state\n", 2912 "state\n",
2935 __func__); 2913 __func__);
2936 return SCI_TASK_FAILURE_INVALID_STATE; 2914 return SCI_TASK_FAILURE_INVALID_STATE;
2937 } 2915 }
2938 2916
2939 status = scic_sds_remote_device_start_task(scic, idev, ireq); 2917 status = scic_sds_remote_device_start_task(ihost, idev, ireq);
2940 switch (status) { 2918 switch (status) {
2941 case SCI_FAILURE_RESET_DEVICE_PARTIAL_SUCCESS: 2919 case SCI_FAILURE_RESET_DEVICE_PARTIAL_SUCCESS:
2942 set_bit(IREQ_ACTIVE, &ireq->flags); 2920 set_bit(IREQ_ACTIVE, &ireq->flags);
@@ -2950,7 +2928,7 @@ enum sci_task_status scic_controller_start_task(
2950 case SCI_SUCCESS: 2928 case SCI_SUCCESS:
2951 set_bit(IREQ_ACTIVE, &ireq->flags); 2929 set_bit(IREQ_ACTIVE, &ireq->flags);
2952 2930
2953 scic_sds_controller_post_request(scic, 2931 scic_sds_controller_post_request(ihost,
2954 scic_sds_request_get_post_context(ireq)); 2932 scic_sds_request_get_post_context(ireq));
2955 break; 2933 break;
2956 default: 2934 default:
generated by cgit v1.2.2 (git 2.25.0) at 2025-03-01 17:22:14 -0500