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authorJeff Skirvin <jeffrey.d.skirvin@intel.com>2012-01-04 04:32:39 -0500
committerJames Bottomley <JBottomley@Parallels.com>2012-01-16 02:40:29 -0500
commitafd13a1f2b05157c7621d87dfe89ea6ea9061bd8 (patch)
tree1dc7a3c2816de4598ada6871f1381336bf1b4192 /drivers/scsi/isci/host.c
parent2e5da889d44a3a9629f895de3488306e7f5ddf16 (diff)
[SCSI] isci: update afe (analog-front-end) recipe for C1
C1 silicon requires updates to the phy tuning recipe and also support for user provided cable selects (per-phy) for short, medium, and long cables. Default to 'short' awaiting support for selecting the cable via oem parameters. Reviewed-by: Jiangbi Liu <jiangbi.liu@intel.com> Signed-off-by: Marcin Tomczak <marcin.tomczak@intel.com> Signed-off-by: Jeff Skirvin <jeffrey.d.skirvin@intel.com> Signed-off-by: Dan Williams <dan.j.williams@intel.com> Signed-off-by: James Bottomley <JBottomley@Parallels.com>
Diffstat (limited to 'drivers/scsi/isci/host.c')
-rw-r--r--drivers/scsi/isci/host.c111
1 files changed, 89 insertions, 22 deletions
diff --git a/drivers/scsi/isci/host.c b/drivers/scsi/isci/host.c
index 8e7de192cf6d..383bb6913087 100644
--- a/drivers/scsi/isci/host.c
+++ b/drivers/scsi/isci/host.c
@@ -1908,12 +1908,23 @@ void sci_controller_power_control_queue_remove(struct isci_host *ihost,
1908 ihost->power_control.requesters[iphy->phy_index] = NULL; 1908 ihost->power_control.requesters[iphy->phy_index] = NULL;
1909} 1909}
1910 1910
1911static int is_long_cable(int phy, unsigned char selection_byte)
1912{
1913 return 0;
1914}
1915
1916static int is_medium_cable(int phy, unsigned char selection_byte)
1917{
1918 return 0;
1919}
1920
1911#define AFE_REGISTER_WRITE_DELAY 10 1921#define AFE_REGISTER_WRITE_DELAY 10
1912 1922
1913static void sci_controller_afe_initialization(struct isci_host *ihost) 1923static void sci_controller_afe_initialization(struct isci_host *ihost)
1914{ 1924{
1915 struct scu_afe_registers __iomem *afe = &ihost->scu_registers->afe; 1925 struct scu_afe_registers __iomem *afe = &ihost->scu_registers->afe;
1916 const struct sci_oem_params *oem = &ihost->oem_parameters; 1926 const struct sci_oem_params *oem = &ihost->oem_parameters;
1927 unsigned char cable_selection_mask = 0;
1917 struct pci_dev *pdev = ihost->pdev; 1928 struct pci_dev *pdev = ihost->pdev;
1918 u32 afe_status; 1929 u32 afe_status;
1919 u32 phy_id; 1930 u32 phy_id;
@@ -1922,11 +1933,11 @@ static void sci_controller_afe_initialization(struct isci_host *ihost)
1922 writel(0x0081000f, &afe->afe_dfx_master_control0); 1933 writel(0x0081000f, &afe->afe_dfx_master_control0);
1923 udelay(AFE_REGISTER_WRITE_DELAY); 1934 udelay(AFE_REGISTER_WRITE_DELAY);
1924 1935
1925 if (is_b0(pdev)) { 1936 if (is_b0(pdev) || is_c0(pdev) || is_c1(pdev)) {
1926 /* PM Rx Equalization Save, PM SPhy Rx Acknowledgement 1937 /* PM Rx Equalization Save, PM SPhy Rx Acknowledgement
1927 * Timer, PM Stagger Timer 1938 * Timer, PM Stagger Timer
1928 */ 1939 */
1929 writel(0x0007BFFF, &afe->afe_pmsn_master_control2); 1940 writel(0x0007FFFF, &afe->afe_pmsn_master_control2);
1930 udelay(AFE_REGISTER_WRITE_DELAY); 1941 udelay(AFE_REGISTER_WRITE_DELAY);
1931 } 1942 }
1932 1943
@@ -1935,14 +1946,23 @@ static void sci_controller_afe_initialization(struct isci_host *ihost)
1935 writel(0x00005A00, &afe->afe_bias_control); 1946 writel(0x00005A00, &afe->afe_bias_control);
1936 else if (is_b0(pdev) || is_c0(pdev)) 1947 else if (is_b0(pdev) || is_c0(pdev))
1937 writel(0x00005F00, &afe->afe_bias_control); 1948 writel(0x00005F00, &afe->afe_bias_control);
1949 else if (is_c1(pdev))
1950 writel(0x00005500, &afe->afe_bias_control);
1938 1951
1939 udelay(AFE_REGISTER_WRITE_DELAY); 1952 udelay(AFE_REGISTER_WRITE_DELAY);
1940 1953
1941 /* Enable PLL */ 1954 /* Enable PLL */
1942 if (is_b0(pdev) || is_c0(pdev)) 1955 if (is_a2(pdev))
1943 writel(0x80040A08, &afe->afe_pll_control0);
1944 else
1945 writel(0x80040908, &afe->afe_pll_control0); 1956 writel(0x80040908, &afe->afe_pll_control0);
1957 else if (is_b0(pdev) || is_c0(pdev))
1958 writel(0x80040A08, &afe->afe_pll_control0);
1959 else if (is_c1(pdev)) {
1960 writel(0x80000B08, &afe->afe_pll_control0);
1961 udelay(AFE_REGISTER_WRITE_DELAY);
1962 writel(0x00000B08, &afe->afe_pll_control0);
1963 udelay(AFE_REGISTER_WRITE_DELAY);
1964 writel(0x80000B08, &afe->afe_pll_control0);
1965 }
1946 1966
1947 udelay(AFE_REGISTER_WRITE_DELAY); 1967 udelay(AFE_REGISTER_WRITE_DELAY);
1948 1968
@@ -1963,46 +1983,68 @@ static void sci_controller_afe_initialization(struct isci_host *ihost)
1963 for (phy_id = 0; phy_id < SCI_MAX_PHYS; phy_id++) { 1983 for (phy_id = 0; phy_id < SCI_MAX_PHYS; phy_id++) {
1964 struct scu_afe_transceiver *xcvr = &afe->scu_afe_xcvr[phy_id]; 1984 struct scu_afe_transceiver *xcvr = &afe->scu_afe_xcvr[phy_id];
1965 const struct sci_phy_oem_params *oem_phy = &oem->phys[phy_id]; 1985 const struct sci_phy_oem_params *oem_phy = &oem->phys[phy_id];
1986 int cable_length_long =
1987 is_long_cable(phy_id, cable_selection_mask);
1988 int cable_length_medium =
1989 is_medium_cable(phy_id, cable_selection_mask);
1990
1991 if (is_a2(pdev)) {
1992 /* All defaults, except the Receive Word
1993 * Alignament/Comma Detect Enable....(0xe800)
1994 */
1995 writel(0x00004512, &xcvr->afe_xcvr_control0);
1996 udelay(AFE_REGISTER_WRITE_DELAY);
1966 1997
1967 if (is_b0(pdev)) { 1998 writel(0x0050100F, &xcvr->afe_xcvr_control1);
1968 /* Configure transmitter SSC parameters */ 1999 udelay(AFE_REGISTER_WRITE_DELAY);
2000 } else if (is_b0(pdev)) {
2001 /* Configure transmitter SSC parameters */
1969 writel(0x00030000, &xcvr->afe_tx_ssc_control); 2002 writel(0x00030000, &xcvr->afe_tx_ssc_control);
1970 udelay(AFE_REGISTER_WRITE_DELAY); 2003 udelay(AFE_REGISTER_WRITE_DELAY);
1971 } else if (is_c0(pdev)) { 2004 } else if (is_c0(pdev)) {
1972 /* Configure transmitter SSC parameters */ 2005 /* Configure transmitter SSC parameters */
1973 writel(0x0003000, &xcvr->afe_tx_ssc_control); 2006 writel(0x00010202, &xcvr->afe_tx_ssc_control);
1974 udelay(AFE_REGISTER_WRITE_DELAY); 2007 udelay(AFE_REGISTER_WRITE_DELAY);
1975 2008
1976 /* All defaults, except the Receive Word 2009 /* All defaults, except the Receive Word
1977 * Alignament/Comma Detect Enable....(0xe800) 2010 * Alignament/Comma Detect Enable....(0xe800)
1978 */ 2011 */
1979 writel(0x00004500, &xcvr->afe_xcvr_control0); 2012 writel(0x00014500, &xcvr->afe_xcvr_control0);
1980 udelay(AFE_REGISTER_WRITE_DELAY); 2013 udelay(AFE_REGISTER_WRITE_DELAY);
1981 } else { 2014 } else if (is_c1(pdev)) {
2015 /* Configure transmitter SSC parameters */
2016 writel(0x00010202, &xcvr->afe_tx_ssc_control);
2017 udelay(AFE_REGISTER_WRITE_DELAY);
2018
1982 /* All defaults, except the Receive Word 2019 /* All defaults, except the Receive Word
1983 * Alignament/Comma Detect Enable....(0xe800) 2020 * Alignament/Comma Detect Enable....(0xe800)
1984 */ 2021 */
1985 writel(0x00004512, &xcvr->afe_xcvr_control0); 2022 writel(0x0001C500, &xcvr->afe_xcvr_control0);
1986 udelay(AFE_REGISTER_WRITE_DELAY);
1987
1988 writel(0x0050100F, &xcvr->afe_xcvr_control1);
1989 udelay(AFE_REGISTER_WRITE_DELAY); 2023 udelay(AFE_REGISTER_WRITE_DELAY);
1990 } 2024 }
1991 2025
1992 /* Power up TX and RX out from power down (PWRDNTX and PWRDNRX) 2026 /* Power up TX and RX out from power down (PWRDNTX and
1993 * & increase TX int & ext bias 20%....(0xe85c) 2027 * PWRDNRX) & increase TX int & ext bias 20%....(0xe85c)
1994 */ 2028 */
1995 if (is_a2(pdev)) 2029 if (is_a2(pdev))
1996 writel(0x000003F0, &xcvr->afe_channel_control); 2030 writel(0x000003F0, &xcvr->afe_channel_control);
1997 else if (is_b0(pdev)) { 2031 else if (is_b0(pdev)) {
1998 /* Power down TX and RX (PWRDNTX and PWRDNRX) */
1999 writel(0x000003D7, &xcvr->afe_channel_control); 2032 writel(0x000003D7, &xcvr->afe_channel_control);
2000 udelay(AFE_REGISTER_WRITE_DELAY); 2033 udelay(AFE_REGISTER_WRITE_DELAY);
2034
2001 writel(0x000003D4, &xcvr->afe_channel_control); 2035 writel(0x000003D4, &xcvr->afe_channel_control);
2002 } else { 2036 } else if (is_c0(pdev)) {
2003 writel(0x000001E7, &xcvr->afe_channel_control); 2037 writel(0x000001E7, &xcvr->afe_channel_control);
2004 udelay(AFE_REGISTER_WRITE_DELAY); 2038 udelay(AFE_REGISTER_WRITE_DELAY);
2039
2005 writel(0x000001E4, &xcvr->afe_channel_control); 2040 writel(0x000001E4, &xcvr->afe_channel_control);
2041 } else if (is_c1(pdev)) {
2042 writel(cable_length_long ? 0x000002F7 : 0x000001F7,
2043 &xcvr->afe_channel_control);
2044 udelay(AFE_REGISTER_WRITE_DELAY);
2045
2046 writel(cable_length_long ? 0x000002F4 : 0x000001F4,
2047 &xcvr->afe_channel_control);
2006 } 2048 }
2007 udelay(AFE_REGISTER_WRITE_DELAY); 2049 udelay(AFE_REGISTER_WRITE_DELAY);
2008 2050
@@ -2012,7 +2054,16 @@ static void sci_controller_afe_initialization(struct isci_host *ihost)
2012 udelay(AFE_REGISTER_WRITE_DELAY); 2054 udelay(AFE_REGISTER_WRITE_DELAY);
2013 } 2055 }
2014 2056
2015 writel(0x00004100, &xcvr->afe_xcvr_control0); 2057 if (is_a2(pdev) || is_b0(pdev))
2058 /* RDPI=0x0(RX Power On), RXOOBDETPDNC=0x0,
2059 * TPD=0x0(TX Power On), RDD=0x0(RX Detect
2060 * Enabled) ....(0xe800)
2061 */
2062 writel(0x00004100, &xcvr->afe_xcvr_control0);
2063 else if (is_c0(pdev))
2064 writel(0x00014100, &xcvr->afe_xcvr_control0);
2065 else if (is_c1(pdev))
2066 writel(0x0001C100, &xcvr->afe_xcvr_control0);
2016 udelay(AFE_REGISTER_WRITE_DELAY); 2067 udelay(AFE_REGISTER_WRITE_DELAY);
2017 2068
2018 /* Leave DFE/FFE on */ 2069 /* Leave DFE/FFE on */
@@ -2023,8 +2074,8 @@ static void sci_controller_afe_initialization(struct isci_host *ihost)
2023 udelay(AFE_REGISTER_WRITE_DELAY); 2074 udelay(AFE_REGISTER_WRITE_DELAY);
2024 /* Enable TX equalization (0xe824) */ 2075 /* Enable TX equalization (0xe824) */
2025 writel(0x00040000, &xcvr->afe_tx_control); 2076 writel(0x00040000, &xcvr->afe_tx_control);
2026 } else { 2077 } else if (is_c0(pdev)) {
2027 writel(0x0140DF0F, &xcvr->afe_rx_ssc_control1); 2078 writel(0x01400C0F, &xcvr->afe_rx_ssc_control1);
2028 udelay(AFE_REGISTER_WRITE_DELAY); 2079 udelay(AFE_REGISTER_WRITE_DELAY);
2029 2080
2030 writel(0x3F6F103F, &xcvr->afe_rx_ssc_control0); 2081 writel(0x3F6F103F, &xcvr->afe_rx_ssc_control0);
@@ -2032,6 +2083,22 @@ static void sci_controller_afe_initialization(struct isci_host *ihost)
2032 2083
2033 /* Enable TX equalization (0xe824) */ 2084 /* Enable TX equalization (0xe824) */
2034 writel(0x00040000, &xcvr->afe_tx_control); 2085 writel(0x00040000, &xcvr->afe_tx_control);
2086 } else if (is_c1(pdev)) {
2087 writel(cable_length_long ? 0x01500C0C :
2088 cable_length_medium ? 0x01400C0D : 0x02400C0D,
2089 &xcvr->afe_xcvr_control1);
2090 udelay(AFE_REGISTER_WRITE_DELAY);
2091
2092 writel(0x000003E0, &xcvr->afe_dfx_rx_control1);
2093 udelay(AFE_REGISTER_WRITE_DELAY);
2094
2095 writel(cable_length_long ? 0x33091C1F :
2096 cable_length_medium ? 0x3315181F : 0x2B17161F,
2097 &xcvr->afe_rx_ssc_control0);
2098 udelay(AFE_REGISTER_WRITE_DELAY);
2099
2100 /* Enable TX equalization (0xe824) */
2101 writel(0x00040000, &xcvr->afe_tx_control);
2035 } 2102 }
2036 2103
2037 udelay(AFE_REGISTER_WRITE_DELAY); 2104 udelay(AFE_REGISTER_WRITE_DELAY);