[SCSI] bfa: Brocade-1860 Fabric Adapter PLL init fixes.

- If flash controller is halted unconditionally, this results in
  illegal write access to flash controller register domain. Since
  flash controller registers are only accessible once s_clk is started
  - added logic to check for WGN status and halt flash controller only
  if it is already running.
- Added check to wait for flash controller halt to be completed before
  proceeding with s_clk/l_clk initializations.
- Removed unnecessary reset logic for PMM 1T memory and moved memory
  initialization after flash access enable.
- Disable Brocade-1860 asic MBOX interrupt before PLL initialization.
- Remove reset enable for S_CLK/L_CLK after both PLL initializations
  are complete.

Signed-off-by: Krishna Gudipati <kgudipat@brocade.com>
Signed-off-by: James Bottomley <JBottomley@Parallels.com>

1 files changed, 11 insertions, 0 deletions

diff --git a/drivers/scsi/bfa/bfi_reg.h b/drivers/scsi/bfa/bfi_reg.h
index d20d2b30ed30..d892064b64a8 100644
--- a/drivers/scsi/bfa/bfi_reg.h
+++ b/drivers/scsi/bfa/bfi_reg.h
@@ -277,6 +277,8 @@ enum {
 #define CT2_LPU1_HOSTFN_CMD_STAT        (CT2_PCI_CPQ_BASE + 0x8c)
 #define CT2_HOSTFN_LPU0_READ_STAT       (CT2_PCI_CPQ_BASE + 0x90)
 #define CT2_HOSTFN_LPU1_READ_STAT       (CT2_PCI_CPQ_BASE + 0x94)
+#define CT2_LPU0_HOSTFN_MBOX0_MSK       (CT2_PCI_CPQ_BASE + 0x98)
+#define CT2_LPU1_HOSTFN_MBOX0_MSK       (CT2_PCI_CPQ_BASE + 0x9C)
 #define CT2_HOST_SEM0_REG               0x000148f0
 #define CT2_HOST_SEM1_REG               0x000148f4
 #define CT2_HOST_SEM2_REG               0x000148f8
@@ -337,6 +339,15 @@ enum {
 #define __GLBL_PF_VF_CFG_RDY            0x00000200
 #define CT2_NFC_CSR_SET_REG             0x00027424
 #define __HALT_NFC_CONTROLLER           0x00000002
+#define __NFC_CONTROLLER_HALTED         0x00001000
+
+#define CT2_CSI_MAC0_CONTROL_REG        0x000270d0
+#define __CSI_MAC_RESET                 0x00000010
+#define __CSI_MAC_AHB_RESET             0x00000008
+#define CT2_CSI_MAC1_CONTROL_REG        0x000270d4
+#define CT2_CSI_MAC_CONTROL_REG(__n)    \
+        (CT2_CSI_MAC0_CONTROL_REG +     \
+        (__n) * (CT2_CSI_MAC1_CONTROL_REG - CT2_CSI_MAC0_CONTROL_REG))
 
 /*
  * Name semaphore registers based on usage