diff options
author | Andrea Bastoni <bastoni@cs.unc.edu> | 2010-05-30 19:16:45 -0400 |
---|---|---|
committer | Andrea Bastoni <bastoni@cs.unc.edu> | 2010-05-30 19:16:45 -0400 |
commit | ada47b5fe13d89735805b566185f4885f5a3f750 (patch) | |
tree | 644b88f8a71896307d71438e9b3af49126ffb22b /drivers/scsi/be2iscsi/be_cmds.c | |
parent | 43e98717ad40a4ae64545b5ba047c7b86aa44f4f (diff) | |
parent | 3280f21d43ee541f97f8cda5792150d2dbec20d5 (diff) |
Merge branch 'wip-2.6.34' into old-private-masterarchived-private-master
Diffstat (limited to 'drivers/scsi/be2iscsi/be_cmds.c')
-rw-r--r-- | drivers/scsi/be2iscsi/be_cmds.c | 330 |
1 files changed, 298 insertions, 32 deletions
diff --git a/drivers/scsi/be2iscsi/be_cmds.c b/drivers/scsi/be2iscsi/be_cmds.c index 08007b6e42df..cda6642c7368 100644 --- a/drivers/scsi/be2iscsi/be_cmds.c +++ b/drivers/scsi/be2iscsi/be_cmds.c | |||
@@ -1,5 +1,5 @@ | |||
1 | /** | 1 | /** |
2 | * Copyright (C) 2005 - 2009 ServerEngines | 2 | * Copyright (C) 2005 - 2010 ServerEngines |
3 | * All rights reserved. | 3 | * All rights reserved. |
4 | * | 4 | * |
5 | * This program is free software; you can redistribute it and/or | 5 | * This program is free software; you can redistribute it and/or |
@@ -19,6 +19,55 @@ | |||
19 | #include "be_mgmt.h" | 19 | #include "be_mgmt.h" |
20 | #include "be_main.h" | 20 | #include "be_main.h" |
21 | 21 | ||
22 | void be_mcc_notify(struct beiscsi_hba *phba) | ||
23 | { | ||
24 | struct be_queue_info *mccq = &phba->ctrl.mcc_obj.q; | ||
25 | u32 val = 0; | ||
26 | |||
27 | val |= mccq->id & DB_MCCQ_RING_ID_MASK; | ||
28 | val |= 1 << DB_MCCQ_NUM_POSTED_SHIFT; | ||
29 | iowrite32(val, phba->db_va + DB_MCCQ_OFFSET); | ||
30 | } | ||
31 | |||
32 | unsigned int alloc_mcc_tag(struct beiscsi_hba *phba) | ||
33 | { | ||
34 | unsigned int tag = 0; | ||
35 | |||
36 | if (phba->ctrl.mcc_tag_available) { | ||
37 | tag = phba->ctrl.mcc_tag[phba->ctrl.mcc_alloc_index]; | ||
38 | phba->ctrl.mcc_tag[phba->ctrl.mcc_alloc_index] = 0; | ||
39 | phba->ctrl.mcc_numtag[tag] = 0; | ||
40 | } | ||
41 | if (tag) { | ||
42 | phba->ctrl.mcc_tag_available--; | ||
43 | if (phba->ctrl.mcc_alloc_index == (MAX_MCC_CMD - 1)) | ||
44 | phba->ctrl.mcc_alloc_index = 0; | ||
45 | else | ||
46 | phba->ctrl.mcc_alloc_index++; | ||
47 | } | ||
48 | return tag; | ||
49 | } | ||
50 | |||
51 | void free_mcc_tag(struct be_ctrl_info *ctrl, unsigned int tag) | ||
52 | { | ||
53 | spin_lock(&ctrl->mbox_lock); | ||
54 | tag = tag & 0x000000FF; | ||
55 | ctrl->mcc_tag[ctrl->mcc_free_index] = tag; | ||
56 | if (ctrl->mcc_free_index == (MAX_MCC_CMD - 1)) | ||
57 | ctrl->mcc_free_index = 0; | ||
58 | else | ||
59 | ctrl->mcc_free_index++; | ||
60 | ctrl->mcc_tag_available++; | ||
61 | spin_unlock(&ctrl->mbox_lock); | ||
62 | } | ||
63 | |||
64 | bool is_link_state_evt(u32 trailer) | ||
65 | { | ||
66 | return (((trailer >> ASYNC_TRAILER_EVENT_CODE_SHIFT) & | ||
67 | ASYNC_TRAILER_EVENT_CODE_MASK) == | ||
68 | ASYNC_EVENT_CODE_LINK_STATE); | ||
69 | } | ||
70 | |||
22 | static inline bool be_mcc_compl_is_new(struct be_mcc_compl *compl) | 71 | static inline bool be_mcc_compl_is_new(struct be_mcc_compl *compl) |
23 | { | 72 | { |
24 | if (compl->flags != 0) { | 73 | if (compl->flags != 0) { |
@@ -54,13 +103,74 @@ static int be_mcc_compl_process(struct be_ctrl_info *ctrl, | |||
54 | return 0; | 103 | return 0; |
55 | } | 104 | } |
56 | 105 | ||
57 | static inline bool is_link_state_evt(u32 trailer) | 106 | int be_mcc_compl_process_isr(struct be_ctrl_info *ctrl, |
107 | struct be_mcc_compl *compl) | ||
58 | { | 108 | { |
59 | return (((trailer >> ASYNC_TRAILER_EVENT_CODE_SHIFT) & | 109 | u16 compl_status, extd_status; |
60 | ASYNC_TRAILER_EVENT_CODE_MASK) == ASYNC_EVENT_CODE_LINK_STATE); | 110 | unsigned short tag; |
111 | |||
112 | be_dws_le_to_cpu(compl, 4); | ||
113 | |||
114 | compl_status = (compl->status >> CQE_STATUS_COMPL_SHIFT) & | ||
115 | CQE_STATUS_COMPL_MASK; | ||
116 | /* The ctrl.mcc_numtag[tag] is filled with | ||
117 | * [31] = valid, [30:24] = Rsvd, [23:16] = wrb, [15:8] = extd_status, | ||
118 | * [7:0] = compl_status | ||
119 | */ | ||
120 | tag = (compl->tag0 & 0x000000FF); | ||
121 | extd_status = (compl->status >> CQE_STATUS_EXTD_SHIFT) & | ||
122 | CQE_STATUS_EXTD_MASK; | ||
123 | |||
124 | ctrl->mcc_numtag[tag] = 0x80000000; | ||
125 | ctrl->mcc_numtag[tag] |= (compl->tag0 & 0x00FF0000); | ||
126 | ctrl->mcc_numtag[tag] |= (extd_status & 0x000000FF) << 8; | ||
127 | ctrl->mcc_numtag[tag] |= (compl_status & 0x000000FF); | ||
128 | wake_up_interruptible(&ctrl->mcc_wait[tag]); | ||
129 | return 0; | ||
130 | } | ||
131 | |||
132 | static struct be_mcc_compl *be_mcc_compl_get(struct beiscsi_hba *phba) | ||
133 | { | ||
134 | struct be_queue_info *mcc_cq = &phba->ctrl.mcc_obj.cq; | ||
135 | struct be_mcc_compl *compl = queue_tail_node(mcc_cq); | ||
136 | |||
137 | if (be_mcc_compl_is_new(compl)) { | ||
138 | queue_tail_inc(mcc_cq); | ||
139 | return compl; | ||
140 | } | ||
141 | return NULL; | ||
142 | } | ||
143 | |||
144 | static void be2iscsi_fail_session(struct iscsi_cls_session *cls_session) | ||
145 | { | ||
146 | iscsi_session_failure(cls_session->dd_data, ISCSI_ERR_CONN_FAILED); | ||
61 | } | 147 | } |
62 | 148 | ||
63 | void beiscsi_cq_notify(struct be_ctrl_info *ctrl, u16 qid, bool arm, | 149 | void beiscsi_async_link_state_process(struct beiscsi_hba *phba, |
150 | struct be_async_event_link_state *evt) | ||
151 | { | ||
152 | switch (evt->port_link_status) { | ||
153 | case ASYNC_EVENT_LINK_DOWN: | ||
154 | SE_DEBUG(DBG_LVL_1, "Link Down on Physical Port %d \n", | ||
155 | evt->physical_port); | ||
156 | phba->state |= BE_ADAPTER_LINK_DOWN; | ||
157 | iscsi_host_for_each_session(phba->shost, | ||
158 | be2iscsi_fail_session); | ||
159 | break; | ||
160 | case ASYNC_EVENT_LINK_UP: | ||
161 | phba->state = BE_ADAPTER_UP; | ||
162 | SE_DEBUG(DBG_LVL_1, "Link UP on Physical Port %d \n", | ||
163 | evt->physical_port); | ||
164 | break; | ||
165 | default: | ||
166 | SE_DEBUG(DBG_LVL_1, "Unexpected Async Notification %d on" | ||
167 | "Physical Port %d \n", | ||
168 | evt->port_link_status, | ||
169 | evt->physical_port); | ||
170 | } | ||
171 | } | ||
172 | |||
173 | static void beiscsi_cq_notify(struct beiscsi_hba *phba, u16 qid, bool arm, | ||
64 | u16 num_popped) | 174 | u16 num_popped) |
65 | { | 175 | { |
66 | u32 val = 0; | 176 | u32 val = 0; |
@@ -68,7 +178,69 @@ void beiscsi_cq_notify(struct be_ctrl_info *ctrl, u16 qid, bool arm, | |||
68 | if (arm) | 178 | if (arm) |
69 | val |= 1 << DB_CQ_REARM_SHIFT; | 179 | val |= 1 << DB_CQ_REARM_SHIFT; |
70 | val |= num_popped << DB_CQ_NUM_POPPED_SHIFT; | 180 | val |= num_popped << DB_CQ_NUM_POPPED_SHIFT; |
71 | iowrite32(val, ctrl->db + DB_CQ_OFFSET); | 181 | iowrite32(val, phba->db_va + DB_CQ_OFFSET); |
182 | } | ||
183 | |||
184 | |||
185 | int beiscsi_process_mcc(struct beiscsi_hba *phba) | ||
186 | { | ||
187 | struct be_mcc_compl *compl; | ||
188 | int num = 0, status = 0; | ||
189 | struct be_ctrl_info *ctrl = &phba->ctrl; | ||
190 | |||
191 | spin_lock_bh(&phba->ctrl.mcc_cq_lock); | ||
192 | while ((compl = be_mcc_compl_get(phba))) { | ||
193 | if (compl->flags & CQE_FLAGS_ASYNC_MASK) { | ||
194 | /* Interpret flags as an async trailer */ | ||
195 | if (is_link_state_evt(compl->flags)) | ||
196 | /* Interpret compl as a async link evt */ | ||
197 | beiscsi_async_link_state_process(phba, | ||
198 | (struct be_async_event_link_state *) compl); | ||
199 | else | ||
200 | SE_DEBUG(DBG_LVL_1, | ||
201 | " Unsupported Async Event, flags" | ||
202 | " = 0x%08x \n", compl->flags); | ||
203 | |||
204 | } else if (compl->flags & CQE_FLAGS_COMPLETED_MASK) { | ||
205 | status = be_mcc_compl_process(ctrl, compl); | ||
206 | atomic_dec(&phba->ctrl.mcc_obj.q.used); | ||
207 | } | ||
208 | be_mcc_compl_use(compl); | ||
209 | num++; | ||
210 | } | ||
211 | |||
212 | if (num) | ||
213 | beiscsi_cq_notify(phba, phba->ctrl.mcc_obj.cq.id, true, num); | ||
214 | |||
215 | spin_unlock_bh(&phba->ctrl.mcc_cq_lock); | ||
216 | return status; | ||
217 | } | ||
218 | |||
219 | /* Wait till no more pending mcc requests are present */ | ||
220 | static int be_mcc_wait_compl(struct beiscsi_hba *phba) | ||
221 | { | ||
222 | int i, status; | ||
223 | for (i = 0; i < mcc_timeout; i++) { | ||
224 | status = beiscsi_process_mcc(phba); | ||
225 | if (status) | ||
226 | return status; | ||
227 | |||
228 | if (atomic_read(&phba->ctrl.mcc_obj.q.used) == 0) | ||
229 | break; | ||
230 | udelay(100); | ||
231 | } | ||
232 | if (i == mcc_timeout) { | ||
233 | dev_err(&phba->pcidev->dev, "mccq poll timed out\n"); | ||
234 | return -1; | ||
235 | } | ||
236 | return 0; | ||
237 | } | ||
238 | |||
239 | /* Notify MCC requests and wait for completion */ | ||
240 | int be_mcc_notify_wait(struct beiscsi_hba *phba) | ||
241 | { | ||
242 | be_mcc_notify(phba); | ||
243 | return be_mcc_wait_compl(phba); | ||
72 | } | 244 | } |
73 | 245 | ||
74 | static int be_mbox_db_ready_wait(struct be_ctrl_info *ctrl) | 246 | static int be_mbox_db_ready_wait(struct be_ctrl_info *ctrl) |
@@ -142,6 +314,52 @@ int be_mbox_notify(struct be_ctrl_info *ctrl) | |||
142 | return 0; | 314 | return 0; |
143 | } | 315 | } |
144 | 316 | ||
317 | /* | ||
318 | * Insert the mailbox address into the doorbell in two steps | ||
319 | * Polls on the mbox doorbell till a command completion (or a timeout) occurs | ||
320 | */ | ||
321 | static int be_mbox_notify_wait(struct beiscsi_hba *phba) | ||
322 | { | ||
323 | int status; | ||
324 | u32 val = 0; | ||
325 | void __iomem *db = phba->ctrl.db + MPU_MAILBOX_DB_OFFSET; | ||
326 | struct be_dma_mem *mbox_mem = &phba->ctrl.mbox_mem; | ||
327 | struct be_mcc_mailbox *mbox = mbox_mem->va; | ||
328 | struct be_mcc_compl *compl = &mbox->compl; | ||
329 | struct be_ctrl_info *ctrl = &phba->ctrl; | ||
330 | |||
331 | val |= MPU_MAILBOX_DB_HI_MASK; | ||
332 | /* at bits 2 - 31 place mbox dma addr msb bits 34 - 63 */ | ||
333 | val |= (upper_32_bits(mbox_mem->dma) >> 2) << 2; | ||
334 | iowrite32(val, db); | ||
335 | |||
336 | /* wait for ready to be set */ | ||
337 | status = be_mbox_db_ready_wait(ctrl); | ||
338 | if (status != 0) | ||
339 | return status; | ||
340 | |||
341 | val = 0; | ||
342 | /* at bits 2 - 31 place mbox dma addr lsb bits 4 - 33 */ | ||
343 | val |= (u32)(mbox_mem->dma >> 4) << 2; | ||
344 | iowrite32(val, db); | ||
345 | |||
346 | status = be_mbox_db_ready_wait(ctrl); | ||
347 | if (status != 0) | ||
348 | return status; | ||
349 | |||
350 | /* A cq entry has been made now */ | ||
351 | if (be_mcc_compl_is_new(compl)) { | ||
352 | status = be_mcc_compl_process(ctrl, &mbox->compl); | ||
353 | be_mcc_compl_use(compl); | ||
354 | if (status) | ||
355 | return status; | ||
356 | } else { | ||
357 | dev_err(&phba->pcidev->dev, "invalid mailbox completion\n"); | ||
358 | return -1; | ||
359 | } | ||
360 | return 0; | ||
361 | } | ||
362 | |||
145 | void be_wrb_hdr_prepare(struct be_mcc_wrb *wrb, int payload_len, | 363 | void be_wrb_hdr_prepare(struct be_mcc_wrb *wrb, int payload_len, |
146 | bool embedded, u8 sge_cnt) | 364 | bool embedded, u8 sge_cnt) |
147 | { | 365 | { |
@@ -203,6 +421,21 @@ struct be_mcc_wrb *wrb_from_mbox(struct be_dma_mem *mbox_mem) | |||
203 | return &((struct be_mcc_mailbox *)(mbox_mem->va))->wrb; | 421 | return &((struct be_mcc_mailbox *)(mbox_mem->va))->wrb; |
204 | } | 422 | } |
205 | 423 | ||
424 | struct be_mcc_wrb *wrb_from_mccq(struct beiscsi_hba *phba) | ||
425 | { | ||
426 | struct be_queue_info *mccq = &phba->ctrl.mcc_obj.q; | ||
427 | struct be_mcc_wrb *wrb; | ||
428 | |||
429 | BUG_ON(atomic_read(&mccq->used) >= mccq->len); | ||
430 | wrb = queue_head_node(mccq); | ||
431 | memset(wrb, 0, sizeof(*wrb)); | ||
432 | wrb->tag0 = (mccq->head & 0x000000FF) << 16; | ||
433 | queue_head_inc(mccq); | ||
434 | atomic_inc(&mccq->used); | ||
435 | return wrb; | ||
436 | } | ||
437 | |||
438 | |||
206 | int beiscsi_cmd_eq_create(struct be_ctrl_info *ctrl, | 439 | int beiscsi_cmd_eq_create(struct be_ctrl_info *ctrl, |
207 | struct be_queue_info *eq, int eq_delay) | 440 | struct be_queue_info *eq, int eq_delay) |
208 | { | 441 | { |
@@ -212,6 +445,7 @@ int beiscsi_cmd_eq_create(struct be_ctrl_info *ctrl, | |||
212 | struct be_dma_mem *q_mem = &eq->dma_mem; | 445 | struct be_dma_mem *q_mem = &eq->dma_mem; |
213 | int status; | 446 | int status; |
214 | 447 | ||
448 | SE_DEBUG(DBG_LVL_8, "In beiscsi_cmd_eq_create\n"); | ||
215 | spin_lock(&ctrl->mbox_lock); | 449 | spin_lock(&ctrl->mbox_lock); |
216 | memset(wrb, 0, sizeof(*wrb)); | 450 | memset(wrb, 0, sizeof(*wrb)); |
217 | 451 | ||
@@ -249,6 +483,7 @@ int be_cmd_fw_initialize(struct be_ctrl_info *ctrl) | |||
249 | int status; | 483 | int status; |
250 | u8 *endian_check; | 484 | u8 *endian_check; |
251 | 485 | ||
486 | SE_DEBUG(DBG_LVL_8, "In be_cmd_fw_initialize\n"); | ||
252 | spin_lock(&ctrl->mbox_lock); | 487 | spin_lock(&ctrl->mbox_lock); |
253 | memset(wrb, 0, sizeof(*wrb)); | 488 | memset(wrb, 0, sizeof(*wrb)); |
254 | 489 | ||
@@ -282,6 +517,7 @@ int beiscsi_cmd_cq_create(struct be_ctrl_info *ctrl, | |||
282 | void *ctxt = &req->context; | 517 | void *ctxt = &req->context; |
283 | int status; | 518 | int status; |
284 | 519 | ||
520 | SE_DEBUG(DBG_LVL_8, "In beiscsi_cmd_cq_create \n"); | ||
285 | spin_lock(&ctrl->mbox_lock); | 521 | spin_lock(&ctrl->mbox_lock); |
286 | memset(wrb, 0, sizeof(*wrb)); | 522 | memset(wrb, 0, sizeof(*wrb)); |
287 | 523 | ||
@@ -289,7 +525,6 @@ int beiscsi_cmd_cq_create(struct be_ctrl_info *ctrl, | |||
289 | 525 | ||
290 | be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON, | 526 | be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON, |
291 | OPCODE_COMMON_CQ_CREATE, sizeof(*req)); | 527 | OPCODE_COMMON_CQ_CREATE, sizeof(*req)); |
292 | |||
293 | if (!q_mem->va) | 528 | if (!q_mem->va) |
294 | SE_DEBUG(DBG_LVL_1, "uninitialized q_mem->va\n"); | 529 | SE_DEBUG(DBG_LVL_1, "uninitialized q_mem->va\n"); |
295 | 530 | ||
@@ -329,6 +564,53 @@ static u32 be_encoded_q_len(int q_len) | |||
329 | len_encoded = 0; | 564 | len_encoded = 0; |
330 | return len_encoded; | 565 | return len_encoded; |
331 | } | 566 | } |
567 | |||
568 | int beiscsi_cmd_mccq_create(struct beiscsi_hba *phba, | ||
569 | struct be_queue_info *mccq, | ||
570 | struct be_queue_info *cq) | ||
571 | { | ||
572 | struct be_mcc_wrb *wrb; | ||
573 | struct be_cmd_req_mcc_create *req; | ||
574 | struct be_dma_mem *q_mem = &mccq->dma_mem; | ||
575 | struct be_ctrl_info *ctrl; | ||
576 | void *ctxt; | ||
577 | int status; | ||
578 | |||
579 | spin_lock(&phba->ctrl.mbox_lock); | ||
580 | ctrl = &phba->ctrl; | ||
581 | wrb = wrb_from_mbox(&ctrl->mbox_mem); | ||
582 | req = embedded_payload(wrb); | ||
583 | ctxt = &req->context; | ||
584 | |||
585 | be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0); | ||
586 | |||
587 | be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON, | ||
588 | OPCODE_COMMON_MCC_CREATE, sizeof(*req)); | ||
589 | |||
590 | req->num_pages = PAGES_4K_SPANNED(q_mem->va, q_mem->size); | ||
591 | |||
592 | AMAP_SET_BITS(struct amap_mcc_context, fid, ctxt, | ||
593 | PCI_FUNC(phba->pcidev->devfn)); | ||
594 | AMAP_SET_BITS(struct amap_mcc_context, valid, ctxt, 1); | ||
595 | AMAP_SET_BITS(struct amap_mcc_context, ring_size, ctxt, | ||
596 | be_encoded_q_len(mccq->len)); | ||
597 | AMAP_SET_BITS(struct amap_mcc_context, cq_id, ctxt, cq->id); | ||
598 | |||
599 | be_dws_cpu_to_le(ctxt, sizeof(req->context)); | ||
600 | |||
601 | be_cmd_page_addrs_prepare(req->pages, ARRAY_SIZE(req->pages), q_mem); | ||
602 | |||
603 | status = be_mbox_notify_wait(phba); | ||
604 | if (!status) { | ||
605 | struct be_cmd_resp_mcc_create *resp = embedded_payload(wrb); | ||
606 | mccq->id = le16_to_cpu(resp->id); | ||
607 | mccq->created = true; | ||
608 | } | ||
609 | spin_unlock(&phba->ctrl.mbox_lock); | ||
610 | |||
611 | return status; | ||
612 | } | ||
613 | |||
332 | int beiscsi_cmd_q_destroy(struct be_ctrl_info *ctrl, struct be_queue_info *q, | 614 | int beiscsi_cmd_q_destroy(struct be_ctrl_info *ctrl, struct be_queue_info *q, |
333 | int queue_type) | 615 | int queue_type) |
334 | { | 616 | { |
@@ -337,6 +619,7 @@ int beiscsi_cmd_q_destroy(struct be_ctrl_info *ctrl, struct be_queue_info *q, | |||
337 | u8 subsys = 0, opcode = 0; | 619 | u8 subsys = 0, opcode = 0; |
338 | int status; | 620 | int status; |
339 | 621 | ||
622 | SE_DEBUG(DBG_LVL_8, "In beiscsi_cmd_q_destroy \n"); | ||
340 | spin_lock(&ctrl->mbox_lock); | 623 | spin_lock(&ctrl->mbox_lock); |
341 | memset(wrb, 0, sizeof(*wrb)); | 624 | memset(wrb, 0, sizeof(*wrb)); |
342 | be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0); | 625 | be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0); |
@@ -350,6 +633,10 @@ int beiscsi_cmd_q_destroy(struct be_ctrl_info *ctrl, struct be_queue_info *q, | |||
350 | subsys = CMD_SUBSYSTEM_COMMON; | 633 | subsys = CMD_SUBSYSTEM_COMMON; |
351 | opcode = OPCODE_COMMON_CQ_DESTROY; | 634 | opcode = OPCODE_COMMON_CQ_DESTROY; |
352 | break; | 635 | break; |
636 | case QTYPE_MCCQ: | ||
637 | subsys = CMD_SUBSYSTEM_COMMON; | ||
638 | opcode = OPCODE_COMMON_MCC_DESTROY; | ||
639 | break; | ||
353 | case QTYPE_WRBQ: | 640 | case QTYPE_WRBQ: |
354 | subsys = CMD_SUBSYSTEM_ISCSI; | 641 | subsys = CMD_SUBSYSTEM_ISCSI; |
355 | opcode = OPCODE_COMMON_ISCSI_WRBQ_DESTROY; | 642 | opcode = OPCODE_COMMON_ISCSI_WRBQ_DESTROY; |
@@ -377,30 +664,6 @@ int beiscsi_cmd_q_destroy(struct be_ctrl_info *ctrl, struct be_queue_info *q, | |||
377 | return status; | 664 | return status; |
378 | } | 665 | } |
379 | 666 | ||
380 | int be_cmd_get_mac_addr(struct be_ctrl_info *ctrl, u8 *mac_addr) | ||
381 | { | ||
382 | struct be_mcc_wrb *wrb = wrb_from_mbox(&ctrl->mbox_mem); | ||
383 | struct be_cmd_req_get_mac_addr *req = embedded_payload(wrb); | ||
384 | int status; | ||
385 | |||
386 | spin_lock(&ctrl->mbox_lock); | ||
387 | memset(wrb, 0, sizeof(*wrb)); | ||
388 | be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0); | ||
389 | be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ISCSI, | ||
390 | OPCODE_COMMON_ISCSI_NTWK_GET_NIC_CONFIG, | ||
391 | sizeof(*req)); | ||
392 | |||
393 | status = be_mbox_notify(ctrl); | ||
394 | if (!status) { | ||
395 | struct be_cmd_resp_get_mac_addr *resp = embedded_payload(wrb); | ||
396 | |||
397 | memcpy(mac_addr, resp->mac_address, ETH_ALEN); | ||
398 | } | ||
399 | |||
400 | spin_unlock(&ctrl->mbox_lock); | ||
401 | return status; | ||
402 | } | ||
403 | |||
404 | int be_cmd_create_default_pdu_queue(struct be_ctrl_info *ctrl, | 667 | int be_cmd_create_default_pdu_queue(struct be_ctrl_info *ctrl, |
405 | struct be_queue_info *cq, | 668 | struct be_queue_info *cq, |
406 | struct be_queue_info *dq, int length, | 669 | struct be_queue_info *dq, int length, |
@@ -412,6 +675,7 @@ int be_cmd_create_default_pdu_queue(struct be_ctrl_info *ctrl, | |||
412 | void *ctxt = &req->context; | 675 | void *ctxt = &req->context; |
413 | int status; | 676 | int status; |
414 | 677 | ||
678 | SE_DEBUG(DBG_LVL_8, "In be_cmd_create_default_pdu_queue\n"); | ||
415 | spin_lock(&ctrl->mbox_lock); | 679 | spin_lock(&ctrl->mbox_lock); |
416 | memset(wrb, 0, sizeof(*wrb)); | 680 | memset(wrb, 0, sizeof(*wrb)); |
417 | 681 | ||
@@ -468,8 +732,10 @@ int be_cmd_wrbq_create(struct be_ctrl_info *ctrl, struct be_dma_mem *q_mem, | |||
468 | be_cmd_page_addrs_prepare(req->pages, ARRAY_SIZE(req->pages), q_mem); | 732 | be_cmd_page_addrs_prepare(req->pages, ARRAY_SIZE(req->pages), q_mem); |
469 | 733 | ||
470 | status = be_mbox_notify(ctrl); | 734 | status = be_mbox_notify(ctrl); |
471 | if (!status) | 735 | if (!status) { |
472 | wrbq->id = le16_to_cpu(resp->cid); | 736 | wrbq->id = le16_to_cpu(resp->cid); |
737 | wrbq->created = true; | ||
738 | } | ||
473 | spin_unlock(&ctrl->mbox_lock); | 739 | spin_unlock(&ctrl->mbox_lock); |
474 | return status; | 740 | return status; |
475 | } | 741 | } |