diff options
author | Lucas De Marchi <lucas.demarchi@profusion.mobi> | 2011-03-30 21:57:33 -0400 |
---|---|---|
committer | Lucas De Marchi <lucas.demarchi@profusion.mobi> | 2011-03-31 10:26:23 -0400 |
commit | 25985edcedea6396277003854657b5f3cb31a628 (patch) | |
tree | f026e810210a2ee7290caeb737c23cb6472b7c38 /drivers/scsi/aic7xxx/aic79xx.reg | |
parent | 6aba74f2791287ec407e0f92487a725a25908067 (diff) |
Fix common misspellings
Fixes generated by 'codespell' and manually reviewed.
Signed-off-by: Lucas De Marchi <lucas.demarchi@profusion.mobi>
Diffstat (limited to 'drivers/scsi/aic7xxx/aic79xx.reg')
-rw-r--r-- | drivers/scsi/aic7xxx/aic79xx.reg | 24 |
1 files changed, 12 insertions, 12 deletions
diff --git a/drivers/scsi/aic7xxx/aic79xx.reg b/drivers/scsi/aic7xxx/aic79xx.reg index 0666c22ab55b..7e12c31ccfda 100644 --- a/drivers/scsi/aic7xxx/aic79xx.reg +++ b/drivers/scsi/aic7xxx/aic79xx.reg | |||
@@ -305,7 +305,7 @@ register HS_MAILBOX { | |||
305 | } | 305 | } |
306 | 306 | ||
307 | /* | 307 | /* |
308 | * Sequencer Interupt Status | 308 | * Sequencer Interrupt Status |
309 | */ | 309 | */ |
310 | register SEQINTSTAT { | 310 | register SEQINTSTAT { |
311 | address 0x00C | 311 | address 0x00C |
@@ -685,7 +685,7 @@ register DCHRXMSG0 { | |||
685 | } | 685 | } |
686 | 686 | ||
687 | /* | 687 | /* |
688 | * CMC Recieve Message 0 | 688 | * CMC Receive Message 0 |
689 | */ | 689 | */ |
690 | register CMCRXMSG0 { | 690 | register CMCRXMSG0 { |
691 | address 0x090 | 691 | address 0x090 |
@@ -696,7 +696,7 @@ register CMCRXMSG0 { | |||
696 | } | 696 | } |
697 | 697 | ||
698 | /* | 698 | /* |
699 | * Overlay Recieve Message 0 | 699 | * Overlay Receive Message 0 |
700 | */ | 700 | */ |
701 | register OVLYRXMSG0 { | 701 | register OVLYRXMSG0 { |
702 | address 0x090 | 702 | address 0x090 |
@@ -732,7 +732,7 @@ register DCHRXMSG1 { | |||
732 | } | 732 | } |
733 | 733 | ||
734 | /* | 734 | /* |
735 | * CMC Recieve Message 1 | 735 | * CMC Receive Message 1 |
736 | */ | 736 | */ |
737 | register CMCRXMSG1 { | 737 | register CMCRXMSG1 { |
738 | address 0x091 | 738 | address 0x091 |
@@ -742,7 +742,7 @@ register CMCRXMSG1 { | |||
742 | } | 742 | } |
743 | 743 | ||
744 | /* | 744 | /* |
745 | * Overlay Recieve Message 1 | 745 | * Overlay Receive Message 1 |
746 | */ | 746 | */ |
747 | register OVLYRXMSG1 { | 747 | register OVLYRXMSG1 { |
748 | address 0x091 | 748 | address 0x091 |
@@ -777,7 +777,7 @@ register DCHRXMSG2 { | |||
777 | } | 777 | } |
778 | 778 | ||
779 | /* | 779 | /* |
780 | * CMC Recieve Message 2 | 780 | * CMC Receive Message 2 |
781 | */ | 781 | */ |
782 | register CMCRXMSG2 { | 782 | register CMCRXMSG2 { |
783 | address 0x092 | 783 | address 0x092 |
@@ -787,7 +787,7 @@ register CMCRXMSG2 { | |||
787 | } | 787 | } |
788 | 788 | ||
789 | /* | 789 | /* |
790 | * Overlay Recieve Message 2 | 790 | * Overlay Receive Message 2 |
791 | */ | 791 | */ |
792 | register OVLYRXMSG2 { | 792 | register OVLYRXMSG2 { |
793 | address 0x092 | 793 | address 0x092 |
@@ -816,7 +816,7 @@ register DCHRXMSG3 { | |||
816 | } | 816 | } |
817 | 817 | ||
818 | /* | 818 | /* |
819 | * CMC Recieve Message 3 | 819 | * CMC Receive Message 3 |
820 | */ | 820 | */ |
821 | register CMCRXMSG3 { | 821 | register CMCRXMSG3 { |
822 | address 0x093 | 822 | address 0x093 |
@@ -826,7 +826,7 @@ register CMCRXMSG3 { | |||
826 | } | 826 | } |
827 | 827 | ||
828 | /* | 828 | /* |
829 | * Overlay Recieve Message 3 | 829 | * Overlay Receive Message 3 |
830 | */ | 830 | */ |
831 | register OVLYRXMSG3 { | 831 | register OVLYRXMSG3 { |
832 | address 0x093 | 832 | address 0x093 |
@@ -1249,7 +1249,7 @@ register TARGPCISTAT { | |||
1249 | 1249 | ||
1250 | /* | 1250 | /* |
1251 | * LQ Packet In | 1251 | * LQ Packet In |
1252 | * The last LQ Packet recieved | 1252 | * The last LQ Packet received |
1253 | */ | 1253 | */ |
1254 | register LQIN { | 1254 | register LQIN { |
1255 | address 0x020 | 1255 | address 0x020 |
@@ -2573,7 +2573,7 @@ register IOPDNCTL { | |||
2573 | } | 2573 | } |
2574 | 2574 | ||
2575 | /* | 2575 | /* |
2576 | * Shaddow Host Address. | 2576 | * Shadow Host Address. |
2577 | */ | 2577 | */ |
2578 | register SHADDR { | 2578 | register SHADDR { |
2579 | address 0x060 | 2579 | address 0x060 |
@@ -3983,7 +3983,7 @@ scratch_ram { | |||
3983 | 3983 | ||
3984 | /* | 3984 | /* |
3985 | * The maximum amount of time to wait, when interrupt coalescing | 3985 | * The maximum amount of time to wait, when interrupt coalescing |
3986 | * is enabled, before issueing a CMDCMPLT interrupt for a completed | 3986 | * is enabled, before issuing a CMDCMPLT interrupt for a completed |
3987 | * command. | 3987 | * command. |
3988 | */ | 3988 | */ |
3989 | INT_COALESCING_TIMER { | 3989 | INT_COALESCING_TIMER { |