diff options
author | Haojian Zhuang <haojian.zhuang@linaro.org> | 2013-02-04 17:28:54 -0500 |
---|---|---|
committer | Linus Torvalds <torvalds@linux-foundation.org> | 2013-02-05 04:38:49 -0500 |
commit | e7e034e18a0ab6bafb2425c3242cac311164f4d6 (patch) | |
tree | fec0169c405a6f6618df263db8d6cb20c4e6cbd4 /drivers/rtc | |
parent | 72fca4a4b32dc778b5b885c3498700e42b610d49 (diff) |
drivers/rtc/rtc-pl031.c: fix the missing operation on enable
The RTC control register should be enabled in the process of
initializing.
Without this patch, I failed to enable RTC in Hisilicon Hi3620 SoC. The
register mapping section in RTC is always read as zero. So I doubt that
ST guys may already enable this register in bootloader. So they won't
meet this issue.
Signed-off-by: Haojian Zhuang <haojian.zhuang@linaro.org>
Cc: Srinidhi Kasagar <srinidhi.kasagar@stericsson.com>
Cc: Linus Walleij <linus.walleij@linaro.org>
Cc: Alessandro Zummo <a.zummo@towertech.it>
Cc: <stable@vger.kernel.org>
Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
Diffstat (limited to 'drivers/rtc')
-rw-r--r-- | drivers/rtc/rtc-pl031.c | 8 |
1 files changed, 5 insertions, 3 deletions
diff --git a/drivers/rtc/rtc-pl031.c b/drivers/rtc/rtc-pl031.c index 08378e3cc21c..10c1a3454e48 100644 --- a/drivers/rtc/rtc-pl031.c +++ b/drivers/rtc/rtc-pl031.c | |||
@@ -44,6 +44,7 @@ | |||
44 | #define RTC_YMR 0x34 /* Year match register */ | 44 | #define RTC_YMR 0x34 /* Year match register */ |
45 | #define RTC_YLR 0x38 /* Year data load register */ | 45 | #define RTC_YLR 0x38 /* Year data load register */ |
46 | 46 | ||
47 | #define RTC_CR_EN (1 << 0) /* counter enable bit */ | ||
47 | #define RTC_CR_CWEN (1 << 26) /* Clockwatch enable bit */ | 48 | #define RTC_CR_CWEN (1 << 26) /* Clockwatch enable bit */ |
48 | 49 | ||
49 | #define RTC_TCR_EN (1 << 1) /* Periodic timer enable bit */ | 50 | #define RTC_TCR_EN (1 << 1) /* Periodic timer enable bit */ |
@@ -320,7 +321,7 @@ static int pl031_probe(struct amba_device *adev, const struct amba_id *id) | |||
320 | struct pl031_local *ldata; | 321 | struct pl031_local *ldata; |
321 | struct pl031_vendor_data *vendor = id->data; | 322 | struct pl031_vendor_data *vendor = id->data; |
322 | struct rtc_class_ops *ops = &vendor->ops; | 323 | struct rtc_class_ops *ops = &vendor->ops; |
323 | unsigned long time; | 324 | unsigned long time, data; |
324 | 325 | ||
325 | ret = amba_request_regions(adev, NULL); | 326 | ret = amba_request_regions(adev, NULL); |
326 | if (ret) | 327 | if (ret) |
@@ -345,10 +346,11 @@ static int pl031_probe(struct amba_device *adev, const struct amba_id *id) | |||
345 | dev_dbg(&adev->dev, "designer ID = 0x%02x\n", amba_manf(adev)); | 346 | dev_dbg(&adev->dev, "designer ID = 0x%02x\n", amba_manf(adev)); |
346 | dev_dbg(&adev->dev, "revision = 0x%01x\n", amba_rev(adev)); | 347 | dev_dbg(&adev->dev, "revision = 0x%01x\n", amba_rev(adev)); |
347 | 348 | ||
349 | data = readl(ldata->base + RTC_CR); | ||
348 | /* Enable the clockwatch on ST Variants */ | 350 | /* Enable the clockwatch on ST Variants */ |
349 | if (vendor->clockwatch) | 351 | if (vendor->clockwatch) |
350 | writel(readl(ldata->base + RTC_CR) | RTC_CR_CWEN, | 352 | data |= RTC_CR_CWEN; |
351 | ldata->base + RTC_CR); | 353 | writel(data | RTC_CR_EN, ldata->base + RTC_CR); |
352 | 354 | ||
353 | /* | 355 | /* |
354 | * On ST PL031 variants, the RTC reset value does not provide correct | 356 | * On ST PL031 variants, the RTC reset value does not provide correct |