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authorIngo Molnar <mingo@kernel.org>2015-03-04 00:35:43 -0500
committerIngo Molnar <mingo@kernel.org>2015-03-04 00:35:43 -0500
commitd2c032e3dc58137a7261a7824d3acce435db1d66 (patch)
tree7eea1c7c6103eefe879f07472eec99b3c41eb792 /drivers/rtc/rtc-imxdi.c
parent7e8e385aaf6ed5b64b5d9108081cfcdcdd021b78 (diff)
parent13a7a6ac0a11197edcd0f756a035f472b42cdf8b (diff)
Merge tag 'v4.0-rc2' into x86/asm, to refresh the tree
Signed-off-by: Ingo Molnar <mingo@kernel.org>
Diffstat (limited to 'drivers/rtc/rtc-imxdi.c')
-rw-r--r--drivers/rtc/rtc-imxdi.c50
1 files changed, 43 insertions, 7 deletions
diff --git a/drivers/rtc/rtc-imxdi.c b/drivers/rtc/rtc-imxdi.c
index 42f5570f42f8..c666eab98273 100644
--- a/drivers/rtc/rtc-imxdi.c
+++ b/drivers/rtc/rtc-imxdi.c
@@ -50,22 +50,58 @@
50#define DCAMR_UNSET 0xFFFFFFFF /* doomsday - 1 sec */ 50#define DCAMR_UNSET 0xFFFFFFFF /* doomsday - 1 sec */
51 51
52#define DCR 0x10 /* Control Reg */ 52#define DCR 0x10 /* Control Reg */
53#define DCR_TDCHL (1 << 30) /* Tamper-detect configuration hard lock */
54#define DCR_TDCSL (1 << 29) /* Tamper-detect configuration soft lock */
55#define DCR_KSSL (1 << 27) /* Key-select soft lock */
56#define DCR_MCHL (1 << 20) /* Monotonic-counter hard lock */
57#define DCR_MCSL (1 << 19) /* Monotonic-counter soft lock */
58#define DCR_TCHL (1 << 18) /* Timer-counter hard lock */
59#define DCR_TCSL (1 << 17) /* Timer-counter soft lock */
60#define DCR_FSHL (1 << 16) /* Failure state hard lock */
53#define DCR_TCE (1 << 3) /* Time Counter Enable */ 61#define DCR_TCE (1 << 3) /* Time Counter Enable */
62#define DCR_MCE (1 << 2) /* Monotonic Counter Enable */
54 63
55#define DSR 0x14 /* Status Reg */ 64#define DSR 0x14 /* Status Reg */
56#define DSR_WBF (1 << 10) /* Write Busy Flag */ 65#define DSR_WTD (1 << 23) /* Wire-mesh tamper detected */
57#define DSR_WNF (1 << 9) /* Write Next Flag */ 66#define DSR_ETBD (1 << 22) /* External tamper B detected */
58#define DSR_WCF (1 << 8) /* Write Complete Flag */ 67#define DSR_ETAD (1 << 21) /* External tamper A detected */
68#define DSR_EBD (1 << 20) /* External boot detected */
69#define DSR_SAD (1 << 19) /* SCC alarm detected */
70#define DSR_TTD (1 << 18) /* Temperatur tamper detected */
71#define DSR_CTD (1 << 17) /* Clock tamper detected */
72#define DSR_VTD (1 << 16) /* Voltage tamper detected */
73#define DSR_WBF (1 << 10) /* Write Busy Flag (synchronous) */
74#define DSR_WNF (1 << 9) /* Write Next Flag (synchronous) */
75#define DSR_WCF (1 << 8) /* Write Complete Flag (synchronous)*/
59#define DSR_WEF (1 << 7) /* Write Error Flag */ 76#define DSR_WEF (1 << 7) /* Write Error Flag */
60#define DSR_CAF (1 << 4) /* Clock Alarm Flag */ 77#define DSR_CAF (1 << 4) /* Clock Alarm Flag */
78#define DSR_MCO (1 << 3) /* monotonic counter overflow */
79#define DSR_TCO (1 << 2) /* time counter overflow */
61#define DSR_NVF (1 << 1) /* Non-Valid Flag */ 80#define DSR_NVF (1 << 1) /* Non-Valid Flag */
62#define DSR_SVF (1 << 0) /* Security Violation Flag */ 81#define DSR_SVF (1 << 0) /* Security Violation Flag */
63 82
64#define DIER 0x18 /* Interrupt Enable Reg */ 83#define DIER 0x18 /* Interrupt Enable Reg (synchronous) */
65#define DIER_WNIE (1 << 9) /* Write Next Interrupt Enable */ 84#define DIER_WNIE (1 << 9) /* Write Next Interrupt Enable */
66#define DIER_WCIE (1 << 8) /* Write Complete Interrupt Enable */ 85#define DIER_WCIE (1 << 8) /* Write Complete Interrupt Enable */
67#define DIER_WEIE (1 << 7) /* Write Error Interrupt Enable */ 86#define DIER_WEIE (1 << 7) /* Write Error Interrupt Enable */
68#define DIER_CAIE (1 << 4) /* Clock Alarm Interrupt Enable */ 87#define DIER_CAIE (1 << 4) /* Clock Alarm Interrupt Enable */
88#define DIER_SVIE (1 << 0) /* Security-violation Interrupt Enable */
89
90#define DMCR 0x1c /* DryIce Monotonic Counter Reg */
91
92#define DTCR 0x28 /* DryIce Tamper Configuration Reg */
93#define DTCR_MOE (1 << 9) /* monotonic overflow enabled */
94#define DTCR_TOE (1 << 8) /* time overflow enabled */
95#define DTCR_WTE (1 << 7) /* wire-mesh tamper enabled */
96#define DTCR_ETBE (1 << 6) /* external B tamper enabled */
97#define DTCR_ETAE (1 << 5) /* external A tamper enabled */
98#define DTCR_EBE (1 << 4) /* external boot tamper enabled */
99#define DTCR_SAIE (1 << 3) /* SCC enabled */
100#define DTCR_TTE (1 << 2) /* temperature tamper enabled */
101#define DTCR_CTE (1 << 1) /* clock tamper enabled */
102#define DTCR_VTE (1 << 0) /* voltage tamper enabled */
103
104#define DGPR 0x3c /* DryIce General Purpose Reg */
69 105
70/** 106/**
71 * struct imxdi_dev - private imxdi rtc data 107 * struct imxdi_dev - private imxdi rtc data
@@ -313,7 +349,7 @@ static irqreturn_t dryice_norm_irq(int irq, void *dev_id)
313 dier = __raw_readl(imxdi->ioaddr + DIER); 349 dier = __raw_readl(imxdi->ioaddr + DIER);
314 350
315 /* handle write complete and write error cases */ 351 /* handle write complete and write error cases */
316 if ((dier & DIER_WCIE)) { 352 if (dier & DIER_WCIE) {
317 /*If the write wait queue is empty then there is no pending 353 /*If the write wait queue is empty then there is no pending
318 operations. It means the interrupt is for DryIce -Security. 354 operations. It means the interrupt is for DryIce -Security.
319 IRQ must be returned as none.*/ 355 IRQ must be returned as none.*/
@@ -322,7 +358,7 @@ static irqreturn_t dryice_norm_irq(int irq, void *dev_id)
322 358
323 /* DSR_WCF clears itself on DSR read */ 359 /* DSR_WCF clears itself on DSR read */
324 dsr = __raw_readl(imxdi->ioaddr + DSR); 360 dsr = __raw_readl(imxdi->ioaddr + DSR);
325 if ((dsr & (DSR_WCF | DSR_WEF))) { 361 if (dsr & (DSR_WCF | DSR_WEF)) {
326 /* mask the interrupt */ 362 /* mask the interrupt */
327 di_int_disable(imxdi, DIER_WCIE); 363 di_int_disable(imxdi, DIER_WCIE);
328 364
@@ -335,7 +371,7 @@ static irqreturn_t dryice_norm_irq(int irq, void *dev_id)
335 } 371 }
336 372
337 /* handle the alarm case */ 373 /* handle the alarm case */
338 if ((dier & DIER_CAIE)) { 374 if (dier & DIER_CAIE) {
339 /* DSR_WCF clears itself on DSR read */ 375 /* DSR_WCF clears itself on DSR read */
340 dsr = __raw_readl(imxdi->ioaddr + DSR); 376 dsr = __raw_readl(imxdi->ioaddr + DSR);
341 if (dsr & DSR_CAF) { 377 if (dsr & DSR_CAF) {