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authorRhyland Klein <rklein@nvidia.com>2012-05-08 14:42:38 -0400
committerSamuel Ortiz <sameo@linux.intel.com>2012-05-20 11:25:23 -0400
commit3f7e82759c692df473675ed06fb90b20f1f225c3 (patch)
treef8f120546e55def9cb88ff9a0b8e13d4b36bb342 /drivers/regulator
parent7ccfe9b1d58ef5cf8fdbd50b6ee2ae0e9aa9cb36 (diff)
mfd: Commonize tps65910 regmap access through header
This change removes the read/write callback functions in favor of common regmap accessors inside the header file. This change also makes use of regmap_read/write for single register access which maps better onto what this driver actually needs. Signed-off-by: Rhyland Klein <rklein@nvidia.com> Signed-off-by: Samuel Ortiz <sameo@linux.intel.com>
Diffstat (limited to 'drivers/regulator')
-rw-r--r--drivers/regulator/tps65910-regulator.c88
1 files changed, 42 insertions, 46 deletions
diff --git a/drivers/regulator/tps65910-regulator.c b/drivers/regulator/tps65910-regulator.c
index 4a37c2b6367f..852b05b20de9 100644
--- a/drivers/regulator/tps65910-regulator.c
+++ b/drivers/regulator/tps65910-regulator.c
@@ -331,21 +331,16 @@ struct tps65910_reg {
331 331
332static inline int tps65910_read(struct tps65910_reg *pmic, u8 reg) 332static inline int tps65910_read(struct tps65910_reg *pmic, u8 reg)
333{ 333{
334 u8 val; 334 unsigned int val;
335 int err; 335 int err;
336 336
337 err = pmic->mfd->read(pmic->mfd, reg, 1, &val); 337 err = tps65910_reg_read(pmic->mfd, reg, &val);
338 if (err) 338 if (err)
339 return err; 339 return err;
340 340
341 return val; 341 return val;
342} 342}
343 343
344static inline int tps65910_write(struct tps65910_reg *pmic, u8 reg, u8 val)
345{
346 return pmic->mfd->write(pmic->mfd, reg, 1, &val);
347}
348
349static int tps65910_modify_bits(struct tps65910_reg *pmic, u8 reg, 344static int tps65910_modify_bits(struct tps65910_reg *pmic, u8 reg,
350 u8 set_mask, u8 clear_mask) 345 u8 set_mask, u8 clear_mask)
351{ 346{
@@ -362,7 +357,7 @@ static int tps65910_modify_bits(struct tps65910_reg *pmic, u8 reg,
362 357
363 data &= ~clear_mask; 358 data &= ~clear_mask;
364 data |= set_mask; 359 data |= set_mask;
365 err = tps65910_write(pmic, reg, data); 360 err = tps65910_reg_write(pmic->mfd, reg, data);
366 if (err) 361 if (err)
367 dev_err(pmic->mfd->dev, "Write for reg 0x%x failed\n", reg); 362 dev_err(pmic->mfd->dev, "Write for reg 0x%x failed\n", reg);
368 363
@@ -371,7 +366,7 @@ out:
371 return err; 366 return err;
372} 367}
373 368
374static int tps65910_reg_read(struct tps65910_reg *pmic, u8 reg) 369static int tps65910_reg_read_locked(struct tps65910_reg *pmic, u8 reg)
375{ 370{
376 int data; 371 int data;
377 372
@@ -385,13 +380,13 @@ static int tps65910_reg_read(struct tps65910_reg *pmic, u8 reg)
385 return data; 380 return data;
386} 381}
387 382
388static int tps65910_reg_write(struct tps65910_reg *pmic, u8 reg, u8 val) 383static int tps65910_reg_write_locked(struct tps65910_reg *pmic, u8 reg, u8 val)
389{ 384{
390 int err; 385 int err;
391 386
392 mutex_lock(&pmic->mutex); 387 mutex_lock(&pmic->mutex);
393 388
394 err = tps65910_write(pmic, reg, val); 389 err = tps65910_reg_write(pmic->mfd, reg, val);
395 if (err < 0) 390 if (err < 0)
396 dev_err(pmic->mfd->dev, "Write for reg 0x%x failed\n", reg); 391 dev_err(pmic->mfd->dev, "Write for reg 0x%x failed\n", reg);
397 392
@@ -476,7 +471,7 @@ static int tps65910_is_enabled(struct regulator_dev *dev)
476 if (reg < 0) 471 if (reg < 0)
477 return reg; 472 return reg;
478 473
479 value = tps65910_reg_read(pmic, reg); 474 value = tps65910_reg_read_locked(pmic, reg);
480 if (value < 0) 475 if (value < 0)
481 return value; 476 return value;
482 477
@@ -493,7 +488,7 @@ static int tps65910_enable(struct regulator_dev *dev)
493 if (reg < 0) 488 if (reg < 0)
494 return reg; 489 return reg;
495 490
496 return tps65910_set_bits(mfd, reg, TPS65910_SUPPLY_STATE_ENABLED); 491 return tps65910_reg_set_bits(mfd, reg, TPS65910_SUPPLY_STATE_ENABLED);
497} 492}
498 493
499static int tps65910_disable(struct regulator_dev *dev) 494static int tps65910_disable(struct regulator_dev *dev)
@@ -506,7 +501,7 @@ static int tps65910_disable(struct regulator_dev *dev)
506 if (reg < 0) 501 if (reg < 0)
507 return reg; 502 return reg;
508 503
509 return tps65910_clear_bits(mfd, reg, TPS65910_SUPPLY_STATE_ENABLED); 504 return tps65910_reg_clear_bits(mfd, reg, TPS65910_SUPPLY_STATE_ENABLED);
510} 505}
511 506
512static int tps65910_enable_time(struct regulator_dev *dev) 507static int tps65910_enable_time(struct regulator_dev *dev)
@@ -532,9 +527,9 @@ static int tps65910_set_mode(struct regulator_dev *dev, unsigned int mode)
532 LDO_ST_MODE_BIT); 527 LDO_ST_MODE_BIT);
533 case REGULATOR_MODE_IDLE: 528 case REGULATOR_MODE_IDLE:
534 value = LDO_ST_ON_BIT | LDO_ST_MODE_BIT; 529 value = LDO_ST_ON_BIT | LDO_ST_MODE_BIT;
535 return tps65910_set_bits(mfd, reg, value); 530 return tps65910_reg_set_bits(mfd, reg, value);
536 case REGULATOR_MODE_STANDBY: 531 case REGULATOR_MODE_STANDBY:
537 return tps65910_clear_bits(mfd, reg, LDO_ST_ON_BIT); 532 return tps65910_reg_clear_bits(mfd, reg, LDO_ST_ON_BIT);
538 } 533 }
539 534
540 return -EINVAL; 535 return -EINVAL;
@@ -549,7 +544,7 @@ static unsigned int tps65910_get_mode(struct regulator_dev *dev)
549 if (reg < 0) 544 if (reg < 0)
550 return reg; 545 return reg;
551 546
552 value = tps65910_reg_read(pmic, reg); 547 value = tps65910_reg_read_locked(pmic, reg);
553 if (value < 0) 548 if (value < 0)
554 return value; 549 return value;
555 550
@@ -569,28 +564,28 @@ static int tps65910_get_voltage_dcdc_sel(struct regulator_dev *dev)
569 564
570 switch (id) { 565 switch (id) {
571 case TPS65910_REG_VDD1: 566 case TPS65910_REG_VDD1:
572 opvsel = tps65910_reg_read(pmic, TPS65910_VDD1_OP); 567 opvsel = tps65910_reg_read_locked(pmic, TPS65910_VDD1_OP);
573 mult = tps65910_reg_read(pmic, TPS65910_VDD1); 568 mult = tps65910_reg_read_locked(pmic, TPS65910_VDD1);
574 mult = (mult & VDD1_VGAIN_SEL_MASK) >> VDD1_VGAIN_SEL_SHIFT; 569 mult = (mult & VDD1_VGAIN_SEL_MASK) >> VDD1_VGAIN_SEL_SHIFT;
575 srvsel = tps65910_reg_read(pmic, TPS65910_VDD1_SR); 570 srvsel = tps65910_reg_read_locked(pmic, TPS65910_VDD1_SR);
576 sr = opvsel & VDD1_OP_CMD_MASK; 571 sr = opvsel & VDD1_OP_CMD_MASK;
577 opvsel &= VDD1_OP_SEL_MASK; 572 opvsel &= VDD1_OP_SEL_MASK;
578 srvsel &= VDD1_SR_SEL_MASK; 573 srvsel &= VDD1_SR_SEL_MASK;
579 vselmax = 75; 574 vselmax = 75;
580 break; 575 break;
581 case TPS65910_REG_VDD2: 576 case TPS65910_REG_VDD2:
582 opvsel = tps65910_reg_read(pmic, TPS65910_VDD2_OP); 577 opvsel = tps65910_reg_read_locked(pmic, TPS65910_VDD2_OP);
583 mult = tps65910_reg_read(pmic, TPS65910_VDD2); 578 mult = tps65910_reg_read_locked(pmic, TPS65910_VDD2);
584 mult = (mult & VDD2_VGAIN_SEL_MASK) >> VDD2_VGAIN_SEL_SHIFT; 579 mult = (mult & VDD2_VGAIN_SEL_MASK) >> VDD2_VGAIN_SEL_SHIFT;
585 srvsel = tps65910_reg_read(pmic, TPS65910_VDD2_SR); 580 srvsel = tps65910_reg_read_locked(pmic, TPS65910_VDD2_SR);
586 sr = opvsel & VDD2_OP_CMD_MASK; 581 sr = opvsel & VDD2_OP_CMD_MASK;
587 opvsel &= VDD2_OP_SEL_MASK; 582 opvsel &= VDD2_OP_SEL_MASK;
588 srvsel &= VDD2_SR_SEL_MASK; 583 srvsel &= VDD2_SR_SEL_MASK;
589 vselmax = 75; 584 vselmax = 75;
590 break; 585 break;
591 case TPS65911_REG_VDDCTRL: 586 case TPS65911_REG_VDDCTRL:
592 opvsel = tps65910_reg_read(pmic, TPS65911_VDDCTRL_OP); 587 opvsel = tps65910_reg_read_locked(pmic, TPS65911_VDDCTRL_OP);
593 srvsel = tps65910_reg_read(pmic, TPS65911_VDDCTRL_SR); 588 srvsel = tps65910_reg_read_locked(pmic, TPS65911_VDDCTRL_SR);
594 sr = opvsel & VDDCTRL_OP_CMD_MASK; 589 sr = opvsel & VDDCTRL_OP_CMD_MASK;
595 opvsel &= VDDCTRL_OP_SEL_MASK; 590 opvsel &= VDDCTRL_OP_SEL_MASK;
596 srvsel &= VDDCTRL_SR_SEL_MASK; 591 srvsel &= VDDCTRL_SR_SEL_MASK;
@@ -630,7 +625,7 @@ static int tps65910_get_voltage(struct regulator_dev *dev)
630 if (reg < 0) 625 if (reg < 0)
631 return reg; 626 return reg;
632 627
633 value = tps65910_reg_read(pmic, reg); 628 value = tps65910_reg_read_locked(pmic, reg);
634 if (value < 0) 629 if (value < 0)
635 return value; 630 return value;
636 631
@@ -669,7 +664,7 @@ static int tps65911_get_voltage(struct regulator_dev *dev)
669 664
670 reg = pmic->get_ctrl_reg(id); 665 reg = pmic->get_ctrl_reg(id);
671 666
672 value = tps65910_reg_read(pmic, reg); 667 value = tps65910_reg_read_locked(pmic, reg);
673 668
674 switch (id) { 669 switch (id) {
675 case TPS65911_REG_LDO1: 670 case TPS65911_REG_LDO1:
@@ -728,7 +723,7 @@ static int tps65910_set_voltage_dcdc_sel(struct regulator_dev *dev,
728 tps65910_modify_bits(pmic, TPS65910_VDD1, 723 tps65910_modify_bits(pmic, TPS65910_VDD1,
729 (dcdc_mult << VDD1_VGAIN_SEL_SHIFT), 724 (dcdc_mult << VDD1_VGAIN_SEL_SHIFT),
730 VDD1_VGAIN_SEL_MASK); 725 VDD1_VGAIN_SEL_MASK);
731 tps65910_reg_write(pmic, TPS65910_VDD1_OP, vsel); 726 tps65910_reg_write_locked(pmic, TPS65910_VDD1_OP, vsel);
732 break; 727 break;
733 case TPS65910_REG_VDD2: 728 case TPS65910_REG_VDD2:
734 dcdc_mult = (selector / VDD1_2_NUM_VOLT_FINE) + 1; 729 dcdc_mult = (selector / VDD1_2_NUM_VOLT_FINE) + 1;
@@ -739,11 +734,11 @@ static int tps65910_set_voltage_dcdc_sel(struct regulator_dev *dev,
739 tps65910_modify_bits(pmic, TPS65910_VDD2, 734 tps65910_modify_bits(pmic, TPS65910_VDD2,
740 (dcdc_mult << VDD2_VGAIN_SEL_SHIFT), 735 (dcdc_mult << VDD2_VGAIN_SEL_SHIFT),
741 VDD1_VGAIN_SEL_MASK); 736 VDD1_VGAIN_SEL_MASK);
742 tps65910_reg_write(pmic, TPS65910_VDD2_OP, vsel); 737 tps65910_reg_write_locked(pmic, TPS65910_VDD2_OP, vsel);
743 break; 738 break;
744 case TPS65911_REG_VDDCTRL: 739 case TPS65911_REG_VDDCTRL:
745 vsel = selector + 3; 740 vsel = selector + 3;
746 tps65910_reg_write(pmic, TPS65911_VDDCTRL_OP, vsel); 741 tps65910_reg_write_locked(pmic, TPS65911_VDDCTRL_OP, vsel);
747 } 742 }
748 743
749 return 0; 744 return 0;
@@ -994,10 +989,10 @@ static int tps65910_set_ext_sleep_config(struct tps65910_reg *pmic,
994 989
995 /* External EN1 control */ 990 /* External EN1 control */
996 if (ext_sleep_config & TPS65910_SLEEP_CONTROL_EXT_INPUT_EN1) 991 if (ext_sleep_config & TPS65910_SLEEP_CONTROL_EXT_INPUT_EN1)
997 ret = tps65910_set_bits(mfd, 992 ret = tps65910_reg_set_bits(mfd,
998 TPS65910_EN1_LDO_ASS + regoffs, bit_pos); 993 TPS65910_EN1_LDO_ASS + regoffs, bit_pos);
999 else 994 else
1000 ret = tps65910_clear_bits(mfd, 995 ret = tps65910_reg_clear_bits(mfd,
1001 TPS65910_EN1_LDO_ASS + regoffs, bit_pos); 996 TPS65910_EN1_LDO_ASS + regoffs, bit_pos);
1002 if (ret < 0) { 997 if (ret < 0) {
1003 dev_err(mfd->dev, 998 dev_err(mfd->dev,
@@ -1007,10 +1002,10 @@ static int tps65910_set_ext_sleep_config(struct tps65910_reg *pmic,
1007 1002
1008 /* External EN2 control */ 1003 /* External EN2 control */
1009 if (ext_sleep_config & TPS65910_SLEEP_CONTROL_EXT_INPUT_EN2) 1004 if (ext_sleep_config & TPS65910_SLEEP_CONTROL_EXT_INPUT_EN2)
1010 ret = tps65910_set_bits(mfd, 1005 ret = tps65910_reg_set_bits(mfd,
1011 TPS65910_EN2_LDO_ASS + regoffs, bit_pos); 1006 TPS65910_EN2_LDO_ASS + regoffs, bit_pos);
1012 else 1007 else
1013 ret = tps65910_clear_bits(mfd, 1008 ret = tps65910_reg_clear_bits(mfd,
1014 TPS65910_EN2_LDO_ASS + regoffs, bit_pos); 1009 TPS65910_EN2_LDO_ASS + regoffs, bit_pos);
1015 if (ret < 0) { 1010 if (ret < 0) {
1016 dev_err(mfd->dev, 1011 dev_err(mfd->dev,
@@ -1022,10 +1017,10 @@ static int tps65910_set_ext_sleep_config(struct tps65910_reg *pmic,
1022 if ((tps65910_chip_id(mfd) == TPS65910) && 1017 if ((tps65910_chip_id(mfd) == TPS65910) &&
1023 (id >= TPS65910_REG_VDIG1)) { 1018 (id >= TPS65910_REG_VDIG1)) {
1024 if (ext_sleep_config & TPS65910_SLEEP_CONTROL_EXT_INPUT_EN3) 1019 if (ext_sleep_config & TPS65910_SLEEP_CONTROL_EXT_INPUT_EN3)
1025 ret = tps65910_set_bits(mfd, 1020 ret = tps65910_reg_set_bits(mfd,
1026 TPS65910_EN3_LDO_ASS + regoffs, bit_pos); 1021 TPS65910_EN3_LDO_ASS + regoffs, bit_pos);
1027 else 1022 else
1028 ret = tps65910_clear_bits(mfd, 1023 ret = tps65910_reg_clear_bits(mfd,
1029 TPS65910_EN3_LDO_ASS + regoffs, bit_pos); 1024 TPS65910_EN3_LDO_ASS + regoffs, bit_pos);
1030 if (ret < 0) { 1025 if (ret < 0) {
1031 dev_err(mfd->dev, 1026 dev_err(mfd->dev,
@@ -1037,10 +1032,10 @@ static int tps65910_set_ext_sleep_config(struct tps65910_reg *pmic,
1037 /* Return if no external control is selected */ 1032 /* Return if no external control is selected */
1038 if (!(ext_sleep_config & EXT_SLEEP_CONTROL)) { 1033 if (!(ext_sleep_config & EXT_SLEEP_CONTROL)) {
1039 /* Clear all sleep controls */ 1034 /* Clear all sleep controls */
1040 ret = tps65910_clear_bits(mfd, 1035 ret = tps65910_reg_clear_bits(mfd,
1041 TPS65910_SLEEP_KEEP_LDO_ON + regoffs, bit_pos); 1036 TPS65910_SLEEP_KEEP_LDO_ON + regoffs, bit_pos);
1042 if (!ret) 1037 if (!ret)
1043 ret = tps65910_clear_bits(mfd, 1038 ret = tps65910_reg_clear_bits(mfd,
1044 TPS65910_SLEEP_SET_LDO_OFF + regoffs, bit_pos); 1039 TPS65910_SLEEP_SET_LDO_OFF + regoffs, bit_pos);
1045 if (ret < 0) 1040 if (ret < 0)
1046 dev_err(mfd->dev, 1041 dev_err(mfd->dev,
@@ -1059,32 +1054,33 @@ static int tps65910_set_ext_sleep_config(struct tps65910_reg *pmic,
1059 (tps65910_chip_id(mfd) == TPS65911))) { 1054 (tps65910_chip_id(mfd) == TPS65911))) {
1060 int op_reg_add = pmic->get_ctrl_reg(id) + 1; 1055 int op_reg_add = pmic->get_ctrl_reg(id) + 1;
1061 int sr_reg_add = pmic->get_ctrl_reg(id) + 2; 1056 int sr_reg_add = pmic->get_ctrl_reg(id) + 2;
1062 int opvsel = tps65910_reg_read(pmic, op_reg_add); 1057 int opvsel = tps65910_reg_read_locked(pmic, op_reg_add);
1063 int srvsel = tps65910_reg_read(pmic, sr_reg_add); 1058 int srvsel = tps65910_reg_read_locked(pmic, sr_reg_add);
1064 if (opvsel & VDD1_OP_CMD_MASK) { 1059 if (opvsel & VDD1_OP_CMD_MASK) {
1065 u8 reg_val = srvsel & VDD1_OP_SEL_MASK; 1060 u8 reg_val = srvsel & VDD1_OP_SEL_MASK;
1066 ret = tps65910_reg_write(pmic, op_reg_add, reg_val); 1061 ret = tps65910_reg_write_locked(pmic, op_reg_add,
1062 reg_val);
1067 if (ret < 0) { 1063 if (ret < 0) {
1068 dev_err(mfd->dev, 1064 dev_err(mfd->dev,
1069 "Error in configuring op register\n"); 1065 "Error in configuring op register\n");
1070 return ret; 1066 return ret;
1071 } 1067 }
1072 } 1068 }
1073 ret = tps65910_reg_write(pmic, sr_reg_add, 0); 1069 ret = tps65910_reg_write_locked(pmic, sr_reg_add, 0);
1074 if (ret < 0) { 1070 if (ret < 0) {
1075 dev_err(mfd->dev, "Error in settting sr register\n"); 1071 dev_err(mfd->dev, "Error in settting sr register\n");
1076 return ret; 1072 return ret;
1077 } 1073 }
1078 } 1074 }
1079 1075
1080 ret = tps65910_clear_bits(mfd, 1076 ret = tps65910_reg_clear_bits(mfd,
1081 TPS65910_SLEEP_KEEP_LDO_ON + regoffs, bit_pos); 1077 TPS65910_SLEEP_KEEP_LDO_ON + regoffs, bit_pos);
1082 if (!ret) { 1078 if (!ret) {
1083 if (ext_sleep_config & TPS65911_SLEEP_CONTROL_EXT_INPUT_SLEEP) 1079 if (ext_sleep_config & TPS65911_SLEEP_CONTROL_EXT_INPUT_SLEEP)
1084 ret = tps65910_set_bits(mfd, 1080 ret = tps65910_reg_set_bits(mfd,
1085 TPS65910_SLEEP_SET_LDO_OFF + regoffs, bit_pos); 1081 TPS65910_SLEEP_SET_LDO_OFF + regoffs, bit_pos);
1086 else 1082 else
1087 ret = tps65910_clear_bits(mfd, 1083 ret = tps65910_reg_clear_bits(mfd,
1088 TPS65910_SLEEP_SET_LDO_OFF + regoffs, bit_pos); 1084 TPS65910_SLEEP_SET_LDO_OFF + regoffs, bit_pos);
1089 } 1085 }
1090 if (ret < 0) 1086 if (ret < 0)
@@ -1117,7 +1113,7 @@ static __devinit int tps65910_probe(struct platform_device *pdev)
1117 platform_set_drvdata(pdev, pmic); 1113 platform_set_drvdata(pdev, pmic);
1118 1114
1119 /* Give control of all register to control port */ 1115 /* Give control of all register to control port */
1120 tps65910_set_bits(pmic->mfd, TPS65910_DEVCTRL, 1116 tps65910_reg_set_bits(pmic->mfd, TPS65910_DEVCTRL,
1121 DEVCTRL_SR_CTL_I2C_SEL_MASK); 1117 DEVCTRL_SR_CTL_I2C_SEL_MASK);
1122 1118
1123 switch(tps65910_chip_id(tps65910)) { 1119 switch(tps65910_chip_id(tps65910)) {