diff options
author | James Ban <james.ban.opensource@diasemi.com> | 2014-07-14 00:48:45 -0400 |
---|---|---|
committer | Mark Brown <broonie@linaro.org> | 2014-07-14 14:15:56 -0400 |
commit | 1028a37daa148cc6cf85aa2aecb4390ddf1e1e56 (patch) | |
tree | dad06ff63e36beb40ee54e7a46f7671a823913cc /drivers/regulator/da9211-regulator.h | |
parent | 7171511eaec5bf23fb06078f59784a3a0626b38f (diff) |
regulator: da9211: new regulator driver
This is the driver for the Dialog DA9211 Multi-phase 12A DC-DC Buck
Converter regulator. It communicates via an I2C bus to the device.
Signed-off-by: James Ban <james.ban.opensource@diasemi.com>
Signed-off-by: Mark Brown <broonie@linaro.org>
Diffstat (limited to 'drivers/regulator/da9211-regulator.h')
-rw-r--r-- | drivers/regulator/da9211-regulator.h | 271 |
1 files changed, 271 insertions, 0 deletions
diff --git a/drivers/regulator/da9211-regulator.h b/drivers/regulator/da9211-regulator.h new file mode 100644 index 000000000000..88b1769e8058 --- /dev/null +++ b/drivers/regulator/da9211-regulator.h | |||
@@ -0,0 +1,271 @@ | |||
1 | /* | ||
2 | * da9211-regulator.h - Regulator definitions for DA9211 | ||
3 | * Copyright (C) 2014 Dialog Semiconductor Ltd. | ||
4 | * | ||
5 | * This library is free software; you can redistribute it and/or | ||
6 | * modify it under the terms of the GNU Library General Public | ||
7 | * License as published by the Free Software Foundation; either | ||
8 | * version 2 of the License, or (at your option) any later version. | ||
9 | * | ||
10 | * This library is distributed in the hope that it will be useful, | ||
11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | ||
13 | * Library General Public License for more details. | ||
14 | */ | ||
15 | |||
16 | #ifndef __DA9211_REGISTERS_H__ | ||
17 | #define __DA9211_REGISTERS_H__ | ||
18 | |||
19 | /* Page selection */ | ||
20 | #define DA9211_REG_PAGE_CON 0x00 | ||
21 | |||
22 | /* System Control and Event Registers */ | ||
23 | #define DA9211_REG_STATUS_A 0x50 | ||
24 | #define DA9211_REG_STATUS_B 0x51 | ||
25 | #define DA9211_REG_EVENT_A 0x52 | ||
26 | #define DA9211_REG_EVENT_B 0x53 | ||
27 | #define DA9211_REG_MASK_A 0x54 | ||
28 | #define DA9211_REG_MASK_B 0x55 | ||
29 | #define DA9211_REG_CONTROL_A 0x56 | ||
30 | |||
31 | /* GPIO Control Registers */ | ||
32 | #define DA9211_REG_GPIO_0_1 0x58 | ||
33 | #define DA9211_REG_GPIO_2_3 0x59 | ||
34 | #define DA9211_REG_GPIO_4 0x5A | ||
35 | |||
36 | /* Regulator Registers */ | ||
37 | #define DA9211_REG_BUCKA_CONT 0x5D | ||
38 | #define DA9211_REG_BUCKB_CONT 0x5E | ||
39 | #define DA9211_REG_BUCK_ILIM 0xD0 | ||
40 | #define DA9211_REG_BUCKA_CONF 0xD1 | ||
41 | #define DA9211_REG_BUCKB_CONF 0xD2 | ||
42 | #define DA9211_REG_BUCK_CONF 0xD3 | ||
43 | #define DA9211_REG_VBACKA_MAX 0xD5 | ||
44 | #define DA9211_REG_VBACKB_MAX 0xD6 | ||
45 | #define DA9211_REG_VBUCKA_A 0xD7 | ||
46 | #define DA9211_REG_VBUCKA_B 0xD8 | ||
47 | #define DA9211_REG_VBUCKB_A 0xD9 | ||
48 | #define DA9211_REG_VBUCKB_B 0xDA | ||
49 | |||
50 | /* I2C Interface Settings */ | ||
51 | #define DA9211_REG_INTERFACE 0x105 | ||
52 | |||
53 | /* BUCK Phase Selection*/ | ||
54 | #define DA9211_REG_CONFIG_E 0x147 | ||
55 | |||
56 | /* | ||
57 | * Registers bits | ||
58 | */ | ||
59 | /* DA9211_REG_PAGE_CON (addr=0x00) */ | ||
60 | #define DA9211_REG_PAGE_SHIFT 1 | ||
61 | #define DA9211_REG_PAGE_MASK 0x02 | ||
62 | /* On I2C registers 0x00 - 0xFF */ | ||
63 | #define DA9211_REG_PAGE0 0 | ||
64 | /* On I2C registers 0x100 - 0x1FF */ | ||
65 | #define DA9211_REG_PAGE2 2 | ||
66 | #define DA9211_PAGE_WRITE_MODE 0x00 | ||
67 | #define DA9211_REPEAT_WRITE_MODE 0x40 | ||
68 | #define DA9211_PAGE_REVERT 0x80 | ||
69 | |||
70 | /* DA9211_REG_STATUS_A (addr=0x50) */ | ||
71 | #define DA9211_GPI0 0x01 | ||
72 | #define DA9211_GPI1 0x02 | ||
73 | #define DA9211_GPI2 0x04 | ||
74 | #define DA9211_GPI3 0x08 | ||
75 | #define DA9211_GPI4 0x10 | ||
76 | |||
77 | /* DA9211_REG_EVENT_A (addr=0x52) */ | ||
78 | #define DA9211_E_GPI0 0x01 | ||
79 | #define DA9211_E_GPI1 0x02 | ||
80 | #define DA9211_E_GPI2 0x04 | ||
81 | #define DA9211_E_GPI3 0x08 | ||
82 | #define DA9211_E_GPI4 0x10 | ||
83 | #define DA9211_E_UVLO_IO 0x40 | ||
84 | |||
85 | /* DA9211_REG_EVENT_B (addr=0x53) */ | ||
86 | #define DA9211_E_PWRGOOD_A 0x01 | ||
87 | #define DA9211_E_PWRGOOD_B 0x02 | ||
88 | #define DA9211_E_TEMP_WARN 0x04 | ||
89 | #define DA9211_E_TEMP_CRIT 0x08 | ||
90 | #define DA9211_E_OV_CURR_A 0x10 | ||
91 | #define DA9211_E_OV_CURR_B 0x20 | ||
92 | |||
93 | /* DA9211_REG_MASK_A (addr=0x54) */ | ||
94 | #define DA9211_M_GPI0 0x01 | ||
95 | #define DA9211_M_GPI1 0x02 | ||
96 | #define DA9211_M_GPI2 0x04 | ||
97 | #define DA9211_M_GPI3 0x08 | ||
98 | #define DA9211_M_GPI4 0x10 | ||
99 | #define DA9211_M_UVLO_IO 0x40 | ||
100 | |||
101 | /* DA9211_REG_MASK_B (addr=0x55) */ | ||
102 | #define DA9211_M_PWRGOOD_A 0x01 | ||
103 | #define DA9211_M_PWRGOOD_B 0x02 | ||
104 | #define DA9211_M_TEMP_WARN 0x04 | ||
105 | #define DA9211_M_TEMP_CRIT 0x08 | ||
106 | #define DA9211_M_OV_CURR_A 0x10 | ||
107 | #define DA9211_M_OV_CURR_B 0x20 | ||
108 | |||
109 | /* DA9211_REG_CONTROL_A (addr=0x56) */ | ||
110 | #define DA9211_DEBOUNCING_SHIFT 0 | ||
111 | #define DA9211_DEBOUNCING_MASK 0x07 | ||
112 | #define DA9211_SLEW_RATE_SHIFT 3 | ||
113 | #define DA9211_SLEW_RATE_A_MASK 0x18 | ||
114 | #define DA9211_SLEW_RATE_B_SHIFT 5 | ||
115 | #define DA9211_SLEW_RATE_B_MASK 0x60 | ||
116 | #define DA9211_V_LOCK 0x80 | ||
117 | |||
118 | /* DA9211_REG_GPIO_0_1 (addr=0x58) */ | ||
119 | #define DA9211_GPIO0_PIN_SHIFT 0 | ||
120 | #define DA9211_GPIO0_PIN_MASK 0x03 | ||
121 | #define DA9211_GPIO0_PIN_GPI 0x00 | ||
122 | #define DA9211_GPIO0_PIN_GPO_OD 0x02 | ||
123 | #define DA9211_GPIO0_PIN_GPO 0x03 | ||
124 | #define DA9211_GPIO0_TYPE 0x04 | ||
125 | #define DA9211_GPIO0_TYPE_GPI 0x00 | ||
126 | #define DA9211_GPIO0_TYPE_GPO 0x04 | ||
127 | #define DA9211_GPIO0_MODE 0x08 | ||
128 | #define DA9211_GPIO1_PIN_SHIFT 4 | ||
129 | #define DA9211_GPIO1_PIN_MASK 0x30 | ||
130 | #define DA9211_GPIO1_PIN_GPI 0x00 | ||
131 | #define DA9211_GPIO1_PIN_VERROR 0x10 | ||
132 | #define DA9211_GPIO1_PIN_GPO_OD 0x20 | ||
133 | #define DA9211_GPIO1_PIN_GPO 0x30 | ||
134 | #define DA9211_GPIO1_TYPE_SHIFT 0x40 | ||
135 | #define DA9211_GPIO1_TYPE_GPI 0x00 | ||
136 | #define DA9211_GPIO1_TYPE_GPO 0x40 | ||
137 | #define DA9211_GPIO1_MODE 0x80 | ||
138 | |||
139 | /* DA9211_REG_GPIO_2_3 (addr=0x59) */ | ||
140 | #define DA9211_GPIO2_PIN_SHIFT 0 | ||
141 | #define DA9211_GPIO2_PIN_MASK 0x03 | ||
142 | #define DA9211_GPIO2_PIN_GPI 0x00 | ||
143 | #define DA9211_GPIO5_PIN_BUCK_CLK 0x10 | ||
144 | #define DA9211_GPIO2_PIN_GPO_OD 0x02 | ||
145 | #define DA9211_GPIO2_PIN_GPO 0x03 | ||
146 | #define DA9211_GPIO2_TYPE 0x04 | ||
147 | #define DA9211_GPIO2_TYPE_GPI 0x00 | ||
148 | #define DA9211_GPIO2_TYPE_GPO 0x04 | ||
149 | #define DA9211_GPIO2_MODE 0x08 | ||
150 | #define DA9211_GPIO3_PIN_SHIFT 4 | ||
151 | #define DA9211_GPIO3_PIN_MASK 0x30 | ||
152 | #define DA9211_GPIO3_PIN_GPI 0x00 | ||
153 | #define DA9211_GPIO3_PIN_IERROR 0x10 | ||
154 | #define DA9211_GPIO3_PIN_GPO_OD 0x20 | ||
155 | #define DA9211_GPIO3_PIN_GPO 0x30 | ||
156 | #define DA9211_GPIO3_TYPE_SHIFT 0x40 | ||
157 | #define DA9211_GPIO3_TYPE_GPI 0x00 | ||
158 | #define DA9211_GPIO3_TYPE_GPO 0x40 | ||
159 | #define DA9211_GPIO3_MODE 0x80 | ||
160 | |||
161 | /* DA9211_REG_GPIO_4 (addr=0x5A) */ | ||
162 | #define DA9211_GPIO4_PIN_SHIFT 0 | ||
163 | #define DA9211_GPIO4_PIN_MASK 0x03 | ||
164 | #define DA9211_GPIO4_PIN_GPI 0x00 | ||
165 | #define DA9211_GPIO4_PIN_GPO_OD 0x02 | ||
166 | #define DA9211_GPIO4_PIN_GPO 0x03 | ||
167 | #define DA9211_GPIO4_TYPE 0x04 | ||
168 | #define DA9211_GPIO4_TYPE_GPI 0x00 | ||
169 | #define DA9211_GPIO4_TYPE_GPO 0x04 | ||
170 | #define DA9211_GPIO4_MODE 0x08 | ||
171 | |||
172 | /* DA9211_REG_BUCKA_CONT (addr=0x5D) */ | ||
173 | #define DA9211_BUCKA_EN 0x01 | ||
174 | #define DA9211_BUCKA_GPI_SHIFT 1 | ||
175 | #define DA9211_BUCKA_GPI_MASK 0x06 | ||
176 | #define DA9211_BUCKA_GPI_OFF 0x00 | ||
177 | #define DA9211_BUCKA_GPI_GPIO0 0x02 | ||
178 | #define DA9211_BUCKA_GPI_GPIO1 0x04 | ||
179 | #define DA9211_BUCKA_GPI_GPIO3 0x06 | ||
180 | #define DA9211_BUCKA_PD_DIS 0x08 | ||
181 | #define DA9211_VBUCKA_SEL 0x10 | ||
182 | #define DA9211_VBUCKA_SEL_A 0x00 | ||
183 | #define DA9211_VBUCKA_SEL_B 0x10 | ||
184 | #define DA9211_VBUCKA_GPI_SHIFT 5 | ||
185 | #define DA9211_VBUCKA_GPI_MASK 0x60 | ||
186 | #define DA9211_VBUCKA_GPI_OFF 0x00 | ||
187 | #define DA9211_VBUCKA_GPI_GPIO1 0x20 | ||
188 | #define DA9211_VBUCKA_GPI_GPIO2 0x40 | ||
189 | #define DA9211_VBUCKA_GPI_GPIO4 0x60 | ||
190 | |||
191 | /* DA9211_REG_BUCKB_CONT (addr=0x5E) */ | ||
192 | #define DA9211_BUCKB_EN 0x01 | ||
193 | #define DA9211_BUCKB_GPI_SHIFT 1 | ||
194 | #define DA9211_BUCKB_GPI_MASK 0x06 | ||
195 | #define DA9211_BUCKB_GPI_OFF 0x00 | ||
196 | #define DA9211_BUCKB_GPI_GPIO0 0x02 | ||
197 | #define DA9211_BUCKB_GPI_GPIO1 0x04 | ||
198 | #define DA9211_BUCKB_GPI_GPIO3 0x06 | ||
199 | #define DA9211_BUCKB_PD_DIS 0x08 | ||
200 | #define DA9211_VBUCKB_SEL 0x10 | ||
201 | #define DA9211_VBUCKB_SEL_A 0x00 | ||
202 | #define DA9211_VBUCKB_SEL_B 0x10 | ||
203 | #define DA9211_VBUCKB_GPI_SHIFT 5 | ||
204 | #define DA9211_VBUCKB_GPI_MASK 0x60 | ||
205 | #define DA9211_VBUCKB_GPI_OFF 0x00 | ||
206 | #define DA9211_VBUCKB_GPI_GPIO1 0x20 | ||
207 | #define DA9211_VBUCKB_GPI_GPIO2 0x40 | ||
208 | #define DA9211_VBUCKB_GPI_GPIO4 0x60 | ||
209 | |||
210 | /* DA9211_REG_BUCK_ILIM (addr=0xD0) */ | ||
211 | #define DA9211_BUCKA_ILIM_SHIFT 0 | ||
212 | #define DA9211_BUCKA_ILIM_MASK 0x0F | ||
213 | #define DA9211_BUCKB_ILIM_SHIFT 4 | ||
214 | #define DA9211_BUCKB_ILIM_MASK 0xF0 | ||
215 | |||
216 | /* DA9211_REG_BUCKA_CONF (addr=0xD1) */ | ||
217 | #define DA9211_BUCKA_MODE_SHIFT 0 | ||
218 | #define DA9211_BUCKA_MODE_MASK 0x03 | ||
219 | #define DA9211_BUCKA_MODE_MANUAL 0x00 | ||
220 | #define DA9211_BUCKA_MODE_SLEEP 0x01 | ||
221 | #define DA9211_BUCKA_MODE_SYNC 0x02 | ||
222 | #define DA9211_BUCKA_MODE_AUTO 0x03 | ||
223 | #define DA9211_BUCKA_UP_CTRL_SHIFT 2 | ||
224 | #define DA9211_BUCKA_UP_CTRL_MASK 0x1C | ||
225 | #define DA9211_BUCKA_DOWN_CTRL_SHIFT 5 | ||
226 | #define DA9211_BUCKA_DOWN_CTRL_MASK 0xE0 | ||
227 | |||
228 | /* DA9211_REG_BUCKB_CONF (addr=0xD2) */ | ||
229 | #define DA9211_BUCKB_MODE_SHIFT 0 | ||
230 | #define DA9211_BUCKB_MODE_MASK 0x03 | ||
231 | #define DA9211_BUCKB_MODE_MANUAL 0x00 | ||
232 | #define DA9211_BUCKB_MODE_SLEEP 0x01 | ||
233 | #define DA9211_BUCKB_MODE_SYNC 0x02 | ||
234 | #define DA9211_BUCKB_MODE_AUTO 0x03 | ||
235 | #define DA9211_BUCKB_UP_CTRL_SHIFT 2 | ||
236 | #define DA9211_BUCKB_UP_CTRL_MASK 0x1C | ||
237 | #define DA9211_BUCKB_DOWN_CTRL_SHIFT 5 | ||
238 | #define DA9211_BUCKB_DOWN_CTRL_MASK 0xE0 | ||
239 | |||
240 | /* DA9211_REG_BUCK_CONF (addr=0xD3) */ | ||
241 | #define DA9211_PHASE_SEL_A_SHIFT 0 | ||
242 | #define DA9211_PHASE_SEL_A_MASK 0x03 | ||
243 | #define DA9211_PHASE_SEL_B_SHIFT 2 | ||
244 | #define DA9211_PHASE_SEL_B_MASK 0x04 | ||
245 | #define DA9211_PH_SH_EN_A_SHIFT 3 | ||
246 | #define DA9211_PH_SH_EN_A_MASK 0x08 | ||
247 | #define DA9211_PH_SH_EN_B_SHIFT 4 | ||
248 | #define DA9211_PH_SH_EN_B_MASK 0x10 | ||
249 | |||
250 | /* DA9211_REG_VBUCKA_MAX (addr=0xD5) */ | ||
251 | #define DA9211_VBUCKA_BASE_SHIFT 0 | ||
252 | #define DA9211_VBUCKA_BASE_MASK 0x7F | ||
253 | |||
254 | /* DA9211_REG_VBUCKB_MAX (addr=0xD6) */ | ||
255 | #define DA9211_VBUCKB_BASE_SHIFT 0 | ||
256 | #define DA9211_VBUCKB_BASE_MASK 0x7F | ||
257 | |||
258 | /* DA9211_REG_VBUCKA/B_A/B (addr=0xD7/0xD8/0xD9/0xDA) */ | ||
259 | #define DA9211_VBUCK_SHIFT 0 | ||
260 | #define DA9211_VBUCK_MASK 0x7F | ||
261 | #define DA9211_VBUCK_BIAS 0 | ||
262 | #define DA9211_BUCK_SL 0x80 | ||
263 | |||
264 | /* DA9211_REG_INTERFACE (addr=0x105) */ | ||
265 | #define DA9211_IF_BASE_ADDR_SHIFT 4 | ||
266 | #define DA9211_IF_BASE_ADDR_MASK 0xF0 | ||
267 | |||
268 | /* DA9211_REG_CONFIG_E (addr=0x147) */ | ||
269 | #define DA9211_SLAVE_SEL 0x40 | ||
270 | |||
271 | #endif /* __DA9211_REGISTERS_H__ */ | ||