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authorLinus Walleij <linus.walleij@linaro.org>2013-11-04 07:02:37 -0500
committerLinus Walleij <linus.walleij@linaro.org>2013-11-04 07:02:37 -0500
commitde91a3789d8ea2ba7a677c6355b703ded59751ad (patch)
treedd9e992cf0508d783d20fc30b58218a875468f07 /drivers/pinctrl
parent5e1109adde6acd0f3424886da09402ac22ed244b (diff)
parent5088451962389924b9f05e22e6956f5c1a515d1a (diff)
Merge branch 'pinmux/next/pfc' of git://linuxtv.org/pinchartl/fbdev into devel
Diffstat (limited to 'drivers/pinctrl')
-rw-r--r--drivers/pinctrl/sh-pfc/Kconfig5
-rw-r--r--drivers/pinctrl/sh-pfc/Makefile1
-rw-r--r--drivers/pinctrl/sh-pfc/core.c9
-rw-r--r--drivers/pinctrl/sh-pfc/core.h1
-rw-r--r--drivers/pinctrl/sh-pfc/pfc-r8a7778.c55
-rw-r--r--drivers/pinctrl/sh-pfc/pfc-r8a7791.c4214
6 files changed, 4285 insertions, 0 deletions
diff --git a/drivers/pinctrl/sh-pfc/Kconfig b/drivers/pinctrl/sh-pfc/Kconfig
index 636a882b406e..26187aa5cf5b 100644
--- a/drivers/pinctrl/sh-pfc/Kconfig
+++ b/drivers/pinctrl/sh-pfc/Kconfig
@@ -45,6 +45,11 @@ config PINCTRL_PFC_R8A7790
45 depends on ARCH_R8A7790 45 depends on ARCH_R8A7790
46 select PINCTRL_SH_PFC 46 select PINCTRL_SH_PFC
47 47
48config PINCTRL_PFC_R8A7791
49 def_bool y
50 depends on ARCH_R8A7791
51 select PINCTRL_SH_PFC
52
48config PINCTRL_PFC_SH7203 53config PINCTRL_PFC_SH7203
49 def_bool y 54 def_bool y
50 depends on CPU_SUBTYPE_SH7203 55 depends on CPU_SUBTYPE_SH7203
diff --git a/drivers/pinctrl/sh-pfc/Makefile b/drivers/pinctrl/sh-pfc/Makefile
index 5e0c222c12d7..ad8f4cf9faaa 100644
--- a/drivers/pinctrl/sh-pfc/Makefile
+++ b/drivers/pinctrl/sh-pfc/Makefile
@@ -8,6 +8,7 @@ obj-$(CONFIG_PINCTRL_PFC_R8A7740) += pfc-r8a7740.o
8obj-$(CONFIG_PINCTRL_PFC_R8A7778) += pfc-r8a7778.o 8obj-$(CONFIG_PINCTRL_PFC_R8A7778) += pfc-r8a7778.o
9obj-$(CONFIG_PINCTRL_PFC_R8A7779) += pfc-r8a7779.o 9obj-$(CONFIG_PINCTRL_PFC_R8A7779) += pfc-r8a7779.o
10obj-$(CONFIG_PINCTRL_PFC_R8A7790) += pfc-r8a7790.o 10obj-$(CONFIG_PINCTRL_PFC_R8A7790) += pfc-r8a7790.o
11obj-$(CONFIG_PINCTRL_PFC_R8A7791) += pfc-r8a7791.o
11obj-$(CONFIG_PINCTRL_PFC_SH7203) += pfc-sh7203.o 12obj-$(CONFIG_PINCTRL_PFC_SH7203) += pfc-sh7203.o
12obj-$(CONFIG_PINCTRL_PFC_SH7264) += pfc-sh7264.o 13obj-$(CONFIG_PINCTRL_PFC_SH7264) += pfc-sh7264.o
13obj-$(CONFIG_PINCTRL_PFC_SH7269) += pfc-sh7269.o 14obj-$(CONFIG_PINCTRL_PFC_SH7269) += pfc-sh7269.o
diff --git a/drivers/pinctrl/sh-pfc/core.c b/drivers/pinctrl/sh-pfc/core.c
index 738f14f65cff..d77ece5217f0 100644
--- a/drivers/pinctrl/sh-pfc/core.c
+++ b/drivers/pinctrl/sh-pfc/core.c
@@ -431,6 +431,12 @@ static const struct of_device_id sh_pfc_of_table[] = {
431 .data = &r8a7790_pinmux_info, 431 .data = &r8a7790_pinmux_info,
432 }, 432 },
433#endif 433#endif
434#ifdef CONFIG_PINCTRL_PFC_R8A7791
435 {
436 .compatible = "renesas,pfc-r8a7791",
437 .data = &r8a7791_pinmux_info,
438 },
439#endif
434#ifdef CONFIG_PINCTRL_PFC_SH7372 440#ifdef CONFIG_PINCTRL_PFC_SH7372
435 { 441 {
436 .compatible = "renesas,pfc-sh7372", 442 .compatible = "renesas,pfc-sh7372",
@@ -558,6 +564,9 @@ static const struct platform_device_id sh_pfc_id_table[] = {
558#ifdef CONFIG_PINCTRL_PFC_R8A7790 564#ifdef CONFIG_PINCTRL_PFC_R8A7790
559 { "pfc-r8a7790", (kernel_ulong_t)&r8a7790_pinmux_info }, 565 { "pfc-r8a7790", (kernel_ulong_t)&r8a7790_pinmux_info },
560#endif 566#endif
567#ifdef CONFIG_PINCTRL_PFC_R8A7791
568 { "pfc-r8a7791", (kernel_ulong_t)&r8a7791_pinmux_info },
569#endif
561#ifdef CONFIG_PINCTRL_PFC_SH7203 570#ifdef CONFIG_PINCTRL_PFC_SH7203
562 { "pfc-sh7203", (kernel_ulong_t)&sh7203_pinmux_info }, 571 { "pfc-sh7203", (kernel_ulong_t)&sh7203_pinmux_info },
563#endif 572#endif
diff --git a/drivers/pinctrl/sh-pfc/core.h b/drivers/pinctrl/sh-pfc/core.h
index a1b23762ac90..11ea87268658 100644
--- a/drivers/pinctrl/sh-pfc/core.h
+++ b/drivers/pinctrl/sh-pfc/core.h
@@ -69,6 +69,7 @@ extern const struct sh_pfc_soc_info r8a7740_pinmux_info;
69extern const struct sh_pfc_soc_info r8a7778_pinmux_info; 69extern const struct sh_pfc_soc_info r8a7778_pinmux_info;
70extern const struct sh_pfc_soc_info r8a7779_pinmux_info; 70extern const struct sh_pfc_soc_info r8a7779_pinmux_info;
71extern const struct sh_pfc_soc_info r8a7790_pinmux_info; 71extern const struct sh_pfc_soc_info r8a7790_pinmux_info;
72extern const struct sh_pfc_soc_info r8a7791_pinmux_info;
72extern const struct sh_pfc_soc_info sh7203_pinmux_info; 73extern const struct sh_pfc_soc_info sh7203_pinmux_info;
73extern const struct sh_pfc_soc_info sh7264_pinmux_info; 74extern const struct sh_pfc_soc_info sh7264_pinmux_info;
74extern const struct sh_pfc_soc_info sh7269_pinmux_info; 75extern const struct sh_pfc_soc_info sh7269_pinmux_info;
diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7778.c b/drivers/pinctrl/sh-pfc/pfc-r8a7778.c
index 20b1d0d671a3..8b1881c20598 100644
--- a/drivers/pinctrl/sh-pfc/pfc-r8a7778.c
+++ b/drivers/pinctrl/sh-pfc/pfc-r8a7778.c
@@ -1304,6 +1304,33 @@ AUDIO_PFC_DAT(audio_clkout_a, AUDIO_CLKOUT_A);
1304AUDIO_PFC_PIN(audio_clkout_b, RCAR_GP_PIN(1, 16)); 1304AUDIO_PFC_PIN(audio_clkout_b, RCAR_GP_PIN(1, 16));
1305AUDIO_PFC_DAT(audio_clkout_b, AUDIO_CLKOUT_B); 1305AUDIO_PFC_DAT(audio_clkout_b, AUDIO_CLKOUT_B);
1306 1306
1307/* - CAN macro --------_----------------------------------------------------- */
1308#define CAN_PFC_PINS(name, args...) SH_PFC_PINS(name, args)
1309#define CAN_PFC_DATA(name, tx, rx) SH_PFC_MUX2(name, tx, rx)
1310#define CAN_PFC_CLK(name, clk) SH_PFC_MUX1(name, clk)
1311
1312/* - CAN0 ------------------------------------------------------------------- */
1313CAN_PFC_PINS(can0_data_a, RCAR_GP_PIN(1, 30), RCAR_GP_PIN(1, 31));
1314CAN_PFC_DATA(can0_data_a, CAN0_TX_A, CAN0_RX_A);
1315CAN_PFC_PINS(can0_data_b, RCAR_GP_PIN(2, 26), RCAR_GP_PIN(2, 27));
1316CAN_PFC_DATA(can0_data_b, CAN0_TX_B, CAN0_RX_B);
1317
1318/* - CAN1 ------------------------------------------------------------------- */
1319CAN_PFC_PINS(can1_data_a, RCAR_GP_PIN(4, 20), RCAR_GP_PIN(4, 19));
1320CAN_PFC_DATA(can1_data_a, CAN1_TX_A, CAN1_RX_A);
1321CAN_PFC_PINS(can1_data_b, RCAR_GP_PIN(2, 28), RCAR_GP_PIN(2, 29));
1322CAN_PFC_DATA(can1_data_b, CAN1_TX_B, CAN1_RX_B);
1323
1324/* - CAN_CLK --------------------------------------------------------------- */
1325CAN_PFC_PINS(can_clk_a, RCAR_GP_PIN(3, 24));
1326CAN_PFC_CLK(can_clk_a, CAN_CLK_A);
1327CAN_PFC_PINS(can_clk_b, RCAR_GP_PIN(1, 16));
1328CAN_PFC_CLK(can_clk_b, CAN_CLK_B);
1329CAN_PFC_PINS(can_clk_c, RCAR_GP_PIN(4, 24));
1330CAN_PFC_CLK(can_clk_c, CAN_CLK_C);
1331CAN_PFC_PINS(can_clk_d, RCAR_GP_PIN(2, 25));
1332CAN_PFC_CLK(can_clk_d, CAN_CLK_D);
1333
1307/* - Ether ------------------------------------------------------------------ */ 1334/* - Ether ------------------------------------------------------------------ */
1308SH_PFC_PINS(ether_rmii, RCAR_GP_PIN(4, 10), RCAR_GP_PIN(4, 11), 1335SH_PFC_PINS(ether_rmii, RCAR_GP_PIN(4, 10), RCAR_GP_PIN(4, 11),
1309 RCAR_GP_PIN(4, 13), RCAR_GP_PIN(4, 9), 1336 RCAR_GP_PIN(4, 13), RCAR_GP_PIN(4, 9),
@@ -1698,6 +1725,14 @@ static const struct sh_pfc_pin_group pinmux_groups[] = {
1698 SH_PFC_PIN_GROUP(audio_clk_c), 1725 SH_PFC_PIN_GROUP(audio_clk_c),
1699 SH_PFC_PIN_GROUP(audio_clkout_a), 1726 SH_PFC_PIN_GROUP(audio_clkout_a),
1700 SH_PFC_PIN_GROUP(audio_clkout_b), 1727 SH_PFC_PIN_GROUP(audio_clkout_b),
1728 SH_PFC_PIN_GROUP(can0_data_a),
1729 SH_PFC_PIN_GROUP(can0_data_b),
1730 SH_PFC_PIN_GROUP(can1_data_a),
1731 SH_PFC_PIN_GROUP(can1_data_b),
1732 SH_PFC_PIN_GROUP(can_clk_a),
1733 SH_PFC_PIN_GROUP(can_clk_b),
1734 SH_PFC_PIN_GROUP(can_clk_c),
1735 SH_PFC_PIN_GROUP(can_clk_d),
1701 SH_PFC_PIN_GROUP(ether_rmii), 1736 SH_PFC_PIN_GROUP(ether_rmii),
1702 SH_PFC_PIN_GROUP(ether_link), 1737 SH_PFC_PIN_GROUP(ether_link),
1703 SH_PFC_PIN_GROUP(ether_magic), 1738 SH_PFC_PIN_GROUP(ether_magic),
@@ -1826,6 +1861,24 @@ static const char * const audio_clk_groups[] = {
1826 "audio_clkout_b", 1861 "audio_clkout_b",
1827}; 1862};
1828 1863
1864static const char * const can0_groups[] = {
1865 "can0_data_a",
1866 "can0_data_b",
1867 "can_clk_a",
1868 "can_clk_b",
1869 "can_clk_c",
1870 "can_clk_d",
1871};
1872
1873static const char * const can1_groups[] = {
1874 "can1_data_a",
1875 "can1_data_b",
1876 "can_clk_a",
1877 "can_clk_b",
1878 "can_clk_c",
1879 "can_clk_d",
1880};
1881
1829static const char * const ether_groups[] = { 1882static const char * const ether_groups[] = {
1830 "ether_rmii", 1883 "ether_rmii",
1831 "ether_link", 1884 "ether_link",
@@ -2022,6 +2075,8 @@ static const char * const vin1_groups[] = {
2022 2075
2023static const struct sh_pfc_function pinmux_functions[] = { 2076static const struct sh_pfc_function pinmux_functions[] = {
2024 SH_PFC_FUNCTION(audio_clk), 2077 SH_PFC_FUNCTION(audio_clk),
2078 SH_PFC_FUNCTION(can0),
2079 SH_PFC_FUNCTION(can1),
2025 SH_PFC_FUNCTION(ether), 2080 SH_PFC_FUNCTION(ether),
2026 SH_PFC_FUNCTION(hscif0), 2081 SH_PFC_FUNCTION(hscif0),
2027 SH_PFC_FUNCTION(hscif1), 2082 SH_PFC_FUNCTION(hscif1),
diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7791.c b/drivers/pinctrl/sh-pfc/pfc-r8a7791.c
new file mode 100644
index 000000000000..bf76a654c02f
--- /dev/null
+++ b/drivers/pinctrl/sh-pfc/pfc-r8a7791.c
@@ -0,0 +1,4214 @@
1/*
2 * r8a7791 processor support - PFC hardware block.
3 *
4 * Copyright (C) 2013 Renesas Electronics Corporation
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2
8 * as published by the Free Software Foundation.
9 */
10
11#include <linux/kernel.h>
12#include <linux/platform_data/gpio-rcar.h>
13
14#include "core.h"
15#include "sh_pfc.h"
16
17#define CPU_ALL_PORT(fn, sfx) \
18 PORT_GP_32(0, fn, sfx), \
19 PORT_GP_32(1, fn, sfx), \
20 PORT_GP_32(2, fn, sfx), \
21 PORT_GP_32(3, fn, sfx), \
22 PORT_GP_32(4, fn, sfx), \
23 PORT_GP_32(5, fn, sfx), \
24 PORT_GP_32(6, fn, sfx), \
25 PORT_GP_32(7, fn, sfx)
26
27enum {
28 PINMUX_RESERVED = 0,
29
30 PINMUX_DATA_BEGIN,
31 GP_ALL(DATA),
32 PINMUX_DATA_END,
33
34 PINMUX_FUNCTION_BEGIN,
35 GP_ALL(FN),
36
37 /* GPSR0 */
38 FN_IP0_0, FN_IP0_1, FN_IP0_2, FN_IP0_3, FN_IP0_4, FN_IP0_5,
39 FN_IP0_6, FN_IP0_7, FN_IP0_8, FN_IP0_9, FN_IP0_10, FN_IP0_11,
40 FN_IP0_12, FN_IP0_13, FN_IP0_14, FN_IP0_15, FN_IP0_18_16, FN_IP0_20_19,
41 FN_IP0_22_21, FN_IP0_24_23, FN_IP0_26_25, FN_IP0_28_27, FN_IP0_30_29,
42 FN_IP1_1_0, FN_IP1_3_2, FN_IP1_5_4, FN_IP1_7_6, FN_IP1_10_8,
43 FN_IP1_13_11, FN_IP1_16_14, FN_IP1_19_17, FN_IP1_22_20,
44
45 /* GPSR1 */
46 FN_IP1_25_23, FN_IP1_28_26, FN_IP1_31_29, FN_IP2_2_0, FN_IP2_4_3,
47 FN_IP2_6_5, FN_IP2_9_7, FN_IP2_12_10, FN_IP2_15_13, FN_IP2_18_16,
48 FN_IP2_20_19, FN_IP2_22_21, FN_EX_CS0_N, FN_IP2_24_23, FN_IP2_26_25,
49 FN_IP2_29_27, FN_IP3_2_0, FN_IP3_5_3, FN_IP3_8_6, FN_RD_N,
50 FN_IP3_11_9, FN_IP3_13_12, FN_IP3_15_14 , FN_IP3_17_16 , FN_IP3_19_18,
51 FN_IP3_21_20,
52
53 /* GPSR2 */
54 FN_IP3_27_25, FN_IP3_30_28, FN_IP4_1_0, FN_IP4_4_2, FN_IP4_7_5,
55 FN_IP4_9_8, FN_IP4_12_10, FN_IP4_15_13, FN_IP4_18_16, FN_IP4_19,
56 FN_IP4_20, FN_IP4_21, FN_IP4_23_22, FN_IP4_25_24, FN_IP4_27_26,
57 FN_IP4_30_28, FN_IP5_2_0, FN_IP5_5_3, FN_IP5_8_6, FN_IP5_11_9,
58 FN_IP5_14_12, FN_IP5_16_15, FN_IP5_19_17, FN_IP5_21_20, FN_IP5_23_22,
59 FN_IP5_25_24, FN_IP5_28_26, FN_IP5_31_29, FN_AUDIO_CLKA, FN_IP6_2_0,
60 FN_IP6_5_3, FN_IP6_7_6,
61
62 /* GPSR3 */
63 FN_IP7_5_3, FN_IP7_8_6, FN_IP7_10_9, FN_IP7_12_11, FN_IP7_14_13,
64 FN_IP7_16_15, FN_IP7_18_17, FN_IP7_20_19, FN_IP7_23_21, FN_IP7_26_24,
65 FN_IP7_29_27, FN_IP8_2_0, FN_IP8_5_3, FN_IP8_8_6, FN_IP8_11_9,
66 FN_IP8_14_12, FN_IP8_17_15, FN_IP8_20_18, FN_IP8_23_21, FN_IP8_25_24,
67 FN_IP8_27_26, FN_IP8_30_28, FN_IP9_2_0, FN_IP9_5_3, FN_IP9_6, FN_IP9_7,
68 FN_IP9_10_8, FN_IP9_11, FN_IP9_12, FN_IP9_15_13, FN_IP9_16,
69 FN_IP9_18_17,
70
71 /* GPSR4 */
72 FN_VI0_CLK, FN_IP9_20_19, FN_IP9_22_21, FN_IP9_24_23, FN_IP9_26_25,
73 FN_VI0_DATA0_VI0_B0, FN_VI0_DATA1_VI0_B1, FN_VI0_DATA2_VI0_B2,
74 FN_IP9_28_27, FN_VI0_DATA4_VI0_B4, FN_VI0_DATA5_VI0_B5,
75 FN_VI0_DATA6_VI0_B6, FN_VI0_DATA7_VI0_B7, FN_IP9_31_29, FN_IP10_2_0,
76 FN_IP10_5_3, FN_IP10_8_6, FN_IP10_11_9, FN_IP10_14_12, FN_IP10_16_15,
77 FN_IP10_18_17, FN_IP10_21_19, FN_IP10_24_22, FN_IP10_26_25,
78 FN_IP10_28_27, FN_IP10_31_29, FN_IP11_2_0, FN_IP11_5_3, FN_IP11_8_6,
79 FN_IP15_1_0, FN_IP15_3_2, FN_IP15_5_4,
80
81 /* GPSR5 */
82 FN_IP11_11_9, FN_IP11_14_12, FN_IP11_16_15, FN_IP11_18_17, FN_IP11_19,
83 FN_IP11_20, FN_IP11_21, FN_IP11_22, FN_IP11_23, FN_IP11_24,
84 FN_IP11_25, FN_IP11_26, FN_IP11_27, FN_IP11_29_28, FN_IP11_31_30,
85 FN_IP12_1_0, FN_IP12_3_2, FN_IP12_6_4, FN_IP12_9_7, FN_IP12_12_10,
86 FN_IP12_15_13, FN_IP12_17_16, FN_IP12_19_18, FN_IP12_21_20,
87 FN_IP12_23_22, FN_IP12_26_24, FN_IP12_29_27, FN_IP13_2_0, FN_IP13_4_3,
88 FN_IP13_6_5, FN_IP13_9_7, FN_IP3_24_22,
89
90 /* GPSR6 */
91 FN_IP13_10, FN_IP13_11, FN_IP13_12, FN_IP13_13, FN_IP13_14,
92 FN_IP13_15, FN_IP13_18_16, FN_IP13_21_19, FN_IP13_22, FN_IP13_24_23,
93 FN_IP13_25, FN_IP13_26, FN_IP13_27, FN_IP13_30_28, FN_IP14_1_0,
94 FN_IP14_2, FN_IP14_3, FN_IP14_4, FN_IP14_5, FN_IP14_6, FN_IP14_7,
95 FN_IP14_10_8, FN_IP14_13_11, FN_IP14_16_14, FN_IP14_19_17,
96 FN_IP14_22_20, FN_IP14_25_23, FN_IP14_28_26, FN_IP14_31_29,
97 FN_USB1_OVC, FN_DU0_DOTCLKIN,
98
99 /* GPSR7 */
100 FN_IP15_17_15, FN_IP15_20_18, FN_IP15_23_21, FN_IP15_26_24,
101 FN_IP15_29_27, FN_IP16_2_0, FN_IP16_5_3, FN_IP16_7_6, FN_IP16_9_8,
102 FN_IP16_11_10, FN_IP6_9_8, FN_IP6_11_10, FN_IP6_13_12, FN_IP6_15_14,
103 FN_IP6_18_16, FN_IP6_20_19, FN_IP6_23_21, FN_IP6_26_24, FN_IP6_29_27,
104 FN_IP7_2_0, FN_IP15_8_6, FN_IP15_11_9, FN_IP15_14_12,
105 FN_USB0_PWEN, FN_USB0_OVC, FN_USB1_PWEN,
106
107 /* IPSR0 */
108 FN_D0, FN_D1, FN_D2, FN_D3, FN_D4, FN_D5, FN_D6, FN_D7, FN_D8,
109 FN_D9, FN_D10, FN_D11, FN_D12, FN_D13, FN_D14, FN_D15,
110 FN_A0, FN_ATAWR0_N_C, FN_MSIOF0_SCK_B, FN_SCL0_C, FN_PWM2_B,
111 FN_A1, FN_MSIOF0_SYNC_B, FN_A2, FN_MSIOF0_SS1_B,
112 FN_A3, FN_MSIOF0_SS2_B, FN_A4, FN_MSIOF0_TXD_B,
113 FN_A5, FN_MSIOF0_RXD_B, FN_A6, FN_MSIOF1_SCK,
114
115 /* IPSR1 */
116 FN_A7, FN_MSIOF1_SYNC, FN_A8, FN_MSIOF1_SS1, FN_SCL0,
117 FN_A9, FN_MSIOF1_SS2, FN_SDA0,
118 FN_A10, FN_MSIOF1_TXD, FN_MSIOF1_TXD_D,
119 FN_A11, FN_MSIOF1_RXD, FN_SCL3_D, FN_MSIOF1_RXD_D,
120 FN_A12, FN_FMCLK, FN_SDA3_D, FN_MSIOF1_SCK_D,
121 FN_A13, FN_ATAG0_N_C, FN_BPFCLK, FN_MSIOF1_SS1_D,
122 FN_A14, FN_ATADIR0_N_C, FN_FMIN, FN_FMIN_C, FN_MSIOF1_SYNC_D,
123 FN_A15, FN_BPFCLK_C,
124 FN_A16, FN_DREQ2_B, FN_FMCLK_C, FN_SCIFA1_SCK_B,
125 FN_A17, FN_DACK2_B, FN_SDA0_C,
126 FN_A18, FN_DREQ1, FN_SCIFA1_RXD_C, FN_SCIFB1_RXD_C,
127
128 /* IPSR2 */
129 FN_A19, FN_DACK1, FN_SCIFA1_TXD_C, FN_SCIFB1_TXD_C, FN_SCIFB1_SCK_B,
130 FN_A20, FN_SPCLK,
131 FN_A21, FN_ATAWR0_N_B, FN_MOSI_IO0,
132 FN_A22, FN_MISO_IO1, FN_FMCLK_B, FN_TX0, FN_SCIFA0_TXD,
133 FN_A23, FN_IO2, FN_BPFCLK_B, FN_RX0, FN_SCIFA0_RXD,
134 FN_A24, FN_DREQ2, FN_IO3, FN_TX1, FN_SCIFA1_TXD,
135 FN_A25, FN_DACK2, FN_SSL, FN_DREQ1_C, FN_RX1, FN_SCIFA1_RXD,
136 FN_CS0_N, FN_ATAG0_N_B, FN_SCL1,
137 FN_CS1_N_A26, FN_ATADIR0_N_B, FN_SDA1,
138 FN_EX_CS1_N, FN_MSIOF2_SCK,
139 FN_EX_CS2_N, FN_ATAWR0_N, FN_MSIOF2_SYNC,
140 FN_EX_CS3_N, FN_ATADIR0_N, FN_MSIOF2_TXD, FN_ATAG0_N, FN_EX_WAIT1,
141
142 /* IPSR3 */
143 FN_EX_CS4_N, FN_ATARD0_N, FN_MSIOF2_RXD, FN_EX_WAIT2,
144 FN_EX_CS5_N, FN_ATACS00_N, FN_MSIOF2_SS1, FN_HRX1_B,
145 FN_SCIFB1_RXD_B, FN_PWM1, FN_TPU_TO1,
146 FN_BS_N, FN_ATACS10_N, FN_MSIOF2_SS2, FN_HTX1_B,
147 FN_SCIFB1_TXD_B, FN_PWM2, FN_TPU_TO2,
148 FN_RD_WR_N, FN_HRX2_B, FN_FMIN_B, FN_SCIFB0_RXD_B, FN_DREQ1_D,
149 FN_WE0_N, FN_HCTS2_N_B, FN_SCIFB0_TXD_B,
150 FN_WE1_N, FN_ATARD0_N_B, FN_HTX2_B, FN_SCIFB0_RTS_N_B,
151 FN_EX_WAIT0, FN_HRTS2_N_B, FN_SCIFB0_CTS_N_B,
152 FN_DREQ0, FN_PWM3, FN_TPU_TO3,
153 FN_DACK0, FN_DRACK0, FN_REMOCON,
154 FN_SPEEDIN, FN_HSCK0_C, FN_HSCK2_C, FN_SCIFB0_SCK_B,
155 FN_SCIFB2_SCK_B, FN_DREQ2_C, FN_HTX2_D,
156 FN_SSI_SCK0129, FN_HRX0_C, FN_HRX2_C, FN_SCIFB0_RXD_C, FN_SCIFB2_RXD_C,
157 FN_SSI_WS0129, FN_HTX0_C, FN_HTX2_C, FN_SCIFB0_TXD_C, FN_SCIFB2_TXD_C,
158
159 /* IPSR4 */
160 FN_SSI_SDATA0, FN_SCL0_B, FN_SCL7_B, FN_MSIOF2_SCK_C,
161 FN_SSI_SCK1, FN_SDA0_B, FN_SDA7_B, FN_MSIOF2_SYNC_C, FN_GLO_I0_D,
162 FN_SSI_WS1, FN_SCL1_B, FN_SCL8_B, FN_MSIOF2_TXD_C, FN_GLO_I1_D,
163 FN_SSI_SDATA1, FN_SDA1_B, FN_SDA8_B, FN_MSIOF2_RXD_C,
164 FN_SSI_SCK2, FN_SCL2, FN_GPS_CLK_B, FN_GLO_Q0_D, FN_HSCK1_E,
165 FN_SSI_WS2, FN_SDA2, FN_GPS_SIGN_B, FN_RX2_E,
166 FN_GLO_Q1_D, FN_HCTS1_N_E,
167 FN_SSI_SDATA2, FN_GPS_MAG_B, FN_TX2_E, FN_HRTS1_N_E,
168 FN_SSI_SCK34, FN_SSI_WS34, FN_SSI_SDATA3,
169 FN_SSI_SCK4, FN_GLO_SS_D,
170 FN_SSI_WS4, FN_GLO_RFON_D,
171 FN_SSI_SDATA4, FN_MSIOF2_SCK_D,
172 FN_SSI_SCK5, FN_MSIOF1_SCK_C, FN_TS_SDATA0, FN_GLO_I0,
173 FN_MSIOF2_SYNC_D, FN_VI1_R2_B,
174
175 /* IPSR5 */
176 FN_SSI_WS5, FN_MSIOF1_SYNC_C, FN_TS_SCK0, FN_GLO_I1,
177 FN_MSIOF2_TXD_D, FN_VI1_R3_B,
178 FN_SSI_SDATA5, FN_MSIOF1_TXD_C, FN_TS_SDEN0, FN_GLO_Q0,
179 FN_MSIOF2_SS1_D, FN_VI1_R4_B,
180 FN_SSI_SCK6, FN_MSIOF1_RXD_C, FN_TS_SPSYNC0, FN_GLO_Q1,
181 FN_MSIOF2_RXD_D, FN_VI1_R5_B,
182 FN_SSI_WS6, FN_GLO_SCLK, FN_MSIOF2_SS2_D, FN_VI1_R6_B,
183 FN_SSI_SDATA6, FN_STP_IVCXO27_0_B, FN_GLO_SDATA, FN_VI1_R7_B,
184 FN_SSI_SCK78, FN_STP_ISCLK_0_B, FN_GLO_SS,
185 FN_SSI_WS78, FN_TX0_D, FN_STP_ISD_0_B, FN_GLO_RFON,
186 FN_SSI_SDATA7, FN_RX0_D, FN_STP_ISEN_0_B,
187 FN_SSI_SDATA8, FN_TX1_D, FN_STP_ISSYNC_0_B,
188 FN_SSI_SCK9, FN_RX1_D, FN_GLO_SCLK_D,
189 FN_SSI_WS9, FN_TX3_D, FN_CAN0_TX_D, FN_GLO_SDATA_D,
190 FN_SSI_SDATA9, FN_RX3_D, FN_CAN0_RX_D,
191
192 /* IPSR6 */
193 FN_AUDIO_CLKB, FN_STP_OPWM_0_B, FN_MSIOF1_SCK_B,
194 FN_SCIF_CLK, FN_BPFCLK_E,
195 FN_AUDIO_CLKC, FN_SCIFB0_SCK_C, FN_MSIOF1_SYNC_B, FN_RX2,
196 FN_SCIFA2_RXD, FN_FMIN_E,
197 FN_AUDIO_CLKOUT, FN_MSIOF1_SS1_B, FN_TX2, FN_SCIFA2_TXD,
198 FN_IRQ0, FN_SCIFB1_RXD_D, FN_INTC_IRQ0_N,
199 FN_IRQ1, FN_SCIFB1_SCK_C, FN_INTC_IRQ1_N,
200 FN_IRQ2, FN_SCIFB1_TXD_D, FN_INTC_IRQ2_N,
201 FN_IRQ3, FN_SCL4_C, FN_MSIOF2_TXD_E, FN_INTC_IRQ3_N,
202 FN_IRQ4, FN_HRX1_C, FN_SDA4_C, FN_MSIOF2_RXD_E, FN_INTC_IRQ4_N,
203 FN_IRQ5, FN_HTX1_C, FN_SCL1_E, FN_MSIOF2_SCK_E,
204 FN_IRQ6, FN_HSCK1_C, FN_MSIOF1_SS2_B, FN_SDA1_E, FN_MSIOF2_SYNC_E,
205 FN_IRQ7, FN_HCTS1_N_C, FN_MSIOF1_TXD_B, FN_GPS_CLK_C, FN_GPS_CLK_D,
206 FN_IRQ8, FN_HRTS1_N_C, FN_MSIOF1_RXD_B, FN_GPS_SIGN_C, FN_GPS_SIGN_D,
207
208 /* IPSR7 */
209 FN_IRQ9, FN_DU1_DOTCLKIN_B, FN_CAN_CLK_D, FN_GPS_MAG_C,
210 FN_SCIF_CLK_B, FN_GPS_MAG_D,
211 FN_DU1_DR0, FN_LCDOUT0, FN_VI1_DATA0_B, FN_TX0_B,
212 FN_SCIFA0_TXD_B, FN_MSIOF2_SCK_B,
213 FN_DU1_DR1, FN_LCDOUT1, FN_VI1_DATA1_B, FN_RX0_B,
214 FN_SCIFA0_RXD_B, FN_MSIOF2_SYNC_B,
215 FN_DU1_DR2, FN_LCDOUT2, FN_SSI_SCK0129_B,
216 FN_DU1_DR3, FN_LCDOUT3, FN_SSI_WS0129_B,
217 FN_DU1_DR4, FN_LCDOUT4, FN_SSI_SDATA0_B,
218 FN_DU1_DR5, FN_LCDOUT5, FN_SSI_SCK1_B,
219 FN_DU1_DR6, FN_LCDOUT6, FN_SSI_WS1_B,
220 FN_DU1_DR7, FN_LCDOUT7, FN_SSI_SDATA1_B,
221 FN_DU1_DG0, FN_LCDOUT8, FN_VI1_DATA2_B, FN_TX1_B,
222 FN_SCIFA1_TXD_B, FN_MSIOF2_SS1_B,
223 FN_DU1_DG1, FN_LCDOUT9, FN_VI1_DATA3_B, FN_RX1_B,
224 FN_SCIFA1_RXD_B, FN_MSIOF2_SS2_B,
225 FN_DU1_DG2, FN_LCDOUT10, FN_VI1_DATA4_B, FN_SCIF1_SCK_B,
226 FN_SCIFA1_SCK, FN_SSI_SCK78_B,
227
228 /* IPSR8 */
229 FN_DU1_DG3, FN_LCDOUT11, FN_VI1_DATA5_B, FN_SSI_WS78_B,
230 FN_DU1_DG4, FN_LCDOUT12, FN_VI1_DATA6_B, FN_HRX0_B,
231 FN_SCIFB2_RXD_B, FN_SSI_SDATA7_B,
232 FN_DU1_DG5, FN_LCDOUT13, FN_VI1_DATA7_B, FN_HCTS0_N_B,
233 FN_SCIFB2_TXD_B, FN_SSI_SDATA8_B,
234 FN_DU1_DG6, FN_LCDOUT14, FN_HRTS0_N_B,
235 FN_SCIFB2_CTS_N_B, FN_SSI_SCK9_B,
236 FN_DU1_DG7, FN_LCDOUT15, FN_HTX0_B, FN_SCIFB2_RTS_N_B, FN_SSI_WS9_B,
237 FN_DU1_DB0, FN_LCDOUT16, FN_VI1_CLK_B, FN_TX2_B,
238 FN_SCIFA2_TXD_B, FN_MSIOF2_TXD_B,
239 FN_DU1_DB1, FN_LCDOUT17, FN_VI1_HSYNC_N_B, FN_RX2_B,
240 FN_SCIFA2_RXD_B, FN_MSIOF2_RXD_B,
241 FN_DU1_DB2, FN_LCDOUT18, FN_VI1_VSYNC_N_B, FN_SCIF2_SCK_B,
242 FN_SCIFA2_SCK, FN_SSI_SDATA9_B,
243 FN_DU1_DB3, FN_LCDOUT19, FN_VI1_CLKENB_B,
244 FN_DU1_DB4, FN_LCDOUT20, FN_VI1_FIELD_B, FN_CAN1_RX,
245 FN_DU1_DB5, FN_LCDOUT21, FN_TX3, FN_SCIFA3_TXD, FN_CAN1_TX,
246
247 /* IPSR9 */
248 FN_DU1_DB6, FN_LCDOUT22, FN_SCL3_C, FN_RX3, FN_SCIFA3_RXD,
249 FN_DU1_DB7, FN_LCDOUT23, FN_SDA3_C, FN_SCIF3_SCK, FN_SCIFA3_SCK,
250 FN_DU1_DOTCLKIN, FN_QSTVA_QVS,
251 FN_DU1_DOTCLKOUT0, FN_QCLK,
252 FN_DU1_DOTCLKOUT1, FN_QSTVB_QVE, FN_CAN0_TX,
253 FN_TX3_B, FN_SCL2_B, FN_PWM4,
254 FN_DU1_EXHSYNC_DU1_HSYNC, FN_QSTH_QHS,
255 FN_DU1_EXVSYNC_DU1_VSYNC, FN_QSTB_QHE,
256 FN_DU1_EXODDF_DU1_ODDF_DISP_CDE, FN_QCPV_QDE,
257 FN_CAN0_RX, FN_RX3_B, FN_SDA2_B,
258 FN_DU1_DISP, FN_QPOLA,
259 FN_DU1_CDE, FN_QPOLB, FN_PWM4_B,
260 FN_VI0_CLKENB, FN_TX4, FN_SCIFA4_TXD, FN_TS_SDATA0_D,
261 FN_VI0_FIELD, FN_RX4, FN_SCIFA4_RXD, FN_TS_SCK0_D,
262 FN_VI0_HSYNC_N, FN_TX5, FN_SCIFA5_TXD, FN_TS_SDEN0_D,
263 FN_VI0_VSYNC_N, FN_RX5, FN_SCIFA5_RXD, FN_TS_SPSYNC0_D,
264 FN_VI0_DATA3_VI0_B3, FN_SCIF3_SCK_B, FN_SCIFA3_SCK_B,
265 FN_VI0_G0, FN_SCL8, FN_STP_IVCXO27_0_C, FN_SCL4,
266 FN_HCTS2_N, FN_SCIFB2_CTS_N, FN_ATAWR1_N,
267
268 /* IPSR10 */
269 FN_VI0_G1, FN_SDA8, FN_STP_ISCLK_0_C, FN_SDA4,
270 FN_HRTS2_N, FN_SCIFB2_RTS_N, FN_ATADIR1_N,
271 FN_VI0_G2, FN_VI2_HSYNC_N, FN_STP_ISD_0_C, FN_SCL3_B,
272 FN_HSCK2, FN_SCIFB2_SCK, FN_ATARD1_N,
273 FN_VI0_G3, FN_VI2_VSYNC_N, FN_STP_ISEN_0_C, FN_SDA3_B,
274 FN_HRX2, FN_SCIFB2_RXD, FN_ATACS01_N,
275 FN_VI0_G4, FN_VI2_CLKENB, FN_STP_ISSYNC_0_C,
276 FN_HTX2, FN_SCIFB2_TXD, FN_SCIFB0_SCK_D,
277 FN_VI0_G5, FN_VI2_FIELD, FN_STP_OPWM_0_C, FN_FMCLK_D,
278 FN_CAN0_TX_E, FN_HTX1_D, FN_SCIFB0_TXD_D,
279 FN_VI0_G6, FN_VI2_CLK, FN_BPFCLK_D,
280 FN_VI0_G7, FN_VI2_DATA0, FN_FMIN_D,
281 FN_VI0_R0, FN_VI2_DATA1, FN_GLO_I0_B,
282 FN_TS_SDATA0_C, FN_ATACS11_N,
283 FN_VI0_R1, FN_VI2_DATA2, FN_GLO_I1_B,
284 FN_TS_SCK0_C, FN_ATAG1_N,
285 FN_VI0_R2, FN_VI2_DATA3, FN_GLO_Q0_B, FN_TS_SDEN0_C,
286 FN_VI0_R3, FN_VI2_DATA4, FN_GLO_Q1_B, FN_TS_SPSYNC0_C,
287 FN_VI0_R4, FN_VI2_DATA5, FN_GLO_SCLK_B, FN_TX0_C, FN_SCL1_D,
288
289 /* IPSR11 */
290 FN_VI0_R5, FN_VI2_DATA6, FN_GLO_SDATA_B, FN_RX0_C, FN_SDA1_D,
291 FN_VI0_R6, FN_VI2_DATA7, FN_GLO_SS_B, FN_TX1_C, FN_SCL4_B,
292 FN_VI0_R7, FN_GLO_RFON_B, FN_RX1_C, FN_CAN0_RX_E,
293 FN_SDA4_B, FN_HRX1_D, FN_SCIFB0_RXD_D,
294 FN_VI1_HSYNC_N, FN_AVB_RXD0, FN_TS_SDATA0_B, FN_TX4_B, FN_SCIFA4_TXD_B,
295 FN_VI1_VSYNC_N, FN_AVB_RXD1, FN_TS_SCK0_B, FN_RX4_B, FN_SCIFA4_RXD_B,
296 FN_VI1_CLKENB, FN_AVB_RXD2, FN_TS_SDEN0_B,
297 FN_VI1_FIELD, FN_AVB_RXD3, FN_TS_SPSYNC0_B,
298 FN_VI1_CLK, FN_AVB_RXD4, FN_VI1_DATA0, FN_AVB_RXD5,
299 FN_VI1_DATA1, FN_AVB_RXD6, FN_VI1_DATA2, FN_AVB_RXD7,
300 FN_VI1_DATA3, FN_AVB_RX_ER, FN_VI1_DATA4, FN_AVB_MDIO,
301 FN_VI1_DATA5, FN_AVB_RX_DV, FN_VI1_DATA6, FN_AVB_MAGIC,
302 FN_VI1_DATA7, FN_AVB_MDC,
303 FN_ETH_MDIO, FN_AVB_RX_CLK, FN_SCL2_C,
304 FN_ETH_CRS_DV, FN_AVB_LINK, FN_SDA2_C,
305
306 /* IPSR12 */
307 FN_ETH_RX_ER, FN_AVB_CRS, FN_SCL3, FN_SCL7,
308 FN_ETH_RXD0, FN_AVB_PHY_INT, FN_SDA3, FN_SDA7,
309 FN_ETH_RXD1, FN_AVB_GTXREFCLK, FN_CAN0_TX_C,
310 FN_SCL2_D, FN_MSIOF1_RXD_E,
311 FN_ETH_LINK, FN_AVB_TXD0, FN_CAN0_RX_C, FN_SDA2_D, FN_MSIOF1_SCK_E,
312 FN_ETH_REFCLK, FN_AVB_TXD1, FN_SCIFA3_RXD_B,
313 FN_CAN1_RX_C, FN_MSIOF1_SYNC_E,
314 FN_ETH_TXD1, FN_AVB_TXD2, FN_SCIFA3_TXD_B,
315 FN_CAN1_TX_C, FN_MSIOF1_TXD_E,
316 FN_ETH_TX_EN, FN_AVB_TXD3, FN_TCLK1_B, FN_CAN_CLK_B,
317 FN_ETH_MAGIC, FN_AVB_TXD4, FN_IETX_C,
318 FN_ETH_TXD0, FN_AVB_TXD5, FN_IECLK_C,
319 FN_ETH_MDC, FN_AVB_TXD6, FN_IERX_C,
320 FN_STP_IVCXO27_0, FN_AVB_TXD7, FN_SCIFB2_TXD_D,
321 FN_ADIDATA_B, FN_MSIOF0_SYNC_C,
322 FN_STP_ISCLK_0, FN_AVB_TX_EN, FN_SCIFB2_RXD_D,
323 FN_ADICS_SAMP_B, FN_MSIOF0_SCK_C,
324
325 /* IPSR13 */
326 FN_STP_ISD_0, FN_AVB_TX_ER, FN_SCIFB2_SCK_C,
327 FN_ADICLK_B, FN_MSIOF0_SS1_C,
328 FN_STP_ISEN_0, FN_AVB_TX_CLK, FN_ADICHS0_B, FN_MSIOF0_SS2_C,
329 FN_STP_ISSYNC_0, FN_AVB_COL, FN_ADICHS1_B, FN_MSIOF0_RXD_C,
330 FN_STP_OPWM_0, FN_AVB_GTX_CLK, FN_PWM0_B,
331 FN_ADICHS2_B, FN_MSIOF0_TXD_C,
332 FN_SD0_CLK, FN_SPCLK_B, FN_SD0_CMD, FN_MOSI_IO0_B,
333 FN_SD0_DATA0, FN_MISO_IO1_B, FN_SD0_DATA1, FN_IO2_B,
334 FN_SD0_DATA2, FN_IO3_B, FN_SD0_DATA3, FN_SSL_B,
335 FN_SD0_CD, FN_MMC_D6_B, FN_SIM0_RST_B, FN_CAN0_RX_F,
336 FN_SCIFA5_TXD_B, FN_TX3_C,
337 FN_SD0_WP, FN_MMC_D7_B, FN_SIM0_D_B, FN_CAN0_TX_F,
338 FN_SCIFA5_RXD_B, FN_RX3_C,
339 FN_SD1_CMD, FN_REMOCON_B, FN_SD1_DATA0, FN_SPEEDIN_B,
340 FN_SD1_DATA1, FN_IETX_B, FN_SD1_DATA2, FN_IECLK_B,
341 FN_SD1_DATA3, FN_IERX_B,
342 FN_SD1_CD, FN_PWM0, FN_TPU_TO0, FN_SCL1_C,
343
344 /* IPSR14 */
345 FN_SD1_WP, FN_PWM1_B, FN_SDA1_C,
346 FN_SD2_CLK, FN_MMC_CLK, FN_SD2_CMD, FN_MMC_CMD,
347 FN_SD2_DATA0, FN_MMC_D0, FN_SD2_DATA1, FN_MMC_D1,
348 FN_SD2_DATA2, FN_MMC_D2, FN_SD2_DATA3, FN_MMC_D3,
349 FN_SD2_CD, FN_MMC_D4, FN_SCL8_C, FN_TX5_B, FN_SCIFA5_TXD_C,
350 FN_SD2_WP, FN_MMC_D5, FN_SDA8_C, FN_RX5_B, FN_SCIFA5_RXD_C,
351 FN_MSIOF0_SCK, FN_RX2_C, FN_ADIDATA, FN_VI1_CLK_C, FN_VI1_G0_B,
352 FN_MSIOF0_SYNC, FN_TX2_C, FN_ADICS_SAMP, FN_VI1_CLKENB_C, FN_VI1_G1_B,
353 FN_MSIOF0_TXD, FN_ADICLK, FN_VI1_FIELD_C, FN_VI1_G2_B,
354 FN_MSIOF0_RXD, FN_ADICHS0, FN_VI1_DATA0_C, FN_VI1_G3_B,
355 FN_MSIOF0_SS1, FN_MMC_D6, FN_ADICHS1, FN_TX0_E,
356 FN_VI1_HSYNC_N_C, FN_SCL7_C, FN_VI1_G4_B,
357 FN_MSIOF0_SS2, FN_MMC_D7, FN_ADICHS2, FN_RX0_E,
358 FN_VI1_VSYNC_N_C, FN_SDA7_C, FN_VI1_G5_B,
359
360 /* IPSR15 */
361 FN_SIM0_RST, FN_IETX, FN_CAN1_TX_D,
362 FN_SIM0_CLK, FN_IECLK, FN_CAN_CLK_C,
363 FN_SIM0_D, FN_IERX, FN_CAN1_RX_D,
364 FN_GPS_CLK, FN_DU1_DOTCLKIN_C, FN_AUDIO_CLKB_B,
365 FN_PWM5_B, FN_SCIFA3_TXD_C,
366 FN_GPS_SIGN, FN_TX4_C, FN_SCIFA4_TXD_C, FN_PWM5,
367 FN_VI1_G6_B, FN_SCIFA3_RXD_C,
368 FN_GPS_MAG, FN_RX4_C, FN_SCIFA4_RXD_C, FN_PWM6,
369 FN_VI1_G7_B, FN_SCIFA3_SCK_C,
370 FN_HCTS0_N, FN_SCIFB0_CTS_N, FN_GLO_I0_C, FN_TCLK1, FN_VI1_DATA1_C,
371 FN_HRTS0_N, FN_SCIFB0_RTS_N, FN_GLO_I1_C, FN_VI1_DATA2_C,
372 FN_HSCK0, FN_SCIFB0_SCK, FN_GLO_Q0_C, FN_CAN_CLK,
373 FN_TCLK2, FN_VI1_DATA3_C,
374 FN_HRX0, FN_SCIFB0_RXD, FN_GLO_Q1_C, FN_CAN0_RX_B, FN_VI1_DATA4_C,
375 FN_HTX0, FN_SCIFB0_TXD, FN_GLO_SCLK_C, FN_CAN0_TX_B, FN_VI1_DATA5_C,
376
377 /* IPSR16 */
378 FN_HRX1, FN_SCIFB1_RXD, FN_VI1_R0_B, FN_GLO_SDATA_C, FN_VI1_DATA6_C,
379 FN_HTX1, FN_SCIFB1_TXD, FN_VI1_R1_B, FN_GLO_SS_C, FN_VI1_DATA7_C,
380 FN_HSCK1, FN_SCIFB1_SCK, FN_MLB_CK, FN_GLO_RFON_C,
381 FN_HCTS1_N, FN_SCIFB1_CTS_N, FN_MLB_SIG, FN_CAN1_TX_B,
382 FN_HRTS1_N, FN_SCIFB1_RTS_N, FN_MLB_DAT, FN_CAN1_RX_B,
383
384 /* MOD_SEL */
385 FN_SEL_SCIF1_0, FN_SEL_SCIF1_1, FN_SEL_SCIF1_2, FN_SEL_SCIF1_3,
386 FN_SEL_SCIFB_0, FN_SEL_SCIFB_1, FN_SEL_SCIFB_2, FN_SEL_SCIFB_3,
387 FN_SEL_SCIFB2_0, FN_SEL_SCIFB2_1, FN_SEL_SCIFB2_2, FN_SEL_SCIFB2_3,
388 FN_SEL_SCIFB1_0, FN_SEL_SCIFB1_1, FN_SEL_SCIFB1_2, FN_SEL_SCIFB1_3,
389 FN_SEL_SCIFA1_0, FN_SEL_SCIFA1_1, FN_SEL_SCIFA1_2,
390 FN_SEL_SSI9_0, FN_SEL_SSI9_1,
391 FN_SEL_SCFA_0, FN_SEL_SCFA_1,
392 FN_SEL_QSP_0, FN_SEL_QSP_1,
393 FN_SEL_SSI7_0, FN_SEL_SSI7_1,
394 FN_SEL_HSCIF1_0, FN_SEL_HSCIF1_1, FN_SEL_HSCIF1_2, FN_SEL_HSCIF1_3,
395 FN_SEL_HSCIF1_4,
396 FN_SEL_VI1_0, FN_SEL_VI1_1, FN_SEL_VI1_2,
397 FN_SEL_TMU1_0, FN_SEL_TMU1_1,
398 FN_SEL_LBS_0, FN_SEL_LBS_1, FN_SEL_LBS_2, FN_SEL_LBS_3,
399 FN_SEL_TSIF0_0, FN_SEL_TSIF0_1, FN_SEL_TSIF0_2, FN_SEL_TSIF0_3,
400 FN_SEL_SOF0_0, FN_SEL_SOF0_1, FN_SEL_SOF0_2,
401
402 /* MOD_SEL2 */
403 FN_SEL_SCIF0_0, FN_SEL_SCIF0_1, FN_SEL_SCIF0_2, FN_SEL_SCIF0_3,
404 FN_SEL_SCIF0_4,
405 FN_SEL_SCIF_0, FN_SEL_SCIF_1,
406 FN_SEL_CAN0_0, FN_SEL_CAN0_1, FN_SEL_CAN0_2, FN_SEL_CAN0_3,
407 FN_SEL_CAN0_4, FN_SEL_CAN0_5,
408 FN_SEL_CAN1_0, FN_SEL_CAN1_1, FN_SEL_CAN1_2, FN_SEL_CAN1_3,
409 FN_SEL_SCIFA2_0, FN_SEL_SCIFA2_1,
410 FN_SEL_SCIF4_0, FN_SEL_SCIF4_1, FN_SEL_SCIF4_2,
411 FN_SEL_ADG_0, FN_SEL_ADG_1,
412 FN_SEL_FM_0, FN_SEL_FM_1, FN_SEL_FM_2, FN_SEL_FM_3, FN_SEL_FM_4,
413 FN_SEL_SCIFA5_0, FN_SEL_SCIFA5_1, FN_SEL_SCIFA5_2,
414 FN_SEL_GPS_0, FN_SEL_GPS_1, FN_SEL_GPS_2, FN_SEL_GPS_3,
415 FN_SEL_SCIFA4_0, FN_SEL_SCIFA4_1, FN_SEL_SCIFA4_2,
416 FN_SEL_SCIFA3_0, FN_SEL_SCIFA3_1, FN_SEL_SCIFA3_2,
417 FN_SEL_SIM_0, FN_SEL_SIM_1,
418 FN_SEL_SSI8_0, FN_SEL_SSI8_1,
419
420 /* MOD_SEL3 */
421 FN_SEL_HSCIF2_0, FN_SEL_HSCIF2_1, FN_SEL_HSCIF2_2, FN_SEL_HSCIF2_3,
422 FN_SEL_CANCLK_0, FN_SEL_CANCLK_1, FN_SEL_CANCLK_2, FN_SEL_CANCLK_3,
423 FN_SEL_IIC8_0, FN_SEL_IIC8_1, FN_SEL_IIC8_2,
424 FN_SEL_IIC7_0, FN_SEL_IIC7_1, FN_SEL_IIC7_2,
425 FN_SEL_IIC4_0, FN_SEL_IIC4_1, FN_SEL_IIC4_2,
426 FN_SEL_IIC3_0, FN_SEL_IIC3_1, FN_SEL_IIC3_2, FN_SEL_IIC3_3,
427 FN_SEL_SCIF3_0, FN_SEL_SCIF3_1, FN_SEL_SCIF3_2, FN_SEL_SCIF3_3,
428 FN_SEL_IEB_0, FN_SEL_IEB_1, FN_SEL_IEB_2,
429 FN_SEL_MMC_0, FN_SEL_MMC_1,
430 FN_SEL_SCIF5_0, FN_SEL_SCIF5_1,
431 FN_SEL_IIC2_0, FN_SEL_IIC2_1, FN_SEL_IIC2_2, FN_SEL_IIC2_3,
432 FN_SEL_IIC1_0, FN_SEL_IIC1_1, FN_SEL_IIC1_2, FN_SEL_IIC1_3,
433 FN_SEL_IIC1_4,
434 FN_SEL_IIC0_0, FN_SEL_IIC0_1, FN_SEL_IIC0_2,
435
436 /* MOD_SEL4 */
437 FN_SEL_SOF1_0, FN_SEL_SOF1_1, FN_SEL_SOF1_2, FN_SEL_SOF1_3,
438 FN_SEL_SOF1_4,
439 FN_SEL_HSCIF0_0, FN_SEL_HSCIF0_1, FN_SEL_HSCIF0_2,
440 FN_SEL_DIS_0, FN_SEL_DIS_1, FN_SEL_DIS_2,
441 FN_SEL_RAD_0, FN_SEL_RAD_1,
442 FN_SEL_RCN_0, FN_SEL_RCN_1,
443 FN_SEL_RSP_0, FN_SEL_RSP_1,
444 FN_SEL_SCIF2_0, FN_SEL_SCIF2_1, FN_SEL_SCIF2_2, FN_SEL_SCIF2_3,
445 FN_SEL_SCIF2_4,
446 FN_SEL_SOF2_0, FN_SEL_SOF2_1, FN_SEL_SOF2_2, FN_SEL_SOF2_3,
447 FN_SEL_SOF2_4,
448 FN_SEL_SSI1_0, FN_SEL_SSI1_1,
449 FN_SEL_SSI0_0, FN_SEL_SSI0_1,
450 FN_SEL_SSP_0, FN_SEL_SSP_1, FN_SEL_SSP_2,
451 PINMUX_FUNCTION_END,
452
453 PINMUX_MARK_BEGIN,
454
455 EX_CS0_N_MARK, RD_N_MARK,
456
457 AUDIO_CLKA_MARK,
458
459 VI0_CLK_MARK, VI0_DATA0_VI0_B0_MARK, VI0_DATA1_VI0_B1_MARK,
460 VI0_DATA2_VI0_B2_MARK, VI0_DATA4_VI0_B4_MARK, VI0_DATA5_VI0_B5_MARK,
461 VI0_DATA6_VI0_B6_MARK, VI0_DATA7_VI0_B7_MARK,
462
463 SD1_CLK_MARK,
464
465 USB0_PWEN_MARK, USB0_OVC_MARK, USB1_PWEN_MARK, USB1_OVC_MARK,
466 DU0_DOTCLKIN_MARK,
467
468 /* IPSR0 */
469 D0_MARK, D1_MARK, D2_MARK, D3_MARK, D4_MARK, D5_MARK,
470 D6_MARK, D7_MARK, D8_MARK,
471 D9_MARK, D10_MARK, D11_MARK, D12_MARK, D13_MARK, D14_MARK, D15_MARK,
472 A0_MARK, ATAWR0_N_C_MARK, MSIOF0_SCK_B_MARK, SCL0_C_MARK, PWM2_B_MARK,
473 A1_MARK, MSIOF0_SYNC_B_MARK, A2_MARK, MSIOF0_SS1_B_MARK,
474 A3_MARK, MSIOF0_SS2_B_MARK, A4_MARK, MSIOF0_TXD_B_MARK,
475 A5_MARK, MSIOF0_RXD_B_MARK, A6_MARK, MSIOF1_SCK_MARK,
476
477 /* IPSR1 */
478 A7_MARK, MSIOF1_SYNC_MARK, A8_MARK, MSIOF1_SS1_MARK, SCL0_MARK,
479 A9_MARK, MSIOF1_SS2_MARK, SDA0_MARK,
480 A10_MARK, MSIOF1_TXD_MARK, MSIOF1_TXD_D_MARK,
481 A11_MARK, MSIOF1_RXD_MARK, SCL3_D_MARK, MSIOF1_RXD_D_MARK,
482 A12_MARK, FMCLK_MARK, SDA3_D_MARK, MSIOF1_SCK_D_MARK,
483 A13_MARK, ATAG0_N_C_MARK, BPFCLK_MARK, MSIOF1_SS1_D_MARK,
484 A14_MARK, ATADIR0_N_C_MARK, FMIN_MARK, FMIN_C_MARK, MSIOF1_SYNC_D_MARK,
485 A15_MARK, BPFCLK_C_MARK,
486 A16_MARK, DREQ2_B_MARK, FMCLK_C_MARK, SCIFA1_SCK_B_MARK,
487 A17_MARK, DACK2_B_MARK, SDA0_C_MARK,
488 A18_MARK, DREQ1_MARK, SCIFA1_RXD_C_MARK, SCIFB1_RXD_C_MARK,
489
490 /* IPSR2 */
491 A19_MARK, DACK1_MARK, SCIFA1_TXD_C_MARK,
492 SCIFB1_TXD_C_MARK, SCIFB1_SCK_B_MARK,
493 A20_MARK, SPCLK_MARK,
494 A21_MARK, ATAWR0_N_B_MARK, MOSI_IO0_MARK,
495 A22_MARK, MISO_IO1_MARK, FMCLK_B_MARK, TX0_MARK, SCIFA0_TXD_MARK,
496 A23_MARK, IO2_MARK, BPFCLK_B_MARK, RX0_MARK, SCIFA0_RXD_MARK,
497 A24_MARK, DREQ2_MARK, IO3_MARK, TX1_MARK, SCIFA1_TXD_MARK,
498 A25_MARK, DACK2_MARK, SSL_MARK, DREQ1_C_MARK,
499 RX1_MARK, SCIFA1_RXD_MARK,
500 CS0_N_MARK, ATAG0_N_B_MARK, SCL1_MARK,
501 CS1_N_A26_MARK, ATADIR0_N_B_MARK, SDA1_MARK,
502 EX_CS1_N_MARK, MSIOF2_SCK_MARK,
503 EX_CS2_N_MARK, ATAWR0_N_MARK, MSIOF2_SYNC_MARK,
504 EX_CS3_N_MARK, ATADIR0_N_MARK, MSIOF2_TXD_MARK,
505 ATAG0_N_MARK, EX_WAIT1_MARK,
506
507 /* IPSR3 */
508 EX_CS4_N_MARK, ATARD0_N_MARK, MSIOF2_RXD_MARK, EX_WAIT2_MARK,
509 EX_CS5_N_MARK, ATACS00_N_MARK, MSIOF2_SS1_MARK, HRX1_B_MARK,
510 SCIFB1_RXD_B_MARK, PWM1_MARK, TPU_TO1_MARK,
511 BS_N_MARK, ATACS10_N_MARK, MSIOF2_SS2_MARK, HTX1_B_MARK,
512 SCIFB1_TXD_B_MARK, PWM2_MARK, TPU_TO2_MARK,
513 RD_WR_N_MARK, HRX2_B_MARK, FMIN_B_MARK,
514 SCIFB0_RXD_B_MARK, DREQ1_D_MARK,
515 WE0_N_MARK, HCTS2_N_B_MARK, SCIFB0_TXD_B_MARK,
516 WE1_N_MARK, ATARD0_N_B_MARK, HTX2_B_MARK, SCIFB0_RTS_N_B_MARK,
517 EX_WAIT0_MARK, HRTS2_N_B_MARK, SCIFB0_CTS_N_B_MARK,
518 DREQ0_MARK, PWM3_MARK, TPU_TO3_MARK,
519 DACK0_MARK, DRACK0_MARK, REMOCON_MARK,
520 SPEEDIN_MARK, HSCK0_C_MARK, HSCK2_C_MARK, SCIFB0_SCK_B_MARK,
521 SCIFB2_SCK_B_MARK, DREQ2_C_MARK, HTX2_D_MARK,
522 SSI_SCK0129_MARK, HRX0_C_MARK, HRX2_C_MARK,
523 SCIFB0_RXD_C_MARK, SCIFB2_RXD_C_MARK,
524 SSI_WS0129_MARK, HTX0_C_MARK, HTX2_C_MARK,
525 SCIFB0_TXD_C_MARK, SCIFB2_TXD_C_MARK,
526
527 /* IPSR4 */
528 SSI_SDATA0_MARK, SCL0_B_MARK, SCL7_B_MARK, MSIOF2_SCK_C_MARK,
529 SSI_SCK1_MARK, SDA0_B_MARK, SDA7_B_MARK,
530 MSIOF2_SYNC_C_MARK, GLO_I0_D_MARK,
531 SSI_WS1_MARK, SCL1_B_MARK, SCL8_B_MARK,
532 MSIOF2_TXD_C_MARK, GLO_I1_D_MARK,
533 SSI_SDATA1_MARK, SDA1_B_MARK, SDA8_B_MARK, MSIOF2_RXD_C_MARK,
534 SSI_SCK2_MARK, SCL2_MARK, GPS_CLK_B_MARK, GLO_Q0_D_MARK, HSCK1_E_MARK,
535 SSI_WS2_MARK, SDA2_MARK, GPS_SIGN_B_MARK, RX2_E_MARK,
536 GLO_Q1_D_MARK, HCTS1_N_E_MARK,
537 SSI_SDATA2_MARK, GPS_MAG_B_MARK, TX2_E_MARK, HRTS1_N_E_MARK,
538 SSI_SCK34_MARK, SSI_WS34_MARK, SSI_SDATA3_MARK,
539 SSI_SCK4_MARK, GLO_SS_D_MARK,
540 SSI_WS4_MARK, GLO_RFON_D_MARK,
541 SSI_SDATA4_MARK, MSIOF2_SCK_D_MARK,
542 SSI_SCK5_MARK, MSIOF1_SCK_C_MARK, TS_SDATA0_MARK, GLO_I0_MARK,
543 MSIOF2_SYNC_D_MARK, VI1_R2_B_MARK,
544
545 /* IPSR5 */
546 SSI_WS5_MARK, MSIOF1_SYNC_C_MARK, TS_SCK0_MARK, GLO_I1_MARK,
547 MSIOF2_TXD_D_MARK, VI1_R3_B_MARK,
548 SSI_SDATA5_MARK, MSIOF1_TXD_C_MARK, TS_SDEN0_MARK, GLO_Q0_MARK,
549 MSIOF2_SS1_D_MARK, VI1_R4_B_MARK,
550 SSI_SCK6_MARK, MSIOF1_RXD_C_MARK, TS_SPSYNC0_MARK, GLO_Q1_MARK,
551 MSIOF2_RXD_D_MARK, VI1_R5_B_MARK,
552 SSI_WS6_MARK, GLO_SCLK_MARK, MSIOF2_SS2_D_MARK, VI1_R6_B_MARK,
553 SSI_SDATA6_MARK, STP_IVCXO27_0_B_MARK, GLO_SDATA_MARK, VI1_R7_B_MARK,
554 SSI_SCK78_MARK, STP_ISCLK_0_B_MARK, GLO_SS_MARK,
555 SSI_WS78_MARK, TX0_D_MARK, STP_ISD_0_B_MARK, GLO_RFON_MARK,
556 SSI_SDATA7_MARK, RX0_D_MARK, STP_ISEN_0_B_MARK,
557 SSI_SDATA8_MARK, TX1_D_MARK, STP_ISSYNC_0_B_MARK,
558 SSI_SCK9_MARK, RX1_D_MARK, GLO_SCLK_D_MARK,
559 SSI_WS9_MARK, TX3_D_MARK, CAN0_TX_D_MARK, GLO_SDATA_D_MARK,
560 SSI_SDATA9_MARK, RX3_D_MARK, CAN0_RX_D_MARK,
561
562 /* IPSR6 */
563 AUDIO_CLKB_MARK, STP_OPWM_0_B_MARK, MSIOF1_SCK_B_MARK,
564 SCIF_CLK_MARK, BPFCLK_E_MARK,
565 AUDIO_CLKC_MARK, SCIFB0_SCK_C_MARK, MSIOF1_SYNC_B_MARK, RX2_MARK,
566 SCIFA2_RXD_MARK, FMIN_E_MARK,
567 AUDIO_CLKOUT_MARK, MSIOF1_SS1_B_MARK, TX2_MARK, SCIFA2_TXD_MARK,
568 IRQ0_MARK, SCIFB1_RXD_D_MARK, INTC_IRQ0_N_MARK,
569 IRQ1_MARK, SCIFB1_SCK_C_MARK, INTC_IRQ1_N_MARK,
570 IRQ2_MARK, SCIFB1_TXD_D_MARK, INTC_IRQ2_N_MARK,
571 IRQ3_MARK, SCL4_C_MARK, MSIOF2_TXD_E_MARK, INTC_IRQ3_N_MARK,
572 IRQ4_MARK, HRX1_C_MARK, SDA4_C_MARK,
573 MSIOF2_RXD_E_MARK, INTC_IRQ4_N_MARK,
574 IRQ5_MARK, HTX1_C_MARK, SCL1_E_MARK, MSIOF2_SCK_E_MARK,
575 IRQ6_MARK, HSCK1_C_MARK, MSIOF1_SS2_B_MARK,
576 SDA1_E_MARK, MSIOF2_SYNC_E_MARK,
577 IRQ7_MARK, HCTS1_N_C_MARK, MSIOF1_TXD_B_MARK,
578 GPS_CLK_C_MARK, GPS_CLK_D_MARK,
579 IRQ8_MARK, HRTS1_N_C_MARK, MSIOF1_RXD_B_MARK,
580 GPS_SIGN_C_MARK, GPS_SIGN_D_MARK,
581
582 /* IPSR7 */
583 IRQ9_MARK, DU1_DOTCLKIN_B_MARK, CAN_CLK_D_MARK, GPS_MAG_C_MARK,
584 SCIF_CLK_B_MARK, GPS_MAG_D_MARK,
585 DU1_DR0_MARK, LCDOUT0_MARK, VI1_DATA0_B_MARK, TX0_B_MARK,
586 SCIFA0_TXD_B_MARK, MSIOF2_SCK_B_MARK,
587 DU1_DR1_MARK, LCDOUT1_MARK, VI1_DATA1_B_MARK, RX0_B_MARK,
588 SCIFA0_RXD_B_MARK, MSIOF2_SYNC_B_MARK,
589 DU1_DR2_MARK, LCDOUT2_MARK, SSI_SCK0129_B_MARK,
590 DU1_DR3_MARK, LCDOUT3_MARK, SSI_WS0129_B_MARK,
591 DU1_DR4_MARK, LCDOUT4_MARK, SSI_SDATA0_B_MARK,
592 DU1_DR5_MARK, LCDOUT5_MARK, SSI_SCK1_B_MARK,
593 DU1_DR6_MARK, LCDOUT6_MARK, SSI_WS1_B_MARK,
594 DU1_DR7_MARK, LCDOUT7_MARK, SSI_SDATA1_B_MARK,
595 DU1_DG0_MARK, LCDOUT8_MARK, VI1_DATA2_B_MARK, TX1_B_MARK,
596 SCIFA1_TXD_B_MARK, MSIOF2_SS1_B_MARK,
597 DU1_DG1_MARK, LCDOUT9_MARK, VI1_DATA3_B_MARK, RX1_B_MARK,
598 SCIFA1_RXD_B_MARK, MSIOF2_SS2_B_MARK,
599 DU1_DG2_MARK, LCDOUT10_MARK, VI1_DATA4_B_MARK, SCIF1_SCK_B_MARK,
600 SCIFA1_SCK_MARK, SSI_SCK78_B_MARK,
601
602 /* IPSR8 */
603 DU1_DG3_MARK, LCDOUT11_MARK, VI1_DATA5_B_MARK, SSI_WS78_B_MARK,
604 DU1_DG4_MARK, LCDOUT12_MARK, VI1_DATA6_B_MARK, HRX0_B_MARK,
605 SCIFB2_RXD_B_MARK, SSI_SDATA7_B_MARK,
606 DU1_DG5_MARK, LCDOUT13_MARK, VI1_DATA7_B_MARK, HCTS0_N_B_MARK,
607 SCIFB2_TXD_B_MARK, SSI_SDATA8_B_MARK,
608 DU1_DG6_MARK, LCDOUT14_MARK, HRTS0_N_B_MARK,
609 SCIFB2_CTS_N_B_MARK, SSI_SCK9_B_MARK,
610 DU1_DG7_MARK, LCDOUT15_MARK, HTX0_B_MARK,
611 SCIFB2_RTS_N_B_MARK, SSI_WS9_B_MARK,
612 DU1_DB0_MARK, LCDOUT16_MARK, VI1_CLK_B_MARK, TX2_B_MARK,
613 SCIFA2_TXD_B_MARK, MSIOF2_TXD_B_MARK,
614 DU1_DB1_MARK, LCDOUT17_MARK, VI1_HSYNC_N_B_MARK, RX2_B_MARK,
615 SCIFA2_RXD_B_MARK, MSIOF2_RXD_B_MARK,
616 DU1_DB2_MARK, LCDOUT18_MARK, VI1_VSYNC_N_B_MARK, SCIF2_SCK_B_MARK,
617 SCIFA2_SCK_MARK, SSI_SDATA9_B_MARK,
618 DU1_DB3_MARK, LCDOUT19_MARK, VI1_CLKENB_B_MARK,
619 DU1_DB4_MARK, LCDOUT20_MARK, VI1_FIELD_B_MARK, CAN1_RX_MARK,
620 DU1_DB5_MARK, LCDOUT21_MARK, TX3_MARK, SCIFA3_TXD_MARK, CAN1_TX_MARK,
621
622 /* IPSR9 */
623 DU1_DB6_MARK, LCDOUT22_MARK, SCL3_C_MARK, RX3_MARK, SCIFA3_RXD_MARK,
624 DU1_DB7_MARK, LCDOUT23_MARK, SDA3_C_MARK,
625 SCIF3_SCK_MARK, SCIFA3_SCK_MARK,
626 DU1_DOTCLKIN_MARK, QSTVA_QVS_MARK,
627 DU1_DOTCLKOUT0_MARK, QCLK_MARK,
628 DU1_DOTCLKOUT1_MARK, QSTVB_QVE_MARK, CAN0_TX_MARK,
629 TX3_B_MARK, SCL2_B_MARK, PWM4_MARK,
630 DU1_EXHSYNC_DU1_HSYNC_MARK, QSTH_QHS_MARK,
631 DU1_EXVSYNC_DU1_VSYNC_MARK, QSTB_QHE_MARK,
632 DU1_EXODDF_DU1_ODDF_DISP_CDE_MARK, QCPV_QDE_MARK,
633 CAN0_RX_MARK, RX3_B_MARK, SDA2_B_MARK,
634 DU1_DISP_MARK, QPOLA_MARK,
635 DU1_CDE_MARK, QPOLB_MARK, PWM4_B_MARK,
636 VI0_CLKENB_MARK, TX4_MARK, SCIFA4_TXD_MARK, TS_SDATA0_D_MARK,
637 VI0_FIELD_MARK, RX4_MARK, SCIFA4_RXD_MARK, TS_SCK0_D_MARK,
638 VI0_HSYNC_N_MARK, TX5_MARK, SCIFA5_TXD_MARK, TS_SDEN0_D_MARK,
639 VI0_VSYNC_N_MARK, RX5_MARK, SCIFA5_RXD_MARK, TS_SPSYNC0_D_MARK,
640 VI0_DATA3_VI0_B3_MARK, SCIF3_SCK_B_MARK, SCIFA3_SCK_B_MARK,
641 VI0_G0_MARK, SCL8_MARK, STP_IVCXO27_0_C_MARK, SCL4_MARK,
642 HCTS2_N_MARK, SCIFB2_CTS_N_MARK, ATAWR1_N_MARK,
643
644 /* IPSR10 */
645 VI0_G1_MARK, SDA8_MARK, STP_ISCLK_0_C_MARK, SDA4_MARK,
646 HRTS2_N_MARK, SCIFB2_RTS_N_MARK, ATADIR1_N_MARK,
647 VI0_G2_MARK, VI2_HSYNC_N_MARK, STP_ISD_0_C_MARK, SCL3_B_MARK,
648 HSCK2_MARK, SCIFB2_SCK_MARK, ATARD1_N_MARK,
649 VI0_G3_MARK, VI2_VSYNC_N_MARK, STP_ISEN_0_C_MARK, SDA3_B_MARK,
650 HRX2_MARK, SCIFB2_RXD_MARK, ATACS01_N_MARK,
651 VI0_G4_MARK, VI2_CLKENB_MARK, STP_ISSYNC_0_C_MARK,
652 HTX2_MARK, SCIFB2_TXD_MARK, SCIFB0_SCK_D_MARK,
653 VI0_G5_MARK, VI2_FIELD_MARK, STP_OPWM_0_C_MARK, FMCLK_D_MARK,
654 CAN0_TX_E_MARK, HTX1_D_MARK, SCIFB0_TXD_D_MARK,
655 VI0_G6_MARK, VI2_CLK_MARK, BPFCLK_D_MARK,
656 VI0_G7_MARK, VI2_DATA0_MARK, FMIN_D_MARK,
657 VI0_R0_MARK, VI2_DATA1_MARK, GLO_I0_B_MARK,
658 TS_SDATA0_C_MARK, ATACS11_N_MARK,
659 VI0_R1_MARK, VI2_DATA2_MARK, GLO_I1_B_MARK,
660 TS_SCK0_C_MARK, ATAG1_N_MARK,
661 VI0_R2_MARK, VI2_DATA3_MARK, GLO_Q0_B_MARK, TS_SDEN0_C_MARK,
662 VI0_R3_MARK, VI2_DATA4_MARK, GLO_Q1_B_MARK, TS_SPSYNC0_C_MARK,
663 VI0_R4_MARK, VI2_DATA5_MARK, GLO_SCLK_B_MARK, TX0_C_MARK, SCL1_D_MARK,
664
665 /* IPSR11 */
666 VI0_R5_MARK, VI2_DATA6_MARK, GLO_SDATA_B_MARK, RX0_C_MARK, SDA1_D_MARK,
667 VI0_R6_MARK, VI2_DATA7_MARK, GLO_SS_B_MARK, TX1_C_MARK, SCL4_B_MARK,
668 VI0_R7_MARK, GLO_RFON_B_MARK, RX1_C_MARK, CAN0_RX_E_MARK,
669 SDA4_B_MARK, HRX1_D_MARK, SCIFB0_RXD_D_MARK,
670 VI1_HSYNC_N_MARK, AVB_RXD0_MARK, TS_SDATA0_B_MARK,
671 TX4_B_MARK, SCIFA4_TXD_B_MARK,
672 VI1_VSYNC_N_MARK, AVB_RXD1_MARK, TS_SCK0_B_MARK,
673 RX4_B_MARK, SCIFA4_RXD_B_MARK,
674 VI1_CLKENB_MARK, AVB_RXD2_MARK, TS_SDEN0_B_MARK,
675 VI1_FIELD_MARK, AVB_RXD3_MARK, TS_SPSYNC0_B_MARK,
676 VI1_CLK_MARK, AVB_RXD4_MARK, VI1_DATA0_MARK, AVB_RXD5_MARK,
677 VI1_DATA1_MARK, AVB_RXD6_MARK, VI1_DATA2_MARK, AVB_RXD7_MARK,
678 VI1_DATA3_MARK, AVB_RX_ER_MARK, VI1_DATA4_MARK, AVB_MDIO_MARK,
679 VI1_DATA5_MARK, AVB_RX_DV_MARK, VI1_DATA6_MARK, AVB_MAGIC_MARK,
680 VI1_DATA7_MARK, AVB_MDC_MARK,
681 ETH_MDIO_MARK, AVB_RX_CLK_MARK, SCL2_C_MARK,
682 ETH_CRS_DV_MARK, AVB_LINK_MARK, SDA2_C_MARK,
683
684 /* IPSR12 */
685 ETH_RX_ER_MARK, AVB_CRS_MARK, SCL3_MARK, SCL7_MARK,
686 ETH_RXD0_MARK, AVB_PHY_INT_MARK, SDA3_MARK, SDA7_MARK,
687 ETH_RXD1_MARK, AVB_GTXREFCLK_MARK, CAN0_TX_C_MARK,
688 SCL2_D_MARK, MSIOF1_RXD_E_MARK,
689 ETH_LINK_MARK, AVB_TXD0_MARK, CAN0_RX_C_MARK,
690 SDA2_D_MARK, MSIOF1_SCK_E_MARK,
691 ETH_REFCLK_MARK, AVB_TXD1_MARK, SCIFA3_RXD_B_MARK,
692 CAN1_RX_C_MARK, MSIOF1_SYNC_E_MARK,
693 ETH_TXD1_MARK, AVB_TXD2_MARK, SCIFA3_TXD_B_MARK,
694 CAN1_TX_C_MARK, MSIOF1_TXD_E_MARK,
695 ETH_TX_EN_MARK, AVB_TXD3_MARK, TCLK1_B_MARK, CAN_CLK_B_MARK,
696 ETH_MAGIC_MARK, AVB_TXD4_MARK, IETX_C_MARK,
697 ETH_TXD0_MARK, AVB_TXD5_MARK, IECLK_C_MARK,
698 ETH_MDC_MARK, AVB_TXD6_MARK, IERX_C_MARK,
699 STP_IVCXO27_0_MARK, AVB_TXD7_MARK, SCIFB2_TXD_D_MARK,
700 ADIDATA_B_MARK, MSIOF0_SYNC_C_MARK,
701 STP_ISCLK_0_MARK, AVB_TX_EN_MARK, SCIFB2_RXD_D_MARK,
702 ADICS_SAMP_B_MARK, MSIOF0_SCK_C_MARK,
703
704 /* IPSR13 */
705 STP_ISD_0_MARK, AVB_TX_ER_MARK, SCIFB2_SCK_C_MARK,
706 ADICLK_B_MARK, MSIOF0_SS1_C_MARK,
707 STP_ISEN_0_MARK, AVB_TX_CLK_MARK, ADICHS0_B_MARK, MSIOF0_SS2_C_MARK,
708 STP_ISSYNC_0_MARK, AVB_COL_MARK, ADICHS1_B_MARK, MSIOF0_RXD_C_MARK,
709 STP_OPWM_0_MARK, AVB_GTX_CLK_MARK, PWM0_B_MARK,
710 ADICHS2_B_MARK, MSIOF0_TXD_C_MARK,
711 SD0_CLK_MARK, SPCLK_B_MARK, SD0_CMD_MARK, MOSI_IO0_B_MARK,
712 SD0_DATA0_MARK, MISO_IO1_B_MARK, SD0_DATA1_MARK, IO2_B_MARK,
713 SD0_DATA2_MARK, IO3_B_MARK, SD0_DATA3_MARK, SSL_B_MARK,
714 SD0_CD_MARK, MMC_D6_B_MARK, SIM0_RST_B_MARK, CAN0_RX_F_MARK,
715 SCIFA5_TXD_B_MARK, TX3_C_MARK,
716 SD0_WP_MARK, MMC_D7_B_MARK, SIM0_D_B_MARK, CAN0_TX_F_MARK,
717 SCIFA5_RXD_B_MARK, RX3_C_MARK,
718 SD1_CMD_MARK, REMOCON_B_MARK, SD1_DATA0_MARK, SPEEDIN_B_MARK,
719 SD1_DATA1_MARK, IETX_B_MARK, SD1_DATA2_MARK, IECLK_B_MARK,
720 SD1_DATA3_MARK, IERX_B_MARK,
721 SD1_CD_MARK, PWM0_MARK, TPU_TO0_MARK, SCL1_C_MARK,
722
723 /* IPSR14 */
724 SD1_WP_MARK, PWM1_B_MARK, SDA1_C_MARK,
725 SD2_CLK_MARK, MMC_CLK_MARK, SD2_CMD_MARK, MMC_CMD_MARK,
726 SD2_DATA0_MARK, MMC_D0_MARK, SD2_DATA1_MARK, MMC_D1_MARK,
727 SD2_DATA2_MARK, MMC_D2_MARK, SD2_DATA3_MARK, MMC_D3_MARK,
728 SD2_CD_MARK, MMC_D4_MARK, SCL8_C_MARK, TX5_B_MARK, SCIFA5_TXD_C_MARK,
729 SD2_WP_MARK, MMC_D5_MARK, SDA8_C_MARK, RX5_B_MARK, SCIFA5_RXD_C_MARK,
730 MSIOF0_SCK_MARK, RX2_C_MARK, ADIDATA_MARK,
731 VI1_CLK_C_MARK, VI1_G0_B_MARK,
732 MSIOF0_SYNC_MARK, TX2_C_MARK, ADICS_SAMP_MARK,
733 VI1_CLKENB_C_MARK, VI1_G1_B_MARK,
734 MSIOF0_TXD_MARK, ADICLK_MARK, VI1_FIELD_C_MARK, VI1_G2_B_MARK,
735 MSIOF0_RXD_MARK, ADICHS0_MARK, VI1_DATA0_C_MARK, VI1_G3_B_MARK,
736 MSIOF0_SS1_MARK, MMC_D6_MARK, ADICHS1_MARK, TX0_E_MARK,
737 VI1_HSYNC_N_C_MARK, SCL7_C_MARK, VI1_G4_B_MARK,
738 MSIOF0_SS2_MARK, MMC_D7_MARK, ADICHS2_MARK, RX0_E_MARK,
739 VI1_VSYNC_N_C_MARK, SDA7_C_MARK, VI1_G5_B_MARK,
740
741 /* IPSR15 */
742 SIM0_RST_MARK, IETX_MARK, CAN1_TX_D_MARK,
743 SIM0_CLK_MARK, IECLK_MARK, CAN_CLK_C_MARK,
744 SIM0_D_MARK, IERX_MARK, CAN1_RX_D_MARK,
745 GPS_CLK_MARK, DU1_DOTCLKIN_C_MARK, AUDIO_CLKB_B_MARK,
746 PWM5_B_MARK, SCIFA3_TXD_C_MARK,
747 GPS_SIGN_MARK, TX4_C_MARK, SCIFA4_TXD_C_MARK, PWM5_MARK,
748 VI1_G6_B_MARK, SCIFA3_RXD_C_MARK,
749 GPS_MAG_MARK, RX4_C_MARK, SCIFA4_RXD_C_MARK, PWM6_MARK,
750 VI1_G7_B_MARK, SCIFA3_SCK_C_MARK,
751 HCTS0_N_MARK, SCIFB0_CTS_N_MARK, GLO_I0_C_MARK,
752 TCLK1_MARK, VI1_DATA1_C_MARK,
753 HRTS0_N_MARK, SCIFB0_RTS_N_MARK, GLO_I1_C_MARK, VI1_DATA2_C_MARK,
754 HSCK0_MARK, SCIFB0_SCK_MARK, GLO_Q0_C_MARK, CAN_CLK_MARK,
755 TCLK2_MARK, VI1_DATA3_C_MARK,
756 HRX0_MARK, SCIFB0_RXD_MARK, GLO_Q1_C_MARK,
757 CAN0_RX_B_MARK, VI1_DATA4_C_MARK,
758 HTX0_MARK, SCIFB0_TXD_MARK, GLO_SCLK_C_MARK,
759 CAN0_TX_B_MARK, VI1_DATA5_C_MARK,
760
761 /* IPSR16 */
762 HRX1_MARK, SCIFB1_RXD_MARK, VI1_R0_B_MARK,
763 GLO_SDATA_C_MARK, VI1_DATA6_C_MARK,
764 HTX1_MARK, SCIFB1_TXD_MARK, VI1_R1_B_MARK,
765 GLO_SS_C_MARK, VI1_DATA7_C_MARK,
766 HSCK1_MARK, SCIFB1_SCK_MARK, MLB_CK_MARK, GLO_RFON_C_MARK,
767 HCTS1_N_MARK, SCIFB1_CTS_N_MARK, MLB_SIG_MARK, CAN1_TX_B_MARK,
768 HRTS1_N_MARK, SCIFB1_RTS_N_MARK, MLB_DAT_MARK, CAN1_RX_B_MARK,
769 PINMUX_MARK_END,
770};
771
772static const u16 pinmux_data[] = {
773 PINMUX_DATA_GP_ALL(), /* PINMUX_DATA(GP_M_N_DATA, GP_M_N_FN...), */
774
775 PINMUX_DATA(EX_CS0_N_MARK, FN_EX_CS0_N),
776 PINMUX_DATA(RD_N_MARK, FN_RD_N),
777 PINMUX_DATA(AUDIO_CLKA_MARK, FN_AUDIO_CLKA),
778 PINMUX_DATA(VI0_CLK_MARK, FN_VI0_CLK),
779 PINMUX_DATA(VI0_DATA0_VI0_B0_MARK, FN_VI0_DATA0_VI0_B0),
780 PINMUX_DATA(VI0_DATA1_VI0_B1_MARK, FN_VI0_DATA1_VI0_B1),
781 PINMUX_DATA(VI0_DATA2_VI0_B2_MARK, FN_VI0_DATA2_VI0_B2),
782 PINMUX_DATA(VI0_DATA4_VI0_B4_MARK, FN_VI0_DATA4_VI0_B4),
783 PINMUX_DATA(VI0_DATA5_VI0_B5_MARK, FN_VI0_DATA5_VI0_B5),
784 PINMUX_DATA(VI0_DATA6_VI0_B6_MARK, FN_VI0_DATA6_VI0_B6),
785 PINMUX_DATA(VI0_DATA7_VI0_B7_MARK, FN_VI0_DATA7_VI0_B7),
786 PINMUX_DATA(USB0_PWEN_MARK, FN_USB0_PWEN),
787 PINMUX_DATA(USB0_OVC_MARK, FN_USB0_OVC),
788 PINMUX_DATA(USB1_PWEN_MARK, FN_USB1_PWEN),
789 PINMUX_DATA(USB1_OVC_MARK, FN_USB1_OVC),
790 PINMUX_DATA(DU0_DOTCLKIN_MARK, FN_DU0_DOTCLKIN),
791
792 /* IPSR0 */
793 PINMUX_IPSR_DATA(IP0_0, D0),
794 PINMUX_IPSR_DATA(IP0_1, D1),
795 PINMUX_IPSR_DATA(IP0_2, D2),
796 PINMUX_IPSR_DATA(IP0_3, D3),
797 PINMUX_IPSR_DATA(IP0_4, D4),
798 PINMUX_IPSR_DATA(IP0_5, D5),
799 PINMUX_IPSR_DATA(IP0_6, D6),
800 PINMUX_IPSR_DATA(IP0_7, D7),
801 PINMUX_IPSR_DATA(IP0_8, D8),
802 PINMUX_IPSR_DATA(IP0_9, D9),
803 PINMUX_IPSR_DATA(IP0_10, D10),
804 PINMUX_IPSR_DATA(IP0_11, D11),
805 PINMUX_IPSR_DATA(IP0_12, D12),
806 PINMUX_IPSR_DATA(IP0_13, D13),
807 PINMUX_IPSR_DATA(IP0_14, D14),
808 PINMUX_IPSR_DATA(IP0_15, D15),
809 PINMUX_IPSR_DATA(IP0_18_16, A0),
810 PINMUX_IPSR_MODSEL_DATA(IP0_18_16, ATAWR0_N_C, SEL_LBS_2),
811 PINMUX_IPSR_MODSEL_DATA(IP0_18_16, MSIOF0_SCK_B, SEL_SOF0_1),
812 PINMUX_IPSR_MODSEL_DATA(IP0_18_16, SCL0_C, SEL_IIC0_2),
813 PINMUX_IPSR_DATA(IP0_18_16, PWM2_B),
814 PINMUX_IPSR_DATA(IP0_20_19, A1),
815 PINMUX_IPSR_MODSEL_DATA(IP0_20_19, MSIOF0_SYNC_B, SEL_SOF0_1),
816 PINMUX_IPSR_DATA(IP0_22_21, A2),
817 PINMUX_IPSR_MODSEL_DATA(IP0_22_21, MSIOF0_SS1_B, SEL_SOF0_1),
818 PINMUX_IPSR_DATA(IP0_24_23, A3),
819 PINMUX_IPSR_MODSEL_DATA(IP0_24_23, MSIOF0_SS2_B, SEL_SOF0_1),
820 PINMUX_IPSR_DATA(IP0_26_25, A4),
821 PINMUX_IPSR_MODSEL_DATA(IP0_26_25, MSIOF0_TXD_B, SEL_SOF0_1),
822 PINMUX_IPSR_DATA(IP0_28_27, A5),
823 PINMUX_IPSR_MODSEL_DATA(IP0_28_27, MSIOF0_RXD_B, SEL_SOF0_1),
824 PINMUX_IPSR_DATA(IP0_30_29, A6),
825 PINMUX_IPSR_MODSEL_DATA(IP0_30_29, MSIOF1_SCK, SEL_SOF1_0),
826
827 /* IPSR1 */
828 PINMUX_IPSR_DATA(IP1_1_0, A7),
829 PINMUX_IPSR_MODSEL_DATA(IP1_1_0, MSIOF1_SYNC, SEL_SOF1_0),
830 PINMUX_IPSR_DATA(IP1_3_2, A8),
831 PINMUX_IPSR_MODSEL_DATA(IP1_3_2, MSIOF1_SS1, SEL_SOF1_0),
832 PINMUX_IPSR_MODSEL_DATA(IP1_3_2, SCL0, SEL_IIC0_0),
833 PINMUX_IPSR_DATA(IP1_5_4, A9),
834 PINMUX_IPSR_MODSEL_DATA(IP1_5_4, MSIOF1_SS2, SEL_SOF1_0),
835 PINMUX_IPSR_MODSEL_DATA(IP1_5_4, SDA0, SEL_IIC0_0),
836 PINMUX_IPSR_DATA(IP1_7_6, A10),
837 PINMUX_IPSR_MODSEL_DATA(IP1_7_6, MSIOF1_TXD, SEL_SOF1_0),
838 PINMUX_IPSR_MODSEL_DATA(IP1_7_6, MSIOF1_TXD_D, SEL_SOF1_3),
839 PINMUX_IPSR_DATA(IP1_10_8, A11),
840 PINMUX_IPSR_MODSEL_DATA(IP1_10_8, MSIOF1_RXD, SEL_SOF1_0),
841 PINMUX_IPSR_MODSEL_DATA(IP1_10_8, SCL3_D, SEL_IIC3_3),
842 PINMUX_IPSR_MODSEL_DATA(IP1_10_8, MSIOF1_RXD_D, SEL_SOF1_3),
843 PINMUX_IPSR_DATA(IP1_13_11, A12),
844 PINMUX_IPSR_MODSEL_DATA(IP1_13_11, FMCLK, SEL_FM_0),
845 PINMUX_IPSR_MODSEL_DATA(IP1_13_11, SDA3_D, SEL_IIC3_3),
846 PINMUX_IPSR_MODSEL_DATA(IP1_13_11, MSIOF1_SCK_D, SEL_SOF1_3),
847 PINMUX_IPSR_DATA(IP1_16_14, A13),
848 PINMUX_IPSR_MODSEL_DATA(IP1_16_14, ATAG0_N_C, SEL_LBS_2),
849 PINMUX_IPSR_MODSEL_DATA(IP1_16_14, BPFCLK, SEL_FM_0),
850 PINMUX_IPSR_MODSEL_DATA(IP1_16_14, MSIOF1_SS1_D, SEL_SOF1_3),
851 PINMUX_IPSR_DATA(IP1_19_17, A14),
852 PINMUX_IPSR_MODSEL_DATA(IP1_19_17, ATADIR0_N_C, SEL_LBS_2),
853 PINMUX_IPSR_MODSEL_DATA(IP1_19_17, FMIN, SEL_FM_0),
854 PINMUX_IPSR_MODSEL_DATA(IP1_19_17, FMIN_C, SEL_FM_2),
855 PINMUX_IPSR_MODSEL_DATA(IP1_19_17, MSIOF1_SYNC_D, SEL_SOF1_3),
856 PINMUX_IPSR_DATA(IP1_22_20, A15),
857 PINMUX_IPSR_MODSEL_DATA(IP1_22_20, BPFCLK_C, SEL_FM_2),
858 PINMUX_IPSR_DATA(IP1_25_23, A16),
859 PINMUX_IPSR_MODSEL_DATA(IP1_25_23, DREQ2_B, SEL_LBS_1),
860 PINMUX_IPSR_MODSEL_DATA(IP1_25_23, FMCLK_C, SEL_FM_2),
861 PINMUX_IPSR_MODSEL_DATA(IP1_25_23, SCIFA1_SCK_B, SEL_SCIFA1_1),
862 PINMUX_IPSR_DATA(IP1_28_26, A17),
863 PINMUX_IPSR_MODSEL_DATA(IP1_28_26, DACK2_B, SEL_LBS_1),
864 PINMUX_IPSR_MODSEL_DATA(IP1_28_26, SDA0_C, SEL_IIC0_2),
865 PINMUX_IPSR_DATA(IP1_31_29, A18),
866 PINMUX_IPSR_MODSEL_DATA(IP1_31_29, DREQ1, SEL_LBS_0),
867 PINMUX_IPSR_MODSEL_DATA(IP1_31_29, SCIFA1_RXD_C, SEL_SCIFA1_2),
868 PINMUX_IPSR_MODSEL_DATA(IP1_31_29, SCIFB1_RXD_C, SEL_SCIFB1_2),
869
870 /* IPSR2 */
871 PINMUX_IPSR_DATA(IP2_2_0, A19),
872 PINMUX_IPSR_DATA(IP2_2_0, DACK1),
873 PINMUX_IPSR_MODSEL_DATA(IP2_2_0, SCIFA1_TXD_C, SEL_SCIFA1_2),
874 PINMUX_IPSR_MODSEL_DATA(IP2_2_0, SCIFB1_TXD_C, SEL_SCIFB1_2),
875 PINMUX_IPSR_MODSEL_DATA(IP2_2_0, SCIFB1_SCK_B, SEL_SCIFB1_0),
876 PINMUX_IPSR_DATA(IP2_2_0, A20),
877 PINMUX_IPSR_MODSEL_DATA(IP2_4_3, SPCLK, SEL_QSP_0),
878 PINMUX_IPSR_DATA(IP2_6_5, A21),
879 PINMUX_IPSR_MODSEL_DATA(IP2_6_5, ATAWR0_N_B, SEL_LBS_1),
880 PINMUX_IPSR_MODSEL_DATA(IP2_6_5, MOSI_IO0, SEL_QSP_0),
881 PINMUX_IPSR_DATA(IP2_9_7, A22),
882 PINMUX_IPSR_MODSEL_DATA(IP2_9_7, MISO_IO1, SEL_QSP_0),
883 PINMUX_IPSR_MODSEL_DATA(IP2_9_7, FMCLK_B, SEL_FM_1),
884 PINMUX_IPSR_MODSEL_DATA(IP2_9_7, TX0, SEL_SCIF0_0),
885 PINMUX_IPSR_MODSEL_DATA(IP2_9_7, SCIFA0_TXD, SEL_SCFA_0),
886 PINMUX_IPSR_DATA(IP2_12_10, A23),
887 PINMUX_IPSR_MODSEL_DATA(IP2_12_10, IO2, SEL_QSP_0),
888 PINMUX_IPSR_MODSEL_DATA(IP2_12_10, BPFCLK_B, SEL_FM_1),
889 PINMUX_IPSR_MODSEL_DATA(IP2_12_10, RX0, SEL_SCIF0_0),
890 PINMUX_IPSR_MODSEL_DATA(IP2_12_10, SCIFA0_RXD, SEL_SCFA_0),
891 PINMUX_IPSR_DATA(IP2_15_13, A24),
892 PINMUX_IPSR_MODSEL_DATA(IP2_15_13, DREQ2, SEL_LBS_0),
893 PINMUX_IPSR_MODSEL_DATA(IP2_15_13, IO3, SEL_QSP_0),
894 PINMUX_IPSR_MODSEL_DATA(IP2_15_13, TX1, SEL_SCIF1_0),
895 PINMUX_IPSR_MODSEL_DATA(IP2_15_13, SCIFA1_TXD, SEL_SCIFA1_0),
896 PINMUX_IPSR_DATA(IP2_18_16, A25),
897 PINMUX_IPSR_MODSEL_DATA(IP2_18_16, DACK2, SEL_LBS_0),
898 PINMUX_IPSR_MODSEL_DATA(IP2_18_16, SSL, SEL_QSP_0),
899 PINMUX_IPSR_MODSEL_DATA(IP2_18_16, DREQ1_C, SEL_LBS_2),
900 PINMUX_IPSR_MODSEL_DATA(IP2_18_16, RX1, SEL_SCIF1_0),
901 PINMUX_IPSR_MODSEL_DATA(IP2_18_16, SCIFA1_RXD, SEL_SCIFA1_0),
902 PINMUX_IPSR_DATA(IP2_20_19, CS0_N),
903 PINMUX_IPSR_MODSEL_DATA(IP2_20_19, ATAG0_N_B, SEL_LBS_1),
904 PINMUX_IPSR_MODSEL_DATA(IP2_20_19, SCL1, SEL_IIC1_0),
905 PINMUX_IPSR_DATA(IP2_22_21, CS1_N_A26),
906 PINMUX_IPSR_MODSEL_DATA(IP2_22_21, ATADIR0_N_B, SEL_LBS_1),
907 PINMUX_IPSR_MODSEL_DATA(IP2_22_21, SDA1, SEL_IIC1_0),
908 PINMUX_IPSR_DATA(IP2_24_23, EX_CS1_N),
909 PINMUX_IPSR_MODSEL_DATA(IP2_24_23, MSIOF2_SCK, SEL_SOF2_0),
910 PINMUX_IPSR_DATA(IP2_26_25, EX_CS2_N),
911 PINMUX_IPSR_MODSEL_DATA(IP2_26_25, ATAWR0_N, SEL_LBS_0),
912 PINMUX_IPSR_MODSEL_DATA(IP2_26_25, MSIOF2_SYNC, SEL_SOF2_0),
913 PINMUX_IPSR_DATA(IP2_29_27, EX_CS3_N),
914 PINMUX_IPSR_MODSEL_DATA(IP2_29_27, ATADIR0_N, SEL_LBS_0),
915 PINMUX_IPSR_MODSEL_DATA(IP2_29_27, MSIOF2_TXD, SEL_SOF2_0),
916 PINMUX_IPSR_MODSEL_DATA(IP2_29_27, ATAG0_N, SEL_LBS_0),
917 PINMUX_IPSR_DATA(IP2_29_27, EX_WAIT1),
918
919 /* IPSR3 */
920 PINMUX_IPSR_DATA(IP3_2_0, EX_CS4_N),
921 PINMUX_IPSR_MODSEL_DATA(IP3_2_0, ATARD0_N, SEL_LBS_0),
922 PINMUX_IPSR_MODSEL_DATA(IP3_2_0, MSIOF2_RXD, SEL_SOF2_0),
923 PINMUX_IPSR_DATA(IP3_2_0, EX_WAIT2),
924 PINMUX_IPSR_DATA(IP3_5_3, EX_CS5_N),
925 PINMUX_IPSR_DATA(IP3_5_3, ATACS00_N),
926 PINMUX_IPSR_MODSEL_DATA(IP3_5_3, MSIOF2_SS1, SEL_SOF2_0),
927 PINMUX_IPSR_MODSEL_DATA(IP3_5_3, HRX1_B, SEL_HSCIF1_1),
928 PINMUX_IPSR_MODSEL_DATA(IP3_5_3, SCIFB1_RXD_B, SEL_SCIFB1_1),
929 PINMUX_IPSR_DATA(IP3_5_3, PWM1),
930 PINMUX_IPSR_DATA(IP3_5_3, TPU_TO1),
931 PINMUX_IPSR_DATA(IP3_8_6, BS_N),
932 PINMUX_IPSR_DATA(IP3_8_6, ATACS10_N),
933 PINMUX_IPSR_MODSEL_DATA(IP3_8_6, MSIOF2_SS2, SEL_SOF2_0),
934 PINMUX_IPSR_MODSEL_DATA(IP3_8_6, HTX1_B, SEL_HSCIF1_1),
935 PINMUX_IPSR_MODSEL_DATA(IP3_8_6, SCIFB1_TXD_B, SEL_SCIFB1_1),
936 PINMUX_IPSR_DATA(IP3_8_6, PWM2),
937 PINMUX_IPSR_DATA(IP3_8_6, TPU_TO2),
938 PINMUX_IPSR_DATA(IP3_11_9, RD_WR_N),
939 PINMUX_IPSR_MODSEL_DATA(IP3_11_9, HRX2_B, SEL_HSCIF2_1),
940 PINMUX_IPSR_MODSEL_DATA(IP3_11_9, FMIN_B, SEL_FM_1),
941 PINMUX_IPSR_MODSEL_DATA(IP3_11_9, SCIFB0_RXD_B, SEL_SCIFB_1),
942 PINMUX_IPSR_MODSEL_DATA(IP3_11_9, DREQ1_D, SEL_LBS_1),
943 PINMUX_IPSR_DATA(IP3_13_12, WE0_N),
944 PINMUX_IPSR_MODSEL_DATA(IP3_13_12, HCTS2_N_B, SEL_HSCIF2_1),
945 PINMUX_IPSR_MODSEL_DATA(IP3_13_12, SCIFB0_TXD_B, SEL_SCIFB_1),
946 PINMUX_IPSR_DATA(IP3_15_14, WE1_N),
947 PINMUX_IPSR_MODSEL_DATA(IP3_15_14, ATARD0_N_B, SEL_LBS_1),
948 PINMUX_IPSR_MODSEL_DATA(IP3_15_14, HTX2_B, SEL_HSCIF2_1),
949 PINMUX_IPSR_MODSEL_DATA(IP3_15_14, SCIFB0_RTS_N_B, SEL_SCIFB_1),
950 PINMUX_IPSR_DATA(IP3_17_16, EX_WAIT0),
951 PINMUX_IPSR_MODSEL_DATA(IP3_17_16, HRTS2_N_B, SEL_HSCIF2_1),
952 PINMUX_IPSR_MODSEL_DATA(IP3_17_16, SCIFB0_CTS_N_B, SEL_SCIFB_1),
953 PINMUX_IPSR_DATA(IP3_19_18, DREQ0),
954 PINMUX_IPSR_DATA(IP3_19_18, PWM3),
955 PINMUX_IPSR_DATA(IP3_19_18, TPU_TO3),
956 PINMUX_IPSR_DATA(IP3_21_20, DACK0),
957 PINMUX_IPSR_DATA(IP3_21_20, DRACK0),
958 PINMUX_IPSR_MODSEL_DATA(IP3_21_20, REMOCON, SEL_RCN_0),
959 PINMUX_IPSR_MODSEL_DATA(IP3_24_22, SPEEDIN, SEL_RSP_0),
960 PINMUX_IPSR_MODSEL_DATA(IP3_24_22, HSCK0_C, SEL_HSCIF0_2),
961 PINMUX_IPSR_MODSEL_DATA(IP3_24_22, HSCK2_C, SEL_HSCIF2_2),
962 PINMUX_IPSR_MODSEL_DATA(IP3_24_22, SCIFB0_SCK_B, SEL_SCIFB_1),
963 PINMUX_IPSR_MODSEL_DATA(IP3_24_22, SCIFB2_SCK_B, SEL_SCIFB2_1),
964 PINMUX_IPSR_MODSEL_DATA(IP3_24_22, DREQ2_C, SEL_LBS_2),
965 PINMUX_IPSR_MODSEL_DATA(IP3_30_28, HTX2_C, SEL_HSCIF2_2),
966 PINMUX_IPSR_MODSEL_DATA(IP3_27_25, SSI_SCK0129, SEL_SSI0_0),
967 PINMUX_IPSR_MODSEL_DATA(IP3_27_25, HRX0_C, SEL_HSCIF0_2),
968 PINMUX_IPSR_MODSEL_DATA(IP3_27_25, HRX2_C, SEL_HSCIF2_2),
969 PINMUX_IPSR_MODSEL_DATA(IP3_27_25, SCIFB0_RXD_C, SEL_SCIFB_2),
970 PINMUX_IPSR_MODSEL_DATA(IP3_27_25, SCIFB2_RXD_C, SEL_SCIFB2_2),
971 PINMUX_IPSR_MODSEL_DATA(IP3_30_28, SSI_WS0129, SEL_SSI0_0),
972 PINMUX_IPSR_MODSEL_DATA(IP3_30_28, HTX0_C, SEL_HSCIF0_2),
973 PINMUX_IPSR_MODSEL_DATA(IP3_30_28, HTX2_C, SEL_HSCIF2_2),
974 PINMUX_IPSR_MODSEL_DATA(IP3_30_28, SCIFB0_TXD_C, SEL_SCIFB_2),
975 PINMUX_IPSR_MODSEL_DATA(IP3_30_28, SCIFB2_TXD_C, SEL_SCIFB2_2),
976
977 /* IPSR4 */
978 PINMUX_IPSR_MODSEL_DATA(IP4_1_0, SSI_SDATA0, SEL_SSI0_0),
979 PINMUX_IPSR_MODSEL_DATA(IP4_1_0, SCL0_B, SEL_IIC0_1),
980 PINMUX_IPSR_MODSEL_DATA(IP4_1_0, SCL7_B, SEL_IIC7_1),
981 PINMUX_IPSR_MODSEL_DATA(IP4_1_0, MSIOF2_SCK_C, SEL_SOF2_2),
982 PINMUX_IPSR_MODSEL_DATA(IP4_4_2, SSI_SCK1, SEL_SSI1_0),
983 PINMUX_IPSR_MODSEL_DATA(IP4_4_2, SDA0_B, SEL_IIC0_1),
984 PINMUX_IPSR_MODSEL_DATA(IP4_4_2, SDA7_B, SEL_IIC7_1),
985 PINMUX_IPSR_MODSEL_DATA(IP4_4_2, MSIOF2_SYNC_C, SEL_SOF2_2),
986 PINMUX_IPSR_MODSEL_DATA(IP4_4_2, GLO_I0_D, SEL_GPS_3),
987 PINMUX_IPSR_MODSEL_DATA(IP4_7_5, SSI_WS1, SEL_SSI1_0),
988 PINMUX_IPSR_MODSEL_DATA(IP4_7_5, SCL1_B, SEL_IIC1_1),
989 PINMUX_IPSR_MODSEL_DATA(IP4_7_5, SCL8_B, SEL_IIC8_1),
990 PINMUX_IPSR_MODSEL_DATA(IP4_7_5, MSIOF2_TXD_C, SEL_SOF2_2),
991 PINMUX_IPSR_MODSEL_DATA(IP4_7_5, GLO_I1_D, SEL_GPS_3),
992 PINMUX_IPSR_MODSEL_DATA(IP4_9_8, SSI_SDATA1, SEL_SSI1_0),
993 PINMUX_IPSR_MODSEL_DATA(IP4_9_8, SDA1_B, SEL_IIC1_1),
994 PINMUX_IPSR_MODSEL_DATA(IP4_9_8, SDA8_B, SEL_IIC8_1),
995 PINMUX_IPSR_MODSEL_DATA(IP4_9_8, MSIOF2_RXD_C, SEL_SOF2_2),
996 PINMUX_IPSR_DATA(IP4_12_10, SSI_SCK2),
997 PINMUX_IPSR_MODSEL_DATA(IP4_12_10, SCL2, SEL_IIC2_0),
998 PINMUX_IPSR_MODSEL_DATA(IP4_12_10, GPS_CLK_B, SEL_GPS_1),
999 PINMUX_IPSR_MODSEL_DATA(IP4_12_10, GLO_Q0_D, SEL_GPS_3),
1000 PINMUX_IPSR_DATA(IP4_15_13, SSI_WS2),
1001 PINMUX_IPSR_MODSEL_DATA(IP4_15_13, SDA2, SEL_IIC2_0),
1002 PINMUX_IPSR_MODSEL_DATA(IP4_15_13, GPS_SIGN_B, SEL_GPS_1),
1003 PINMUX_IPSR_MODSEL_DATA(IP4_15_13, RX2_E, SEL_SCIF2_4),
1004 PINMUX_IPSR_MODSEL_DATA(IP4_15_13, GLO_Q1_D, SEL_GPS_3),
1005 PINMUX_IPSR_DATA(IP4_18_16, SSI_SDATA2),
1006 PINMUX_IPSR_MODSEL_DATA(IP4_18_16, GPS_MAG_B, SEL_GPS_1),
1007 PINMUX_IPSR_MODSEL_DATA(IP4_18_16, TX2_E, SEL_SCIF2_4),
1008 PINMUX_IPSR_DATA(IP4_19, SSI_SCK34),
1009 PINMUX_IPSR_DATA(IP4_20, SSI_WS34),
1010 PINMUX_IPSR_DATA(IP4_21, SSI_SDATA3),
1011 PINMUX_IPSR_DATA(IP4_23_22, SSI_SCK4),
1012 PINMUX_IPSR_MODSEL_DATA(IP4_23_22, GLO_SS_D, SEL_GPS_3),
1013 PINMUX_IPSR_DATA(IP4_25_24, SSI_WS4),
1014 PINMUX_IPSR_MODSEL_DATA(IP4_25_24, GLO_RFON_D, SEL_GPS_3),
1015 PINMUX_IPSR_DATA(IP4_27_26, SSI_SDATA4),
1016 PINMUX_IPSR_MODSEL_DATA(IP4_27_26, MSIOF2_SCK_D, SEL_SOF2_3),
1017 PINMUX_IPSR_DATA(IP4_30_28, SSI_SCK5),
1018 PINMUX_IPSR_MODSEL_DATA(IP4_30_28, MSIOF1_SCK_C, SEL_SOF1_2),
1019 PINMUX_IPSR_MODSEL_DATA(IP4_30_28, TS_SDATA0, SEL_TSIF0_0),
1020 PINMUX_IPSR_MODSEL_DATA(IP4_30_28, GLO_I0, SEL_GPS_0),
1021 PINMUX_IPSR_MODSEL_DATA(IP4_30_28, MSIOF2_SYNC_D, SEL_SOF2_3),
1022 PINMUX_IPSR_DATA(IP4_30_28, VI1_R2_B),
1023
1024 /* IPSR5 */
1025 PINMUX_IPSR_DATA(IP5_2_0, SSI_WS5),
1026 PINMUX_IPSR_MODSEL_DATA(IP5_2_0, MSIOF1_SYNC_C, SEL_SOF1_2),
1027 PINMUX_IPSR_MODSEL_DATA(IP5_2_0, TS_SCK0, SEL_TSIF0_0),
1028 PINMUX_IPSR_MODSEL_DATA(IP5_2_0, GLO_I1, SEL_GPS_0),
1029 PINMUX_IPSR_MODSEL_DATA(IP5_2_0, MSIOF2_TXD_D, SEL_SOF2_3),
1030 PINMUX_IPSR_DATA(IP5_2_0, VI1_R3_B),
1031 PINMUX_IPSR_DATA(IP5_5_3, SSI_SDATA5),
1032 PINMUX_IPSR_MODSEL_DATA(IP5_5_3, MSIOF1_TXD_C, SEL_SOF1_2),
1033 PINMUX_IPSR_MODSEL_DATA(IP5_5_3, TS_SDEN0, SEL_TSIF0_0),
1034 PINMUX_IPSR_MODSEL_DATA(IP5_5_3, GLO_Q0, SEL_GPS_0),
1035 PINMUX_IPSR_MODSEL_DATA(IP5_5_3, MSIOF2_SS1_D, SEL_SOF2_3),
1036 PINMUX_IPSR_DATA(IP5_5_3, VI1_R4_B),
1037 PINMUX_IPSR_DATA(IP5_8_6, SSI_SCK6),
1038 PINMUX_IPSR_MODSEL_DATA(IP5_8_6, MSIOF1_RXD_C, SEL_SOF1_2),
1039 PINMUX_IPSR_MODSEL_DATA(IP5_8_6, TS_SPSYNC0, SEL_TSIF0_0),
1040 PINMUX_IPSR_MODSEL_DATA(IP5_8_6, GLO_Q1, SEL_GPS_0),
1041 PINMUX_IPSR_MODSEL_DATA(IP5_8_6, MSIOF2_RXD_D, SEL_SOF2_3),
1042 PINMUX_IPSR_DATA(IP5_8_6, VI1_R5_B),
1043 PINMUX_IPSR_DATA(IP5_11_9, SSI_WS6),
1044 PINMUX_IPSR_MODSEL_DATA(IP5_11_9, GLO_SCLK, SEL_GPS_0),
1045 PINMUX_IPSR_MODSEL_DATA(IP5_11_9, MSIOF2_SS2_D, SEL_SOF2_3),
1046 PINMUX_IPSR_DATA(IP5_11_9, VI1_R6_B),
1047 PINMUX_IPSR_DATA(IP5_14_12, SSI_SDATA6),
1048 PINMUX_IPSR_MODSEL_DATA(IP5_14_12, STP_IVCXO27_0_B, SEL_SSP_1),
1049 PINMUX_IPSR_MODSEL_DATA(IP5_14_12, GLO_SDATA, SEL_GPS_0),
1050 PINMUX_IPSR_DATA(IP5_14_12, VI1_R7_B),
1051 PINMUX_IPSR_MODSEL_DATA(IP5_16_15, SSI_SCK78, SEL_SSI7_0),
1052 PINMUX_IPSR_MODSEL_DATA(IP5_16_15, STP_ISCLK_0_B, SEL_SSP_1),
1053 PINMUX_IPSR_MODSEL_DATA(IP5_16_15, GLO_SS, SEL_GPS_0),
1054 PINMUX_IPSR_MODSEL_DATA(IP5_19_17, SSI_WS78, SEL_SSI7_0),
1055 PINMUX_IPSR_MODSEL_DATA(IP5_19_17, TX0_D, SEL_SCIF0_3),
1056 PINMUX_IPSR_MODSEL_DATA(IP5_19_17, STP_ISD_0_B, SEL_SSP_1),
1057 PINMUX_IPSR_MODSEL_DATA(IP5_19_17, GLO_RFON, SEL_GPS_0),
1058 PINMUX_IPSR_MODSEL_DATA(IP5_21_20, SSI_SDATA7, SEL_SSI7_0),
1059 PINMUX_IPSR_MODSEL_DATA(IP5_21_20, RX0_D, SEL_SCIF0_3),
1060 PINMUX_IPSR_MODSEL_DATA(IP5_21_20, STP_ISEN_0_B, SEL_SSP_1),
1061 PINMUX_IPSR_MODSEL_DATA(IP5_23_22, SSI_SDATA8, SEL_SSI8_0),
1062 PINMUX_IPSR_MODSEL_DATA(IP5_23_22, TX1_D, SEL_SCIF1_3),
1063 PINMUX_IPSR_MODSEL_DATA(IP5_23_22, STP_ISSYNC_0_B, SEL_SSP_1),
1064 PINMUX_IPSR_MODSEL_DATA(IP5_25_24, SSI_SCK9, SEL_SSI9_0),
1065 PINMUX_IPSR_MODSEL_DATA(IP5_25_24, RX1_D, SEL_SCIF1_3),
1066 PINMUX_IPSR_MODSEL_DATA(IP5_25_24, GLO_SCLK_D, SEL_GPS_3),
1067 PINMUX_IPSR_MODSEL_DATA(IP5_28_26, SSI_WS9, SEL_SSI9_0),
1068 PINMUX_IPSR_MODSEL_DATA(IP5_28_26, TX3_D, SEL_SCIF3_3),
1069 PINMUX_IPSR_MODSEL_DATA(IP5_28_26, CAN0_TX_D, SEL_CAN0_3),
1070 PINMUX_IPSR_MODSEL_DATA(IP5_28_26, GLO_SDATA_D, SEL_GPS_3),
1071 PINMUX_IPSR_MODSEL_DATA(IP5_31_29, SSI_SDATA9, SEL_SSI9_0),
1072 PINMUX_IPSR_MODSEL_DATA(IP5_31_29, RX3_D, SEL_SCIF3_3),
1073 PINMUX_IPSR_MODSEL_DATA(IP5_31_29, CAN0_RX_D, SEL_CAN0_3),
1074
1075 /* IPSR6 */
1076 PINMUX_IPSR_MODSEL_DATA(IP6_2_0, AUDIO_CLKB, SEL_ADG_0),
1077 PINMUX_IPSR_MODSEL_DATA(IP6_2_0, STP_OPWM_0_B, SEL_SSP_1),
1078 PINMUX_IPSR_MODSEL_DATA(IP6_2_0, MSIOF1_SCK_B, SEL_SOF1_1),
1079 PINMUX_IPSR_MODSEL_DATA(IP6_2_0, SCIF_CLK, SEL_SCIF_0),
1080 PINMUX_IPSR_MODSEL_DATA(IP6_2_0, BPFCLK_E, SEL_FM_4),
1081 PINMUX_IPSR_DATA(IP6_5_3, AUDIO_CLKC),
1082 PINMUX_IPSR_MODSEL_DATA(IP6_5_3, SCIFB0_SCK_C, SEL_SCIFB_2),
1083 PINMUX_IPSR_MODSEL_DATA(IP6_5_3, MSIOF1_SYNC_B, SEL_SOF1_1),
1084 PINMUX_IPSR_MODSEL_DATA(IP6_5_3, RX2, SEL_SCIF2_0),
1085 PINMUX_IPSR_MODSEL_DATA(IP6_5_3, SCIFA2_RXD, SEL_SCIFA2_0),
1086 PINMUX_IPSR_MODSEL_DATA(IP6_5_3, FMIN_E, SEL_FM_4),
1087 PINMUX_IPSR_DATA(IP6_7_6, AUDIO_CLKOUT),
1088 PINMUX_IPSR_MODSEL_DATA(IP6_7_6, MSIOF1_SS1_B, SEL_SOF1_1),
1089 PINMUX_IPSR_MODSEL_DATA(IP6_5_3, TX2, SEL_SCIF2_0),
1090 PINMUX_IPSR_MODSEL_DATA(IP6_7_6, SCIFA2_TXD, SEL_SCIFA2_0),
1091 PINMUX_IPSR_DATA(IP6_9_8, IRQ0),
1092 PINMUX_IPSR_MODSEL_DATA(IP6_9_8, SCIFB1_RXD_D, SEL_SCIFB1_3),
1093 PINMUX_IPSR_DATA(IP6_9_8, INTC_IRQ0_N),
1094 PINMUX_IPSR_DATA(IP6_11_10, IRQ1),
1095 PINMUX_IPSR_MODSEL_DATA(IP6_11_10, SCIFB1_SCK_C, SEL_SCIFB1_2),
1096 PINMUX_IPSR_DATA(IP6_11_10, INTC_IRQ1_N),
1097 PINMUX_IPSR_DATA(IP6_13_12, IRQ2),
1098 PINMUX_IPSR_MODSEL_DATA(IP6_13_12, SCIFB1_TXD_D, SEL_SCIFB1_3),
1099 PINMUX_IPSR_DATA(IP6_13_12, INTC_IRQ2_N),
1100 PINMUX_IPSR_DATA(IP6_15_14, IRQ3),
1101 PINMUX_IPSR_MODSEL_DATA(IP6_15_14, SCL4_C, SEL_IIC4_2),
1102 PINMUX_IPSR_MODSEL_DATA(IP6_15_14, MSIOF2_TXD_E, SEL_SOF2_4),
1103 PINMUX_IPSR_DATA(IP6_15_14, INTC_IRQ4_N),
1104 PINMUX_IPSR_DATA(IP6_18_16, IRQ4),
1105 PINMUX_IPSR_MODSEL_DATA(IP6_18_16, HRX1_C, SEL_HSCIF1_2),
1106 PINMUX_IPSR_MODSEL_DATA(IP6_18_16, SDA4_C, SEL_IIC4_2),
1107 PINMUX_IPSR_MODSEL_DATA(IP6_18_16, MSIOF2_RXD_E, SEL_SOF2_4),
1108 PINMUX_IPSR_DATA(IP6_18_16, INTC_IRQ4_N),
1109 PINMUX_IPSR_DATA(IP6_20_19, IRQ5),
1110 PINMUX_IPSR_MODSEL_DATA(IP6_20_19, HTX1_C, SEL_HSCIF1_2),
1111 PINMUX_IPSR_MODSEL_DATA(IP6_20_19, SCL1_E, SEL_IIC1_4),
1112 PINMUX_IPSR_MODSEL_DATA(IP6_20_19, MSIOF2_SCK_E, SEL_SOF2_4),
1113 PINMUX_IPSR_DATA(IP6_23_21, IRQ6),
1114 PINMUX_IPSR_MODSEL_DATA(IP6_23_21, HSCK1_C, SEL_HSCIF1_2),
1115 PINMUX_IPSR_MODSEL_DATA(IP6_23_21, MSIOF1_SS2_B, SEL_SOF1_1),
1116 PINMUX_IPSR_MODSEL_DATA(IP6_23_21, SDA1_E, SEL_IIC1_4),
1117 PINMUX_IPSR_MODSEL_DATA(IP6_23_21, MSIOF2_SYNC_E, SEL_SOF2_4),
1118 PINMUX_IPSR_DATA(IP6_26_24, IRQ7),
1119 PINMUX_IPSR_MODSEL_DATA(IP6_26_24, HCTS1_N_C, SEL_HSCIF1_2),
1120 PINMUX_IPSR_MODSEL_DATA(IP6_26_24, MSIOF1_TXD_B, SEL_SOF1_1),
1121 PINMUX_IPSR_MODSEL_DATA(IP6_26_24, GPS_CLK_C, SEL_GPS_2),
1122 PINMUX_IPSR_MODSEL_DATA(IP6_26_24, GPS_CLK_D, SEL_GPS_3),
1123 PINMUX_IPSR_DATA(IP6_29_27, IRQ8),
1124 PINMUX_IPSR_MODSEL_DATA(IP6_29_27, HRTS1_N_C, SEL_HSCIF1_2),
1125 PINMUX_IPSR_MODSEL_DATA(IP6_29_27, MSIOF1_RXD_B, SEL_SOF1_1),
1126 PINMUX_IPSR_MODSEL_DATA(IP6_29_27, GPS_SIGN_C, SEL_GPS_2),
1127 PINMUX_IPSR_MODSEL_DATA(IP6_29_27, GPS_SIGN_D, SEL_GPS_3),
1128
1129 /* IPSR7 */
1130 PINMUX_IPSR_DATA(IP7_2_0, IRQ9),
1131 PINMUX_IPSR_MODSEL_DATA(IP7_2_0, DU1_DOTCLKIN_B, SEL_DIS_1),
1132 PINMUX_IPSR_MODSEL_DATA(IP7_2_0, CAN_CLK_D, SEL_CANCLK_3),
1133 PINMUX_IPSR_MODSEL_DATA(IP7_2_0, GPS_MAG_C, SEL_GPS_2),
1134 PINMUX_IPSR_MODSEL_DATA(IP7_2_0, SCIF_CLK_B, SEL_SCIF_1),
1135 PINMUX_IPSR_MODSEL_DATA(IP7_2_0, GPS_MAG_D, SEL_GPS_3),
1136 PINMUX_IPSR_DATA(IP7_5_3, DU1_DR0),
1137 PINMUX_IPSR_DATA(IP7_5_3, LCDOUT0),
1138 PINMUX_IPSR_MODSEL_DATA(IP7_5_3, VI1_DATA0_B, SEL_VI1_1),
1139 PINMUX_IPSR_MODSEL_DATA(IP7_5_3, TX0_B, SEL_SCIF0_1),
1140 PINMUX_IPSR_MODSEL_DATA(IP7_5_3, SCIFA0_TXD_B, SEL_SCFA_1),
1141 PINMUX_IPSR_MODSEL_DATA(IP7_5_3, MSIOF2_SCK_B, SEL_SOF2_1),
1142 PINMUX_IPSR_DATA(IP7_8_6, DU1_DR1),
1143 PINMUX_IPSR_DATA(IP7_8_6, LCDOUT1),
1144 PINMUX_IPSR_MODSEL_DATA(IP7_8_6, VI1_DATA1_B, SEL_VI1_1),
1145 PINMUX_IPSR_MODSEL_DATA(IP7_8_6, RX0_B, SEL_SCIF0_1),
1146 PINMUX_IPSR_MODSEL_DATA(IP7_8_6, SCIFA0_RXD_B, SEL_SCFA_1),
1147 PINMUX_IPSR_MODSEL_DATA(IP7_8_6, MSIOF2_SYNC_B, SEL_SOF2_1),
1148 PINMUX_IPSR_DATA(IP7_10_9, DU1_DR2),
1149 PINMUX_IPSR_DATA(IP7_10_9, LCDOUT2),
1150 PINMUX_IPSR_MODSEL_DATA(IP7_10_9, SSI_SCK0129_B, SEL_SSI0_1),
1151 PINMUX_IPSR_DATA(IP7_12_11, DU1_DR3),
1152 PINMUX_IPSR_DATA(IP7_12_11, LCDOUT3),
1153 PINMUX_IPSR_MODSEL_DATA(IP7_12_11, SSI_WS0129_B, SEL_SSI0_1),
1154 PINMUX_IPSR_DATA(IP7_14_13, DU1_DR4),
1155 PINMUX_IPSR_DATA(IP7_14_13, LCDOUT4),
1156 PINMUX_IPSR_MODSEL_DATA(IP7_14_13, SSI_SDATA0_B, SEL_SSI0_1),
1157 PINMUX_IPSR_DATA(IP7_16_15, DU1_DR5),
1158 PINMUX_IPSR_DATA(IP7_16_15, LCDOUT5),
1159 PINMUX_IPSR_MODSEL_DATA(IP7_16_15, SSI_SCK1_B, SEL_SSI1_1),
1160 PINMUX_IPSR_DATA(IP7_18_17, DU1_DR6),
1161 PINMUX_IPSR_DATA(IP7_18_17, LCDOUT6),
1162 PINMUX_IPSR_MODSEL_DATA(IP7_18_17, SSI_WS1_B, SEL_SSI1_1),
1163 PINMUX_IPSR_DATA(IP7_20_19, DU1_DR7),
1164 PINMUX_IPSR_DATA(IP7_20_19, LCDOUT7),
1165 PINMUX_IPSR_MODSEL_DATA(IP7_20_19, SSI_SDATA1_B, SEL_SSI1_1),
1166 PINMUX_IPSR_DATA(IP7_23_21, DU1_DG0),
1167 PINMUX_IPSR_DATA(IP7_23_21, LCDOUT8),
1168 PINMUX_IPSR_MODSEL_DATA(IP7_23_21, VI1_DATA2_B, SEL_VI1_1),
1169 PINMUX_IPSR_MODSEL_DATA(IP7_23_21, TX1_B, SEL_SCIF1_1),
1170 PINMUX_IPSR_MODSEL_DATA(IP7_23_21, SCIFA1_TXD_B, SEL_SCIFA1_1),
1171 PINMUX_IPSR_MODSEL_DATA(IP7_23_21, MSIOF2_SS1_B, SEL_SOF2_1),
1172 PINMUX_IPSR_DATA(IP7_26_24, DU1_DG1),
1173 PINMUX_IPSR_DATA(IP7_26_24, LCDOUT9),
1174 PINMUX_IPSR_MODSEL_DATA(IP7_26_24, VI1_DATA3_B, SEL_VI1_1),
1175 PINMUX_IPSR_MODSEL_DATA(IP7_26_24, RX1_B, SEL_SCIF1_1),
1176 PINMUX_IPSR_MODSEL_DATA(IP7_26_24, SCIFA1_RXD_B, SEL_SCIFA1_1),
1177 PINMUX_IPSR_MODSEL_DATA(IP7_26_24, MSIOF2_SS2_B, SEL_SOF2_1),
1178 PINMUX_IPSR_DATA(IP7_29_27, DU1_DG2),
1179 PINMUX_IPSR_DATA(IP7_29_27, LCDOUT10),
1180 PINMUX_IPSR_MODSEL_DATA(IP7_29_27, VI1_DATA4_B, SEL_VI1_1),
1181 PINMUX_IPSR_DATA(IP7_29_27, SCIF1_SCK_B),
1182 PINMUX_IPSR_MODSEL_DATA(IP7_29_27, SCIFA1_SCK, SEL_SCIFA1_0),
1183 PINMUX_IPSR_MODSEL_DATA(IP7_29_27, SSI_SCK78_B, SEL_SSI7_1),
1184
1185 /* IPSR8 */
1186 PINMUX_IPSR_DATA(IP8_2_0, DU1_DG3),
1187 PINMUX_IPSR_DATA(IP8_2_0, LCDOUT11),
1188 PINMUX_IPSR_MODSEL_DATA(IP8_2_0, VI1_DATA5_B, SEL_VI1_1),
1189 PINMUX_IPSR_MODSEL_DATA(IP8_2_0, SSI_WS78_B, SEL_SSI7_1),
1190 PINMUX_IPSR_DATA(IP8_5_3, DU1_DG4),
1191 PINMUX_IPSR_DATA(IP8_5_3, LCDOUT12),
1192 PINMUX_IPSR_MODSEL_DATA(IP8_5_3, VI1_DATA6_B, SEL_VI1_1),
1193 PINMUX_IPSR_MODSEL_DATA(IP8_5_3, HRX0_B, SEL_HSCIF0_1),
1194 PINMUX_IPSR_MODSEL_DATA(IP8_5_3, SCIFB2_RXD_B, SEL_SCIFB2_1),
1195 PINMUX_IPSR_MODSEL_DATA(IP8_5_3, SSI_SDATA7_B, SEL_SSI7_1),
1196 PINMUX_IPSR_DATA(IP8_8_6, DU1_DG5),
1197 PINMUX_IPSR_DATA(IP8_8_6, LCDOUT13),
1198 PINMUX_IPSR_MODSEL_DATA(IP8_8_6, VI1_DATA7_B, SEL_VI1_1),
1199 PINMUX_IPSR_MODSEL_DATA(IP8_8_6, HCTS0_N_B, SEL_HSCIF0_1),
1200 PINMUX_IPSR_MODSEL_DATA(IP8_8_6, SCIFB2_TXD_B, SEL_SCIFB2_1),
1201 PINMUX_IPSR_MODSEL_DATA(IP8_8_6, SSI_SDATA8_B, SEL_SSI8_1),
1202 PINMUX_IPSR_DATA(IP8_11_9, DU1_DG6),
1203 PINMUX_IPSR_DATA(IP8_11_9, LCDOUT14),
1204 PINMUX_IPSR_MODSEL_DATA(IP8_11_9, HRTS0_N_B, SEL_HSCIF0_1),
1205 PINMUX_IPSR_MODSEL_DATA(IP8_11_9, SCIFB2_CTS_N_B, SEL_SCIFB2_1),
1206 PINMUX_IPSR_MODSEL_DATA(IP8_11_9, SSI_SCK9_B, SEL_SSI9_1),
1207 PINMUX_IPSR_DATA(IP8_14_12, DU1_DG7),
1208 PINMUX_IPSR_DATA(IP8_14_12, LCDOUT15),
1209 PINMUX_IPSR_MODSEL_DATA(IP8_14_12, HTX0_B, SEL_HSCIF0_1),
1210 PINMUX_IPSR_MODSEL_DATA(IP8_14_12, SCIFB2_RTS_N_B, SEL_SCIFB2_1),
1211 PINMUX_IPSR_MODSEL_DATA(IP8_14_12, SSI_WS9_B, SEL_SSI9_1),
1212 PINMUX_IPSR_DATA(IP8_17_15, DU1_DB0),
1213 PINMUX_IPSR_DATA(IP8_17_15, LCDOUT16),
1214 PINMUX_IPSR_MODSEL_DATA(IP8_17_15, VI1_CLK_B, SEL_VI1_1),
1215 PINMUX_IPSR_MODSEL_DATA(IP8_17_15, TX2_B, SEL_SCIF2_1),
1216 PINMUX_IPSR_MODSEL_DATA(IP8_17_15, SCIFA2_TXD_B, SEL_SCIFA2_1),
1217 PINMUX_IPSR_MODSEL_DATA(IP8_17_15, MSIOF2_TXD_B, SEL_SOF2_1),
1218 PINMUX_IPSR_DATA(IP8_20_18, DU1_DB1),
1219 PINMUX_IPSR_DATA(IP8_20_18, LCDOUT17),
1220 PINMUX_IPSR_MODSEL_DATA(IP8_20_18, VI1_HSYNC_N_B, SEL_VI1_1),
1221 PINMUX_IPSR_MODSEL_DATA(IP8_20_18, RX2_B, SEL_SCIF2_1),
1222 PINMUX_IPSR_MODSEL_DATA(IP8_20_18, SCIFA2_RXD_B, SEL_SCIFA2_1),
1223 PINMUX_IPSR_MODSEL_DATA(IP8_20_18, MSIOF2_RXD_B, SEL_SOF2_1),
1224 PINMUX_IPSR_DATA(IP8_23_21, DU1_DB2),
1225 PINMUX_IPSR_DATA(IP8_23_21, LCDOUT18),
1226 PINMUX_IPSR_MODSEL_DATA(IP8_23_21, VI1_VSYNC_N_B, SEL_VI1_1),
1227 PINMUX_IPSR_DATA(IP8_23_21, SCIF2_SCK_B),
1228 PINMUX_IPSR_MODSEL_DATA(IP8_23_21, SCIFA2_SCK, SEL_SCIFA2_1),
1229 PINMUX_IPSR_MODSEL_DATA(IP8_23_21, SSI_SDATA9_B, SEL_SSI9_1),
1230 PINMUX_IPSR_DATA(IP8_25_24, DU1_DB3),
1231 PINMUX_IPSR_DATA(IP8_25_24, LCDOUT19),
1232 PINMUX_IPSR_MODSEL_DATA(IP8_25_24, VI1_CLKENB_B, SEL_VI1_1),
1233 PINMUX_IPSR_DATA(IP8_27_26, DU1_DB4),
1234 PINMUX_IPSR_DATA(IP8_27_26, LCDOUT20),
1235 PINMUX_IPSR_MODSEL_DATA(IP8_27_26, VI1_FIELD_B, SEL_VI1_1),
1236 PINMUX_IPSR_MODSEL_DATA(IP8_27_26, CAN1_RX, SEL_CAN1_0),
1237 PINMUX_IPSR_DATA(IP8_30_28, DU1_DB5),
1238 PINMUX_IPSR_DATA(IP8_30_28, LCDOUT21),
1239 PINMUX_IPSR_MODSEL_DATA(IP8_30_28, TX3, SEL_SCIF3_0),
1240 PINMUX_IPSR_MODSEL_DATA(IP8_30_28, SCIFA3_TXD, SEL_SCIFA3_0),
1241 PINMUX_IPSR_MODSEL_DATA(IP8_30_28, CAN1_TX, SEL_CAN1_0),
1242
1243 /* IPSR9 */
1244 PINMUX_IPSR_DATA(IP9_2_0, DU1_DB6),
1245 PINMUX_IPSR_DATA(IP9_2_0, LCDOUT22),
1246 PINMUX_IPSR_MODSEL_DATA(IP9_2_0, SCL3_C, SEL_IIC3_2),
1247 PINMUX_IPSR_MODSEL_DATA(IP9_2_0, RX3, SEL_SCIF3_0),
1248 PINMUX_IPSR_MODSEL_DATA(IP9_2_0, SCIFA3_RXD, SEL_SCIFA3_0),
1249 PINMUX_IPSR_DATA(IP9_5_3, DU1_DB7),
1250 PINMUX_IPSR_DATA(IP9_5_3, LCDOUT23),
1251 PINMUX_IPSR_MODSEL_DATA(IP9_5_3, SDA3_C, SEL_IIC3_2),
1252 PINMUX_IPSR_MODSEL_DATA(IP9_5_3, SCIF3_SCK, SEL_SCIF3_0),
1253 PINMUX_IPSR_MODSEL_DATA(IP9_5_3, SCIFA3_SCK, SEL_SCIFA3_0),
1254 PINMUX_IPSR_MODSEL_DATA(IP9_6, DU1_DOTCLKIN, SEL_DIS_0),
1255 PINMUX_IPSR_DATA(IP9_6, QSTVA_QVS),
1256 PINMUX_IPSR_DATA(IP9_7, DU1_DOTCLKOUT0),
1257 PINMUX_IPSR_DATA(IP9_7, QCLK),
1258 PINMUX_IPSR_DATA(IP9_10_8, DU1_DOTCLKOUT1),
1259 PINMUX_IPSR_DATA(IP9_10_8, QSTVB_QVE),
1260 PINMUX_IPSR_MODSEL_DATA(IP9_10_8, CAN0_TX, SEL_CAN0_0),
1261 PINMUX_IPSR_MODSEL_DATA(IP9_10_8, TX3_B, SEL_SCIF3_1),
1262 PINMUX_IPSR_MODSEL_DATA(IP9_10_8, SCL2_B, SEL_IIC2_1),
1263 PINMUX_IPSR_DATA(IP9_10_8, PWM4),
1264 PINMUX_IPSR_DATA(IP9_11, DU1_EXHSYNC_DU1_HSYNC),
1265 PINMUX_IPSR_DATA(IP9_11, QSTH_QHS),
1266 PINMUX_IPSR_DATA(IP9_12, DU1_EXVSYNC_DU1_VSYNC),
1267 PINMUX_IPSR_DATA(IP9_12, QSTB_QHE),
1268 PINMUX_IPSR_DATA(IP9_15_13, DU1_EXODDF_DU1_ODDF_DISP_CDE),
1269 PINMUX_IPSR_DATA(IP9_15_13, QCPV_QDE),
1270 PINMUX_IPSR_MODSEL_DATA(IP9_15_13, CAN0_RX, SEL_CAN0_0),
1271 PINMUX_IPSR_MODSEL_DATA(IP9_15_13, RX3_B, SEL_SCIF3_1),
1272 PINMUX_IPSR_MODSEL_DATA(IP9_15_13, SDA2_B, SEL_IIC2_1),
1273 PINMUX_IPSR_DATA(IP9_16, DU1_DISP),
1274 PINMUX_IPSR_DATA(IP9_16, QPOLA),
1275 PINMUX_IPSR_DATA(IP9_18_17, DU1_CDE),
1276 PINMUX_IPSR_DATA(IP9_18_17, QPOLB),
1277 PINMUX_IPSR_DATA(IP9_18_17, PWM4_B),
1278 PINMUX_IPSR_DATA(IP9_20_19, VI0_CLKENB),
1279 PINMUX_IPSR_MODSEL_DATA(IP9_20_19, TX4, SEL_SCIF4_0),
1280 PINMUX_IPSR_MODSEL_DATA(IP9_20_19, SCIFA4_TXD, SEL_SCIFA4_0),
1281 PINMUX_IPSR_MODSEL_DATA(IP9_20_19, TS_SDATA0_D, SEL_TSIF0_3),
1282 PINMUX_IPSR_DATA(IP9_22_21, VI0_FIELD),
1283 PINMUX_IPSR_MODSEL_DATA(IP9_22_21, RX4, SEL_SCIF4_0),
1284 PINMUX_IPSR_MODSEL_DATA(IP9_22_21, SCIFA4_RXD, SEL_SCIFA4_0),
1285 PINMUX_IPSR_MODSEL_DATA(IP9_22_21, TS_SCK0_D, SEL_TSIF0_3),
1286 PINMUX_IPSR_DATA(IP9_24_23, VI0_HSYNC_N),
1287 PINMUX_IPSR_MODSEL_DATA(IP9_24_23, TX5, SEL_SCIF5_0),
1288 PINMUX_IPSR_MODSEL_DATA(IP9_24_23, SCIFA5_TXD, SEL_SCIFA5_0),
1289 PINMUX_IPSR_MODSEL_DATA(IP9_24_23, TS_SDEN0_D, SEL_TSIF0_3),
1290 PINMUX_IPSR_DATA(IP9_26_25, VI0_VSYNC_N),
1291 PINMUX_IPSR_MODSEL_DATA(IP9_26_25, RX5, SEL_SCIF5_0),
1292 PINMUX_IPSR_MODSEL_DATA(IP9_26_25, SCIFA5_RXD, SEL_SCIFA5_0),
1293 PINMUX_IPSR_MODSEL_DATA(IP9_26_25, TS_SPSYNC0_D, SEL_TSIF0_3),
1294 PINMUX_IPSR_DATA(IP9_28_27, VI0_DATA3_VI0_B3),
1295 PINMUX_IPSR_MODSEL_DATA(IP9_28_27, SCIF3_SCK_B, SEL_SCIF3_1),
1296 PINMUX_IPSR_MODSEL_DATA(IP9_28_27, SCIFA3_SCK_B, SEL_SCIFA3_1),
1297 PINMUX_IPSR_DATA(IP9_31_29, VI0_G0),
1298 PINMUX_IPSR_MODSEL_DATA(IP9_31_29, SCL8, SEL_IIC8_0),
1299 PINMUX_IPSR_MODSEL_DATA(IP9_31_29, STP_IVCXO27_0_C, SEL_SSP_2),
1300 PINMUX_IPSR_MODSEL_DATA(IP9_31_29, SCL4, SEL_IIC4_0),
1301 PINMUX_IPSR_MODSEL_DATA(IP9_31_29, HCTS2_N, SEL_HSCIF2_0),
1302 PINMUX_IPSR_MODSEL_DATA(IP9_31_29, SCIFB2_CTS_N, SEL_SCIFB2_0),
1303 PINMUX_IPSR_DATA(IP9_31_29, ATAWR1_N),
1304
1305 /* IPSR10 */
1306 PINMUX_IPSR_DATA(IP10_2_0, VI0_G1),
1307 PINMUX_IPSR_MODSEL_DATA(IP10_2_0, SDA8, SEL_IIC8_0),
1308 PINMUX_IPSR_MODSEL_DATA(IP10_2_0, STP_ISCLK_0_C, SEL_SSP_2),
1309 PINMUX_IPSR_MODSEL_DATA(IP10_2_0, SDA4, SEL_IIC4_0),
1310 PINMUX_IPSR_MODSEL_DATA(IP10_2_0, HRTS2_N, SEL_HSCIF2_0),
1311 PINMUX_IPSR_MODSEL_DATA(IP10_2_0, SCIFB2_RTS_N, SEL_SCIFB2_0),
1312 PINMUX_IPSR_DATA(IP10_2_0, ATADIR1_N),
1313 PINMUX_IPSR_DATA(IP10_5_3, VI0_G2),
1314 PINMUX_IPSR_DATA(IP10_5_3, VI2_HSYNC_N),
1315 PINMUX_IPSR_MODSEL_DATA(IP10_5_3, STP_ISD_0_C, SEL_SSP_2),
1316 PINMUX_IPSR_MODSEL_DATA(IP10_5_3, SCL3_B, SEL_IIC3_1),
1317 PINMUX_IPSR_MODSEL_DATA(IP10_5_3, HSCK2, SEL_HSCIF2_0),
1318 PINMUX_IPSR_MODSEL_DATA(IP10_5_3, SCIFB2_SCK, SEL_SCIFB2_0),
1319 PINMUX_IPSR_DATA(IP10_5_3, ATARD1_N),
1320 PINMUX_IPSR_DATA(IP10_8_6, VI0_G3),
1321 PINMUX_IPSR_DATA(IP10_8_6, VI2_VSYNC_N),
1322 PINMUX_IPSR_MODSEL_DATA(IP10_8_6, STP_ISEN_0_C, SEL_SSP_2),
1323 PINMUX_IPSR_MODSEL_DATA(IP10_8_6, SDA3_B, SEL_IIC3_1),
1324 PINMUX_IPSR_MODSEL_DATA(IP10_8_6, HRX2, SEL_HSCIF2_0),
1325 PINMUX_IPSR_MODSEL_DATA(IP10_8_6, SCIFB2_RXD, SEL_SCIFB2_0),
1326 PINMUX_IPSR_DATA(IP10_8_6, ATACS01_N),
1327 PINMUX_IPSR_DATA(IP10_11_9, VI0_G4),
1328 PINMUX_IPSR_DATA(IP10_11_9, VI2_CLKENB),
1329 PINMUX_IPSR_MODSEL_DATA(IP10_11_9, STP_ISSYNC_0_C, SEL_SSP_2),
1330 PINMUX_IPSR_MODSEL_DATA(IP10_11_9, HTX2, SEL_HSCIF2_0),
1331 PINMUX_IPSR_MODSEL_DATA(IP10_11_9, SCIFB2_TXD, SEL_SCIFB2_0),
1332 PINMUX_IPSR_MODSEL_DATA(IP10_11_9, SCIFB0_SCK_D, SEL_SCIFB_3),
1333 PINMUX_IPSR_DATA(IP10_14_12, VI0_G5),
1334 PINMUX_IPSR_DATA(IP10_14_12, VI2_FIELD),
1335 PINMUX_IPSR_MODSEL_DATA(IP10_14_12, STP_OPWM_0_C, SEL_SSP_2),
1336 PINMUX_IPSR_MODSEL_DATA(IP10_14_12, FMCLK_D, SEL_FM_3),
1337 PINMUX_IPSR_MODSEL_DATA(IP10_14_12, CAN0_TX_E, SEL_CAN0_4),
1338 PINMUX_IPSR_MODSEL_DATA(IP10_14_12, HTX1_D, SEL_HSCIF1_3),
1339 PINMUX_IPSR_MODSEL_DATA(IP10_14_12, SCIFB0_TXD_D, SEL_SCIFB_3),
1340 PINMUX_IPSR_DATA(IP10_16_15, VI0_G6),
1341 PINMUX_IPSR_DATA(IP10_16_15, VI2_CLK),
1342 PINMUX_IPSR_MODSEL_DATA(IP10_16_15, BPFCLK_D, SEL_FM_3),
1343 PINMUX_IPSR_DATA(IP10_18_17, VI0_G7),
1344 PINMUX_IPSR_DATA(IP10_18_17, VI2_DATA0),
1345 PINMUX_IPSR_MODSEL_DATA(IP10_18_17, FMIN_D, SEL_FM_3),
1346 PINMUX_IPSR_DATA(IP10_21_19, VI0_R0),
1347 PINMUX_IPSR_DATA(IP10_21_19, VI2_DATA1),
1348 PINMUX_IPSR_MODSEL_DATA(IP10_21_19, GLO_I0_B, SEL_GPS_1),
1349 PINMUX_IPSR_MODSEL_DATA(IP10_21_19, TS_SDATA0_C, SEL_TSIF0_2),
1350 PINMUX_IPSR_DATA(IP10_21_19, ATACS11_N),
1351 PINMUX_IPSR_DATA(IP10_24_22, VI0_R1),
1352 PINMUX_IPSR_DATA(IP10_24_22, VI2_DATA2),
1353 PINMUX_IPSR_MODSEL_DATA(IP10_24_22, GLO_I1_B, SEL_GPS_1),
1354 PINMUX_IPSR_MODSEL_DATA(IP10_24_22, TS_SCK0_C, SEL_TSIF0_2),
1355 PINMUX_IPSR_DATA(IP10_24_22, ATAG1_N),
1356 PINMUX_IPSR_DATA(IP10_26_25, VI0_R2),
1357 PINMUX_IPSR_DATA(IP10_26_25, VI2_DATA3),
1358 PINMUX_IPSR_MODSEL_DATA(IP10_26_25, GLO_Q0_B, SEL_GPS_1),
1359 PINMUX_IPSR_MODSEL_DATA(IP10_26_25, TS_SDEN0_C, SEL_TSIF0_2),
1360 PINMUX_IPSR_DATA(IP10_28_27, VI0_R3),
1361 PINMUX_IPSR_DATA(IP10_28_27, VI2_DATA4),
1362 PINMUX_IPSR_MODSEL_DATA(IP10_28_27, GLO_Q1_B, SEL_GPS_1),
1363 PINMUX_IPSR_MODSEL_DATA(IP10_28_27, TS_SPSYNC0_C, SEL_TSIF0_2),
1364 PINMUX_IPSR_DATA(IP10_31_29, VI0_R4),
1365 PINMUX_IPSR_DATA(IP10_31_29, VI2_DATA5),
1366 PINMUX_IPSR_MODSEL_DATA(IP10_31_29, GLO_SCLK_B, SEL_GPS_1),
1367 PINMUX_IPSR_MODSEL_DATA(IP10_31_29, TX0_C, SEL_SCIF0_2),
1368 PINMUX_IPSR_MODSEL_DATA(IP10_31_29, SCL1_D, SEL_IIC1_3),
1369
1370 /* IPSR11 */
1371 PINMUX_IPSR_DATA(IP11_2_0, VI0_R5),
1372 PINMUX_IPSR_DATA(IP11_2_0, VI2_DATA6),
1373 PINMUX_IPSR_MODSEL_DATA(IP11_2_0, GLO_SDATA_B, SEL_GPS_1),
1374 PINMUX_IPSR_MODSEL_DATA(IP11_2_0, RX0_C, SEL_SCIF0_2),
1375 PINMUX_IPSR_MODSEL_DATA(IP11_2_0, SDA1_D, SEL_IIC1_3),
1376 PINMUX_IPSR_DATA(IP11_5_3, VI0_R6),
1377 PINMUX_IPSR_DATA(IP11_5_3, VI2_DATA7),
1378 PINMUX_IPSR_MODSEL_DATA(IP11_5_3, GLO_SS_B, SEL_GPS_1),
1379 PINMUX_IPSR_MODSEL_DATA(IP11_5_3, TX1_C, SEL_SCIF1_2),
1380 PINMUX_IPSR_MODSEL_DATA(IP11_5_3, SCL4_B, SEL_IIC4_1),
1381 PINMUX_IPSR_DATA(IP11_8_6, VI0_R7),
1382 PINMUX_IPSR_MODSEL_DATA(IP11_8_6, GLO_RFON_B, SEL_GPS_1),
1383 PINMUX_IPSR_MODSEL_DATA(IP11_8_6, RX1_C, SEL_SCIF1_2),
1384 PINMUX_IPSR_MODSEL_DATA(IP11_8_6, CAN0_RX_E, SEL_CAN0_4),
1385 PINMUX_IPSR_MODSEL_DATA(IP11_8_6, SDA4_B, SEL_IIC4_1),
1386 PINMUX_IPSR_MODSEL_DATA(IP11_8_6, HRX1_D, SEL_HSCIF1_3),
1387 PINMUX_IPSR_MODSEL_DATA(IP11_8_6, SCIFB0_RXD_D, SEL_SCIFB_3),
1388 PINMUX_IPSR_MODSEL_DATA(IP11_11_9, VI1_HSYNC_N, SEL_VI1_0),
1389 PINMUX_IPSR_DATA(IP11_11_9, AVB_RXD0),
1390 PINMUX_IPSR_MODSEL_DATA(IP11_11_9, TS_SDATA0_B, SEL_TSIF0_1),
1391 PINMUX_IPSR_MODSEL_DATA(IP11_11_9, TX4_B, SEL_SCIF4_1),
1392 PINMUX_IPSR_MODSEL_DATA(IP11_11_9, SCIFA4_TXD_B, SEL_SCIFA4_1),
1393 PINMUX_IPSR_MODSEL_DATA(IP11_14_12, VI1_VSYNC_N, SEL_VI1_0),
1394 PINMUX_IPSR_DATA(IP11_14_12, AVB_RXD1),
1395 PINMUX_IPSR_MODSEL_DATA(IP11_14_12, TS_SCK0_B, SEL_TSIF0_1),
1396 PINMUX_IPSR_MODSEL_DATA(IP11_14_12, RX4_B, SEL_SCIF4_1),
1397 PINMUX_IPSR_MODSEL_DATA(IP11_14_12, SCIFA4_RXD_B, SEL_SCIFA4_1),
1398 PINMUX_IPSR_MODSEL_DATA(IP11_16_15, VI1_CLKENB, SEL_VI1_0),
1399 PINMUX_IPSR_DATA(IP11_16_15, AVB_RXD2),
1400 PINMUX_IPSR_MODSEL_DATA(IP11_16_15, TS_SDEN0_B, SEL_TSIF0_1),
1401 PINMUX_IPSR_MODSEL_DATA(IP11_18_17, VI1_FIELD, SEL_VI1_0),
1402 PINMUX_IPSR_DATA(IP11_18_17, AVB_RXD3),
1403 PINMUX_IPSR_MODSEL_DATA(IP11_18_17, TS_SPSYNC0_B, SEL_TSIF0_1),
1404 PINMUX_IPSR_MODSEL_DATA(IP11_19, VI1_CLK, SEL_VI1_0),
1405 PINMUX_IPSR_DATA(IP11_19, AVB_RXD4),
1406 PINMUX_IPSR_MODSEL_DATA(IP11_20, VI1_DATA0, SEL_VI1_0),
1407 PINMUX_IPSR_DATA(IP11_20, AVB_RXD5),
1408 PINMUX_IPSR_MODSEL_DATA(IP11_21, VI1_DATA1, SEL_VI1_0),
1409 PINMUX_IPSR_DATA(IP11_21, AVB_RXD6),
1410 PINMUX_IPSR_MODSEL_DATA(IP11_22, VI1_DATA2, SEL_VI1_0),
1411 PINMUX_IPSR_DATA(IP11_22, AVB_RXD7),
1412 PINMUX_IPSR_MODSEL_DATA(IP11_23, VI1_DATA3, SEL_VI1_0),
1413 PINMUX_IPSR_DATA(IP11_23, AVB_RX_ER),
1414 PINMUX_IPSR_MODSEL_DATA(IP11_24, VI1_DATA4, SEL_VI1_0),
1415 PINMUX_IPSR_DATA(IP11_24, AVB_MDIO),
1416 PINMUX_IPSR_MODSEL_DATA(IP11_25, VI1_DATA5, SEL_VI1_0),
1417 PINMUX_IPSR_DATA(IP11_25, AVB_RX_DV),
1418 PINMUX_IPSR_MODSEL_DATA(IP11_26, VI1_DATA6, SEL_VI1_0),
1419 PINMUX_IPSR_DATA(IP11_26, AVB_MAGIC),
1420 PINMUX_IPSR_MODSEL_DATA(IP11_27, VI1_DATA7, SEL_VI1_0),
1421 PINMUX_IPSR_DATA(IP11_27, AVB_MDC),
1422 PINMUX_IPSR_DATA(IP11_29_28, ETH_MDIO),
1423 PINMUX_IPSR_DATA(IP11_29_28, AVB_RX_CLK),
1424 PINMUX_IPSR_MODSEL_DATA(IP11_29_28, SCL2_C, SEL_IIC2_2),
1425 PINMUX_IPSR_DATA(IP11_31_30, ETH_CRS_DV),
1426 PINMUX_IPSR_DATA(IP11_31_30, AVB_LINK),
1427 PINMUX_IPSR_MODSEL_DATA(IP11_31_30, SDA2_C, SEL_IIC2_2),
1428
1429 /* IPSR12 */
1430 PINMUX_IPSR_DATA(IP12_1_0, ETH_RX_ER),
1431 PINMUX_IPSR_DATA(IP12_1_0, AVB_CRS),
1432 PINMUX_IPSR_MODSEL_DATA(IP12_1_0, SCL3, SEL_IIC3_0),
1433 PINMUX_IPSR_MODSEL_DATA(IP12_1_0, SCL7, SEL_IIC7_0),
1434 PINMUX_IPSR_DATA(IP12_3_2, ETH_RXD0),
1435 PINMUX_IPSR_DATA(IP12_3_2, AVB_PHY_INT),
1436 PINMUX_IPSR_MODSEL_DATA(IP12_3_2, SDA3, SEL_IIC3_0),
1437 PINMUX_IPSR_MODSEL_DATA(IP12_3_2, SDA7, SEL_IIC7_0),
1438 PINMUX_IPSR_DATA(IP12_6_4, ETH_RXD1),
1439 PINMUX_IPSR_DATA(IP12_6_4, AVB_GTXREFCLK),
1440 PINMUX_IPSR_MODSEL_DATA(IP12_6_4, CAN0_TX_C, SEL_CAN0_2),
1441 PINMUX_IPSR_MODSEL_DATA(IP12_6_4, SCL2_D, SEL_IIC2_3),
1442 PINMUX_IPSR_MODSEL_DATA(IP12_6_4, MSIOF1_RXD_E, SEL_SOF1_4),
1443 PINMUX_IPSR_DATA(IP12_9_7, ETH_LINK),
1444 PINMUX_IPSR_DATA(IP12_9_7, AVB_TXD0),
1445 PINMUX_IPSR_MODSEL_DATA(IP12_9_7, CAN0_RX_C, SEL_CAN0_2),
1446 PINMUX_IPSR_MODSEL_DATA(IP12_9_7, SDA2_D, SEL_IIC2_3),
1447 PINMUX_IPSR_MODSEL_DATA(IP12_9_7, MSIOF1_SCK_E, SEL_SOF1_4),
1448 PINMUX_IPSR_DATA(IP12_12_10, ETH_REFCLK),
1449 PINMUX_IPSR_DATA(IP12_12_10, AVB_TXD1),
1450 PINMUX_IPSR_MODSEL_DATA(IP12_12_10, SCIFA3_RXD_B, SEL_SCIFA3_1),
1451 PINMUX_IPSR_MODSEL_DATA(IP12_12_10, CAN1_RX_C, SEL_CAN1_2),
1452 PINMUX_IPSR_MODSEL_DATA(IP12_12_10, MSIOF1_SYNC_E, SEL_SOF1_4),
1453 PINMUX_IPSR_DATA(IP12_15_13, ETH_TXD1),
1454 PINMUX_IPSR_DATA(IP12_15_13, AVB_TXD2),
1455 PINMUX_IPSR_MODSEL_DATA(IP12_15_13, SCIFA3_TXD_B, SEL_SCIFA3_1),
1456 PINMUX_IPSR_MODSEL_DATA(IP12_15_13, CAN1_TX_C, SEL_CAN1_2),
1457 PINMUX_IPSR_MODSEL_DATA(IP12_15_13, MSIOF1_TXD_E, SEL_SOF1_4),
1458 PINMUX_IPSR_DATA(IP12_17_16, ETH_TX_EN),
1459 PINMUX_IPSR_DATA(IP12_17_16, AVB_TXD3),
1460 PINMUX_IPSR_MODSEL_DATA(IP12_17_16, TCLK1_B, SEL_TMU1_0),
1461 PINMUX_IPSR_MODSEL_DATA(IP12_17_16, CAN_CLK_B, SEL_CANCLK_1),
1462 PINMUX_IPSR_DATA(IP12_19_18, ETH_MAGIC),
1463 PINMUX_IPSR_DATA(IP12_19_18, AVB_TXD4),
1464 PINMUX_IPSR_MODSEL_DATA(IP12_19_18, IETX_C, SEL_IEB_2),
1465 PINMUX_IPSR_DATA(IP12_21_20, ETH_TXD0),
1466 PINMUX_IPSR_DATA(IP12_21_20, AVB_TXD5),
1467 PINMUX_IPSR_MODSEL_DATA(IP12_21_20, IECLK_C, SEL_IEB_2),
1468 PINMUX_IPSR_DATA(IP12_23_22, ETH_MDC),
1469 PINMUX_IPSR_DATA(IP12_23_22, AVB_TXD6),
1470 PINMUX_IPSR_MODSEL_DATA(IP12_23_22, IERX_C, SEL_IEB_2),
1471 PINMUX_IPSR_MODSEL_DATA(IP12_26_24, STP_IVCXO27_0, SEL_SSP_0),
1472 PINMUX_IPSR_DATA(IP12_26_24, AVB_TXD7),
1473 PINMUX_IPSR_MODSEL_DATA(IP12_26_24, SCIFB2_TXD_D, SEL_SCIFB2_3),
1474 PINMUX_IPSR_MODSEL_DATA(IP12_26_24, ADIDATA_B, SEL_RAD_1),
1475 PINMUX_IPSR_MODSEL_DATA(IP12_26_24, MSIOF0_SYNC_C, SEL_SOF0_2),
1476 PINMUX_IPSR_MODSEL_DATA(IP12_29_27, STP_ISCLK_0, SEL_SSP_0),
1477 PINMUX_IPSR_DATA(IP12_29_27, AVB_TX_EN),
1478 PINMUX_IPSR_MODSEL_DATA(IP12_29_27, SCIFB2_RXD_D, SEL_SCIFB2_3),
1479 PINMUX_IPSR_MODSEL_DATA(IP12_29_27, ADICS_SAMP_B, SEL_RAD_1),
1480 PINMUX_IPSR_MODSEL_DATA(IP12_29_27, MSIOF0_SCK_C, SEL_SOF0_2),
1481
1482 /* IPSR13 */
1483 PINMUX_IPSR_MODSEL_DATA(IP13_2_0, STP_ISD_0, SEL_SSP_0),
1484 PINMUX_IPSR_DATA(IP13_2_0, AVB_TX_ER),
1485 PINMUX_IPSR_MODSEL_DATA(IP13_2_0, SCIFB2_SCK_C, SEL_SCIFB2_2),
1486 PINMUX_IPSR_MODSEL_DATA(IP13_2_0, ADICLK_B, SEL_RAD_1),
1487 PINMUX_IPSR_MODSEL_DATA(IP13_2_0, MSIOF0_SS1_C, SEL_SOF0_2),
1488 PINMUX_IPSR_MODSEL_DATA(IP13_4_3, STP_ISEN_0, SEL_SSP_0),
1489 PINMUX_IPSR_DATA(IP13_4_3, AVB_TX_CLK),
1490 PINMUX_IPSR_MODSEL_DATA(IP13_4_3, ADICHS0_B, SEL_RAD_1),
1491 PINMUX_IPSR_MODSEL_DATA(IP13_4_3, MSIOF0_SS2_C, SEL_SOF0_2),
1492 PINMUX_IPSR_MODSEL_DATA(IP13_6_5, STP_ISSYNC_0, SEL_SSP_0),
1493 PINMUX_IPSR_DATA(IP13_6_5, AVB_COL),
1494 PINMUX_IPSR_MODSEL_DATA(IP13_6_5, ADICHS1_B, SEL_RAD_1),
1495 PINMUX_IPSR_MODSEL_DATA(IP13_6_5, MSIOF0_RXD_C, SEL_SOF0_2),
1496 PINMUX_IPSR_MODSEL_DATA(IP13_9_7, STP_OPWM_0, SEL_SSP_0),
1497 PINMUX_IPSR_DATA(IP13_9_7, AVB_GTX_CLK),
1498 PINMUX_IPSR_DATA(IP13_9_7, PWM0_B),
1499 PINMUX_IPSR_MODSEL_DATA(IP13_9_7, ADICHS2_B, SEL_RAD_1),
1500 PINMUX_IPSR_MODSEL_DATA(IP13_9_7, MSIOF0_TXD_C, SEL_SOF0_2),
1501 PINMUX_IPSR_DATA(IP13_10, SD0_CLK),
1502 PINMUX_IPSR_MODSEL_DATA(IP13_10, SPCLK_B, SEL_QSP_1),
1503 PINMUX_IPSR_DATA(IP13_11, SD0_CMD),
1504 PINMUX_IPSR_MODSEL_DATA(IP13_11, MOSI_IO0_B, SEL_QSP_1),
1505 PINMUX_IPSR_DATA(IP13_12, SD0_DATA0),
1506 PINMUX_IPSR_MODSEL_DATA(IP13_12, MISO_IO1_B, SEL_QSP_1),
1507 PINMUX_IPSR_DATA(IP13_13, SD0_DATA1),
1508 PINMUX_IPSR_MODSEL_DATA(IP13_13, IO2_B, SEL_QSP_1),
1509 PINMUX_IPSR_DATA(IP13_14, SD0_DATA2),
1510 PINMUX_IPSR_MODSEL_DATA(IP13_14, IO3_B, SEL_QSP_1),
1511 PINMUX_IPSR_DATA(IP13_15, SD0_DATA3),
1512 PINMUX_IPSR_MODSEL_DATA(IP13_15, SSL_B, SEL_QSP_1),
1513 PINMUX_IPSR_DATA(IP13_18_16, SD0_CD),
1514 PINMUX_IPSR_MODSEL_DATA(IP13_18_16, MMC_D6_B, SEL_MMC_1),
1515 PINMUX_IPSR_MODSEL_DATA(IP13_18_16, SIM0_RST_B, SEL_SIM_1),
1516 PINMUX_IPSR_MODSEL_DATA(IP13_18_16, CAN0_RX_F, SEL_CAN0_5),
1517 PINMUX_IPSR_MODSEL_DATA(IP13_18_16, SCIFA5_TXD_B, SEL_SCIFA5_1),
1518 PINMUX_IPSR_MODSEL_DATA(IP13_18_16, TX3_C, SEL_SCIF3_2),
1519 PINMUX_IPSR_DATA(IP13_21_19, SD0_WP),
1520 PINMUX_IPSR_MODSEL_DATA(IP13_21_19, MMC_D7_B, SEL_MMC_1),
1521 PINMUX_IPSR_MODSEL_DATA(IP13_21_19, SIM0_D_B, SEL_SIM_1),
1522 PINMUX_IPSR_MODSEL_DATA(IP13_21_19, CAN0_TX_F, SEL_CAN0_5),
1523 PINMUX_IPSR_MODSEL_DATA(IP13_21_19, SCIFA5_RXD_B, SEL_SCIFA5_1),
1524 PINMUX_IPSR_MODSEL_DATA(IP13_21_19, RX3_C, SEL_SCIF3_2),
1525 PINMUX_IPSR_DATA(IP13_22, SD1_CMD),
1526 PINMUX_IPSR_MODSEL_DATA(IP13_22, REMOCON_B, SEL_RCN_1),
1527 PINMUX_IPSR_DATA(IP13_24_23, SD1_DATA0),
1528 PINMUX_IPSR_MODSEL_DATA(IP13_24_23, SPEEDIN_B, SEL_RSP_1),
1529 PINMUX_IPSR_DATA(IP13_25, SD1_DATA1),
1530 PINMUX_IPSR_MODSEL_DATA(IP13_25, IETX_B, SEL_IEB_1),
1531 PINMUX_IPSR_DATA(IP13_26, SD1_DATA2),
1532 PINMUX_IPSR_MODSEL_DATA(IP13_26, IECLK_B, SEL_IEB_1),
1533 PINMUX_IPSR_DATA(IP13_27, SD1_DATA3),
1534 PINMUX_IPSR_MODSEL_DATA(IP13_27, IERX_B, SEL_IEB_1),
1535 PINMUX_IPSR_DATA(IP13_30_28, SD1_CD),
1536 PINMUX_IPSR_DATA(IP13_30_28, PWM0),
1537 PINMUX_IPSR_DATA(IP13_30_28, TPU_TO0),
1538 PINMUX_IPSR_MODSEL_DATA(IP13_30_28, SCL1_C, SEL_IIC1_2),
1539
1540 /* IPSR14 */
1541 PINMUX_IPSR_DATA(IP14_1_0, SD1_WP),
1542 PINMUX_IPSR_DATA(IP14_1_0, PWM1_B),
1543 PINMUX_IPSR_MODSEL_DATA(IP14_1_0, SDA1_C, SEL_IIC1_2),
1544 PINMUX_IPSR_DATA(IP14_2, SD2_CLK),
1545 PINMUX_IPSR_DATA(IP14_2, MMC_CLK),
1546 PINMUX_IPSR_DATA(IP14_3, SD2_CMD),
1547 PINMUX_IPSR_DATA(IP14_3, MMC_CMD),
1548 PINMUX_IPSR_DATA(IP14_4, SD2_DATA0),
1549 PINMUX_IPSR_DATA(IP14_4, MMC_D0),
1550 PINMUX_IPSR_DATA(IP14_5, SD2_DATA1),
1551 PINMUX_IPSR_DATA(IP14_5, MMC_D1),
1552 PINMUX_IPSR_DATA(IP14_6, SD2_DATA2),
1553 PINMUX_IPSR_DATA(IP14_6, MMC_D2),
1554 PINMUX_IPSR_DATA(IP14_7, SD2_DATA3),
1555 PINMUX_IPSR_DATA(IP14_7, MMC_D3),
1556 PINMUX_IPSR_DATA(IP14_10_8, SD2_CD),
1557 PINMUX_IPSR_DATA(IP14_10_8, MMC_D4),
1558 PINMUX_IPSR_MODSEL_DATA(IP14_10_8, SCL8_C, SEL_IIC8_2),
1559 PINMUX_IPSR_MODSEL_DATA(IP14_10_8, TX5_B, SEL_SCIF5_1),
1560 PINMUX_IPSR_MODSEL_DATA(IP14_10_8, SCIFA5_TXD_C, SEL_SCIFA5_2),
1561 PINMUX_IPSR_DATA(IP14_13_11, SD2_WP),
1562 PINMUX_IPSR_DATA(IP14_13_11, MMC_D5),
1563 PINMUX_IPSR_MODSEL_DATA(IP14_13_11, SDA8_C, SEL_IIC8_2),
1564 PINMUX_IPSR_MODSEL_DATA(IP14_13_11, RX5_B, SEL_SCIF5_1),
1565 PINMUX_IPSR_MODSEL_DATA(IP14_13_11, SCIFA5_RXD_C, SEL_SCIFA5_2),
1566 PINMUX_IPSR_MODSEL_DATA(IP14_16_14, MSIOF0_SCK, SEL_SOF0_0),
1567 PINMUX_IPSR_MODSEL_DATA(IP14_16_14, RX2_C, SEL_SCIF2_2),
1568 PINMUX_IPSR_MODSEL_DATA(IP14_16_14, ADIDATA, SEL_RAD_0),
1569 PINMUX_IPSR_MODSEL_DATA(IP14_16_14, VI1_CLK_C, SEL_VI1_2),
1570 PINMUX_IPSR_DATA(IP14_16_14, VI1_G0_B),
1571 PINMUX_IPSR_MODSEL_DATA(IP14_19_17, MSIOF0_SYNC, SEL_SOF0_0),
1572 PINMUX_IPSR_MODSEL_DATA(IP14_19_17, TX2_C, SEL_SCIF2_2),
1573 PINMUX_IPSR_MODSEL_DATA(IP14_19_17, ADICS_SAMP, SEL_RAD_0),
1574 PINMUX_IPSR_MODSEL_DATA(IP14_19_17, VI1_CLKENB_C, SEL_VI1_2),
1575 PINMUX_IPSR_DATA(IP14_19_17, VI1_G1_B),
1576 PINMUX_IPSR_MODSEL_DATA(IP14_22_20, MSIOF0_TXD, SEL_SOF0_0),
1577 PINMUX_IPSR_MODSEL_DATA(IP14_22_20, ADICLK, SEL_RAD_0),
1578 PINMUX_IPSR_MODSEL_DATA(IP14_22_20, VI1_FIELD_C, SEL_VI1_2),
1579 PINMUX_IPSR_DATA(IP14_22_20, VI1_G2_B),
1580 PINMUX_IPSR_MODSEL_DATA(IP14_25_23, MSIOF0_RXD, SEL_SOF0_0),
1581 PINMUX_IPSR_MODSEL_DATA(IP14_25_23, ADICHS0, SEL_RAD_0),
1582 PINMUX_IPSR_MODSEL_DATA(IP14_25_23, VI1_DATA0_C, SEL_VI1_2),
1583 PINMUX_IPSR_DATA(IP14_25_23, VI1_G3_B),
1584 PINMUX_IPSR_MODSEL_DATA(IP14_28_26, MSIOF0_SS1, SEL_SOF0_0),
1585 PINMUX_IPSR_MODSEL_DATA(IP14_28_26, MMC_D6, SEL_MMC_0),
1586 PINMUX_IPSR_MODSEL_DATA(IP14_28_26, ADICHS1, SEL_RAD_0),
1587 PINMUX_IPSR_MODSEL_DATA(IP14_28_26, TX0_E, SEL_SCIF0_4),
1588 PINMUX_IPSR_MODSEL_DATA(IP14_28_26, VI1_HSYNC_N_C, SEL_VI1_2),
1589 PINMUX_IPSR_MODSEL_DATA(IP14_28_26, SCL7_C, SEL_IIC7_2),
1590 PINMUX_IPSR_DATA(IP14_28_26, VI1_G4_B),
1591 PINMUX_IPSR_MODSEL_DATA(IP14_31_29, MSIOF0_SS2, SEL_SOF0_0),
1592 PINMUX_IPSR_MODSEL_DATA(IP14_31_29, MMC_D7, SEL_MMC_0),
1593 PINMUX_IPSR_MODSEL_DATA(IP14_31_29, ADICHS2, SEL_RAD_0),
1594 PINMUX_IPSR_MODSEL_DATA(IP14_31_29, RX0_E, SEL_SCIF0_4),
1595 PINMUX_IPSR_MODSEL_DATA(IP14_31_29, VI1_VSYNC_N_C, SEL_VI1_2),
1596 PINMUX_IPSR_MODSEL_DATA(IP14_31_29, SDA7_C, SEL_IIC7_2),
1597 PINMUX_IPSR_DATA(IP14_31_29, VI1_G5_B),
1598
1599 /* IPSR15 */
1600 PINMUX_IPSR_MODSEL_DATA(IP15_1_0, SIM0_RST, SEL_SIM_0),
1601 PINMUX_IPSR_MODSEL_DATA(IP15_1_0, IETX, SEL_IEB_0),
1602 PINMUX_IPSR_MODSEL_DATA(IP15_1_0, CAN1_TX_D, SEL_CAN1_3),
1603 PINMUX_IPSR_DATA(IP15_3_2, SIM0_CLK),
1604 PINMUX_IPSR_MODSEL_DATA(IP15_3_2, IECLK, SEL_IEB_0),
1605 PINMUX_IPSR_MODSEL_DATA(IP15_3_2, CAN_CLK_C, SEL_CANCLK_2),
1606 PINMUX_IPSR_MODSEL_DATA(IP15_5_4, SIM0_D, SEL_SIM_0),
1607 PINMUX_IPSR_MODSEL_DATA(IP15_5_4, IERX, SEL_IEB_0),
1608 PINMUX_IPSR_MODSEL_DATA(IP15_5_4, CAN1_RX_D, SEL_CAN1_3),
1609 PINMUX_IPSR_MODSEL_DATA(IP15_8_6, GPS_CLK, SEL_GPS_0),
1610 PINMUX_IPSR_MODSEL_DATA(IP15_8_6, DU1_DOTCLKIN_C, SEL_DIS_2),
1611 PINMUX_IPSR_MODSEL_DATA(IP15_8_6, AUDIO_CLKB_B, SEL_ADG_1),
1612 PINMUX_IPSR_DATA(IP15_8_6, PWM5_B),
1613 PINMUX_IPSR_MODSEL_DATA(IP15_8_6, SCIFA3_TXD_C, SEL_SCIFA3_2),
1614 PINMUX_IPSR_MODSEL_DATA(IP15_11_9, GPS_SIGN, SEL_GPS_0),
1615 PINMUX_IPSR_MODSEL_DATA(IP15_11_9, TX4_C, SEL_SCIF4_2),
1616 PINMUX_IPSR_MODSEL_DATA(IP15_11_9, SCIFA4_TXD_C, SEL_SCIFA4_2),
1617 PINMUX_IPSR_DATA(IP15_11_9, PWM5),
1618 PINMUX_IPSR_DATA(IP15_11_9, VI1_G6_B),
1619 PINMUX_IPSR_MODSEL_DATA(IP15_11_9, SCIFA3_RXD_C, SEL_SCIFA3_2),
1620 PINMUX_IPSR_MODSEL_DATA(IP15_14_12, GPS_MAG, SEL_GPS_0),
1621 PINMUX_IPSR_MODSEL_DATA(IP15_14_12, RX4_C, SEL_SCIF4_2),
1622 PINMUX_IPSR_MODSEL_DATA(IP15_14_12, SCIFA4_RXD_C, SEL_SCIFA4_2),
1623 PINMUX_IPSR_DATA(IP15_14_12, PWM6),
1624 PINMUX_IPSR_DATA(IP15_14_12, VI1_G7_B),
1625 PINMUX_IPSR_MODSEL_DATA(IP15_14_12, SCIFA3_SCK_C, SEL_SCIFA3_2),
1626 PINMUX_IPSR_MODSEL_DATA(IP15_17_15, HCTS0_N, SEL_HSCIF0_0),
1627 PINMUX_IPSR_MODSEL_DATA(IP15_17_15, SCIFB0_CTS_N, SEL_SCIFB_0),
1628 PINMUX_IPSR_MODSEL_DATA(IP15_17_15, GLO_I0_C, SEL_GPS_2),
1629 PINMUX_IPSR_MODSEL_DATA(IP15_17_15, TCLK1, SEL_TMU1_0),
1630 PINMUX_IPSR_MODSEL_DATA(IP15_17_15, VI1_DATA1_C, SEL_VI1_2),
1631 PINMUX_IPSR_MODSEL_DATA(IP15_20_18, HRTS0_N, SEL_HSCIF0_0),
1632 PINMUX_IPSR_MODSEL_DATA(IP15_20_18, SCIFB0_RTS_N, SEL_SCIFB_0),
1633 PINMUX_IPSR_MODSEL_DATA(IP15_20_18, GLO_I1_C, SEL_GPS_2),
1634 PINMUX_IPSR_MODSEL_DATA(IP15_20_18, VI1_DATA2_C, SEL_VI1_2),
1635 PINMUX_IPSR_MODSEL_DATA(IP15_23_21, HSCK0, SEL_HSCIF0_0),
1636 PINMUX_IPSR_MODSEL_DATA(IP15_23_21, SCIFB0_SCK, SEL_SCIFB_0),
1637 PINMUX_IPSR_MODSEL_DATA(IP15_23_21, GLO_Q0_C, SEL_GPS_2),
1638 PINMUX_IPSR_MODSEL_DATA(IP15_23_21, CAN_CLK, SEL_CANCLK_0),
1639 PINMUX_IPSR_DATA(IP15_23_21, TCLK2),
1640 PINMUX_IPSR_MODSEL_DATA(IP15_23_21, VI1_DATA3_C, SEL_VI1_2),
1641 PINMUX_IPSR_MODSEL_DATA(IP15_26_24, HRX0, SEL_HSCIF0_0),
1642 PINMUX_IPSR_MODSEL_DATA(IP15_26_24, SCIFB0_RXD, SEL_SCIFB_0),
1643 PINMUX_IPSR_MODSEL_DATA(IP15_26_24, GLO_Q1_C, SEL_GPS_2),
1644 PINMUX_IPSR_MODSEL_DATA(IP15_26_24, CAN0_RX_B, SEL_CAN0_1),
1645 PINMUX_IPSR_MODSEL_DATA(IP15_26_24, VI1_DATA4_C, SEL_VI1_2),
1646 PINMUX_IPSR_MODSEL_DATA(IP15_29_27, HTX0, SEL_HSCIF0_0),
1647 PINMUX_IPSR_MODSEL_DATA(IP15_29_27, SCIFB0_TXD, SEL_SCIFB_0),
1648 PINMUX_IPSR_MODSEL_DATA(IP15_29_27, GLO_SCLK_C, SEL_GPS_2),
1649 PINMUX_IPSR_MODSEL_DATA(IP15_29_27, CAN0_TX_B, SEL_CAN0_1),
1650 PINMUX_IPSR_MODSEL_DATA(IP15_29_27, VI1_DATA5_C, SEL_VI1_2),
1651
1652 /* IPSR16 */
1653 PINMUX_IPSR_MODSEL_DATA(IP16_2_0, HRX1, SEL_HSCIF1_0),
1654 PINMUX_IPSR_MODSEL_DATA(IP16_2_0, SCIFB1_RXD, SEL_SCIFB1_0),
1655 PINMUX_IPSR_DATA(IP16_2_0, VI1_R0_B),
1656 PINMUX_IPSR_MODSEL_DATA(IP16_2_0, GLO_SDATA_C, SEL_GPS_2),
1657 PINMUX_IPSR_MODSEL_DATA(IP16_2_0, VI1_DATA6_C, SEL_VI1_2),
1658 PINMUX_IPSR_MODSEL_DATA(IP16_5_3, HTX1, SEL_HSCIF1_0),
1659 PINMUX_IPSR_MODSEL_DATA(IP16_5_3, SCIFB1_TXD, SEL_SCIFB1_0),
1660 PINMUX_IPSR_DATA(IP16_5_3, VI1_R1_B),
1661 PINMUX_IPSR_MODSEL_DATA(IP16_5_3, GLO_SS_C, SEL_GPS_2),
1662 PINMUX_IPSR_MODSEL_DATA(IP16_5_3, VI1_DATA7_C, SEL_VI1_2),
1663 PINMUX_IPSR_MODSEL_DATA(IP16_7_6, HSCK1, SEL_HSCIF1_0),
1664 PINMUX_IPSR_MODSEL_DATA(IP16_7_6, SCIFB1_SCK, SEL_SCIFB1_0),
1665 PINMUX_IPSR_DATA(IP16_7_6, MLB_CK),
1666 PINMUX_IPSR_MODSEL_DATA(IP16_7_6, GLO_RFON_C, SEL_GPS_2),
1667 PINMUX_IPSR_MODSEL_DATA(IP16_9_8, HCTS1_N, SEL_HSCIF1_0),
1668 PINMUX_IPSR_DATA(IP16_9_8, SCIFB1_CTS_N),
1669 PINMUX_IPSR_DATA(IP16_9_8, MLB_SIG),
1670 PINMUX_IPSR_MODSEL_DATA(IP16_9_8, CAN1_TX_B, SEL_CAN1_1),
1671 PINMUX_IPSR_MODSEL_DATA(IP16_11_10, HRTS1_N, SEL_HSCIF1_0),
1672 PINMUX_IPSR_DATA(IP16_11_10, SCIFB1_RTS_N),
1673 PINMUX_IPSR_DATA(IP16_11_10, MLB_DAT),
1674 PINMUX_IPSR_MODSEL_DATA(IP16_11_10, CAN1_RX_B, SEL_CAN1_1),
1675};
1676
1677static struct sh_pfc_pin pinmux_pins[] = {
1678 PINMUX_GPIO_GP_ALL(),
1679};
1680
1681/* - DU --------------------------------------------------------------------- */
1682static const unsigned int du_rgb666_pins[] = {
1683 /* R[7:2], G[7:2], B[7:2] */
1684 RCAR_GP_PIN(3, 7), RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 5),
1685 RCAR_GP_PIN(3, 4), RCAR_GP_PIN(3, 3), RCAR_GP_PIN(3, 2),
1686 RCAR_GP_PIN(3, 15), RCAR_GP_PIN(3, 14), RCAR_GP_PIN(3, 13),
1687 RCAR_GP_PIN(3, 12), RCAR_GP_PIN(3, 11), RCAR_GP_PIN(3, 10),
1688 RCAR_GP_PIN(3, 23), RCAR_GP_PIN(3, 22), RCAR_GP_PIN(3, 21),
1689 RCAR_GP_PIN(3, 20), RCAR_GP_PIN(3, 19), RCAR_GP_PIN(3, 18),
1690};
1691static const unsigned int du_rgb666_mux[] = {
1692 DU1_DR7_MARK, DU1_DR6_MARK, DU1_DR5_MARK, DU1_DR4_MARK,
1693 DU1_DR3_MARK, DU1_DR2_MARK,
1694 DU1_DG7_MARK, DU1_DG6_MARK, DU1_DG5_MARK, DU1_DG4_MARK,
1695 DU1_DG3_MARK, DU1_DG2_MARK,
1696 DU1_DB7_MARK, DU1_DB6_MARK, DU1_DB5_MARK, DU1_DB4_MARK,
1697 DU1_DB3_MARK, DU1_DB2_MARK,
1698};
1699static const unsigned int du_rgb888_pins[] = {
1700 /* R[7:0], G[7:0], B[7:0] */
1701 RCAR_GP_PIN(3, 7), RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 5),
1702 RCAR_GP_PIN(3, 4), RCAR_GP_PIN(3, 3), RCAR_GP_PIN(3, 2),
1703 RCAR_GP_PIN(3, 1), RCAR_GP_PIN(3, 0),
1704 RCAR_GP_PIN(3, 15), RCAR_GP_PIN(3, 14), RCAR_GP_PIN(3, 13),
1705 RCAR_GP_PIN(3, 12), RCAR_GP_PIN(3, 11), RCAR_GP_PIN(3, 10),
1706 RCAR_GP_PIN(3, 9), RCAR_GP_PIN(3, 8),
1707 RCAR_GP_PIN(3, 23), RCAR_GP_PIN(3, 22), RCAR_GP_PIN(3, 21),
1708 RCAR_GP_PIN(3, 20), RCAR_GP_PIN(3, 19), RCAR_GP_PIN(3, 18),
1709 RCAR_GP_PIN(3, 17), RCAR_GP_PIN(3, 16),
1710};
1711static const unsigned int du_rgb888_mux[] = {
1712 DU1_DR7_MARK, DU1_DR6_MARK, DU1_DR5_MARK, DU1_DR4_MARK,
1713 DU1_DR3_MARK, DU1_DR2_MARK, DU1_DR1_MARK, DU1_DR0_MARK,
1714 DU1_DG7_MARK, DU1_DG6_MARK, DU1_DG5_MARK, DU1_DG4_MARK,
1715 DU1_DG3_MARK, DU1_DG2_MARK, DU1_DG1_MARK, DU1_DG0_MARK,
1716 DU1_DB7_MARK, DU1_DB6_MARK, DU1_DB5_MARK, DU1_DB4_MARK,
1717 DU1_DB3_MARK, DU1_DB2_MARK, DU1_DB1_MARK, DU1_DB0_MARK,
1718};
1719static const unsigned int du_clk_out_0_pins[] = {
1720 /* CLKOUT */
1721 RCAR_GP_PIN(3, 25),
1722};
1723static const unsigned int du_clk_out_0_mux[] = {
1724 DU1_DOTCLKOUT0_MARK
1725};
1726static const unsigned int du_clk_out_1_pins[] = {
1727 /* CLKOUT */
1728 RCAR_GP_PIN(3, 26),
1729};
1730static const unsigned int du_clk_out_1_mux[] = {
1731 DU1_DOTCLKOUT1_MARK
1732};
1733static const unsigned int du_sync_1_pins[] = {
1734 /* EXVSYNC/VSYNC, EXHSYNC/HSYNC, EXDISP/EXODDF/EXCDE */
1735 RCAR_GP_PIN(3, 29), RCAR_GP_PIN(3, 28), RCAR_GP_PIN(3, 27),
1736};
1737static const unsigned int du_sync_1_mux[] = {
1738 DU1_EXODDF_DU1_ODDF_DISP_CDE_MARK,
1739 DU1_EXVSYNC_DU1_VSYNC_MARK, DU1_EXHSYNC_DU1_HSYNC_MARK
1740};
1741static const unsigned int du_cde_disp_pins[] = {
1742 /* CDE DISP */
1743 RCAR_GP_PIN(3, 31), RCAR_GP_PIN(3, 30),
1744};
1745static const unsigned int du0_clk_in_pins[] = {
1746 /* CLKIN */
1747 RCAR_GP_PIN(6, 31),
1748};
1749static const unsigned int du0_clk_in_mux[] = {
1750 DU0_DOTCLKIN_MARK
1751};
1752static const unsigned int du_cde_disp_mux[] = {
1753 DU1_CDE_MARK, DU1_DISP_MARK
1754};
1755static const unsigned int du1_clk_in_pins[] = {
1756 /* CLKIN */
1757 RCAR_GP_PIN(7, 20), RCAR_GP_PIN(7, 19), RCAR_GP_PIN(3, 24),
1758};
1759static const unsigned int du1_clk_in_mux[] = {
1760 DU1_DOTCLKIN_C_MARK, DU1_DOTCLKIN_B_MARK, DU1_DOTCLKIN_MARK
1761};
1762/* - ETH -------------------------------------------------------------------- */
1763static const unsigned int eth_link_pins[] = {
1764 /* LINK */
1765 RCAR_GP_PIN(5, 18),
1766};
1767static const unsigned int eth_link_mux[] = {
1768 ETH_LINK_MARK,
1769};
1770static const unsigned int eth_magic_pins[] = {
1771 /* MAGIC */
1772 RCAR_GP_PIN(5, 22),
1773};
1774static const unsigned int eth_magic_mux[] = {
1775 ETH_MAGIC_MARK,
1776};
1777static const unsigned int eth_mdio_pins[] = {
1778 /* MDC, MDIO */
1779 RCAR_GP_PIN(5, 24), RCAR_GP_PIN(5, 13),
1780};
1781static const unsigned int eth_mdio_mux[] = {
1782 ETH_MDC_MARK, ETH_MDIO_MARK,
1783};
1784static const unsigned int eth_rmii_pins[] = {
1785 /* RXD[0:1], RX_ER, CRS_DV, TXD[0:1], TX_EN, REF_CLK */
1786 RCAR_GP_PIN(5, 16), RCAR_GP_PIN(5, 17), RCAR_GP_PIN(5, 15),
1787 RCAR_GP_PIN(5, 14), RCAR_GP_PIN(5, 23), RCAR_GP_PIN(5, 20),
1788 RCAR_GP_PIN(5, 21), RCAR_GP_PIN(5, 19),
1789};
1790static const unsigned int eth_rmii_mux[] = {
1791 ETH_RXD0_MARK, ETH_RXD1_MARK, ETH_RX_ER_MARK, ETH_CRS_DV_MARK,
1792 ETH_TXD0_MARK, ETH_TXD1_MARK, ETH_TX_EN_MARK, ETH_REFCLK_MARK,
1793};
1794/* - INTC ------------------------------------------------------------------- */
1795static const unsigned int intc_irq0_pins[] = {
1796 /* IRQ */
1797 RCAR_GP_PIN(7, 10),
1798};
1799static const unsigned int intc_irq0_mux[] = {
1800 IRQ0_MARK,
1801};
1802static const unsigned int intc_irq1_pins[] = {
1803 /* IRQ */
1804 RCAR_GP_PIN(7, 11),
1805};
1806static const unsigned int intc_irq1_mux[] = {
1807 IRQ1_MARK,
1808};
1809static const unsigned int intc_irq2_pins[] = {
1810 /* IRQ */
1811 RCAR_GP_PIN(7, 12),
1812};
1813static const unsigned int intc_irq2_mux[] = {
1814 IRQ2_MARK,
1815};
1816static const unsigned int intc_irq3_pins[] = {
1817 /* IRQ */
1818 RCAR_GP_PIN(7, 13),
1819};
1820static const unsigned int intc_irq3_mux[] = {
1821 IRQ3_MARK,
1822};
1823/* - MMCIF ------------------------------------------------------------------ */
1824static const unsigned int mmc_data1_pins[] = {
1825 /* D[0] */
1826 RCAR_GP_PIN(6, 18),
1827};
1828static const unsigned int mmc_data1_mux[] = {
1829 MMC_D0_MARK,
1830};
1831static const unsigned int mmc_data4_pins[] = {
1832 /* D[0:3] */
1833 RCAR_GP_PIN(6, 18), RCAR_GP_PIN(6, 19),
1834 RCAR_GP_PIN(6, 20), RCAR_GP_PIN(6, 21),
1835};
1836static const unsigned int mmc_data4_mux[] = {
1837 MMC_D0_MARK, MMC_D1_MARK, MMC_D2_MARK, MMC_D3_MARK,
1838};
1839static const unsigned int mmc_data8_pins[] = {
1840 /* D[0:7] */
1841 RCAR_GP_PIN(6, 18), RCAR_GP_PIN(6, 19),
1842 RCAR_GP_PIN(6, 20), RCAR_GP_PIN(6, 21),
1843 RCAR_GP_PIN(6, 22), RCAR_GP_PIN(6, 23),
1844 RCAR_GP_PIN(6, 28), RCAR_GP_PIN(6, 29),
1845};
1846static const unsigned int mmc_data8_mux[] = {
1847 MMC_D0_MARK, MMC_D1_MARK, MMC_D2_MARK, MMC_D3_MARK,
1848 MMC_D4_MARK, MMC_D5_MARK, MMC_D6_MARK, MMC_D7_MARK,
1849};
1850static const unsigned int mmc_ctrl_pins[] = {
1851 /* CLK, CMD */
1852 RCAR_GP_PIN(6, 16), RCAR_GP_PIN(6, 17),
1853};
1854static const unsigned int mmc_ctrl_mux[] = {
1855 MMC_CLK_MARK, MMC_CMD_MARK,
1856};
1857/* - MSIOF0 ----------------------------------------------------------------- */
1858static const unsigned int msiof0_clk_pins[] = {
1859 /* SCK */
1860 RCAR_GP_PIN(6, 24),
1861};
1862static const unsigned int msiof0_clk_mux[] = {
1863 MSIOF0_SCK_MARK,
1864};
1865static const unsigned int msiof0_sync_pins[] = {
1866 /* SYNC */
1867 RCAR_GP_PIN(6, 25),
1868};
1869static const unsigned int msiof0_sync_mux[] = {
1870 MSIOF0_SYNC_MARK,
1871};
1872static const unsigned int msiof0_ss1_pins[] = {
1873 /* SS1 */
1874 RCAR_GP_PIN(6, 28),
1875};
1876static const unsigned int msiof0_ss1_mux[] = {
1877 MSIOF0_SS1_MARK,
1878};
1879static const unsigned int msiof0_ss2_pins[] = {
1880 /* SS2 */
1881 RCAR_GP_PIN(6, 29),
1882};
1883static const unsigned int msiof0_ss2_mux[] = {
1884 MSIOF0_SS2_MARK,
1885};
1886static const unsigned int msiof0_rx_pins[] = {
1887 /* RXD */
1888 RCAR_GP_PIN(6, 27),
1889};
1890static const unsigned int msiof0_rx_mux[] = {
1891 MSIOF0_RXD_MARK,
1892};
1893static const unsigned int msiof0_tx_pins[] = {
1894 /* TXD */
1895 RCAR_GP_PIN(6, 26),
1896};
1897static const unsigned int msiof0_tx_mux[] = {
1898 MSIOF0_TXD_MARK,
1899};
1900/* - MSIOF1 ----------------------------------------------------------------- */
1901static const unsigned int msiof1_clk_pins[] = {
1902 /* SCK */
1903 RCAR_GP_PIN(0, 22),
1904};
1905static const unsigned int msiof1_clk_mux[] = {
1906 MSIOF1_SCK_MARK,
1907};
1908static const unsigned int msiof1_sync_pins[] = {
1909 /* SYNC */
1910 RCAR_GP_PIN(0, 23),
1911};
1912static const unsigned int msiof1_sync_mux[] = {
1913 MSIOF1_SYNC_MARK,
1914};
1915static const unsigned int msiof1_ss1_pins[] = {
1916 /* SS1 */
1917 RCAR_GP_PIN(0, 24),
1918};
1919static const unsigned int msiof1_ss1_mux[] = {
1920 MSIOF1_SS1_MARK,
1921};
1922static const unsigned int msiof1_ss2_pins[] = {
1923 /* SS2 */
1924 RCAR_GP_PIN(0, 25),
1925};
1926static const unsigned int msiof1_ss2_mux[] = {
1927 MSIOF1_SS2_MARK,
1928};
1929static const unsigned int msiof1_rx_pins[] = {
1930 /* RXD */
1931 RCAR_GP_PIN(0, 27),
1932};
1933static const unsigned int msiof1_rx_mux[] = {
1934 MSIOF1_RXD_MARK,
1935};
1936static const unsigned int msiof1_tx_pins[] = {
1937 /* TXD */
1938 RCAR_GP_PIN(0, 26),
1939};
1940static const unsigned int msiof1_tx_mux[] = {
1941 MSIOF1_TXD_MARK,
1942};
1943/* - MSIOF2 ----------------------------------------------------------------- */
1944static const unsigned int msiof2_clk_pins[] = {
1945 /* SCK */
1946 RCAR_GP_PIN(1, 13),
1947};
1948static const unsigned int msiof2_clk_mux[] = {
1949 MSIOF2_SCK_MARK,
1950};
1951static const unsigned int msiof2_sync_pins[] = {
1952 /* SYNC */
1953 RCAR_GP_PIN(1, 14),
1954};
1955static const unsigned int msiof2_sync_mux[] = {
1956 MSIOF2_SYNC_MARK,
1957};
1958static const unsigned int msiof2_ss1_pins[] = {
1959 /* SS1 */
1960 RCAR_GP_PIN(1, 17),
1961};
1962static const unsigned int msiof2_ss1_mux[] = {
1963 MSIOF2_SS1_MARK,
1964};
1965static const unsigned int msiof2_ss2_pins[] = {
1966 /* SS2 */
1967 RCAR_GP_PIN(1, 18),
1968};
1969static const unsigned int msiof2_ss2_mux[] = {
1970 MSIOF2_SS2_MARK,
1971};
1972static const unsigned int msiof2_rx_pins[] = {
1973 /* RXD */
1974 RCAR_GP_PIN(1, 16),
1975};
1976static const unsigned int msiof2_rx_mux[] = {
1977 MSIOF2_RXD_MARK,
1978};
1979static const unsigned int msiof2_tx_pins[] = {
1980 /* TXD */
1981 RCAR_GP_PIN(1, 15),
1982};
1983static const unsigned int msiof2_tx_mux[] = {
1984 MSIOF2_TXD_MARK,
1985};
1986/* - SCIF0 ------------------------------------------------------------------ */
1987static const unsigned int scif0_data_pins[] = {
1988 /* RX, TX */
1989 RCAR_GP_PIN(1, 7), RCAR_GP_PIN(1, 6),
1990};
1991static const unsigned int scif0_data_mux[] = {
1992 RX0_MARK, TX0_MARK,
1993};
1994static const unsigned int scif0_data_b_pins[] = {
1995 /* RX, TX */
1996 RCAR_GP_PIN(3, 1), RCAR_GP_PIN(3, 0),
1997};
1998static const unsigned int scif0_data_b_mux[] = {
1999 RX0_B_MARK, TX0_B_MARK,
2000};
2001static const unsigned int scif0_data_c_pins[] = {
2002 /* RX, TX */
2003 RCAR_GP_PIN(4, 26), RCAR_GP_PIN(4, 25),
2004};
2005static const unsigned int scif0_data_c_mux[] = {
2006 RX0_C_MARK, TX0_C_MARK,
2007};
2008static const unsigned int scif0_data_d_pins[] = {
2009 /* RX, TX */
2010 RCAR_GP_PIN(2, 23), RCAR_GP_PIN(2, 22),
2011};
2012static const unsigned int scif0_data_d_mux[] = {
2013 RX0_D_MARK, TX0_D_MARK,
2014};
2015static const unsigned int scif0_data_e_pins[] = {
2016 /* RX, TX */
2017 RCAR_GP_PIN(6, 29), RCAR_GP_PIN(6, 28),
2018};
2019static const unsigned int scif0_data_e_mux[] = {
2020 RX0_E_MARK, TX0_E_MARK,
2021};
2022/* - SCIF1 ------------------------------------------------------------------ */
2023static const unsigned int scif1_data_pins[] = {
2024 /* RX, TX */
2025 RCAR_GP_PIN(1, 9), RCAR_GP_PIN(1, 8),
2026};
2027static const unsigned int scif1_data_mux[] = {
2028 RX1_MARK, TX1_MARK,
2029};
2030static const unsigned int scif1_data_b_pins[] = {
2031 /* RX, TX */
2032 RCAR_GP_PIN(3, 9), RCAR_GP_PIN(3, 8),
2033};
2034static const unsigned int scif1_data_b_mux[] = {
2035 RX1_B_MARK, TX1_B_MARK,
2036};
2037static const unsigned int scif1_clk_b_pins[] = {
2038 /* SCK */
2039 RCAR_GP_PIN(3, 10),
2040};
2041static const unsigned int scif1_clk_b_mux[] = {
2042 SCIF1_SCK_B_MARK,
2043};
2044static const unsigned int scif1_data_c_pins[] = {
2045 /* RX, TX */
2046 RCAR_GP_PIN(4, 28), RCAR_GP_PIN(4, 27),
2047};
2048static const unsigned int scif1_data_c_mux[] = {
2049 RX1_C_MARK, TX1_C_MARK,
2050};
2051static const unsigned int scif1_data_d_pins[] = {
2052 /* RX, TX */
2053 RCAR_GP_PIN(2, 25), RCAR_GP_PIN(2, 24),
2054};
2055static const unsigned int scif1_data_d_mux[] = {
2056 RX1_D_MARK, TX1_D_MARK,
2057};
2058/* - SCIF2 ------------------------------------------------------------------ */
2059static const unsigned int scif2_data_pins[] = {
2060 /* RX, TX */
2061 RCAR_GP_PIN(2, 30), RCAR_GP_PIN(2, 31),
2062};
2063static const unsigned int scif2_data_mux[] = {
2064 RX2_MARK, TX2_MARK,
2065};
2066static const unsigned int scif2_data_b_pins[] = {
2067 /* RX, TX */
2068 RCAR_GP_PIN(3, 17), RCAR_GP_PIN(3, 16),
2069};
2070static const unsigned int scif2_data_b_mux[] = {
2071 RX2_B_MARK, TX2_B_MARK,
2072};
2073static const unsigned int scif2_clk_b_pins[] = {
2074 /* SCK */
2075 RCAR_GP_PIN(3, 18),
2076};
2077static const unsigned int scif2_clk_b_mux[] = {
2078 SCIF2_SCK_B_MARK,
2079};
2080static const unsigned int scif2_data_c_pins[] = {
2081 /* RX, TX */
2082 RCAR_GP_PIN(6, 24), RCAR_GP_PIN(6, 25),
2083};
2084static const unsigned int scif2_data_c_mux[] = {
2085 RX2_C_MARK, TX2_C_MARK,
2086};
2087static const unsigned int scif2_data_e_pins[] = {
2088 /* RX, TX */
2089 RCAR_GP_PIN(2, 7), RCAR_GP_PIN(2, 8),
2090};
2091static const unsigned int scif2_data_e_mux[] = {
2092 RX2_E_MARK, TX2_E_MARK,
2093};
2094/* - SCIF3 ------------------------------------------------------------------ */
2095static const unsigned int scif3_data_pins[] = {
2096 /* RX, TX */
2097 RCAR_GP_PIN(3, 22), RCAR_GP_PIN(3, 21),
2098};
2099static const unsigned int scif3_data_mux[] = {
2100 RX3_MARK, TX3_MARK,
2101};
2102static const unsigned int scif3_clk_pins[] = {
2103 /* SCK */
2104 RCAR_GP_PIN(3, 23),
2105};
2106static const unsigned int scif3_clk_mux[] = {
2107 SCIF3_SCK_MARK,
2108};
2109static const unsigned int scif3_data_b_pins[] = {
2110 /* RX, TX */
2111 RCAR_GP_PIN(3, 29), RCAR_GP_PIN(3, 26),
2112};
2113static const unsigned int scif3_data_b_mux[] = {
2114 RX3_B_MARK, TX3_B_MARK,
2115};
2116static const unsigned int scif3_clk_b_pins[] = {
2117 /* SCK */
2118 RCAR_GP_PIN(4, 8),
2119};
2120static const unsigned int scif3_clk_b_mux[] = {
2121 SCIF3_SCK_B_MARK,
2122};
2123static const unsigned int scif3_data_c_pins[] = {
2124 /* RX, TX */
2125 RCAR_GP_PIN(6, 7), RCAR_GP_PIN(6, 6),
2126};
2127static const unsigned int scif3_data_c_mux[] = {
2128 RX3_C_MARK, TX3_C_MARK,
2129};
2130static const unsigned int scif3_data_d_pins[] = {
2131 /* RX, TX */
2132 RCAR_GP_PIN(2, 27), RCAR_GP_PIN(2, 26),
2133};
2134static const unsigned int scif3_data_d_mux[] = {
2135 RX3_D_MARK, TX3_D_MARK,
2136};
2137/* - SCIF4 ------------------------------------------------------------------ */
2138static const unsigned int scif4_data_pins[] = {
2139 /* RX, TX */
2140 RCAR_GP_PIN(4, 2), RCAR_GP_PIN(4, 1),
2141};
2142static const unsigned int scif4_data_mux[] = {
2143 RX4_MARK, TX4_MARK,
2144};
2145static const unsigned int scif4_data_b_pins[] = {
2146 /* RX, TX */
2147 RCAR_GP_PIN(5, 1), RCAR_GP_PIN(5, 0),
2148};
2149static const unsigned int scif4_data_b_mux[] = {
2150 RX4_B_MARK, TX4_B_MARK,
2151};
2152static const unsigned int scif4_data_c_pins[] = {
2153 /* RX, TX */
2154 RCAR_GP_PIN(7, 22), RCAR_GP_PIN(7, 21),
2155};
2156static const unsigned int scif4_data_c_mux[] = {
2157 RX4_C_MARK, TX4_C_MARK,
2158};
2159/* - SCIF5 ------------------------------------------------------------------ */
2160static const unsigned int scif5_data_pins[] = {
2161 /* RX, TX */
2162 RCAR_GP_PIN(4, 4), RCAR_GP_PIN(4, 3),
2163};
2164static const unsigned int scif5_data_mux[] = {
2165 RX5_MARK, TX5_MARK,
2166};
2167static const unsigned int scif5_data_b_pins[] = {
2168 /* RX, TX */
2169 RCAR_GP_PIN(6, 23), RCAR_GP_PIN(6, 22),
2170};
2171static const unsigned int scif5_data_b_mux[] = {
2172 RX5_B_MARK, TX5_B_MARK,
2173};
2174/* - SCIFA0 ----------------------------------------------------------------- */
2175static const unsigned int scifa0_data_pins[] = {
2176 /* RXD, TXD */
2177 RCAR_GP_PIN(1, 7), RCAR_GP_PIN(1, 6),
2178};
2179static const unsigned int scifa0_data_mux[] = {
2180 SCIFA0_RXD_MARK, SCIFA0_TXD_MARK,
2181};
2182static const unsigned int scifa0_data_b_pins[] = {
2183 /* RXD, TXD */
2184 RCAR_GP_PIN(3, 1), RCAR_GP_PIN(3, 0),
2185};
2186static const unsigned int scifa0_data_b_mux[] = {
2187 SCIFA0_RXD_B_MARK, SCIFA0_TXD_B_MARK
2188};
2189/* - SCIFA1 ----------------------------------------------------------------- */
2190static const unsigned int scifa1_data_pins[] = {
2191 /* RXD, TXD */
2192 RCAR_GP_PIN(1, 9), RCAR_GP_PIN(1, 8),
2193};
2194static const unsigned int scifa1_data_mux[] = {
2195 SCIFA1_RXD_MARK, SCIFA1_TXD_MARK,
2196};
2197static const unsigned int scifa1_clk_pins[] = {
2198 /* SCK */
2199 RCAR_GP_PIN(3, 10),
2200};
2201static const unsigned int scifa1_clk_mux[] = {
2202 SCIFA1_SCK_MARK,
2203};
2204static const unsigned int scifa1_data_b_pins[] = {
2205 /* RXD, TXD */
2206 RCAR_GP_PIN(3, 9), RCAR_GP_PIN(3, 8),
2207};
2208static const unsigned int scifa1_data_b_mux[] = {
2209 SCIFA1_RXD_B_MARK, SCIFA1_TXD_B_MARK,
2210};
2211static const unsigned int scifa1_clk_b_pins[] = {
2212 /* SCK */
2213 RCAR_GP_PIN(1, 0),
2214};
2215static const unsigned int scifa1_clk_b_mux[] = {
2216 SCIFA1_SCK_B_MARK,
2217};
2218static const unsigned int scifa1_data_c_pins[] = {
2219 /* RXD, TXD */
2220 RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3),
2221};
2222static const unsigned int scifa1_data_c_mux[] = {
2223 SCIFA1_RXD_C_MARK, SCIFA1_TXD_C_MARK,
2224};
2225/* - SCIFA2 ----------------------------------------------------------------- */
2226static const unsigned int scifa2_data_pins[] = {
2227 /* RXD, TXD */
2228 RCAR_GP_PIN(2, 30), RCAR_GP_PIN(2, 31),
2229};
2230static const unsigned int scifa2_data_mux[] = {
2231 SCIFA2_RXD_MARK, SCIFA2_TXD_MARK,
2232};
2233static const unsigned int scifa2_clk_pins[] = {
2234 /* SCK */
2235 RCAR_GP_PIN(3, 18),
2236};
2237static const unsigned int scifa2_clk_mux[] = {
2238 SCIFA2_SCK_MARK,
2239};
2240static const unsigned int scifa2_data_b_pins[] = {
2241 /* RXD, TXD */
2242 RCAR_GP_PIN(3, 17), RCAR_GP_PIN(3, 16),
2243};
2244static const unsigned int scifa2_data_b_mux[] = {
2245 SCIFA2_RXD_B_MARK, SCIFA2_TXD_B_MARK,
2246};
2247/* - SCIFA3 ----------------------------------------------------------------- */
2248static const unsigned int scifa3_data_pins[] = {
2249 /* RXD, TXD */
2250 RCAR_GP_PIN(3, 22), RCAR_GP_PIN(3, 21),
2251};
2252static const unsigned int scifa3_data_mux[] = {
2253 SCIFA3_RXD_MARK, SCIFA3_TXD_MARK,
2254};
2255static const unsigned int scifa3_clk_pins[] = {
2256 /* SCK */
2257 RCAR_GP_PIN(3, 23),
2258};
2259static const unsigned int scifa3_clk_mux[] = {
2260 SCIFA3_SCK_MARK,
2261};
2262static const unsigned int scifa3_data_b_pins[] = {
2263 /* RXD, TXD */
2264 RCAR_GP_PIN(5, 19), RCAR_GP_PIN(5, 20),
2265};
2266static const unsigned int scifa3_data_b_mux[] = {
2267 SCIFA3_RXD_B_MARK, SCIFA3_TXD_B_MARK,
2268};
2269static const unsigned int scifa3_clk_b_pins[] = {
2270 /* SCK */
2271 RCAR_GP_PIN(4, 8),
2272};
2273static const unsigned int scifa3_clk_b_mux[] = {
2274 SCIFA3_SCK_B_MARK,
2275};
2276static const unsigned int scifa3_data_c_pins[] = {
2277 /* RXD, TXD */
2278 RCAR_GP_PIN(7, 21), RCAR_GP_PIN(7, 20),
2279};
2280static const unsigned int scifa3_data_c_mux[] = {
2281 SCIFA3_RXD_C_MARK, SCIFA3_TXD_C_MARK,
2282};
2283static const unsigned int scifa3_clk_c_pins[] = {
2284 /* SCK */
2285 RCAR_GP_PIN(7, 22),
2286};
2287static const unsigned int scifa3_clk_c_mux[] = {
2288 SCIFA3_SCK_C_MARK,
2289};
2290/* - SCIFA4 ----------------------------------------------------------------- */
2291static const unsigned int scifa4_data_pins[] = {
2292 /* RXD, TXD */
2293 RCAR_GP_PIN(4, 2), RCAR_GP_PIN(4, 1),
2294};
2295static const unsigned int scifa4_data_mux[] = {
2296 SCIFA4_RXD_MARK, SCIFA4_TXD_MARK,
2297};
2298static const unsigned int scifa4_data_b_pins[] = {
2299 /* RXD, TXD */
2300 RCAR_GP_PIN(5, 1), RCAR_GP_PIN(5, 0),
2301};
2302static const unsigned int scifa4_data_b_mux[] = {
2303 SCIFA4_RXD_B_MARK, SCIFA4_TXD_B_MARK,
2304};
2305static const unsigned int scifa4_data_c_pins[] = {
2306 /* RXD, TXD */
2307 RCAR_GP_PIN(7, 22), RCAR_GP_PIN(7, 21),
2308};
2309static const unsigned int scifa4_data_c_mux[] = {
2310 SCIFA4_RXD_C_MARK, SCIFA4_TXD_C_MARK,
2311};
2312/* - SCIFA5 ----------------------------------------------------------------- */
2313static const unsigned int scifa5_data_pins[] = {
2314 /* RXD, TXD */
2315 RCAR_GP_PIN(4, 4), RCAR_GP_PIN(4, 3),
2316};
2317static const unsigned int scifa5_data_mux[] = {
2318 SCIFA5_RXD_MARK, SCIFA5_TXD_MARK,
2319};
2320static const unsigned int scifa5_data_b_pins[] = {
2321 /* RXD, TXD */
2322 RCAR_GP_PIN(6, 7), RCAR_GP_PIN(6, 6),
2323};
2324static const unsigned int scifa5_data_b_mux[] = {
2325 SCIFA5_RXD_B_MARK, SCIFA5_TXD_B_MARK,
2326};
2327static const unsigned int scifa5_data_c_pins[] = {
2328 /* RXD, TXD */
2329 RCAR_GP_PIN(6, 23), RCAR_GP_PIN(6, 22),
2330};
2331static const unsigned int scifa5_data_c_mux[] = {
2332 SCIFA5_RXD_C_MARK, SCIFA5_TXD_C_MARK,
2333};
2334/* - SCIFB0 ----------------------------------------------------------------- */
2335static const unsigned int scifb0_data_pins[] = {
2336 /* RXD, TXD */
2337 RCAR_GP_PIN(7, 3), RCAR_GP_PIN(7, 4),
2338};
2339static const unsigned int scifb0_data_mux[] = {
2340 SCIFB0_RXD_MARK, SCIFB0_TXD_MARK,
2341};
2342static const unsigned int scifb0_clk_pins[] = {
2343 /* SCK */
2344 RCAR_GP_PIN(7, 2),
2345};
2346static const unsigned int scifb0_clk_mux[] = {
2347 SCIFB0_SCK_MARK,
2348};
2349static const unsigned int scifb0_ctrl_pins[] = {
2350 /* RTS, CTS */
2351 RCAR_GP_PIN(7, 1), RCAR_GP_PIN(7, 0),
2352};
2353static const unsigned int scifb0_ctrl_mux[] = {
2354 SCIFB0_RTS_N_MARK, SCIFB0_CTS_N_MARK,
2355};
2356static const unsigned int scifb0_data_b_pins[] = {
2357 /* RXD, TXD */
2358 RCAR_GP_PIN(1, 20), RCAR_GP_PIN(1, 21),
2359};
2360static const unsigned int scifb0_data_b_mux[] = {
2361 SCIFB0_RXD_B_MARK, SCIFB0_TXD_B_MARK,
2362};
2363static const unsigned int scifb0_clk_b_pins[] = {
2364 /* SCK */
2365 RCAR_GP_PIN(5, 31),
2366};
2367static const unsigned int scifb0_clk_b_mux[] = {
2368 SCIFB0_SCK_B_MARK,
2369};
2370static const unsigned int scifb0_ctrl_b_pins[] = {
2371 /* RTS, CTS */
2372 RCAR_GP_PIN(1, 22), RCAR_GP_PIN(1, 23),
2373};
2374static const unsigned int scifb0_ctrl_b_mux[] = {
2375 SCIFB0_RTS_N_B_MARK, SCIFB0_CTS_N_B_MARK,
2376};
2377static const unsigned int scifb0_data_c_pins[] = {
2378 /* RXD, TXD */
2379 RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 1),
2380};
2381static const unsigned int scifb0_data_c_mux[] = {
2382 SCIFB0_RXD_C_MARK, SCIFB0_TXD_C_MARK,
2383};
2384static const unsigned int scifb0_clk_c_pins[] = {
2385 /* SCK */
2386 RCAR_GP_PIN(2, 30),
2387};
2388static const unsigned int scifb0_clk_c_mux[] = {
2389 SCIFB0_SCK_C_MARK,
2390};
2391static const unsigned int scifb0_data_d_pins[] = {
2392 /* RXD, TXD */
2393 RCAR_GP_PIN(4, 28), RCAR_GP_PIN(4, 18),
2394};
2395static const unsigned int scifb0_data_d_mux[] = {
2396 SCIFB0_RXD_D_MARK, SCIFB0_TXD_D_MARK,
2397};
2398static const unsigned int scifb0_clk_d_pins[] = {
2399 /* SCK */
2400 RCAR_GP_PIN(4, 17),
2401};
2402static const unsigned int scifb0_clk_d_mux[] = {
2403 SCIFB0_SCK_D_MARK,
2404};
2405/* - SCIFB1 ----------------------------------------------------------------- */
2406static const unsigned int scifb1_data_pins[] = {
2407 /* RXD, TXD */
2408 RCAR_GP_PIN(7, 5), RCAR_GP_PIN(7, 6),
2409};
2410static const unsigned int scifb1_data_mux[] = {
2411 SCIFB1_RXD_MARK, SCIFB1_TXD_MARK,
2412};
2413static const unsigned int scifb1_clk_pins[] = {
2414 /* SCK */
2415 RCAR_GP_PIN(7, 7),
2416};
2417static const unsigned int scifb1_clk_mux[] = {
2418 SCIFB1_SCK_MARK,
2419};
2420static const unsigned int scifb1_ctrl_pins[] = {
2421 /* RTS, CTS */
2422 RCAR_GP_PIN(7, 9), RCAR_GP_PIN(7, 8),
2423};
2424static const unsigned int scifb1_ctrl_mux[] = {
2425 SCIFB1_RTS_N_MARK, SCIFB1_CTS_N_MARK,
2426};
2427static const unsigned int scifb1_data_b_pins[] = {
2428 /* RXD, TXD */
2429 RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 18),
2430};
2431static const unsigned int scifb1_data_b_mux[] = {
2432 SCIFB1_RXD_B_MARK, SCIFB1_TXD_B_MARK,
2433};
2434static const unsigned int scifb1_clk_b_pins[] = {
2435 /* SCK */
2436 RCAR_GP_PIN(1, 3),
2437};
2438static const unsigned int scifb1_clk_b_mux[] = {
2439 SCIFB1_SCK_B_MARK,
2440};
2441static const unsigned int scifb1_data_c_pins[] = {
2442 /* RXD, TXD */
2443 RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3),
2444};
2445static const unsigned int scifb1_data_c_mux[] = {
2446 SCIFB1_RXD_C_MARK, SCIFB1_TXD_C_MARK,
2447};
2448static const unsigned int scifb1_clk_c_pins[] = {
2449 /* SCK */
2450 RCAR_GP_PIN(7, 11),
2451};
2452static const unsigned int scifb1_clk_c_mux[] = {
2453 SCIFB1_SCK_C_MARK,
2454};
2455static const unsigned int scifb1_data_d_pins[] = {
2456 /* RXD, TXD */
2457 RCAR_GP_PIN(7, 10), RCAR_GP_PIN(7, 12),
2458};
2459static const unsigned int scifb1_data_d_mux[] = {
2460 SCIFB1_RXD_D_MARK, SCIFB1_TXD_D_MARK,
2461};
2462/* - SCIFB2 ----------------------------------------------------------------- */
2463static const unsigned int scifb2_data_pins[] = {
2464 /* RXD, TXD */
2465 RCAR_GP_PIN(4, 16), RCAR_GP_PIN(4, 17),
2466};
2467static const unsigned int scifb2_data_mux[] = {
2468 SCIFB2_RXD_MARK, SCIFB2_TXD_MARK,
2469};
2470static const unsigned int scifb2_clk_pins[] = {
2471 /* SCK */
2472 RCAR_GP_PIN(4, 15),
2473};
2474static const unsigned int scifb2_clk_mux[] = {
2475 SCIFB2_SCK_MARK,
2476};
2477static const unsigned int scifb2_ctrl_pins[] = {
2478 /* RTS, CTS */
2479 RCAR_GP_PIN(4, 14), RCAR_GP_PIN(4, 13),
2480};
2481static const unsigned int scifb2_ctrl_mux[] = {
2482 SCIFB2_RTS_N_MARK, SCIFB2_CTS_N_MARK,
2483};
2484static const unsigned int scifb2_data_b_pins[] = {
2485 /* RXD, TXD */
2486 RCAR_GP_PIN(3, 12), RCAR_GP_PIN(3, 13),
2487};
2488static const unsigned int scifb2_data_b_mux[] = {
2489 SCIFB2_RXD_B_MARK, SCIFB2_TXD_B_MARK,
2490};
2491static const unsigned int scifb2_clk_b_pins[] = {
2492 /* SCK */
2493 RCAR_GP_PIN(5, 31),
2494};
2495static const unsigned int scifb2_clk_b_mux[] = {
2496 SCIFB2_SCK_B_MARK,
2497};
2498static const unsigned int scifb2_ctrl_b_pins[] = {
2499 /* RTS, CTS */
2500 RCAR_GP_PIN(3, 15), RCAR_GP_PIN(3, 14),
2501};
2502static const unsigned int scifb2_ctrl_b_mux[] = {
2503 SCIFB2_RTS_N_B_MARK, SCIFB2_CTS_N_B_MARK,
2504};
2505static const unsigned int scifb2_data_c_pins[] = {
2506 /* RXD, TXD */
2507 RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 1),
2508};
2509static const unsigned int scifb2_data_c_mux[] = {
2510 SCIFB2_RXD_C_MARK, SCIFB2_TXD_C_MARK,
2511};
2512static const unsigned int scifb2_clk_c_pins[] = {
2513 /* SCK */
2514 RCAR_GP_PIN(5, 27),
2515};
2516static const unsigned int scifb2_clk_c_mux[] = {
2517 SCIFB2_SCK_C_MARK,
2518};
2519static const unsigned int scifb2_data_d_pins[] = {
2520 /* RXD, TXD */
2521 RCAR_GP_PIN(5, 26), RCAR_GP_PIN(5, 25),
2522};
2523static const unsigned int scifb2_data_d_mux[] = {
2524 SCIFB2_RXD_D_MARK, SCIFB2_TXD_D_MARK,
2525};
2526/* - SDHI0 ------------------------------------------------------------------ */
2527static const unsigned int sdhi0_data1_pins[] = {
2528 /* D0 */
2529 RCAR_GP_PIN(6, 2),
2530};
2531static const unsigned int sdhi0_data1_mux[] = {
2532 SD0_DATA0_MARK,
2533};
2534static const unsigned int sdhi0_data4_pins[] = {
2535 /* D[0:3] */
2536 RCAR_GP_PIN(6, 2), RCAR_GP_PIN(6, 3),
2537 RCAR_GP_PIN(6, 4), RCAR_GP_PIN(6, 5),
2538};
2539static const unsigned int sdhi0_data4_mux[] = {
2540 SD0_DATA0_MARK, SD0_DATA1_MARK, SD0_DATA2_MARK, SD0_DATA3_MARK,
2541};
2542static const unsigned int sdhi0_ctrl_pins[] = {
2543 /* CLK, CMD */
2544 RCAR_GP_PIN(6, 0), RCAR_GP_PIN(6, 1),
2545};
2546static const unsigned int sdhi0_ctrl_mux[] = {
2547 SD0_CLK_MARK, SD0_CMD_MARK,
2548};
2549static const unsigned int sdhi0_cd_pins[] = {
2550 /* CD */
2551 RCAR_GP_PIN(6, 6),
2552};
2553static const unsigned int sdhi0_cd_mux[] = {
2554 SD0_CD_MARK,
2555};
2556static const unsigned int sdhi0_wp_pins[] = {
2557 /* WP */
2558 RCAR_GP_PIN(6, 7),
2559};
2560static const unsigned int sdhi0_wp_mux[] = {
2561 SD0_WP_MARK,
2562};
2563/* - SDHI1 ------------------------------------------------------------------ */
2564static const unsigned int sdhi1_data1_pins[] = {
2565 /* D0 */
2566 RCAR_GP_PIN(6, 10),
2567};
2568static const unsigned int sdhi1_data1_mux[] = {
2569 SD1_DATA0_MARK,
2570};
2571static const unsigned int sdhi1_data4_pins[] = {
2572 /* D[0:3] */
2573 RCAR_GP_PIN(6, 10), RCAR_GP_PIN(6, 11),
2574 RCAR_GP_PIN(6, 12), RCAR_GP_PIN(6, 13),
2575};
2576static const unsigned int sdhi1_data4_mux[] = {
2577 SD1_DATA0_MARK, SD1_DATA1_MARK, SD1_DATA2_MARK, SD1_DATA3_MARK,
2578};
2579static const unsigned int sdhi1_ctrl_pins[] = {
2580 /* CLK, CMD */
2581 RCAR_GP_PIN(6, 8), RCAR_GP_PIN(6, 9),
2582};
2583static const unsigned int sdhi1_ctrl_mux[] = {
2584 SD1_CLK_MARK, SD1_CMD_MARK,
2585};
2586static const unsigned int sdhi1_cd_pins[] = {
2587 /* CD */
2588 RCAR_GP_PIN(6, 14),
2589};
2590static const unsigned int sdhi1_cd_mux[] = {
2591 SD1_CD_MARK,
2592};
2593static const unsigned int sdhi1_wp_pins[] = {
2594 /* WP */
2595 RCAR_GP_PIN(6, 15),
2596};
2597static const unsigned int sdhi1_wp_mux[] = {
2598 SD1_WP_MARK,
2599};
2600/* - SDHI2 ------------------------------------------------------------------ */
2601static const unsigned int sdhi2_data1_pins[] = {
2602 /* D0 */
2603 RCAR_GP_PIN(6, 18),
2604};
2605static const unsigned int sdhi2_data1_mux[] = {
2606 SD2_DATA0_MARK,
2607};
2608static const unsigned int sdhi2_data4_pins[] = {
2609 /* D[0:3] */
2610 RCAR_GP_PIN(6, 18), RCAR_GP_PIN(6, 19),
2611 RCAR_GP_PIN(6, 20), RCAR_GP_PIN(6, 21),
2612};
2613static const unsigned int sdhi2_data4_mux[] = {
2614 SD2_DATA0_MARK, SD2_DATA1_MARK, SD2_DATA2_MARK, SD2_DATA3_MARK,
2615};
2616static const unsigned int sdhi2_ctrl_pins[] = {
2617 /* CLK, CMD */
2618 RCAR_GP_PIN(6, 16), RCAR_GP_PIN(6, 17),
2619};
2620static const unsigned int sdhi2_ctrl_mux[] = {
2621 SD2_CLK_MARK, SD2_CMD_MARK,
2622};
2623static const unsigned int sdhi2_cd_pins[] = {
2624 /* CD */
2625 RCAR_GP_PIN(6, 22),
2626};
2627static const unsigned int sdhi2_cd_mux[] = {
2628 SD2_CD_MARK,
2629};
2630static const unsigned int sdhi2_wp_pins[] = {
2631 /* WP */
2632 RCAR_GP_PIN(6, 23),
2633};
2634static const unsigned int sdhi2_wp_mux[] = {
2635 SD2_WP_MARK,
2636};
2637/* - USB0 ------------------------------------------------------------------- */
2638static const unsigned int usb0_pwen_pins[] = {
2639 /* PWEN */
2640 RCAR_GP_PIN(7, 23),
2641};
2642static const unsigned int usb0_pwen_mux[] = {
2643 USB0_PWEN_MARK,
2644};
2645static const unsigned int usb0_ovc_pins[] = {
2646 /* OVC */
2647 RCAR_GP_PIN(7, 24),
2648};
2649static const unsigned int usb0_ovc_mux[] = {
2650 USB0_OVC_MARK,
2651};
2652/* - USB1 ------------------------------------------------------------------- */
2653static const unsigned int usb1_pwen_pins[] = {
2654 /* PWEN */
2655 RCAR_GP_PIN(7, 25),
2656};
2657static const unsigned int usb1_pwen_mux[] = {
2658 USB1_PWEN_MARK,
2659};
2660static const unsigned int usb1_ovc_pins[] = {
2661 /* OVC */
2662 RCAR_GP_PIN(6, 30),
2663};
2664static const unsigned int usb1_ovc_mux[] = {
2665 USB1_OVC_MARK,
2666};
2667
2668static const struct sh_pfc_pin_group pinmux_groups[] = {
2669 SH_PFC_PIN_GROUP(du_rgb666),
2670 SH_PFC_PIN_GROUP(du_rgb888),
2671 SH_PFC_PIN_GROUP(du_clk_out_0),
2672 SH_PFC_PIN_GROUP(du_clk_out_1),
2673 SH_PFC_PIN_GROUP(du_sync_1),
2674 SH_PFC_PIN_GROUP(du_cde_disp),
2675 SH_PFC_PIN_GROUP(du0_clk_in),
2676 SH_PFC_PIN_GROUP(du1_clk_in),
2677 SH_PFC_PIN_GROUP(eth_link),
2678 SH_PFC_PIN_GROUP(eth_magic),
2679 SH_PFC_PIN_GROUP(eth_mdio),
2680 SH_PFC_PIN_GROUP(eth_rmii),
2681 SH_PFC_PIN_GROUP(intc_irq0),
2682 SH_PFC_PIN_GROUP(intc_irq1),
2683 SH_PFC_PIN_GROUP(intc_irq2),
2684 SH_PFC_PIN_GROUP(intc_irq3),
2685 SH_PFC_PIN_GROUP(mmc_data1),
2686 SH_PFC_PIN_GROUP(mmc_data4),
2687 SH_PFC_PIN_GROUP(mmc_data8),
2688 SH_PFC_PIN_GROUP(mmc_ctrl),
2689 SH_PFC_PIN_GROUP(msiof0_clk),
2690 SH_PFC_PIN_GROUP(msiof0_sync),
2691 SH_PFC_PIN_GROUP(msiof0_ss1),
2692 SH_PFC_PIN_GROUP(msiof0_ss2),
2693 SH_PFC_PIN_GROUP(msiof0_rx),
2694 SH_PFC_PIN_GROUP(msiof0_tx),
2695 SH_PFC_PIN_GROUP(msiof1_clk),
2696 SH_PFC_PIN_GROUP(msiof1_sync),
2697 SH_PFC_PIN_GROUP(msiof1_ss1),
2698 SH_PFC_PIN_GROUP(msiof1_ss2),
2699 SH_PFC_PIN_GROUP(msiof1_rx),
2700 SH_PFC_PIN_GROUP(msiof1_tx),
2701 SH_PFC_PIN_GROUP(msiof2_clk),
2702 SH_PFC_PIN_GROUP(msiof2_sync),
2703 SH_PFC_PIN_GROUP(msiof2_ss1),
2704 SH_PFC_PIN_GROUP(msiof2_ss2),
2705 SH_PFC_PIN_GROUP(msiof2_rx),
2706 SH_PFC_PIN_GROUP(msiof2_tx),
2707 SH_PFC_PIN_GROUP(scif0_data),
2708 SH_PFC_PIN_GROUP(scif0_data_b),
2709 SH_PFC_PIN_GROUP(scif0_data_c),
2710 SH_PFC_PIN_GROUP(scif0_data_d),
2711 SH_PFC_PIN_GROUP(scif0_data_e),
2712 SH_PFC_PIN_GROUP(scif1_data),
2713 SH_PFC_PIN_GROUP(scif1_data_b),
2714 SH_PFC_PIN_GROUP(scif1_clk_b),
2715 SH_PFC_PIN_GROUP(scif1_data_c),
2716 SH_PFC_PIN_GROUP(scif1_data_d),
2717 SH_PFC_PIN_GROUP(scif2_data),
2718 SH_PFC_PIN_GROUP(scif2_data_b),
2719 SH_PFC_PIN_GROUP(scif2_clk_b),
2720 SH_PFC_PIN_GROUP(scif2_data_c),
2721 SH_PFC_PIN_GROUP(scif2_data_e),
2722 SH_PFC_PIN_GROUP(scif3_data),
2723 SH_PFC_PIN_GROUP(scif3_clk),
2724 SH_PFC_PIN_GROUP(scif3_data_b),
2725 SH_PFC_PIN_GROUP(scif3_clk_b),
2726 SH_PFC_PIN_GROUP(scif3_data_c),
2727 SH_PFC_PIN_GROUP(scif3_data_d),
2728 SH_PFC_PIN_GROUP(scif4_data),
2729 SH_PFC_PIN_GROUP(scif4_data_b),
2730 SH_PFC_PIN_GROUP(scif4_data_c),
2731 SH_PFC_PIN_GROUP(scif5_data),
2732 SH_PFC_PIN_GROUP(scif5_data_b),
2733 SH_PFC_PIN_GROUP(scifa0_data),
2734 SH_PFC_PIN_GROUP(scifa0_data_b),
2735 SH_PFC_PIN_GROUP(scifa1_data),
2736 SH_PFC_PIN_GROUP(scifa1_clk),
2737 SH_PFC_PIN_GROUP(scifa1_data_b),
2738 SH_PFC_PIN_GROUP(scifa1_clk_b),
2739 SH_PFC_PIN_GROUP(scifa1_data_c),
2740 SH_PFC_PIN_GROUP(scifa2_data),
2741 SH_PFC_PIN_GROUP(scifa2_clk),
2742 SH_PFC_PIN_GROUP(scifa2_data_b),
2743 SH_PFC_PIN_GROUP(scifa3_data),
2744 SH_PFC_PIN_GROUP(scifa3_clk),
2745 SH_PFC_PIN_GROUP(scifa3_data_b),
2746 SH_PFC_PIN_GROUP(scifa3_clk_b),
2747 SH_PFC_PIN_GROUP(scifa3_data_c),
2748 SH_PFC_PIN_GROUP(scifa3_clk_c),
2749 SH_PFC_PIN_GROUP(scifa4_data),
2750 SH_PFC_PIN_GROUP(scifa4_data_b),
2751 SH_PFC_PIN_GROUP(scifa4_data_c),
2752 SH_PFC_PIN_GROUP(scifa5_data),
2753 SH_PFC_PIN_GROUP(scifa5_data_b),
2754 SH_PFC_PIN_GROUP(scifa5_data_c),
2755 SH_PFC_PIN_GROUP(scifb0_data),
2756 SH_PFC_PIN_GROUP(scifb0_clk),
2757 SH_PFC_PIN_GROUP(scifb0_ctrl),
2758 SH_PFC_PIN_GROUP(scifb0_data_b),
2759 SH_PFC_PIN_GROUP(scifb0_clk_b),
2760 SH_PFC_PIN_GROUP(scifb0_ctrl_b),
2761 SH_PFC_PIN_GROUP(scifb0_data_c),
2762 SH_PFC_PIN_GROUP(scifb0_clk_c),
2763 SH_PFC_PIN_GROUP(scifb0_data_d),
2764 SH_PFC_PIN_GROUP(scifb0_clk_d),
2765 SH_PFC_PIN_GROUP(scifb1_data),
2766 SH_PFC_PIN_GROUP(scifb1_clk),
2767 SH_PFC_PIN_GROUP(scifb1_ctrl),
2768 SH_PFC_PIN_GROUP(scifb1_data_b),
2769 SH_PFC_PIN_GROUP(scifb1_clk_b),
2770 SH_PFC_PIN_GROUP(scifb1_data_c),
2771 SH_PFC_PIN_GROUP(scifb1_clk_c),
2772 SH_PFC_PIN_GROUP(scifb1_data_d),
2773 SH_PFC_PIN_GROUP(scifb2_data),
2774 SH_PFC_PIN_GROUP(scifb2_clk),
2775 SH_PFC_PIN_GROUP(scifb2_ctrl),
2776 SH_PFC_PIN_GROUP(scifb2_data_b),
2777 SH_PFC_PIN_GROUP(scifb2_clk_b),
2778 SH_PFC_PIN_GROUP(scifb2_ctrl_b),
2779 SH_PFC_PIN_GROUP(scifb2_data_c),
2780 SH_PFC_PIN_GROUP(scifb2_clk_c),
2781 SH_PFC_PIN_GROUP(scifb2_data_d),
2782 SH_PFC_PIN_GROUP(sdhi0_data1),
2783 SH_PFC_PIN_GROUP(sdhi0_data4),
2784 SH_PFC_PIN_GROUP(sdhi0_ctrl),
2785 SH_PFC_PIN_GROUP(sdhi0_cd),
2786 SH_PFC_PIN_GROUP(sdhi0_wp),
2787 SH_PFC_PIN_GROUP(sdhi1_data1),
2788 SH_PFC_PIN_GROUP(sdhi1_data4),
2789 SH_PFC_PIN_GROUP(sdhi1_ctrl),
2790 SH_PFC_PIN_GROUP(sdhi1_cd),
2791 SH_PFC_PIN_GROUP(sdhi1_wp),
2792 SH_PFC_PIN_GROUP(sdhi2_data1),
2793 SH_PFC_PIN_GROUP(sdhi2_data4),
2794 SH_PFC_PIN_GROUP(sdhi2_ctrl),
2795 SH_PFC_PIN_GROUP(sdhi2_cd),
2796 SH_PFC_PIN_GROUP(sdhi2_wp),
2797 SH_PFC_PIN_GROUP(usb0_pwen),
2798 SH_PFC_PIN_GROUP(usb0_ovc),
2799 SH_PFC_PIN_GROUP(usb1_pwen),
2800 SH_PFC_PIN_GROUP(usb1_ovc),
2801};
2802
2803static const char * const du_groups[] = {
2804 "du_rgb666",
2805 "du_rgb888",
2806 "du_clk_out_0",
2807 "du_clk_out_1",
2808 "du_sync_1",
2809 "du_cde_disp",
2810};
2811
2812static const char * const du0_groups[] = {
2813 "du0_clk_in",
2814};
2815
2816static const char * const du1_groups[] = {
2817 "du1_clk_in",
2818};
2819
2820static const char * const eth_groups[] = {
2821 "eth_link",
2822 "eth_magic",
2823 "eth_mdio",
2824 "eth_rmii",
2825};
2826
2827static const char * const intc_groups[] = {
2828 "intc_irq0",
2829 "intc_irq1",
2830 "intc_irq2",
2831 "intc_irq3",
2832};
2833
2834static const char * const mmc_groups[] = {
2835 "mmc_data1",
2836 "mmc_data4",
2837 "mmc_data8",
2838 "mmc_ctrl",
2839};
2840
2841static const char * const msiof0_groups[] = {
2842 "msiof0_clk",
2843 "msiof0_ctrl",
2844 "msiof0_data",
2845};
2846
2847static const char * const msiof1_groups[] = {
2848 "msiof1_clk",
2849 "msiof1_ctrl",
2850 "msiof1_data",
2851};
2852
2853static const char * const msiof2_groups[] = {
2854 "msiof2_clk",
2855 "msiof2_ctrl",
2856 "msiof2_data",
2857};
2858
2859static const char * const scif0_groups[] = {
2860 "scif0_data",
2861 "scif0_data_b",
2862 "scif0_data_c",
2863 "scif0_data_d",
2864 "scif0_data_e",
2865};
2866
2867static const char * const scif1_groups[] = {
2868 "scif1_data",
2869 "scif1_data_b",
2870 "scif1_clk_b",
2871 "scif1_data_c",
2872 "scif1_data_d",
2873};
2874
2875static const char * const scif2_groups[] = {
2876 "scif2_data",
2877 "scif2_data_b",
2878 "scif2_clk_b",
2879 "scif2_data_c",
2880 "scif2_data_e",
2881};
2882static const char * const scif3_groups[] = {
2883 "scif3_data",
2884 "scif3_clk",
2885 "scif3_data_b",
2886 "scif3_clk_b",
2887 "scif3_data_c",
2888 "scif3_data_d",
2889};
2890static const char * const scif4_groups[] = {
2891 "scif4_data",
2892 "scif4_data_b",
2893 "scif4_data_c",
2894};
2895static const char * const scif5_groups[] = {
2896 "scif5_data",
2897 "scif5_data_b",
2898};
2899static const char * const scifa0_groups[] = {
2900 "scifa0_data",
2901 "scifa0_data_b",
2902};
2903static const char * const scifa1_groups[] = {
2904 "scifa1_data",
2905 "scifa1_clk",
2906 "scifa1_data_b",
2907 "scifa1_clk_b",
2908 "scifa1_data_c",
2909};
2910static const char * const scifa2_groups[] = {
2911 "scifa2_data",
2912 "scifa2_clk",
2913 "scifa2_data_b",
2914};
2915static const char * const scifa3_groups[] = {
2916 "scifa3_data",
2917 "scifa3_clk",
2918 "scifa3_data_b",
2919 "scifa3_clk_b",
2920 "scifa3_data_c",
2921 "scifa3_clk_c",
2922};
2923static const char * const scifa4_groups[] = {
2924 "scifa4_data",
2925 "scifa4_data_b",
2926 "scifa4_data_c",
2927};
2928static const char * const scifa5_groups[] = {
2929 "scifa5_data",
2930 "scifa5_data_b",
2931 "scifa5_data_c",
2932};
2933static const char * const scifb0_groups[] = {
2934 "scifb0_data",
2935 "scifb0_clk",
2936 "scifb0_ctrl",
2937 "scifb0_data_b",
2938 "scifb0_clk_b",
2939 "scifb0_ctrl_b",
2940 "scifb0_data_c",
2941 "scifb0_clk_c",
2942 "scifb0_data_d",
2943 "scifb0_clk_d",
2944};
2945static const char * const scifb1_groups[] = {
2946 "scifb1_data",
2947 "scifb1_clk",
2948 "scifb1_ctrl",
2949 "scifb1_data_b",
2950 "scifb1_clk_b",
2951 "scifb1_data_c",
2952 "scifb1_clk_c",
2953 "scifb1_data_d",
2954};
2955static const char * const scifb2_groups[] = {
2956 "scifb2_data",
2957 "scifb2_clk",
2958 "scifb2_ctrl",
2959 "scifb2_data_b",
2960 "scifb2_clk_b",
2961 "scifb2_ctrl_b",
2962 "scifb0_data_c",
2963 "scifb2_clk_c",
2964 "scifb2_data_d",
2965};
2966
2967static const char * const sdhi0_groups[] = {
2968 "sdhi0_data1",
2969 "sdhi0_data4",
2970 "sdhi0_ctrl",
2971 "sdhi0_cd",
2972 "sdhi0_wp",
2973};
2974
2975static const char * const sdhi1_groups[] = {
2976 "sdhi1_data1",
2977 "sdhi1_data4",
2978 "sdhi1_ctrl",
2979 "sdhi1_cd",
2980 "sdhi1_wp",
2981};
2982
2983static const char * const sdhi2_groups[] = {
2984 "sdhi2_data1",
2985 "sdhi2_data4",
2986 "sdhi2_ctrl",
2987 "sdhi2_cd",
2988 "sdhi2_wp",
2989};
2990
2991static const char * const usb0_groups[] = {
2992 "usb0_pwen",
2993 "usb0_ovc",
2994};
2995static const char * const usb1_groups[] = {
2996 "usb1_pwen",
2997 "usb1_ovc",
2998};
2999
3000static const struct sh_pfc_function pinmux_functions[] = {
3001 SH_PFC_FUNCTION(du),
3002 SH_PFC_FUNCTION(du0),
3003 SH_PFC_FUNCTION(du1),
3004 SH_PFC_FUNCTION(eth),
3005 SH_PFC_FUNCTION(intc),
3006 SH_PFC_FUNCTION(mmc),
3007 SH_PFC_FUNCTION(msiof0),
3008 SH_PFC_FUNCTION(msiof1),
3009 SH_PFC_FUNCTION(msiof2),
3010 SH_PFC_FUNCTION(scif0),
3011 SH_PFC_FUNCTION(scif1),
3012 SH_PFC_FUNCTION(scif2),
3013 SH_PFC_FUNCTION(scif3),
3014 SH_PFC_FUNCTION(scif4),
3015 SH_PFC_FUNCTION(scif5),
3016 SH_PFC_FUNCTION(scifa0),
3017 SH_PFC_FUNCTION(scifa1),
3018 SH_PFC_FUNCTION(scifa2),
3019 SH_PFC_FUNCTION(scifa3),
3020 SH_PFC_FUNCTION(scifa4),
3021 SH_PFC_FUNCTION(scifa5),
3022 SH_PFC_FUNCTION(scifb0),
3023 SH_PFC_FUNCTION(scifb1),
3024 SH_PFC_FUNCTION(scifb2),
3025 SH_PFC_FUNCTION(sdhi0),
3026 SH_PFC_FUNCTION(sdhi1),
3027 SH_PFC_FUNCTION(sdhi2),
3028 SH_PFC_FUNCTION(usb0),
3029 SH_PFC_FUNCTION(usb1),
3030};
3031
3032static struct pinmux_cfg_reg pinmux_config_regs[] = {
3033 { PINMUX_CFG_REG("GPSR0", 0xE6060004, 32, 1) {
3034 GP_0_31_FN, FN_IP1_22_20,
3035 GP_0_30_FN, FN_IP1_19_17,
3036 GP_0_29_FN, FN_IP1_16_14,
3037 GP_0_28_FN, FN_IP1_13_11,
3038 GP_0_27_FN, FN_IP1_10_8,
3039 GP_0_26_FN, FN_IP1_7_6,
3040 GP_0_25_FN, FN_IP1_5_4,
3041 GP_0_24_FN, FN_IP1_3_2,
3042 GP_0_23_FN, FN_IP1_1_0,
3043 GP_0_22_FN, FN_IP0_30_29,
3044 GP_0_21_FN, FN_IP0_28_27,
3045 GP_0_20_FN, FN_IP0_26_25,
3046 GP_0_19_FN, FN_IP0_24_23,
3047 GP_0_18_FN, FN_IP0_22_21,
3048 GP_0_17_FN, FN_IP0_20_19,
3049 GP_0_16_FN, FN_IP0_18_16,
3050 GP_0_15_FN, FN_IP0_15,
3051 GP_0_14_FN, FN_IP0_14,
3052 GP_0_13_FN, FN_IP0_13,
3053 GP_0_12_FN, FN_IP0_12,
3054 GP_0_11_FN, FN_IP0_11,
3055 GP_0_10_FN, FN_IP0_10,
3056 GP_0_9_FN, FN_IP0_9,
3057 GP_0_8_FN, FN_IP0_8,
3058 GP_0_7_FN, FN_IP0_7,
3059 GP_0_6_FN, FN_IP0_6,
3060 GP_0_5_FN, FN_IP0_5,
3061 GP_0_4_FN, FN_IP0_4,
3062 GP_0_3_FN, FN_IP0_3,
3063 GP_0_2_FN, FN_IP0_2,
3064 GP_0_1_FN, FN_IP0_1,
3065 GP_0_0_FN, FN_IP0_0, }
3066 },
3067 { PINMUX_CFG_REG("GPSR1", 0xE6060008, 32, 1) {
3068 0, 0,
3069 0, 0,
3070 0, 0,
3071 0, 0,
3072 0, 0,
3073 0, 0,
3074 GP_1_25_FN, FN_IP3_21_20,
3075 GP_1_24_FN, FN_IP3_19_18,
3076 GP_1_23_FN, FN_IP3_17_16,
3077 GP_1_22_FN, FN_IP3_15_14,
3078 GP_1_21_FN, FN_IP3_13_12,
3079 GP_1_20_FN, FN_IP3_11_9,
3080 GP_1_19_FN, FN_RD_N,
3081 GP_1_18_FN, FN_IP3_8_6,
3082 GP_1_17_FN, FN_IP3_5_3,
3083 GP_1_16_FN, FN_IP3_2_0,
3084 GP_1_15_FN, FN_IP2_29_27,
3085 GP_1_14_FN, FN_IP2_26_25,
3086 GP_1_13_FN, FN_IP2_24_23,
3087 GP_1_12_FN, FN_EX_CS0_N,
3088 GP_1_11_FN, FN_IP2_22_21,
3089 GP_1_10_FN, FN_IP2_20_19,
3090 GP_1_9_FN, FN_IP2_18_16,
3091 GP_1_8_FN, FN_IP2_15_13,
3092 GP_1_7_FN, FN_IP2_12_10,
3093 GP_1_6_FN, FN_IP2_9_7,
3094 GP_1_5_FN, FN_IP2_6_5,
3095 GP_1_4_FN, FN_IP2_4_3,
3096 GP_1_3_FN, FN_IP2_2_0,
3097 GP_1_2_FN, FN_IP1_31_29,
3098 GP_1_1_FN, FN_IP1_28_26,
3099 GP_1_0_FN, FN_IP1_25_23, }
3100 },
3101 { PINMUX_CFG_REG("GPSR2", 0xE606000C, 32, 1) {
3102 GP_2_31_FN, FN_IP6_7_6,
3103 GP_2_30_FN, FN_IP6_5_3,
3104 GP_2_29_FN, FN_IP6_2_0,
3105 GP_2_28_FN, FN_AUDIO_CLKA,
3106 GP_2_27_FN, FN_IP5_31_29,
3107 GP_2_26_FN, FN_IP5_28_26,
3108 GP_2_25_FN, FN_IP5_25_24,
3109 GP_2_24_FN, FN_IP5_23_22,
3110 GP_2_23_FN, FN_IP5_21_20,
3111 GP_2_22_FN, FN_IP5_19_17,
3112 GP_2_21_FN, FN_IP5_16_15,
3113 GP_2_20_FN, FN_IP5_14_12,
3114 GP_2_19_FN, FN_IP5_11_9,
3115 GP_2_18_FN, FN_IP5_8_6,
3116 GP_2_17_FN, FN_IP5_5_3,
3117 GP_2_16_FN, FN_IP5_2_0,
3118 GP_2_15_FN, FN_IP4_30_28,
3119 GP_2_14_FN, FN_IP4_27_26,
3120 GP_2_13_FN, FN_IP4_25_24,
3121 GP_2_12_FN, FN_IP4_23_22,
3122 GP_2_11_FN, FN_IP4_21,
3123 GP_2_10_FN, FN_IP4_20,
3124 GP_2_9_FN, FN_IP4_19,
3125 GP_2_8_FN, FN_IP4_18_16,
3126 GP_2_7_FN, FN_IP4_15_13,
3127 GP_2_6_FN, FN_IP4_12_10,
3128 GP_2_5_FN, FN_IP4_9_8,
3129 GP_2_4_FN, FN_IP4_7_5,
3130 GP_2_3_FN, FN_IP4_4_2,
3131 GP_2_2_FN, FN_IP4_1_0,
3132 GP_2_1_FN, FN_IP3_30_28,
3133 GP_2_0_FN, FN_IP3_27_25 }
3134 },
3135 { PINMUX_CFG_REG("GPSR3", 0xE6060010, 32, 1) {
3136 GP_3_31_FN, FN_IP9_18_17,
3137 GP_3_30_FN, FN_IP9_16,
3138 GP_3_29_FN, FN_IP9_15_13,
3139 GP_3_28_FN, FN_IP9_12,
3140 GP_3_27_FN, FN_IP9_11,
3141 GP_3_26_FN, FN_IP9_10_8,
3142 GP_3_25_FN, FN_IP9_7,
3143 GP_3_24_FN, FN_IP9_6,
3144 GP_3_23_FN, FN_IP9_5_3,
3145 GP_3_22_FN, FN_IP9_2_0,
3146 GP_3_21_FN, FN_IP8_30_28,
3147 GP_3_20_FN, FN_IP8_27_26,
3148 GP_3_19_FN, FN_IP8_25_24,
3149 GP_3_18_FN, FN_IP8_23_21,
3150 GP_3_17_FN, FN_IP8_20_18,
3151 GP_3_16_FN, FN_IP8_17_15,
3152 GP_3_15_FN, FN_IP8_14_12,
3153 GP_3_14_FN, FN_IP8_11_9,
3154 GP_3_13_FN, FN_IP8_8_6,
3155 GP_3_12_FN, FN_IP8_5_3,
3156 GP_3_11_FN, FN_IP8_2_0,
3157 GP_3_10_FN, FN_IP7_29_27,
3158 GP_3_9_FN, FN_IP7_26_24,
3159 GP_3_8_FN, FN_IP7_23_21,
3160 GP_3_7_FN, FN_IP7_20_19,
3161 GP_3_6_FN, FN_IP7_18_17,
3162 GP_3_5_FN, FN_IP7_16_15,
3163 GP_3_4_FN, FN_IP7_14_13,
3164 GP_3_3_FN, FN_IP7_12_11,
3165 GP_3_2_FN, FN_IP7_10_9,
3166 GP_3_1_FN, FN_IP7_8_6,
3167 GP_3_0_FN, FN_IP7_5_3 }
3168 },
3169 { PINMUX_CFG_REG("GPSR4", 0xE6060014, 32, 1) {
3170 GP_4_31_FN, FN_IP15_5_4,
3171 GP_4_30_FN, FN_IP15_3_2,
3172 GP_4_29_FN, FN_IP15_1_0,
3173 GP_4_28_FN, FN_IP11_8_6,
3174 GP_4_27_FN, FN_IP11_5_3,
3175 GP_4_26_FN, FN_IP11_2_0,
3176 GP_4_25_FN, FN_IP10_31_29,
3177 GP_4_24_FN, FN_IP10_28_27,
3178 GP_4_23_FN, FN_IP10_26_25,
3179 GP_4_22_FN, FN_IP10_24_22,
3180 GP_4_21_FN, FN_IP10_21_19,
3181 GP_4_20_FN, FN_IP10_18_17,
3182 GP_4_19_FN, FN_IP10_16_15,
3183 GP_4_18_FN, FN_IP10_14_12,
3184 GP_4_17_FN, FN_IP10_11_9,
3185 GP_4_16_FN, FN_IP10_8_6,
3186 GP_4_15_FN, FN_IP10_5_3,
3187 GP_4_14_FN, FN_IP10_2_0,
3188 GP_4_13_FN, FN_IP9_31_29,
3189 GP_4_12_FN, FN_VI0_DATA7_VI0_B7,
3190 GP_4_11_FN, FN_VI0_DATA6_VI0_B6,
3191 GP_4_10_FN, FN_VI0_DATA5_VI0_B5,
3192 GP_4_9_FN, FN_VI0_DATA4_VI0_B4,
3193 GP_4_8_FN, FN_IP9_28_27,
3194 GP_4_7_FN, FN_VI0_DATA2_VI0_B2,
3195 GP_4_6_FN, FN_VI0_DATA1_VI0_B1,
3196 GP_4_5_FN, FN_VI0_DATA0_VI0_B0,
3197 GP_4_4_FN, FN_IP9_26_25,
3198 GP_4_3_FN, FN_IP9_24_23,
3199 GP_4_2_FN, FN_IP9_22_21,
3200 GP_4_1_FN, FN_IP9_20_19,
3201 GP_4_0_FN, FN_VI0_CLK }
3202 },
3203 { PINMUX_CFG_REG("GPSR5", 0xE6060018, 32, 1) {
3204 GP_5_31_FN, FN_IP3_24_22,
3205 GP_5_30_FN, FN_IP13_9_7,
3206 GP_5_29_FN, FN_IP13_6_5,
3207 GP_5_28_FN, FN_IP13_4_3,
3208 GP_5_27_FN, FN_IP13_2_0,
3209 GP_5_26_FN, FN_IP12_29_27,
3210 GP_5_25_FN, FN_IP12_26_24,
3211 GP_5_24_FN, FN_IP12_23_22,
3212 GP_5_23_FN, FN_IP12_21_20,
3213 GP_5_22_FN, FN_IP12_19_18,
3214 GP_5_21_FN, FN_IP12_17_16,
3215 GP_5_20_FN, FN_IP12_15_13,
3216 GP_5_19_FN, FN_IP12_12_10,
3217 GP_5_18_FN, FN_IP12_9_7,
3218 GP_5_17_FN, FN_IP12_6_4,
3219 GP_5_16_FN, FN_IP12_3_2,
3220 GP_5_15_FN, FN_IP12_1_0,
3221 GP_5_14_FN, FN_IP11_31_30,
3222 GP_5_13_FN, FN_IP11_29_28,
3223 GP_5_12_FN, FN_IP11_27,
3224 GP_5_11_FN, FN_IP11_26,
3225 GP_5_10_FN, FN_IP11_25,
3226 GP_5_9_FN, FN_IP11_24,
3227 GP_5_8_FN, FN_IP11_23,
3228 GP_5_7_FN, FN_IP11_22,
3229 GP_5_6_FN, FN_IP11_21,
3230 GP_5_5_FN, FN_IP11_20,
3231 GP_5_4_FN, FN_IP11_19,
3232 GP_5_3_FN, FN_IP11_18_17,
3233 GP_5_2_FN, FN_IP11_16_15,
3234 GP_5_1_FN, FN_IP11_14_12,
3235 GP_5_0_FN, FN_IP11_11_9 }
3236 },
3237 { PINMUX_CFG_REG("GPSR6", 0xE606001C, 32, 1) {
3238 GP_6_31_FN, FN_DU0_DOTCLKIN,
3239 GP_6_30_FN, FN_USB1_OVC,
3240 GP_6_29_FN, FN_IP14_31_29,
3241 GP_6_28_FN, FN_IP14_28_26,
3242 GP_6_27_FN, FN_IP14_25_23,
3243 GP_6_26_FN, FN_IP14_22_20,
3244 GP_6_25_FN, FN_IP14_19_17,
3245 GP_6_24_FN, FN_IP14_16_14,
3246 GP_6_23_FN, FN_IP14_13_11,
3247 GP_6_22_FN, FN_IP14_10_8,
3248 GP_6_21_FN, FN_IP14_7,
3249 GP_6_20_FN, FN_IP14_6,
3250 GP_6_19_FN, FN_IP14_5,
3251 GP_6_18_FN, FN_IP14_4,
3252 GP_6_17_FN, FN_IP14_3,
3253 GP_6_16_FN, FN_IP14_2,
3254 GP_6_15_FN, FN_IP14_1_0,
3255 GP_6_14_FN, FN_IP13_30_28,
3256 GP_6_13_FN, FN_IP13_27,
3257 GP_6_12_FN, FN_IP13_26,
3258 GP_6_11_FN, FN_IP13_25,
3259 GP_6_10_FN, FN_IP13_24_23,
3260 GP_6_9_FN, FN_IP13_22,
3261 0, 0,
3262 GP_6_7_FN, FN_IP13_21_19,
3263 GP_6_6_FN, FN_IP13_18_16,
3264 GP_6_5_FN, FN_IP13_15,
3265 GP_6_4_FN, FN_IP13_14,
3266 GP_6_3_FN, FN_IP13_13,
3267 GP_6_2_FN, FN_IP13_12,
3268 GP_6_1_FN, FN_IP13_11,
3269 GP_6_0_FN, FN_IP13_10 }
3270 },
3271 { PINMUX_CFG_REG("GPSR7", 0xE6060074, 32, 1) {
3272 0, 0,
3273 0, 0,
3274 0, 0,
3275 0, 0,
3276 0, 0,
3277 0, 0,
3278 GP_7_25_FN, FN_USB1_PWEN,
3279 GP_7_24_FN, FN_USB0_OVC,
3280 GP_7_23_FN, FN_USB0_PWEN,
3281 GP_7_22_FN, FN_IP15_14_12,
3282 GP_7_21_FN, FN_IP15_11_9,
3283 GP_7_20_FN, FN_IP15_8_6,
3284 GP_7_19_FN, FN_IP7_2_0,
3285 GP_7_18_FN, FN_IP6_29_27,
3286 GP_7_17_FN, FN_IP6_26_24,
3287 GP_7_16_FN, FN_IP6_23_21,
3288 GP_7_15_FN, FN_IP6_20_19,
3289 GP_7_14_FN, FN_IP6_18_16,
3290 GP_7_13_FN, FN_IP6_15_14,
3291 GP_7_12_FN, FN_IP6_13_12,
3292 GP_7_11_FN, FN_IP6_11_10,
3293 GP_7_10_FN, FN_IP6_9_8,
3294 GP_7_9_FN, FN_IP16_11_10,
3295 GP_7_8_FN, FN_IP16_9_8,
3296 GP_7_7_FN, FN_IP16_7_6,
3297 GP_7_6_FN, FN_IP16_5_3,
3298 GP_7_5_FN, FN_IP16_2_0,
3299 GP_7_4_FN, FN_IP15_29_27,
3300 GP_7_3_FN, FN_IP15_26_24,
3301 GP_7_2_FN, FN_IP15_23_21,
3302 GP_7_1_FN, FN_IP15_20_18,
3303 GP_7_0_FN, FN_IP15_17_15 }
3304 },
3305 { PINMUX_CFG_REG_VAR("IPSR0", 0xE6060020, 32,
3306 1, 2, 2, 2, 2, 2, 2, 3, 1, 1, 1, 1, 1, 1, 1, 1,
3307 1, 1, 1, 1, 1, 1, 1, 1) {
3308 /* IP0_31 [1] */
3309 0, 0,
3310 /* IP0_30_29 [2] */
3311 FN_A6, FN_MSIOF1_SCK,
3312 0, 0,
3313 /* IP0_28_27 [2] */
3314 FN_A5, FN_MSIOF0_RXD_B,
3315 0, 0,
3316 /* IP0_26_25 [2] */
3317 FN_A4, FN_MSIOF0_TXD_B,
3318 0, 0,
3319 /* IP0_24_23 [2] */
3320 FN_A3, FN_MSIOF0_SS2_B,
3321 0, 0,
3322 /* IP0_22_21 [2] */
3323 FN_A2, FN_MSIOF0_SS1_B,
3324 0, 0,
3325 /* IP0_20_19 [2] */
3326 FN_A1, FN_MSIOF0_SYNC_B,
3327 0, 0,
3328 /* IP0_18_16 [3] */
3329 FN_A0, FN_ATAWR0_N_C, FN_MSIOF0_SCK_B, FN_SCL0_C, FN_PWM2_B,
3330 0, 0, 0,
3331 /* IP0_15 [1] */
3332 FN_D15, 0,
3333 /* IP0_14 [1] */
3334 FN_D14, 0,
3335 /* IP0_13 [1] */
3336 FN_D13, 0,
3337 /* IP0_12 [1] */
3338 FN_D12, 0,
3339 /* IP0_11 [1] */
3340 FN_D11, 0,
3341 /* IP0_10 [1] */
3342 FN_D10, 0,
3343 /* IP0_9 [1] */
3344 FN_D9, 0,
3345 /* IP0_8 [1] */
3346 FN_D8, 0,
3347 /* IP0_7 [1] */
3348 FN_D7, 0,
3349 /* IP0_6 [1] */
3350 FN_D6, 0,
3351 /* IP0_5 [1] */
3352 FN_D5, 0,
3353 /* IP0_4 [1] */
3354 FN_D4, 0,
3355 /* IP0_3 [1] */
3356 FN_D3, 0,
3357 /* IP0_2 [1] */
3358 FN_D2, 0,
3359 /* IP0_1 [1] */
3360 FN_D1, 0,
3361 /* IP0_0 [1] */
3362 FN_D0, 0, }
3363 },
3364 { PINMUX_CFG_REG_VAR("IPSR1", 0xE6060024, 32,
3365 3, 3, 3, 3, 3, 3, 3, 3, 2, 2, 2, 2) {
3366 /* IP1_31_29 [3] */
3367 FN_A18, FN_DREQ1, FN_SCIFA1_RXD_C, 0, FN_SCIFB1_RXD_C,
3368 0, 0, 0,
3369 /* IP1_28_26 [3] */
3370 FN_A17, FN_DACK2_B, 0, FN_SDA0_C,
3371 0, 0, 0, 0,
3372 /* IP1_25_23 [3] */
3373 FN_A16, FN_DREQ2_B, FN_FMCLK_C, 0, FN_SCIFA1_SCK_B,
3374 0, 0, 0,
3375 /* IP1_22_20 [3] */
3376 FN_A15, FN_BPFCLK_C,
3377 0, 0, 0, 0, 0, 0,
3378 /* IP1_19_17 [3] */
3379 FN_A14, FN_ATADIR0_N_C, FN_FMIN, FN_FMIN_C, FN_MSIOF1_SYNC_D,
3380 0, 0, 0,
3381 /* IP1_16_14 [3] */
3382 FN_A13, FN_ATAG0_N_C, FN_BPFCLK, FN_MSIOF1_SS1_D,
3383 0, 0, 0, 0,
3384 /* IP1_13_11 [3] */
3385 FN_A12, FN_FMCLK, FN_SDA3_D, FN_MSIOF1_SCK_D,
3386 0, 0, 0, 0,
3387 /* IP1_10_8 [3] */
3388 FN_A11, FN_MSIOF1_RXD, FN_SCL3_D, FN_MSIOF1_RXD_D,
3389 0, 0, 0, 0,
3390 /* IP1_7_6 [2] */
3391 FN_A10, FN_MSIOF1_TXD, 0, FN_MSIOF1_TXD_D,
3392 /* IP1_5_4 [2] */
3393 FN_A9, FN_MSIOF1_SS2, FN_SDA0, 0,
3394 /* IP1_3_2 [2] */
3395 FN_A8, FN_MSIOF1_SS1, FN_SCL0, 0,
3396 /* IP1_1_0 [2] */
3397 FN_A7, FN_MSIOF1_SYNC,
3398 0, 0, }
3399 },
3400 { PINMUX_CFG_REG_VAR("IPSR2", 0xE6060028, 32,
3401 2, 3, 2, 2, 2, 2, 3, 3, 3, 3, 2, 2, 3) {
3402 /* IP2_31_20 [2] */
3403 0, 0, 0, 0,
3404 /* IP2_29_27 [3] */
3405 FN_EX_CS3_N, FN_ATADIR0_N, FN_MSIOF2_TXD,
3406 FN_ATAG0_N, 0, FN_EX_WAIT1,
3407 0, 0,
3408 /* IP2_26_25 [2] */
3409 FN_EX_CS2_N, FN_ATAWR0_N, FN_MSIOF2_SYNC, 0,
3410 /* IP2_24_23 [2] */
3411 FN_EX_CS1_N, FN_MSIOF2_SCK, 0, 0,
3412 /* IP2_22_21 [2] */
3413 FN_CS1_N_A26, FN_ATADIR0_N_B, FN_SDA1, 0,
3414 /* IP2_20_19 [2] */
3415 FN_CS0_N, FN_ATAG0_N_B, FN_SCL1, 0,
3416 /* IP2_18_16 [3] */
3417 FN_A25, FN_DACK2, FN_SSL, FN_DREQ1_C, FN_RX1, FN_SCIFA1_RXD,
3418 0, 0,
3419 /* IP2_15_13 [3] */
3420 FN_A24, FN_DREQ2, FN_IO3, FN_TX1, FN_SCIFA1_TXD,
3421 0, 0, 0,
3422 /* IP2_12_0 [3] */
3423 FN_A23, FN_IO2, FN_BPFCLK_B, FN_RX0, FN_SCIFA0_RXD,
3424 0, 0, 0,
3425 /* IP2_9_7 [3] */
3426 FN_A22, FN_MISO_IO1, FN_FMCLK_B, FN_TX0, FN_SCIFA0_TXD,
3427 0, 0, 0,
3428 /* IP2_6_5 [2] */
3429 FN_A21, FN_ATAWR0_N_B, FN_MOSI_IO0, 0,
3430 /* IP2_4_3 [2] */
3431 FN_A20, FN_SPCLK, 0, 0,
3432 /* IP2_2_0 [3] */
3433 FN_A19, FN_DACK1, FN_SCIFA1_TXD_C, 0,
3434 FN_SCIFB1_TXD_C, 0, FN_SCIFB1_SCK_B, 0, }
3435 },
3436 { PINMUX_CFG_REG_VAR("IPSR3", 0xE606002C, 32,
3437 1, 3, 3, 3, 2, 2, 2, 2, 2, 3, 3, 3, 3) {
3438 /* IP3_31 [1] */
3439 0, 0,
3440 /* IP3_30_28 [3] */
3441 FN_SSI_WS0129, FN_HTX0_C, FN_HTX2_C,
3442 FN_SCIFB0_TXD_C, FN_SCIFB2_TXD_C,
3443 0, 0, 0,
3444 /* IP3_27_25 [3] */
3445 FN_SSI_SCK0129, FN_HRX0_C, FN_HRX2_C,
3446 FN_SCIFB0_RXD_C, FN_SCIFB2_RXD_C,
3447 0, 0, 0,
3448 /* IP3_24_22 [3] */
3449 FN_SPEEDIN, 0, FN_HSCK0_C, FN_HSCK2_C, FN_SCIFB0_SCK_B,
3450 FN_SCIFB2_SCK_B, FN_DREQ2_C, FN_HTX2_D,
3451 /* IP3_21_20 [2] */
3452 FN_DACK0, FN_DRACK0, FN_REMOCON, 0,
3453 /* IP3_19_18 [2] */
3454 FN_DREQ0, FN_PWM3, FN_TPU_TO3, 0,
3455 /* IP3_17_16 [2] */
3456 FN_EX_WAIT0, FN_HRTS2_N_B, FN_SCIFB0_CTS_N_B, 0,
3457 /* IP3_15_14 [2] */
3458 FN_WE1_N, FN_ATARD0_N_B, FN_HTX2_B, FN_SCIFB0_RTS_N_B,
3459 /* IP3_13_12 [2] */
3460 FN_WE0_N, FN_HCTS2_N_B, FN_SCIFB0_TXD_B, 0,
3461 /* IP3_11_9 [3] */
3462 FN_RD_WR_N, FN_HRX2_B, FN_FMIN_B, FN_SCIFB0_RXD_B, FN_DREQ1_D,
3463 0, 0, 0,
3464 /* IP3_8_6 [3] */
3465 FN_BS_N, FN_ATACS10_N, FN_MSIOF2_SS2, FN_HTX1_B,
3466 FN_SCIFB1_TXD_B, FN_PWM2, FN_TPU_TO2, 0,
3467 /* IP3_5_3 [3] */
3468 FN_EX_CS5_N, FN_ATACS00_N, FN_MSIOF2_SS1, FN_HRX1_B,
3469 FN_SCIFB1_RXD_B, FN_PWM1, FN_TPU_TO1, 0,
3470 /* IP3_2_0 [3] */
3471 FN_EX_CS4_N, FN_ATARD0_N, FN_MSIOF2_RXD, 0, FN_EX_WAIT2,
3472 0, 0, 0, }
3473 },
3474 { PINMUX_CFG_REG_VAR("IPSR4", 0xE6060030, 32,
3475 1, 3, 2, 2, 2, 1, 1, 1, 3, 3, 3, 2, 3, 3, 2) {
3476 /* IP4_31 [1] */
3477 0, 0,
3478 /* IP4_30_28 [3] */
3479 FN_SSI_SCK5, FN_MSIOF1_SCK_C, FN_TS_SDATA0, FN_GLO_I0,
3480 FN_MSIOF2_SYNC_D, FN_VI1_R2_B,
3481 0, 0,
3482 /* IP4_27_26 [2] */
3483 FN_SSI_SDATA4, FN_MSIOF2_SCK_D, 0, 0,
3484 /* IP4_25_24 [2] */
3485 FN_SSI_WS4, FN_GLO_RFON_D, 0, 0,
3486 /* IP4_23_22 [2] */
3487 FN_SSI_SCK4, FN_GLO_SS_D, 0, 0,
3488 /* IP4_21 [1] */
3489 FN_SSI_SDATA3, 0,
3490 /* IP4_20 [1] */
3491 FN_SSI_WS34, 0,
3492 /* IP4_19 [1] */
3493 FN_SSI_SCK34, 0,
3494 /* IP4_18_16 [3] */
3495 FN_SSI_SDATA2, FN_GPS_MAG_B, FN_TX2_E, FN_HRTS1_N_E,
3496 0, 0, 0, 0,
3497 /* IP4_15_13 [3] */
3498 FN_SSI_WS2, FN_SDA2, FN_GPS_SIGN_B, FN_RX2_E,
3499 FN_GLO_Q1_D, FN_HCTS1_N_E,
3500 0, 0,
3501 /* IP4_12_10 [3] */
3502 FN_SSI_SCK2, FN_SCL2, FN_GPS_CLK_B, FN_GLO_Q0_D, FN_HSCK1_E,
3503 0, 0, 0,
3504 /* IP4_9_8 [2] */
3505 FN_SSI_SDATA1, FN_SDA1_B, FN_SDA8_B, FN_MSIOF2_RXD_C,
3506 /* IP4_7_5 [3] */
3507 FN_SSI_WS1, FN_SCL1_B, FN_SCL8_B, FN_MSIOF2_TXD_C, FN_GLO_I1_D,
3508 0, 0, 0,
3509 /* IP4_4_2 [3] */
3510 FN_SSI_SCK1, FN_SDA0_B, FN_SDA7_B,
3511 FN_MSIOF2_SYNC_C, FN_GLO_I0_D,
3512 0, 0, 0,
3513 /* IP4_1_0 [2] */
3514 FN_SSI_SDATA0, FN_SCL0_B, FN_SCL7_B, FN_MSIOF2_SCK_C, }
3515 },
3516 { PINMUX_CFG_REG_VAR("IPSR5", 0xE6060034, 32,
3517 3, 3, 2, 2, 2, 3, 2, 3, 3, 3, 3, 3) {
3518 /* IP5_31_29 [3] */
3519 FN_SSI_SDATA9, FN_RX3_D, FN_CAN0_RX_D,
3520 0, 0, 0, 0, 0,
3521 /* IP5_28_26 [3] */
3522 FN_SSI_WS9, FN_TX3_D, FN_CAN0_TX_D, FN_GLO_SDATA_D,
3523 0, 0, 0, 0,
3524 /* IP5_25_24 [2] */
3525 FN_SSI_SCK9, FN_RX1_D, FN_GLO_SCLK_D, 0,
3526 /* IP5_23_22 [2] */
3527 FN_SSI_SDATA8, FN_TX1_D, FN_STP_ISSYNC_0_B, 0,
3528 /* IP5_21_20 [2] */
3529 FN_SSI_SDATA7, FN_RX0_D, FN_STP_ISEN_0_B, 0,
3530 /* IP5_19_17 [3] */
3531 FN_SSI_WS78, FN_TX0_D, FN_STP_ISD_0_B, FN_GLO_RFON,
3532 0, 0, 0, 0,
3533 /* IP5_16_15 [2] */
3534 FN_SSI_SCK78, FN_STP_ISCLK_0_B, FN_GLO_SS, 0,
3535 /* IP5_14_12 [3] */
3536 FN_SSI_SDATA6, FN_STP_IVCXO27_0_B, FN_GLO_SDATA, FN_VI1_R7_B,
3537 0, 0, 0, 0,
3538 /* IP5_11_9 [3] */
3539 FN_SSI_WS6, FN_GLO_SCLK, FN_MSIOF2_SS2_D, FN_VI1_R6_B,
3540 0, 0, 0, 0,
3541 /* IP5_8_6 [3] */
3542 FN_SSI_SCK6, FN_MSIOF1_RXD_C, FN_TS_SPSYNC0, FN_GLO_Q1,
3543 FN_MSIOF2_RXD_D, FN_VI1_R5_B,
3544 0, 0,
3545 /* IP5_5_3 [3] */
3546 FN_SSI_SDATA5, FN_MSIOF1_TXD_C, FN_TS_SDEN0, FN_GLO_Q0,
3547 FN_MSIOF2_SS1_D, FN_VI1_R4_B,
3548 0, 0,
3549 /* IP5_2_0 [3] */
3550 FN_SSI_WS5, FN_MSIOF1_SYNC_C, FN_TS_SCK0, FN_GLO_I1,
3551 FN_MSIOF2_TXD_D, FN_VI1_R3_B,
3552 0, 0, }
3553 },
3554 { PINMUX_CFG_REG_VAR("IPSR6", 0xE6060038, 32,
3555 2, 3, 3, 3, 2, 3, 2, 2, 2, 2, 2, 3, 3) {
3556 /* IP6_31_30 [2] */
3557 0, 0, 0, 0,
3558 /* IP6_29_27 [3] */
3559 FN_IRQ8, FN_HRTS1_N_C, FN_MSIOF1_RXD_B,
3560 FN_GPS_SIGN_C, FN_GPS_SIGN_D,
3561 0, 0, 0,
3562 /* IP6_26_24 [3] */
3563 FN_IRQ7, FN_HCTS1_N_C, FN_MSIOF1_TXD_B,
3564 FN_GPS_CLK_C, FN_GPS_CLK_D,
3565 0, 0, 0,
3566 /* IP6_23_21 [3] */
3567 FN_IRQ6, FN_HSCK1_C, FN_MSIOF1_SS2_B,
3568 FN_SDA1_E, FN_MSIOF2_SYNC_E,
3569 0, 0, 0,
3570 /* IP6_20_19 [2] */
3571 FN_IRQ5, FN_HTX1_C, FN_SCL1_E, FN_MSIOF2_SCK_E,
3572 /* IP6_18_16 [3] */
3573 FN_IRQ4, FN_HRX1_C, FN_SDA4_C, FN_MSIOF2_RXD_E, FN_INTC_IRQ4_N,
3574 0, 0, 0,
3575 /* IP6_15_14 [2] */
3576 FN_IRQ3, FN_SCL4_C, FN_MSIOF2_TXD_E, FN_INTC_IRQ3_N,
3577 /* IP6_13_12 [2] */
3578 FN_IRQ2, FN_SCIFB1_TXD_D, FN_INTC_IRQ2_N, 0,
3579 /* IP6_11_10 [2] */
3580 FN_IRQ1, FN_SCIFB1_SCK_C, FN_INTC_IRQ1_N, 0,
3581 /* IP6_9_8 [2] */
3582 FN_IRQ0, FN_SCIFB1_RXD_D, FN_INTC_IRQ0_N, 0,
3583 /* IP6_7_6 [2] */
3584 FN_AUDIO_CLKOUT, FN_MSIOF1_SS1_B, FN_TX2, FN_SCIFA2_TXD,
3585 /* IP6_5_3 [3] */
3586 FN_AUDIO_CLKC, FN_SCIFB0_SCK_C, FN_MSIOF1_SYNC_B, FN_RX2,
3587 FN_SCIFA2_RXD, FN_FMIN_E,
3588 0, 0,
3589 /* IP6_2_0 [3] */
3590 FN_AUDIO_CLKB, FN_STP_OPWM_0_B, FN_MSIOF1_SCK_B,
3591 FN_SCIF_CLK, 0, FN_BPFCLK_E,
3592 0, 0, }
3593 },
3594 { PINMUX_CFG_REG_VAR("IPSR7", 0xE606003C, 32,
3595 2, 3, 3, 3, 2, 2, 2, 2, 2, 2, 3, 3, 3) {
3596 /* IP7_31_30 [2] */
3597 0, 0, 0, 0,
3598 /* IP7_29_27 [3] */
3599 FN_DU1_DG2, FN_LCDOUT10, FN_VI1_DATA4_B, FN_SCIF1_SCK_B,
3600 FN_SCIFA1_SCK, FN_SSI_SCK78_B,
3601 0, 0,
3602 /* IP7_26_24 [3] */
3603 FN_DU1_DG1, FN_LCDOUT9, FN_VI1_DATA3_B, FN_RX1_B,
3604 FN_SCIFA1_RXD_B, FN_MSIOF2_SS2_B,
3605 0, 0,
3606 /* IP7_23_21 [3] */
3607 FN_DU1_DG0, FN_LCDOUT8, FN_VI1_DATA2_B, FN_TX1_B,
3608 FN_SCIFA1_TXD_B, FN_MSIOF2_SS1_B,
3609 0, 0,
3610 /* IP7_20_19 [2] */
3611 FN_DU1_DR7, FN_LCDOUT7, FN_SSI_SDATA1_B, 0,
3612 /* IP7_18_17 [2] */
3613 FN_DU1_DR6, FN_LCDOUT6, FN_SSI_WS1_B, 0,
3614 /* IP7_16_15 [2] */
3615 FN_DU1_DR5, FN_LCDOUT5, FN_SSI_SCK1_B, 0,
3616 /* IP7_14_13 [2] */
3617 FN_DU1_DR4, FN_LCDOUT4, FN_SSI_SDATA0_B, 0,
3618 /* IP7_12_11 [2] */
3619 FN_DU1_DR3, FN_LCDOUT3, FN_SSI_WS0129_B, 0,
3620 /* IP7_10_9 [2] */
3621 FN_DU1_DR2, FN_LCDOUT2, FN_SSI_SCK0129_B, 0,
3622 /* IP7_8_6 [3] */
3623 FN_DU1_DR1, FN_LCDOUT1, FN_VI1_DATA1_B, FN_RX0_B,
3624 FN_SCIFA0_RXD_B, FN_MSIOF2_SYNC_B,
3625 0, 0,
3626 /* IP7_5_3 [3] */
3627 FN_DU1_DR0, FN_LCDOUT0, FN_VI1_DATA0_B, FN_TX0_B,
3628 FN_SCIFA0_TXD_B, FN_MSIOF2_SCK_B,
3629 0, 0,
3630 /* IP7_2_0 [3] */
3631 FN_IRQ9, FN_DU1_DOTCLKIN_B, FN_CAN_CLK_D, FN_GPS_MAG_C,
3632 FN_SCIF_CLK_B, FN_GPS_MAG_D,
3633 0, 0, }
3634 },
3635 { PINMUX_CFG_REG_VAR("IPSR8", 0xE6060040, 32,
3636 1, 3, 2, 2, 3, 3, 3, 3, 3, 3, 3, 3) {
3637 /* IP8_31 [1] */
3638 0, 0,
3639 /* IP8_30_28 [3] */
3640 FN_DU1_DB5, FN_LCDOUT21, FN_TX3, FN_SCIFA3_TXD, FN_CAN1_TX,
3641 0, 0, 0,
3642 /* IP8_27_26 [2] */
3643 FN_DU1_DB4, FN_LCDOUT20, FN_VI1_FIELD_B, FN_CAN1_RX,
3644 /* IP8_25_24 [2] */
3645 FN_DU1_DB3, FN_LCDOUT19, FN_VI1_CLKENB_B, 0,
3646 /* IP8_23_21 [3] */
3647 FN_DU1_DB2, FN_LCDOUT18, FN_VI1_VSYNC_N_B, FN_SCIF2_SCK_B,
3648 FN_SCIFA2_SCK, FN_SSI_SDATA9_B,
3649 0, 0,
3650 /* IP8_20_18 [3] */
3651 FN_DU1_DB1, FN_LCDOUT17, FN_VI1_HSYNC_N_B, FN_RX2_B,
3652 FN_SCIFA2_RXD_B, FN_MSIOF2_RXD_B,
3653 0, 0,
3654 /* IP8_17_15 [3] */
3655 FN_DU1_DB0, FN_LCDOUT16, FN_VI1_CLK_B, FN_TX2_B,
3656 FN_SCIFA2_TXD_B, FN_MSIOF2_TXD_B,
3657 0, 0,
3658 /* IP8_14_12 [3] */
3659 FN_DU1_DG7, FN_LCDOUT15, FN_HTX0_B,
3660 FN_SCIFB2_RTS_N_B, FN_SSI_WS9_B,
3661 0, 0, 0,
3662 /* IP8_11_9 [3] */
3663 FN_DU1_DG6, FN_LCDOUT14, FN_HRTS0_N_B,
3664 FN_SCIFB2_CTS_N_B, FN_SSI_SCK9_B,
3665 0, 0, 0,
3666 /* IP8_8_6 [3] */
3667 FN_DU1_DG5, FN_LCDOUT13, FN_VI1_DATA7_B, FN_HCTS0_N_B,
3668 FN_SCIFB2_TXD_B, FN_SSI_SDATA8_B,
3669 0, 0,
3670 /* IP8_5_3 [3] */
3671 FN_DU1_DG4, FN_LCDOUT12, FN_VI1_DATA6_B, FN_HRX0_B,
3672 FN_SCIFB2_RXD_B, FN_SSI_SDATA7_B,
3673 0, 0,
3674 /* IP8_2_0 [3] */
3675 FN_DU1_DG3, FN_LCDOUT11, FN_VI1_DATA5_B, 0, FN_SSI_WS78_B,
3676 0, 0, 0, }
3677 },
3678 { PINMUX_CFG_REG_VAR("IPSR9", 0xE6060044, 32,
3679 3, 2, 2, 2, 2, 2, 2, 1, 3, 1, 1, 3, 1, 1, 3, 3) {
3680 /* IP9_31_29 [3] */
3681 FN_VI0_G0, FN_SCL8, FN_STP_IVCXO27_0_C, FN_SCL4,
3682 FN_HCTS2_N, FN_SCIFB2_CTS_N, FN_ATAWR1_N, 0,
3683 /* IP9_28_27 [2] */
3684 FN_VI0_DATA3_VI0_B3, FN_SCIF3_SCK_B, FN_SCIFA3_SCK_B, 0,
3685 /* IP9_26_25 [2] */
3686 FN_VI0_VSYNC_N, FN_RX5, FN_SCIFA5_RXD, FN_TS_SPSYNC0_D,
3687 /* IP9_24_23 [2] */
3688 FN_VI0_HSYNC_N, FN_TX5, FN_SCIFA5_TXD, FN_TS_SDEN0_D,
3689 /* IP9_22_21 [2] */
3690 FN_VI0_FIELD, FN_RX4, FN_SCIFA4_RXD, FN_TS_SCK0_D,
3691 /* IP9_20_19 [2] */
3692 FN_VI0_CLKENB, FN_TX4, FN_SCIFA4_TXD, FN_TS_SDATA0_D,
3693 /* IP9_18_17 [2] */
3694 FN_DU1_CDE, FN_QPOLB, FN_PWM4_B, 0,
3695 /* IP9_16 [1] */
3696 FN_DU1_DISP, FN_QPOLA,
3697 /* IP9_15_13 [3] */
3698 FN_DU1_EXODDF_DU1_ODDF_DISP_CDE, FN_QCPV_QDE,
3699 FN_CAN0_RX, FN_RX3_B, FN_SDA2_B,
3700 0, 0, 0,
3701 /* IP9_12 [1] */
3702 FN_DU1_EXVSYNC_DU1_VSYNC, FN_QSTB_QHE,
3703 /* IP9_11 [1] */
3704 FN_DU1_EXHSYNC_DU1_HSYNC, FN_QSTH_QHS,
3705 /* IP9_10_8 [3] */
3706 FN_DU1_DOTCLKOUT1, FN_QSTVB_QVE, FN_CAN0_TX,
3707 FN_TX3_B, FN_SCL2_B, FN_PWM4,
3708 0, 0,
3709 /* IP9_7 [1] */
3710 FN_DU1_DOTCLKOUT0, FN_QCLK,
3711 /* IP9_6 [1] */
3712 FN_DU1_DOTCLKIN, FN_QSTVA_QVS,
3713 /* IP9_5_3 [3] */
3714 FN_DU1_DB7, FN_LCDOUT23, FN_SDA3_C,
3715 FN_SCIF3_SCK, FN_SCIFA3_SCK,
3716 0, 0, 0,
3717 /* IP9_2_0 [3] */
3718 FN_DU1_DB6, FN_LCDOUT22, FN_SCL3_C, FN_RX3, FN_SCIFA3_RXD,
3719 0, 0, 0, }
3720 },
3721 { PINMUX_CFG_REG_VAR("IPSR10", 0xE6060048, 32,
3722 3, 2, 2, 3, 3, 2, 2, 3, 3, 3, 3, 3) {
3723 /* IP10_31_29 [3] */
3724 FN_VI0_R4, FN_VI2_DATA5, FN_GLO_SCLK_B, FN_TX0_C, FN_SCL1_D,
3725 0, 0, 0,
3726 /* IP10_28_27 [2] */
3727 FN_VI0_R3, FN_VI2_DATA4, FN_GLO_Q1_B, FN_TS_SPSYNC0_C,
3728 /* IP10_26_25 [2] */
3729 FN_VI0_R2, FN_VI2_DATA3, FN_GLO_Q0_B, FN_TS_SDEN0_C,
3730 /* IP10_24_22 [3] */
3731 FN_VI0_R1, FN_VI2_DATA2, FN_GLO_I1_B, FN_TS_SCK0_C, FN_ATAG1_N,
3732 0, 0, 0,
3733 /* IP10_21_29 [3] */
3734 FN_VI0_R0, FN_VI2_DATA1, FN_GLO_I0_B,
3735 FN_TS_SDATA0_C, FN_ATACS11_N,
3736 0, 0, 0,
3737 /* IP10_18_17 [2] */
3738 FN_VI0_G7, FN_VI2_DATA0, FN_FMIN_D, 0,
3739 /* IP10_16_15 [2] */
3740 FN_VI0_G6, FN_VI2_CLK, FN_BPFCLK_D, 0,
3741 /* IP10_14_12 [3] */
3742 FN_VI0_G5, FN_VI2_FIELD, FN_STP_OPWM_0_C, FN_FMCLK_D,
3743 FN_CAN0_TX_E, FN_HTX1_D, FN_SCIFB0_TXD_D, 0,
3744 /* IP10_11_9 [3] */
3745 FN_VI0_G4, FN_VI2_CLKENB, FN_STP_ISSYNC_0_C,
3746 FN_HTX2, FN_SCIFB2_TXD, FN_SCIFB0_SCK_D,
3747 0, 0,
3748 /* IP10_8_6 [3] */
3749 FN_VI0_G3, FN_VI2_VSYNC_N, FN_STP_ISEN_0_C, FN_SDA3_B,
3750 FN_HRX2, FN_SCIFB2_RXD, FN_ATACS01_N, 0,
3751 /* IP10_5_3 [3] */
3752 FN_VI0_G2, FN_VI2_HSYNC_N, FN_STP_ISD_0_C, FN_SCL3_B,
3753 FN_HSCK2, FN_SCIFB2_SCK, FN_ATARD1_N, 0,
3754 /* IP10_2_0 [3] */
3755 FN_VI0_G1, FN_SDA8, FN_STP_ISCLK_0_C, FN_SDA4,
3756 FN_HRTS2_N, FN_SCIFB2_RTS_N, FN_ATADIR1_N, 0, }
3757 },
3758 { PINMUX_CFG_REG_VAR("IPSR11", 0xE606004C, 32,
3759 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 2, 2,
3760 3, 3, 3, 3, 3) {
3761 /* IP11_31_30 [2] */
3762 FN_ETH_CRS_DV, FN_AVB_LINK, FN_SDA2_C, 0,
3763 /* IP11_29_28 [2] */
3764 FN_ETH_MDIO, FN_AVB_RX_CLK, FN_SCL2_C, 0,
3765 /* IP11_27 [1] */
3766 FN_VI1_DATA7, FN_AVB_MDC,
3767 /* IP11_26 [1] */
3768 FN_VI1_DATA6, FN_AVB_MAGIC,
3769 /* IP11_25 [1] */
3770 FN_VI1_DATA5, FN_AVB_RX_DV,
3771 /* IP11_24 [1] */
3772 FN_VI1_DATA4, FN_AVB_MDIO,
3773 /* IP11_23 [1] */
3774 FN_VI1_DATA3, FN_AVB_RX_ER,
3775 /* IP11_22 [1] */
3776 FN_VI1_DATA2, FN_AVB_RXD7,
3777 /* IP11_21 [1] */
3778 FN_VI1_DATA1, FN_AVB_RXD6,
3779 /* IP11_20 [1] */
3780 FN_VI1_DATA0, FN_AVB_RXD5,
3781 /* IP11_19 [1] */
3782 FN_VI1_CLK, FN_AVB_RXD4,
3783 /* IP11_18_17 [2] */
3784 FN_VI1_FIELD, FN_AVB_RXD3, FN_TS_SPSYNC0_B, 0,
3785 /* IP11_16_15 [2] */
3786 FN_VI1_CLKENB, FN_AVB_RXD2, FN_TS_SDEN0_B, 0,
3787 /* IP11_14_12 [3] */
3788 FN_VI1_VSYNC_N, FN_AVB_RXD1, FN_TS_SCK0_B,
3789 FN_RX4_B, FN_SCIFA4_RXD_B,
3790 0, 0, 0,
3791 /* IP11_11_9 [3] */
3792 FN_VI1_HSYNC_N, FN_AVB_RXD0, FN_TS_SDATA0_B,
3793 FN_TX4_B, FN_SCIFA4_TXD_B,
3794 0, 0, 0,
3795 /* IP11_8_6 [3] */
3796 FN_VI0_R7, FN_GLO_RFON_B, FN_RX1_C, FN_CAN0_RX_E,
3797 FN_SDA4_B, FN_HRX1_D, FN_SCIFB0_RXD_D, 0,
3798 /* IP11_5_3 [3] */
3799 FN_VI0_R6, FN_VI2_DATA7, FN_GLO_SS_B, FN_TX1_C, FN_SCL4_B,
3800 0, 0, 0,
3801 /* IP11_2_0 [3] */
3802 FN_VI0_R5, FN_VI2_DATA6, FN_GLO_SDATA_B, FN_RX0_C, FN_SDA1_D,
3803 0, 0, 0, }
3804 },
3805 { PINMUX_CFG_REG_VAR("IPSR12", 0xE6060050, 32,
3806 2, 3, 3, 2, 2, 2, 2, 3, 3, 3, 3, 2, 2) {
3807 /* IP12_31_30 [2] */
3808 0, 0, 0, 0,
3809 /* IP12_29_27 [3] */
3810 FN_STP_ISCLK_0, FN_AVB_TX_EN, FN_SCIFB2_RXD_D,
3811 FN_ADICS_SAMP_B, FN_MSIOF0_SCK_C,
3812 0, 0, 0,
3813 /* IP12_26_24 [3] */
3814 FN_STP_IVCXO27_0, FN_AVB_TXD7, FN_SCIFB2_TXD_D,
3815 FN_ADIDATA_B, FN_MSIOF0_SYNC_C,
3816 0, 0, 0,
3817 /* IP12_23_22 [2] */
3818 FN_ETH_MDC, FN_AVB_TXD6, FN_IERX_C, 0,
3819 /* IP12_21_20 [2] */
3820 FN_ETH_TXD0, FN_AVB_TXD5, FN_IECLK_C, 0,
3821 /* IP12_19_18 [2] */
3822 FN_ETH_MAGIC, FN_AVB_TXD4, FN_IETX_C, 0,
3823 /* IP12_17_16 [2] */
3824 FN_ETH_TX_EN, FN_AVB_TXD3, FN_TCLK1_B, FN_CAN_CLK_B,
3825 /* IP12_15_13 [3] */
3826 FN_ETH_TXD1, FN_AVB_TXD2, FN_SCIFA3_TXD_B,
3827 FN_CAN1_TX_C, FN_MSIOF1_TXD_E,
3828 0, 0, 0,
3829 /* IP12_12_10 [3] */
3830 FN_ETH_REFCLK, FN_AVB_TXD1, FN_SCIFA3_RXD_B,
3831 FN_CAN1_RX_C, FN_MSIOF1_SYNC_E,
3832 0, 0, 0,
3833 /* IP12_9_7 [3] */
3834 FN_ETH_LINK, FN_AVB_TXD0, FN_CAN0_RX_C,
3835 FN_SDA2_D, FN_MSIOF1_SCK_E,
3836 0, 0, 0,
3837 /* IP12_6_4 [3] */
3838 FN_ETH_RXD1, FN_AVB_GTXREFCLK, FN_CAN0_TX_C,
3839 FN_SCL2_D, FN_MSIOF1_RXD_E,
3840 0, 0, 0,
3841 /* IP12_3_2 [2] */
3842 FN_ETH_RXD0, FN_AVB_PHY_INT, FN_SDA3, FN_SDA7,
3843 /* IP12_1_0 [2] */
3844 FN_ETH_RX_ER, FN_AVB_CRS, FN_SCL3, FN_SCL7, }
3845 },
3846 { PINMUX_CFG_REG_VAR("IPSR13", 0xE6060054, 32,
3847 1, 3, 1, 1, 1, 2, 1, 3, 3, 1, 1, 1, 1, 1, 1,
3848 3, 2, 2, 3) {
3849 /* IP13_31 [1] */
3850 0, 0,
3851 /* IP13_30_28 [3] */
3852 FN_SD1_CD, FN_PWM0, FN_TPU_TO0, FN_SCL1_C,
3853 0, 0, 0, 0,
3854 /* IP13_27 [1] */
3855 FN_SD1_DATA3, FN_IERX_B,
3856 /* IP13_26 [1] */
3857 FN_SD1_DATA2, FN_IECLK_B,
3858 /* IP13_25 [1] */
3859 FN_SD1_DATA1, FN_IETX_B,
3860 /* IP13_24_23 [2] */
3861 FN_SD1_DATA0, FN_SPEEDIN_B, 0, 0,
3862 /* IP13_22 [1] */
3863 FN_SD1_CMD, FN_REMOCON_B,
3864 /* IP13_21_19 [3] */
3865 FN_SD0_WP, FN_MMC_D7_B, FN_SIM0_D_B, FN_CAN0_TX_F,
3866 FN_SCIFA5_RXD_B, FN_RX3_C,
3867 0, 0,
3868 /* IP13_18_16 [3] */
3869 FN_SD0_CD, FN_MMC_D6_B, FN_SIM0_RST_B, FN_CAN0_RX_F,
3870 FN_SCIFA5_TXD_B, FN_TX3_C,
3871 0, 0,
3872 /* IP13_15 [1] */
3873 FN_SD0_DATA3, FN_SSL_B,
3874 /* IP13_14 [1] */
3875 FN_SD0_DATA2, FN_IO3_B,
3876 /* IP13_13 [1] */
3877 FN_SD0_DATA1, FN_IO2_B,
3878 /* IP13_12 [1] */
3879 FN_SD0_DATA0, FN_MISO_IO1_B,
3880 /* IP13_11 [1] */
3881 FN_SD0_CMD, FN_MOSI_IO0_B,
3882 /* IP13_10 [1] */
3883 FN_SD0_CLK, FN_SPCLK_B,
3884 /* IP13_9_7 [3] */
3885 FN_STP_OPWM_0, FN_AVB_GTX_CLK, FN_PWM0_B,
3886 FN_ADICHS2_B, FN_MSIOF0_TXD_C,
3887 0, 0, 0,
3888 /* IP13_6_5 [2] */
3889 FN_STP_ISSYNC_0, FN_AVB_COL, FN_ADICHS1_B, FN_MSIOF0_RXD_C,
3890 /* IP13_4_3 [2] */
3891 FN_STP_ISEN_0, FN_AVB_TX_CLK, FN_ADICHS0_B, FN_MSIOF0_SS2_C,
3892 /* IP13_2_0 [3] */
3893 FN_STP_ISD_0, FN_AVB_TX_ER, FN_SCIFB2_SCK_C,
3894 FN_ADICLK_B, FN_MSIOF0_SS1_C,
3895 0, 0, 0, }
3896 },
3897 { PINMUX_CFG_REG_VAR("IPSR14", 0xE6060058, 32,
3898 3, 3, 3, 3, 3, 3, 3, 3, 1, 1, 1, 1, 1, 1, 2) {
3899 /* IP14_31_29 [3] */
3900 FN_MSIOF0_SS2, FN_MMC_D7, FN_ADICHS2, FN_RX0_E,
3901 FN_VI1_VSYNC_N_C, FN_SDA7_C, FN_VI1_G5_B, 0,
3902 /* IP14_28_26 [3] */
3903 FN_MSIOF0_SS1, FN_MMC_D6, FN_ADICHS1, FN_TX0_E,
3904 FN_VI1_HSYNC_N_C, FN_SCL7_C, FN_VI1_G4_B, 0,
3905 /* IP14_25_23 [3] */
3906 FN_MSIOF0_RXD, FN_ADICHS0, 0, FN_VI1_DATA0_C, FN_VI1_G3_B,
3907 0, 0, 0,
3908 /* IP14_22_20 [3] */
3909 FN_MSIOF0_TXD, FN_ADICLK, 0, FN_VI1_FIELD_C, FN_VI1_G2_B,
3910 0, 0, 0,
3911 /* IP14_19_17 [3] */
3912 FN_MSIOF0_SYNC, FN_TX2_C, FN_ADICS_SAMP, 0,
3913 FN_VI1_CLKENB_C, FN_VI1_G1_B,
3914 0, 0,
3915 /* IP14_16_14 [3] */
3916 FN_MSIOF0_SCK, FN_RX2_C, FN_ADIDATA, 0,
3917 FN_VI1_CLK_C, FN_VI1_G0_B,
3918 0, 0,
3919 /* IP14_13_11 [3] */
3920 FN_SD2_WP, FN_MMC_D5, FN_SDA8_C, FN_RX5_B, FN_SCIFA5_RXD_C,
3921 0, 0, 0,
3922 /* IP14_10_8 [3] */
3923 FN_SD2_CD, FN_MMC_D4, FN_SCL8_C, FN_TX5_B, FN_SCIFA5_TXD_C,
3924 0, 0, 0,
3925 /* IP14_7 [1] */
3926 FN_SD2_DATA3, FN_MMC_D3,
3927 /* IP14_6 [1] */
3928 FN_SD2_DATA2, FN_MMC_D2,
3929 /* IP14_5 [1] */
3930 FN_SD2_DATA1, FN_MMC_D1,
3931 /* IP14_4 [1] */
3932 FN_SD2_DATA0, FN_MMC_D0,
3933 /* IP14_3 [1] */
3934 FN_SD2_CMD, FN_MMC_CMD,
3935 /* IP14_2 [1] */
3936 FN_SD2_CLK, FN_MMC_CLK,
3937 /* IP14_1_0 [2] */
3938 FN_SD1_WP, FN_PWM1_B, FN_SDA1_C, 0, }
3939 },
3940 { PINMUX_CFG_REG_VAR("IPSR15", 0xE606005C, 32,
3941 2, 3, 3, 3, 3, 3, 3, 3, 3, 2, 2, 2) {
3942 /* IP15_31_30 [2] */
3943 0, 0, 0, 0,
3944 /* IP15_29_27 [3] */
3945 FN_HTX0, FN_SCIFB0_TXD, 0, FN_GLO_SCLK_C,
3946 FN_CAN0_TX_B, FN_VI1_DATA5_C,
3947 0, 0,
3948 /* IP15_26_24 [3] */
3949 FN_HRX0, FN_SCIFB0_RXD, 0, FN_GLO_Q1_C,
3950 FN_CAN0_RX_B, FN_VI1_DATA4_C,
3951 0, 0,
3952 /* IP15_23_21 [3] */
3953 FN_HSCK0, FN_SCIFB0_SCK, 0, FN_GLO_Q0_C, FN_CAN_CLK,
3954 FN_TCLK2, FN_VI1_DATA3_C, 0,
3955 /* IP15_20_18 [3] */
3956 FN_HRTS0_N, FN_SCIFB0_RTS_N, 0, FN_GLO_I1_C, FN_VI1_DATA2_C,
3957 0, 0, 0,
3958 /* IP15_17_15 [3] */
3959 FN_HCTS0_N, FN_SCIFB0_CTS_N, 0, FN_GLO_I0_C,
3960 FN_TCLK1, FN_VI1_DATA1_C,
3961 0, 0,
3962 /* IP15_14_12 [3] */
3963 FN_GPS_MAG, FN_RX4_C, FN_SCIFA4_RXD_C, FN_PWM6,
3964 FN_VI1_G7_B, FN_SCIFA3_SCK_C,
3965 0, 0,
3966 /* IP15_11_9 [3] */
3967 FN_GPS_SIGN, FN_TX4_C, FN_SCIFA4_TXD_C, FN_PWM5,
3968 FN_VI1_G6_B, FN_SCIFA3_RXD_C,
3969 0, 0,
3970 /* IP15_8_6 [3] */
3971 FN_GPS_CLK, FN_DU1_DOTCLKIN_C, FN_AUDIO_CLKB_B,
3972 FN_PWM5_B, FN_SCIFA3_TXD_C,
3973 0, 0, 0,
3974 /* IP15_5_4 [2] */
3975 FN_SIM0_D, FN_IERX, FN_CAN1_RX_D, 0,
3976 /* IP15_3_2 [2] */
3977 FN_SIM0_CLK, FN_IECLK, FN_CAN_CLK_C, 0,
3978 /* IP15_1_0 [2] */
3979 FN_SIM0_RST, FN_IETX, FN_CAN1_TX_D, 0, }
3980 },
3981 { PINMUX_CFG_REG_VAR("IPSR16", 0xE6060160, 32,
3982 4, 4, 4, 4, 4, 2, 2, 2, 3, 3) {
3983 /* IP16_31_28 [4] */
3984 0, 0, 0, 0, 0, 0, 0, 0,
3985 0, 0, 0, 0, 0, 0, 0, 0,
3986 /* IP16_27_24 [4] */
3987 0, 0, 0, 0, 0, 0, 0, 0,
3988 0, 0, 0, 0, 0, 0, 0, 0,
3989 /* IP16_23_20 [4] */
3990 0, 0, 0, 0, 0, 0, 0, 0,
3991 0, 0, 0, 0, 0, 0, 0, 0,
3992 /* IP16_19_16 [4] */
3993 0, 0, 0, 0, 0, 0, 0, 0,
3994 0, 0, 0, 0, 0, 0, 0, 0,
3995 /* IP16_15_12 [4] */
3996 0, 0, 0, 0, 0, 0, 0, 0,
3997 0, 0, 0, 0, 0, 0, 0, 0,
3998 /* IP16_11_10 [2] */
3999 FN_HRTS1_N, FN_SCIFB1_RTS_N, FN_MLB_DAT, FN_CAN1_RX_B,
4000 /* IP16_9_8 [2] */
4001 FN_HCTS1_N, FN_SCIFB1_CTS_N, FN_MLB_SIG, FN_CAN1_TX_B,
4002 /* IP16_7_6 [2] */
4003 FN_HSCK1, FN_SCIFB1_SCK, FN_MLB_CK, FN_GLO_RFON_C,
4004 /* IP16_5_3 [3] */
4005 FN_HTX1, FN_SCIFB1_TXD, FN_VI1_R1_B,
4006 FN_GLO_SS_C, FN_VI1_DATA7_C,
4007 0, 0, 0,
4008 /* IP16_2_0 [3] */
4009 FN_HRX1, FN_SCIFB1_RXD, FN_VI1_R0_B,
4010 FN_GLO_SDATA_C, FN_VI1_DATA6_C,
4011 0, 0, 0, }
4012 },
4013 { PINMUX_CFG_REG_VAR("MOD_SEL", 0xE6060090, 32,
4014 1, 2, 2, 2, 3, 2, 1, 1, 1, 1,
4015 3, 2, 2, 2, 1, 2, 2, 2) {
4016 /* RESEVED [1] */
4017 0, 0,
4018 /* SEL_SCIF1 [2] */
4019 FN_SEL_SCIF1_0, FN_SEL_SCIF1_1, FN_SEL_SCIF1_2, FN_SEL_SCIF1_3,
4020 /* SEL_SCIFB [2] */
4021 FN_SEL_SCIFB_0, FN_SEL_SCIFB_1, FN_SEL_SCIFB_2, FN_SEL_SCIFB_3,
4022 /* SEL_SCIFB2 [2] */
4023 FN_SEL_SCIFB2_0, FN_SEL_SCIFB2_1,
4024 FN_SEL_SCIFB2_2, FN_SEL_SCIFB2_3,
4025 /* SEL_SCIFB1 [3] */
4026 FN_SEL_SCIFB1_0, FN_SEL_SCIFB1_1,
4027 FN_SEL_SCIFB1_2, FN_SEL_SCIFB1_3,
4028 0, 0, 0, 0,
4029 /* SEL_SCIFA1 [2] */
4030 FN_SEL_SCIFA1_0, FN_SEL_SCIFA1_1, FN_SEL_SCIFA1_2, 0,
4031 /* SEL_SSI9 [1] */
4032 FN_SEL_SSI9_0, FN_SEL_SSI9_1,
4033 /* SEL_SCFA [1] */
4034 FN_SEL_SCFA_0, FN_SEL_SCFA_1,
4035 /* SEL_QSP [1] */
4036 FN_SEL_QSP_0, FN_SEL_QSP_1,
4037 /* SEL_SSI7 [1] */
4038 FN_SEL_SSI7_0, FN_SEL_SSI7_1,
4039 /* SEL_HSCIF1 [3] */
4040 FN_SEL_HSCIF1_0, FN_SEL_HSCIF1_1, FN_SEL_HSCIF1_2,
4041 FN_SEL_HSCIF1_3, FN_SEL_HSCIF1_4,
4042 0, 0, 0,
4043 /* RESEVED [2] */
4044 0, 0, 0, 0,
4045 /* SEL_VI1 [2] */
4046 FN_SEL_VI1_0, FN_SEL_VI1_1, FN_SEL_VI1_2, 0,
4047 /* RESEVED [2] */
4048 0, 0, 0, 0,
4049 /* SEL_TMU [1] */
4050 FN_SEL_TMU1_0, FN_SEL_TMU1_1,
4051 /* SEL_LBS [2] */
4052 FN_SEL_LBS_0, FN_SEL_LBS_1, FN_SEL_LBS_2, FN_SEL_LBS_3,
4053 /* SEL_TSIF0 [2] */
4054 FN_SEL_TSIF0_0, FN_SEL_TSIF0_1, FN_SEL_TSIF0_2, FN_SEL_TSIF0_3,
4055 /* SEL_SOF0 [2] */
4056 FN_SEL_SOF0_0, FN_SEL_SOF0_1, FN_SEL_SOF0_2, 0, }
4057 },
4058 { PINMUX_CFG_REG_VAR("MOD_SEL2", 0xE6060094, 32,
4059 3, 1, 1, 3, 2, 1, 1, 2, 2,
4060 1, 3, 2, 1, 2, 2, 2, 1, 1, 1) {
4061 /* SEL_SCIF0 [3] */
4062 FN_SEL_SCIF0_0, FN_SEL_SCIF0_1, FN_SEL_SCIF0_2,
4063 FN_SEL_SCIF0_3, FN_SEL_SCIF0_4,
4064 0, 0, 0,
4065 /* RESEVED [1] */
4066 0, 0,
4067 /* SEL_SCIF [1] */
4068 FN_SEL_SCIF_0, FN_SEL_SCIF_1,
4069 /* SEL_CAN0 [3] */
4070 FN_SEL_CAN0_0, FN_SEL_CAN0_1, FN_SEL_CAN0_2, FN_SEL_CAN0_3,
4071 FN_SEL_CAN0_4, FN_SEL_CAN0_5,
4072 0, 0,
4073 /* SEL_CAN1 [2] */
4074 FN_SEL_CAN1_0, FN_SEL_CAN1_1, FN_SEL_CAN1_2, FN_SEL_CAN1_3,
4075 /* RESEVED [1] */
4076 0, 0,
4077 /* SEL_SCIFA2 [1] */
4078 FN_SEL_SCIFA2_0, FN_SEL_SCIFA2_1,
4079 /* SEL_SCIF4 [2] */
4080 FN_SEL_SCIF4_0, FN_SEL_SCIF4_1, FN_SEL_SCIF4_2, 0,
4081 /* RESEVED [2] */
4082 0, 0, 0, 0,
4083 /* SEL_ADG [1] */
4084 FN_SEL_ADG_0, FN_SEL_ADG_1,
4085 /* SEL_FM [3] */
4086 FN_SEL_FM_0, FN_SEL_FM_1, FN_SEL_FM_2,
4087 FN_SEL_FM_3, FN_SEL_FM_4,
4088 0, 0, 0,
4089 /* SEL_SCIFA5 [2] */
4090 FN_SEL_SCIFA5_0, FN_SEL_SCIFA5_1, FN_SEL_SCIFA5_2, 0,
4091 /* RESEVED [1] */
4092 0, 0,
4093 /* SEL_GPS [2] */
4094 FN_SEL_GPS_0, FN_SEL_GPS_1, FN_SEL_GPS_2, FN_SEL_GPS_3,
4095 /* SEL_SCIFA4 [2] */
4096 FN_SEL_SCIFA4_0, FN_SEL_SCIFA4_1, FN_SEL_SCIFA4_2, 0,
4097 /* SEL_SCIFA3 [2] */
4098 FN_SEL_SCIFA3_0, FN_SEL_SCIFA3_1, FN_SEL_SCIFA3_2, 0,
4099 /* SEL_SIM [1] */
4100 FN_SEL_SIM_0, FN_SEL_SIM_1,
4101 /* RESEVED [1] */
4102 0, 0,
4103 /* SEL_SSI8 [1] */
4104 FN_SEL_SSI8_0, FN_SEL_SSI8_1, }
4105 },
4106 { PINMUX_CFG_REG_VAR("MOD_SEL3", 0xE6060098, 32,
4107 2, 2, 2, 2, 2, 2, 2, 2,
4108 1, 1, 2, 2, 3, 2, 2, 2, 1) {
4109 /* SEL_HSCIF2 [2] */
4110 FN_SEL_HSCIF2_0, FN_SEL_HSCIF2_1,
4111 FN_SEL_HSCIF2_2, FN_SEL_HSCIF2_3,
4112 /* SEL_CANCLK [2] */
4113 FN_SEL_CANCLK_0, FN_SEL_CANCLK_1,
4114 FN_SEL_CANCLK_2, FN_SEL_CANCLK_3,
4115 /* SEL_IIC8 [2] */
4116 FN_SEL_IIC8_0, FN_SEL_IIC8_1, FN_SEL_IIC8_2, 0,
4117 /* SEL_IIC7 [2] */
4118 FN_SEL_IIC7_0, FN_SEL_IIC7_1, FN_SEL_IIC7_2, 0,
4119 /* SEL_IIC4 [2] */
4120 FN_SEL_IIC4_0, FN_SEL_IIC4_1, FN_SEL_IIC4_2, 0,
4121 /* SEL_IIC3 [2] */
4122 FN_SEL_IIC3_0, FN_SEL_IIC3_1, FN_SEL_IIC3_2, FN_SEL_IIC3_3,
4123 /* SEL_SCIF3 [2] */
4124 FN_SEL_SCIF3_0, FN_SEL_SCIF3_1, FN_SEL_SCIF3_2, FN_SEL_SCIF3_3,
4125 /* SEL_IEB [2] */
4126 FN_SEL_IEB_0, FN_SEL_IEB_1, FN_SEL_IEB_2,
4127 /* SEL_MMC [1] */
4128 FN_SEL_MMC_0, FN_SEL_MMC_1,
4129 /* SEL_SCIF5 [1] */
4130 FN_SEL_SCIF5_0, FN_SEL_SCIF5_1,
4131 /* RESEVED [2] */
4132 0, 0, 0, 0,
4133 /* SEL_IIC2 [2] */
4134 FN_SEL_IIC2_0, FN_SEL_IIC2_1, FN_SEL_IIC2_2, FN_SEL_IIC2_3,
4135 /* SEL_IIC1 [3] */
4136 FN_SEL_IIC1_0, FN_SEL_IIC1_1, FN_SEL_IIC1_2, FN_SEL_IIC1_3,
4137 FN_SEL_IIC1_4,
4138 0, 0, 0,
4139 /* SEL_IIC0 [2] */
4140 FN_SEL_IIC0_0, FN_SEL_IIC0_1, FN_SEL_IIC0_2, 0,
4141 /* RESEVED [2] */
4142 0, 0, 0, 0,
4143 /* RESEVED [2] */
4144 0, 0, 0, 0,
4145 /* RESEVED [1] */
4146 0, 0, }
4147 },
4148 { PINMUX_CFG_REG_VAR("MOD_SEL4", 0xE606009C, 32,
4149 3, 2, 2, 1, 1, 1, 1, 3, 2,
4150 2, 3, 1, 1, 1, 2, 2, 2, 2) {
4151 /* SEL_SOF1 [3] */
4152 FN_SEL_SOF1_0, FN_SEL_SOF1_1, FN_SEL_SOF1_2, FN_SEL_SOF1_3,
4153 FN_SEL_SOF1_4,
4154 0, 0, 0,
4155 /* SEL_HSCIF0 [2] */
4156 FN_SEL_HSCIF0_0, FN_SEL_HSCIF0_1, FN_SEL_HSCIF0_2, 0,
4157 /* SEL_DIS [2] */
4158 FN_SEL_DIS_0, FN_SEL_DIS_1, FN_SEL_DIS_2, 0,
4159 /* RESEVED [1] */
4160 0, 0,
4161 /* SEL_RAD [1] */
4162 FN_SEL_RAD_0, FN_SEL_RAD_1,
4163 /* SEL_RCN [1] */
4164 FN_SEL_RCN_0, FN_SEL_RCN_1,
4165 /* SEL_RSP [1] */
4166 FN_SEL_RSP_0, FN_SEL_RSP_1,
4167 /* SEL_SCIF2 [3] */
4168 FN_SEL_SCIF2_0, FN_SEL_SCIF2_1, FN_SEL_SCIF2_2,
4169 FN_SEL_SCIF2_3, FN_SEL_SCIF2_4,
4170 0, 0, 0,
4171 /* RESEVED [2] */
4172 0, 0, 0, 0,
4173 /* RESEVED [2] */
4174 0, 0, 0, 0,
4175 /* SEL_SOF2 [3] */
4176 FN_SEL_SOF2_0, FN_SEL_SOF2_1, FN_SEL_SOF2_2,
4177 FN_SEL_SOF2_3, FN_SEL_SOF2_4,
4178 0, 0, 0,
4179 /* RESEVED [1] */
4180 0, 0,
4181 /* SEL_SSI1 [1] */
4182 FN_SEL_SSI1_0, FN_SEL_SSI1_1,
4183 /* SEL_SSI0 [1] */
4184 FN_SEL_SSI0_0, FN_SEL_SSI0_1,
4185 /* SEL_SSP [2] */
4186 FN_SEL_SSP_0, FN_SEL_SSP_1, FN_SEL_SSP_2, 0,
4187 /* RESEVED [2] */
4188 0, 0, 0, 0,
4189 /* RESEVED [2] */
4190 0, 0, 0, 0,
4191 /* RESEVED [2] */
4192 0, 0, 0, 0, }
4193 },
4194 { },
4195};
4196
4197const struct sh_pfc_soc_info r8a7791_pinmux_info = {
4198 .name = "r8a77910_pfc",
4199 .unlock_reg = 0xe6060000, /* PMMR */
4200
4201 .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
4202
4203 .pins = pinmux_pins,
4204 .nr_pins = ARRAY_SIZE(pinmux_pins),
4205 .groups = pinmux_groups,
4206 .nr_groups = ARRAY_SIZE(pinmux_groups),
4207 .functions = pinmux_functions,
4208 .nr_functions = ARRAY_SIZE(pinmux_functions),
4209
4210 .cfg_regs = pinmux_config_regs,
4211
4212 .gpio_data = pinmux_data,
4213 .gpio_data_size = ARRAY_SIZE(pinmux_data),
4214};
generated by cgit v1.2.2 (git 2.25.0) at 2025-01-16 17:29:14 -0500