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authorLaurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>2012-12-15 17:51:36 -0500
committerSimon Horman <horms+renesas@verge.net.au>2013-01-24 19:24:27 -0500
commitac1ebc2190f575fce6685941f5eeecac808ba467 (patch)
tree3892cb73eb497b0b423a3d2b55bf0318cf9f5a6a /drivers/pinctrl
parent0ff25baba0386ce9de32b90b5116f1a14a4224b8 (diff)
sh-pfc: Add sh7734 pinmux support
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> Acked-by: Paul Mundt <lethal@linux-sh.org> Acked-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Diffstat (limited to 'drivers/pinctrl')
-rw-r--r--drivers/pinctrl/sh-pfc/Kconfig6
-rw-r--r--drivers/pinctrl/sh-pfc/Makefile1
-rw-r--r--drivers/pinctrl/sh-pfc/core.c3
-rw-r--r--drivers/pinctrl/sh-pfc/core.h1
-rw-r--r--drivers/pinctrl/sh-pfc/pfc-sh7734.c2474
5 files changed, 2485 insertions, 0 deletions
diff --git a/drivers/pinctrl/sh-pfc/Kconfig b/drivers/pinctrl/sh-pfc/Kconfig
index 77b1a3f41a25..2942f097dc38 100644
--- a/drivers/pinctrl/sh-pfc/Kconfig
+++ b/drivers/pinctrl/sh-pfc/Kconfig
@@ -83,4 +83,10 @@ config PINCTRL_PFC_SH7724
83 depends on GENERIC_GPIO 83 depends on GENERIC_GPIO
84 select PINCTRL_SH_PFC 84 select PINCTRL_SH_PFC
85 85
86config PINCTRL_PFC_SH7734
87 def_bool y
88 depends on CPU_SUBTYPE_SH7734
89 depends on GENERIC_GPIO
90 select PINCTRL_SH_PFC
91
86endif 92endif
diff --git a/drivers/pinctrl/sh-pfc/Makefile b/drivers/pinctrl/sh-pfc/Makefile
index 177f9e5d96a7..4ea3a4c15df6 100644
--- a/drivers/pinctrl/sh-pfc/Makefile
+++ b/drivers/pinctrl/sh-pfc/Makefile
@@ -14,3 +14,4 @@ obj-$(CONFIG_PINCTRL_PFC_SH7720) += pfc-sh7720.o
14obj-$(CONFIG_PINCTRL_PFC_SH7722) += pfc-sh7722.o 14obj-$(CONFIG_PINCTRL_PFC_SH7722) += pfc-sh7722.o
15obj-$(CONFIG_PINCTRL_PFC_SH7723) += pfc-sh7723.o 15obj-$(CONFIG_PINCTRL_PFC_SH7723) += pfc-sh7723.o
16obj-$(CONFIG_PINCTRL_PFC_SH7724) += pfc-sh7724.o 16obj-$(CONFIG_PINCTRL_PFC_SH7724) += pfc-sh7724.o
17obj-$(CONFIG_PINCTRL_PFC_SH7734) += pfc-sh7734.o
diff --git a/drivers/pinctrl/sh-pfc/core.c b/drivers/pinctrl/sh-pfc/core.c
index c1b2bf5460f1..a8af4a3df362 100644
--- a/drivers/pinctrl/sh-pfc/core.c
+++ b/drivers/pinctrl/sh-pfc/core.c
@@ -589,6 +589,9 @@ static const struct platform_device_id sh_pfc_id_table[] = {
589#ifdef CONFIG_PINCTRL_PFC_SH7724 589#ifdef CONFIG_PINCTRL_PFC_SH7724
590 { "pfc-sh7724", (kernel_ulong_t)&sh7724_pinmux_info }, 590 { "pfc-sh7724", (kernel_ulong_t)&sh7724_pinmux_info },
591#endif 591#endif
592#ifdef CONFIG_PINCTRL_PFC_SH7734
593 { "pfc-sh7734", (kernel_ulong_t)&sh7734_pinmux_info },
594#endif
592 { "sh-pfc", 0 }, 595 { "sh-pfc", 0 },
593 { }, 596 { },
594}; 597};
diff --git a/drivers/pinctrl/sh-pfc/core.h b/drivers/pinctrl/sh-pfc/core.h
index 7e05889feedc..54839d92de5d 100644
--- a/drivers/pinctrl/sh-pfc/core.h
+++ b/drivers/pinctrl/sh-pfc/core.h
@@ -62,5 +62,6 @@ extern struct sh_pfc_soc_info sh7720_pinmux_info;
62extern struct sh_pfc_soc_info sh7722_pinmux_info; 62extern struct sh_pfc_soc_info sh7722_pinmux_info;
63extern struct sh_pfc_soc_info sh7723_pinmux_info; 63extern struct sh_pfc_soc_info sh7723_pinmux_info;
64extern struct sh_pfc_soc_info sh7724_pinmux_info; 64extern struct sh_pfc_soc_info sh7724_pinmux_info;
65extern struct sh_pfc_soc_info sh7734_pinmux_info;
65 66
66#endif /* __SH_PFC_CORE_H__ */ 67#endif /* __SH_PFC_CORE_H__ */
diff --git a/drivers/pinctrl/sh-pfc/pfc-sh7734.c b/drivers/pinctrl/sh-pfc/pfc-sh7734.c
new file mode 100644
index 000000000000..cbb5f4c5f4b0
--- /dev/null
+++ b/drivers/pinctrl/sh-pfc/pfc-sh7734.c
@@ -0,0 +1,2474 @@
1/*
2 * SH7734 processor support - PFC hardware block
3 *
4 * Copyright (C) 2012 Renesas Solutions Corp.
5 * Copyright (C) 2012 Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
6 *
7 * This file is subject to the terms and conditions of the GNU General Public
8 * License. See the file "COPYING" in the main directory of this archive
9 * for more details.
10 */
11#include <linux/init.h>
12#include <linux/kernel.h>
13#include <linux/sh_pfc.h>
14#include <cpu/sh7734.h>
15
16#define CPU_32_PORT(fn, pfx, sfx) \
17 PORT_10(fn, pfx, sfx), PORT_10(fn, pfx##1, sfx), \
18 PORT_10(fn, pfx##2, sfx), PORT_1(fn, pfx##30, sfx), \
19 PORT_1(fn, pfx##31, sfx)
20
21#define CPU_32_PORT5(fn, pfx, sfx) \
22 PORT_1(fn, pfx##0, sfx), PORT_1(fn, pfx##1, sfx), \
23 PORT_1(fn, pfx##2, sfx), PORT_1(fn, pfx##3, sfx), \
24 PORT_1(fn, pfx##4, sfx), PORT_1(fn, pfx##5, sfx), \
25 PORT_1(fn, pfx##6, sfx), PORT_1(fn, pfx##7, sfx), \
26 PORT_1(fn, pfx##8, sfx), PORT_1(fn, pfx##9, sfx), \
27 PORT_1(fn, pfx##10, sfx), PORT_1(fn, pfx##11, sfx)
28
29/* GPSR0 - GPSR5 */
30#define CPU_ALL_PORT(fn, pfx, sfx) \
31 CPU_32_PORT(fn, pfx##_0_, sfx), \
32 CPU_32_PORT(fn, pfx##_1_, sfx), \
33 CPU_32_PORT(fn, pfx##_2_, sfx), \
34 CPU_32_PORT(fn, pfx##_3_, sfx), \
35 CPU_32_PORT(fn, pfx##_4_, sfx), \
36 CPU_32_PORT5(fn, pfx##_5_, sfx)
37
38#define _GP_GPIO(pfx, sfx) PINMUX_GPIO(GPIO_GP##pfx, GP##pfx##_DATA)
39#define _GP_DATA(pfx, sfx) PINMUX_DATA(GP##pfx##_DATA, GP##pfx##_FN, \
40 GP##pfx##_IN, GP##pfx##_OUT)
41
42#define _GP_INOUTSEL(pfx, sfx) GP##pfx##_IN, GP##pfx##_OUT
43#define _GP_INDT(pfx, sfx) GP##pfx##_DATA
44
45#define GP_ALL(str) CPU_ALL_PORT(_PORT_ALL, GP, str)
46#define PINMUX_GPIO_GP_ALL() CPU_ALL_PORT(_GP_GPIO, , unused)
47#define PINMUX_DATA_GP_ALL() CPU_ALL_PORT(_GP_DATA, , unused)
48
49#define PORT_10_REV(fn, pfx, sfx) \
50 PORT_1(fn, pfx##9, sfx), PORT_1(fn, pfx##8, sfx), \
51 PORT_1(fn, pfx##7, sfx), PORT_1(fn, pfx##6, sfx), \
52 PORT_1(fn, pfx##5, sfx), PORT_1(fn, pfx##4, sfx), \
53 PORT_1(fn, pfx##3, sfx), PORT_1(fn, pfx##2, sfx), \
54 PORT_1(fn, pfx##1, sfx), PORT_1(fn, pfx##0, sfx)
55
56#define CPU_32_PORT_REV(fn, pfx, sfx) \
57 PORT_1(fn, pfx##31, sfx), PORT_1(fn, pfx##30, sfx), \
58 PORT_10_REV(fn, pfx##2, sfx), PORT_10_REV(fn, pfx##1, sfx), \
59 PORT_10_REV(fn, pfx, sfx)
60
61#define GP_INOUTSEL(bank) CPU_32_PORT_REV(_GP_INOUTSEL, _##bank##_, unused)
62#define GP_INDT(bank) CPU_32_PORT_REV(_GP_INDT, _##bank##_, unused)
63
64#define PINMUX_IPSR_DATA(ipsr, fn) PINMUX_DATA(fn##_MARK, FN_##ipsr, FN_##fn)
65#define PINMUX_IPSR_MODSEL_DATA(ipsr, fn, ms) PINMUX_DATA(fn##_MARK, FN_##ms, \
66 FN_##ipsr, FN_##fn)
67
68enum {
69 PINMUX_RESERVED = 0,
70
71 PINMUX_DATA_BEGIN,
72 GP_ALL(DATA), /* GP_0_0_DATA -> GP_5_11_DATA */
73 PINMUX_DATA_END,
74
75 PINMUX_INPUT_BEGIN,
76 GP_ALL(IN), /* GP_0_0_IN -> GP_5_11_IN */
77 PINMUX_INPUT_END,
78
79 PINMUX_OUTPUT_BEGIN,
80 GP_ALL(OUT), /* GP_0_0_OUT -> GP_5_11_OUT */
81 PINMUX_OUTPUT_END,
82
83 PINMUX_FUNCTION_BEGIN,
84 GP_ALL(FN), /* GP_0_0_FN -> GP_5_11_FN */
85
86 /* GPSR0 */
87 FN_IP1_9_8, FN_IP1_11_10, FN_IP1_13_12, FN_IP1_15_14,
88 FN_IP0_7_6, FN_IP0_9_8, FN_IP0_11_10, FN_IP0_13_12,
89 FN_IP0_15_14, FN_IP0_17_16, FN_IP0_19_18, FN_IP0_21_20,
90 FN_IP0_23_22, FN_IP0_25_24, FN_IP0_27_26, FN_IP0_29_28,
91 FN_IP0_31_30, FN_IP1_1_0, FN_IP1_3_2, FN_IP1_5_4,
92 FN_IP1_7_6, FN_IP11_28, FN_IP0_1_0, FN_IP0_3_2,
93 FN_IP0_5_4, FN_IP1_17_16, FN_IP1_19_18, FN_IP1_22_20,
94 FN_IP1_25_23, FN_IP1_28_26, FN_IP1_31_29, FN_IP2_2_0,
95
96 /* GPSR1 */
97 FN_IP3_20, FN_IP3_29_27, FN_IP11_20_19, FN_IP11_22_21,
98 FN_IP2_16_14, FN_IP2_19_17, FN_IP2_22_20, FN_IP2_24_23,
99 FN_IP2_27_25, FN_IP2_30_28, FN_IP3_1_0, FN_CLKOUT,
100 FN_BS, FN_CS0, FN_IP3_2, FN_EX_CS0,
101 FN_IP3_5_3, FN_IP3_8_6, FN_IP3_11_9, FN_IP3_14_12,
102 FN_IP3_17_15, FN_RD, FN_IP3_19_18, FN_WE0,
103 FN_WE1, FN_IP2_4_3, FN_IP3_23_21, FN_IP3_26_24,
104 FN_IP2_7_5, FN_IP2_10_8, FN_IP2_13_11, FN_IP11_25_23,
105
106 /* GPSR2 */
107 FN_IP11_6_4, FN_IP11_9_7, FN_IP11_11_10, FN_IP4_2_0,
108 FN_IP8_29_28, FN_IP11_27_26, FN_IP8_22_20, FN_IP8_25_23,
109 FN_IP11_12, FN_IP8_27_26, FN_IP4_5_3, FN_IP4_8_6,
110 FN_IP4_11_9, FN_IP4_14_12, FN_IP4_17_15, FN_IP4_19_18,
111 FN_IP4_21_20, FN_IP4_23_22, FN_IP4_25_24, FN_IP4_27_26,
112 FN_IP4_29_28, FN_IP4_31_30, FN_IP5_2_0, FN_IP5_5_3,
113 FN_IP5_8_6, FN_IP5_11_9, FN_IP5_14_12, FN_IP5_17_15,
114 FN_IP5_20_18, FN_IP5_22_21, FN_IP5_24_23, FN_IP5_26_25,
115
116 /* GPSR3 */
117 FN_IP6_2_0, FN_IP6_5_3, FN_IP6_7_6, FN_IP6_9_8,
118 FN_IP6_11_10, FN_IP6_13_12, FN_IP6_15_14, FN_IP6_17_16,
119 FN_IP6_20_18, FN_IP6_23_21, FN_IP7_2_0, FN_IP7_5_3,
120 FN_IP7_8_6, FN_IP7_11_9, FN_IP7_14_12, FN_IP7_17_15,
121 FN_IP7_20_18, FN_IP7_23_21, FN_IP7_26_24, FN_IP7_28_27,
122 FN_IP7_30_29, FN_IP8_1_0, FN_IP8_3_2, FN_IP8_5_4,
123 FN_IP8_7_6, FN_IP8_9_8, FN_IP8_11_10, FN_IP8_13_12,
124 FN_IP8_15_14, FN_IP8_17_16, FN_IP8_19_18, FN_IP9_1_0,
125
126 /* GPSR4 */
127 FN_IP9_19_18, FN_IP9_21_20, FN_IP9_23_22, FN_IP9_25_24,
128 FN_IP9_11_10, FN_IP9_13_12, FN_IP9_15_14, FN_IP9_17_16,
129 FN_IP9_3_2, FN_IP9_5_4, FN_IP9_7_6, FN_IP9_9_8,
130 FN_IP9_27_26, FN_IP9_29_28, FN_IP10_2_0, FN_IP10_5_3,
131 FN_IP10_8_6, FN_IP10_11_9, FN_IP10_14_12, FN_IP10_15,
132 FN_IP10_18_16, FN_IP10_21_19, FN_IP11_0, FN_IP11_1,
133 FN_SCL0, FN_IP11_2, FN_PENC0, FN_IP11_15_13, /* Need check*/
134 FN_USB_OVC0, FN_IP11_18_16,
135 FN_IP10_22, FN_IP10_24_23,
136
137 /* GPSR5 */
138 FN_IP10_25, FN_IP11_3, FN_IRQ2_B, FN_IRQ3_B,
139 FN_IP10_27_26, /* 10 */
140 FN_IP10_29_28, /* 11 */
141
142 /* IPSR0 */
143 FN_A15, FN_ST0_VCO_CLKIN, FN_LCD_DATA15_A, FN_TIOC3D_C,
144 FN_A14, FN_LCD_DATA14_A, FN_TIOC3C_C,
145 FN_A13, FN_LCD_DATA13_A, FN_TIOC3B_C,
146 FN_A12, FN_LCD_DATA12_A, FN_TIOC3A_C,
147 FN_A11, FN_ST0_D7, FN_LCD_DATA11_A, FN_TIOC2B_C,
148 FN_A10, FN_ST0_D6, FN_LCD_DATA10_A, FN_TIOC2A_C,
149 FN_A9, FN_ST0_D5, FN_LCD_DATA9_A, FN_TIOC1B_C,
150 FN_A8, FN_ST0_D4, FN_LCD_DATA8_A, FN_TIOC1A_C,
151 FN_A7, FN_ST0_D3, FN_LCD_DATA7_A, FN_TIOC0D_C,
152 FN_A6, FN_ST0_D2, FN_LCD_DATA6_A, FN_TIOC0C_C,
153 FN_A5, FN_ST0_D1, FN_LCD_DATA5_A, FN_TIOC0B_C,
154 FN_A4, FN_ST0_D0, FN_LCD_DATA4_A, FN_TIOC0A_C,
155 FN_A3, FN_ST0_VLD, FN_LCD_DATA3_A, FN_TCLKD_C,
156 FN_A2, FN_ST0_SYC, FN_LCD_DATA2_A, FN_TCLKC_C,
157 FN_A1, FN_ST0_REQ, FN_LCD_DATA1_A, FN_TCLKB_C,
158 FN_A0, FN_ST0_CLKIN, FN_LCD_DATA0_A, FN_TCLKA_C,
159
160 /* IPSR1 */
161 FN_D3, FN_SD0_DAT3_A, FN_MMC_D3_A, FN_ST1_D6, FN_FD3_A,
162 FN_D2, FN_SD0_DAT2_A, FN_MMC_D2_A, FN_ST1_D5, FN_FD2_A,
163 FN_D1, FN_SD0_DAT1_A, FN_MMC_D1_A, FN_ST1_D4, FN_FD1_A,
164 FN_D0, FN_SD0_DAT0_A, FN_MMC_D0_A, FN_ST1_D3, FN_FD0_A,
165 FN_A25, FN_TX2_D, FN_ST1_D2,
166 FN_A24, FN_RX2_D, FN_ST1_D1,
167 FN_A23, FN_ST1_D0, FN_LCD_M_DISP_A,
168 FN_A22, FN_ST1_VLD, FN_LCD_VEPWC_A,
169 FN_A21, FN_ST1_SYC, FN_LCD_VCPWC_A,
170 FN_A20, FN_ST1_REQ, FN_LCD_FLM_A,
171 FN_A19, FN_ST1_CLKIN, FN_LCD_CLK_A, FN_TIOC4D_C,
172 FN_A18, FN_ST1_PWM, FN_LCD_CL2_A, FN_TIOC4C_C,
173 FN_A17, FN_ST1_VCO_CLKIN, FN_LCD_CL1_A, FN_TIOC4B_C,
174 FN_A16, FN_ST0_PWM, FN_LCD_DON_A, FN_TIOC4A_C,
175
176 /* IPSR2 */
177 FN_D14, FN_TX2_B, FN_FSE_A, FN_ET0_TX_CLK_B,
178 FN_D13, FN_RX2_B, FN_FRB_A, FN_ET0_ETXD6_B,
179 FN_D12, FN_FWE_A, FN_ET0_ETXD5_B,
180 FN_D11, FN_RSPI_MISO_A, FN_QMI_QIO1_A, FN_FRE_A,
181 FN_ET0_ETXD3_B,
182 FN_D10, FN_RSPI_MOSI_A, FN_QMO_QIO0_A, FN_FALE_A,
183 FN_ET0_ETXD2_B,
184 FN_D9, FN_SD0_CMD_A, FN_MMC_CMD_A, FN_QIO3_A, FN_FCLE_A,
185 FN_ET0_ETXD1_B,
186 FN_D8, FN_SD0_CLK_A, FN_MMC_CLK_A, FN_QIO2_A, FN_FCE_A,
187 FN_ET0_GTX_CLK_B,
188 FN_D7, FN_RSPI_SSL_A, FN_MMC_D7_A, FN_QSSL_A, FN_FD7_A,
189 FN_D6, FN_RSPI_RSPCK_A, FN_MMC_D6_A, FN_QSPCLK_A, FN_FD6_A,
190 FN_D5, FN_SD0_WP_A, FN_MMC_D5_A, FN_FD5_A,
191 FN_D4, FN_SD0_CD_A, FN_MMC_D4_A, FN_ST1_D7, FN_FD4_A,
192
193 /* IPSR3 */
194 FN_DRACK0, FN_SD1_DAT2_A, FN_ATAG, FN_TCLK1_A, FN_ET0_ETXD7,
195 FN_EX_WAIT2, FN_SD1_DAT1_A, FN_DACK2, FN_CAN1_RX_C,
196 FN_ET0_MAGIC_C, FN_ET0_ETXD6_A,
197 FN_EX_WAIT1, FN_SD1_DAT0_A, FN_DREQ2, FN_CAN1_TX_C,
198 FN_ET0_LINK_C, FN_ET0_ETXD5_A,
199 FN_EX_WAIT0, FN_TCLK1_B,
200 FN_RD_WR, FN_TCLK0, FN_CAN_CLK_B, FN_ET0_ETXD4,
201 FN_EX_CS5, FN_SD1_CMD_A, FN_ATADIR, FN_QSSL_B, FN_ET0_ETXD3_A,
202 FN_EX_CS4, FN_SD1_WP_A, FN_ATAWR, FN_QMI_QIO1_B, FN_ET0_ETXD2_A,
203 FN_EX_CS3, FN_SD1_CD_A, FN_ATARD, FN_QMO_QIO0_B, FN_ET0_ETXD1_A,
204 FN_EX_CS2, FN_TX3_B, FN_ATACS1, FN_QSPCLK_B, FN_ET0_GTX_CLK_A,
205 FN_EX_CS1, FN_RX3_B, FN_ATACS0, FN_QIO2_B, FN_ET0_ETXD0,
206 FN_CS1_A26, FN_QIO3_B,
207 FN_D15, FN_SCK2_B,
208
209 /* IPSR4 */
210 FN_SCK2_A, FN_VI0_G3,
211 FN_RTS1_B, FN_VI0_G2,
212 FN_CTS1_B, FN_VI0_DATA7_VI0_G1,
213 FN_TX1_B, FN_VI0_DATA6_VI0_G0, FN_ET0_PHY_INT_A,
214 FN_RX1_B, FN_VI0_DATA5_VI0_B5, FN_ET0_MAGIC_A,
215 FN_SCK1_B, FN_VI0_DATA4_VI0_B4, FN_ET0_LINK_A,
216 FN_RTS0_B, FN_VI0_DATA3_VI0_B3, FN_ET0_MDIO_A,
217 FN_CTS0_B, FN_VI0_DATA2_VI0_B2, FN_RMII0_MDIO_A, FN_ET0_MDC,
218 FN_HTX0_A, FN_TX1_A, FN_VI0_DATA1_VI0_B1, FN_RMII0_MDC_A, FN_ET0_COL,
219 FN_HRX0_A, FN_RX1_A, FN_VI0_DATA0_VI0_B0, FN_RMII0_CRS_DV_A, FN_ET0_CRS,
220 FN_HSCK0_A, FN_SCK1_A, FN_VI0_VSYNC, FN_RMII0_RX_ER_A, FN_ET0_RX_ER,
221 FN_HRTS0_A, FN_RTS1_A, FN_VI0_HSYNC, FN_RMII0_TXD_EN_A, FN_ET0_RX_DV,
222 FN_HCTS0_A, FN_CTS1_A, FN_VI0_FIELD, FN_RMII0_RXD1_A, FN_ET0_ERXD7,
223
224 /* IPSR5 */
225 FN_SD2_CLK_A, FN_RX2_A, FN_VI0_G4, FN_ET0_RX_CLK_B,
226 FN_SD2_CMD_A, FN_TX2_A, FN_VI0_G5, FN_ET0_ERXD2_B,
227 FN_SD2_DAT0_A, FN_RX3_A, FN_VI0_R0, FN_ET0_ERXD3_B,
228 FN_SD2_DAT1_A, FN_TX3_A, FN_VI0_R1, FN_ET0_MDIO_B,
229 FN_SD2_DAT2_A, FN_RX4_A, FN_VI0_R2, FN_ET0_LINK_B,
230 FN_SD2_DAT3_A, FN_TX4_A, FN_VI0_R3, FN_ET0_MAGIC_B,
231 FN_SD2_CD_A, FN_RX5_A, FN_VI0_R4, FN_ET0_PHY_INT_B,
232 FN_SD2_WP_A, FN_TX5_A, FN_VI0_R5,
233 FN_REF125CK, FN_ADTRG, FN_RX5_C,
234 FN_REF50CK, FN_CTS1_E, FN_HCTS0_D,
235
236 /* IPSR6 */
237 FN_DU0_DR0, FN_SCIF_CLK_B, FN_HRX0_D, FN_IETX_A, FN_TCLKA_A, FN_HIFD00,
238 FN_DU0_DR1, FN_SCK0_B, FN_HTX0_D, FN_IERX_A, FN_TCLKB_A, FN_HIFD01,
239 FN_DU0_DR2, FN_RX0_B, FN_TCLKC_A, FN_HIFD02,
240 FN_DU0_DR3, FN_TX0_B, FN_TCLKD_A, FN_HIFD03,
241 FN_DU0_DR4, FN_CTS0_C, FN_TIOC0A_A, FN_HIFD04,
242 FN_DU0_DR5, FN_RTS0_C, FN_TIOC0B_A, FN_HIFD05,
243 FN_DU0_DR6, FN_SCK1_C, FN_TIOC0C_A, FN_HIFD06,
244 FN_DU0_DR7, FN_RX1_C, FN_TIOC0D_A, FN_HIFD07,
245 FN_DU0_DG0, FN_TX1_C, FN_HSCK0_D, FN_IECLK_A, FN_TIOC1A_A, FN_HIFD08,
246 FN_DU0_DG1, FN_CTS1_C, FN_HRTS0_D, FN_TIOC1B_A, FN_HIFD09,
247
248 /* IPSR7 */
249 FN_DU0_DG2, FN_RTS1_C, FN_RMII0_MDC_B, FN_TIOC2A_A, FN_HIFD10,
250 FN_DU0_DG3, FN_SCK2_C, FN_RMII0_MDIO_B, FN_TIOC2B_A, FN_HIFD11,
251 FN_DU0_DG4, FN_RX2_C, FN_RMII0_CRS_DV_B, FN_TIOC3A_A, FN_HIFD12,
252 FN_DU0_DG5, FN_TX2_C, FN_RMII0_RX_ER_B, FN_TIOC3B_A, FN_HIFD13,
253 FN_DU0_DG6, FN_RX3_C, FN_RMII0_RXD0_B, FN_TIOC3C_A, FN_HIFD14,
254 FN_DU0_DG7, FN_TX3_C, FN_RMII0_RXD1_B, FN_TIOC3D_A, FN_HIFD15,
255 FN_DU0_DB0, FN_RX4_C, FN_RMII0_TXD_EN_B, FN_TIOC4A_A, FN_HIFCS,
256 FN_DU0_DB1, FN_TX4_C, FN_RMII0_TXD0_B, FN_TIOC4B_A, FN_HIFRS,
257 FN_DU0_DB2, FN_RX5_B, FN_RMII0_TXD1_B, FN_TIOC4C_A, FN_HIFWR,
258 FN_DU0_DB3, FN_TX5_B, FN_TIOC4D_A, FN_HIFRD,
259 FN_DU0_DB4, FN_HIFINT,
260
261 /* IPSR8 */
262 FN_DU0_DB5, FN_HIFDREQ,
263 FN_DU0_DB6, FN_HIFRDY,
264 FN_DU0_DB7, FN_SSI_SCK0_B, FN_HIFEBL_B,
265 FN_DU0_DOTCLKIN, FN_HSPI_CS0_C, FN_SSI_WS0_B,
266 FN_DU0_DOTCLKOUT, FN_HSPI_CLK0_C, FN_SSI_SDATA0_B,
267 FN_DU0_EXHSYNC_DU0_HSYNC, FN_HSPI_TX0_C, FN_SSI_SCK1_B,
268 FN_DU0_EXVSYNC_DU0_VSYNC, FN_HSPI_RX0_C, FN_SSI_WS1_B,
269 FN_DU0_EXODDF_DU0_ODDF, FN_CAN0_RX_B, FN_HSCK0_B, FN_SSI_SDATA1_B,
270 FN_DU0_DISP, FN_CAN0_TX_B, FN_HRX0_B, FN_AUDIO_CLKA_B,
271 FN_DU0_CDE, FN_HTX0_B, FN_AUDIO_CLKB_B, FN_LCD_VCPWC_B,
272 FN_IRQ0_A, FN_HSPI_TX_B, FN_RX3_E, FN_ET0_ERXD0,
273 FN_IRQ1_A, FN_HSPI_RX_B, FN_TX3_E, FN_ET0_ERXD1,
274 FN_IRQ2_A, FN_CTS0_A, FN_HCTS0_B, FN_ET0_ERXD2_A,
275 FN_IRQ3_A, FN_RTS0_A, FN_HRTS0_B, FN_ET0_ERXD3_A,
276
277 /* IPSR9 */
278 FN_VI1_CLK_A, FN_FD0_B, FN_LCD_DATA0_B,
279 FN_VI1_0_A, FN_FD1_B, FN_LCD_DATA1_B,
280 FN_VI1_1_A, FN_FD2_B, FN_LCD_DATA2_B,
281 FN_VI1_2_A, FN_FD3_B, FN_LCD_DATA3_B,
282 FN_VI1_3_A, FN_FD4_B, FN_LCD_DATA4_B,
283 FN_VI1_4_A, FN_FD5_B, FN_LCD_DATA5_B,
284 FN_VI1_5_A, FN_FD6_B, FN_LCD_DATA6_B,
285 FN_VI1_6_A, FN_FD7_B, FN_LCD_DATA7_B,
286 FN_VI1_7_A, FN_FCE_B, FN_LCD_DATA8_B,
287 FN_SSI_SCK0_A, FN_TIOC1A_B, FN_LCD_DATA9_B,
288 FN_SSI_WS0_A, FN_TIOC1B_B, FN_LCD_DATA10_B,
289 FN_SSI_SDATA0_A, FN_VI1_0_B, FN_TIOC2A_B, FN_LCD_DATA11_B,
290 FN_SSI_SCK1_A, FN_VI1_1_B, FN_TIOC2B_B, FN_LCD_DATA12_B,
291 FN_SSI_WS1_A, FN_VI1_2_B, FN_LCD_DATA13_B,
292 FN_SSI_SDATA1_A, FN_VI1_3_B, FN_LCD_DATA14_B,
293
294 /* IPSR10 */
295 FN_SSI_SCK23, FN_VI1_4_B, FN_RX1_D, FN_FCLE_B, FN_LCD_DATA15_B,
296 FN_SSI_WS23, FN_VI1_5_B, FN_TX1_D, FN_HSCK0_C, FN_FALE_B, FN_LCD_DON_B,
297 FN_SSI_SDATA2, FN_VI1_6_B, FN_HRX0_C, FN_FRE_B, FN_LCD_CL1_B,
298 FN_SSI_SDATA3, FN_VI1_7_B, FN_HTX0_C, FN_FWE_B, FN_LCD_CL2_B,
299 FN_AUDIO_CLKA_A, FN_VI1_CLK_B, FN_SCK1_D, FN_IECLK_B, FN_LCD_FLM_B,
300 FN_AUDIO_CLKB_A, FN_LCD_CLK_B,
301 FN_AUDIO_CLKC, FN_SCK1_E, FN_HCTS0_C, FN_FRB_B, FN_LCD_VEPWC_B,
302 FN_AUDIO_CLKOUT, FN_TX1_E, FN_HRTS0_C, FN_FSE_B, FN_LCD_M_DISP_B,
303 FN_CAN_CLK_A, FN_RX4_D,
304 FN_CAN0_TX_A, FN_TX4_D, FN_MLB_CLK,
305 FN_CAN1_RX_A, FN_IRQ1_B,
306 FN_CAN0_RX_A, FN_IRQ0_B, FN_MLB_SIG,
307 FN_CAN1_TX_A, FN_TX5_C, FN_MLB_DAT,
308
309 /* IPSR11 */
310 FN_SCL1, FN_SCIF_CLK_C,
311 FN_SDA1, FN_RX1_E,
312 FN_SDA0, FN_HIFEBL_A,
313 FN_SDSELF, FN_RTS1_E,
314 FN_SCIF_CLK_A, FN_HSPI_CLK_A, FN_VI0_CLK, FN_RMII0_TXD0_A, FN_ET0_ERXD4,
315 FN_SCK0_A, FN_HSPI_CS_A, FN_VI0_CLKENB, FN_RMII0_TXD1_A, FN_ET0_ERXD5,
316 FN_RX0_A, FN_HSPI_RX_A, FN_RMII0_RXD0_A, FN_ET0_ERXD6,
317 FN_TX0_A, FN_HSPI_TX_A,
318 FN_PENC1, FN_TX3_D, FN_CAN1_TX_B, FN_TX5_D, FN_IETX_B,
319 FN_USB_OVC1, FN_RX3_D, FN_CAN1_RX_B, FN_RX5_D, FN_IERX_B,
320 FN_DREQ0, FN_SD1_CLK_A, FN_ET0_TX_EN,
321 FN_DACK0, FN_SD1_DAT3_A, FN_ET0_TX_ER,
322 FN_DREQ1, FN_HSPI_CLK_B, FN_RX4_B, FN_ET0_PHY_INT_C, FN_ET0_TX_CLK_A,
323 FN_DACK1, FN_HSPI_CS_B, FN_TX4_B, FN_ET0_RX_CLK_A,
324 FN_PRESETOUT, FN_ST_CLKOUT,
325
326 /* MOD_SEL1 */
327 FN_SEL_IEBUS_0, FN_SEL_IEBUS_1,
328 FN_SEL_RQSPI_0, FN_SEL_RQSPI_1,
329 FN_SEL_VIN1_0, FN_SEL_VIN1_1,
330 FN_SEL_HIF_0, FN_SEL_HIF_1,
331 FN_SEL_RSPI_0, FN_SEL_RSPI_1,
332 FN_SEL_LCDC_0, FN_SEL_LCDC_1,
333 FN_SEL_ET0_CTL_0, FN_SEL_ET0_CTL_1, FN_SEL_ET0_CTL_2,
334 FN_SEL_ET0_0, FN_SEL_ET0_1,
335 FN_SEL_RMII_0, FN_SEL_RMII_1,
336 FN_SEL_TMU_0, FN_SEL_TMU_1,
337 FN_SEL_HSPI_0, FN_SEL_HSPI_1, FN_SEL_HSPI_2,
338 FN_SEL_HSCIF_0, FN_SEL_HSCIF_1, FN_SEL_HSCIF_2, FN_SEL_HSCIF_3,
339 FN_SEL_RCAN_CLK_0, FN_SEL_RCAN_CLK_1,
340 FN_SEL_RCAN1_0, FN_SEL_RCAN1_1, FN_SEL_RCAN1_2,
341 FN_SEL_RCAN0_0, FN_SEL_RCAN0_1,
342 FN_SEL_SDHI2_0, FN_SEL_SDHI2_1,
343 FN_SEL_SDHI1_0, FN_SEL_SDHI1_1,
344 FN_SEL_SDHI0_0, FN_SEL_SDHI0_1,
345 FN_SEL_SSI1_0, FN_SEL_SSI1_1,
346 FN_SEL_SSI0_0, FN_SEL_SSI0_1,
347 FN_SEL_AUDIO_CLKB_0, FN_SEL_AUDIO_CLKB_1,
348 FN_SEL_AUDIO_CLKA_0, FN_SEL_AUDIO_CLKA_1,
349 FN_SEL_FLCTL_0, FN_SEL_FLCTL_1,
350 FN_SEL_MMC_0, FN_SEL_MMC_1,
351 FN_SEL_INTC_0, FN_SEL_INTC_1,
352
353 /* MOD_SEL2 */
354 FN_SEL_MTU2_CLK_0, FN_SEL_MTU2_CLK_1,
355 FN_SEL_MTU2_CH4_0, FN_SEL_MTU2_CH4_1,
356 FN_SEL_MTU2_CH3_0, FN_SEL_MTU2_CH3_1,
357 FN_SEL_MTU2_CH2_0, FN_SEL_MTU2_CH2_1, FN_SEL_MTU2_CH2_2,
358 FN_SEL_MTU2_CH1_0, FN_SEL_MTU2_CH1_1, FN_SEL_MTU2_CH1_2,
359 FN_SEL_MTU2_CH0_0, FN_SEL_MTU2_CH0_1,
360 FN_SEL_SCIF5_0, FN_SEL_SCIF5_1,
361 FN_SEL_SCIF5_2, FN_SEL_SCIF5_3,
362 FN_SEL_SCIF4_0, FN_SEL_SCIF4_1,
363 FN_SEL_SCIF4_2, FN_SEL_SCIF4_3,
364 FN_SEL_SCIF3_0, FN_SEL_SCIF3_1, FN_SEL_SCIF3_2,
365 FN_SEL_SCIF3_3, FN_SEL_SCIF3_4,
366 FN_SEL_SCIF2_0, FN_SEL_SCIF2_1, FN_SEL_SCIF2_2,
367 FN_SEL_SCIF2_3,
368 FN_SEL_SCIF1_0, FN_SEL_SCIF1_1, FN_SEL_SCIF1_2,
369 FN_SEL_SCIF1_3, FN_SEL_SCIF1_4,
370 FN_SEL_SCIF0_0, FN_SEL_SCIF0_1, FN_SEL_SCIF0_2,
371 FN_SEL_SCIF_CLK_0, FN_SEL_SCIF_CLK_1, FN_SEL_SCIF_CLK_2,
372
373 PINMUX_FUNCTION_END,
374
375 PINMUX_MARK_BEGIN,
376
377 CLKOUT_MARK, BS_MARK, CS0_MARK, EX_CS0_MARK, RD_MARK,
378 WE0_MARK, WE1_MARK,
379
380 SCL0_MARK, PENC0_MARK, USB_OVC0_MARK,
381
382 IRQ2_B_MARK, IRQ3_B_MARK,
383
384 /* IPSR0 */
385 A15_MARK, ST0_VCO_CLKIN_MARK, LCD_DATA15_A_MARK, TIOC3D_C_MARK,
386 A14_MARK, LCD_DATA14_A_MARK, TIOC3C_C_MARK,
387 A13_MARK, LCD_DATA13_A_MARK, TIOC3B_C_MARK,
388 A12_MARK, LCD_DATA12_A_MARK, TIOC3A_C_MARK,
389 A11_MARK, ST0_D7_MARK, LCD_DATA11_A_MARK, TIOC2B_C_MARK,
390 A10_MARK, ST0_D6_MARK, LCD_DATA10_A_MARK, TIOC2A_C_MARK,
391 A9_MARK, ST0_D5_MARK, LCD_DATA9_A_MARK, TIOC1B_C_MARK,
392 A8_MARK, ST0_D4_MARK, LCD_DATA8_A_MARK, TIOC1A_C_MARK,
393 A7_MARK, ST0_D3_MARK, LCD_DATA7_A_MARK, TIOC0D_C_MARK,
394 A6_MARK, ST0_D2_MARK, LCD_DATA6_A_MARK, TIOC0C_C_MARK,
395 A5_MARK, ST0_D1_MARK, LCD_DATA5_A_MARK, TIOC0B_C_MARK,
396 A4_MARK, ST0_D0_MARK, LCD_DATA4_A_MARK, TIOC0A_C_MARK,
397 A3_MARK, ST0_VLD_MARK, LCD_DATA3_A_MARK, TCLKD_C_MARK,
398 A2_MARK, ST0_SYC_MARK, LCD_DATA2_A_MARK, TCLKC_C_MARK,
399 A1_MARK, ST0_REQ_MARK, LCD_DATA1_A_MARK, TCLKB_C_MARK,
400 A0_MARK, ST0_CLKIN_MARK, LCD_DATA0_A_MARK, TCLKA_C_MARK,
401
402 /* IPSR1 */
403 D3_MARK, SD0_DAT3_A_MARK, MMC_D3_A_MARK, ST1_D6_MARK, FD3_A_MARK,
404 D2_MARK, SD0_DAT2_A_MARK, MMC_D2_A_MARK, ST1_D5_MARK, FD2_A_MARK,
405 D1_MARK, SD0_DAT1_A_MARK, MMC_D1_A_MARK, ST1_D4_MARK, FD1_A_MARK,
406 D0_MARK, SD0_DAT0_A_MARK, MMC_D0_A_MARK, ST1_D3_MARK, FD0_A_MARK,
407 A25_MARK, TX2_D_MARK, ST1_D2_MARK,
408 A24_MARK, RX2_D_MARK, ST1_D1_MARK,
409 A23_MARK, ST1_D0_MARK, LCD_M_DISP_A_MARK,
410 A22_MARK, ST1_VLD_MARK, LCD_VEPWC_A_MARK,
411 A21_MARK, ST1_SYC_MARK, LCD_VCPWC_A_MARK,
412 A20_MARK, ST1_REQ_MARK, LCD_FLM_A_MARK,
413 A19_MARK, ST1_CLKIN_MARK, LCD_CLK_A_MARK, TIOC4D_C_MARK,
414 A18_MARK, ST1_PWM_MARK, LCD_CL2_A_MARK, TIOC4C_C_MARK,
415 A17_MARK, ST1_VCO_CLKIN_MARK, LCD_CL1_A_MARK, TIOC4B_C_MARK,
416 A16_MARK, ST0_PWM_MARK, LCD_DON_A_MARK, TIOC4A_C_MARK,
417
418 /* IPSR2 */
419 D14_MARK, TX2_B_MARK, FSE_A_MARK, ET0_TX_CLK_B_MARK,
420 D13_MARK, RX2_B_MARK, FRB_A_MARK, ET0_ETXD6_B_MARK,
421 D12_MARK, FWE_A_MARK, ET0_ETXD5_B_MARK,
422 D11_MARK, RSPI_MISO_A_MARK, QMI_QIO1_A_MARK, FRE_A_MARK,
423 ET0_ETXD3_B_MARK,
424 D10_MARK, RSPI_MOSI_A_MARK, QMO_QIO0_A_MARK, FALE_A_MARK,
425 ET0_ETXD2_B_MARK,
426 D9_MARK, SD0_CMD_A_MARK, MMC_CMD_A_MARK, QIO3_A_MARK,
427 FCLE_A_MARK, ET0_ETXD1_B_MARK,
428 D8_MARK, SD0_CLK_A_MARK, MMC_CLK_A_MARK, QIO2_A_MARK,
429 FCE_A_MARK, ET0_GTX_CLK_B_MARK,
430 D7_MARK, RSPI_SSL_A_MARK, MMC_D7_A_MARK, QSSL_A_MARK,
431 FD7_A_MARK,
432 D6_MARK, RSPI_RSPCK_A_MARK, MMC_D6_A_MARK, QSPCLK_A_MARK,
433 FD6_A_MARK,
434 D5_MARK, SD0_WP_A_MARK, MMC_D5_A_MARK, FD5_A_MARK,
435 D4_MARK, SD0_CD_A_MARK, MMC_D4_A_MARK, ST1_D7_MARK,
436 FD4_A_MARK,
437
438 /* IPSR3 */
439 DRACK0_MARK, SD1_DAT2_A_MARK, ATAG_MARK, TCLK1_A_MARK, ET0_ETXD7_MARK,
440 EX_WAIT2_MARK, SD1_DAT1_A_MARK, DACK2_MARK, CAN1_RX_C_MARK,
441 ET0_MAGIC_C_MARK, ET0_ETXD6_A_MARK,
442 EX_WAIT1_MARK, SD1_DAT0_A_MARK, DREQ2_MARK, CAN1_TX_C_MARK,
443 ET0_LINK_C_MARK, ET0_ETXD5_A_MARK,
444 EX_WAIT0_MARK, TCLK1_B_MARK,
445 RD_WR_MARK, TCLK0_MARK, CAN_CLK_B_MARK, ET0_ETXD4_MARK,
446 EX_CS5_MARK, SD1_CMD_A_MARK, ATADIR_MARK, QSSL_B_MARK,
447 ET0_ETXD3_A_MARK,
448 EX_CS4_MARK, SD1_WP_A_MARK, ATAWR_MARK, QMI_QIO1_B_MARK,
449 ET0_ETXD2_A_MARK,
450 EX_CS3_MARK, SD1_CD_A_MARK, ATARD_MARK, QMO_QIO0_B_MARK,
451 ET0_ETXD1_A_MARK,
452 EX_CS2_MARK, TX3_B_MARK, ATACS1_MARK, QSPCLK_B_MARK,
453 ET0_GTX_CLK_A_MARK,
454 EX_CS1_MARK, RX3_B_MARK, ATACS0_MARK, QIO2_B_MARK,
455 ET0_ETXD0_MARK,
456 CS1_A26_MARK, QIO3_B_MARK,
457 D15_MARK, SCK2_B_MARK,
458
459 /* IPSR4 */
460 SCK2_A_MARK, VI0_G3_MARK,
461 RTS1_B_MARK, VI0_G2_MARK,
462 CTS1_B_MARK, VI0_DATA7_VI0_G1_MARK,
463 TX1_B_MARK, VI0_DATA6_VI0_G0_MARK, ET0_PHY_INT_A_MARK,
464 RX1_B_MARK, VI0_DATA5_VI0_B5_MARK, ET0_MAGIC_A_MARK,
465 SCK1_B_MARK, VI0_DATA4_VI0_B4_MARK, ET0_LINK_A_MARK,
466 RTS0_B_MARK, VI0_DATA3_VI0_B3_MARK, ET0_MDIO_A_MARK,
467 CTS0_B_MARK, VI0_DATA2_VI0_B2_MARK, RMII0_MDIO_A_MARK,
468 ET0_MDC_MARK,
469 HTX0_A_MARK, TX1_A_MARK, VI0_DATA1_VI0_B1_MARK,
470 RMII0_MDC_A_MARK, ET0_COL_MARK,
471 HRX0_A_MARK, RX1_A_MARK, VI0_DATA0_VI0_B0_MARK,
472 RMII0_CRS_DV_A_MARK, ET0_CRS_MARK,
473 HSCK0_A_MARK, SCK1_A_MARK, VI0_VSYNC_MARK,
474 RMII0_RX_ER_A_MARK, ET0_RX_ER_MARK,
475 HRTS0_A_MARK, RTS1_A_MARK, VI0_HSYNC_MARK,
476 RMII0_TXD_EN_A_MARK, ET0_RX_DV_MARK,
477 HCTS0_A_MARK, CTS1_A_MARK, VI0_FIELD_MARK,
478 RMII0_RXD1_A_MARK, ET0_ERXD7_MARK,
479
480 /* IPSR5 */
481 SD2_CLK_A_MARK, RX2_A_MARK, VI0_G4_MARK, ET0_RX_CLK_B_MARK,
482 SD2_CMD_A_MARK, TX2_A_MARK, VI0_G5_MARK, ET0_ERXD2_B_MARK,
483 SD2_DAT0_A_MARK, RX3_A_MARK, VI0_R0_MARK, ET0_ERXD3_B_MARK,
484 SD2_DAT1_A_MARK, TX3_A_MARK, VI0_R1_MARK, ET0_MDIO_B_MARK,
485 SD2_DAT2_A_MARK, RX4_A_MARK, VI0_R2_MARK, ET0_LINK_B_MARK,
486 SD2_DAT3_A_MARK, TX4_A_MARK, VI0_R3_MARK, ET0_MAGIC_B_MARK,
487 SD2_CD_A_MARK, RX5_A_MARK, VI0_R4_MARK, ET0_PHY_INT_B_MARK,
488 SD2_WP_A_MARK, TX5_A_MARK, VI0_R5_MARK,
489 REF125CK_MARK, ADTRG_MARK, RX5_C_MARK,
490 REF50CK_MARK, CTS1_E_MARK, HCTS0_D_MARK,
491
492 /* IPSR6 */
493 DU0_DR0_MARK, SCIF_CLK_B_MARK, HRX0_D_MARK, IETX_A_MARK,
494 TCLKA_A_MARK, HIFD00_MARK,
495 DU0_DR1_MARK, SCK0_B_MARK, HTX0_D_MARK, IERX_A_MARK,
496 TCLKB_A_MARK, HIFD01_MARK,
497 DU0_DR2_MARK, RX0_B_MARK, TCLKC_A_MARK, HIFD02_MARK,
498 DU0_DR3_MARK, TX0_B_MARK, TCLKD_A_MARK, HIFD03_MARK,
499 DU0_DR4_MARK, CTS0_C_MARK, TIOC0A_A_MARK, HIFD04_MARK,
500 DU0_DR5_MARK, RTS0_C_MARK, TIOC0B_A_MARK, HIFD05_MARK,
501 DU0_DR6_MARK, SCK1_C_MARK, TIOC0C_A_MARK, HIFD06_MARK,
502 DU0_DR7_MARK, RX1_C_MARK, TIOC0D_A_MARK, HIFD07_MARK,
503 DU0_DG0_MARK, TX1_C_MARK, HSCK0_D_MARK, IECLK_A_MARK,
504 TIOC1A_A_MARK, HIFD08_MARK,
505 DU0_DG1_MARK, CTS1_C_MARK, HRTS0_D_MARK, TIOC1B_A_MARK,
506 HIFD09_MARK,
507
508 /* IPSR7 */
509 DU0_DG2_MARK, RTS1_C_MARK, RMII0_MDC_B_MARK, TIOC2A_A_MARK,
510 HIFD10_MARK,
511 DU0_DG3_MARK, SCK2_C_MARK, RMII0_MDIO_B_MARK, TIOC2B_A_MARK,
512 HIFD11_MARK,
513 DU0_DG4_MARK, RX2_C_MARK, RMII0_CRS_DV_B_MARK, TIOC3A_A_MARK,
514 HIFD12_MARK,
515 DU0_DG5_MARK, TX2_C_MARK, RMII0_RX_ER_B_MARK, TIOC3B_A_MARK,
516 HIFD13_MARK,
517 DU0_DG6_MARK, RX3_C_MARK, RMII0_RXD0_B_MARK, TIOC3C_A_MARK,
518 HIFD14_MARK,
519 DU0_DG7_MARK, TX3_C_MARK, RMII0_RXD1_B_MARK, TIOC3D_A_MARK,
520 HIFD15_MARK,
521 DU0_DB0_MARK, RX4_C_MARK, RMII0_TXD_EN_B_MARK, TIOC4A_A_MARK,
522 HIFCS_MARK,
523 DU0_DB1_MARK, TX4_C_MARK, RMII0_TXD0_B_MARK, TIOC4B_A_MARK,
524 HIFRS_MARK,
525 DU0_DB2_MARK, RX5_B_MARK, RMII0_TXD1_B_MARK, TIOC4C_A_MARK,
526 HIFWR_MARK,
527 DU0_DB3_MARK, TX5_B_MARK, TIOC4D_A_MARK, HIFRD_MARK,
528 DU0_DB4_MARK, HIFINT_MARK,
529
530 /* IPSR8 */
531 DU0_DB5_MARK, HIFDREQ_MARK,
532 DU0_DB6_MARK, HIFRDY_MARK,
533 DU0_DB7_MARK, SSI_SCK0_B_MARK, HIFEBL_B_MARK,
534 DU0_DOTCLKIN_MARK, HSPI_CS0_C_MARK, SSI_WS0_B_MARK,
535 DU0_DOTCLKOUT_MARK, HSPI_CLK0_C_MARK, SSI_SDATA0_B_MARK,
536 DU0_EXHSYNC_DU0_HSYNC_MARK, HSPI_TX0_C_MARK, SSI_SCK1_B_MARK,
537 DU0_EXVSYNC_DU0_VSYNC_MARK, HSPI_RX0_C_MARK, SSI_WS1_B_MARK,
538 DU0_EXODDF_DU0_ODDF_MARK, CAN0_RX_B_MARK, HSCK0_B_MARK,
539 SSI_SDATA1_B_MARK,
540 DU0_DISP_MARK, CAN0_TX_B_MARK, HRX0_B_MARK, AUDIO_CLKA_B_MARK,
541 DU0_CDE_MARK, HTX0_B_MARK, AUDIO_CLKB_B_MARK, LCD_VCPWC_B_MARK,
542 IRQ0_A_MARK, HSPI_TX_B_MARK, RX3_E_MARK, ET0_ERXD0_MARK,
543 IRQ1_A_MARK, HSPI_RX_B_MARK, TX3_E_MARK, ET0_ERXD1_MARK,
544 IRQ2_A_MARK, CTS0_A_MARK, HCTS0_B_MARK, ET0_ERXD2_A_MARK,
545 IRQ3_A_MARK, RTS0_A_MARK, HRTS0_B_MARK, ET0_ERXD3_A_MARK,
546
547 /* IPSR9 */
548 VI1_CLK_A_MARK, FD0_B_MARK, LCD_DATA0_B_MARK,
549 VI1_0_A_MARK, FD1_B_MARK, LCD_DATA1_B_MARK,
550 VI1_1_A_MARK, FD2_B_MARK, LCD_DATA2_B_MARK,
551 VI1_2_A_MARK, FD3_B_MARK, LCD_DATA3_B_MARK,
552 VI1_3_A_MARK, FD4_B_MARK, LCD_DATA4_B_MARK,
553 VI1_4_A_MARK, FD5_B_MARK, LCD_DATA5_B_MARK,
554 VI1_5_A_MARK, FD6_B_MARK, LCD_DATA6_B_MARK,
555 VI1_6_A_MARK, FD7_B_MARK, LCD_DATA7_B_MARK,
556 VI1_7_A_MARK, FCE_B_MARK, LCD_DATA8_B_MARK,
557 SSI_SCK0_A_MARK, TIOC1A_B_MARK, LCD_DATA9_B_MARK,
558 SSI_WS0_A_MARK, TIOC1B_B_MARK, LCD_DATA10_B_MARK,
559 SSI_SDATA0_A_MARK, VI1_0_B_MARK, TIOC2A_B_MARK, LCD_DATA11_B_MARK,
560 SSI_SCK1_A_MARK, VI1_1_B_MARK, TIOC2B_B_MARK, LCD_DATA12_B_MARK,
561 SSI_WS1_A_MARK, VI1_2_B_MARK, LCD_DATA13_B_MARK,
562 SSI_SDATA1_A_MARK, VI1_3_B_MARK, LCD_DATA14_B_MARK,
563
564 /* IPSR10 */
565 SSI_SCK23_MARK, VI1_4_B_MARK, RX1_D_MARK, FCLE_B_MARK,
566 LCD_DATA15_B_MARK,
567 SSI_WS23_MARK, VI1_5_B_MARK, TX1_D_MARK, HSCK0_C_MARK,
568 FALE_B_MARK, LCD_DON_B_MARK,
569 SSI_SDATA2_MARK, VI1_6_B_MARK, HRX0_C_MARK, FRE_B_MARK,
570 LCD_CL1_B_MARK,
571 SSI_SDATA3_MARK, VI1_7_B_MARK, HTX0_C_MARK, FWE_B_MARK,
572 LCD_CL2_B_MARK,
573 AUDIO_CLKA_A_MARK, VI1_CLK_B_MARK, SCK1_D_MARK, IECLK_B_MARK,
574 LCD_FLM_B_MARK,
575 AUDIO_CLKB_A_MARK, LCD_CLK_B_MARK,
576 AUDIO_CLKC_MARK, SCK1_E_MARK, HCTS0_C_MARK, FRB_B_MARK,
577 LCD_VEPWC_B_MARK,
578 AUDIO_CLKOUT_MARK, TX1_E_MARK, HRTS0_C_MARK, FSE_B_MARK,
579 LCD_M_DISP_B_MARK,
580 CAN_CLK_A_MARK, RX4_D_MARK,
581 CAN0_TX_A_MARK, TX4_D_MARK, MLB_CLK_MARK,
582 CAN1_RX_A_MARK, IRQ1_B_MARK,
583 CAN0_RX_A_MARK, IRQ0_B_MARK, MLB_SIG_MARK,
584 CAN1_TX_A_MARK, TX5_C_MARK, MLB_DAT_MARK,
585
586 /* IPSR11 */
587 SCL1_MARK, SCIF_CLK_C_MARK,
588 SDA1_MARK, RX1_E_MARK,
589 SDA0_MARK, HIFEBL_A_MARK,
590 SDSELF_MARK, RTS1_E_MARK,
591 SCIF_CLK_A_MARK, HSPI_CLK_A_MARK, VI0_CLK_MARK, RMII0_TXD0_A_MARK,
592 ET0_ERXD4_MARK,
593 SCK0_A_MARK, HSPI_CS_A_MARK, VI0_CLKENB_MARK, RMII0_TXD1_A_MARK,
594 ET0_ERXD5_MARK,
595 RX0_A_MARK, HSPI_RX_A_MARK, RMII0_RXD0_A_MARK, ET0_ERXD6_MARK,
596 TX0_A_MARK, HSPI_TX_A_MARK,
597 PENC1_MARK, TX3_D_MARK, CAN1_TX_B_MARK, TX5_D_MARK,
598 IETX_B_MARK,
599 USB_OVC1_MARK, RX3_D_MARK, CAN1_RX_B_MARK, RX5_D_MARK,
600 IERX_B_MARK,
601 DREQ0_MARK, SD1_CLK_A_MARK, ET0_TX_EN_MARK,
602 DACK0_MARK, SD1_DAT3_A_MARK, ET0_TX_ER_MARK,
603 DREQ1_MARK, HSPI_CLK_B_MARK, RX4_B_MARK, ET0_PHY_INT_C_MARK,
604 ET0_TX_CLK_A_MARK,
605 DACK1_MARK, HSPI_CS_B_MARK, TX4_B_MARK, ET0_RX_CLK_A_MARK,
606 PRESETOUT_MARK, ST_CLKOUT_MARK,
607
608 PINMUX_MARK_END,
609};
610
611static pinmux_enum_t pinmux_data[] = {
612 PINMUX_DATA_GP_ALL(), /* PINMUX_DATA(GP_M_N_DATA, GP_M_N_FN...), */
613
614 PINMUX_DATA(CLKOUT_MARK, FN_CLKOUT),
615 PINMUX_DATA(BS_MARK, FN_BS), PINMUX_DATA(CS0_MARK, FN_CS0),
616 PINMUX_DATA(EX_CS0_MARK, FN_EX_CS0),
617 PINMUX_DATA(RD_MARK, FN_RD), PINMUX_DATA(WE0_MARK, FN_WE0),
618 PINMUX_DATA(WE1_MARK, FN_WE1),
619 PINMUX_DATA(SCL0_MARK, FN_SCL0), PINMUX_DATA(PENC0_MARK, FN_PENC0),
620 PINMUX_DATA(USB_OVC0_MARK, FN_USB_OVC0),
621 PINMUX_DATA(IRQ2_B_MARK, FN_IRQ2_B),
622 PINMUX_DATA(IRQ3_B_MARK, FN_IRQ3_B),
623
624 /* IPSR0 */
625 PINMUX_IPSR_DATA(IP0_1_0, A0),
626 PINMUX_IPSR_DATA(IP0_1_0, ST0_CLKIN),
627 PINMUX_IPSR_MODSEL_DATA(IP0_1_0, LCD_DATA0_A, SEL_LCDC_0),
628 PINMUX_IPSR_MODSEL_DATA(IP0_1_0, TCLKA_C, SEL_MTU2_CLK_1),
629
630 PINMUX_IPSR_DATA(IP0_3_2, A1),
631 PINMUX_IPSR_DATA(IP0_3_2, ST0_REQ),
632 PINMUX_IPSR_MODSEL_DATA(IP0_3_2, LCD_DATA1_A, SEL_LCDC_0),
633 PINMUX_IPSR_MODSEL_DATA(IP0_3_2, TCLKB_C, SEL_MTU2_CLK_1),
634
635 PINMUX_IPSR_DATA(IP0_5_4, A2),
636 PINMUX_IPSR_DATA(IP0_5_4, ST0_SYC),
637 PINMUX_IPSR_MODSEL_DATA(IP0_5_4, LCD_DATA2_A, SEL_LCDC_0),
638 PINMUX_IPSR_MODSEL_DATA(IP0_5_4, TCLKC_C, SEL_MTU2_CLK_1),
639
640 PINMUX_IPSR_DATA(IP0_7_6, A3),
641 PINMUX_IPSR_DATA(IP0_7_6, ST0_VLD),
642 PINMUX_IPSR_MODSEL_DATA(IP0_7_6, LCD_DATA3_A, SEL_LCDC_0),
643 PINMUX_IPSR_MODSEL_DATA(IP0_7_6, TCLKD_C, SEL_MTU2_CLK_1),
644
645 PINMUX_IPSR_DATA(IP0_9_8, A4),
646 PINMUX_IPSR_DATA(IP0_9_8, ST0_D0),
647 PINMUX_IPSR_MODSEL_DATA(IP0_9_8, LCD_DATA4_A, SEL_LCDC_0),
648 PINMUX_IPSR_MODSEL_DATA(IP0_9_8, TIOC0A_C, SEL_MTU2_CH0_1),
649
650 PINMUX_IPSR_DATA(IP0_11_10, A5),
651 PINMUX_IPSR_DATA(IP0_11_10, ST0_D1),
652 PINMUX_IPSR_MODSEL_DATA(IP0_11_10, LCD_DATA5_A, SEL_LCDC_0),
653 PINMUX_IPSR_MODSEL_DATA(IP0_11_10, TIOC0B_C, SEL_MTU2_CH0_1),
654
655 PINMUX_IPSR_DATA(IP0_13_12, A6),
656 PINMUX_IPSR_DATA(IP0_13_12, ST0_D2),
657 PINMUX_IPSR_MODSEL_DATA(IP0_13_12, LCD_DATA6_A, SEL_LCDC_0),
658 PINMUX_IPSR_MODSEL_DATA(IP0_13_12, TIOC0C_C, SEL_MTU2_CH0_1),
659
660 PINMUX_IPSR_DATA(IP0_15_14, A7),
661 PINMUX_IPSR_DATA(IP0_15_14, ST0_D3),
662 PINMUX_IPSR_MODSEL_DATA(IP0_15_14, LCD_DATA7_A, SEL_LCDC_0),
663 PINMUX_IPSR_MODSEL_DATA(IP0_15_14, TIOC0D_C, SEL_MTU2_CH0_1),
664
665 PINMUX_IPSR_DATA(IP0_17_16, A8),
666 PINMUX_IPSR_DATA(IP0_17_16, ST0_D4),
667 PINMUX_IPSR_MODSEL_DATA(IP0_17_16, LCD_DATA8_A, SEL_LCDC_0),
668 PINMUX_IPSR_MODSEL_DATA(IP0_17_16, TIOC1A_C, SEL_MTU2_CH1_2),
669
670 PINMUX_IPSR_DATA(IP0_19_18, A9),
671 PINMUX_IPSR_DATA(IP0_19_18, ST0_D5),
672 PINMUX_IPSR_MODSEL_DATA(IP0_19_18, LCD_DATA9_A, SEL_LCDC_0),
673 PINMUX_IPSR_MODSEL_DATA(IP0_19_18, TIOC1B_C, SEL_MTU2_CH1_2),
674
675 PINMUX_IPSR_DATA(IP0_21_20, A10),
676 PINMUX_IPSR_DATA(IP0_21_20, ST0_D6),
677 PINMUX_IPSR_MODSEL_DATA(IP0_21_20, LCD_DATA10_A, SEL_LCDC_0),
678 PINMUX_IPSR_MODSEL_DATA(IP0_21_20, TIOC2A_C, SEL_MTU2_CH2_2),
679
680 PINMUX_IPSR_DATA(IP0_23_22, A11),
681 PINMUX_IPSR_DATA(IP0_23_22, ST0_D7),
682 PINMUX_IPSR_MODSEL_DATA(IP0_23_22, LCD_DATA11_A, SEL_LCDC_0),
683 PINMUX_IPSR_MODSEL_DATA(IP0_23_22, TIOC2B_C, SEL_MTU2_CH2_2),
684
685 PINMUX_IPSR_DATA(IP0_25_24, A12),
686 PINMUX_IPSR_MODSEL_DATA(IP0_25_24, LCD_DATA12_A, SEL_LCDC_0),
687 PINMUX_IPSR_MODSEL_DATA(IP0_25_24, TIOC3A_C, SEL_MTU2_CH3_1),
688
689 PINMUX_IPSR_DATA(IP0_27_26, A13),
690 PINMUX_IPSR_MODSEL_DATA(IP0_27_26, LCD_DATA13_A, SEL_LCDC_0),
691 PINMUX_IPSR_MODSEL_DATA(IP0_27_26, TIOC3B_C, SEL_MTU2_CH3_1),
692
693 PINMUX_IPSR_DATA(IP0_29_28, A14),
694 PINMUX_IPSR_MODSEL_DATA(IP0_29_28, LCD_DATA14_A, SEL_LCDC_0),
695 PINMUX_IPSR_MODSEL_DATA(IP0_29_28, TIOC3C_C, SEL_MTU2_CH3_1),
696
697 PINMUX_IPSR_DATA(IP0_31_30, A15),
698 PINMUX_IPSR_DATA(IP0_31_30, ST0_VCO_CLKIN),
699 PINMUX_IPSR_MODSEL_DATA(IP0_31_30, LCD_DATA15_A, SEL_LCDC_0),
700 PINMUX_IPSR_MODSEL_DATA(IP0_31_30, TIOC3D_C, SEL_MTU2_CH3_1),
701
702
703 /* IPSR1 */
704 PINMUX_IPSR_DATA(IP1_1_0, A16),
705 PINMUX_IPSR_DATA(IP1_1_0, ST0_PWM),
706 PINMUX_IPSR_MODSEL_DATA(IP1_1_0, LCD_DON_A, SEL_LCDC_0),
707 PINMUX_IPSR_MODSEL_DATA(IP1_1_0, TIOC4A_C, SEL_MTU2_CH4_1),
708
709 PINMUX_IPSR_DATA(IP1_3_2, A17),
710 PINMUX_IPSR_DATA(IP1_3_2, ST1_VCO_CLKIN),
711 PINMUX_IPSR_MODSEL_DATA(IP1_3_2, LCD_CL1_A, SEL_LCDC_0),
712 PINMUX_IPSR_MODSEL_DATA(IP1_3_2, TIOC4B_C, SEL_MTU2_CH4_1),
713
714 PINMUX_IPSR_DATA(IP1_5_4, A18),
715 PINMUX_IPSR_DATA(IP1_5_4, ST1_PWM),
716 PINMUX_IPSR_MODSEL_DATA(IP1_5_4, LCD_CL2_A, SEL_LCDC_0),
717 PINMUX_IPSR_MODSEL_DATA(IP1_5_4, TIOC4C_C, SEL_MTU2_CH4_1),
718
719 PINMUX_IPSR_DATA(IP1_7_6, A19),
720 PINMUX_IPSR_DATA(IP1_7_6, ST1_CLKIN),
721 PINMUX_IPSR_MODSEL_DATA(IP1_7_6, LCD_CLK_A, SEL_LCDC_0),
722 PINMUX_IPSR_MODSEL_DATA(IP1_7_6, TIOC4D_C, SEL_MTU2_CH4_1),
723
724 PINMUX_IPSR_DATA(IP1_9_8, A20),
725 PINMUX_IPSR_DATA(IP1_9_8, ST1_REQ),
726 PINMUX_IPSR_MODSEL_DATA(IP1_9_8, LCD_FLM_A, SEL_LCDC_0),
727
728 PINMUX_IPSR_DATA(IP1_11_10, A21),
729 PINMUX_IPSR_DATA(IP1_11_10, ST1_SYC),
730 PINMUX_IPSR_MODSEL_DATA(IP1_11_10, LCD_VCPWC_A, SEL_LCDC_0),
731
732 PINMUX_IPSR_DATA(IP1_13_12, A22),
733 PINMUX_IPSR_DATA(IP1_13_12, ST1_VLD),
734 PINMUX_IPSR_MODSEL_DATA(IP1_13_12, LCD_VEPWC_A, SEL_LCDC_0),
735
736 PINMUX_IPSR_DATA(IP1_15_14, A23),
737 PINMUX_IPSR_DATA(IP1_15_14, ST1_D0),
738 PINMUX_IPSR_MODSEL_DATA(IP1_15_14, LCD_M_DISP_A, SEL_LCDC_0),
739
740 PINMUX_IPSR_DATA(IP1_17_16, A24),
741 PINMUX_IPSR_MODSEL_DATA(IP1_17_16, RX2_D, SEL_SCIF2_3),
742 PINMUX_IPSR_DATA(IP1_17_16, ST1_D1),
743
744 PINMUX_IPSR_DATA(IP1_19_18, A25),
745 PINMUX_IPSR_MODSEL_DATA(IP1_17_16, RX2_D, SEL_SCIF2_3),
746 PINMUX_IPSR_DATA(IP1_17_16, ST1_D2),
747
748 PINMUX_IPSR_DATA(IP1_22_20, D0),
749 PINMUX_IPSR_MODSEL_DATA(IP1_22_20, SD0_DAT0_A, SEL_SDHI0_0),
750 PINMUX_IPSR_MODSEL_DATA(IP1_22_20, MMC_D0_A, SEL_MMC_0),
751 PINMUX_IPSR_DATA(IP1_22_20, ST1_D3),
752 PINMUX_IPSR_MODSEL_DATA(IP1_22_20, FD0_A, SEL_FLCTL_0),
753
754 PINMUX_IPSR_DATA(IP1_25_23, D1),
755 PINMUX_IPSR_MODSEL_DATA(IP1_25_23, SD0_DAT0_A, SEL_SDHI0_0),
756 PINMUX_IPSR_MODSEL_DATA(IP1_25_23, MMC_D1_A, SEL_MMC_0),
757 PINMUX_IPSR_DATA(IP1_25_23, ST1_D4),
758 PINMUX_IPSR_MODSEL_DATA(IP1_25_23, FD1_A, SEL_FLCTL_0),
759
760 PINMUX_IPSR_DATA(IP1_28_26, D2),
761 PINMUX_IPSR_MODSEL_DATA(IP1_28_26, SD0_DAT0_A, SEL_SDHI0_0),
762 PINMUX_IPSR_MODSEL_DATA(IP1_28_26, MMC_D2_A, SEL_MMC_0),
763 PINMUX_IPSR_DATA(IP1_28_26, ST1_D5),
764 PINMUX_IPSR_MODSEL_DATA(IP1_28_26, FD2_A, SEL_FLCTL_0),
765
766 PINMUX_IPSR_DATA(IP1_31_29, D3),
767 PINMUX_IPSR_MODSEL_DATA(IP1_31_29, SD0_DAT0_A, SEL_SDHI0_0),
768 PINMUX_IPSR_MODSEL_DATA(IP1_31_29, MMC_D3_A, SEL_MMC_0),
769 PINMUX_IPSR_DATA(IP1_31_29, ST1_D6),
770 PINMUX_IPSR_MODSEL_DATA(IP1_31_29, FD3_A, SEL_FLCTL_0),
771
772 /* IPSR2 */
773 PINMUX_IPSR_DATA(IP2_2_0, D4),
774 PINMUX_IPSR_MODSEL_DATA(IP2_2_0, SD0_CD_A, SEL_SDHI0_0),
775 PINMUX_IPSR_MODSEL_DATA(IP2_2_0, MMC_D4_A, SEL_MMC_0),
776 PINMUX_IPSR_DATA(IP2_2_0, ST1_D7),
777 PINMUX_IPSR_MODSEL_DATA(IP2_2_0, FD4_A, SEL_FLCTL_0),
778
779 PINMUX_IPSR_DATA(IP2_4_3, D5),
780 PINMUX_IPSR_MODSEL_DATA(IP2_4_3, SD0_WP_A, SEL_SDHI0_0),
781 PINMUX_IPSR_MODSEL_DATA(IP2_4_3, MMC_D5_A, SEL_MMC_0),
782 PINMUX_IPSR_MODSEL_DATA(IP2_4_3, FD5_A, SEL_FLCTL_0),
783
784 PINMUX_IPSR_DATA(IP2_7_5, D6),
785 PINMUX_IPSR_MODSEL_DATA(IP2_7_5, RSPI_RSPCK_A, SEL_RSPI_0),
786 PINMUX_IPSR_MODSEL_DATA(IP2_7_5, MMC_D6_A, SEL_MMC_0),
787 PINMUX_IPSR_MODSEL_DATA(IP2_7_5, QSPCLK_A, SEL_RQSPI_0),
788 PINMUX_IPSR_MODSEL_DATA(IP2_7_5, FD6_A, SEL_FLCTL_0),
789
790 PINMUX_IPSR_DATA(IP2_10_8, D7),
791 PINMUX_IPSR_MODSEL_DATA(IP2_10_8, RSPI_SSL_A, SEL_RSPI_0),
792 PINMUX_IPSR_MODSEL_DATA(IP2_10_8, MMC_D7_A, SEL_MMC_0),
793 PINMUX_IPSR_MODSEL_DATA(IP2_10_8, QSSL_A, SEL_RQSPI_0),
794 PINMUX_IPSR_MODSEL_DATA(IP2_10_8, FD7_A, SEL_FLCTL_0),
795
796 PINMUX_IPSR_DATA(IP2_13_11, D8),
797 PINMUX_IPSR_MODSEL_DATA(IP2_13_11, SD0_CLK_A, SEL_SDHI0_0),
798 PINMUX_IPSR_MODSEL_DATA(IP2_13_11, MMC_CLK_A, SEL_MMC_0),
799 PINMUX_IPSR_MODSEL_DATA(IP2_13_11, QIO2_A, SEL_RQSPI_0),
800 PINMUX_IPSR_MODSEL_DATA(IP2_13_11, FCE_A, SEL_FLCTL_0),
801 PINMUX_IPSR_MODSEL_DATA(IP2_13_11, ET0_GTX_CLK_B, SEL_ET0_1),
802
803 PINMUX_IPSR_DATA(IP2_16_14, D9),
804 PINMUX_IPSR_MODSEL_DATA(IP2_16_14, SD0_CMD_A, SEL_SDHI0_0),
805 PINMUX_IPSR_MODSEL_DATA(IP2_16_14, MMC_CMD_A, SEL_MMC_0),
806 PINMUX_IPSR_MODSEL_DATA(IP2_16_14, QIO3_A, SEL_RQSPI_0),
807 PINMUX_IPSR_MODSEL_DATA(IP2_16_14, FCLE_A, SEL_FLCTL_0),
808 PINMUX_IPSR_MODSEL_DATA(IP2_16_14, ET0_ETXD1_B, SEL_ET0_1),
809
810 PINMUX_IPSR_DATA(IP2_19_17, D10),
811 PINMUX_IPSR_MODSEL_DATA(IP2_19_17, RSPI_MOSI_A, SEL_RSPI_0),
812 PINMUX_IPSR_MODSEL_DATA(IP2_19_17, QMO_QIO0_A, SEL_RQSPI_0),
813 PINMUX_IPSR_MODSEL_DATA(IP2_19_17, FALE_A, SEL_FLCTL_0),
814 PINMUX_IPSR_MODSEL_DATA(IP2_19_17, ET0_ETXD2_B, SEL_ET0_1),
815
816 PINMUX_IPSR_DATA(IP2_22_20, D11),
817 PINMUX_IPSR_MODSEL_DATA(IP2_22_20, RSPI_MISO_A, SEL_RSPI_0),
818 PINMUX_IPSR_MODSEL_DATA(IP2_22_20, QMI_QIO1_A, SEL_RQSPI_0),
819 PINMUX_IPSR_MODSEL_DATA(IP2_22_20, FRE_A, SEL_FLCTL_0),
820
821 PINMUX_IPSR_DATA(IP2_24_23, D12),
822 PINMUX_IPSR_MODSEL_DATA(IP2_24_23, FWE_A, SEL_FLCTL_0),
823 PINMUX_IPSR_MODSEL_DATA(IP2_24_23, ET0_ETXD5_B, SEL_ET0_1),
824
825 PINMUX_IPSR_DATA(IP2_27_25, D13),
826 PINMUX_IPSR_MODSEL_DATA(IP2_27_25, RX2_B, SEL_SCIF2_1),
827 PINMUX_IPSR_MODSEL_DATA(IP2_27_25, FRB_A, SEL_FLCTL_0),
828 PINMUX_IPSR_MODSEL_DATA(IP2_27_25, ET0_ETXD6_B, SEL_ET0_1),
829
830 PINMUX_IPSR_DATA(IP2_30_28, D14),
831 PINMUX_IPSR_MODSEL_DATA(IP2_30_28, TX2_B, SEL_SCIF2_1),
832 PINMUX_IPSR_MODSEL_DATA(IP2_30_28, FSE_A, SEL_FLCTL_0),
833 PINMUX_IPSR_MODSEL_DATA(IP2_30_28, ET0_TX_CLK_B, SEL_ET0_1),
834
835 /* IPSR3 */
836 PINMUX_IPSR_DATA(IP3_1_0, D15),
837 PINMUX_IPSR_MODSEL_DATA(IP3_1_0, SCK2_B, SEL_SCIF2_1),
838
839 PINMUX_IPSR_DATA(IP3_2, CS1_A26),
840 PINMUX_IPSR_MODSEL_DATA(IP3_2, QIO3_B, SEL_RQSPI_1),
841
842 PINMUX_IPSR_DATA(IP3_5_3, EX_CS1),
843 PINMUX_IPSR_MODSEL_DATA(IP3_5_3, RX3_B, SEL_SCIF2_1),
844 PINMUX_IPSR_DATA(IP3_5_3, ATACS0),
845 PINMUX_IPSR_MODSEL_DATA(IP3_5_3, QIO2_B, SEL_RQSPI_1),
846 PINMUX_IPSR_DATA(IP3_5_3, ET0_ETXD0),
847
848 PINMUX_IPSR_DATA(IP3_8_6, EX_CS2),
849 PINMUX_IPSR_MODSEL_DATA(IP3_8_6, TX3_B, SEL_SCIF3_1),
850 PINMUX_IPSR_DATA(IP3_8_6, ATACS1),
851 PINMUX_IPSR_MODSEL_DATA(IP3_8_6, QSPCLK_B, SEL_RQSPI_1),
852 PINMUX_IPSR_MODSEL_DATA(IP3_8_6, ET0_GTX_CLK_A, SEL_ET0_0),
853
854 PINMUX_IPSR_DATA(IP3_11_9, EX_CS3),
855 PINMUX_IPSR_MODSEL_DATA(IP3_11_9, SD1_CD_A, SEL_SDHI1_0),
856 PINMUX_IPSR_DATA(IP3_11_9, ATARD),
857 PINMUX_IPSR_MODSEL_DATA(IP3_11_9, QMO_QIO0_B, SEL_RQSPI_1),
858 PINMUX_IPSR_MODSEL_DATA(IP3_11_9, ET0_ETXD1_A, SEL_ET0_0),
859
860 PINMUX_IPSR_DATA(IP3_14_12, EX_CS4),
861 PINMUX_IPSR_MODSEL_DATA(IP3_14_12, SD1_WP_A, SEL_SDHI1_0),
862 PINMUX_IPSR_DATA(IP3_14_12, ATAWR),
863 PINMUX_IPSR_MODSEL_DATA(IP3_14_12, QMI_QIO1_B, SEL_RQSPI_1),
864 PINMUX_IPSR_MODSEL_DATA(IP3_14_12, ET0_ETXD2_A, SEL_ET0_0),
865
866 PINMUX_IPSR_DATA(IP3_17_15, EX_CS5),
867 PINMUX_IPSR_MODSEL_DATA(IP3_17_15, SD1_CMD_A, SEL_SDHI1_0),
868 PINMUX_IPSR_DATA(IP3_17_15, ATADIR),
869 PINMUX_IPSR_MODSEL_DATA(IP3_17_15, QSSL_B, SEL_RQSPI_1),
870 PINMUX_IPSR_MODSEL_DATA(IP3_17_15, ET0_ETXD3_A, SEL_ET0_0),
871
872 PINMUX_IPSR_DATA(IP3_19_18, RD_WR),
873 PINMUX_IPSR_DATA(IP3_19_18, TCLK0),
874 PINMUX_IPSR_MODSEL_DATA(IP3_19_18, CAN_CLK_B, SEL_RCAN_CLK_1),
875 PINMUX_IPSR_DATA(IP3_19_18, ET0_ETXD4),
876
877 PINMUX_IPSR_DATA(IP3_20, EX_WAIT0),
878 PINMUX_IPSR_MODSEL_DATA(IP3_20, TCLK1_B, SEL_TMU_1),
879
880 PINMUX_IPSR_DATA(IP3_23_21, EX_WAIT1),
881 PINMUX_IPSR_MODSEL_DATA(IP3_23_21, SD1_DAT0_A, SEL_SDHI1_0),
882 PINMUX_IPSR_DATA(IP3_23_21, DREQ2),
883 PINMUX_IPSR_MODSEL_DATA(IP3_23_21, CAN1_TX_C, SEL_RCAN1_2),
884 PINMUX_IPSR_MODSEL_DATA(IP3_23_21, ET0_LINK_C, SEL_ET0_CTL_2),
885 PINMUX_IPSR_MODSEL_DATA(IP3_23_21, ET0_ETXD5_A, SEL_ET0_0),
886
887 PINMUX_IPSR_DATA(IP3_26_24, EX_WAIT2),
888 PINMUX_IPSR_MODSEL_DATA(IP3_26_24, SD1_DAT1_A, SEL_SDHI1_0),
889 PINMUX_IPSR_DATA(IP3_26_24, DACK2),
890 PINMUX_IPSR_MODSEL_DATA(IP3_26_24, CAN1_RX_C, SEL_RCAN1_2),
891 PINMUX_IPSR_MODSEL_DATA(IP3_26_24, ET0_MAGIC_C, SEL_ET0_CTL_2),
892 PINMUX_IPSR_MODSEL_DATA(IP3_26_24, ET0_ETXD6_A, SEL_ET0_0),
893
894 PINMUX_IPSR_DATA(IP3_29_27, DRACK0),
895 PINMUX_IPSR_MODSEL_DATA(IP3_29_27, SD1_DAT2_A, SEL_SDHI1_0),
896 PINMUX_IPSR_DATA(IP3_29_27, ATAG),
897 PINMUX_IPSR_MODSEL_DATA(IP3_29_27, TCLK1_A, SEL_TMU_0),
898 PINMUX_IPSR_DATA(IP3_29_27, ET0_ETXD7),
899
900 /* IPSR4 */
901 PINMUX_IPSR_MODSEL_DATA(IP4_2_0, HCTS0_A, SEL_HSCIF_0),
902 PINMUX_IPSR_MODSEL_DATA(IP4_2_0, CTS1_A, SEL_SCIF1_0),
903 PINMUX_IPSR_DATA(IP4_2_0, VI0_FIELD),
904 PINMUX_IPSR_MODSEL_DATA(IP4_2_0, RMII0_RXD1_A, SEL_RMII_0),
905 PINMUX_IPSR_DATA(IP4_2_0, ET0_ERXD7),
906
907 PINMUX_IPSR_MODSEL_DATA(IP4_5_3, HRTS0_A, SEL_HSCIF_0),
908 PINMUX_IPSR_MODSEL_DATA(IP4_5_3, RTS1_A, SEL_SCIF1_0),
909 PINMUX_IPSR_DATA(IP4_5_3, VI0_HSYNC),
910 PINMUX_IPSR_MODSEL_DATA(IP4_5_3, RMII0_TXD_EN_A, SEL_RMII_0),
911 PINMUX_IPSR_DATA(IP4_5_3, ET0_RX_DV),
912
913 PINMUX_IPSR_MODSEL_DATA(IP4_8_6, HSCK0_A, SEL_HSCIF_0),
914 PINMUX_IPSR_MODSEL_DATA(IP4_8_6, SCK1_A, SEL_SCIF1_0),
915 PINMUX_IPSR_DATA(IP4_8_6, VI0_VSYNC),
916 PINMUX_IPSR_MODSEL_DATA(IP4_8_6, RMII0_RX_ER_A, SEL_RMII_0),
917 PINMUX_IPSR_DATA(IP4_8_6, ET0_RX_ER),
918
919 PINMUX_IPSR_MODSEL_DATA(IP4_11_9, HRX0_A, SEL_HSCIF_0),
920 PINMUX_IPSR_MODSEL_DATA(IP4_11_9, RX1_A, SEL_SCIF1_0),
921 PINMUX_IPSR_DATA(IP4_11_9, VI0_DATA0_VI0_B0),
922 PINMUX_IPSR_MODSEL_DATA(IP4_11_9, RMII0_CRS_DV_A, SEL_RMII_0),
923 PINMUX_IPSR_DATA(IP4_11_9, ET0_CRS),
924
925 PINMUX_IPSR_MODSEL_DATA(IP4_14_12, HTX0_A, SEL_HSCIF_0),
926 PINMUX_IPSR_MODSEL_DATA(IP4_14_12, TX1_A, SEL_SCIF1_0),
927 PINMUX_IPSR_DATA(IP4_14_12, VI0_DATA1_VI0_B1),
928 PINMUX_IPSR_MODSEL_DATA(IP4_14_12, RMII0_MDC_A, SEL_RMII_0),
929 PINMUX_IPSR_DATA(IP4_14_12, ET0_COL),
930
931 PINMUX_IPSR_MODSEL_DATA(IP4_17_15, CTS0_B, SEL_SCIF0_1),
932 PINMUX_IPSR_DATA(IP4_17_15, VI0_DATA2_VI0_B2),
933 PINMUX_IPSR_MODSEL_DATA(IP4_17_15, RMII0_MDIO_A, SEL_RMII_0),
934 PINMUX_IPSR_DATA(IP4_17_15, ET0_MDC),
935
936 PINMUX_IPSR_MODSEL_DATA(IP4_19_18, RTS0_B, SEL_SCIF0_1),
937 PINMUX_IPSR_DATA(IP4_19_18, VI0_DATA3_VI0_B3),
938 PINMUX_IPSR_MODSEL_DATA(IP4_19_18, ET0_MDIO_A, SEL_ET0_0),
939
940 PINMUX_IPSR_MODSEL_DATA(IP4_21_20, SCK1_B, SEL_SCIF1_1),
941 PINMUX_IPSR_DATA(IP4_21_20, VI0_DATA4_VI0_B4),
942 PINMUX_IPSR_MODSEL_DATA(IP4_21_20, ET0_LINK_A, SEL_ET0_CTL_0),
943
944 PINMUX_IPSR_MODSEL_DATA(IP4_23_22, RX1_B, SEL_SCIF1_1),
945 PINMUX_IPSR_DATA(IP4_23_22, VI0_DATA5_VI0_B5),
946 PINMUX_IPSR_MODSEL_DATA(IP4_23_22, ET0_MAGIC_A, SEL_ET0_CTL_0),
947
948 PINMUX_IPSR_MODSEL_DATA(IP4_25_24, TX1_B, SEL_SCIF1_1),
949 PINMUX_IPSR_DATA(IP4_25_24, VI0_DATA6_VI0_G0),
950 PINMUX_IPSR_MODSEL_DATA(IP4_25_24, ET0_PHY_INT_A, SEL_ET0_CTL_0),
951
952 PINMUX_IPSR_MODSEL_DATA(IP4_27_26, CTS1_B, SEL_SCIF1_1),
953 PINMUX_IPSR_DATA(IP4_27_26, VI0_DATA7_VI0_G1),
954
955 PINMUX_IPSR_MODSEL_DATA(IP4_29_28, RTS1_B, SEL_SCIF1_1),
956 PINMUX_IPSR_DATA(IP4_29_28, VI0_G2),
957
958 PINMUX_IPSR_MODSEL_DATA(IP4_31_30, SCK2_A, SEL_SCIF2_0),
959 PINMUX_IPSR_DATA(IP4_31_30, VI0_G3),
960
961 /* IPSR5 */
962 PINMUX_IPSR_MODSEL_DATA(IP5_2_0, SD2_CLK_A, SEL_SDHI2_0),
963 PINMUX_IPSR_MODSEL_DATA(IP5_2_0, RX2_A, SEL_SCIF2_0),
964 PINMUX_IPSR_DATA(IP5_2_0, VI0_G4),
965 PINMUX_IPSR_MODSEL_DATA(IP5_2_0, ET0_RX_CLK_B, SEL_ET0_1),
966
967 PINMUX_IPSR_MODSEL_DATA(IP5_5_3, SD2_CMD_A, SEL_SDHI2_0),
968 PINMUX_IPSR_MODSEL_DATA(IP5_5_3, TX2_A, SEL_SCIF2_0),
969 PINMUX_IPSR_DATA(IP5_5_3, VI0_G5),
970 PINMUX_IPSR_MODSEL_DATA(IP5_5_3, ET0_ERXD2_B, SEL_ET0_1),
971
972 PINMUX_IPSR_MODSEL_DATA(IP5_8_6, SD2_DAT0_A, SEL_SDHI2_0),
973 PINMUX_IPSR_MODSEL_DATA(IP5_8_6, RX3_A, SEL_SCIF3_0),
974 PINMUX_IPSR_DATA(IP4_8_6, VI0_R0),
975 PINMUX_IPSR_MODSEL_DATA(IP4_8_6, ET0_ERXD2_B, SEL_ET0_1),
976
977 PINMUX_IPSR_MODSEL_DATA(IP5_11_9, SD2_DAT1_A, SEL_SDHI2_0),
978 PINMUX_IPSR_MODSEL_DATA(IP5_11_9, TX3_A, SEL_SCIF3_0),
979 PINMUX_IPSR_DATA(IP5_11_9, VI0_R1),
980 PINMUX_IPSR_MODSEL_DATA(IP5_11_9, ET0_MDIO_B, SEL_ET0_1),
981
982 PINMUX_IPSR_MODSEL_DATA(IP5_14_12, SD2_DAT2_A, SEL_SDHI2_0),
983 PINMUX_IPSR_MODSEL_DATA(IP5_14_12, RX4_A, SEL_SCIF4_0),
984 PINMUX_IPSR_DATA(IP5_14_12, VI0_R2),
985 PINMUX_IPSR_MODSEL_DATA(IP5_14_12, ET0_LINK_B, SEL_ET0_CTL_1),
986
987 PINMUX_IPSR_MODSEL_DATA(IP5_17_15, SD2_DAT3_A, SEL_SDHI2_0),
988 PINMUX_IPSR_MODSEL_DATA(IP5_17_15, TX4_A, SEL_SCIF4_0),
989 PINMUX_IPSR_DATA(IP5_17_15, VI0_R3),
990 PINMUX_IPSR_MODSEL_DATA(IP5_17_15, ET0_MAGIC_B, SEL_ET0_CTL_1),
991
992 PINMUX_IPSR_MODSEL_DATA(IP5_20_18, SD2_CD_A, SEL_SDHI2_0),
993 PINMUX_IPSR_MODSEL_DATA(IP5_20_18, RX5_A, SEL_SCIF5_0),
994 PINMUX_IPSR_DATA(IP5_20_18, VI0_R4),
995 PINMUX_IPSR_MODSEL_DATA(IP5_20_18, ET0_PHY_INT_B, SEL_ET0_CTL_1),
996
997 PINMUX_IPSR_MODSEL_DATA(IP5_22_21, SD2_WP_A, SEL_SDHI2_0),
998 PINMUX_IPSR_MODSEL_DATA(IP5_22_21, TX5_A, SEL_SCIF5_0),
999 PINMUX_IPSR_DATA(IP5_22_21, VI0_R5),
1000
1001 PINMUX_IPSR_DATA(IP5_24_23, REF125CK),
1002 PINMUX_IPSR_DATA(IP5_24_23, ADTRG),
1003 PINMUX_IPSR_MODSEL_DATA(IP5_24_23, RX5_C, SEL_SCIF5_2),
1004 PINMUX_IPSR_DATA(IP5_26_25, REF50CK),
1005 PINMUX_IPSR_MODSEL_DATA(IP5_26_25, CTS1_E, SEL_SCIF1_3),
1006 PINMUX_IPSR_MODSEL_DATA(IP5_26_25, HCTS0_D, SEL_HSCIF_3),
1007
1008 /* IPSR6 */
1009 PINMUX_IPSR_DATA(IP6_2_0, DU0_DR0),
1010 PINMUX_IPSR_MODSEL_DATA(IP6_2_0, SCIF_CLK_B, SEL_SCIF_CLK_1),
1011 PINMUX_IPSR_MODSEL_DATA(IP6_2_0, HRX0_D, SEL_HSCIF_3),
1012 PINMUX_IPSR_MODSEL_DATA(IP6_2_0, IETX_A, SEL_IEBUS_0),
1013 PINMUX_IPSR_MODSEL_DATA(IP6_2_0, TCLKA_A, SEL_MTU2_CLK_0),
1014 PINMUX_IPSR_DATA(IP6_2_0, HIFD00),
1015
1016 PINMUX_IPSR_DATA(IP6_5_3, DU0_DR1),
1017 PINMUX_IPSR_MODSEL_DATA(IP6_5_3, SCK0_B, SEL_SCIF0_1),
1018 PINMUX_IPSR_MODSEL_DATA(IP6_5_3, HTX0_D, SEL_HSCIF_3),
1019 PINMUX_IPSR_MODSEL_DATA(IP6_5_3, IERX_A, SEL_IEBUS_0),
1020 PINMUX_IPSR_MODSEL_DATA(IP6_5_3, TCLKB_A, SEL_MTU2_CLK_0),
1021 PINMUX_IPSR_DATA(IP6_5_3, HIFD01),
1022
1023 PINMUX_IPSR_DATA(IP6_7_6, DU0_DR2),
1024 PINMUX_IPSR_MODSEL_DATA(IP6_7_6, RX0_B, SEL_SCIF0_1),
1025 PINMUX_IPSR_MODSEL_DATA(IP6_7_6, TCLKC_A, SEL_MTU2_CLK_0),
1026 PINMUX_IPSR_DATA(IP6_7_6, HIFD02),
1027
1028 PINMUX_IPSR_DATA(IP6_9_8, DU0_DR3),
1029 PINMUX_IPSR_MODSEL_DATA(IP6_9_8, TX0_B, SEL_SCIF0_1),
1030 PINMUX_IPSR_MODSEL_DATA(IP6_9_8, TCLKD_A, SEL_MTU2_CLK_0),
1031 PINMUX_IPSR_DATA(IP6_9_8, HIFD03),
1032
1033 PINMUX_IPSR_DATA(IP6_11_10, DU0_DR4),
1034 PINMUX_IPSR_MODSEL_DATA(IP6_11_10, CTS0_C, SEL_SCIF0_2),
1035 PINMUX_IPSR_MODSEL_DATA(IP6_11_10, TIOC0A_A, SEL_MTU2_CH0_0),
1036 PINMUX_IPSR_DATA(IP6_11_10, HIFD04),
1037
1038 PINMUX_IPSR_DATA(IP6_13_12, DU0_DR5),
1039 PINMUX_IPSR_MODSEL_DATA(IP6_13_12, RTS0_C, SEL_SCIF0_1),
1040 PINMUX_IPSR_MODSEL_DATA(IP6_13_12, TIOC0B_A, SEL_MTU2_CH0_0),
1041 PINMUX_IPSR_DATA(IP6_13_12, HIFD05),
1042
1043 PINMUX_IPSR_DATA(IP6_15_14, DU0_DR6),
1044 PINMUX_IPSR_MODSEL_DATA(IP6_15_14, SCK1_C, SEL_SCIF1_2),
1045 PINMUX_IPSR_MODSEL_DATA(IP6_15_14, TIOC0C_A, SEL_MTU2_CH0_0),
1046 PINMUX_IPSR_DATA(IP6_15_14, HIFD06),
1047
1048 PINMUX_IPSR_DATA(IP6_17_16, DU0_DR7),
1049 PINMUX_IPSR_MODSEL_DATA(IP6_17_16, RX1_C, SEL_SCIF1_2),
1050 PINMUX_IPSR_MODSEL_DATA(IP6_17_16, TIOC0D_A, SEL_MTU2_CH0_0),
1051 PINMUX_IPSR_DATA(IP6_17_16, HIFD07),
1052
1053 PINMUX_IPSR_DATA(IP6_20_18, DU0_DG0),
1054 PINMUX_IPSR_MODSEL_DATA(IP6_20_18, TX1_C, SEL_SCIF1_2),
1055 PINMUX_IPSR_MODSEL_DATA(IP6_20_18, HSCK0_D, SEL_HSCIF_3),
1056 PINMUX_IPSR_MODSEL_DATA(IP6_20_18, IECLK_A, SEL_IEBUS_0),
1057 PINMUX_IPSR_MODSEL_DATA(IP6_20_18, TIOC1A_A, SEL_MTU2_CH1_0),
1058 PINMUX_IPSR_DATA(IP6_20_18, HIFD08),
1059
1060 PINMUX_IPSR_DATA(IP6_23_21, DU0_DG1),
1061 PINMUX_IPSR_MODSEL_DATA(IP6_23_21, CTS1_C, SEL_SCIF1_2),
1062 PINMUX_IPSR_MODSEL_DATA(IP6_23_21, HRTS0_D, SEL_HSCIF_3),
1063 PINMUX_IPSR_MODSEL_DATA(IP6_23_21, TIOC1B_A, SEL_MTU2_CH1_0),
1064 PINMUX_IPSR_DATA(IP6_23_21, HIFD09),
1065
1066 /* IPSR7 */
1067 PINMUX_IPSR_DATA(IP7_2_0, DU0_DG2),
1068 PINMUX_IPSR_MODSEL_DATA(IP7_2_0, RTS1_C, SEL_SCIF1_2),
1069 PINMUX_IPSR_MODSEL_DATA(IP7_2_0, RMII0_MDC_B, SEL_RMII_1),
1070 PINMUX_IPSR_MODSEL_DATA(IP7_2_0, TIOC2A_A, SEL_MTU2_CH2_0),
1071 PINMUX_IPSR_DATA(IP7_2_0, HIFD10),
1072
1073 PINMUX_IPSR_DATA(IP7_5_3, DU0_DG3),
1074 PINMUX_IPSR_MODSEL_DATA(IP7_5_3, SCK2_C, SEL_SCIF2_2),
1075 PINMUX_IPSR_MODSEL_DATA(IP7_5_3, RMII0_MDIO_B, SEL_RMII_1),
1076 PINMUX_IPSR_MODSEL_DATA(IP7_5_3, TIOC2B_A, SEL_MTU2_CH2_0),
1077 PINMUX_IPSR_DATA(IP7_5_3, HIFD11),
1078
1079 PINMUX_IPSR_DATA(IP7_8_6, DU0_DG4),
1080 PINMUX_IPSR_MODSEL_DATA(IP7_8_6, RX2_C, SEL_SCIF2_2),
1081 PINMUX_IPSR_MODSEL_DATA(IP7_8_6, RMII0_CRS_DV_B, SEL_RMII_1),
1082 PINMUX_IPSR_MODSEL_DATA(IP7_8_6, TIOC3A_A, SEL_MTU2_CH3_0),
1083 PINMUX_IPSR_DATA(IP7_8_6, HIFD12),
1084
1085 PINMUX_IPSR_DATA(IP7_11_9, DU0_DG5),
1086 PINMUX_IPSR_MODSEL_DATA(IP7_11_9, TX2_C, SEL_SCIF2_2),
1087 PINMUX_IPSR_MODSEL_DATA(IP7_11_9, RMII0_RX_ER_B, SEL_RMII_1),
1088 PINMUX_IPSR_MODSEL_DATA(IP7_11_9, TIOC3B_A, SEL_MTU2_CH3_0),
1089 PINMUX_IPSR_DATA(IP7_11_9, HIFD13),
1090
1091 PINMUX_IPSR_DATA(IP7_14_12, DU0_DG6),
1092 PINMUX_IPSR_MODSEL_DATA(IP7_14_12, RX3_C, SEL_SCIF3_2),
1093 PINMUX_IPSR_MODSEL_DATA(IP7_14_12, RMII0_RXD0_B, SEL_RMII_1),
1094 PINMUX_IPSR_MODSEL_DATA(IP7_14_12, TIOC3C_A, SEL_MTU2_CH3_0),
1095 PINMUX_IPSR_DATA(IP7_14_12, HIFD14),
1096
1097 PINMUX_IPSR_DATA(IP7_17_15, DU0_DG7),
1098 PINMUX_IPSR_MODSEL_DATA(IP7_17_15, TX3_C, SEL_SCIF3_2),
1099 PINMUX_IPSR_MODSEL_DATA(IP7_17_15, RMII0_RXD1_B, SEL_RMII_1),
1100 PINMUX_IPSR_MODSEL_DATA(IP7_17_15, TIOC3D_A, SEL_MTU2_CH3_0),
1101 PINMUX_IPSR_DATA(IP7_17_15, HIFD15),
1102
1103 PINMUX_IPSR_DATA(IP7_20_18, DU0_DB0),
1104 PINMUX_IPSR_MODSEL_DATA(IP7_20_18, RX4_C, SEL_SCIF4_2),
1105 PINMUX_IPSR_MODSEL_DATA(IP7_20_18, RMII0_TXD_EN_B, SEL_RMII_1),
1106 PINMUX_IPSR_MODSEL_DATA(IP7_20_18, TIOC4A_A, SEL_MTU2_CH4_0),
1107 PINMUX_IPSR_DATA(IP7_20_18, HIFCS),
1108
1109 PINMUX_IPSR_DATA(IP7_23_21, DU0_DB1),
1110 PINMUX_IPSR_MODSEL_DATA(IP7_23_21, TX4_C, SEL_SCIF4_2),
1111 PINMUX_IPSR_MODSEL_DATA(IP7_23_21, RMII0_TXD0_B, SEL_RMII_1),
1112 PINMUX_IPSR_MODSEL_DATA(IP7_23_21, TIOC4B_A, SEL_MTU2_CH4_0),
1113 PINMUX_IPSR_DATA(IP7_23_21, HIFWR),
1114
1115 PINMUX_IPSR_DATA(IP7_26_24, DU0_DB2),
1116 PINMUX_IPSR_MODSEL_DATA(IP7_26_24, RX5_B, SEL_SCIF5_1),
1117 PINMUX_IPSR_MODSEL_DATA(IP7_26_24, RMII0_TXD1_B, SEL_RMII_1),
1118 PINMUX_IPSR_MODSEL_DATA(IP7_26_24, TIOC4C_A, SEL_MTU2_CH4_0),
1119
1120 PINMUX_IPSR_DATA(IP7_28_27, DU0_DB3),
1121 PINMUX_IPSR_MODSEL_DATA(IP7_28_27, TX5_B, SEL_SCIF5_1),
1122 PINMUX_IPSR_MODSEL_DATA(IP7_28_27, TIOC4D_A, SEL_MTU2_CH4_0),
1123 PINMUX_IPSR_DATA(IP7_28_27, HIFRD),
1124
1125 PINMUX_IPSR_DATA(IP7_30_29, DU0_DB4),
1126 PINMUX_IPSR_DATA(IP7_30_29, HIFINT),
1127
1128 /* IPSR8 */
1129 PINMUX_IPSR_DATA(IP8_1_0, DU0_DB5),
1130 PINMUX_IPSR_DATA(IP8_1_0, HIFDREQ),
1131
1132 PINMUX_IPSR_DATA(IP8_3_2, DU0_DB6),
1133 PINMUX_IPSR_DATA(IP8_3_2, HIFRDY),
1134
1135 PINMUX_IPSR_DATA(IP8_5_4, DU0_DB7),
1136 PINMUX_IPSR_MODSEL_DATA(IP8_5_4, SSI_SCK0_B, SEL_SSI0_1),
1137 PINMUX_IPSR_MODSEL_DATA(IP8_5_4, HIFEBL_B, SEL_HIF_1),
1138
1139 PINMUX_IPSR_DATA(IP8_7_6, DU0_DOTCLKIN),
1140 PINMUX_IPSR_MODSEL_DATA(IP8_7_6, HSPI_CS0_C, SEL_HSPI_2),
1141 PINMUX_IPSR_MODSEL_DATA(IP8_7_6, SSI_WS0_B, SEL_SSI0_1),
1142
1143 PINMUX_IPSR_DATA(IP8_9_8, DU0_DOTCLKOUT),
1144 PINMUX_IPSR_MODSEL_DATA(IP8_9_8, HSPI_CLK0_C, SEL_HSPI_2),
1145 PINMUX_IPSR_MODSEL_DATA(IP8_9_8, SSI_SDATA0_B, SEL_SSI0_1),
1146
1147 PINMUX_IPSR_DATA(IP8_11_10, DU0_EXHSYNC_DU0_HSYNC),
1148 PINMUX_IPSR_MODSEL_DATA(IP8_11_10, HSPI_TX0_C, SEL_HSPI_2),
1149 PINMUX_IPSR_MODSEL_DATA(IP8_11_10, SSI_SCK1_B, SEL_SSI1_1),
1150
1151 PINMUX_IPSR_DATA(IP8_13_12, DU0_EXVSYNC_DU0_VSYNC),
1152 PINMUX_IPSR_MODSEL_DATA(IP8_13_12, HSPI_RX0_C, SEL_HSPI_2),
1153 PINMUX_IPSR_MODSEL_DATA(IP8_13_12, SSI_WS1_B, SEL_SSI1_1),
1154
1155 PINMUX_IPSR_DATA(IP8_15_14, DU0_EXODDF_DU0_ODDF),
1156 PINMUX_IPSR_MODSEL_DATA(IP8_15_14, CAN0_RX_B, SEL_RCAN0_1),
1157 PINMUX_IPSR_MODSEL_DATA(IP8_15_14, HSCK0_B, SEL_HSCIF_1),
1158 PINMUX_IPSR_MODSEL_DATA(IP8_15_14, SSI_SDATA1_B, SEL_SSI1_1),
1159
1160 PINMUX_IPSR_DATA(IP8_17_16, DU0_DISP),
1161 PINMUX_IPSR_MODSEL_DATA(IP8_17_16, CAN0_TX_B, SEL_RCAN0_1),
1162 PINMUX_IPSR_MODSEL_DATA(IP8_17_16, HRX0_B, SEL_HSCIF_1),
1163 PINMUX_IPSR_MODSEL_DATA(IP8_17_16, AUDIO_CLKA_B, SEL_AUDIO_CLKA_1),
1164
1165 PINMUX_IPSR_DATA(IP8_19_18, DU0_CDE),
1166 PINMUX_IPSR_MODSEL_DATA(IP8_19_18, HTX0_B, SEL_HSCIF_1),
1167 PINMUX_IPSR_MODSEL_DATA(IP8_19_18, AUDIO_CLKB_B, SEL_AUDIO_CLKB_1),
1168 PINMUX_IPSR_MODSEL_DATA(IP8_19_18, LCD_VCPWC_B, SEL_LCDC_1),
1169
1170 PINMUX_IPSR_MODSEL_DATA(IP8_22_20, IRQ0_A, SEL_INTC_0),
1171 PINMUX_IPSR_MODSEL_DATA(IP8_22_20, HSPI_TX_B, SEL_HSPI_1),
1172 PINMUX_IPSR_MODSEL_DATA(IP8_22_20, RX3_E, SEL_SCIF3_4),
1173 PINMUX_IPSR_DATA(IP8_22_20, ET0_ERXD0),
1174
1175 PINMUX_IPSR_MODSEL_DATA(IP8_25_23, IRQ1_A, SEL_INTC_0),
1176 PINMUX_IPSR_MODSEL_DATA(IP8_25_23, HSPI_RX_B, SEL_HSPI_1),
1177 PINMUX_IPSR_MODSEL_DATA(IP8_25_23, TX3_E, SEL_SCIF3_4),
1178 PINMUX_IPSR_DATA(IP8_25_23, ET0_ERXD1),
1179
1180 PINMUX_IPSR_MODSEL_DATA(IP8_27_26, IRQ2_A, SEL_INTC_0),
1181 PINMUX_IPSR_MODSEL_DATA(IP8_27_26, CTS0_A, SEL_SCIF0_0),
1182 PINMUX_IPSR_MODSEL_DATA(IP8_27_26, HCTS0_B, SEL_HSCIF_1),
1183 PINMUX_IPSR_MODSEL_DATA(IP8_27_26, ET0_ERXD2_A, SEL_ET0_0),
1184
1185 PINMUX_IPSR_MODSEL_DATA(IP8_29_28, IRQ3_A, SEL_INTC_0),
1186 PINMUX_IPSR_MODSEL_DATA(IP8_29_28, RTS0_A, SEL_SCIF0_0),
1187 PINMUX_IPSR_MODSEL_DATA(IP8_29_28, HRTS0_B, SEL_HSCIF_1),
1188 PINMUX_IPSR_MODSEL_DATA(IP8_29_28, ET0_ERXD3_A, SEL_ET0_0),
1189
1190 /* IPSR9 */
1191 PINMUX_IPSR_MODSEL_DATA(IP9_1_0, VI1_CLK_A, SEL_VIN1_0),
1192 PINMUX_IPSR_MODSEL_DATA(IP9_1_0, FD0_B, SEL_FLCTL_1),
1193 PINMUX_IPSR_MODSEL_DATA(IP9_1_0, LCD_DATA0_B, SEL_LCDC_1),
1194
1195 PINMUX_IPSR_MODSEL_DATA(IP9_3_2, VI1_0_A, SEL_VIN1_0),
1196 PINMUX_IPSR_MODSEL_DATA(IP9_3_2, FD1_B, SEL_FLCTL_1),
1197 PINMUX_IPSR_MODSEL_DATA(IP9_3_2, LCD_DATA1_B, SEL_LCDC_1),
1198
1199 PINMUX_IPSR_MODSEL_DATA(IP9_5_4, VI1_1_A, SEL_VIN1_0),
1200 PINMUX_IPSR_MODSEL_DATA(IP9_5_4, FD2_B, SEL_FLCTL_1),
1201 PINMUX_IPSR_MODSEL_DATA(IP9_5_4, LCD_DATA2_B, SEL_LCDC_1),
1202
1203 PINMUX_IPSR_MODSEL_DATA(IP9_7_6, VI1_2_A, SEL_VIN1_0),
1204 PINMUX_IPSR_MODSEL_DATA(IP9_7_6, FD3_B, SEL_FLCTL_1),
1205 PINMUX_IPSR_MODSEL_DATA(IP9_7_6, LCD_DATA3_B, SEL_LCDC_1),
1206
1207 PINMUX_IPSR_MODSEL_DATA(IP9_9_8, VI1_3_A, SEL_VIN1_0),
1208 PINMUX_IPSR_MODSEL_DATA(IP9_9_8, FD4_B, SEL_FLCTL_1),
1209 PINMUX_IPSR_MODSEL_DATA(IP9_9_8, LCD_DATA4_B, SEL_LCDC_1),
1210
1211 PINMUX_IPSR_MODSEL_DATA(IP9_11_10, VI1_4_A, SEL_VIN1_0),
1212 PINMUX_IPSR_MODSEL_DATA(IP9_11_10, FD5_B, SEL_FLCTL_1),
1213 PINMUX_IPSR_MODSEL_DATA(IP9_11_10, LCD_DATA5_B, SEL_LCDC_1),
1214
1215 PINMUX_IPSR_MODSEL_DATA(IP9_13_12, VI1_5_A, SEL_VIN1_0),
1216 PINMUX_IPSR_MODSEL_DATA(IP9_13_12, FD6_B, SEL_FLCTL_1),
1217 PINMUX_IPSR_MODSEL_DATA(IP9_13_12, LCD_DATA6_B, SEL_LCDC_1),
1218
1219 PINMUX_IPSR_MODSEL_DATA(IP9_15_14, VI1_6_A, SEL_VIN1_0),
1220 PINMUX_IPSR_MODSEL_DATA(IP9_15_14, FD7_B, SEL_FLCTL_1),
1221 PINMUX_IPSR_MODSEL_DATA(IP9_15_14, LCD_DATA7_B, SEL_LCDC_1),
1222
1223 PINMUX_IPSR_MODSEL_DATA(IP9_17_16, VI1_7_A, SEL_VIN1_0),
1224 PINMUX_IPSR_MODSEL_DATA(IP9_17_16, FCE_B, SEL_FLCTL_1),
1225 PINMUX_IPSR_MODSEL_DATA(IP9_17_16, LCD_DATA8_B, SEL_LCDC_1),
1226
1227 PINMUX_IPSR_MODSEL_DATA(IP9_19_18, SSI_SCK0_A, SEL_SSI0_0),
1228 PINMUX_IPSR_MODSEL_DATA(IP9_19_18, TIOC1A_B, SEL_MTU2_CH1_1),
1229 PINMUX_IPSR_MODSEL_DATA(IP9_19_18, LCD_DATA9_B, SEL_LCDC_1),
1230
1231 PINMUX_IPSR_MODSEL_DATA(IP9_21_20, SSI_WS0_A, SEL_SSI0_0),
1232 PINMUX_IPSR_MODSEL_DATA(IP9_21_20, TIOC1B_B, SEL_MTU2_CH1_1),
1233 PINMUX_IPSR_MODSEL_DATA(IP9_21_20, LCD_DATA10_B, SEL_LCDC_1),
1234
1235 PINMUX_IPSR_MODSEL_DATA(IP9_23_22, SSI_SDATA0_A, SEL_SSI0_0),
1236 PINMUX_IPSR_MODSEL_DATA(IP9_23_22, VI1_0_B, SEL_VIN1_1),
1237 PINMUX_IPSR_MODSEL_DATA(IP9_23_22, TIOC2A_B, SEL_MTU2_CH2_1),
1238 PINMUX_IPSR_MODSEL_DATA(IP9_23_22, LCD_DATA11_B, SEL_LCDC_1),
1239
1240 PINMUX_IPSR_MODSEL_DATA(IP9_25_24, SSI_SCK1_A, SEL_SSI1_0),
1241 PINMUX_IPSR_MODSEL_DATA(IP9_25_24, VI1_1_B, SEL_VIN1_1),
1242 PINMUX_IPSR_MODSEL_DATA(IP9_25_24, TIOC2B_B, SEL_MTU2_CH2_1),
1243 PINMUX_IPSR_MODSEL_DATA(IP9_25_24, LCD_DATA12_B, SEL_LCDC_1),
1244
1245 PINMUX_IPSR_MODSEL_DATA(IP9_27_26, SSI_WS1_A, SEL_SSI1_0),
1246 PINMUX_IPSR_MODSEL_DATA(IP9_27_26, VI1_2_B, SEL_VIN1_1),
1247 PINMUX_IPSR_MODSEL_DATA(IP9_27_26, LCD_DATA13_B, SEL_LCDC_1),
1248
1249 PINMUX_IPSR_MODSEL_DATA(IP9_29_28, SSI_SDATA1_A, SEL_SSI1_0),
1250 PINMUX_IPSR_MODSEL_DATA(IP9_29_28, VI1_3_B, SEL_VIN1_1),
1251 PINMUX_IPSR_MODSEL_DATA(IP9_29_28, LCD_DATA14_B, SEL_LCDC_1),
1252
1253 /* IPSE10 */
1254 PINMUX_IPSR_DATA(IP10_2_0, SSI_SCK23),
1255 PINMUX_IPSR_MODSEL_DATA(IP10_2_0, VI1_4_B, SEL_VIN1_1),
1256 PINMUX_IPSR_MODSEL_DATA(IP10_2_0, RX1_D, SEL_SCIF1_3),
1257 PINMUX_IPSR_MODSEL_DATA(IP10_2_0, FCLE_B, SEL_FLCTL_1),
1258 PINMUX_IPSR_MODSEL_DATA(IP10_2_0, LCD_DATA15_B, SEL_LCDC_1),
1259
1260 PINMUX_IPSR_DATA(IP10_5_3, SSI_WS23),
1261 PINMUX_IPSR_MODSEL_DATA(IP10_5_3, VI1_5_B, SEL_VIN1_1),
1262 PINMUX_IPSR_MODSEL_DATA(IP10_5_3, TX1_D, SEL_SCIF1_3),
1263 PINMUX_IPSR_MODSEL_DATA(IP10_5_3, HSCK0_C, SEL_HSCIF_2),
1264 PINMUX_IPSR_MODSEL_DATA(IP10_5_3, FALE_B, SEL_FLCTL_1),
1265 PINMUX_IPSR_MODSEL_DATA(IP10_5_3, LCD_DON_B, SEL_LCDC_1),
1266
1267 PINMUX_IPSR_DATA(IP10_8_6, SSI_SDATA2),
1268 PINMUX_IPSR_MODSEL_DATA(IP10_8_6, VI1_6_B, SEL_VIN1_1),
1269 PINMUX_IPSR_MODSEL_DATA(IP10_8_6, HRX0_C, SEL_HSCIF_2),
1270 PINMUX_IPSR_MODSEL_DATA(IP10_8_6, FRE_B, SEL_FLCTL_1),
1271 PINMUX_IPSR_MODSEL_DATA(IP10_8_6, LCD_CL1_B, SEL_LCDC_1),
1272
1273 PINMUX_IPSR_DATA(IP10_11_9, SSI_SDATA3),
1274 PINMUX_IPSR_MODSEL_DATA(IP10_11_9, VI1_7_B, SEL_VIN1_1),
1275 PINMUX_IPSR_MODSEL_DATA(IP10_11_9, HTX0_C, SEL_HSCIF_2),
1276 PINMUX_IPSR_MODSEL_DATA(IP10_11_9, FWE_B, SEL_FLCTL_1),
1277 PINMUX_IPSR_MODSEL_DATA(IP10_11_9, LCD_CL2_B, SEL_LCDC_1),
1278
1279 PINMUX_IPSR_MODSEL_DATA(IP10_14_12, AUDIO_CLKA_A, SEL_AUDIO_CLKA_0),
1280 PINMUX_IPSR_MODSEL_DATA(IP10_14_12, VI1_CLK_B, SEL_VIN1_1),
1281 PINMUX_IPSR_MODSEL_DATA(IP10_14_12, SCK1_D, SEL_SCIF1_3),
1282 PINMUX_IPSR_MODSEL_DATA(IP10_14_12, IECLK_B, SEL_IEBUS_1),
1283 PINMUX_IPSR_MODSEL_DATA(IP10_14_12, LCD_FLM_B, SEL_LCDC_1),
1284
1285 PINMUX_IPSR_MODSEL_DATA(IP10_15, AUDIO_CLKB_A, SEL_AUDIO_CLKB_0),
1286 PINMUX_IPSR_MODSEL_DATA(IP10_15, LCD_CLK_B, SEL_LCDC_1),
1287
1288 PINMUX_IPSR_DATA(IP10_18_16, AUDIO_CLKC),
1289 PINMUX_IPSR_MODSEL_DATA(IP10_18_16, SCK1_E, SEL_SCIF1_4),
1290 PINMUX_IPSR_MODSEL_DATA(IP10_18_16, HCTS0_C, SEL_HSCIF_2),
1291 PINMUX_IPSR_MODSEL_DATA(IP10_18_16, FRB_B, SEL_FLCTL_1),
1292 PINMUX_IPSR_MODSEL_DATA(IP10_18_16, LCD_VEPWC_B, SEL_LCDC_1),
1293
1294 PINMUX_IPSR_DATA(IP10_21_19, AUDIO_CLKOUT),
1295 PINMUX_IPSR_MODSEL_DATA(IP10_21_19, TX1_E, SEL_SCIF1_4),
1296 PINMUX_IPSR_MODSEL_DATA(IP10_21_19, HRTS0_C, SEL_HSCIF_2),
1297 PINMUX_IPSR_MODSEL_DATA(IP10_21_19, FSE_B, SEL_FLCTL_1),
1298 PINMUX_IPSR_MODSEL_DATA(IP10_21_19, LCD_M_DISP_B, SEL_LCDC_1),
1299
1300 PINMUX_IPSR_MODSEL_DATA(IP10_22, CAN_CLK_A, SEL_RCAN_CLK_0),
1301 PINMUX_IPSR_MODSEL_DATA(IP10_22, RX4_D, SEL_SCIF4_3),
1302
1303 PINMUX_IPSR_MODSEL_DATA(IP10_24_23, CAN0_TX_A, SEL_RCAN0_0),
1304 PINMUX_IPSR_MODSEL_DATA(IP10_24_23, TX4_D, SEL_SCIF4_3),
1305 PINMUX_IPSR_DATA(IP10_24_23, MLB_CLK),
1306
1307 PINMUX_IPSR_MODSEL_DATA(IP10_25, CAN1_RX_A, SEL_RCAN1_0),
1308 PINMUX_IPSR_MODSEL_DATA(IP10_25, IRQ1_B, SEL_INTC_1),
1309
1310 PINMUX_IPSR_MODSEL_DATA(IP10_27_26, CAN0_RX_A, SEL_RCAN0_0),
1311 PINMUX_IPSR_MODSEL_DATA(IP10_27_26, IRQ0_B, SEL_INTC_1),
1312 PINMUX_IPSR_DATA(IP10_27_26, MLB_SIG),
1313
1314 PINMUX_IPSR_MODSEL_DATA(IP10_29_28, CAN1_TX_A, SEL_RCAN1_0),
1315 PINMUX_IPSR_MODSEL_DATA(IP10_29_28, TX5_C, SEL_SCIF1_2),
1316 PINMUX_IPSR_DATA(IP10_29_28, MLB_DAT),
1317
1318 /* IPSR11 */
1319 PINMUX_IPSR_DATA(IP11_0, SCL1),
1320 PINMUX_IPSR_MODSEL_DATA(IP11_0, SCIF_CLK_C, SEL_SCIF_CLK_2),
1321
1322 PINMUX_IPSR_DATA(IP11_1, SDA1),
1323 PINMUX_IPSR_MODSEL_DATA(IP11_0, RX1_E, SEL_SCIF1_4),
1324
1325 PINMUX_IPSR_DATA(IP11_2, SDA0),
1326 PINMUX_IPSR_MODSEL_DATA(IP11_2, HIFEBL_A, SEL_HIF_0),
1327
1328 PINMUX_IPSR_DATA(IP11_3, SDSELF),
1329 PINMUX_IPSR_MODSEL_DATA(IP11_3, RTS1_E, SEL_SCIF1_3),
1330
1331 PINMUX_IPSR_MODSEL_DATA(IP11_6_4, SCIF_CLK_A, SEL_SCIF_CLK_0),
1332 PINMUX_IPSR_MODSEL_DATA(IP11_6_4, HSPI_CLK_A, SEL_HSPI_0),
1333 PINMUX_IPSR_DATA(IP11_6_4, VI0_CLK),
1334 PINMUX_IPSR_MODSEL_DATA(IP11_6_4, RMII0_TXD0_A, SEL_RMII_0),
1335 PINMUX_IPSR_DATA(IP11_6_4, ET0_ERXD4),
1336
1337 PINMUX_IPSR_MODSEL_DATA(IP11_9_7, SCK0_A, SEL_SCIF0_0),
1338 PINMUX_IPSR_MODSEL_DATA(IP11_9_7, HSPI_CS_A, SEL_HSPI_0),
1339 PINMUX_IPSR_DATA(IP11_9_7, VI0_CLKENB),
1340 PINMUX_IPSR_MODSEL_DATA(IP11_9_7, RMII0_TXD1_A, SEL_RMII_0),
1341 PINMUX_IPSR_DATA(IP11_9_7, ET0_ERXD5),
1342
1343 PINMUX_IPSR_MODSEL_DATA(IP11_11_10, RX0_A, SEL_SCIF0_0),
1344 PINMUX_IPSR_MODSEL_DATA(IP11_11_10, HSPI_RX_A, SEL_HSPI_0),
1345 PINMUX_IPSR_MODSEL_DATA(IP11_11_10, RMII0_RXD0_A, SEL_RMII_0),
1346 PINMUX_IPSR_DATA(IP11_11_10, ET0_ERXD6),
1347
1348 PINMUX_IPSR_MODSEL_DATA(IP11_12, TX0_A, SEL_SCIF0_0),
1349 PINMUX_IPSR_MODSEL_DATA(IP11_12, HSPI_TX_A, SEL_HSPI_0),
1350
1351 PINMUX_IPSR_DATA(IP11_15_13, PENC1),
1352 PINMUX_IPSR_MODSEL_DATA(IP11_15_13, TX3_D, SEL_SCIF3_3),
1353 PINMUX_IPSR_MODSEL_DATA(IP11_15_13, CAN1_TX_B, SEL_RCAN1_1),
1354 PINMUX_IPSR_MODSEL_DATA(IP11_15_13, TX5_D, SEL_SCIF5_3),
1355 PINMUX_IPSR_MODSEL_DATA(IP11_15_13, IETX_B, SEL_IEBUS_1),
1356
1357 PINMUX_IPSR_DATA(IP11_18_16, USB_OVC1),
1358 PINMUX_IPSR_MODSEL_DATA(IP11_18_16, RX3_D, SEL_SCIF3_3),
1359 PINMUX_IPSR_MODSEL_DATA(IP11_18_16, CAN1_RX_B, SEL_RCAN1_1),
1360 PINMUX_IPSR_MODSEL_DATA(IP11_18_16, RX5_D, SEL_SCIF5_3),
1361 PINMUX_IPSR_MODSEL_DATA(IP11_18_16, IERX_B, SEL_IEBUS_1),
1362
1363 PINMUX_IPSR_DATA(IP11_20_19, DREQ0),
1364 PINMUX_IPSR_MODSEL_DATA(IP11_20_19, SD1_CLK_A, SEL_SDHI1_0),
1365 PINMUX_IPSR_DATA(IP11_20_19, ET0_TX_EN),
1366
1367 PINMUX_IPSR_DATA(IP11_22_21, DACK0),
1368 PINMUX_IPSR_MODSEL_DATA(IP11_22_21, SD1_DAT3_A, SEL_SDHI1_0),
1369 PINMUX_IPSR_DATA(IP11_22_21, ET0_TX_ER),
1370
1371 PINMUX_IPSR_DATA(IP11_25_23, DREQ1),
1372 PINMUX_IPSR_MODSEL_DATA(IP11_25_23, HSPI_CLK_B, SEL_HSPI_1),
1373 PINMUX_IPSR_MODSEL_DATA(IP11_25_23, RX4_B, SEL_SCIF4_1),
1374 PINMUX_IPSR_MODSEL_DATA(IP11_25_23, ET0_PHY_INT_C, SEL_ET0_CTL_0),
1375 PINMUX_IPSR_MODSEL_DATA(IP11_25_23, ET0_TX_CLK_A, SEL_ET0_0),
1376
1377 PINMUX_IPSR_DATA(IP11_27_26, DACK1),
1378 PINMUX_IPSR_MODSEL_DATA(IP11_27_26, HSPI_CS_B, SEL_HSPI_1),
1379 PINMUX_IPSR_MODSEL_DATA(IP11_27_26, TX4_B, SEL_SCIF3_1),
1380 PINMUX_IPSR_MODSEL_DATA(IP11_27_26, ET0_RX_CLK_A, SEL_ET0_0),
1381
1382 PINMUX_IPSR_DATA(IP11_28, PRESETOUT),
1383 PINMUX_IPSR_DATA(IP11_28, ST_CLKOUT),
1384};
1385
1386static struct pinmux_gpio pinmux_gpios[] = {
1387 PINMUX_GPIO_GP_ALL(),
1388
1389 GPIO_FN(CLKOUT), GPIO_FN(BS), GPIO_FN(CS0), GPIO_FN(EX_CS0),
1390 GPIO_FN(RD), GPIO_FN(WE0), GPIO_FN(WE1),
1391 GPIO_FN(SCL0), GPIO_FN(PENC0), GPIO_FN(USB_OVC0),
1392 GPIO_FN(IRQ2_B), GPIO_FN(IRQ3_B),
1393
1394 /* IPSR0 */
1395 GPIO_FN(A0), GPIO_FN(ST0_CLKIN), GPIO_FN(LCD_DATA0_A),
1396 GPIO_FN(TCLKA_C),
1397 GPIO_FN(A1), GPIO_FN(ST0_REQ), GPIO_FN(LCD_DATA1_A),
1398 GPIO_FN(TCLKB_C),
1399 GPIO_FN(A2), GPIO_FN(ST0_SYC), GPIO_FN(LCD_DATA2_A),
1400 GPIO_FN(TCLKC_C),
1401 GPIO_FN(A3), GPIO_FN(ST0_VLD), GPIO_FN(LCD_DATA3_A),
1402 GPIO_FN(TCLKD_C),
1403 GPIO_FN(A4), GPIO_FN(ST0_D0), GPIO_FN(LCD_DATA4_A),
1404 GPIO_FN(TIOC0A_C),
1405 GPIO_FN(A5), GPIO_FN(ST0_D1), GPIO_FN(LCD_DATA5_A),
1406 GPIO_FN(TIOC0B_C),
1407 GPIO_FN(A6), GPIO_FN(ST0_D2), GPIO_FN(LCD_DATA6_A),
1408 GPIO_FN(TIOC0C_C),
1409 GPIO_FN(A7), GPIO_FN(ST0_D3), GPIO_FN(LCD_DATA7_A),
1410 GPIO_FN(TIOC0D_C),
1411 GPIO_FN(A8), GPIO_FN(ST0_D4), GPIO_FN(LCD_DATA8_A),
1412 GPIO_FN(TIOC1A_C),
1413 GPIO_FN(A9), GPIO_FN(ST0_D5), GPIO_FN(LCD_DATA9_A),
1414 GPIO_FN(TIOC1B_C),
1415 GPIO_FN(A10), GPIO_FN(ST0_D6), GPIO_FN(LCD_DATA10_A),
1416 GPIO_FN(TIOC2A_C),
1417 GPIO_FN(A11), GPIO_FN(ST0_D7), GPIO_FN(LCD_DATA11_A),
1418 GPIO_FN(TIOC2B_C),
1419 GPIO_FN(A12), GPIO_FN(LCD_DATA12_A), GPIO_FN(TIOC3A_C),
1420 GPIO_FN(A13), GPIO_FN(LCD_DATA13_A), GPIO_FN(TIOC3B_C),
1421 GPIO_FN(A14), GPIO_FN(LCD_DATA14_A), GPIO_FN(TIOC3C_C),
1422 GPIO_FN(A15), GPIO_FN(ST0_VCO_CLKIN), GPIO_FN(LCD_DATA15_A),
1423 GPIO_FN(TIOC3D_C),
1424
1425 /* IPSR1 */
1426 GPIO_FN(A16), GPIO_FN(ST0_PWM), GPIO_FN(LCD_DON_A),
1427 GPIO_FN(TIOC4A_C),
1428 GPIO_FN(A17), GPIO_FN(ST1_VCO_CLKIN), GPIO_FN(LCD_CL1_A),
1429 GPIO_FN(TIOC4B_C),
1430 GPIO_FN(A18), GPIO_FN(ST1_PWM), GPIO_FN(LCD_CL2_A),
1431 GPIO_FN(TIOC4C_C),
1432 GPIO_FN(A19), GPIO_FN(ST1_CLKIN), GPIO_FN(LCD_CLK_A),
1433 GPIO_FN(TIOC4D_C),
1434 GPIO_FN(A20), GPIO_FN(ST1_REQ), GPIO_FN(LCD_FLM_A),
1435 GPIO_FN(A21), GPIO_FN(ST1_SYC), GPIO_FN(LCD_VCPWC_A),
1436 GPIO_FN(A22), GPIO_FN(ST1_VLD), GPIO_FN(LCD_VEPWC_A),
1437 GPIO_FN(A23), GPIO_FN(ST1_D0), GPIO_FN(LCD_M_DISP_A),
1438 GPIO_FN(A24), GPIO_FN(RX2_D), GPIO_FN(ST1_D1),
1439 GPIO_FN(A25), GPIO_FN(TX2_D), GPIO_FN(ST1_D2),
1440 GPIO_FN(D0), GPIO_FN(SD0_DAT0_A), GPIO_FN(MMC_D0_A),
1441 GPIO_FN(ST1_D3), GPIO_FN(FD0_A),
1442 GPIO_FN(D1), GPIO_FN(SD0_DAT1_A), GPIO_FN(MMC_D1_A),
1443 GPIO_FN(ST1_D4), GPIO_FN(FD1_A),
1444 GPIO_FN(D2), GPIO_FN(SD0_DAT2_A), GPIO_FN(MMC_D2_A),
1445 GPIO_FN(ST1_D5), GPIO_FN(FD2_A),
1446 GPIO_FN(D3), GPIO_FN(SD0_DAT3_A), GPIO_FN(MMC_D3_A),
1447 GPIO_FN(ST1_D6), GPIO_FN(FD3_A),
1448
1449 /* IPSR2 */
1450 GPIO_FN(D4), GPIO_FN(SD0_CD_A), GPIO_FN(MMC_D4_A), GPIO_FN(ST1_D7),
1451 GPIO_FN(FD4_A),
1452 GPIO_FN(D5), GPIO_FN(SD0_WP_A), GPIO_FN(MMC_D5_A), GPIO_FN(FD5_A),
1453 GPIO_FN(D6), GPIO_FN(RSPI_RSPCK_A), GPIO_FN(MMC_D6_A),
1454 GPIO_FN(QSPCLK_A),
1455 GPIO_FN(FD6_A),
1456 GPIO_FN(D7), GPIO_FN(RSPI_SSL_A), GPIO_FN(MMC_D7_A), GPIO_FN(QSSL_A),
1457 GPIO_FN(FD7_A),
1458 GPIO_FN(D8), GPIO_FN(SD0_CLK_A), GPIO_FN(MMC_CLK_A), GPIO_FN(QIO2_A),
1459 GPIO_FN(FCE_A), GPIO_FN(ET0_GTX_CLK_B),
1460 GPIO_FN(D9), GPIO_FN(SD0_CMD_A), GPIO_FN(MMC_CMD_A), GPIO_FN(QIO3_A),
1461 GPIO_FN(FCLE_A), GPIO_FN(ET0_ETXD1_B),
1462 GPIO_FN(D10), GPIO_FN(RSPI_MOSI_A), GPIO_FN(QMO_QIO0_A),
1463 GPIO_FN(FALE_A), GPIO_FN(ET0_ETXD2_B),
1464 GPIO_FN(D11), GPIO_FN(RSPI_MISO_A), GPIO_FN(QMI_QIO1_A), GPIO_FN(FRE_A),
1465 GPIO_FN(ET0_ETXD3_B),
1466 GPIO_FN(D12), GPIO_FN(FWE_A), GPIO_FN(ET0_ETXD5_B),
1467 GPIO_FN(D13), GPIO_FN(RX2_B), GPIO_FN(FRB_A), GPIO_FN(ET0_ETXD6_B),
1468 GPIO_FN(D14), GPIO_FN(TX2_B), GPIO_FN(FSE_A), GPIO_FN(ET0_TX_CLK_B),
1469
1470 /* IPSR3 */
1471 GPIO_FN(D15), GPIO_FN(SCK2_B),
1472 GPIO_FN(CS1_A26), GPIO_FN(QIO3_B),
1473 GPIO_FN(EX_CS1), GPIO_FN(RX3_B), GPIO_FN(ATACS0), GPIO_FN(QIO2_B),
1474 GPIO_FN(ET0_ETXD0),
1475 GPIO_FN(EX_CS2), GPIO_FN(TX3_B), GPIO_FN(ATACS1), GPIO_FN(QSPCLK_B),
1476 GPIO_FN(ET0_GTX_CLK_A),
1477 GPIO_FN(EX_CS3), GPIO_FN(SD1_CD_A), GPIO_FN(ATARD), GPIO_FN(QMO_QIO0_B),
1478 GPIO_FN(ET0_ETXD1_A),
1479 GPIO_FN(EX_CS4), GPIO_FN(SD1_WP_A), GPIO_FN(ATAWR), GPIO_FN(QMI_QIO1_B),
1480 GPIO_FN(ET0_ETXD2_A),
1481 GPIO_FN(EX_CS5), GPIO_FN(SD1_CMD_A), GPIO_FN(ATADIR), GPIO_FN(QSSL_B),
1482 GPIO_FN(ET0_ETXD3_A),
1483 GPIO_FN(RD_WR), GPIO_FN(TCLK1_B),
1484 GPIO_FN(EX_WAIT0), GPIO_FN(TCLK1_B),
1485 GPIO_FN(EX_WAIT1), GPIO_FN(SD1_DAT0_A), GPIO_FN(DREQ2),
1486 GPIO_FN(CAN1_TX_C), GPIO_FN(ET0_LINK_C), GPIO_FN(ET0_ETXD5_A),
1487 GPIO_FN(EX_WAIT2), GPIO_FN(SD1_DAT1_A), GPIO_FN(DACK2),
1488 GPIO_FN(CAN1_RX_C), GPIO_FN(ET0_MAGIC_C), GPIO_FN(ET0_ETXD6_A),
1489 GPIO_FN(DRACK0), GPIO_FN(SD1_DAT2_A), GPIO_FN(ATAG), GPIO_FN(TCLK1_A),
1490 GPIO_FN(ET0_ETXD7),
1491
1492 /* IPSR4 */
1493 GPIO_FN(HCTS0_A), GPIO_FN(CTS1_A), GPIO_FN(VI0_FIELD),
1494 GPIO_FN(RMII0_RXD1_A), GPIO_FN(ET0_ERXD7),
1495 GPIO_FN(HRTS0_A), GPIO_FN(RTS1_A), GPIO_FN(VI0_HSYNC),
1496 GPIO_FN(RMII0_TXD_EN_A), GPIO_FN(ET0_RX_DV),
1497 GPIO_FN(HSCK0_A), GPIO_FN(SCK1_A), GPIO_FN(VI0_VSYNC),
1498 GPIO_FN(RMII0_RX_ER_A), GPIO_FN(ET0_RX_ER),
1499 GPIO_FN(HRX0_A), GPIO_FN(RX1_A), GPIO_FN(VI0_DATA0_VI0_B0),
1500 GPIO_FN(RMII0_CRS_DV_A), GPIO_FN(ET0_CRS),
1501 GPIO_FN(HTX0_A), GPIO_FN(TX1_A), GPIO_FN(VI0_DATA1_VI0_B1),
1502 GPIO_FN(RMII0_MDC_A), GPIO_FN(ET0_COL),
1503 GPIO_FN(CTS0_B), GPIO_FN(VI0_DATA2_VI0_B2), GPIO_FN(RMII0_MDIO_A),
1504 GPIO_FN(ET0_MDC),
1505 GPIO_FN(RTS0_B), GPIO_FN(VI0_DATA3_VI0_B3), GPIO_FN(ET0_MDIO_A),
1506 GPIO_FN(SCK1_B), GPIO_FN(VI0_DATA4_VI0_B4), GPIO_FN(ET0_LINK_A),
1507 GPIO_FN(RX1_B), GPIO_FN(VI0_DATA5_VI0_B5), GPIO_FN(ET0_MAGIC_A),
1508 GPIO_FN(TX1_B), GPIO_FN(VI0_DATA6_VI0_G0), GPIO_FN(ET0_PHY_INT_A),
1509 GPIO_FN(CTS1_B), GPIO_FN(VI0_DATA7_VI0_G1),
1510 GPIO_FN(RTS1_B), GPIO_FN(VI0_G2),
1511 GPIO_FN(SCK2_A), GPIO_FN(VI0_G3),
1512
1513 /* IPSR5 */
1514 GPIO_FN(REF50CK), GPIO_FN(CTS1_E), GPIO_FN(HCTS0_D),
1515 GPIO_FN(REF125CK), GPIO_FN(ADTRG), GPIO_FN(RX5_C),
1516 GPIO_FN(SD2_WP_A), GPIO_FN(TX5_A), GPIO_FN(VI0_R5),
1517 GPIO_FN(SD2_CD_A), GPIO_FN(RX5_A), GPIO_FN(VI0_R4),
1518 GPIO_FN(ET0_PHY_INT_B),
1519 GPIO_FN(SD2_DAT3_A), GPIO_FN(TX4_A), GPIO_FN(VI0_R3),
1520 GPIO_FN(ET0_MAGIC_B),
1521 GPIO_FN(SD2_DAT2_A), GPIO_FN(RX4_A), GPIO_FN(VI0_R2),
1522 GPIO_FN(ET0_LINK_B),
1523 GPIO_FN(SD2_DAT1_A), GPIO_FN(TX3_A), GPIO_FN(VI0_R1),
1524 GPIO_FN(ET0_MDIO_B),
1525 GPIO_FN(SD2_DAT0_A), GPIO_FN(RX3_A), GPIO_FN(VI0_R0),
1526 GPIO_FN(ET0_ERXD3_B),
1527 GPIO_FN(SD2_CMD_A), GPIO_FN(TX2_A), GPIO_FN(VI0_G5),
1528 GPIO_FN(ET0_ERXD2_B),
1529 GPIO_FN(SD2_CLK_A), GPIO_FN(RX2_A), GPIO_FN(VI0_G4),
1530 GPIO_FN(ET0_RX_CLK_B),
1531
1532 /* IPSR6 */
1533 GPIO_FN(DU0_DG1), GPIO_FN(CTS1_C), GPIO_FN(HRTS0_D),
1534 GPIO_FN(TIOC1B_A), GPIO_FN(HIFD09),
1535 GPIO_FN(DU0_DG0), GPIO_FN(TX1_C), GPIO_FN(HSCK0_D),
1536 GPIO_FN(IECLK_A), GPIO_FN(TIOC1A_A), GPIO_FN(HIFD08),
1537 GPIO_FN(DU0_DR7), GPIO_FN(RX1_C), GPIO_FN(TIOC0D_A),
1538 GPIO_FN(HIFD07),
1539 GPIO_FN(DU0_DR6), GPIO_FN(SCK1_C), GPIO_FN(TIOC0C_A),
1540 GPIO_FN(HIFD06),
1541 GPIO_FN(DU0_DR5), GPIO_FN(RTS0_C), GPIO_FN(TIOC0B_A),
1542 GPIO_FN(HIFD05),
1543 GPIO_FN(DU0_DR4), GPIO_FN(CTS0_C), GPIO_FN(TIOC0A_A),
1544 GPIO_FN(HIFD04),
1545 GPIO_FN(DU0_DR3), GPIO_FN(TX0_B), GPIO_FN(TCLKD_A), GPIO_FN(HIFD03),
1546 GPIO_FN(DU0_DR2), GPIO_FN(RX0_B), GPIO_FN(TCLKC_A), GPIO_FN(HIFD02),
1547 GPIO_FN(DU0_DR1), GPIO_FN(SCK0_B), GPIO_FN(HTX0_D),
1548 GPIO_FN(IERX_A), GPIO_FN(TCLKB_A), GPIO_FN(HIFD01),
1549 GPIO_FN(DU0_DR0), GPIO_FN(SCIF_CLK_B), GPIO_FN(HRX0_D),
1550 GPIO_FN(IETX_A), GPIO_FN(TCLKA_A), GPIO_FN(HIFD00),
1551
1552 /* IPSR7 */
1553 GPIO_FN(DU0_DB4), GPIO_FN(HIFINT),
1554 GPIO_FN(DU0_DB3), GPIO_FN(TX5_B), GPIO_FN(TIOC4D_A), GPIO_FN(HIFRD),
1555 GPIO_FN(DU0_DB2), GPIO_FN(RX5_B), GPIO_FN(RMII0_TXD1_B),
1556 GPIO_FN(TIOC4C_A), GPIO_FN(HIFWR),
1557 GPIO_FN(DU0_DB1), GPIO_FN(TX4_C), GPIO_FN(RMII0_TXD0_B),
1558 GPIO_FN(TIOC4B_A), GPIO_FN(HIFRS),
1559 GPIO_FN(DU0_DB0), GPIO_FN(RX4_C), GPIO_FN(RMII0_TXD_EN_B),
1560 GPIO_FN(TIOC4A_A), GPIO_FN(HIFCS),
1561 GPIO_FN(DU0_DG7), GPIO_FN(TX3_C), GPIO_FN(RMII0_RXD1_B),
1562 GPIO_FN(TIOC3D_A), GPIO_FN(HIFD15),
1563 GPIO_FN(DU0_DG6), GPIO_FN(RX3_C), GPIO_FN(RMII0_RXD0_B),
1564 GPIO_FN(TIOC3C_A), GPIO_FN(HIFD14),
1565 GPIO_FN(DU0_DG5), GPIO_FN(TX2_C), GPIO_FN(RMII0_RX_ER_B),
1566 GPIO_FN(TIOC3B_A), GPIO_FN(HIFD13),
1567 GPIO_FN(DU0_DG4), GPIO_FN(RX2_C), GPIO_FN(RMII0_CRS_DV_B),
1568 GPIO_FN(TIOC3A_A), GPIO_FN(HIFD12),
1569 GPIO_FN(DU0_DG3), GPIO_FN(SCK2_C), GPIO_FN(RMII0_MDIO_B),
1570 GPIO_FN(TIOC2B_A), GPIO_FN(HIFD11),
1571 GPIO_FN(DU0_DG2), GPIO_FN(RTS1_C), GPIO_FN(RMII0_MDC_B),
1572 GPIO_FN(TIOC2A_A), GPIO_FN(HIFD10),
1573
1574 /* IPSR8 */
1575 GPIO_FN(IRQ3_A), GPIO_FN(RTS0_A), GPIO_FN(HRTS0_B),
1576 GPIO_FN(ET0_ERXD3_A),
1577 GPIO_FN(IRQ2_A), GPIO_FN(CTS0_A), GPIO_FN(HCTS0_B),
1578 GPIO_FN(ET0_ERXD2_A),
1579 GPIO_FN(IRQ1_A), GPIO_FN(HSPI_RX_B), GPIO_FN(TX3_E),
1580 GPIO_FN(ET0_ERXD1),
1581 GPIO_FN(IRQ0_A), GPIO_FN(HSPI_TX_B), GPIO_FN(RX3_E),
1582 GPIO_FN(ET0_ERXD0),
1583 GPIO_FN(DU0_CDE), GPIO_FN(HTX0_B), GPIO_FN(AUDIO_CLKB_B),
1584 GPIO_FN(LCD_VCPWC_B),
1585 GPIO_FN(DU0_DISP), GPIO_FN(CAN0_TX_B), GPIO_FN(HRX0_B),
1586 GPIO_FN(AUDIO_CLKA_B),
1587 GPIO_FN(DU0_EXODDF_DU0_ODDF), GPIO_FN(CAN0_RX_B), GPIO_FN(HSCK0_B),
1588 GPIO_FN(SSI_SDATA1_B),
1589 GPIO_FN(DU0_EXVSYNC_DU0_VSYNC), GPIO_FN(HSPI_RX0_C),
1590 GPIO_FN(SSI_WS1_B),
1591 GPIO_FN(DU0_EXHSYNC_DU0_HSYNC), GPIO_FN(HSPI_TX0_C),
1592 GPIO_FN(SSI_SCK1_B),
1593 GPIO_FN(DU0_DOTCLKOUT), GPIO_FN(HSPI_CLK0_C),
1594 GPIO_FN(SSI_SDATA0_B),
1595 GPIO_FN(DU0_DOTCLKIN), GPIO_FN(HSPI_CS0_C),
1596 GPIO_FN(SSI_WS0_B),
1597 GPIO_FN(DU0_DB7), GPIO_FN(SSI_SCK0_B), GPIO_FN(HIFEBL_B),
1598 GPIO_FN(DU0_DB6), GPIO_FN(HIFRDY),
1599 GPIO_FN(DU0_DB5), GPIO_FN(HIFDREQ),
1600
1601 /* IPSR9 */
1602 GPIO_FN(SSI_SDATA1_A), GPIO_FN(VI1_3_B), GPIO_FN(LCD_DATA14_B),
1603 GPIO_FN(SSI_WS1_A), GPIO_FN(VI1_2_B), GPIO_FN(LCD_DATA13_B),
1604 GPIO_FN(SSI_SCK1_A), GPIO_FN(VI1_1_B), GPIO_FN(TIOC2B_B),
1605 GPIO_FN(LCD_DATA12_B),
1606 GPIO_FN(SSI_SDATA0_A), GPIO_FN(VI1_0_B), GPIO_FN(TIOC2A_B),
1607 GPIO_FN(LCD_DATA11_B),
1608 GPIO_FN(SSI_WS0_A), GPIO_FN(TIOC1B_B), GPIO_FN(LCD_DATA10_B),
1609 GPIO_FN(SSI_SCK0_A), GPIO_FN(TIOC1A_B), GPIO_FN(LCD_DATA9_B),
1610 GPIO_FN(VI1_7_A), GPIO_FN(FCE_B), GPIO_FN(LCD_DATA8_B),
1611 GPIO_FN(VI1_6_A), GPIO_FN(FD7_B), GPIO_FN(LCD_DATA7_B),
1612 GPIO_FN(VI1_5_A), GPIO_FN(FD6_B), GPIO_FN(LCD_DATA6_B),
1613 GPIO_FN(VI1_4_A), GPIO_FN(FD5_B), GPIO_FN(LCD_DATA5_B),
1614 GPIO_FN(VI1_3_A), GPIO_FN(FD4_B), GPIO_FN(LCD_DATA4_B),
1615 GPIO_FN(VI1_2_A), GPIO_FN(FD3_B), GPIO_FN(LCD_DATA3_B),
1616 GPIO_FN(VI1_1_A), GPIO_FN(FD2_B), GPIO_FN(LCD_DATA2_B),
1617 GPIO_FN(VI1_0_A), GPIO_FN(FD1_B), GPIO_FN(LCD_DATA1_B),
1618 GPIO_FN(VI1_CLK_A), GPIO_FN(FD0_B), GPIO_FN(LCD_DATA0_B),
1619
1620 /* IPSR10 */
1621 GPIO_FN(CAN1_TX_A), GPIO_FN(TX5_C), GPIO_FN(MLB_DAT),
1622 GPIO_FN(CAN0_RX_A), GPIO_FN(IRQ0_B), GPIO_FN(MLB_SIG),
1623 GPIO_FN(CAN1_RX_A), GPIO_FN(IRQ1_B),
1624 GPIO_FN(CAN0_TX_A), GPIO_FN(TX4_D), GPIO_FN(MLB_CLK),
1625 GPIO_FN(CAN_CLK_A), GPIO_FN(RX4_D),
1626 GPIO_FN(AUDIO_CLKOUT), GPIO_FN(TX1_E), GPIO_FN(HRTS0_C),
1627 GPIO_FN(FSE_B), GPIO_FN(LCD_M_DISP_B),
1628 GPIO_FN(AUDIO_CLKC), GPIO_FN(SCK1_E), GPIO_FN(HCTS0_C),
1629 GPIO_FN(FRB_B), GPIO_FN(LCD_VEPWC_B),
1630 GPIO_FN(AUDIO_CLKB_A), GPIO_FN(LCD_CLK_B),
1631 GPIO_FN(AUDIO_CLKA_A), GPIO_FN(VI1_CLK_B), GPIO_FN(SCK1_D),
1632 GPIO_FN(IECLK_B), GPIO_FN(LCD_FLM_B),
1633 GPIO_FN(SSI_SDATA3), GPIO_FN(VI1_7_B), GPIO_FN(HTX0_C),
1634 GPIO_FN(FWE_B), GPIO_FN(LCD_CL2_B),
1635 GPIO_FN(SSI_SDATA2), GPIO_FN(VI1_6_B), GPIO_FN(HRX0_C),
1636 GPIO_FN(FRE_B), GPIO_FN(LCD_CL1_B),
1637 GPIO_FN(SSI_WS23), GPIO_FN(VI1_5_B), GPIO_FN(TX1_D),
1638 GPIO_FN(HSCK0_C), GPIO_FN(FALE_B), GPIO_FN(LCD_DON_B),
1639 GPIO_FN(SSI_SCK23), GPIO_FN(VI1_4_B), GPIO_FN(RX1_D),
1640 GPIO_FN(FCLE_B), GPIO_FN(LCD_DATA15_B),
1641
1642 /* IPSR11 */
1643 GPIO_FN(PRESETOUT), GPIO_FN(ST_CLKOUT),
1644 GPIO_FN(DACK1), GPIO_FN(HSPI_CS_B), GPIO_FN(TX4_B),
1645 GPIO_FN(ET0_RX_CLK_A),
1646 GPIO_FN(DREQ1), GPIO_FN(HSPI_CLK_B), GPIO_FN(RX4_B),
1647 GPIO_FN(ET0_PHY_INT_C), GPIO_FN(ET0_TX_CLK_A),
1648 GPIO_FN(DACK0), GPIO_FN(SD1_DAT3_A), GPIO_FN(ET0_TX_ER),
1649 GPIO_FN(DREQ0), GPIO_FN(SD1_CLK_A), GPIO_FN(ET0_TX_EN),
1650 GPIO_FN(USB_OVC1), GPIO_FN(RX3_D), GPIO_FN(CAN1_RX_B),
1651 GPIO_FN(RX5_D), GPIO_FN(IERX_B),
1652 GPIO_FN(PENC1), GPIO_FN(TX3_D), GPIO_FN(CAN1_TX_B),
1653 GPIO_FN(TX5_D), GPIO_FN(IETX_B),
1654 GPIO_FN(TX0_A), GPIO_FN(HSPI_TX_A),
1655 GPIO_FN(RX0_A), GPIO_FN(HSPI_RX_A), GPIO_FN(RMII0_RXD0_A),
1656 GPIO_FN(ET0_ERXD6),
1657 GPIO_FN(SCK0_A), GPIO_FN(HSPI_CS_A), GPIO_FN(VI0_CLKENB),
1658 GPIO_FN(RMII0_TXD1_A), GPIO_FN(ET0_ERXD5),
1659 GPIO_FN(SCIF_CLK_A), GPIO_FN(HSPI_CLK_A), GPIO_FN(VI0_CLK),
1660 GPIO_FN(RMII0_TXD0_A), GPIO_FN(ET0_ERXD4),
1661 GPIO_FN(SDSELF), GPIO_FN(RTS1_E),
1662 GPIO_FN(SDA0), GPIO_FN(HIFEBL_A),
1663 GPIO_FN(SDA1), GPIO_FN(RX1_E),
1664 GPIO_FN(SCL1), GPIO_FN(SCIF_CLK_C),
1665};
1666
1667static struct pinmux_cfg_reg pinmux_config_regs[] = {
1668 { PINMUX_CFG_REG("GPSR0", 0xFFFC0004, 32, 1) {
1669 GP_0_31_FN, FN_IP2_2_0,
1670 GP_0_30_FN, FN_IP1_31_29,
1671 GP_0_29_FN, FN_IP1_28_26,
1672 GP_0_28_FN, FN_IP1_25_23,
1673 GP_0_27_FN, FN_IP1_22_20,
1674 GP_0_26_FN, FN_IP1_19_18,
1675 GP_0_25_FN, FN_IP1_17_16,
1676 GP_0_24_FN, FN_IP0_5_4,
1677 GP_0_23_FN, FN_IP0_3_2,
1678 GP_0_22_FN, FN_IP0_1_0,
1679 GP_0_21_FN, FN_IP11_28,
1680 GP_0_20_FN, FN_IP1_7_6,
1681 GP_0_19_FN, FN_IP1_5_4,
1682 GP_0_18_FN, FN_IP1_3_2,
1683 GP_0_17_FN, FN_IP1_1_0,
1684 GP_0_16_FN, FN_IP0_31_30,
1685 GP_0_15_FN, FN_IP0_29_28,
1686 GP_0_14_FN, FN_IP0_27_26,
1687 GP_0_13_FN, FN_IP0_25_24,
1688 GP_0_12_FN, FN_IP0_23_22,
1689 GP_0_11_FN, FN_IP0_21_20,
1690 GP_0_10_FN, FN_IP0_19_18,
1691 GP_0_9_FN, FN_IP0_17_16,
1692 GP_0_8_FN, FN_IP0_15_14,
1693 GP_0_7_FN, FN_IP0_13_12,
1694 GP_0_6_FN, FN_IP0_11_10,
1695 GP_0_5_FN, FN_IP0_9_8,
1696 GP_0_4_FN, FN_IP0_7_6,
1697 GP_0_3_FN, FN_IP1_15_14,
1698 GP_0_2_FN, FN_IP1_13_12,
1699 GP_0_1_FN, FN_IP1_11_10,
1700 GP_0_0_FN, FN_IP1_9_8 }
1701 },
1702 { PINMUX_CFG_REG("GPSR1", 0xFFFC0008, 32, 1) {
1703 GP_1_31_FN, FN_IP11_25_23,
1704 GP_1_30_FN, FN_IP2_13_11,
1705 GP_1_29_FN, FN_IP2_10_8,
1706 GP_1_28_FN, FN_IP2_7_5,
1707 GP_1_27_FN, FN_IP3_26_24,
1708 GP_1_26_FN, FN_IP3_23_21,
1709 GP_1_25_FN, FN_IP2_4_3,
1710 GP_1_24_FN, FN_WE1,
1711 GP_1_23_FN, FN_WE0,
1712 GP_1_22_FN, FN_IP3_19_18,
1713 GP_1_21_FN, FN_RD,
1714 GP_1_20_FN, FN_IP3_17_15,
1715 GP_1_19_FN, FN_IP3_14_12,
1716 GP_1_18_FN, FN_IP3_11_9,
1717 GP_1_17_FN, FN_IP3_8_6,
1718 GP_1_16_FN, FN_IP3_5_3,
1719 GP_1_15_FN, FN_EX_CS0,
1720 GP_1_14_FN, FN_IP3_2,
1721 GP_1_13_FN, FN_CS0,
1722 GP_1_12_FN, FN_BS,
1723 GP_1_11_FN, FN_CLKOUT,
1724 GP_1_10_FN, FN_IP3_1_0,
1725 GP_1_9_FN, FN_IP2_30_28,
1726 GP_1_8_FN, FN_IP2_27_25,
1727 GP_1_7_FN, FN_IP2_24_23,
1728 GP_1_6_FN, FN_IP2_22_20,
1729 GP_1_5_FN, FN_IP2_19_17,
1730 GP_1_4_FN, FN_IP2_16_14,
1731 GP_1_3_FN, FN_IP11_22_21,
1732 GP_1_2_FN, FN_IP11_20_19,
1733 GP_1_1_FN, FN_IP3_29_27,
1734 GP_1_0_FN, FN_IP3_20 }
1735 },
1736 { PINMUX_CFG_REG("GPSR2", 0xFFFC000C, 32, 1) {
1737 GP_2_31_FN, FN_IP4_31_30,
1738 GP_2_30_FN, FN_IP5_2_0,
1739 GP_2_29_FN, FN_IP5_5_3,
1740 GP_2_28_FN, FN_IP5_8_6,
1741 GP_2_27_FN, FN_IP5_11_9,
1742 GP_2_26_FN, FN_IP5_14_12,
1743 GP_2_25_FN, FN_IP5_17_15,
1744 GP_2_24_FN, FN_IP5_20_18,
1745 GP_2_23_FN, FN_IP5_22_21,
1746 GP_2_22_FN, FN_IP5_24_23,
1747 GP_2_21_FN, FN_IP5_26_25,
1748 GP_2_20_FN, FN_IP4_29_28,
1749 GP_2_19_FN, FN_IP4_27_26,
1750 GP_2_18_FN, FN_IP4_25_24,
1751 GP_2_17_FN, FN_IP4_23_22,
1752 GP_2_16_FN, FN_IP4_21_20,
1753 GP_2_15_FN, FN_IP4_19_18,
1754 GP_2_14_FN, FN_IP4_17_15,
1755 GP_2_13_FN, FN_IP4_14_12,
1756 GP_2_12_FN, FN_IP4_11_9,
1757 GP_2_11_FN, FN_IP4_8_6,
1758 GP_2_10_FN, FN_IP4_5_3,
1759 GP_2_9_FN, FN_IP8_27_26,
1760 GP_2_8_FN, FN_IP11_12,
1761 GP_2_7_FN, FN_IP8_25_23,
1762 GP_2_6_FN, FN_IP8_22_20,
1763 GP_2_5_FN, FN_IP11_27_26,
1764 GP_2_4_FN, FN_IP8_29_28,
1765 GP_2_3_FN, FN_IP4_2_0,
1766 GP_2_2_FN, FN_IP11_11_10,
1767 GP_2_1_FN, FN_IP11_9_7,
1768 GP_2_0_FN, FN_IP11_6_4 }
1769 },
1770 { PINMUX_CFG_REG("GPSR3", 0xFFFC0010, 32, 1) {
1771 GP_3_31_FN, FN_IP9_1_0,
1772 GP_3_30_FN, FN_IP8_19_18,
1773 GP_3_29_FN, FN_IP8_17_16,
1774 GP_3_28_FN, FN_IP8_15_14,
1775 GP_3_27_FN, FN_IP8_13_12,
1776 GP_3_26_FN, FN_IP8_11_10,
1777 GP_3_25_FN, FN_IP8_9_8,
1778 GP_3_24_FN, FN_IP8_7_6,
1779 GP_3_23_FN, FN_IP8_5_4,
1780 GP_3_22_FN, FN_IP8_3_2,
1781 GP_3_21_FN, FN_IP8_1_0,
1782 GP_3_20_FN, FN_IP7_30_29,
1783 GP_3_19_FN, FN_IP7_28_27,
1784 GP_3_18_FN, FN_IP7_26_24,
1785 GP_3_17_FN, FN_IP7_23_21,
1786 GP_3_16_FN, FN_IP7_20_18,
1787 GP_3_15_FN, FN_IP7_17_15,
1788 GP_3_14_FN, FN_IP7_14_12,
1789 GP_3_13_FN, FN_IP7_11_9,
1790 GP_3_12_FN, FN_IP7_8_6,
1791 GP_3_11_FN, FN_IP7_5_3,
1792 GP_3_10_FN, FN_IP7_2_0,
1793 GP_3_9_FN, FN_IP6_23_21,
1794 GP_3_8_FN, FN_IP6_20_18,
1795 GP_3_7_FN, FN_IP6_17_16,
1796 GP_3_6_FN, FN_IP6_15_14,
1797 GP_3_5_FN, FN_IP6_13_12,
1798 GP_3_4_FN, FN_IP6_11_10,
1799 GP_3_3_FN, FN_IP6_9_8,
1800 GP_3_2_FN, FN_IP6_7_6,
1801 GP_3_1_FN, FN_IP6_5_3,
1802 GP_3_0_FN, FN_IP6_2_0 }
1803 },
1804
1805 { PINMUX_CFG_REG("GPSR4", 0xFFFC0014, 32, 1) {
1806 GP_4_31_FN, FN_IP10_24_23,
1807 GP_4_30_FN, FN_IP10_22,
1808 GP_4_29_FN, FN_IP11_18_16,
1809 GP_4_28_FN, FN_USB_OVC0,
1810 GP_4_27_FN, FN_IP11_15_13,
1811 GP_4_26_FN, FN_PENC0,
1812 GP_4_25_FN, FN_IP11_2,
1813 GP_4_24_FN, FN_SCL0,
1814 GP_4_23_FN, FN_IP11_1,
1815 GP_4_22_FN, FN_IP11_0,
1816 GP_4_21_FN, FN_IP10_21_19,
1817 GP_4_20_FN, FN_IP10_18_16,
1818 GP_4_19_FN, FN_IP10_15,
1819 GP_4_18_FN, FN_IP10_14_12,
1820 GP_4_17_FN, FN_IP10_11_9,
1821 GP_4_16_FN, FN_IP10_8_6,
1822 GP_4_15_FN, FN_IP10_5_3,
1823 GP_4_14_FN, FN_IP10_2_0,
1824 GP_4_13_FN, FN_IP9_29_28,
1825 GP_4_12_FN, FN_IP9_27_26,
1826 GP_4_11_FN, FN_IP9_9_8,
1827 GP_4_10_FN, FN_IP9_7_6,
1828 GP_4_9_FN, FN_IP9_5_4,
1829 GP_4_8_FN, FN_IP9_3_2,
1830 GP_4_7_FN, FN_IP9_17_16,
1831 GP_4_6_FN, FN_IP9_15_14,
1832 GP_4_5_FN, FN_IP9_13_12,
1833 GP_4_4_FN, FN_IP9_11_10,
1834 GP_4_3_FN, FN_IP9_25_24,
1835 GP_4_2_FN, FN_IP9_23_22,
1836 GP_4_1_FN, FN_IP9_21_20,
1837 GP_4_0_FN, FN_IP9_19_18 }
1838 },
1839 { PINMUX_CFG_REG("GPSR5", 0xFFFC0018, 32, 1) {
1840 0, 0, 0, 0, 0, 0, 0, 0, /* 31 - 28 */
1841 0, 0, 0, 0, 0, 0, 0, 0, /* 27 - 24 */
1842 0, 0, 0, 0, 0, 0, 0, 0, /* 23 - 20 */
1843 0, 0, 0, 0, 0, 0, 0, 0, /* 19 - 16 */
1844 0, 0, 0, 0, 0, 0, 0, 0, /* 15 - 12 */
1845 GP_5_11_FN, FN_IP10_29_28,
1846 GP_5_10_FN, FN_IP10_27_26,
1847 0, 0, 0, 0, 0, 0, 0, 0, /* 9 - 6 */
1848 0, 0, 0, 0, /* 5, 4 */
1849 GP_5_3_FN, FN_IRQ3_B,
1850 GP_5_2_FN, FN_IRQ2_B,
1851 GP_5_1_FN, FN_IP11_3,
1852 GP_5_0_FN, FN_IP10_25 }
1853 },
1854
1855 { PINMUX_CFG_REG_VAR("IPSR0", 0xFFFC001C, 32,
1856 2, 2, 2, 2, 2, 2, 2, 2,
1857 2, 2, 2, 2, 2, 2, 2, 2) {
1858 /* IP0_31_30 [2] */
1859 FN_A15, FN_ST0_VCO_CLKIN, FN_LCD_DATA15_A,
1860 FN_TIOC3D_C,
1861 /* IP0_29_28 [2] */
1862 FN_A14, FN_LCD_DATA14_A, FN_TIOC3C_C, 0,
1863 /* IP0_27_26 [2] */
1864 FN_A13, FN_LCD_DATA13_A, FN_TIOC3B_C, 0,
1865 /* IP0_25_24 [2] */
1866 FN_A12, FN_LCD_DATA12_A, FN_TIOC3A_C, 0,
1867 /* IP0_23_22 [2] */
1868 FN_A11, FN_ST0_D7, FN_LCD_DATA11_A, FN_TIOC2B_C,
1869 /* IP0_21_20 [2] */
1870 FN_A10, FN_ST0_D6, FN_LCD_DATA10_A, FN_TIOC2A_C,
1871 /* IP0_19_18 [2] */
1872 FN_A9, FN_ST0_D5, FN_LCD_DATA9_A, FN_TIOC1B_C,
1873 /* IP0_17_16 [2] */
1874 FN_A8, FN_ST0_D4, FN_LCD_DATA8_A, FN_TIOC1A_C,
1875 /* IP0_15_14 [2] */
1876 FN_A7, FN_ST0_D3, FN_LCD_DATA7_A, FN_TIOC0D_C,
1877 /* IP0_13_12 [2] */
1878 FN_A6, FN_ST0_D2, FN_LCD_DATA6_A, FN_TIOC0C_C,
1879 /* IP0_11_10 [2] */
1880 FN_A5, FN_ST0_D1, FN_LCD_DATA5_A, FN_TIOC0B_C,
1881 /* IP0_9_8 [2] */
1882 FN_A4, FN_ST0_D0, FN_LCD_DATA4_A, FN_TIOC0A_C,
1883 /* IP0_7_6 [2] */
1884 FN_A3, FN_ST0_VLD, FN_LCD_DATA3_A, FN_TCLKD_C,
1885 /* IP0_5_4 [2] */
1886 FN_A2, FN_ST0_SYC, FN_LCD_DATA2_A, FN_TCLKC_C,
1887 /* IP0_3_2 [2] */
1888 FN_A1, FN_ST0_REQ, FN_LCD_DATA1_A, FN_TCLKB_C,
1889 /* IP0_1_0 [2] */
1890 FN_A0, FN_ST0_CLKIN, FN_LCD_DATA0_A, FN_TCLKA_C }
1891 },
1892 { PINMUX_CFG_REG_VAR("IPSR1", 0xFFFC0020, 32,
1893 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2) {
1894 /* IP1_31_29 [3] */
1895 FN_D3, FN_SD0_DAT3_A, FN_MMC_D3_A, FN_ST1_D6,
1896 FN_FD3_A, 0, 0, 0,
1897 /* IP1_28_26 [3] */
1898 FN_D2, FN_SD0_DAT2_A, FN_MMC_D2_A, FN_ST1_D5,
1899 FN_FD2_A, 0, 0, 0,
1900 /* IP1_25_23 [3] */
1901 FN_D1, FN_SD0_DAT1_A, FN_MMC_D1_A, FN_ST1_D4,
1902 FN_FD1_A, 0, 0, 0,
1903 /* IP1_22_20 [3] */
1904 FN_D0, FN_SD0_DAT0_A, FN_MMC_D0_A, FN_ST1_D3,
1905 FN_FD0_A, 0, 0, 0,
1906 /* IP1_19_18 [2] */
1907 FN_A25, FN_TX2_D, FN_ST1_D2, 0,
1908 /* IP1_17_16 [2] */
1909 FN_A24, FN_RX2_D, FN_ST1_D1, 0,
1910 /* IP1_15_14 [2] */
1911 FN_A23, FN_ST1_D0, FN_LCD_M_DISP_A, 0,
1912 /* IP1_13_12 [2] */
1913 FN_A22, FN_ST1_VLD, FN_LCD_VEPWC_A, 0,
1914 /* IP1_11_10 [2] */
1915 FN_A21, FN_ST1_SYC, FN_LCD_VCPWC_A, 0,
1916 /* IP1_9_8 [2] */
1917 FN_A20, FN_ST1_REQ, FN_LCD_FLM_A, 0,
1918 /* IP1_7_6 [2] */
1919 FN_A19, FN_ST1_CLKIN, FN_LCD_CLK_A, FN_TIOC4D_C,
1920 /* IP1_5_4 [2] */
1921 FN_A18, FN_ST1_PWM, FN_LCD_CL2_A, FN_TIOC4C_C,
1922 /* IP1_3_2 [2] */
1923 FN_A17, FN_ST1_VCO_CLKIN, FN_LCD_CL1_A, FN_TIOC4B_C,
1924 /* IP1_1_0 [2] */
1925 FN_A16, FN_ST0_PWM, FN_LCD_DON_A, FN_TIOC4A_C }
1926 },
1927 { PINMUX_CFG_REG_VAR("IPSR2", 0xFFFC0024, 32,
1928 1, 3, 3, 2, 3, 3, 3, 3, 3, 3, 2, 3) {
1929 /* IP2_31 [1] */
1930 0, 0,
1931 /* IP2_30_28 [3] */
1932 FN_D14, FN_TX2_B, 0, FN_FSE_A,
1933 FN_ET0_TX_CLK_B, 0, 0, 0,
1934 /* IP2_27_25 [3] */
1935 FN_D13, FN_RX2_B, 0, FN_FRB_A,
1936 FN_ET0_ETXD6_B, 0, 0, 0,
1937 /* IP2_24_23 [2] */
1938 FN_D12, 0, FN_FWE_A, FN_ET0_ETXD5_B,
1939 /* IP2_22_20 [3] */
1940 FN_D11, FN_RSPI_MISO_A, 0, FN_QMI_QIO1_A,
1941 FN_FRE_A, FN_ET0_ETXD3_B, 0, 0,
1942 /* IP2_19_17 [3] */
1943 FN_D10, FN_RSPI_MOSI_A, 0, FN_QMO_QIO0_A,
1944 FN_FALE_A, FN_ET0_ETXD2_B, 0, 0,
1945 /* IP2_16_14 [3] */
1946 FN_D9, FN_SD0_CMD_A, FN_MMC_CMD_A, FN_QIO3_A,
1947 FN_FCLE_A, FN_ET0_ETXD1_B, 0, 0,
1948 /* IP2_13_11 [3] */
1949 FN_D8, FN_SD0_CLK_A, FN_MMC_CLK_A, FN_QIO2_A,
1950 FN_FCE_A, FN_ET0_GTX_CLK_B, 0, 0,
1951 /* IP2_10_8 [3] */
1952 FN_D7, FN_RSPI_SSL_A, FN_MMC_D7_A, FN_QSSL_A,
1953 FN_FD7_A, 0, 0, 0,
1954 /* IP2_7_5 [3] */
1955 FN_D6, FN_RSPI_RSPCK_A, FN_MMC_D6_A, FN_QSPCLK_A,
1956 FN_FD6_A, 0, 0, 0,
1957 /* IP2_4_3 [2] */
1958 FN_D5, FN_SD0_WP_A, FN_MMC_D5_A, FN_FD5_A,
1959 /* IP2_2_0 [3] */
1960 FN_D4, FN_SD0_CD_A, FN_MMC_D4_A, FN_ST1_D7,
1961 FN_FD4_A, 0, 0, 0 }
1962 },
1963 { PINMUX_CFG_REG_VAR("IPSR3", 0xFFFC0028, 32,
1964 2, 3, 3, 3, 1, 2, 3, 3, 3, 3, 3, 1, 2) {
1965 /* IP3_31_30 [2] */
1966 0, 0, 0, 0,
1967 /* IP3_29_27 [3] */
1968 FN_DRACK0, FN_SD1_DAT2_A, FN_ATAG, FN_TCLK1_A,
1969 FN_ET0_ETXD7, 0, 0, 0,
1970 /* IP3_26_24 [3] */
1971 FN_EX_WAIT2, FN_SD1_DAT1_A, FN_DACK2, FN_CAN1_RX_C,
1972 FN_ET0_MAGIC_C, FN_ET0_ETXD6_A, 0, 0,
1973 /* IP3_23_21 [3] */
1974 FN_EX_WAIT1, FN_SD1_DAT0_A, FN_DREQ2, FN_CAN1_TX_C,
1975 FN_ET0_LINK_C, FN_ET0_ETXD5_A, 0, 0,
1976 /* IP3_20 [1] */
1977 FN_EX_WAIT0, FN_TCLK1_B,
1978 /* IP3_19_18 [2] */
1979 FN_RD_WR, FN_TCLK1_B, 0, 0,
1980 /* IP3_17_15 [3] */
1981 FN_EX_CS5, FN_SD1_CMD_A, FN_ATADIR, FN_QSSL_B,
1982 FN_ET0_ETXD3_A, 0, 0, 0,
1983 /* IP3_14_12 [3] */
1984 FN_EX_CS4, FN_SD1_WP_A, FN_ATAWR, FN_QMI_QIO1_B,
1985 FN_ET0_ETXD2_A, 0, 0, 0,
1986 /* IP3_11_9 [3] */
1987 FN_EX_CS3, FN_SD1_CD_A, FN_ATARD, FN_QMO_QIO0_B,
1988 FN_ET0_ETXD1_A, 0, 0, 0,
1989 /* IP3_8_6 [3] */
1990 FN_EX_CS2, FN_TX3_B, FN_ATACS1, FN_QSPCLK_B,
1991 FN_ET0_GTX_CLK_A, 0, 0, 0,
1992 /* IP3_5_3 [3] */
1993 FN_EX_CS1, FN_RX3_B, FN_ATACS0, FN_QIO2_B,
1994 FN_ET0_ETXD0, 0, 0, 0,
1995 /* IP3_2 [1] */
1996 FN_CS1_A26, FN_QIO3_B,
1997 /* IP3_1_0 [2] */
1998 FN_D15, FN_SCK2_B, 0, 0 }
1999 },
2000 { PINMUX_CFG_REG_VAR("IPSR4", 0xFFFC002C, 32,
2001 2, 2, 2, 2, 2, 2 , 2, 3, 3, 3, 3, 3, 3) {
2002 /* IP4_31_30 [2] */
2003 0, FN_SCK2_A, FN_VI0_G3, 0,
2004 /* IP4_29_28 [2] */
2005 0, FN_RTS1_B, FN_VI0_G2, 0,
2006 /* IP4_27_26 [2] */
2007 0, FN_CTS1_B, FN_VI0_DATA7_VI0_G1, 0,
2008 /* IP4_25_24 [2] */
2009 0, FN_TX1_B, FN_VI0_DATA6_VI0_G0, FN_ET0_PHY_INT_A,
2010 /* IP4_23_22 [2] */
2011 0, FN_RX1_B, FN_VI0_DATA5_VI0_B5, FN_ET0_MAGIC_A,
2012 /* IP4_21_20 [2] */
2013 0, FN_SCK1_B, FN_VI0_DATA4_VI0_B4, FN_ET0_LINK_A,
2014 /* IP4_19_18 [2] */
2015 0, FN_RTS0_B, FN_VI0_DATA3_VI0_B3, FN_ET0_MDIO_A,
2016 /* IP4_17_15 [3] */
2017 0, FN_CTS0_B, FN_VI0_DATA2_VI0_B2, FN_RMII0_MDIO_A,
2018 FN_ET0_MDC, 0, 0, 0,
2019 /* IP4_14_12 [3] */
2020 FN_HTX0_A, FN_TX1_A, FN_VI0_DATA1_VI0_B1, FN_RMII0_MDC_A,
2021 FN_ET0_COL, 0, 0, 0,
2022 /* IP4_11_9 [3] */
2023 FN_HRX0_A, FN_RX1_A, FN_VI0_DATA0_VI0_B0, FN_RMII0_CRS_DV_A,
2024 FN_ET0_CRS, 0, 0, 0,
2025 /* IP4_8_6 [3] */
2026 FN_HSCK0_A, FN_SCK1_A, FN_VI0_VSYNC, FN_RMII0_RX_ER_A,
2027 FN_ET0_RX_ER, 0, 0, 0,
2028 /* IP4_5_3 [3] */
2029 FN_HRTS0_A, FN_RTS1_A, FN_VI0_HSYNC, FN_RMII0_TXD_EN_A,
2030 FN_ET0_RX_DV, 0, 0, 0,
2031 /* IP4_2_0 [3] */
2032 FN_HCTS0_A, FN_CTS1_A, FN_VI0_FIELD, FN_RMII0_RXD1_A,
2033 FN_ET0_ERXD7, 0, 0, 0 }
2034 },
2035 { PINMUX_CFG_REG_VAR("IPSR5", 0xFFFC0030, 32,
2036 1, 1, 1, 1, 1, 2, 2, 2, 3, 3, 3, 3, 3, 3, 3) {
2037 /* IP5_31 [1] */
2038 0, 0,
2039 /* IP5_30 [1] */
2040 0, 0,
2041 /* IP5_29 [1] */
2042 0, 0,
2043 /* IP5_28 [1] */
2044 0, 0,
2045 /* IP5_27 [1] */
2046 0, 0,
2047 /* IP5_26_25 [2] */
2048 FN_REF50CK, FN_CTS1_E, FN_HCTS0_D, 0,
2049 /* IP5_24_23 [2] */
2050 FN_REF125CK, FN_ADTRG, FN_RX5_C, 0,
2051 /* IP5_22_21 [2] */
2052 FN_SD2_WP_A, FN_TX5_A, FN_VI0_R5, 0,
2053 /* IP5_20_18 [3] */
2054 FN_SD2_CD_A, FN_RX5_A, FN_VI0_R4, 0,
2055 0, 0, 0, FN_ET0_PHY_INT_B,
2056 /* IP5_17_15 [3] */
2057 FN_SD2_DAT3_A, FN_TX4_A, FN_VI0_R3, 0,
2058 0, 0, 0, FN_ET0_MAGIC_B,
2059 /* IP5_14_12 [3] */
2060 FN_SD2_DAT2_A, FN_RX4_A, FN_VI0_R2, 0,
2061 0, 0, 0, FN_ET0_LINK_B,
2062 /* IP5_11_9 [3] */
2063 FN_SD2_DAT1_A, FN_TX3_A, FN_VI0_R1, 0,
2064 0, 0, 0, FN_ET0_MDIO_B,
2065 /* IP5_8_6 [3] */
2066 FN_SD2_DAT0_A, FN_RX3_A, FN_VI0_R0, 0,
2067 0, 0, 0, FN_ET0_ERXD3_B,
2068 /* IP5_5_3 [3] */
2069 FN_SD2_CMD_A, FN_TX2_A, FN_VI0_G5, 0,
2070 0, 0, 0, FN_ET0_ERXD2_B,
2071 /* IP5_2_0 [3] */
2072 FN_SD2_CLK_A, FN_RX2_A, FN_VI0_G4, 0,
2073 FN_ET0_RX_CLK_B, 0, 0, 0 }
2074 },
2075 { PINMUX_CFG_REG_VAR("IPSR6", 0xFFFC0034, 32,
2076 1, 1, 1, 1, 1, 1, 1, 1,
2077 3, 3, 2, 2, 2, 2, 2, 2, 3, 3) {
2078 /* IP5_31 [1] */
2079 0, 0,
2080 /* IP6_30 [1] */
2081 0, 0,
2082 /* IP6_29 [1] */
2083 0, 0,
2084 /* IP6_28 [1] */
2085 0, 0,
2086 /* IP6_27 [1] */
2087 0, 0,
2088 /* IP6_26 [1] */
2089 0, 0,
2090 /* IP6_25 [1] */
2091 0, 0,
2092 /* IP6_24 [1] */
2093 0, 0,
2094 /* IP6_23_21 [3] */
2095 FN_DU0_DG1, FN_CTS1_C, FN_HRTS0_D, FN_TIOC1B_A,
2096 FN_HIFD09, 0, 0, 0,
2097 /* IP6_20_18 [3] */
2098 FN_DU0_DG0, FN_TX1_C, FN_HSCK0_D, FN_IECLK_A,
2099 FN_TIOC1A_A, FN_HIFD08, 0, 0,
2100 /* IP6_17_16 [2] */
2101 FN_DU0_DR7, FN_RX1_C, FN_TIOC0D_A, FN_HIFD07,
2102 /* IP6_15_14 [2] */
2103 FN_DU0_DR6, FN_SCK1_C, FN_TIOC0C_A, FN_HIFD06,
2104 /* IP6_13_12 [2] */
2105 FN_DU0_DR5, FN_RTS0_C, FN_TIOC0B_A, FN_HIFD05,
2106 /* IP6_11_10 [2] */
2107 FN_DU0_DR4, FN_CTS0_C, FN_TIOC0A_A, FN_HIFD04,
2108 /* IP6_9_8 [2] */
2109 FN_DU0_DR3, FN_TX0_B, FN_TCLKD_A, FN_HIFD03,
2110 /* IP6_7_6 [2] */
2111 FN_DU0_DR2, FN_RX0_B, FN_TCLKC_A, FN_HIFD02,
2112 /* IP6_5_3 [3] */
2113 FN_DU0_DR1, FN_SCK0_B, FN_HTX0_D, FN_IERX_A,
2114 FN_TCLKB_A, FN_HIFD01, 0, 0,
2115 /* IP6_2_0 [3] */
2116 FN_DU0_DR0, FN_SCIF_CLK_B, FN_HRX0_D, FN_IETX_A,
2117 FN_TCLKA_A, FN_HIFD00, 0, 0 }
2118 },
2119 { PINMUX_CFG_REG_VAR("IPSR7", 0xFFFC0038, 32,
2120 1, 2, 2, 3, 3, 3, 3, 3, 3, 3, 3, 3) {
2121 /* IP7_31 [1] */
2122 0, 0,
2123 /* IP7_30_29 [2] */
2124 FN_DU0_DB4, 0, FN_HIFINT, 0,
2125 /* IP7_28_27 [2] */
2126 FN_DU0_DB3, FN_TX5_B, FN_TIOC4D_A, FN_HIFRD,
2127 /* IP7_26_24 [3] */
2128 FN_DU0_DB2, FN_RX5_B, FN_RMII0_TXD1_B, FN_TIOC4C_A,
2129 FN_HIFWR, 0, 0, 0,
2130 /* IP7_23_21 [3] */
2131 FN_DU0_DB1, FN_TX4_C, FN_RMII0_TXD0_B, FN_TIOC4B_A,
2132 FN_HIFRS, 0, 0, 0,
2133 /* IP7_20_18 [3] */
2134 FN_DU0_DB0, FN_RX4_C, FN_RMII0_TXD_EN_B, FN_TIOC4A_A,
2135 FN_HIFCS, 0, 0, 0,
2136 /* IP7_17_15 [3] */
2137 FN_DU0_DG7, FN_TX3_C, FN_RMII0_RXD1_B, FN_TIOC3D_A,
2138 FN_HIFD15, 0, 0, 0,
2139 /* IP7_14_12 [3] */
2140 FN_DU0_DG6, FN_RX3_C, FN_RMII0_RXD0_B, FN_TIOC3C_A,
2141 FN_HIFD14, 0, 0, 0,
2142 /* IP7_11_9 [3] */
2143 FN_DU0_DG5, FN_TX2_C, FN_RMII0_RX_ER_B, FN_TIOC3B_A,
2144 FN_HIFD13, 0, 0, 0,
2145 /* IP7_8_6 [3] */
2146 FN_DU0_DG4, FN_RX2_C, FN_RMII0_CRS_DV_B, FN_TIOC3A_A,
2147 FN_HIFD12, 0, 0, 0,
2148 /* IP7_5_3 [3] */
2149 FN_DU0_DG3, FN_SCK2_C, FN_RMII0_MDIO_B, FN_TIOC2B_A,
2150 FN_HIFD11, 0, 0, 0,
2151 /* IP7_2_0 [3] */
2152 FN_DU0_DG2, FN_RTS1_C, FN_RMII0_MDC_B, FN_TIOC2A_A,
2153 FN_HIFD10, 0, 0, 0 }
2154 },
2155 { PINMUX_CFG_REG_VAR("IPSR8", 0xFFFC003C, 32,
2156 2, 2, 2, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2) {
2157 /* IP9_31_30 [2] */
2158 0, 0, 0, 0,
2159 /* IP8_29_28 [2] */
2160 FN_IRQ3_A, FN_RTS0_A, FN_HRTS0_B, FN_ET0_ERXD3_A,
2161 /* IP8_27_26 [2] */
2162 FN_IRQ2_A, FN_CTS0_A, FN_HCTS0_B, FN_ET0_ERXD2_A,
2163 /* IP8_25_23 [3] */
2164 FN_IRQ1_A, 0, FN_HSPI_RX_B, FN_TX3_E,
2165 FN_ET0_ERXD1, 0, 0, 0,
2166 /* IP8_22_20 [3] */
2167 FN_IRQ0_A, 0, FN_HSPI_TX_B, FN_RX3_E,
2168 FN_ET0_ERXD0, 0, 0, 0,
2169 /* IP8_19_18 [2] */
2170 FN_DU0_CDE, FN_HTX0_B, FN_AUDIO_CLKB_B, FN_LCD_VCPWC_B,
2171 /* IP8_17_16 [2] */
2172 FN_DU0_DISP, FN_CAN0_TX_B, FN_HRX0_B, FN_AUDIO_CLKA_B,
2173 /* IP8_15_14 [2] */
2174 FN_DU0_EXODDF_DU0_ODDF, FN_CAN0_RX_B, FN_HSCK0_B,
2175 FN_SSI_SDATA1_B,
2176 /* IP8_13_12 [2] */
2177 FN_DU0_EXVSYNC_DU0_VSYNC, 0, FN_HSPI_RX0_C, FN_SSI_WS1_B,
2178 /* IP8_11_10 [2] */
2179 FN_DU0_EXHSYNC_DU0_HSYNC, 0, FN_HSPI_TX0_C, FN_SSI_SCK1_B,
2180 /* IP8_9_8 [2] */
2181 FN_DU0_DOTCLKOUT, 0, FN_HSPI_CLK0_C, FN_SSI_SDATA0_B,
2182 /* IP8_7_6 [2] */
2183 FN_DU0_DOTCLKIN, 0, FN_HSPI_CS0_C, FN_SSI_WS0_B,
2184 /* IP8_5_4 [2] */
2185 FN_DU0_DB7, 0, FN_SSI_SCK0_B, FN_HIFEBL_B,
2186 /* IP8_3_2 [2] */
2187 FN_DU0_DB6, 0, FN_HIFRDY, 0,
2188 /* IP8_1_0 [2] */
2189 FN_DU0_DB5, 0, FN_HIFDREQ, 0 }
2190 },
2191 { PINMUX_CFG_REG_VAR("IPSR9", 0xFFFC0040, 32,
2192 2, 2, 2, 2, 2, 2, 2, 2,
2193 2, 2, 2, 2, 2, 2, 2, 2) {
2194 /* IP9_31_30 [2] */
2195 0, 0, 0, 0,
2196 /* IP9_29_28 [2] */
2197 FN_SSI_SDATA1_A, FN_VI1_3_B, FN_LCD_DATA14_B, 0,
2198 /* IP9_27_26 [2] */
2199 FN_SSI_WS1_A, FN_VI1_2_B, FN_LCD_DATA13_B, 0,
2200 /* IP9_25_24 [2] */
2201 FN_SSI_SCK1_A, FN_VI1_1_B, FN_TIOC2B_B, FN_LCD_DATA12_B,
2202 /* IP9_23_22 [2] */
2203 FN_SSI_SDATA0_A, FN_VI1_0_B, FN_TIOC2A_B, FN_LCD_DATA11_B,
2204 /* IP9_21_20 [2] */
2205 FN_SSI_WS0_A, FN_TIOC1B_B, FN_LCD_DATA10_B, 0,
2206 /* IP9_19_18 [2] */
2207 FN_SSI_SCK0_A, FN_TIOC1A_B, FN_LCD_DATA9_B, 0,
2208 /* IP9_17_16 [2] */
2209 FN_VI1_7_A, FN_FCE_B, FN_LCD_DATA8_B, 0,
2210 /* IP9_15_14 [2] */
2211 FN_VI1_6_A, 0, FN_FD7_B, FN_LCD_DATA7_B,
2212 /* IP9_13_12 [2] */
2213 FN_VI1_5_A, 0, FN_FD6_B, FN_LCD_DATA6_B,
2214 /* IP9_11_10 [2] */
2215 FN_VI1_4_A, 0, FN_FD5_B, FN_LCD_DATA5_B,
2216 /* IP9_9_8 [2] */
2217 FN_VI1_3_A, 0, FN_FD4_B, FN_LCD_DATA4_B,
2218 /* IP9_7_6 [2] */
2219 FN_VI1_2_A, 0, FN_FD3_B, FN_LCD_DATA3_B,
2220 /* IP9_5_4 [2] */
2221 FN_VI1_1_A, 0, FN_FD2_B, FN_LCD_DATA2_B,
2222 /* IP9_3_2 [2] */
2223 FN_VI1_0_A, 0, FN_FD1_B, FN_LCD_DATA1_B,
2224 /* IP9_1_0 [2] */
2225 FN_VI1_CLK_A, 0, FN_FD0_B, FN_LCD_DATA0_B }
2226 },
2227 { PINMUX_CFG_REG_VAR("IPSR10", 0xFFFC0044, 32,
2228 2, 2, 2, 1, 2, 1, 3,
2229 3, 1, 3, 3, 3, 3, 3) {
2230 /* IP9_31_30 [2] */
2231 0, 0, 0, 0,
2232 /* IP10_29_28 [2] */
2233 FN_CAN1_TX_A, FN_TX5_C, FN_MLB_DAT, 0,
2234 /* IP10_27_26 [2] */
2235 FN_CAN0_RX_A, FN_IRQ0_B, FN_MLB_SIG, 0,
2236 /* IP10_25 [1] */
2237 FN_CAN1_RX_A, FN_IRQ1_B,
2238 /* IP10_24_23 [2] */
2239 FN_CAN0_TX_A, FN_TX4_D, FN_MLB_CLK, 0,
2240 /* IP10_22 [1] */
2241 FN_CAN_CLK_A, FN_RX4_D,
2242 /* IP10_21_19 [3] */
2243 FN_AUDIO_CLKOUT, FN_TX1_E, FN_HRTS0_C, FN_FSE_B,
2244 FN_LCD_M_DISP_B, 0, 0, 0,
2245 /* IP10_18_16 [3] */
2246 FN_AUDIO_CLKC, FN_SCK1_E, FN_HCTS0_C, FN_FRB_B,
2247 FN_LCD_VEPWC_B, 0, 0, 0,
2248 /* IP10_15 [1] */
2249 FN_AUDIO_CLKB_A, FN_LCD_CLK_B,
2250 /* IP10_14_12 [3] */
2251 FN_AUDIO_CLKA_A, FN_VI1_CLK_B, FN_SCK1_D, FN_IECLK_B,
2252 FN_LCD_FLM_B, 0, 0, 0,
2253 /* IP10_11_9 [3] */
2254 FN_SSI_SDATA3, FN_VI1_7_B, FN_HTX0_C, FN_FWE_B,
2255 FN_LCD_CL2_B, 0, 0, 0,
2256 /* IP10_8_6 [3] */
2257 FN_SSI_SDATA2, FN_VI1_6_B, FN_HRX0_C, FN_FRE_B,
2258 FN_LCD_CL1_B, 0, 0, 0,
2259 /* IP10_5_3 [3] */
2260 FN_SSI_WS23, FN_VI1_5_B, FN_TX1_D, FN_HSCK0_C, FN_FALE_B,
2261 FN_LCD_DON_B, 0, 0, 0,
2262 /* IP10_2_0 [3] */
2263 FN_SSI_SCK23, FN_VI1_4_B, FN_RX1_D, FN_FCLE_B,
2264 FN_LCD_DATA15_B, 0, 0, 0 }
2265 },
2266 { PINMUX_CFG_REG_VAR("IPSR11", 0xFFFC0048, 32,
2267 3, 1, 2, 2, 2, 3, 3, 1, 2, 3, 3, 1, 1, 1, 1) {
2268 /* IP11_31_29 [3] */
2269 0, 0, 0, 0, 0, 0, 0, 0,
2270 /* IP11_28 [1] */
2271 FN_PRESETOUT, FN_ST_CLKOUT,
2272 /* IP11_27_26 [2] */
2273 FN_DACK1, FN_HSPI_CS_B, FN_TX4_B, FN_ET0_RX_CLK_A,
2274 /* IP11_25_23 [3] */
2275 FN_DREQ1, FN_HSPI_CLK_B, FN_RX4_B, FN_ET0_PHY_INT_C,
2276 FN_ET0_TX_CLK_A, 0, 0, 0,
2277 /* IP11_22_21 [2] */
2278 FN_DACK0, FN_SD1_DAT3_A, FN_ET0_TX_ER, 0,
2279 /* IP11_20_19 [2] */
2280 FN_DREQ0, FN_SD1_CLK_A, FN_ET0_TX_EN, 0,
2281 /* IP11_18_16 [3] */
2282 FN_USB_OVC1, FN_RX3_D, FN_CAN1_RX_B, FN_RX5_D,
2283 FN_IERX_B, 0, 0, 0,
2284 /* IP11_15_13 [3] */
2285 FN_PENC1, FN_TX3_D, FN_CAN1_TX_B, FN_TX5_D,
2286 FN_IETX_B, 0, 0, 0,
2287 /* IP11_12 [1] */
2288 FN_TX0_A, FN_HSPI_TX_A,
2289 /* IP11_11_10 [2] */
2290 FN_RX0_A, FN_HSPI_RX_A, FN_RMII0_RXD0_A, FN_ET0_ERXD6,
2291 /* IP11_9_7 [3] */
2292 FN_SCK0_A, FN_HSPI_CS_A, FN_VI0_CLKENB, FN_RMII0_TXD1_A,
2293 FN_ET0_ERXD5, 0, 0, 0,
2294 /* IP11_6_4 [3] */
2295 FN_SCIF_CLK_A, FN_HSPI_CLK_A, FN_VI0_CLK, FN_RMII0_TXD0_A,
2296 FN_ET0_ERXD4, 0, 0, 0,
2297 /* IP11_3 [1] */
2298 FN_SDSELF, FN_RTS1_E,
2299 /* IP11_2 [1] */
2300 FN_SDA0, FN_HIFEBL_A,
2301 /* IP11_1 [1] */
2302 FN_SDA1, FN_RX1_E,
2303 /* IP11_0 [1] */
2304 FN_SCL1, FN_SCIF_CLK_C }
2305 },
2306 { PINMUX_CFG_REG_VAR("MOD_SEL1", 0xFFFC004C, 32,
2307 3, 1, 1, 1, 1, 1, 1, 2, 1, 1, 1, 2, 2,
2308 1, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1) {
2309 /* SEL1_31_29 [3] */
2310 0, 0, 0, 0, 0, 0, 0, 0,
2311 /* SEL1_28 [1] */
2312 FN_SEL_IEBUS_0, FN_SEL_IEBUS_1,
2313 /* SEL1_27 [1] */
2314 FN_SEL_RQSPI_0, FN_SEL_RQSPI_1,
2315 /* SEL1_26 [1] */
2316 FN_SEL_VIN1_0, FN_SEL_VIN1_1,
2317 /* SEL1_25 [1] */
2318 FN_SEL_HIF_0, FN_SEL_HIF_1,
2319 /* SEL1_24 [1] */
2320 FN_SEL_RSPI_0, FN_SEL_RSPI_1,
2321 /* SEL1_23 [1] */
2322 FN_SEL_LCDC_0, FN_SEL_LCDC_1,
2323 /* SEL1_22_21 [2] */
2324 FN_SEL_ET0_CTL_0, FN_SEL_ET0_CTL_1, FN_SEL_ET0_CTL_2, 0,
2325 /* SEL1_20 [1] */
2326 FN_SEL_ET0_0, FN_SEL_ET0_1,
2327 /* SEL1_19 [1] */
2328 FN_SEL_RMII_0, FN_SEL_RMII_1,
2329 /* SEL1_18 [1] */
2330 FN_SEL_TMU_0, FN_SEL_TMU_1,
2331 /* SEL1_17_16 [2] */
2332 FN_SEL_HSPI_0, FN_SEL_HSPI_1, FN_SEL_HSPI_2, 0,
2333 /* SEL1_15_14 [2] */
2334 FN_SEL_HSCIF_0, FN_SEL_HSCIF_1, FN_SEL_HSCIF_2, FN_SEL_HSCIF_3,
2335 /* SEL1_13 [1] */
2336 FN_SEL_RCAN_CLK_0, FN_SEL_RCAN_CLK_1,
2337 /* SEL1_12_11 [2] */
2338 FN_SEL_RCAN1_0, FN_SEL_RCAN1_1, FN_SEL_RCAN1_2, 0,
2339 /* SEL1_10 [1] */
2340 FN_SEL_RCAN0_0, FN_SEL_RCAN0_1,
2341 /* SEL1_9 [1] */
2342 FN_SEL_SDHI2_0, FN_SEL_SDHI2_1,
2343 /* SEL1_8 [1] */
2344 FN_SEL_SDHI1_0, FN_SEL_SDHI1_1,
2345 /* SEL1_7 [1] */
2346 FN_SEL_SDHI0_0, FN_SEL_SDHI0_1,
2347 /* SEL1_6 [1] */
2348 FN_SEL_SSI1_0, FN_SEL_SSI1_1,
2349 /* SEL1_5 [1] */
2350 FN_SEL_SSI0_0, FN_SEL_SSI0_1,
2351 /* SEL1_4 [1] */
2352 FN_SEL_AUDIO_CLKB_0, FN_SEL_AUDIO_CLKB_1,
2353 /* SEL1_3 [1] */
2354 FN_SEL_AUDIO_CLKA_0, FN_SEL_AUDIO_CLKA_1,
2355 /* SEL1_2 [1] */
2356 FN_SEL_FLCTL_0, FN_SEL_FLCTL_1,
2357 /* SEL1_1 [1] */
2358 FN_SEL_MMC_0, FN_SEL_MMC_1,
2359 /* SEL1_0 [1] */
2360 FN_SEL_INTC_0, FN_SEL_INTC_1 }
2361 },
2362 { PINMUX_CFG_REG_VAR("MOD_SEL2", 0xFFFC0050, 32,
2363 1, 1, 1, 1, 1, 1, 1, 1,
2364 1, 1, 1, 2, 2, 1, 2, 2, 3, 2, 3, 2, 2) {
2365 /* SEL2_31 [1] */
2366 0, 0,
2367 /* SEL2_30 [1] */
2368 0, 0,
2369 /* SEL2_29 [1] */
2370 0, 0,
2371 /* SEL2_28 [1] */
2372 0, 0,
2373 /* SEL2_27 [1] */
2374 0, 0,
2375 /* SEL2_26 [1] */
2376 0, 0,
2377 /* SEL2_25 [1] */
2378 0, 0,
2379 /* SEL2_24 [1] */
2380 0, 0,
2381 /* SEL2_23 [1] */
2382 FN_SEL_MTU2_CLK_0, FN_SEL_MTU2_CLK_1,
2383 /* SEL2_22 [1] */
2384 FN_SEL_MTU2_CH4_0, FN_SEL_MTU2_CH4_1,
2385 /* SEL2_21 [1] */
2386 FN_SEL_MTU2_CH3_0, FN_SEL_MTU2_CH3_1,
2387 /* SEL2_20_19 [2] */
2388 FN_SEL_MTU2_CH2_0, FN_SEL_MTU2_CH2_1, FN_SEL_MTU2_CH2_2, 0,
2389 /* SEL2_18_17 [2] */
2390 FN_SEL_MTU2_CH1_0, FN_SEL_MTU2_CH1_1, FN_SEL_MTU2_CH1_2, 0,
2391 /* SEL2_16 [1] */
2392 FN_SEL_MTU2_CH0_0, FN_SEL_MTU2_CH0_1,
2393 /* SEL2_15_14 [2] */
2394 FN_SEL_SCIF5_0, FN_SEL_SCIF5_1, FN_SEL_SCIF5_2, FN_SEL_SCIF5_3,
2395 /* SEL2_13_12 [2] */
2396 FN_SEL_SCIF4_0, FN_SEL_SCIF4_1, FN_SEL_SCIF4_2, FN_SEL_SCIF4_3,
2397 /* SEL2_11_9 [3] */
2398 FN_SEL_SCIF3_0, FN_SEL_SCIF3_1, FN_SEL_SCIF3_2, FN_SEL_SCIF3_3,
2399 FN_SEL_SCIF3_4, 0, 0, 0,
2400 /* SEL2_8_7 [2] */
2401 FN_SEL_SCIF2_0, FN_SEL_SCIF2_1, FN_SEL_SCIF2_2, FN_SEL_SCIF2_3,
2402 /* SEL2_6_4 [3] */
2403 FN_SEL_SCIF1_0, FN_SEL_SCIF1_1, FN_SEL_SCIF1_2, FN_SEL_SCIF1_3,
2404 FN_SEL_SCIF1_4, 0, 0, 0,
2405 /* SEL2_3_2 [2] */
2406 FN_SEL_SCIF0_0, FN_SEL_SCIF0_1, FN_SEL_SCIF0_2, 0,
2407 /* SEL2_1_0 [2] */
2408 FN_SEL_SCIF_CLK_0, FN_SEL_SCIF_CLK_1, FN_SEL_SCIF_CLK_2, 0 }
2409 },
2410 /* GPIO 0 - 5*/
2411 { PINMUX_CFG_REG("INOUTSEL0", 0xFFC40004, 32, 1) { GP_INOUTSEL(0) } },
2412 { PINMUX_CFG_REG("INOUTSEL1", 0xFFC41004, 32, 1) { GP_INOUTSEL(1) } },
2413 { PINMUX_CFG_REG("INOUTSEL2", 0xFFC42004, 32, 1) { GP_INOUTSEL(2) } },
2414 { PINMUX_CFG_REG("INOUTSEL3", 0xFFC43004, 32, 1) { GP_INOUTSEL(3) } },
2415 { PINMUX_CFG_REG("INOUTSEL4", 0xFFC44004, 32, 1) { GP_INOUTSEL(4) } },
2416 { PINMUX_CFG_REG("INOUTSEL5", 0xffc45004, 32, 1) {
2417 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, /* 31 - 24 */
2418 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, /* 23 - 16 */
2419 0, 0, 0, 0, 0, 0, 0, 0, /* 15 - 12 */
2420 GP_5_11_IN, GP_5_11_OUT,
2421 GP_5_10_IN, GP_5_10_OUT,
2422 GP_5_9_IN, GP_5_9_OUT,
2423 GP_5_8_IN, GP_5_8_OUT,
2424 GP_5_7_IN, GP_5_7_OUT,
2425 GP_5_6_IN, GP_5_6_OUT,
2426 GP_5_5_IN, GP_5_5_OUT,
2427 GP_5_4_IN, GP_5_4_OUT,
2428 GP_5_3_IN, GP_5_3_OUT,
2429 GP_5_2_IN, GP_5_2_OUT,
2430 GP_5_1_IN, GP_5_1_OUT,
2431 GP_5_0_IN, GP_5_0_OUT }
2432 },
2433 { },
2434};
2435
2436static struct pinmux_data_reg pinmux_data_regs[] = {
2437 /* GPIO 0 - 5*/
2438 { PINMUX_DATA_REG("INDT0", 0xFFC4000C, 32) { GP_INDT(0) } },
2439 { PINMUX_DATA_REG("INDT1", 0xFFC4100C, 32) { GP_INDT(1) } },
2440 { PINMUX_DATA_REG("INDT2", 0xFFC4200C, 32) { GP_INDT(2) } },
2441 { PINMUX_DATA_REG("INDT3", 0xFFC4300C, 32) { GP_INDT(3) } },
2442 { PINMUX_DATA_REG("INDT4", 0xFFC4400C, 32) { GP_INDT(4) } },
2443 { PINMUX_DATA_REG("INDT5", 0xFFC4500C, 32) {
2444 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2445 0, 0, 0, 0,
2446 GP_5_11_DATA, GP_5_10_DATA, GP_5_9_DATA, GP_5_8_DATA,
2447 GP_5_7_DATA, GP_5_6_DATA, GP_5_5_DATA, GP_5_4_DATA,
2448 GP_5_3_DATA, GP_5_2_DATA, GP_5_1_DATA, GP_5_0_DATA }
2449 },
2450 { },
2451};
2452
2453struct sh_pfc_soc_info sh7734_pinmux_info = {
2454 .name = "sh7734_pfc",
2455
2456 .unlock_reg = 0xFFFC0000,
2457
2458 .reserved_id = PINMUX_RESERVED,
2459 .data = { PINMUX_DATA_BEGIN, PINMUX_DATA_END },
2460 .input = { PINMUX_INPUT_BEGIN, PINMUX_INPUT_END },
2461 .output = { PINMUX_OUTPUT_BEGIN, PINMUX_OUTPUT_END },
2462 .mark = { PINMUX_MARK_BEGIN, PINMUX_MARK_END },
2463 .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
2464
2465 .first_gpio = GPIO_GP_0_0,
2466 .last_gpio = GPIO_FN_ST_CLKOUT,
2467
2468 .gpios = pinmux_gpios,
2469 .cfg_regs = pinmux_config_regs,
2470 .data_regs = pinmux_data_regs,
2471
2472 .gpio_data = pinmux_data,
2473 .gpio_data_size = ARRAY_SIZE(pinmux_data),
2474};
generated by cgit v1.2.2 (git 2.25.0) at 2024-09-20 04:41:44 -0400