pinctrl: add Intel BayTrail GPIO/pinctrl support

Add support for gpio on Intel BayTrail platforms. BayTrail supports 3 banks
of gpios called SCORE, NCORE ans SUS with 102, 28 and 44 gpio pins.
Supports gpio interrupts and ACPI gpio events

Pins may be muxed to alternate function instead of gpio by firmware.
This driver does not touch the pin muxing and expect firmare
to set pin muxing and pullup/down properties properly.

Signed-off-by: Mathias Nyman <mathias.nyman@linux.intel.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>

3 files changed, 556 insertions, 0 deletions

diff --git a/drivers/pinctrl/Kconfig b/drivers/pinctrl/Kconfig
index 269c0406dce4..e01976fb1175 100644
--- a/drivers/pinctrl/Kconfig
+++ b/drivers/pinctrl/Kconfig
@@ -58,6 +58,18 @@ config PINCTRL_AT91
         help
           Say Y here to enable the at91 pinctrl driver
 
+config PINCTRL_BAYTRAIL
+        bool "Intel Baytrail GPIO pin control"
+        depends on GPIOLIB && ACPI && X86
+        select IRQ_DOMAIN
+        help
+          driver for memory mapped GPIO functionality on Intel Baytrail
+          platforms. Supports 3 banks with 102, 28 and 44 gpios.
+          Most pins are usually muxed to some other functionality by firmware,
+          so only a small amount is available for gpio use.
+
+          Requires ACPI device enumeration code to set up a platform device.
+
 config PINCTRL_BCM2835
         bool
         select PINMUX
diff --git a/drivers/pinctrl/Makefile b/drivers/pinctrl/Makefile
index ff38aca65689..9031afddb9ad 100644
--- a/drivers/pinctrl/Makefile
+++ b/drivers/pinctrl/Makefile
@@ -16,6 +16,7 @@ obj-$(CONFIG_PINCTRL_AB9540)	+= pinctrl-ab9540.o
 obj-$(CONFIG_PINCTRL_AB8505)    += pinctrl-ab8505.o
 obj-$(CONFIG_PINCTRL_AT91)      += pinctrl-at91.o
 obj-$(CONFIG_PINCTRL_BCM2835)   += pinctrl-bcm2835.o
+obj-$(CONFIG_PINCTRL_BAYTRAIL)  += pinctrl-baytrail.o
 obj-$(CONFIG_PINCTRL_IMX)       += pinctrl-imx.o
 obj-$(CONFIG_PINCTRL_IMX35)     += pinctrl-imx35.o
 obj-$(CONFIG_PINCTRL_IMX51)     += pinctrl-imx51.o
diff --git a/drivers/pinctrl/pinctrl-baytrail.c b/drivers/pinctrl/pinctrl-baytrail.c
new file mode 100644
index 000000000000..e9d735dcebfb
--- /dev/null
+++ b/drivers/pinctrl/pinctrl-baytrail.c
@@ -0,0 +1,543 @@
+/*
+ * Pinctrl GPIO driver for Intel Baytrail
+ * Copyright (c) 2012-2013, Intel Corporation.
+ *
+ * Author: Mathias Nyman <mathias.nyman@linux.intel.com>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
+ *
+ */
+
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/init.h>
+#include <linux/types.h>
+#include <linux/bitops.h>
+#include <linux/interrupt.h>
+#include <linux/irq.h>
+#include <linux/gpio.h>
+#include <linux/irqdomain.h>
+#include <linux/acpi.h>
+#include <linux/acpi_gpio.h>
+#include <linux/platform_device.h>
+#include <linux/seq_file.h>
+#include <linux/io.h>
+#include <linux/pm_runtime.h>
+#include <linux/pinctrl/pinctrl.h>
+
+/* memory mapped register offsets */
+#define BYT_CONF0_REG           0x000
+#define BYT_CONF1_REG           0x004
+#define BYT_VAL_REG             0x008
+#define BYT_DFT_REG             0x00c
+#define BYT_INT_STAT_REG        0x800
+
+/* BYT_CONF0_REG register bits */
+#define BYT_TRIG_NEG            BIT(26)
+#define BYT_TRIG_POS            BIT(25)
+#define BYT_TRIG_LVL            BIT(24)
+#define BYT_PIN_MUX             0x07
+
+/* BYT_VAL_REG register bits */
+#define BYT_INPUT_EN            BIT(2)  /* 0: input enabled (active low)*/
+#define BYT_OUTPUT_EN           BIT(1)  /* 0: output enabled (active low)*/
+#define BYT_LEVEL               BIT(0)
+
+#define BYT_DIR_MASK            (BIT(1) | BIT(2))
+#define BYT_TRIG_MASK           (BIT(26) | BIT(25) | BIT(24))
+
+#define BYT_NGPIO_SCORE         102
+#define BYT_NGPIO_NCORE         28
+#define BYT_NGPIO_SUS           44
+
+/*
+ * Baytrail gpio controller consist of three separate sub-controllers called
+ * SCORE, NCORE and SUS. The sub-controllers are identified by their acpi UID.
+ *
+ * GPIO numbering is _not_ ordered meaning that gpio # 0 in ACPI namespace does
+ * _not_ correspond to the first gpio register at controller's gpio base.
+ * There is no logic or pattern in mapping gpio numbers to registers (pads) so
+ * each sub-controller needs to have its own mapping table
+ */
+
+/* score_pins[gpio_nr] = pad_nr */
+
+static unsigned const score_pins[BYT_NGPIO_SCORE] = {
+        85, 89, 93, 96, 99, 102, 98, 101, 34, 37,
+        36, 38, 39, 35, 40, 84, 62, 61, 64, 59,
+        54, 56, 60, 55, 63, 57, 51, 50, 53, 47,
+        52, 49, 48, 43, 46, 41, 45, 42, 58, 44,
+        95, 105, 70, 68, 67, 66, 69, 71, 65, 72,
+        86, 90, 88, 92, 103, 77, 79, 83, 78, 81,
+        80, 82, 13, 12, 15, 14, 17, 18, 19, 16,
+        2, 1, 0, 4, 6, 7, 9, 8, 33, 32,
+        31, 30, 29, 27, 25, 28, 26, 23, 21, 20,
+        24, 22, 5, 3, 10, 11, 106, 87, 91, 104,
+        97, 100,
+};
+
+static unsigned const ncore_pins[BYT_NGPIO_NCORE] = {
+        19, 18, 17, 20, 21, 22, 24, 25, 23, 16,
+        14, 15, 12, 26, 27, 1, 4, 8, 11, 0,
+        3, 6, 10, 13, 2, 5, 9, 7,
+};
+
+static unsigned const sus_pins[BYT_NGPIO_SUS] = {
+        29, 33, 30, 31, 32, 34, 36, 35, 38, 37,
+        18, 7, 11, 20, 17, 1, 8, 10, 19, 12,
+        0, 2, 23, 39, 28, 27, 22, 21, 24, 25,
+        26, 51, 56, 54, 49, 55, 48, 57, 50, 58,
+        52, 53, 59, 40,
+};
+
+static struct pinctrl_gpio_range byt_ranges[] = {
+        {
+                .name = "1", /* match with acpi _UID in probe */
+                .npins = BYT_NGPIO_SCORE,
+                .pins = score_pins,
+        },
+        {
+                .name = "2",
+                .npins = BYT_NGPIO_NCORE,
+                .pins = ncore_pins,
+        },
+        {
+                .name = "3",
+                .npins = BYT_NGPIO_SUS,
+                .pins = sus_pins,
+        },
+        {
+        },
+};
+
+struct byt_gpio {
+        struct gpio_chip                chip;
+        struct irq_domain               *domain;
+        struct platform_device          *pdev;
+        spinlock_t                      lock;
+        void __iomem                    *reg_base;
+        struct pinctrl_gpio_range       *range;
+};
+
+static void __iomem *byt_gpio_reg(struct gpio_chip *chip, unsigned offset,
+                                 int reg)
+{
+        struct byt_gpio *vg = container_of(chip, struct byt_gpio, chip);
+        u32 reg_offset;
+        void __iomem *ptr;
+
+        if (reg == BYT_INT_STAT_REG)
+                reg_offset = (offset / 32) * 4;
+        else
+                reg_offset = vg->range->pins[offset] * 16;
+
+        ptr = (void __iomem *) (vg->reg_base + reg_offset + reg);
+        return ptr;
+}
+
+static int byt_gpio_request(struct gpio_chip *chip, unsigned offset)
+{