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authorJiri Kosina <jkosina@suse.cz>2014-11-20 08:42:02 -0500
committerJiri Kosina <jkosina@suse.cz>2014-11-20 08:42:02 -0500
commita02001086bbfb4da35d1228bebc2f1b442db455f (patch)
tree62ab47936cef06fd08657ca5b6cd1df98c19be57 /drivers/pinctrl
parenteff264efeeb0898408e8c9df72d8a32621035bed (diff)
parentfc14f9c1272f62c3e8d01300f52467c0d9af50f9 (diff)
Merge Linus' tree to be be to apply submitted patches to newer code than
current trivial.git base
Diffstat (limited to 'drivers/pinctrl')
-rw-r--r--drivers/pinctrl/Kconfig214
-rw-r--r--drivers/pinctrl/Makefile44
-rw-r--r--drivers/pinctrl/berlin/berlin.c29
-rw-r--r--drivers/pinctrl/core.c24
-rw-r--r--drivers/pinctrl/freescale/Kconfig108
-rw-r--r--drivers/pinctrl/freescale/Makefile19
-rw-r--r--drivers/pinctrl/freescale/pinctrl-imx.c (renamed from drivers/pinctrl/pinctrl-imx.c)19
-rw-r--r--drivers/pinctrl/freescale/pinctrl-imx.h (renamed from drivers/pinctrl/pinctrl-imx.h)7
-rw-r--r--drivers/pinctrl/freescale/pinctrl-imx1-core.c (renamed from drivers/pinctrl/pinctrl-imx1-core.c)10
-rw-r--r--drivers/pinctrl/freescale/pinctrl-imx1.c279
-rw-r--r--drivers/pinctrl/freescale/pinctrl-imx1.h (renamed from drivers/pinctrl/pinctrl-imx1.h)0
-rw-r--r--drivers/pinctrl/freescale/pinctrl-imx21.c342
-rw-r--r--drivers/pinctrl/freescale/pinctrl-imx23.c (renamed from drivers/pinctrl/pinctrl-imx23.c)2
-rw-r--r--drivers/pinctrl/freescale/pinctrl-imx25.c (renamed from drivers/pinctrl/pinctrl-imx25.c)2
-rw-r--r--drivers/pinctrl/freescale/pinctrl-imx27.c (renamed from drivers/pinctrl/pinctrl-imx27.c)54
-rw-r--r--drivers/pinctrl/freescale/pinctrl-imx28.c (renamed from drivers/pinctrl/pinctrl-imx28.c)2
-rw-r--r--drivers/pinctrl/freescale/pinctrl-imx35.c (renamed from drivers/pinctrl/pinctrl-imx35.c)2
-rw-r--r--drivers/pinctrl/freescale/pinctrl-imx50.c (renamed from drivers/pinctrl/pinctrl-imx50.c)2
-rw-r--r--drivers/pinctrl/freescale/pinctrl-imx51.c (renamed from drivers/pinctrl/pinctrl-imx51.c)2
-rw-r--r--drivers/pinctrl/freescale/pinctrl-imx53.c (renamed from drivers/pinctrl/pinctrl-imx53.c)2
-rw-r--r--drivers/pinctrl/freescale/pinctrl-imx6dl.c (renamed from drivers/pinctrl/pinctrl-imx6dl.c)2
-rw-r--r--drivers/pinctrl/freescale/pinctrl-imx6q.c (renamed from drivers/pinctrl/pinctrl-imx6q.c)2
-rw-r--r--drivers/pinctrl/freescale/pinctrl-imx6sl.c (renamed from drivers/pinctrl/pinctrl-imx6sl.c)3
-rw-r--r--drivers/pinctrl/freescale/pinctrl-imx6sx.c (renamed from drivers/pinctrl/pinctrl-imx6sx.c)2
-rw-r--r--drivers/pinctrl/freescale/pinctrl-mxs.c (renamed from drivers/pinctrl/pinctrl-mxs.c)8
-rw-r--r--drivers/pinctrl/freescale/pinctrl-mxs.h (renamed from drivers/pinctrl/pinctrl-mxs.h)0
-rw-r--r--drivers/pinctrl/freescale/pinctrl-vf610.c (renamed from drivers/pinctrl/pinctrl-vf610.c)2
-rw-r--r--drivers/pinctrl/mvebu/pinctrl-mvebu.c6
-rw-r--r--drivers/pinctrl/nomadik/Kconfig51
-rw-r--r--drivers/pinctrl/nomadik/Makefile10
-rw-r--r--drivers/pinctrl/nomadik/pinctrl-ab8500.c (renamed from drivers/pinctrl/pinctrl-ab8500.c)0
-rw-r--r--drivers/pinctrl/nomadik/pinctrl-ab8505.c (renamed from drivers/pinctrl/pinctrl-ab8505.c)0
-rw-r--r--drivers/pinctrl/nomadik/pinctrl-ab8540.c (renamed from drivers/pinctrl/pinctrl-ab8540.c)0
-rw-r--r--drivers/pinctrl/nomadik/pinctrl-ab9540.c (renamed from drivers/pinctrl/pinctrl-ab9540.c)0
-rw-r--r--drivers/pinctrl/nomadik/pinctrl-abx500.c (renamed from drivers/pinctrl/pinctrl-abx500.c)137
-rw-r--r--drivers/pinctrl/nomadik/pinctrl-abx500.h (renamed from drivers/pinctrl/pinctrl-abx500.h)0
-rw-r--r--drivers/pinctrl/nomadik/pinctrl-nomadik-db8500.c (renamed from drivers/pinctrl/pinctrl-nomadik-db8500.c)0
-rw-r--r--drivers/pinctrl/nomadik/pinctrl-nomadik-db8540.c (renamed from drivers/pinctrl/pinctrl-nomadik-db8540.c)0
-rw-r--r--drivers/pinctrl/nomadik/pinctrl-nomadik-stn8815.c (renamed from drivers/pinctrl/pinctrl-nomadik-stn8815.c)0
-rw-r--r--drivers/pinctrl/nomadik/pinctrl-nomadik.c (renamed from drivers/pinctrl/pinctrl-nomadik.c)162
-rw-r--r--drivers/pinctrl/nomadik/pinctrl-nomadik.h (renamed from drivers/pinctrl/pinctrl-nomadik.h)0
-rw-r--r--drivers/pinctrl/pinctrl-adi2.c48
-rw-r--r--drivers/pinctrl/pinctrl-as3722.c15
-rw-r--r--drivers/pinctrl/pinctrl-at91.c243
-rw-r--r--drivers/pinctrl/pinctrl-baytrail.c112
-rw-r--r--drivers/pinctrl/pinctrl-bcm281xx.c10
-rw-r--r--drivers/pinctrl/pinctrl-bcm2835.c15
-rw-r--r--drivers/pinctrl/pinctrl-coh901.c10
-rw-r--r--drivers/pinctrl/pinctrl-lantiq.c8
-rw-r--r--drivers/pinctrl/pinctrl-palmas.c5
-rw-r--r--drivers/pinctrl/pinctrl-rockchip.c416
-rw-r--r--drivers/pinctrl/pinctrl-single.c79
-rw-r--r--drivers/pinctrl/pinctrl-st.c22
-rw-r--r--drivers/pinctrl/pinctrl-tb10x.c21
-rw-r--r--drivers/pinctrl/pinctrl-tegra-xusb.c974
-rw-r--r--drivers/pinctrl/pinctrl-tegra.c20
-rw-r--r--drivers/pinctrl/pinctrl-tegra114.c2
-rw-r--r--drivers/pinctrl/pinctrl-tegra124.c69
-rw-r--r--drivers/pinctrl/pinctrl-tegra20.c2
-rw-r--r--drivers/pinctrl/pinctrl-tegra30.c2
-rw-r--r--drivers/pinctrl/pinctrl-tz1090-pdc.c35
-rw-r--r--drivers/pinctrl/pinctrl-tz1090.c64
-rw-r--r--drivers/pinctrl/pinctrl-u300.c20
-rw-r--r--drivers/pinctrl/pinctrl-xway.c2
-rw-r--r--drivers/pinctrl/pinmux.c14
-rw-r--r--drivers/pinctrl/qcom/Kconfig50
-rw-r--r--drivers/pinctrl/qcom/Makefile7
-rw-r--r--drivers/pinctrl/qcom/pinctrl-apq8064.c (renamed from drivers/pinctrl/pinctrl-apq8064.c)28
-rw-r--r--drivers/pinctrl/qcom/pinctrl-apq8084.c1245
-rw-r--r--drivers/pinctrl/qcom/pinctrl-ipq8064.c (renamed from drivers/pinctrl/pinctrl-ipq8064.c)19
-rw-r--r--drivers/pinctrl/qcom/pinctrl-msm.c (renamed from drivers/pinctrl/pinctrl-msm.c)99
-rw-r--r--drivers/pinctrl/qcom/pinctrl-msm.h (renamed from drivers/pinctrl/pinctrl-msm.h)3
-rw-r--r--drivers/pinctrl/qcom/pinctrl-msm8960.c1284
-rw-r--r--drivers/pinctrl/qcom/pinctrl-msm8x74.c (renamed from drivers/pinctrl/pinctrl-msm8x74.c)31
-rw-r--r--drivers/pinctrl/samsung/Kconfig28
-rw-r--r--drivers/pinctrl/samsung/Makefile7
-rw-r--r--drivers/pinctrl/samsung/pinctrl-exynos.c (renamed from drivers/pinctrl/pinctrl-exynos.c)376
-rw-r--r--drivers/pinctrl/samsung/pinctrl-exynos.h (renamed from drivers/pinctrl/pinctrl-exynos.h)0
-rw-r--r--drivers/pinctrl/samsung/pinctrl-exynos5440.c (renamed from drivers/pinctrl/pinctrl-exynos5440.c)23
-rw-r--r--drivers/pinctrl/samsung/pinctrl-s3c24xx.c (renamed from drivers/pinctrl/pinctrl-s3c24xx.c)0
-rw-r--r--drivers/pinctrl/samsung/pinctrl-s3c64xx.c (renamed from drivers/pinctrl/pinctrl-s3c64xx.c)0
-rw-r--r--drivers/pinctrl/samsung/pinctrl-samsung.c (renamed from drivers/pinctrl/pinctrl-samsung.c)746
-rw-r--r--drivers/pinctrl/samsung/pinctrl-samsung.h (renamed from drivers/pinctrl/pinctrl-samsung.h)19
-rw-r--r--drivers/pinctrl/sh-pfc/core.c10
-rw-r--r--drivers/pinctrl/sh-pfc/core.h1
-rw-r--r--drivers/pinctrl/sh-pfc/gpio.c9
-rw-r--r--drivers/pinctrl/sh-pfc/pfc-r8a73a4.c4
-rw-r--r--drivers/pinctrl/sh-pfc/pfc-r8a7740.c4
-rw-r--r--drivers/pinctrl/sh-pfc/pfc-r8a7791.c417
-rw-r--r--drivers/pinctrl/sh-pfc/pfc-sh7372.c4
-rw-r--r--drivers/pinctrl/sh-pfc/pfc-sh73a0.c30
-rw-r--r--drivers/pinctrl/sh-pfc/pinctrl.c28
-rw-r--r--drivers/pinctrl/sh-pfc/sh_pfc.h1
-rw-r--r--drivers/pinctrl/sirf/pinctrl-atlas6.c129
-rw-r--r--drivers/pinctrl/sirf/pinctrl-prima2.c173
-rw-r--r--drivers/pinctrl/sirf/pinctrl-sirf.c85
-rw-r--r--drivers/pinctrl/spear/Kconfig1
-rw-r--r--drivers/pinctrl/spear/pinctrl-plgpio.c84
-rw-r--r--drivers/pinctrl/spear/pinctrl-spear.c11
-rw-r--r--drivers/pinctrl/spear/pinctrl-spear1310.c2
-rw-r--r--drivers/pinctrl/spear/pinctrl-spear1340.c2
-rw-r--r--drivers/pinctrl/spear/pinctrl-spear300.c2
-rw-r--r--drivers/pinctrl/spear/pinctrl-spear310.c2
-rw-r--r--drivers/pinctrl/spear/pinctrl-spear320.c2
-rw-r--r--drivers/pinctrl/sunxi/Kconfig24
-rw-r--r--drivers/pinctrl/sunxi/Makefile2
-rw-r--r--drivers/pinctrl/sunxi/pinctrl-sun4i-a10.c1
-rw-r--r--drivers/pinctrl/sunxi/pinctrl-sun5i-a10s.c1
-rw-r--r--drivers/pinctrl/sunxi/pinctrl-sun5i-a13.c4
-rw-r--r--drivers/pinctrl/sunxi/pinctrl-sun6i-a31-r.c1
-rw-r--r--drivers/pinctrl/sunxi/pinctrl-sun6i-a31.c217
-rw-r--r--drivers/pinctrl/sunxi/pinctrl-sun7i-a20.c1
-rw-r--r--drivers/pinctrl/sunxi/pinctrl-sun8i-a23-r.c142
-rw-r--r--drivers/pinctrl/sunxi/pinctrl-sun8i-a23.c593
-rw-r--r--drivers/pinctrl/sunxi/pinctrl-sunxi.c195
-rw-r--r--drivers/pinctrl/sunxi/pinctrl-sunxi.h44
-rw-r--r--drivers/pinctrl/vt8500/pinctrl-wmt.c29
117 files changed, 7815 insertions, 2161 deletions
diff --git a/drivers/pinctrl/Kconfig b/drivers/pinctrl/Kconfig
index 0042ccb46b9a..c6a66de6ed72 100644
--- a/drivers/pinctrl/Kconfig
+++ b/drivers/pinctrl/Kconfig
@@ -11,10 +11,10 @@ menu "Pin controllers"
11 depends on PINCTRL 11 depends on PINCTRL
12 12
13config PINMUX 13config PINMUX
14 bool "Support pin multiplexing controllers" 14 bool "Support pin multiplexing controllers" if COMPILE_TEST
15 15
16config PINCONF 16config PINCONF
17 bool "Support pin configuration controllers" 17 bool "Support pin configuration controllers" if COMPILE_TEST
18 18
19config GENERIC_PINCONF 19config GENERIC_PINCONF
20 bool 20 bool
@@ -26,29 +26,6 @@ config DEBUG_PINCTRL
26 help 26 help
27 Say Y here to add some extra checks and diagnostics to PINCTRL calls. 27 Say Y here to add some extra checks and diagnostics to PINCTRL calls.
28 28
29config PINCTRL_ABX500
30 bool "ST-Ericsson ABx500 family Mixed Signal Circuit gpio functions"
31 depends on AB8500_CORE
32 select GENERIC_PINCONF
33 help
34 Select this to enable the ABx500 family IC GPIO driver
35
36config PINCTRL_AB8500
37 bool "AB8500 pin controller driver"
38 depends on PINCTRL_ABX500 && ARCH_U8500
39
40config PINCTRL_AB8540
41 bool "AB8540 pin controller driver"
42 depends on PINCTRL_ABX500 && ARCH_U8500
43
44config PINCTRL_AB9540
45 bool "AB9540 pin controller driver"
46 depends on PINCTRL_ABX500 && ARCH_U8500
47
48config PINCTRL_AB8505
49 bool "AB8505 pin controller driver"
50 depends on PINCTRL_ABX500 && ARCH_U8500
51
52config PINCTRL_ADI2 29config PINCTRL_ADI2
53 bool "ADI pin controller driver" 30 bool "ADI pin controller driver"
54 depends on BLACKFIN 31 depends on BLACKFIN
@@ -93,7 +70,7 @@ config PINCTRL_AT91
93config PINCTRL_BAYTRAIL 70config PINCTRL_BAYTRAIL
94 bool "Intel Baytrail GPIO pin control" 71 bool "Intel Baytrail GPIO pin control"
95 depends on GPIOLIB && ACPI && X86 72 depends on GPIOLIB && ACPI && X86
96 select IRQ_DOMAIN 73 select GPIOLIB_IRQCHIP
97 help 74 help
98 driver for memory mapped GPIO functionality on Intel Baytrail 75 driver for memory mapped GPIO functionality on Intel Baytrail
99 platforms. Supports 3 banks with 102, 28 and 44 gpios. 76 platforms. Supports 3 banks with 102, 28 and 44 gpios.
@@ -109,7 +86,7 @@ config PINCTRL_BCM2835
109 86
110config PINCTRL_BCM281XX 87config PINCTRL_BCM281XX
111 bool "Broadcom BCM281xx pinctrl driver" 88 bool "Broadcom BCM281xx pinctrl driver"
112 depends on OF 89 depends on OF && (ARCH_BCM_MOBILE || COMPILE_TEST)
113 select PINMUX 90 select PINMUX
114 select PINCONF 91 select PINCONF
115 select GENERIC_PINCONF 92 select GENERIC_PINCONF
@@ -120,88 +97,6 @@ config PINCTRL_BCM281XX
120 BCM28145, and BCM28155 SoCs. This driver requires the pinctrl 97 BCM28145, and BCM28155 SoCs. This driver requires the pinctrl
121 framework. GPIO is provided by a separate GPIO driver. 98 framework. GPIO is provided by a separate GPIO driver.
122 99
123config PINCTRL_IMX
124 bool
125 select PINMUX
126 select PINCONF
127
128config PINCTRL_IMX1_CORE
129 bool
130 select PINMUX
131 select PINCONF
132
133config PINCTRL_IMX27
134 bool "IMX27 pinctrl driver"
135 depends on SOC_IMX27
136 select PINCTRL_IMX1_CORE
137 help
138 Say Y here to enable the imx27 pinctrl driver
139
140
141config PINCTRL_IMX25
142 bool "IMX25 pinctrl driver"
143 depends on OF
144 depends on SOC_IMX25
145 select PINCTRL_IMX
146 help
147 Say Y here to enable the imx25 pinctrl driver
148
149config PINCTRL_IMX35
150 bool "IMX35 pinctrl driver"
151 depends on SOC_IMX35
152 select PINCTRL_IMX
153 help
154 Say Y here to enable the imx35 pinctrl driver
155
156config PINCTRL_IMX50
157 bool "IMX50 pinctrl driver"
158 depends on SOC_IMX50
159 select PINCTRL_IMX
160 help
161 Say Y here to enable the imx50 pinctrl driver
162
163config PINCTRL_IMX51
164 bool "IMX51 pinctrl driver"
165 depends on SOC_IMX51
166 select PINCTRL_IMX
167 help
168 Say Y here to enable the imx51 pinctrl driver
169
170config PINCTRL_IMX53
171 bool "IMX53 pinctrl driver"
172 depends on SOC_IMX53
173 select PINCTRL_IMX
174 help
175 Say Y here to enable the imx53 pinctrl driver
176
177config PINCTRL_IMX6Q
178 bool "IMX6Q/DL pinctrl driver"
179 depends on SOC_IMX6Q
180 select PINCTRL_IMX
181 help
182 Say Y here to enable the imx6q/dl pinctrl driver
183
184config PINCTRL_IMX6SL
185 bool "IMX6SL pinctrl driver"
186 depends on SOC_IMX6SL
187 select PINCTRL_IMX
188 help
189 Say Y here to enable the imx6sl pinctrl driver
190
191config PINCTRL_IMX6SX
192 bool "IMX6SX pinctrl driver"
193 depends on SOC_IMX6SX
194 select PINCTRL_IMX
195 help
196 Say Y here to enable the imx6sx pinctrl driver
197
198config PINCTRL_VF610
199 bool "Freescale Vybrid VF610 pinctrl driver"
200 depends on SOC_VF610
201 select PINCTRL_IMX
202 help
203 Say Y here to enable the Freescale Vybrid VF610 pinctrl driver
204
205config PINCTRL_LANTIQ 100config PINCTRL_LANTIQ
206 bool 101 bool
207 depends on LANTIQ 102 depends on LANTIQ
@@ -213,71 +108,6 @@ config PINCTRL_FALCON
213 depends on SOC_FALCON 108 depends on SOC_FALCON
214 depends on PINCTRL_LANTIQ 109 depends on PINCTRL_LANTIQ
215 110
216config PINCTRL_MXS
217 bool
218 select PINMUX
219 select PINCONF
220
221config PINCTRL_IMX23
222 bool
223 select PINCTRL_MXS
224
225config PINCTRL_IMX28
226 bool
227 select PINCTRL_MXS
228
229config PINCTRL_MSM
230 bool
231 select PINMUX
232 select PINCONF
233 select GENERIC_PINCONF
234 select GPIOLIB_IRQCHIP
235
236config PINCTRL_APQ8064
237 tristate "Qualcomm APQ8064 pin controller driver"
238 depends on GPIOLIB && OF
239 select PINCTRL_MSM
240 help
241 This is the pinctrl, pinmux, pinconf and gpiolib driver for the
242 Qualcomm TLMM block found in the Qualcomm APQ8064 platform.
243
244config PINCTRL_IPQ8064
245 tristate "Qualcomm IPQ8064 pin controller driver"
246 depends on GPIOLIB && OF
247 select PINCTRL_MSM
248 help
249 This is the pinctrl, pinmux, pinconf and gpiolib driver for the
250 Qualcomm TLMM block found in the Qualcomm IPQ8064 platform.
251
252config PINCTRL_MSM8X74
253 tristate "Qualcomm 8x74 pin controller driver"
254 depends on GPIOLIB && OF && (ARCH_QCOM || COMPILE_TEST)
255 select PINCTRL_MSM
256 help
257 This is the pinctrl, pinmux, pinconf and gpiolib driver for the
258 Qualcomm TLMM block found in the Qualcomm 8974 platform.
259
260config PINCTRL_NOMADIK
261 bool "Nomadik pin controller driver"
262 depends on ARCH_U8500 || ARCH_NOMADIK
263 select PINMUX
264 select PINCONF
265 select GPIOLIB
266 select OF_GPIO
267 select GPIOLIB_IRQCHIP
268
269config PINCTRL_STN8815
270 bool "STN8815 pin controller driver"
271 depends on PINCTRL_NOMADIK && ARCH_NOMADIK
272
273config PINCTRL_DB8500
274 bool "DB8500 pin controller driver"
275 depends on PINCTRL_NOMADIK && ARCH_U8500
276
277config PINCTRL_DB8540
278 bool "DB8540 pin controller driver"
279 depends on PINCTRL_NOMADIK && ARCH_U8500
280
281config PINCTRL_ROCKCHIP 111config PINCTRL_ROCKCHIP
282 bool 112 bool
283 select PINMUX 113 select PINMUX
@@ -328,6 +158,12 @@ config PINCTRL_TEGRA124
328 bool 158 bool
329 select PINCTRL_TEGRA 159 select PINCTRL_TEGRA
330 160
161config PINCTRL_TEGRA_XUSB
162 def_bool y if ARCH_TEGRA
163 select GENERIC_PHY
164 select PINCONF
165 select PINMUX
166
331config PINCTRL_TZ1090 167config PINCTRL_TZ1090
332 bool "Toumaz Xenif TZ1090 pin control driver" 168 bool "Toumaz Xenif TZ1090 pin control driver"
333 depends on SOC_TZ1090 169 depends on SOC_TZ1090
@@ -356,22 +192,6 @@ config PINCTRL_COH901
356 COH 901 335 and COH 901 571/3. They contain 3, 5 or 7 192 COH 901 335 and COH 901 571/3. They contain 3, 5 or 7
357 ports of 8 GPIO pins each. 193 ports of 8 GPIO pins each.
358 194
359config PINCTRL_SAMSUNG
360 bool
361 select PINMUX
362 select PINCONF
363
364config PINCTRL_EXYNOS
365 bool "Pinctrl driver data for Samsung EXYNOS SoCs other than 5440"
366 depends on OF && GPIOLIB && (ARCH_EXYNOS || ARCH_S5PV210)
367 select PINCTRL_SAMSUNG
368
369config PINCTRL_EXYNOS5440
370 bool "Samsung EXYNOS5440 SoC pinctrl driver"
371 depends on SOC_EXYNOS5440
372 select PINMUX
373 select PINCONF
374
375config PINCTRL_PALMAS 195config PINCTRL_PALMAS
376 bool "Pinctrl driver for the PALMAS Series MFD devices" 196 bool "Pinctrl driver for the PALMAS Series MFD devices"
377 depends on OF && MFD_PALMAS 197 depends on OF && MFD_PALMAS
@@ -383,18 +203,12 @@ config PINCTRL_PALMAS
383 open drain configuration for the Palmas series devices like 203 open drain configuration for the Palmas series devices like
384 TPS65913, TPS80036 etc. 204 TPS65913, TPS80036 etc.
385 205
386config PINCTRL_S3C24XX
387 bool "Samsung S3C24XX SoC pinctrl driver"
388 depends on ARCH_S3C24XX
389 select PINCTRL_SAMSUNG
390
391config PINCTRL_S3C64XX
392 bool "Samsung S3C64XX SoC pinctrl driver"
393 depends on ARCH_S3C64XX
394 select PINCTRL_SAMSUNG
395
396source "drivers/pinctrl/berlin/Kconfig" 206source "drivers/pinctrl/berlin/Kconfig"
207source "drivers/pinctrl/freescale/Kconfig"
397source "drivers/pinctrl/mvebu/Kconfig" 208source "drivers/pinctrl/mvebu/Kconfig"
209source "drivers/pinctrl/nomadik/Kconfig"
210source "drivers/pinctrl/qcom/Kconfig"
211source "drivers/pinctrl/samsung/Kconfig"
398source "drivers/pinctrl/sh-pfc/Kconfig" 212source "drivers/pinctrl/sh-pfc/Kconfig"
399source "drivers/pinctrl/spear/Kconfig" 213source "drivers/pinctrl/spear/Kconfig"
400source "drivers/pinctrl/sunxi/Kconfig" 214source "drivers/pinctrl/sunxi/Kconfig"
diff --git a/drivers/pinctrl/Makefile b/drivers/pinctrl/Makefile
index c4b5d405b8f5..51f52d32859e 100644
--- a/drivers/pinctrl/Makefile
+++ b/drivers/pinctrl/Makefile
@@ -9,11 +9,6 @@ ifeq ($(CONFIG_OF),y)
9obj-$(CONFIG_PINCTRL) += devicetree.o 9obj-$(CONFIG_PINCTRL) += devicetree.o
10endif 10endif
11obj-$(CONFIG_GENERIC_PINCONF) += pinconf-generic.o 11obj-$(CONFIG_GENERIC_PINCONF) += pinconf-generic.o
12obj-$(CONFIG_PINCTRL_ABX500) += pinctrl-abx500.o
13obj-$(CONFIG_PINCTRL_AB8500) += pinctrl-ab8500.o
14obj-$(CONFIG_PINCTRL_AB8540) += pinctrl-ab8540.o
15obj-$(CONFIG_PINCTRL_AB9540) += pinctrl-ab9540.o
16obj-$(CONFIG_PINCTRL_AB8505) += pinctrl-ab8505.o
17obj-$(CONFIG_PINCTRL_ADI2) += pinctrl-adi2.o 12obj-$(CONFIG_PINCTRL_ADI2) += pinctrl-adi2.o
18obj-$(CONFIG_PINCTRL_AS3722) += pinctrl-as3722.o 13obj-$(CONFIG_PINCTRL_AS3722) += pinctrl-as3722.o
19obj-$(CONFIG_PINCTRL_BF54x) += pinctrl-adi2-bf54x.o 14obj-$(CONFIG_PINCTRL_BF54x) += pinctrl-adi2-bf54x.o
@@ -22,30 +17,7 @@ obj-$(CONFIG_PINCTRL_AT91) += pinctrl-at91.o
22obj-$(CONFIG_PINCTRL_BCM2835) += pinctrl-bcm2835.o 17obj-$(CONFIG_PINCTRL_BCM2835) += pinctrl-bcm2835.o
23obj-$(CONFIG_PINCTRL_BAYTRAIL) += pinctrl-baytrail.o 18obj-$(CONFIG_PINCTRL_BAYTRAIL) += pinctrl-baytrail.o
24obj-$(CONFIG_PINCTRL_BCM281XX) += pinctrl-bcm281xx.o 19obj-$(CONFIG_PINCTRL_BCM281XX) += pinctrl-bcm281xx.o
25obj-$(CONFIG_PINCTRL_IMX) += pinctrl-imx.o
26obj-$(CONFIG_PINCTRL_IMX1_CORE) += pinctrl-imx1-core.o
27obj-$(CONFIG_PINCTRL_IMX27) += pinctrl-imx27.o
28obj-$(CONFIG_PINCTRL_IMX35) += pinctrl-imx35.o
29obj-$(CONFIG_PINCTRL_IMX50) += pinctrl-imx50.o
30obj-$(CONFIG_PINCTRL_IMX51) += pinctrl-imx51.o
31obj-$(CONFIG_PINCTRL_IMX53) += pinctrl-imx53.o
32obj-$(CONFIG_PINCTRL_IMX6Q) += pinctrl-imx6q.o
33obj-$(CONFIG_PINCTRL_IMX6Q) += pinctrl-imx6dl.o
34obj-$(CONFIG_PINCTRL_IMX6SL) += pinctrl-imx6sl.o
35obj-$(CONFIG_PINCTRL_IMX6SX) += pinctrl-imx6sx.o
36obj-$(CONFIG_PINCTRL_FALCON) += pinctrl-falcon.o 20obj-$(CONFIG_PINCTRL_FALCON) += pinctrl-falcon.o
37obj-$(CONFIG_PINCTRL_MXS) += pinctrl-mxs.o
38obj-$(CONFIG_PINCTRL_IMX23) += pinctrl-imx23.o
39obj-$(CONFIG_PINCTRL_IMX25) += pinctrl-imx25.o
40obj-$(CONFIG_PINCTRL_IMX28) += pinctrl-imx28.o
41obj-$(CONFIG_PINCTRL_MSM) += pinctrl-msm.o
42obj-$(CONFIG_PINCTRL_APQ8064) += pinctrl-apq8064.o
43obj-$(CONFIG_PINCTRL_IPQ8064) += pinctrl-ipq8064.o
44obj-$(CONFIG_PINCTRL_MSM8X74) += pinctrl-msm8x74.o
45obj-$(CONFIG_PINCTRL_NOMADIK) += pinctrl-nomadik.o
46obj-$(CONFIG_PINCTRL_STN8815) += pinctrl-nomadik-stn8815.o
47obj-$(CONFIG_PINCTRL_DB8500) += pinctrl-nomadik-db8500.o
48obj-$(CONFIG_PINCTRL_DB8540) += pinctrl-nomadik-db8540.o
49obj-$(CONFIG_PINCTRL_PALMAS) += pinctrl-palmas.o 21obj-$(CONFIG_PINCTRL_PALMAS) += pinctrl-palmas.o
50obj-$(CONFIG_PINCTRL_ROCKCHIP) += pinctrl-rockchip.o 22obj-$(CONFIG_PINCTRL_ROCKCHIP) += pinctrl-rockchip.o
51obj-$(CONFIG_PINCTRL_SINGLE) += pinctrl-single.o 23obj-$(CONFIG_PINCTRL_SINGLE) += pinctrl-single.o
@@ -55,25 +27,23 @@ obj-$(CONFIG_PINCTRL_TEGRA20) += pinctrl-tegra20.o
55obj-$(CONFIG_PINCTRL_TEGRA30) += pinctrl-tegra30.o 27obj-$(CONFIG_PINCTRL_TEGRA30) += pinctrl-tegra30.o
56obj-$(CONFIG_PINCTRL_TEGRA114) += pinctrl-tegra114.o 28obj-$(CONFIG_PINCTRL_TEGRA114) += pinctrl-tegra114.o
57obj-$(CONFIG_PINCTRL_TEGRA124) += pinctrl-tegra124.o 29obj-$(CONFIG_PINCTRL_TEGRA124) += pinctrl-tegra124.o
30obj-$(CONFIG_PINCTRL_TEGRA_XUSB) += pinctrl-tegra-xusb.o
58obj-$(CONFIG_PINCTRL_TZ1090) += pinctrl-tz1090.o 31obj-$(CONFIG_PINCTRL_TZ1090) += pinctrl-tz1090.o
59obj-$(CONFIG_PINCTRL_TZ1090_PDC) += pinctrl-tz1090-pdc.o 32obj-$(CONFIG_PINCTRL_TZ1090_PDC) += pinctrl-tz1090-pdc.o
60obj-$(CONFIG_PINCTRL_U300) += pinctrl-u300.o 33obj-$(CONFIG_PINCTRL_U300) += pinctrl-u300.o
61obj-$(CONFIG_PINCTRL_COH901) += pinctrl-coh901.o 34obj-$(CONFIG_PINCTRL_COH901) += pinctrl-coh901.o
62obj-$(CONFIG_PINCTRL_SAMSUNG) += pinctrl-samsung.o
63obj-$(CONFIG_PINCTRL_EXYNOS) += pinctrl-exynos.o
64obj-$(CONFIG_PINCTRL_EXYNOS5440) += pinctrl-exynos5440.o
65obj-$(CONFIG_PINCTRL_S3C24XX) += pinctrl-s3c24xx.o
66obj-$(CONFIG_PINCTRL_S3C64XX) += pinctrl-s3c64xx.o
67obj-$(CONFIG_PINCTRL_XWAY) += pinctrl-xway.o 35obj-$(CONFIG_PINCTRL_XWAY) += pinctrl-xway.o
68obj-$(CONFIG_PINCTRL_LANTIQ) += pinctrl-lantiq.o 36obj-$(CONFIG_PINCTRL_LANTIQ) += pinctrl-lantiq.o
69obj-$(CONFIG_PINCTRL_TB10X) += pinctrl-tb10x.o 37obj-$(CONFIG_PINCTRL_TB10X) += pinctrl-tb10x.o
70obj-$(CONFIG_PINCTRL_ST) += pinctrl-st.o 38obj-$(CONFIG_PINCTRL_ST) += pinctrl-st.o
71obj-$(CONFIG_PINCTRL_VF610) += pinctrl-vf610.o
72 39
73obj-$(CONFIG_ARCH_BERLIN) += berlin/ 40obj-$(CONFIG_ARCH_BERLIN) += berlin/
41obj-y += freescale/
74obj-$(CONFIG_PLAT_ORION) += mvebu/ 42obj-$(CONFIG_PLAT_ORION) += mvebu/
75obj-$(CONFIG_ARCH_SHMOBILE) += sh-pfc/ 43obj-y += nomadik/
76obj-$(CONFIG_SUPERH) += sh-pfc/ 44obj-$(CONFIG_ARCH_QCOM) += qcom/
45obj-$(CONFIG_PINCTRL_SAMSUNG) += samsung/
46obj-$(CONFIG_PINCTRL_SH_PFC) += sh-pfc/
77obj-$(CONFIG_PLAT_SPEAR) += spear/ 47obj-$(CONFIG_PLAT_SPEAR) += spear/
78obj-$(CONFIG_ARCH_VT8500) += vt8500/
79obj-$(CONFIG_ARCH_SUNXI) += sunxi/ 48obj-$(CONFIG_ARCH_SUNXI) += sunxi/
49obj-$(CONFIG_ARCH_VT8500) += vt8500/
diff --git a/drivers/pinctrl/berlin/berlin.c b/drivers/pinctrl/berlin/berlin.c
index 86db2235ab00..7f0b0f93242b 100644
--- a/drivers/pinctrl/berlin/berlin.c
+++ b/drivers/pinctrl/berlin/berlin.c
@@ -99,30 +99,11 @@ static int berlin_pinctrl_dt_node_to_map(struct pinctrl_dev *pctrl_dev,
99 return 0; 99 return 0;
100} 100}
101 101
102static void berlin_pinctrl_dt_free_map(struct pinctrl_dev *pctrl_dev,
103 struct pinctrl_map *map,
104 unsigned nmaps)
105{
106 int i;
107
108 for (i = 0; i < nmaps; i++) {
109 if (map[i].type == PIN_MAP_TYPE_MUX_GROUP) {
110 kfree(map[i].data.mux.group);
111
112 /* a function can be applied to multiple groups */
113 if (i == 0)
114 kfree(map[i].data.mux.function);
115 }
116 }
117
118 kfree(map);
119}
120
121static const struct pinctrl_ops berlin_pinctrl_ops = { 102static const struct pinctrl_ops berlin_pinctrl_ops = {
122 .get_groups_count = &berlin_pinctrl_get_group_count, 103 .get_groups_count = &berlin_pinctrl_get_group_count,
123 .get_group_name = &berlin_pinctrl_get_group_name, 104 .get_group_name = &berlin_pinctrl_get_group_name,
124 .dt_node_to_map = &berlin_pinctrl_dt_node_to_map, 105 .dt_node_to_map = &berlin_pinctrl_dt_node_to_map,
125 .dt_free_map = &berlin_pinctrl_dt_free_map, 106 .dt_free_map = &pinctrl_utils_dt_free_map,
126}; 107};
127 108
128static int berlin_pinmux_get_functions_count(struct pinctrl_dev *pctrl_dev) 109static int berlin_pinmux_get_functions_count(struct pinctrl_dev *pctrl_dev)
@@ -170,9 +151,9 @@ berlin_pinctrl_find_function_by_name(struct berlin_pinctrl *pctrl,
170 return NULL; 151 return NULL;
171} 152}
172 153
173static int berlin_pinmux_enable(struct pinctrl_dev *pctrl_dev, 154static int berlin_pinmux_set(struct pinctrl_dev *pctrl_dev,
174 unsigned function, 155 unsigned function,
175 unsigned group) 156 unsigned group)
176{ 157{
177 struct berlin_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctrl_dev); 158 struct berlin_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctrl_dev);
178 const struct berlin_desc_group *group_desc = pctrl->desc->groups + group; 159 const struct berlin_desc_group *group_desc = pctrl->desc->groups + group;
@@ -197,7 +178,7 @@ static const struct pinmux_ops berlin_pinmux_ops = {
197 .get_functions_count = &berlin_pinmux_get_functions_count, 178 .get_functions_count = &berlin_pinmux_get_functions_count,
198 .get_function_name = &berlin_pinmux_get_function_name, 179 .get_function_name = &berlin_pinmux_get_function_name,
199 .get_function_groups = &berlin_pinmux_get_function_groups, 180 .get_function_groups = &berlin_pinmux_get_function_groups,
200 .enable = &berlin_pinmux_enable, 181 .set_mux = &berlin_pinmux_set,
201}; 182};
202 183
203static int berlin_pinctrl_add_function(struct berlin_pinctrl *pctrl, 184static int berlin_pinctrl_add_function(struct berlin_pinctrl *pctrl,
diff --git a/drivers/pinctrl/core.c b/drivers/pinctrl/core.c
index e09474ecde23..e4f65510c87e 100644
--- a/drivers/pinctrl/core.c
+++ b/drivers/pinctrl/core.c
@@ -992,29 +992,15 @@ int pinctrl_select_state(struct pinctrl *p, struct pinctrl_state *state)
992 992
993 if (p->state) { 993 if (p->state) {
994 /* 994 /*
995 * The set of groups with a mux configuration in the old state 995 * For each pinmux setting in the old state, forget SW's record
996 * may not be identical to the set of groups with a mux setting 996 * of mux owner for that pingroup. Any pingroups which are
997 * in the new state. While this might be unusual, it's entirely 997 * still owned by the new state will be re-acquired by the call
998 * possible for the "user"-supplied mapping table to be written 998 * to pinmux_enable_setting() in the loop below.
999 * that way. For each group that was configured in the old state
1000 * but not in the new state, this code puts that group into a
1001 * safe/disabled state.
1002 */ 999 */
1003 list_for_each_entry(setting, &p->state->settings, node) { 1000 list_for_each_entry(setting, &p->state->settings, node) {
1004 bool found = false;
1005 if (setting->type != PIN_MAP_TYPE_MUX_GROUP) 1001 if (setting->type != PIN_MAP_TYPE_MUX_GROUP)
1006 continue; 1002 continue;
1007 list_for_each_entry(setting2, &state->settings, node) { 1003 pinmux_disable_setting(setting);
1008 if (setting2->type != PIN_MAP_TYPE_MUX_GROUP)
1009 continue;
1010 if (setting2->data.mux.group ==
1011 setting->data.mux.group) {
1012 found = true;
1013 break;
1014 }
1015 }
1016 if (!found)
1017 pinmux_disable_setting(setting);
1018 } 1004 }
1019 } 1005 }
1020 1006
diff --git a/drivers/pinctrl/freescale/Kconfig b/drivers/pinctrl/freescale/Kconfig
new file mode 100644
index 000000000000..16aac38793fe
--- /dev/null
+++ b/drivers/pinctrl/freescale/Kconfig
@@ -0,0 +1,108 @@
1config PINCTRL_IMX
2 bool
3 select PINMUX
4 select PINCONF
5
6config PINCTRL_IMX1_CORE
7 bool
8 select PINMUX
9 select PINCONF
10
11config PINCTRL_IMX1
12 bool "IMX1 pinctrl driver"
13 depends on SOC_IMX1
14 select PINCTRL_IMX1_CORE
15 help
16 Say Y here to enable the imx1 pinctrl driver
17
18config PINCTRL_IMX21
19 bool "i.MX21 pinctrl driver"
20 depends on SOC_IMX21
21 select PINCTRL_IMX1_CORE
22 help
23 Say Y here to enable the i.MX21 pinctrl driver
24
25config PINCTRL_IMX27
26 bool "IMX27 pinctrl driver"
27 depends on SOC_IMX27
28 select PINCTRL_IMX1_CORE
29 help
30 Say Y here to enable the imx27 pinctrl driver
31
32
33config PINCTRL_IMX25
34 bool "IMX25 pinctrl driver"
35 depends on OF
36 depends on SOC_IMX25
37 select PINCTRL_IMX
38 help
39 Say Y here to enable the imx25 pinctrl driver
40
41config PINCTRL_IMX35
42 bool "IMX35 pinctrl driver"
43 depends on SOC_IMX35
44 select PINCTRL_IMX
45 help
46 Say Y here to enable the imx35 pinctrl driver
47
48config PINCTRL_IMX50
49 bool "IMX50 pinctrl driver"
50 depends on SOC_IMX50
51 select PINCTRL_IMX
52 help
53 Say Y here to enable the imx50 pinctrl driver
54
55config PINCTRL_IMX51
56 bool "IMX51 pinctrl driver"
57 depends on SOC_IMX51
58 select PINCTRL_IMX
59 help
60 Say Y here to enable the imx51 pinctrl driver
61
62config PINCTRL_IMX53
63 bool "IMX53 pinctrl driver"
64 depends on SOC_IMX53
65 select PINCTRL_IMX
66 help
67 Say Y here to enable the imx53 pinctrl driver
68
69config PINCTRL_IMX6Q
70 bool "IMX6Q/DL pinctrl driver"
71 depends on SOC_IMX6Q
72 select PINCTRL_IMX
73 help
74 Say Y here to enable the imx6q/dl pinctrl driver
75
76config PINCTRL_IMX6SL
77 bool "IMX6SL pinctrl driver"
78 depends on SOC_IMX6SL
79 select PINCTRL_IMX
80 help
81 Say Y here to enable the imx6sl pinctrl driver
82
83config PINCTRL_IMX6SX
84 bool "IMX6SX pinctrl driver"
85 depends on SOC_IMX6SX
86 select PINCTRL_IMX
87 help
88 Say Y here to enable the imx6sx pinctrl driver
89
90config PINCTRL_VF610
91 bool "Freescale Vybrid VF610 pinctrl driver"
92 depends on SOC_VF610
93 select PINCTRL_IMX
94 help
95 Say Y here to enable the Freescale Vybrid VF610 pinctrl driver
96
97config PINCTRL_MXS
98 bool
99 select PINMUX
100 select PINCONF
101
102config PINCTRL_IMX23
103 bool
104 select PINCTRL_MXS
105
106config PINCTRL_IMX28
107 bool
108 select PINCTRL_MXS
diff --git a/drivers/pinctrl/freescale/Makefile b/drivers/pinctrl/freescale/Makefile
new file mode 100644
index 000000000000..bba73c22f043
--- /dev/null
+++ b/drivers/pinctrl/freescale/Makefile
@@ -0,0 +1,19 @@
1# Freescale pin control drivers
2obj-$(CONFIG_PINCTRL_IMX) += pinctrl-imx.o
3obj-$(CONFIG_PINCTRL_IMX1_CORE) += pinctrl-imx1-core.o
4obj-$(CONFIG_PINCTRL_IMX1) += pinctrl-imx1.o
5obj-$(CONFIG_PINCTRL_IMX21) += pinctrl-imx21.o
6obj-$(CONFIG_PINCTRL_IMX27) += pinctrl-imx27.o
7obj-$(CONFIG_PINCTRL_IMX35) += pinctrl-imx35.o
8obj-$(CONFIG_PINCTRL_IMX50) += pinctrl-imx50.o
9obj-$(CONFIG_PINCTRL_IMX51) += pinctrl-imx51.o
10obj-$(CONFIG_PINCTRL_IMX53) += pinctrl-imx53.o
11obj-$(CONFIG_PINCTRL_IMX6Q) += pinctrl-imx6q.o
12obj-$(CONFIG_PINCTRL_IMX6Q) += pinctrl-imx6dl.o
13obj-$(CONFIG_PINCTRL_IMX6SL) += pinctrl-imx6sl.o
14obj-$(CONFIG_PINCTRL_IMX6SX) += pinctrl-imx6sx.o
15obj-$(CONFIG_PINCTRL_VF610) += pinctrl-vf610.o
16obj-$(CONFIG_PINCTRL_MXS) += pinctrl-mxs.o
17obj-$(CONFIG_PINCTRL_IMX23) += pinctrl-imx23.o
18obj-$(CONFIG_PINCTRL_IMX25) += pinctrl-imx25.o
19obj-$(CONFIG_PINCTRL_IMX28) += pinctrl-imx28.o
diff --git a/drivers/pinctrl/pinctrl-imx.c b/drivers/pinctrl/freescale/pinctrl-imx.c
index a24448e5d399..f2446769247f 100644
--- a/drivers/pinctrl/pinctrl-imx.c
+++ b/drivers/pinctrl/freescale/pinctrl-imx.c
@@ -24,7 +24,7 @@
24#include <linux/pinctrl/pinmux.h> 24#include <linux/pinctrl/pinmux.h>
25#include <linux/slab.h> 25#include <linux/slab.h>
26 26
27#include "core.h" 27#include "../core.h"
28#include "pinctrl-imx.h" 28#include "pinctrl-imx.h"
29 29
30/* The bits in CONFIG cell defined in binding doc*/ 30/* The bits in CONFIG cell defined in binding doc*/
@@ -179,8 +179,8 @@ static const struct pinctrl_ops imx_pctrl_ops = {
179 179
180}; 180};
181 181
182static int imx_pmx_enable(struct pinctrl_dev *pctldev, unsigned selector, 182static int imx_pmx_set(struct pinctrl_dev *pctldev, unsigned selector,
183 unsigned group) 183 unsigned group)
184{ 184{
185 struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev); 185 struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
186 const struct imx_pinctrl_soc_info *info = ipctl->info; 186 const struct imx_pinctrl_soc_info *info = ipctl->info;
@@ -204,7 +204,7 @@ static int imx_pmx_enable(struct pinctrl_dev *pctldev, unsigned selector,
204 pin_id = pin->pin; 204 pin_id = pin->pin;
205 pin_reg = &info->pin_regs[pin_id]; 205 pin_reg = &info->pin_regs[pin_id];
206 206
207 if (!(info->flags & ZERO_OFFSET_VALID) && !pin_reg->mux_reg) { 207 if (pin_reg->mux_reg == -1) {
208 dev_err(ipctl->dev, "Pin(%s) does not support mux function\n", 208 dev_err(ipctl->dev, "Pin(%s) does not support mux function\n",
209 info->pins[pin_id].name); 209 info->pins[pin_id].name);
210 return -EINVAL; 210 return -EINVAL;
@@ -298,7 +298,7 @@ static const struct pinmux_ops imx_pmx_ops = {
298 .get_functions_count = imx_pmx_get_funcs_count, 298 .get_functions_count = imx_pmx_get_funcs_count,
299 .get_function_name = imx_pmx_get_func_name, 299 .get_function_name = imx_pmx_get_func_name,
300 .get_function_groups = imx_pmx_get_groups, 300 .get_function_groups = imx_pmx_get_groups,
301 .enable = imx_pmx_enable, 301 .set_mux = imx_pmx_set,
302}; 302};
303 303
304static int imx_pinconf_get(struct pinctrl_dev *pctldev, 304static int imx_pinconf_get(struct pinctrl_dev *pctldev,
@@ -308,7 +308,7 @@ static int imx_pinconf_get(struct pinctrl_dev *pctldev,
308 const struct imx_pinctrl_soc_info *info = ipctl->info; 308 const struct imx_pinctrl_soc_info *info = ipctl->info;
309 const struct imx_pin_reg *pin_reg = &info->pin_regs[pin_id]; 309 const struct imx_pin_reg *pin_reg = &info->pin_regs[pin_id];
310 310
311 if (!(info->flags & ZERO_OFFSET_VALID) && !pin_reg->conf_reg) { 311 if (pin_reg->conf_reg == -1) {
312 dev_err(info->dev, "Pin(%s) does not support config function\n", 312 dev_err(info->dev, "Pin(%s) does not support config function\n",
313 info->pins[pin_id].name); 313 info->pins[pin_id].name);
314 return -EINVAL; 314 return -EINVAL;
@@ -331,7 +331,7 @@ static int imx_pinconf_set(struct pinctrl_dev *pctldev,
331 const struct imx_pin_reg *pin_reg = &info->pin_regs[pin_id]; 331 const struct imx_pin_reg *pin_reg = &info->pin_regs[pin_id];
332 int i; 332 int i;
333 333
334 if (!(info->flags & ZERO_OFFSET_VALID) && !pin_reg->conf_reg) { 334 if (pin_reg->conf_reg == -1) {
335 dev_err(info->dev, "Pin(%s) does not support config function\n", 335 dev_err(info->dev, "Pin(%s) does not support config function\n",
336 info->pins[pin_id].name); 336 info->pins[pin_id].name);
337 return -EINVAL; 337 return -EINVAL;
@@ -515,7 +515,7 @@ static int imx_pinctrl_parse_functions(struct device_node *np,
515 /* Initialise function */ 515 /* Initialise function */
516 func->name = np->name; 516 func->name = np->name;
517 func->num_groups = of_get_child_count(np); 517 func->num_groups = of_get_child_count(np);
518 if (func->num_groups <= 0) { 518 if (func->num_groups == 0) {
519 dev_err(info->dev, "no groups defined in %s\n", np->full_name); 519 dev_err(info->dev, "no groups defined in %s\n", np->full_name);
520 return -EINVAL; 520 return -EINVAL;
521 } 521 }
@@ -586,10 +586,11 @@ int imx_pinctrl_probe(struct platform_device *pdev,
586 if (!ipctl) 586 if (!ipctl)
587 return -ENOMEM; 587 return -ENOMEM;
588 588
589 info->pin_regs = devm_kzalloc(&pdev->dev, sizeof(*info->pin_regs) * 589 info->pin_regs = devm_kmalloc(&pdev->dev, sizeof(*info->pin_regs) *
590 info->npins, GFP_KERNEL); 590 info->npins, GFP_KERNEL);
591 if (!info->pin_regs) 591 if (!info->pin_regs)
592 return -ENOMEM; 592 return -ENOMEM;
593 memset(info->pin_regs, 0xff, sizeof(*info->pin_regs) * info->npins);
593 594
594 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 595 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
595 ipctl->base = devm_ioremap_resource(&pdev->dev, res); 596 ipctl->base = devm_ioremap_resource(&pdev->dev, res);
diff --git a/drivers/pinctrl/pinctrl-imx.h b/drivers/pinctrl/freescale/pinctrl-imx.h
index db408b057000..49e55d39f7c8 100644
--- a/drivers/pinctrl/pinctrl-imx.h
+++ b/drivers/pinctrl/freescale/pinctrl-imx.h
@@ -67,8 +67,8 @@ struct imx_pmx_func {
67 * @conf_reg: config register offset 67 * @conf_reg: config register offset
68 */ 68 */
69struct imx_pin_reg { 69struct imx_pin_reg {
70 u16 mux_reg; 70 s16 mux_reg;
71 u16 conf_reg; 71 s16 conf_reg;
72}; 72};
73 73
74struct imx_pinctrl_soc_info { 74struct imx_pinctrl_soc_info {
@@ -83,8 +83,7 @@ struct imx_pinctrl_soc_info {
83 unsigned int flags; 83 unsigned int flags;
84}; 84};
85 85
86#define ZERO_OFFSET_VALID 0x1 86#define SHARE_MUX_CONF_REG 0x1
87#define SHARE_MUX_CONF_REG 0x2
88 87
89#define NO_MUX 0x0 88#define NO_MUX 0x0
90#define NO_PAD 0x0 89#define NO_PAD 0x0
diff --git a/drivers/pinctrl/pinctrl-imx1-core.c b/drivers/pinctrl/freescale/pinctrl-imx1-core.c
index 815384b377b5..5ac59fbb2440 100644
--- a/drivers/pinctrl/pinctrl-imx1-core.c
+++ b/drivers/pinctrl/freescale/pinctrl-imx1-core.c
@@ -28,7 +28,7 @@
28#include <linux/pinctrl/pinmux.h> 28#include <linux/pinctrl/pinmux.h>
29#include <linux/slab.h> 29#include <linux/slab.h>
30 30
31#include "core.h" 31#include "../core.h"
32#include "pinctrl-imx1.h" 32#include "pinctrl-imx1.h"
33 33
34struct imx1_pinctrl { 34struct imx1_pinctrl {
@@ -298,8 +298,8 @@ static const struct pinctrl_ops imx1_pctrl_ops = {
298 298
299}; 299};
300 300
301static int imx1_pmx_enable(struct pinctrl_dev *pctldev, unsigned selector, 301static int imx1_pmx_set(struct pinctrl_dev *pctldev, unsigned selector,
302 unsigned group) 302 unsigned group)
303{ 303{
304 struct imx1_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev); 304 struct imx1_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
305 const struct imx1_pinctrl_soc_info *info = ipctl->info; 305 const struct imx1_pinctrl_soc_info *info = ipctl->info;
@@ -385,7 +385,7 @@ static const struct pinmux_ops imx1_pmx_ops = {
385 .get_functions_count = imx1_pmx_get_funcs_count, 385 .get_functions_count = imx1_pmx_get_funcs_count,
386 .get_function_name = imx1_pmx_get_func_name, 386 .get_function_name = imx1_pmx_get_func_name,
387 .get_function_groups = imx1_pmx_get_groups, 387 .get_function_groups = imx1_pmx_get_groups,
388 .enable = imx1_pmx_enable, 388 .set_mux = imx1_pmx_set,
389}; 389};
390 390
391static int imx1_pinconf_get(struct pinctrl_dev *pctldev, 391static int imx1_pinconf_get(struct pinctrl_dev *pctldev,
@@ -526,7 +526,7 @@ static int imx1_pinctrl_parse_functions(struct device_node *np,
526 /* Initialise function */ 526 /* Initialise function */
527 func->name = np->name; 527 func->name = np->name;
528 func->num_groups = of_get_child_count(np); 528 func->num_groups = of_get_child_count(np);
529 if (func->num_groups <= 0) 529 if (func->num_groups == 0)
530 return -EINVAL; 530 return -EINVAL;
531 531
532 func->groups = devm_kzalloc(info->dev, 532 func->groups = devm_kzalloc(info->dev,
diff --git a/drivers/pinctrl/freescale/pinctrl-imx1.c b/drivers/pinctrl/freescale/pinctrl-imx1.c
new file mode 100644
index 000000000000..533a6e519648
--- /dev/null
+++ b/drivers/pinctrl/freescale/pinctrl-imx1.c
@@ -0,0 +1,279 @@
1/*
2 * i.MX1 pinctrl driver based on imx pinmux core
3 *
4 * Copyright (C) 2014 Alexander Shiyan <shc_work@mail.ru>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 */
11
12#include <linux/module.h>
13#include <linux/of.h>
14#include <linux/platform_device.h>
15#include <linux/pinctrl/pinctrl.h>
16
17#include "pinctrl-imx1.h"
18
19#define PAD_ID(port, pin) ((port) * 32 + (pin))
20#define PA 0
21#define PB 1
22#define PC 2
23#define PD 3
24
25enum imx1_pads {
26 MX1_PAD_A24 = PAD_ID(PA, 0),
27 MX1_PAD_TIN = PAD_ID(PA, 1),
28 MX1_PAD_PWMO = PAD_ID(PA, 2),
29 MX1_PAD_CSI_MCLK = PAD_ID(PA, 3),
30 MX1_PAD_CSI_D0 = PAD_ID(PA, 4),
31 MX1_PAD_CSI_D1 = PAD_ID(PA, 5),
32 MX1_PAD_CSI_D2 = PAD_ID(PA, 6),
33 MX1_PAD_CSI_D3 = PAD_ID(PA, 7),
34 MX1_PAD_CSI_D4 = PAD_ID(PA, 8),
35 MX1_PAD_CSI_D5 = PAD_ID(PA, 9),
36 MX1_PAD_CSI_D6 = PAD_ID(PA, 10),
37 MX1_PAD_CSI_D7 = PAD_ID(PA, 11),
38 MX1_PAD_CSI_VSYNC = PAD_ID(PA, 12),
39 MX1_PAD_CSI_HSYNC = PAD_ID(PA, 13),
40 MX1_PAD_CSI_PIXCLK = PAD_ID(PA, 14),
41 MX1_PAD_I2C_SDA = PAD_ID(PA, 15),
42 MX1_PAD_I2C_SCL = PAD_ID(PA, 16),
43 MX1_PAD_DTACK = PAD_ID(PA, 17),
44 MX1_PAD_BCLK = PAD_ID(PA, 18),
45 MX1_PAD_LBA = PAD_ID(PA, 19),
46 MX1_PAD_ECB = PAD_ID(PA, 20),
47 MX1_PAD_A0 = PAD_ID(PA, 21),
48 MX1_PAD_CS4 = PAD_ID(PA, 22),
49 MX1_PAD_CS5 = PAD_ID(PA, 23),
50 MX1_PAD_A16 = PAD_ID(PA, 24),
51 MX1_PAD_A17 = PAD_ID(PA, 25),
52 MX1_PAD_A18 = PAD_ID(PA, 26),
53 MX1_PAD_A19 = PAD_ID(PA, 27),
54 MX1_PAD_A20 = PAD_ID(PA, 28),
55 MX1_PAD_A21 = PAD_ID(PA, 29),
56 MX1_PAD_A22 = PAD_ID(PA, 30),
57 MX1_PAD_A23 = PAD_ID(PA, 31),
58 MX1_PAD_SD_DAT0 = PAD_ID(PB, 8),
59 MX1_PAD_SD_DAT1 = PAD_ID(PB, 9),
60 MX1_PAD_SD_DAT2 = PAD_ID(PB, 10),
61 MX1_PAD_SD_DAT3 = PAD_ID(PB, 11),
62 MX1_PAD_SD_SCLK = PAD_ID(PB, 12),
63 MX1_PAD_SD_CMD = PAD_ID(PB, 13),
64 MX1_PAD_SIM_SVEN = PAD_ID(PB, 14),
65 MX1_PAD_SIM_PD = PAD_ID(PB, 15),
66 MX1_PAD_SIM_TX = PAD_ID(PB, 16),
67 MX1_PAD_SIM_RX = PAD_ID(PB, 17),
68 MX1_PAD_SIM_RST = PAD_ID(PB, 18),
69 MX1_PAD_SIM_CLK = PAD_ID(PB, 19),
70 MX1_PAD_USBD_AFE = PAD_ID(PB, 20),
71 MX1_PAD_USBD_OE = PAD_ID(PB, 21),
72 MX1_PAD_USBD_RCV = PAD_ID(PB, 22),
73 MX1_PAD_USBD_SUSPND = PAD_ID(PB, 23),
74 MX1_PAD_USBD_VP = PAD_ID(PB, 24),
75 MX1_PAD_USBD_VM = PAD_ID(PB, 25),
76 MX1_PAD_USBD_VPO = PAD_ID(PB, 26),
77 MX1_PAD_USBD_VMO = PAD_ID(PB, 27),
78 MX1_PAD_UART2_CTS = PAD_ID(PB, 28),
79 MX1_PAD_UART2_RTS = PAD_ID(PB, 29),
80 MX1_PAD_UART2_TXD = PAD_ID(PB, 30),
81 MX1_PAD_UART2_RXD = PAD_ID(PB, 31),
82 MX1_PAD_SSI_RXFS = PAD_ID(PC, 3),
83 MX1_PAD_SSI_RXCLK = PAD_ID(PC, 4),
84 MX1_PAD_SSI_RXDAT = PAD_ID(PC, 5),
85 MX1_PAD_SSI_TXDAT = PAD_ID(PC, 6),
86 MX1_PAD_SSI_TXFS = PAD_ID(PC, 7),
87 MX1_PAD_SSI_TXCLK = PAD_ID(PC, 8),
88 MX1_PAD_UART1_CTS = PAD_ID(PC, 9),
89 MX1_PAD_UART1_RTS = PAD_ID(PC, 10),
90 MX1_PAD_UART1_TXD = PAD_ID(PC, 11),
91 MX1_PAD_UART1_RXD = PAD_ID(PC, 12),
92 MX1_PAD_SPI1_RDY = PAD_ID(PC, 13),
93 MX1_PAD_SPI1_SCLK = PAD_ID(PC, 14),
94 MX1_PAD_SPI1_SS = PAD_ID(PC, 15),
95 MX1_PAD_SPI1_MISO = PAD_ID(PC, 16),
96 MX1_PAD_SPI1_MOSI = PAD_ID(PC, 17),
97 MX1_PAD_BT13 = PAD_ID(PC, 19),
98 MX1_PAD_BT12 = PAD_ID(PC, 20),
99 MX1_PAD_BT11 = PAD_ID(PC, 21),
100 MX1_PAD_BT10 = PAD_ID(PC, 22),
101 MX1_PAD_BT9 = PAD_ID(PC, 23),
102 MX1_PAD_BT8 = PAD_ID(PC, 24),
103 MX1_PAD_BT7 = PAD_ID(PC, 25),
104 MX1_PAD_BT6 = PAD_ID(PC, 26),
105 MX1_PAD_BT5 = PAD_ID(PC, 27),
106 MX1_PAD_BT4 = PAD_ID(PC, 28),
107 MX1_PAD_BT3 = PAD_ID(PC, 29),
108 MX1_PAD_BT2 = PAD_ID(PC, 30),
109 MX1_PAD_BT1 = PAD_ID(PC, 31),
110 MX1_PAD_LSCLK = PAD_ID(PD, 6),
111 MX1_PAD_REV = PAD_ID(PD, 7),
112 MX1_PAD_CLS = PAD_ID(PD, 8),
113 MX1_PAD_PS = PAD_ID(PD, 9),
114 MX1_PAD_SPL_SPR = PAD_ID(PD, 10),
115 MX1_PAD_CONTRAST = PAD_ID(PD, 11),
116 MX1_PAD_ACD_OE = PAD_ID(PD, 12),
117 MX1_PAD_LP_HSYNC = PAD_ID(PD, 13),
118 MX1_PAD_FLM_VSYNC = PAD_ID(PD, 14),
119 MX1_PAD_LD0 = PAD_ID(PD, 15),
120 MX1_PAD_LD1 = PAD_ID(PD, 16),
121 MX1_PAD_LD2 = PAD_ID(PD, 17),
122 MX1_PAD_LD3 = PAD_ID(PD, 18),
123 MX1_PAD_LD4 = PAD_ID(PD, 19),
124 MX1_PAD_LD5 = PAD_ID(PD, 20),
125 MX1_PAD_LD6 = PAD_ID(PD, 21),
126 MX1_PAD_LD7 = PAD_ID(PD, 22),
127 MX1_PAD_LD8 = PAD_ID(PD, 23),
128 MX1_PAD_LD9 = PAD_ID(PD, 24),
129 MX1_PAD_LD10 = PAD_ID(PD, 25),
130 MX1_PAD_LD11 = PAD_ID(PD, 26),
131 MX1_PAD_LD12 = PAD_ID(PD, 27),
132 MX1_PAD_LD13 = PAD_ID(PD, 28),
133 MX1_PAD_LD14 = PAD_ID(PD, 29),
134 MX1_PAD_LD15 = PAD_ID(PD, 30),
135 MX1_PAD_TMR2OUT = PAD_ID(PD, 31),
136};
137
138/* Pad names for the pinmux subsystem */
139static const struct pinctrl_pin_desc imx1_pinctrl_pads[] = {
140 IMX_PINCTRL_PIN(MX1_PAD_A24),
141 IMX_PINCTRL_PIN(MX1_PAD_TIN),
142 IMX_PINCTRL_PIN(MX1_PAD_PWMO),
143 IMX_PINCTRL_PIN(MX1_PAD_CSI_MCLK),
144 IMX_PINCTRL_PIN(MX1_PAD_CSI_D0),
145 IMX_PINCTRL_PIN(MX1_PAD_CSI_D1),
146 IMX_PINCTRL_PIN(MX1_PAD_CSI_D2),
147 IMX_PINCTRL_PIN(MX1_PAD_CSI_D3),
148 IMX_PINCTRL_PIN(MX1_PAD_CSI_D4),
149 IMX_PINCTRL_PIN(MX1_PAD_CSI_D5),
150 IMX_PINCTRL_PIN(MX1_PAD_CSI_D6),
151 IMX_PINCTRL_PIN(MX1_PAD_CSI_D7),
152 IMX_PINCTRL_PIN(MX1_PAD_CSI_VSYNC),
153 IMX_PINCTRL_PIN(MX1_PAD_CSI_HSYNC),
154 IMX_PINCTRL_PIN(MX1_PAD_CSI_PIXCLK),
155 IMX_PINCTRL_PIN(MX1_PAD_I2C_SDA),
156 IMX_PINCTRL_PIN(MX1_PAD_I2C_SCL),
157 IMX_PINCTRL_PIN(MX1_PAD_DTACK),
158 IMX_PINCTRL_PIN(MX1_PAD_BCLK),
159 IMX_PINCTRL_PIN(MX1_PAD_LBA),
160 IMX_PINCTRL_PIN(MX1_PAD_ECB),
161 IMX_PINCTRL_PIN(MX1_PAD_A0),
162 IMX_PINCTRL_PIN(MX1_PAD_CS4),
163 IMX_PINCTRL_PIN(MX1_PAD_CS5),
164 IMX_PINCTRL_PIN(MX1_PAD_A16),
165 IMX_PINCTRL_PIN(MX1_PAD_A17),
166 IMX_PINCTRL_PIN(MX1_PAD_A18),
167 IMX_PINCTRL_PIN(MX1_PAD_A19),
168 IMX_PINCTRL_PIN(MX1_PAD_A20),
169 IMX_PINCTRL_PIN(MX1_PAD_A21),
170 IMX_PINCTRL_PIN(MX1_PAD_A22),
171 IMX_PINCTRL_PIN(MX1_PAD_A23),
172 IMX_PINCTRL_PIN(MX1_PAD_SD_DAT0),
173 IMX_PINCTRL_PIN(MX1_PAD_SD_DAT1),
174 IMX_PINCTRL_PIN(MX1_PAD_SD_DAT2),
175 IMX_PINCTRL_PIN(MX1_PAD_SD_DAT3),
176 IMX_PINCTRL_PIN(MX1_PAD_SD_SCLK),
177 IMX_PINCTRL_PIN(MX1_PAD_SD_CMD),
178 IMX_PINCTRL_PIN(MX1_PAD_SIM_SVEN),
179 IMX_PINCTRL_PIN(MX1_PAD_SIM_PD),
180 IMX_PINCTRL_PIN(MX1_PAD_SIM_TX),
181 IMX_PINCTRL_PIN(MX1_PAD_SIM_RX),
182 IMX_PINCTRL_PIN(MX1_PAD_SIM_CLK),
183 IMX_PINCTRL_PIN(MX1_PAD_USBD_AFE),
184 IMX_PINCTRL_PIN(MX1_PAD_USBD_OE),
185 IMX_PINCTRL_PIN(MX1_PAD_USBD_RCV),
186 IMX_PINCTRL_PIN(MX1_PAD_USBD_SUSPND),
187 IMX_PINCTRL_PIN(MX1_PAD_USBD_VP),
188 IMX_PINCTRL_PIN(MX1_PAD_USBD_VM),
189 IMX_PINCTRL_PIN(MX1_PAD_USBD_VPO),
190 IMX_PINCTRL_PIN(MX1_PAD_USBD_VMO),
191 IMX_PINCTRL_PIN(MX1_PAD_UART2_CTS),
192 IMX_PINCTRL_PIN(MX1_PAD_UART2_RTS),
193 IMX_PINCTRL_PIN(MX1_PAD_UART2_TXD),
194 IMX_PINCTRL_PIN(MX1_PAD_UART2_RXD),
195 IMX_PINCTRL_PIN(MX1_PAD_SSI_RXFS),
196 IMX_PINCTRL_PIN(MX1_PAD_SSI_RXCLK),
197 IMX_PINCTRL_PIN(MX1_PAD_SSI_RXDAT),
198 IMX_PINCTRL_PIN(MX1_PAD_SSI_TXDAT),
199 IMX_PINCTRL_PIN(MX1_PAD_SSI_TXFS),
200 IMX_PINCTRL_PIN(MX1_PAD_SSI_TXCLK),
201 IMX_PINCTRL_PIN(MX1_PAD_UART1_CTS),
202 IMX_PINCTRL_PIN(MX1_PAD_UART1_RTS),
203 IMX_PINCTRL_PIN(MX1_PAD_UART1_TXD),
204 IMX_PINCTRL_PIN(MX1_PAD_UART1_RXD),
205 IMX_PINCTRL_PIN(MX1_PAD_SPI1_RDY),
206 IMX_PINCTRL_PIN(MX1_PAD_SPI1_SCLK),
207 IMX_PINCTRL_PIN(MX1_PAD_SPI1_SS),
208 IMX_PINCTRL_PIN(MX1_PAD_SPI1_MISO),
209 IMX_PINCTRL_PIN(MX1_PAD_SPI1_MOSI),
210 IMX_PINCTRL_PIN(MX1_PAD_BT13),
211 IMX_PINCTRL_PIN(MX1_PAD_BT12),
212 IMX_PINCTRL_PIN(MX1_PAD_BT11),
213 IMX_PINCTRL_PIN(MX1_PAD_BT10),
214 IMX_PINCTRL_PIN(MX1_PAD_BT9),
215 IMX_PINCTRL_PIN(MX1_PAD_BT8),
216 IMX_PINCTRL_PIN(MX1_PAD_BT7),
217 IMX_PINCTRL_PIN(MX1_PAD_BT6),
218 IMX_PINCTRL_PIN(MX1_PAD_BT5),
219 IMX_PINCTRL_PIN(MX1_PAD_BT4),
220 IMX_PINCTRL_PIN(MX1_PAD_BT3),
221 IMX_PINCTRL_PIN(MX1_PAD_BT2),
222 IMX_PINCTRL_PIN(MX1_PAD_BT1),
223 IMX_PINCTRL_PIN(MX1_PAD_LSCLK),
224 IMX_PINCTRL_PIN(MX1_PAD_REV),
225 IMX_PINCTRL_PIN(MX1_PAD_CLS),
226 IMX_PINCTRL_PIN(MX1_PAD_PS),
227 IMX_PINCTRL_PIN(MX1_PAD_SPL_SPR),
228 IMX_PINCTRL_PIN(MX1_PAD_CONTRAST),
229 IMX_PINCTRL_PIN(MX1_PAD_ACD_OE),
230 IMX_PINCTRL_PIN(MX1_PAD_LP_HSYNC),
231 IMX_PINCTRL_PIN(MX1_PAD_FLM_VSYNC),
232 IMX_PINCTRL_PIN(MX1_PAD_LD0),
233 IMX_PINCTRL_PIN(MX1_PAD_LD1),
234 IMX_PINCTRL_PIN(MX1_PAD_LD2),
235 IMX_PINCTRL_PIN(MX1_PAD_LD3),
236 IMX_PINCTRL_PIN(MX1_PAD_LD4),
237 IMX_PINCTRL_PIN(MX1_PAD_LD5),
238 IMX_PINCTRL_PIN(MX1_PAD_LD6),
239 IMX_PINCTRL_PIN(MX1_PAD_LD7),
240 IMX_PINCTRL_PIN(MX1_PAD_LD8),
241 IMX_PINCTRL_PIN(MX1_PAD_LD9),
242 IMX_PINCTRL_PIN(MX1_PAD_LD10),
243 IMX_PINCTRL_PIN(MX1_PAD_LD11),
244 IMX_PINCTRL_PIN(MX1_PAD_LD12),
245 IMX_PINCTRL_PIN(MX1_PAD_LD13),
246 IMX_PINCTRL_PIN(MX1_PAD_LD14),
247 IMX_PINCTRL_PIN(MX1_PAD_LD15),
248 IMX_PINCTRL_PIN(MX1_PAD_TMR2OUT),
249};
250
251static struct imx1_pinctrl_soc_info imx1_pinctrl_info = {
252 .pins = imx1_pinctrl_pads,
253 .npins = ARRAY_SIZE(imx1_pinctrl_pads),
254};
255
256static int __init imx1_pinctrl_probe(struct platform_device *pdev)
257{
258 return imx1_pinctrl_core_probe(pdev, &imx1_pinctrl_info);
259}
260
261static const struct of_device_id imx1_pinctrl_of_match[] = {
262 { .compatible = "fsl,imx1-iomuxc", },
263 { }
264};
265MODULE_DEVICE_TABLE(of, imx1_pinctrl_of_match);
266
267static struct platform_driver imx1_pinctrl_driver = {
268 .driver = {
269 .name = "imx1-pinctrl",
270 .owner = THIS_MODULE,
271 .of_match_table = imx1_pinctrl_of_match,
272 },
273 .remove = imx1_pinctrl_core_remove,
274};
275module_platform_driver_probe(imx1_pinctrl_driver, imx1_pinctrl_probe);
276
277MODULE_AUTHOR("Alexander Shiyan <shc_work@mail.ru>");
278MODULE_DESCRIPTION("Freescale i.MX1 pinctrl driver");
279MODULE_LICENSE("GPL");
diff --git a/drivers/pinctrl/pinctrl-imx1.h b/drivers/pinctrl/freescale/pinctrl-imx1.h
index 692a54c15cda..692a54c15cda 100644
--- a/drivers/pinctrl/pinctrl-imx1.h
+++ b/drivers/pinctrl/freescale/pinctrl-imx1.h
diff --git a/drivers/pinctrl/freescale/pinctrl-imx21.c b/drivers/pinctrl/freescale/pinctrl-imx21.c
new file mode 100644
index 000000000000..1b3b2311b033
--- /dev/null
+++ b/drivers/pinctrl/freescale/pinctrl-imx21.c
@@ -0,0 +1,342 @@
1/*
2 * i.MX21 pinctrl driver based on imx pinmux core
3 *
4 * Copyright (C) 2014 Alexander Shiyan <shc_work@mail.ru>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 */
11
12#include <linux/module.h>
13#include <linux/of.h>
14#include <linux/platform_device.h>
15#include <linux/pinctrl/pinctrl.h>
16
17#include "pinctrl-imx1.h"
18
19#define PAD_ID(port, pin) ((port) * 32 + (pin))
20#define PA 0
21#define PB 1
22#define PC 2
23#define PD 3
24#define PE 4
25#define PF 5
26
27enum imx21_pads {
28 MX21_PAD_LSCLK = PAD_ID(PA, 5),
29 MX21_PAD_LD0 = PAD_ID(PA, 6),
30 MX21_PAD_LD1 = PAD_ID(PA, 7),
31 MX21_PAD_LD2 = PAD_ID(PA, 8),
32 MX21_PAD_LD3 = PAD_ID(PA, 9),
33 MX21_PAD_LD4 = PAD_ID(PA, 10),
34 MX21_PAD_LD5 = PAD_ID(PA, 11),
35 MX21_PAD_LD6 = PAD_ID(PA, 12),
36 MX21_PAD_LD7 = PAD_ID(PA, 13),
37 MX21_PAD_LD8 = PAD_ID(PA, 14),
38 MX21_PAD_LD9 = PAD_ID(PA, 15),
39 MX21_PAD_LD10 = PAD_ID(PA, 16),
40 MX21_PAD_LD11 = PAD_ID(PA, 17),
41 MX21_PAD_LD12 = PAD_ID(PA, 18),
42 MX21_PAD_LD13 = PAD_ID(PA, 19),
43 MX21_PAD_LD14 = PAD_ID(PA, 20),
44 MX21_PAD_LD15 = PAD_ID(PA, 21),
45 MX21_PAD_LD16 = PAD_ID(PA, 22),
46 MX21_PAD_LD17 = PAD_ID(PA, 23),
47 MX21_PAD_REV = PAD_ID(PA, 24),
48 MX21_PAD_CLS = PAD_ID(PA, 25),
49 MX21_PAD_PS = PAD_ID(PA, 26),
50 MX21_PAD_SPL_SPR = PAD_ID(PA, 27),
51 MX21_PAD_HSYNC = PAD_ID(PA, 28),
52 MX21_PAD_VSYNC = PAD_ID(PA, 29),
53 MX21_PAD_CONTRAST = PAD_ID(PA, 30),
54 MX21_PAD_OE_ACD = PAD_ID(PA, 31),
55 MX21_PAD_SD2_D0 = PAD_ID(PB, 4),
56 MX21_PAD_SD2_D1 = PAD_ID(PB, 5),
57 MX21_PAD_SD2_D2 = PAD_ID(PB, 6),
58 MX21_PAD_SD2_D3 = PAD_ID(PB, 7),
59 MX21_PAD_SD2_CMD = PAD_ID(PB, 8),
60 MX21_PAD_SD2_CLK = PAD_ID(PB, 9),
61 MX21_PAD_CSI_D0 = PAD_ID(PB, 10),
62 MX21_PAD_CSI_D1 = PAD_ID(PB, 11),
63 MX21_PAD_CSI_D2 = PAD_ID(PB, 12),
64 MX21_PAD_CSI_D3 = PAD_ID(PB, 13),
65 MX21_PAD_CSI_D4 = PAD_ID(PB, 14),
66 MX21_PAD_CSI_MCLK = PAD_ID(PB, 15),
67 MX21_PAD_CSI_PIXCLK = PAD_ID(PB, 16),
68 MX21_PAD_CSI_D5 = PAD_ID(PB, 17),
69 MX21_PAD_CSI_D6 = PAD_ID(PB, 18),
70 MX21_PAD_CSI_D7 = PAD_ID(PB, 19),
71 MX21_PAD_CSI_VSYNC = PAD_ID(PB, 20),
72 MX21_PAD_CSI_HSYNC = PAD_ID(PB, 21),
73 MX21_PAD_USB_BYP = PAD_ID(PB, 22),
74 MX21_PAD_USB_PWR = PAD_ID(PB, 23),
75 MX21_PAD_USB_OC = PAD_ID(PB, 24),
76 MX21_PAD_USBH_ON = PAD_ID(PB, 25),
77 MX21_PAD_USBH1_FS = PAD_ID(PB, 26),
78 MX21_PAD_USBH1_OE = PAD_ID(PB, 27),
79 MX21_PAD_USBH1_TXDM = PAD_ID(PB, 28),
80 MX21_PAD_USBH1_TXDP = PAD_ID(PB, 29),
81 MX21_PAD_USBH1_RXDM = PAD_ID(PB, 30),
82 MX21_PAD_USBH1_RXDP = PAD_ID(PB, 31),
83 MX21_PAD_USBG_SDA = PAD_ID(PC, 5),
84 MX21_PAD_USBG_SCL = PAD_ID(PC, 6),
85 MX21_PAD_USBG_ON = PAD_ID(PC, 7),
86 MX21_PAD_USBG_FS = PAD_ID(PC, 8),
87 MX21_PAD_USBG_OE = PAD_ID(PC, 9),
88 MX21_PAD_USBG_TXDM = PAD_ID(PC, 10),
89 MX21_PAD_USBG_TXDP = PAD_ID(PC, 11),
90 MX21_PAD_USBG_RXDM = PAD_ID(PC, 12),
91 MX21_PAD_USBG_RXDP = PAD_ID(PC, 13),
92 MX21_PAD_TOUT = PAD_ID(PC, 14),
93 MX21_PAD_TIN = PAD_ID(PC, 15),
94 MX21_PAD_SAP_FS = PAD_ID(PC, 16),
95 MX21_PAD_SAP_RXD = PAD_ID(PC, 17),
96 MX21_PAD_SAP_TXD = PAD_ID(PC, 18),
97 MX21_PAD_SAP_CLK = PAD_ID(PC, 19),
98 MX21_PAD_SSI1_FS = PAD_ID(PC, 20),
99 MX21_PAD_SSI1_RXD = PAD_ID(PC, 21),
100 MX21_PAD_SSI1_TXD = PAD_ID(PC, 22),
101 MX21_PAD_SSI1_CLK = PAD_ID(PC, 23),
102 MX21_PAD_SSI2_FS = PAD_ID(PC, 24),
103 MX21_PAD_SSI2_RXD = PAD_ID(PC, 25),
104 MX21_PAD_SSI2_TXD = PAD_ID(PC, 26),
105 MX21_PAD_SSI2_CLK = PAD_ID(PC, 27),
106 MX21_PAD_SSI3_FS = PAD_ID(PC, 28),
107 MX21_PAD_SSI3_RXD = PAD_ID(PC, 29),
108 MX21_PAD_SSI3_TXD = PAD_ID(PC, 30),
109 MX21_PAD_SSI3_CLK = PAD_ID(PC, 31),
110 MX21_PAD_I2C_DATA = PAD_ID(PD, 17),
111 MX21_PAD_I2C_CLK = PAD_ID(PD, 18),
112 MX21_PAD_CSPI2_SS2 = PAD_ID(PD, 19),
113 MX21_PAD_CSPI2_SS1 = PAD_ID(PD, 20),
114 MX21_PAD_CSPI2_SS0 = PAD_ID(PD, 21),
115 MX21_PAD_CSPI2_SCLK = PAD_ID(PD, 22),
116 MX21_PAD_CSPI2_MISO = PAD_ID(PD, 23),
117 MX21_PAD_CSPI2_MOSI = PAD_ID(PD, 24),
118 MX21_PAD_CSPI1_RDY = PAD_ID(PD, 25),
119 MX21_PAD_CSPI1_SS2 = PAD_ID(PD, 26),
120 MX21_PAD_CSPI1_SS1 = PAD_ID(PD, 27),
121 MX21_PAD_CSPI1_SS0 = PAD_ID(PD, 28),
122 MX21_PAD_CSPI1_SCLK = PAD_ID(PD, 29),
123 MX21_PAD_CSPI1_MISO = PAD_ID(PD, 30),
124 MX21_PAD_CSPI1_MOSI = PAD_ID(PD, 31),
125 MX21_PAD_TEST_WB2 = PAD_ID(PE, 0),
126 MX21_PAD_TEST_WB1 = PAD_ID(PE, 1),
127 MX21_PAD_TEST_WB0 = PAD_ID(PE, 2),
128 MX21_PAD_UART2_CTS = PAD_ID(PE, 3),
129 MX21_PAD_UART2_RTS = PAD_ID(PE, 4),
130 MX21_PAD_PWMO = PAD_ID(PE, 5),
131 MX21_PAD_UART2_TXD = PAD_ID(PE, 6),
132 MX21_PAD_UART2_RXD = PAD_ID(PE, 7),
133 MX21_PAD_UART3_TXD = PAD_ID(PE, 8),
134 MX21_PAD_UART3_RXD = PAD_ID(PE, 9),
135 MX21_PAD_UART3_CTS = PAD_ID(PE, 10),
136 MX21_PAD_UART3_RTS = PAD_ID(PE, 11),
137 MX21_PAD_UART1_TXD = PAD_ID(PE, 12),
138 MX21_PAD_UART1_RXD = PAD_ID(PE, 13),
139 MX21_PAD_UART1_CTS = PAD_ID(PE, 14),
140 MX21_PAD_UART1_RTS = PAD_ID(PE, 15),
141 MX21_PAD_RTCK = PAD_ID(PE, 16),
142 MX21_PAD_RESET_OUT = PAD_ID(PE, 17),
143 MX21_PAD_SD1_D0 = PAD_ID(PE, 18),
144 MX21_PAD_SD1_D1 = PAD_ID(PE, 19),
145 MX21_PAD_SD1_D2 = PAD_ID(PE, 20),
146 MX21_PAD_SD1_D3 = PAD_ID(PE, 21),
147 MX21_PAD_SD1_CMD = PAD_ID(PE, 22),
148 MX21_PAD_SD1_CLK = PAD_ID(PE, 23),
149 MX21_PAD_NFRB = PAD_ID(PF, 0),
150 MX21_PAD_NFCE = PAD_ID(PF, 1),
151 MX21_PAD_NFWP = PAD_ID(PF, 2),
152 MX21_PAD_NFCLE = PAD_ID(PF, 3),
153 MX21_PAD_NFALE = PAD_ID(PF, 4),
154 MX21_PAD_NFRE = PAD_ID(PF, 5),
155 MX21_PAD_NFWE = PAD_ID(PF, 6),
156 MX21_PAD_NFIO0 = PAD_ID(PF, 7),
157 MX21_PAD_NFIO1 = PAD_ID(PF, 8),
158 MX21_PAD_NFIO2 = PAD_ID(PF, 9),
159 MX21_PAD_NFIO3 = PAD_ID(PF, 10),
160 MX21_PAD_NFIO4 = PAD_ID(PF, 11),
161 MX21_PAD_NFIO5 = PAD_ID(PF, 12),
162 MX21_PAD_NFIO6 = PAD_ID(PF, 13),
163 MX21_PAD_NFIO7 = PAD_ID(PF, 14),
164 MX21_PAD_CLKO = PAD_ID(PF, 15),
165 MX21_PAD_RESERVED = PAD_ID(PF, 16),
166 MX21_PAD_CS4 = PAD_ID(PF, 21),
167 MX21_PAD_CS5 = PAD_ID(PF, 22),
168};
169
170/* Pad names for the pinmux subsystem */
171static const struct pinctrl_pin_desc imx21_pinctrl_pads[] = {
172 IMX_PINCTRL_PIN(MX21_PAD_LSCLK),
173 IMX_PINCTRL_PIN(MX21_PAD_LD0),
174 IMX_PINCTRL_PIN(MX21_PAD_LD1),
175 IMX_PINCTRL_PIN(MX21_PAD_LD2),
176 IMX_PINCTRL_PIN(MX21_PAD_LD3),
177 IMX_PINCTRL_PIN(MX21_PAD_LD4),
178 IMX_PINCTRL_PIN(MX21_PAD_LD5),
179 IMX_PINCTRL_PIN(MX21_PAD_LD6),
180 IMX_PINCTRL_PIN(MX21_PAD_LD7),
181 IMX_PINCTRL_PIN(MX21_PAD_LD8),
182 IMX_PINCTRL_PIN(MX21_PAD_LD9),
183 IMX_PINCTRL_PIN(MX21_PAD_LD10),
184 IMX_PINCTRL_PIN(MX21_PAD_LD11),
185 IMX_PINCTRL_PIN(MX21_PAD_LD12),
186 IMX_PINCTRL_PIN(MX21_PAD_LD13),
187 IMX_PINCTRL_PIN(MX21_PAD_LD14),
188 IMX_PINCTRL_PIN(MX21_PAD_LD15),
189 IMX_PINCTRL_PIN(MX21_PAD_LD16),
190 IMX_PINCTRL_PIN(MX21_PAD_LD17),
191 IMX_PINCTRL_PIN(MX21_PAD_REV),
192 IMX_PINCTRL_PIN(MX21_PAD_CLS),
193 IMX_PINCTRL_PIN(MX21_PAD_PS),
194 IMX_PINCTRL_PIN(MX21_PAD_SPL_SPR),
195 IMX_PINCTRL_PIN(MX21_PAD_HSYNC),
196 IMX_PINCTRL_PIN(MX21_PAD_VSYNC),
197 IMX_PINCTRL_PIN(MX21_PAD_CONTRAST),
198 IMX_PINCTRL_PIN(MX21_PAD_OE_ACD),
199 IMX_PINCTRL_PIN(MX21_PAD_SD2_D0),
200 IMX_PINCTRL_PIN(MX21_PAD_SD2_D1),
201 IMX_PINCTRL_PIN(MX21_PAD_SD2_D2),
202 IMX_PINCTRL_PIN(MX21_PAD_SD2_D3),
203 IMX_PINCTRL_PIN(MX21_PAD_SD2_CMD),
204 IMX_PINCTRL_PIN(MX21_PAD_SD2_CLK),
205 IMX_PINCTRL_PIN(MX21_PAD_CSI_D0),
206 IMX_PINCTRL_PIN(MX21_PAD_CSI_D1),
207 IMX_PINCTRL_PIN(MX21_PAD_CSI_D2),
208 IMX_PINCTRL_PIN(MX21_PAD_CSI_D3),
209 IMX_PINCTRL_PIN(MX21_PAD_CSI_D4),
210 IMX_PINCTRL_PIN(MX21_PAD_CSI_MCLK),
211 IMX_PINCTRL_PIN(MX21_PAD_CSI_PIXCLK),
212 IMX_PINCTRL_PIN(MX21_PAD_CSI_D5),
213 IMX_PINCTRL_PIN(MX21_PAD_CSI_D6),
214 IMX_PINCTRL_PIN(MX21_PAD_CSI_D7),
215 IMX_PINCTRL_PIN(MX21_PAD_CSI_VSYNC),
216 IMX_PINCTRL_PIN(MX21_PAD_CSI_HSYNC),
217 IMX_PINCTRL_PIN(MX21_PAD_USB_BYP),
218 IMX_PINCTRL_PIN(MX21_PAD_USB_PWR),
219 IMX_PINCTRL_PIN(MX21_PAD_USB_OC),
220 IMX_PINCTRL_PIN(MX21_PAD_USBH_ON),
221 IMX_PINCTRL_PIN(MX21_PAD_USBH1_FS),
222 IMX_PINCTRL_PIN(MX21_PAD_USBH1_OE),
223 IMX_PINCTRL_PIN(MX21_PAD_USBH1_TXDM),
224 IMX_PINCTRL_PIN(MX21_PAD_USBH1_TXDP),
225 IMX_PINCTRL_PIN(MX21_PAD_USBH1_RXDM),
226 IMX_PINCTRL_PIN(MX21_PAD_USBH1_RXDP),
227 IMX_PINCTRL_PIN(MX21_PAD_USBG_SDA),
228 IMX_PINCTRL_PIN(MX21_PAD_USBG_SCL),
229 IMX_PINCTRL_PIN(MX21_PAD_USBG_ON),
230 IMX_PINCTRL_PIN(MX21_PAD_USBG_FS),
231 IMX_PINCTRL_PIN(MX21_PAD_USBG_OE),
232 IMX_PINCTRL_PIN(MX21_PAD_USBG_TXDM),
233 IMX_PINCTRL_PIN(MX21_PAD_USBG_TXDP),
234 IMX_PINCTRL_PIN(MX21_PAD_USBG_RXDM),
235 IMX_PINCTRL_PIN(MX21_PAD_USBG_RXDP),
236 IMX_PINCTRL_PIN(MX21_PAD_TOUT),
237 IMX_PINCTRL_PIN(MX21_PAD_TIN),
238 IMX_PINCTRL_PIN(MX21_PAD_SAP_FS),
239 IMX_PINCTRL_PIN(MX21_PAD_SAP_RXD),
240 IMX_PINCTRL_PIN(MX21_PAD_SAP_TXD),
241 IMX_PINCTRL_PIN(MX21_PAD_SAP_CLK),
242 IMX_PINCTRL_PIN(MX21_PAD_SSI1_FS),
243 IMX_PINCTRL_PIN(MX21_PAD_SSI1_RXD),
244 IMX_PINCTRL_PIN(MX21_PAD_SSI1_TXD),
245 IMX_PINCTRL_PIN(MX21_PAD_SSI1_CLK),
246 IMX_PINCTRL_PIN(MX21_PAD_SSI2_FS),
247 IMX_PINCTRL_PIN(MX21_PAD_SSI2_RXD),
248 IMX_PINCTRL_PIN(MX21_PAD_SSI2_TXD),
249 IMX_PINCTRL_PIN(MX21_PAD_SSI2_CLK),
250 IMX_PINCTRL_PIN(MX21_PAD_SSI3_FS),
251 IMX_PINCTRL_PIN(MX21_PAD_SSI3_RXD),
252 IMX_PINCTRL_PIN(MX21_PAD_SSI3_TXD),
253 IMX_PINCTRL_PIN(MX21_PAD_SSI3_CLK),
254 IMX_PINCTRL_PIN(MX21_PAD_I2C_DATA),
255 IMX_PINCTRL_PIN(MX21_PAD_I2C_CLK),
256 IMX_PINCTRL_PIN(MX21_PAD_CSPI2_SS2),
257 IMX_PINCTRL_PIN(MX21_PAD_CSPI2_SS1),
258 IMX_PINCTRL_PIN(MX21_PAD_CSPI2_SS0),
259 IMX_PINCTRL_PIN(MX21_PAD_CSPI2_SCLK),
260 IMX_PINCTRL_PIN(MX21_PAD_CSPI2_MISO),
261 IMX_PINCTRL_PIN(MX21_PAD_CSPI2_MOSI),
262 IMX_PINCTRL_PIN(MX21_PAD_CSPI1_RDY),
263 IMX_PINCTRL_PIN(MX21_PAD_CSPI1_SS2),
264 IMX_PINCTRL_PIN(MX21_PAD_CSPI1_SS1),
265 IMX_PINCTRL_PIN(MX21_PAD_CSPI1_SS0),
266 IMX_PINCTRL_PIN(MX21_PAD_CSPI1_SCLK),
267 IMX_PINCTRL_PIN(MX21_PAD_CSPI1_MISO),
268 IMX_PINCTRL_PIN(MX21_PAD_CSPI1_MOSI),
269 IMX_PINCTRL_PIN(MX21_PAD_TEST_WB2),
270 IMX_PINCTRL_PIN(MX21_PAD_TEST_WB1),
271 IMX_PINCTRL_PIN(MX21_PAD_TEST_WB0),
272 IMX_PINCTRL_PIN(MX21_PAD_UART2_CTS),
273 IMX_PINCTRL_PIN(MX21_PAD_UART2_RTS),
274 IMX_PINCTRL_PIN(MX21_PAD_PWMO),
275 IMX_PINCTRL_PIN(MX21_PAD_UART2_TXD),
276 IMX_PINCTRL_PIN(MX21_PAD_UART2_RXD),
277 IMX_PINCTRL_PIN(MX21_PAD_UART3_TXD),
278 IMX_PINCTRL_PIN(MX21_PAD_UART3_RXD),
279 IMX_PINCTRL_PIN(MX21_PAD_UART3_CTS),
280 IMX_PINCTRL_PIN(MX21_PAD_UART3_RTS),
281 IMX_PINCTRL_PIN(MX21_PAD_UART1_TXD),
282 IMX_PINCTRL_PIN(MX21_PAD_UART1_RXD),
283 IMX_PINCTRL_PIN(MX21_PAD_UART1_CTS),
284 IMX_PINCTRL_PIN(MX21_PAD_UART1_RTS),
285 IMX_PINCTRL_PIN(MX21_PAD_RTCK),
286 IMX_PINCTRL_PIN(MX21_PAD_RESET_OUT),
287 IMX_PINCTRL_PIN(MX21_PAD_SD1_D0),
288 IMX_PINCTRL_PIN(MX21_PAD_SD1_D1),
289 IMX_PINCTRL_PIN(MX21_PAD_SD1_D2),
290 IMX_PINCTRL_PIN(MX21_PAD_SD1_D3),
291 IMX_PINCTRL_PIN(MX21_PAD_SD1_CMD),
292 IMX_PINCTRL_PIN(MX21_PAD_SD1_CLK),
293 IMX_PINCTRL_PIN(MX21_PAD_NFRB),
294 IMX_PINCTRL_PIN(MX21_PAD_NFCE),
295 IMX_PINCTRL_PIN(MX21_PAD_NFWP),
296 IMX_PINCTRL_PIN(MX21_PAD_NFCLE),
297 IMX_PINCTRL_PIN(MX21_PAD_NFALE),
298 IMX_PINCTRL_PIN(MX21_PAD_NFRE),
299 IMX_PINCTRL_PIN(MX21_PAD_NFWE),
300 IMX_PINCTRL_PIN(MX21_PAD_NFIO0),
301 IMX_PINCTRL_PIN(MX21_PAD_NFIO1),
302 IMX_PINCTRL_PIN(MX21_PAD_NFIO2),
303 IMX_PINCTRL_PIN(MX21_PAD_NFIO3),
304 IMX_PINCTRL_PIN(MX21_PAD_NFIO4),
305 IMX_PINCTRL_PIN(MX21_PAD_NFIO5),
306 IMX_PINCTRL_PIN(MX21_PAD_NFIO6),
307 IMX_PINCTRL_PIN(MX21_PAD_NFIO7),
308 IMX_PINCTRL_PIN(MX21_PAD_CLKO),
309 IMX_PINCTRL_PIN(MX21_PAD_RESERVED),
310 IMX_PINCTRL_PIN(MX21_PAD_CS4),
311 IMX_PINCTRL_PIN(MX21_PAD_CS5),
312};
313
314static struct imx1_pinctrl_soc_info imx21_pinctrl_info = {
315 .pins = imx21_pinctrl_pads,
316 .npins = ARRAY_SIZE(imx21_pinctrl_pads),
317};
318
319static int __init imx21_pinctrl_probe(struct platform_device *pdev)
320{
321 return imx1_pinctrl_core_probe(pdev, &imx21_pinctrl_info);
322}
323
324static const struct of_device_id imx21_pinctrl_of_match[] = {
325 { .compatible = "fsl,imx21-iomuxc", },
326 { }
327};
328MODULE_DEVICE_TABLE(of, imx21_pinctrl_of_match);
329
330static struct platform_driver imx21_pinctrl_driver = {
331 .driver = {
332 .name = "imx21-pinctrl",
333 .owner = THIS_MODULE,
334 .of_match_table = imx21_pinctrl_of_match,
335 },
336 .remove = imx1_pinctrl_core_remove,
337};
338module_platform_driver_probe(imx21_pinctrl_driver, imx21_pinctrl_probe);
339
340MODULE_AUTHOR("Alexander Shiyan <shc_work@mail.ru>");
341MODULE_DESCRIPTION("Freescale i.MX21 pinctrl driver");
342MODULE_LICENSE("GPL");
diff --git a/drivers/pinctrl/pinctrl-imx23.c b/drivers/pinctrl/freescale/pinctrl-imx23.c
index e76d75c9d1ba..df79096becb0 100644
--- a/drivers/pinctrl/pinctrl-imx23.c
+++ b/drivers/pinctrl/freescale/pinctrl-imx23.c
@@ -272,7 +272,7 @@ static int imx23_pinctrl_probe(struct platform_device *pdev)
272 return mxs_pinctrl_probe(pdev, &imx23_pinctrl_data); 272 return mxs_pinctrl_probe(pdev, &imx23_pinctrl_data);
273} 273}
274 274
275static struct of_device_id imx23_pinctrl_of_match[] = { 275static const struct of_device_id imx23_pinctrl_of_match[] = {
276 { .compatible = "fsl,imx23-pinctrl", }, 276 { .compatible = "fsl,imx23-pinctrl", },
277 { /* sentinel */ } 277 { /* sentinel */ }
278}; 278};
diff --git a/drivers/pinctrl/pinctrl-imx25.c b/drivers/pinctrl/freescale/pinctrl-imx25.c
index 1aae1b61c4dc..550e6d77ac2b 100644
--- a/drivers/pinctrl/pinctrl-imx25.c
+++ b/drivers/pinctrl/freescale/pinctrl-imx25.c
@@ -315,7 +315,7 @@ static struct imx_pinctrl_soc_info imx25_pinctrl_info = {
315 .npins = ARRAY_SIZE(imx25_pinctrl_pads), 315 .npins = ARRAY_SIZE(imx25_pinctrl_pads),
316}; 316};
317 317
318static struct of_device_id imx25_pinctrl_of_match[] = { 318static const struct of_device_id imx25_pinctrl_of_match[] = {
319 { .compatible = "fsl,imx25-iomuxc", }, 319 { .compatible = "fsl,imx25-iomuxc", },
320 { /* sentinel */ } 320 { /* sentinel */ }
321}; 321};
diff --git a/drivers/pinctrl/pinctrl-imx27.c b/drivers/pinctrl/freescale/pinctrl-imx27.c
index 417c99205bc2..945eccadea74 100644
--- a/drivers/pinctrl/pinctrl-imx27.c
+++ b/drivers/pinctrl/freescale/pinctrl-imx27.c
@@ -63,10 +63,6 @@ enum imx27_pads {
63 MX27_PAD_CONTRAST = PAD_ID(PA, 30), 63 MX27_PAD_CONTRAST = PAD_ID(PA, 30),
64 MX27_PAD_OE_ACD = PAD_ID(PA, 31), 64 MX27_PAD_OE_ACD = PAD_ID(PA, 31),
65 65
66 MX27_PAD_UNUSED0 = PAD_ID(PB, 0),
67 MX27_PAD_UNUSED1 = PAD_ID(PB, 1),
68 MX27_PAD_UNUSED2 = PAD_ID(PB, 2),
69 MX27_PAD_UNUSED3 = PAD_ID(PB, 3),
70 MX27_PAD_SD2_D0 = PAD_ID(PB, 4), 66 MX27_PAD_SD2_D0 = PAD_ID(PB, 4),
71 MX27_PAD_SD2_D1 = PAD_ID(PB, 5), 67 MX27_PAD_SD2_D1 = PAD_ID(PB, 5),
72 MX27_PAD_SD2_D2 = PAD_ID(PB, 6), 68 MX27_PAD_SD2_D2 = PAD_ID(PB, 6),
@@ -96,11 +92,6 @@ enum imx27_pads {
96 MX27_PAD_USBH1_RXDM = PAD_ID(PB, 30), 92 MX27_PAD_USBH1_RXDM = PAD_ID(PB, 30),
97 MX27_PAD_USBH1_RXDP = PAD_ID(PB, 31), 93 MX27_PAD_USBH1_RXDP = PAD_ID(PB, 31),
98 94
99 MX27_PAD_UNUSED4 = PAD_ID(PC, 0),
100 MX27_PAD_UNUSED5 = PAD_ID(PC, 1),
101 MX27_PAD_UNUSED6 = PAD_ID(PC, 2),
102 MX27_PAD_UNUSED7 = PAD_ID(PC, 3),
103 MX27_PAD_UNUSED8 = PAD_ID(PC, 4),
104 MX27_PAD_I2C2_SDA = PAD_ID(PC, 5), 95 MX27_PAD_I2C2_SDA = PAD_ID(PC, 5),
105 MX27_PAD_I2C2_SCL = PAD_ID(PC, 6), 96 MX27_PAD_I2C2_SCL = PAD_ID(PC, 6),
106 MX27_PAD_USBOTG_DATA5 = PAD_ID(PC, 7), 97 MX27_PAD_USBOTG_DATA5 = PAD_ID(PC, 7),
@@ -188,12 +179,6 @@ enum imx27_pads {
188 MX27_PAD_SD1_CLK = PAD_ID(PE, 23), 179 MX27_PAD_SD1_CLK = PAD_ID(PE, 23),
189 MX27_PAD_USBOTG_CLK = PAD_ID(PE, 24), 180 MX27_PAD_USBOTG_CLK = PAD_ID(PE, 24),
190 MX27_PAD_USBOTG_DATA7 = PAD_ID(PE, 25), 181 MX27_PAD_USBOTG_DATA7 = PAD_ID(PE, 25),
191 MX27_PAD_UNUSED9 = PAD_ID(PE, 26),
192 MX27_PAD_UNUSED10 = PAD_ID(PE, 27),
193 MX27_PAD_UNUSED11 = PAD_ID(PE, 28),
194 MX27_PAD_UNUSED12 = PAD_ID(PE, 29),
195 MX27_PAD_UNUSED13 = PAD_ID(PE, 30),
196 MX27_PAD_UNUSED14 = PAD_ID(PE, 31),
197 182
198 MX27_PAD_NFRB = PAD_ID(PF, 0), 183 MX27_PAD_NFRB = PAD_ID(PF, 0),
199 MX27_PAD_NFCLE = PAD_ID(PF, 1), 184 MX27_PAD_NFCLE = PAD_ID(PF, 1),
@@ -219,14 +204,6 @@ enum imx27_pads {
219 MX27_PAD_CS4_B = PAD_ID(PF, 21), 204 MX27_PAD_CS4_B = PAD_ID(PF, 21),
220 MX27_PAD_CS5_B = PAD_ID(PF, 22), 205 MX27_PAD_CS5_B = PAD_ID(PF, 22),
221 MX27_PAD_ATA_DATA15 = PAD_ID(PF, 23), 206 MX27_PAD_ATA_DATA15 = PAD_ID(PF, 23),
222 MX27_PAD_UNUSED15 = PAD_ID(PF, 24),
223 MX27_PAD_UNUSED16 = PAD_ID(PF, 25),
224 MX27_PAD_UNUSED17 = PAD_ID(PF, 26),
225 MX27_PAD_UNUSED18 = PAD_ID(PF, 27),
226 MX27_PAD_UNUSED19 = PAD_ID(PF, 28),
227 MX27_PAD_UNUSED20 = PAD_ID(PF, 29),
228 MX27_PAD_UNUSED21 = PAD_ID(PF, 30),
229 MX27_PAD_UNUSED22 = PAD_ID(PF, 31),
230}; 207};
231 208
232/* Pad names for the pinmux subsystem */ 209/* Pad names for the pinmux subsystem */
@@ -264,10 +241,6 @@ static const struct pinctrl_pin_desc imx27_pinctrl_pads[] = {
264 IMX_PINCTRL_PIN(MX27_PAD_CONTRAST), 241 IMX_PINCTRL_PIN(MX27_PAD_CONTRAST),
265 IMX_PINCTRL_PIN(MX27_PAD_OE_ACD), 242 IMX_PINCTRL_PIN(MX27_PAD_OE_ACD),
266 243
267 IMX_PINCTRL_PIN(MX27_PAD_UNUSED0),
268 IMX_PINCTRL_PIN(MX27_PAD_UNUSED1),
269 IMX_PINCTRL_PIN(MX27_PAD_UNUSED2),
270 IMX_PINCTRL_PIN(MX27_PAD_UNUSED3),
271 IMX_PINCTRL_PIN(MX27_PAD_SD2_D0), 244 IMX_PINCTRL_PIN(MX27_PAD_SD2_D0),
272 IMX_PINCTRL_PIN(MX27_PAD_SD2_D1), 245 IMX_PINCTRL_PIN(MX27_PAD_SD2_D1),
273 IMX_PINCTRL_PIN(MX27_PAD_SD2_D2), 246 IMX_PINCTRL_PIN(MX27_PAD_SD2_D2),
@@ -297,11 +270,6 @@ static const struct pinctrl_pin_desc imx27_pinctrl_pads[] = {
297 IMX_PINCTRL_PIN(MX27_PAD_USBH1_RXDM), 270 IMX_PINCTRL_PIN(MX27_PAD_USBH1_RXDM),
298 IMX_PINCTRL_PIN(MX27_PAD_USBH1_RXDP), 271 IMX_PINCTRL_PIN(MX27_PAD_USBH1_RXDP),
299 272
300 IMX_PINCTRL_PIN(MX27_PAD_UNUSED4),
301 IMX_PINCTRL_PIN(MX27_PAD_UNUSED5),
302 IMX_PINCTRL_PIN(MX27_PAD_UNUSED6),
303 IMX_PINCTRL_PIN(MX27_PAD_UNUSED7),
304 IMX_PINCTRL_PIN(MX27_PAD_UNUSED8),
305 IMX_PINCTRL_PIN(MX27_PAD_I2C2_SDA), 273 IMX_PINCTRL_PIN(MX27_PAD_I2C2_SDA),
306 IMX_PINCTRL_PIN(MX27_PAD_I2C2_SCL), 274 IMX_PINCTRL_PIN(MX27_PAD_I2C2_SCL),
307 IMX_PINCTRL_PIN(MX27_PAD_USBOTG_DATA5), 275 IMX_PINCTRL_PIN(MX27_PAD_USBOTG_DATA5),
@@ -389,12 +357,6 @@ static const struct pinctrl_pin_desc imx27_pinctrl_pads[] = {
389 IMX_PINCTRL_PIN(MX27_PAD_SD1_CLK), 357 IMX_PINCTRL_PIN(MX27_PAD_SD1_CLK),
390 IMX_PINCTRL_PIN(MX27_PAD_USBOTG_CLK), 358 IMX_PINCTRL_PIN(MX27_PAD_USBOTG_CLK),
391 IMX_PINCTRL_PIN(MX27_PAD_USBOTG_DATA7), 359 IMX_PINCTRL_PIN(MX27_PAD_USBOTG_DATA7),
392 IMX_PINCTRL_PIN(MX27_PAD_UNUSED9),
393 IMX_PINCTRL_PIN(MX27_PAD_UNUSED10),
394 IMX_PINCTRL_PIN(MX27_PAD_UNUSED11),
395 IMX_PINCTRL_PIN(MX27_PAD_UNUSED12),
396 IMX_PINCTRL_PIN(MX27_PAD_UNUSED13),
397 IMX_PINCTRL_PIN(MX27_PAD_UNUSED14),
398 360
399 IMX_PINCTRL_PIN(MX27_PAD_NFRB), 361 IMX_PINCTRL_PIN(MX27_PAD_NFRB),
400 IMX_PINCTRL_PIN(MX27_PAD_NFCLE), 362 IMX_PINCTRL_PIN(MX27_PAD_NFCLE),
@@ -420,14 +382,6 @@ static const struct pinctrl_pin_desc imx27_pinctrl_pads[] = {
420 IMX_PINCTRL_PIN(MX27_PAD_CS4_B), 382 IMX_PINCTRL_PIN(MX27_PAD_CS4_B),
421 IMX_PINCTRL_PIN(MX27_PAD_CS5_B), 383 IMX_PINCTRL_PIN(MX27_PAD_CS5_B),
422 IMX_PINCTRL_PIN(MX27_PAD_ATA_DATA15), 384 IMX_PINCTRL_PIN(MX27_PAD_ATA_DATA15),
423 IMX_PINCTRL_PIN(MX27_PAD_UNUSED15),
424 IMX_PINCTRL_PIN(MX27_PAD_UNUSED16),
425 IMX_PINCTRL_PIN(MX27_PAD_UNUSED17),
426 IMX_PINCTRL_PIN(MX27_PAD_UNUSED18),
427 IMX_PINCTRL_PIN(MX27_PAD_UNUSED19),
428 IMX_PINCTRL_PIN(MX27_PAD_UNUSED20),
429 IMX_PINCTRL_PIN(MX27_PAD_UNUSED21),
430 IMX_PINCTRL_PIN(MX27_PAD_UNUSED22),
431}; 385};
432 386
433static struct imx1_pinctrl_soc_info imx27_pinctrl_info = { 387static struct imx1_pinctrl_soc_info imx27_pinctrl_info = {
@@ -435,17 +389,11 @@ static struct imx1_pinctrl_soc_info imx27_pinctrl_info = {
435 .npins = ARRAY_SIZE(imx27_pinctrl_pads), 389 .npins = ARRAY_SIZE(imx27_pinctrl_pads),
436}; 390};
437 391
438static struct of_device_id imx27_pinctrl_of_match[] = { 392static const struct of_device_id imx27_pinctrl_of_match[] = {
439 { .compatible = "fsl,imx27-iomuxc", }, 393 { .compatible = "fsl,imx27-iomuxc", },
440 { /* sentinel */ } 394 { /* sentinel */ }
441}; 395};
442 396
443struct imx27_pinctrl_private {
444 int num_gpio_childs;
445 struct platform_device **gpio_dev;
446 struct mxc_gpio_platform_data *gpio_pdata;
447};
448
449static int imx27_pinctrl_probe(struct platform_device *pdev) 397static int imx27_pinctrl_probe(struct platform_device *pdev)
450{ 398{
451 return imx1_pinctrl_core_probe(pdev, &imx27_pinctrl_info); 399 return imx1_pinctrl_core_probe(pdev, &imx27_pinctrl_info);
diff --git a/drivers/pinctrl/pinctrl-imx28.c b/drivers/pinctrl/freescale/pinctrl-imx28.c
index 79c9c8d296af..3bd45da21229 100644
--- a/drivers/pinctrl/pinctrl-imx28.c
+++ b/drivers/pinctrl/freescale/pinctrl-imx28.c
@@ -388,7 +388,7 @@ static int imx28_pinctrl_probe(struct platform_device *pdev)
388 return mxs_pinctrl_probe(pdev, &imx28_pinctrl_data); 388 return mxs_pinctrl_probe(pdev, &imx28_pinctrl_data);
389} 389}
390 390
391static struct of_device_id imx28_pinctrl_of_match[] = { 391static const struct of_device_id imx28_pinctrl_of_match[] = {
392 { .compatible = "fsl,imx28-pinctrl", }, 392 { .compatible = "fsl,imx28-pinctrl", },
393 { /* sentinel */ } 393 { /* sentinel */ }
394}; 394};
diff --git a/drivers/pinctrl/pinctrl-imx35.c b/drivers/pinctrl/freescale/pinctrl-imx35.c
index 278a04ae8940..6bfbcd0112c1 100644
--- a/drivers/pinctrl/pinctrl-imx35.c
+++ b/drivers/pinctrl/freescale/pinctrl-imx35.c
@@ -1005,7 +1005,7 @@ static struct imx_pinctrl_soc_info imx35_pinctrl_info = {
1005 .npins = ARRAY_SIZE(imx35_pinctrl_pads), 1005 .npins = ARRAY_SIZE(imx35_pinctrl_pads),
1006}; 1006};
1007 1007
1008static struct of_device_id imx35_pinctrl_of_match[] = { 1008static const struct of_device_id imx35_pinctrl_of_match[] = {
1009 { .compatible = "fsl,imx35-iomuxc", }, 1009 { .compatible = "fsl,imx35-iomuxc", },
1010 { /* sentinel */ } 1010 { /* sentinel */ }
1011}; 1011};
diff --git a/drivers/pinctrl/pinctrl-imx50.c b/drivers/pinctrl/freescale/pinctrl-imx50.c
index b06feed1b038..e8bd604ab147 100644
--- a/drivers/pinctrl/pinctrl-imx50.c
+++ b/drivers/pinctrl/freescale/pinctrl-imx50.c
@@ -391,7 +391,7 @@ static struct imx_pinctrl_soc_info imx50_pinctrl_info = {
391 .npins = ARRAY_SIZE(imx50_pinctrl_pads), 391 .npins = ARRAY_SIZE(imx50_pinctrl_pads),
392}; 392};
393 393
394static struct of_device_id imx50_pinctrl_of_match[] = { 394static const struct of_device_id imx50_pinctrl_of_match[] = {
395 { .compatible = "fsl,imx50-iomuxc", }, 395 { .compatible = "fsl,imx50-iomuxc", },
396 { /* sentinel */ } 396 { /* sentinel */ }
397}; 397};
diff --git a/drivers/pinctrl/pinctrl-imx51.c b/drivers/pinctrl/freescale/pinctrl-imx51.c
index 19ab182bef61..b818051db7c9 100644
--- a/drivers/pinctrl/pinctrl-imx51.c
+++ b/drivers/pinctrl/freescale/pinctrl-imx51.c
@@ -768,7 +768,7 @@ static struct imx_pinctrl_soc_info imx51_pinctrl_info = {
768 .npins = ARRAY_SIZE(imx51_pinctrl_pads), 768 .npins = ARRAY_SIZE(imx51_pinctrl_pads),
769}; 769};
770 770
771static struct of_device_id imx51_pinctrl_of_match[] = { 771static const struct of_device_id imx51_pinctrl_of_match[] = {
772 { .compatible = "fsl,imx51-iomuxc", }, 772 { .compatible = "fsl,imx51-iomuxc", },
773 { /* sentinel */ } 773 { /* sentinel */ }
774}; 774};
diff --git a/drivers/pinctrl/pinctrl-imx53.c b/drivers/pinctrl/freescale/pinctrl-imx53.c
index f8d45c4cfde7..1884d53cf750 100644
--- a/drivers/pinctrl/pinctrl-imx53.c
+++ b/drivers/pinctrl/freescale/pinctrl-imx53.c
@@ -454,7 +454,7 @@ static struct imx_pinctrl_soc_info imx53_pinctrl_info = {
454 .npins = ARRAY_SIZE(imx53_pinctrl_pads), 454 .npins = ARRAY_SIZE(imx53_pinctrl_pads),
455}; 455};
456 456
457static struct of_device_id imx53_pinctrl_of_match[] = { 457static const struct of_device_id imx53_pinctrl_of_match[] = {
458 { .compatible = "fsl,imx53-iomuxc", }, 458 { .compatible = "fsl,imx53-iomuxc", },
459 { /* sentinel */ } 459 { /* sentinel */ }
460}; 460};
diff --git a/drivers/pinctrl/pinctrl-imx6dl.c b/drivers/pinctrl/freescale/pinctrl-imx6dl.c
index db2a1489bd99..656c4b08cc2e 100644
--- a/drivers/pinctrl/pinctrl-imx6dl.c
+++ b/drivers/pinctrl/freescale/pinctrl-imx6dl.c
@@ -460,7 +460,7 @@ static struct imx_pinctrl_soc_info imx6dl_pinctrl_info = {
460 .npins = ARRAY_SIZE(imx6dl_pinctrl_pads), 460 .npins = ARRAY_SIZE(imx6dl_pinctrl_pads),
461}; 461};
462 462
463static struct of_device_id imx6dl_pinctrl_of_match[] = { 463static const struct of_device_id imx6dl_pinctrl_of_match[] = {
464 { .compatible = "fsl,imx6dl-iomuxc", }, 464 { .compatible = "fsl,imx6dl-iomuxc", },
465 { /* sentinel */ } 465 { /* sentinel */ }
466}; 466};
diff --git a/drivers/pinctrl/pinctrl-imx6q.c b/drivers/pinctrl/freescale/pinctrl-imx6q.c
index 8eb5ac1bd5f6..59bb5b4ec0f6 100644
--- a/drivers/pinctrl/pinctrl-imx6q.c
+++ b/drivers/pinctrl/freescale/pinctrl-imx6q.c
@@ -466,7 +466,7 @@ static struct imx_pinctrl_soc_info imx6q_pinctrl_info = {
466 .npins = ARRAY_SIZE(imx6q_pinctrl_pads), 466 .npins = ARRAY_SIZE(imx6q_pinctrl_pads),
467}; 467};
468 468
469static struct of_device_id imx6q_pinctrl_of_match[] = { 469static const struct of_device_id imx6q_pinctrl_of_match[] = {
470 { .compatible = "fsl,imx6q-iomuxc", }, 470 { .compatible = "fsl,imx6q-iomuxc", },
471 { /* sentinel */ } 471 { /* sentinel */ }
472}; 472};
diff --git a/drivers/pinctrl/pinctrl-imx6sl.c b/drivers/pinctrl/freescale/pinctrl-imx6sl.c
index f21b7389df3c..e0924bd7b98c 100644
--- a/drivers/pinctrl/pinctrl-imx6sl.c
+++ b/drivers/pinctrl/freescale/pinctrl-imx6sl.c
@@ -366,10 +366,11 @@ static struct imx_pinctrl_soc_info imx6sl_pinctrl_info = {
366 .npins = ARRAY_SIZE(imx6sl_pinctrl_pads), 366 .npins = ARRAY_SIZE(imx6sl_pinctrl_pads),
367}; 367};
368 368
369static struct of_device_id imx6sl_pinctrl_of_match[] = { 369static const struct of_device_id imx6sl_pinctrl_of_match[] = {
370 { .compatible = "fsl,imx6sl-iomuxc", }, 370 { .compatible = "fsl,imx6sl-iomuxc", },
371 { /* sentinel */ } 371 { /* sentinel */ }
372}; 372};
373MODULE_DEVICE_TABLE(of, imx6sl_pinctrl_of_match);
373 374
374static int imx6sl_pinctrl_probe(struct platform_device *pdev) 375static int imx6sl_pinctrl_probe(struct platform_device *pdev)
375{ 376{
diff --git a/drivers/pinctrl/pinctrl-imx6sx.c b/drivers/pinctrl/freescale/pinctrl-imx6sx.c
index 09758a56b9df..840344c8580d 100644
--- a/drivers/pinctrl/pinctrl-imx6sx.c
+++ b/drivers/pinctrl/freescale/pinctrl-imx6sx.c
@@ -370,7 +370,7 @@ static struct imx_pinctrl_soc_info imx6sx_pinctrl_info = {
370 .npins = ARRAY_SIZE(imx6sx_pinctrl_pads), 370 .npins = ARRAY_SIZE(imx6sx_pinctrl_pads),
371}; 371};
372 372
373static struct of_device_id imx6sx_pinctrl_of_match[] = { 373static const struct of_device_id imx6sx_pinctrl_of_match[] = {
374 { .compatible = "fsl,imx6sx-iomuxc", }, 374 { .compatible = "fsl,imx6sx-iomuxc", },
375 { /* sentinel */ } 375 { /* sentinel */ }
376}; 376};
diff --git a/drivers/pinctrl/pinctrl-mxs.c b/drivers/pinctrl/freescale/pinctrl-mxs.c
index 40c76f26998c..f98c6bb0f769 100644
--- a/drivers/pinctrl/pinctrl-mxs.c
+++ b/drivers/pinctrl/freescale/pinctrl-mxs.c
@@ -21,7 +21,7 @@
21#include <linux/pinctrl/pinmux.h> 21#include <linux/pinctrl/pinmux.h>
22#include <linux/platform_device.h> 22#include <linux/platform_device.h>
23#include <linux/slab.h> 23#include <linux/slab.h>
24#include "core.h" 24#include "../core.h"
25#include "pinctrl-mxs.h" 25#include "pinctrl-mxs.h"
26 26
27#define SUFFIX_LEN 4 27#define SUFFIX_LEN 4
@@ -195,8 +195,8 @@ static int mxs_pinctrl_get_func_groups(struct pinctrl_dev *pctldev,
195 return 0; 195 return 0;
196} 196}
197 197
198static int mxs_pinctrl_enable(struct pinctrl_dev *pctldev, unsigned selector, 198static int mxs_pinctrl_set_mux(struct pinctrl_dev *pctldev, unsigned selector,
199 unsigned group) 199 unsigned group)
200{ 200{
201 struct mxs_pinctrl_data *d = pinctrl_dev_get_drvdata(pctldev); 201 struct mxs_pinctrl_data *d = pinctrl_dev_get_drvdata(pctldev);
202 struct mxs_group *g = &d->soc->groups[group]; 202 struct mxs_group *g = &d->soc->groups[group];
@@ -223,7 +223,7 @@ static const struct pinmux_ops mxs_pinmux_ops = {
223 .get_functions_count = mxs_pinctrl_get_funcs_count, 223 .get_functions_count = mxs_pinctrl_get_funcs_count,
224 .get_function_name = mxs_pinctrl_get_func_name, 224 .get_function_name = mxs_pinctrl_get_func_name,
225 .get_function_groups = mxs_pinctrl_get_func_groups, 225 .get_function_groups = mxs_pinctrl_get_func_groups,
226 .enable = mxs_pinctrl_enable, 226 .set_mux = mxs_pinctrl_set_mux,
227}; 227};
228 228
229static int mxs_pinconf_get(struct pinctrl_dev *pctldev, 229static int mxs_pinconf_get(struct pinctrl_dev *pctldev,
diff --git a/drivers/pinctrl/pinctrl-mxs.h b/drivers/pinctrl/freescale/pinctrl-mxs.h
index fdd88d0bae22..fdd88d0bae22 100644
--- a/drivers/pinctrl/pinctrl-mxs.h
+++ b/drivers/pinctrl/freescale/pinctrl-mxs.h
diff --git a/drivers/pinctrl/pinctrl-vf610.c b/drivers/pinctrl/freescale/pinctrl-vf610.c
index bddd913d28ba..b788e1578954 100644
--- a/drivers/pinctrl/pinctrl-vf610.c
+++ b/drivers/pinctrl/freescale/pinctrl-vf610.c
@@ -299,7 +299,7 @@ static const struct pinctrl_pin_desc vf610_pinctrl_pads[] = {
299static struct imx_pinctrl_soc_info vf610_pinctrl_info = { 299static struct imx_pinctrl_soc_info vf610_pinctrl_info = {
300 .pins = vf610_pinctrl_pads, 300 .pins = vf610_pinctrl_pads,
301 .npins = ARRAY_SIZE(vf610_pinctrl_pads), 301 .npins = ARRAY_SIZE(vf610_pinctrl_pads),
302 .flags = ZERO_OFFSET_VALID | SHARE_MUX_CONF_REG, 302 .flags = SHARE_MUX_CONF_REG,
303}; 303};
304 304
305static struct of_device_id vf610_pinctrl_of_match[] = { 305static struct of_device_id vf610_pinctrl_of_match[] = {
diff --git a/drivers/pinctrl/mvebu/pinctrl-mvebu.c b/drivers/pinctrl/mvebu/pinctrl-mvebu.c
index 9908374f8f92..f3b426cdaf8f 100644
--- a/drivers/pinctrl/mvebu/pinctrl-mvebu.c
+++ b/drivers/pinctrl/mvebu/pinctrl-mvebu.c
@@ -259,8 +259,8 @@ static int mvebu_pinmux_get_groups(struct pinctrl_dev *pctldev, unsigned fid,
259 return 0; 259 return 0;
260} 260}
261 261
262static int mvebu_pinmux_enable(struct pinctrl_dev *pctldev, unsigned fid, 262static int mvebu_pinmux_set(struct pinctrl_dev *pctldev, unsigned fid,
263 unsigned gid) 263 unsigned gid)
264{ 264{
265 struct mvebu_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); 265 struct mvebu_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
266 struct mvebu_pinctrl_function *func = &pctl->functions[fid]; 266 struct mvebu_pinctrl_function *func = &pctl->functions[fid];
@@ -344,7 +344,7 @@ static const struct pinmux_ops mvebu_pinmux_ops = {
344 .get_function_groups = mvebu_pinmux_get_groups, 344 .get_function_groups = mvebu_pinmux_get_groups,
345 .gpio_request_enable = mvebu_pinmux_gpio_request_enable, 345 .gpio_request_enable = mvebu_pinmux_gpio_request_enable,
346 .gpio_set_direction = mvebu_pinmux_gpio_set_direction, 346 .gpio_set_direction = mvebu_pinmux_gpio_set_direction,
347 .enable = mvebu_pinmux_enable, 347 .set_mux = mvebu_pinmux_set,
348}; 348};
349 349
350static int mvebu_pinctrl_get_groups_count(struct pinctrl_dev *pctldev) 350static int mvebu_pinctrl_get_groups_count(struct pinctrl_dev *pctldev)
diff --git a/drivers/pinctrl/nomadik/Kconfig b/drivers/pinctrl/nomadik/Kconfig
new file mode 100644
index 000000000000..d48a5aa24a29
--- /dev/null
+++ b/drivers/pinctrl/nomadik/Kconfig
@@ -0,0 +1,51 @@
1if ARCH_U8500
2
3config PINCTRL_ABX500
4 bool "ST-Ericsson ABx500 family Mixed Signal Circuit gpio functions"
5 depends on AB8500_CORE
6 select GENERIC_PINCONF
7 help
8 Select this to enable the ABx500 family IC GPIO driver
9
10config PINCTRL_AB8500
11 bool "AB8500 pin controller driver"
12 depends on PINCTRL_ABX500 && ARCH_U8500
13
14config PINCTRL_AB8540
15 bool "AB8540 pin controller driver"
16 depends on PINCTRL_ABX500 && ARCH_U8500
17
18config PINCTRL_AB9540
19 bool "AB9540 pin controller driver"
20 depends on PINCTRL_ABX500 && ARCH_U8500
21
22config PINCTRL_AB8505
23 bool "AB8505 pin controller driver"
24 depends on PINCTRL_ABX500 && ARCH_U8500
25
26endif
27
28if (ARCH_U8500 || ARCH_NOMADIK)
29
30config PINCTRL_NOMADIK
31 bool "Nomadik pin controller driver"
32 depends on ARCH_U8500 || ARCH_NOMADIK
33 select PINMUX
34 select PINCONF
35 select GPIOLIB
36 select OF_GPIO
37 select GPIOLIB_IRQCHIP
38
39config PINCTRL_STN8815
40 bool "STN8815 pin controller driver"
41 depends on PINCTRL_NOMADIK && ARCH_NOMADIK
42
43config PINCTRL_DB8500
44 bool "DB8500 pin controller driver"
45 depends on PINCTRL_NOMADIK && ARCH_U8500
46
47config PINCTRL_DB8540
48 bool "DB8540 pin controller driver"
49 depends on PINCTRL_NOMADIK && ARCH_U8500
50
51endif
diff --git a/drivers/pinctrl/nomadik/Makefile b/drivers/pinctrl/nomadik/Makefile
new file mode 100644
index 000000000000..30b27f18cd52
--- /dev/null
+++ b/drivers/pinctrl/nomadik/Makefile
@@ -0,0 +1,10 @@
1# Nomadik family pin control drivers
2obj-$(CONFIG_PINCTRL_ABX500) += pinctrl-abx500.o
3obj-$(CONFIG_PINCTRL_AB8500) += pinctrl-ab8500.o
4obj-$(CONFIG_PINCTRL_AB8540) += pinctrl-ab8540.o
5obj-$(CONFIG_PINCTRL_AB9540) += pinctrl-ab9540.o
6obj-$(CONFIG_PINCTRL_AB8505) += pinctrl-ab8505.o
7obj-$(CONFIG_PINCTRL_NOMADIK) += pinctrl-nomadik.o
8obj-$(CONFIG_PINCTRL_STN8815) += pinctrl-nomadik-stn8815.o
9obj-$(CONFIG_PINCTRL_DB8500) += pinctrl-nomadik-db8500.o
10obj-$(CONFIG_PINCTRL_DB8540) += pinctrl-nomadik-db8540.o
diff --git a/drivers/pinctrl/pinctrl-ab8500.c b/drivers/pinctrl/nomadik/pinctrl-ab8500.c
index 2ac2d0ad3025..2ac2d0ad3025 100644
--- a/drivers/pinctrl/pinctrl-ab8500.c
+++ b/drivers/pinctrl/nomadik/pinctrl-ab8500.c
diff --git a/drivers/pinctrl/pinctrl-ab8505.c b/drivers/pinctrl/nomadik/pinctrl-ab8505.c
index bf0ef4ac376f..bf0ef4ac376f 100644
--- a/drivers/pinctrl/pinctrl-ab8505.c
+++ b/drivers/pinctrl/nomadik/pinctrl-ab8505.c
diff --git a/drivers/pinctrl/pinctrl-ab8540.c b/drivers/pinctrl/nomadik/pinctrl-ab8540.c
index 9867535d49c1..9867535d49c1 100644
--- a/drivers/pinctrl/pinctrl-ab8540.c
+++ b/drivers/pinctrl/nomadik/pinctrl-ab8540.c
diff --git a/drivers/pinctrl/pinctrl-ab9540.c b/drivers/pinctrl/nomadik/pinctrl-ab9540.c
index 1a281ca95dac..1a281ca95dac 100644
--- a/drivers/pinctrl/pinctrl-ab9540.c
+++ b/drivers/pinctrl/nomadik/pinctrl-ab9540.c
diff --git a/drivers/pinctrl/pinctrl-abx500.c b/drivers/pinctrl/nomadik/pinctrl-abx500.c
index 163da9c3ea0e..228972827132 100644
--- a/drivers/pinctrl/pinctrl-abx500.c
+++ b/drivers/pinctrl/nomadik/pinctrl-abx500.c
@@ -32,8 +32,9 @@
32#include <linux/pinctrl/machine.h> 32#include <linux/pinctrl/machine.h>
33 33
34#include "pinctrl-abx500.h" 34#include "pinctrl-abx500.h"
35#include "core.h" 35#include "../core.h"
36#include "pinconf.h" 36#include "../pinconf.h"
37#include "../pinctrl-utils.h"
37 38
38/* 39/*
39 * The AB9540 and AB8540 GPIO support are extended versions 40 * The AB9540 and AB8540 GPIO support are extended versions
@@ -620,8 +621,7 @@ static void abx500_gpio_dbg_show_one(struct seq_file *s,
620 } else 621 } else
621 seq_printf(s, " %-9s", chip->get(chip, offset) ? "hi" : "lo"); 622 seq_printf(s, " %-9s", chip->get(chip, offset) ? "hi" : "lo");
622 623
623 if (pctldev) 624 mode = abx500_get_mode(pctldev, chip, offset);
624 mode = abx500_get_mode(pctldev, chip, offset);
625 625
626 seq_printf(s, " %s", (mode < 0) ? "unknown" : modes[mode]); 626 seq_printf(s, " %s", (mode < 0) ? "unknown" : modes[mode]);
627 627
@@ -709,8 +709,8 @@ static int abx500_pmx_get_func_groups(struct pinctrl_dev *pctldev,
709 return 0; 709 return 0;
710} 710}
711 711
712static int abx500_pmx_enable(struct pinctrl_dev *pctldev, unsigned function, 712static int abx500_pmx_set(struct pinctrl_dev *pctldev, unsigned function,
713 unsigned group) 713 unsigned group)
714{ 714{
715 struct abx500_pinctrl *pct = pinctrl_dev_get_drvdata(pctldev); 715 struct abx500_pinctrl *pct = pinctrl_dev_get_drvdata(pctldev);
716 struct gpio_chip *chip = &pct->chip; 716 struct gpio_chip *chip = &pct->chip;
@@ -737,20 +737,6 @@ static int abx500_pmx_enable(struct pinctrl_dev *pctldev, unsigned function,
737 return ret; 737 return ret;
738} 738}
739 739
740static void abx500_pmx_disable(struct pinctrl_dev *pctldev,
741 unsigned function, unsigned group)
742{
743 struct abx500_pinctrl *pct = pinctrl_dev_get_drvdata(pctldev);
744 const struct abx500_pingroup *g;
745
746 g = &pct->soc->groups[group];
747 if (g->altsetting < 0)
748 return;
749
750 /* FIXME: poke out the mux, set the pin to some default state? */
751 dev_dbg(pct->dev, "disable group %s, %u pins\n", g->name, g->npins);
752}
753
754static int abx500_gpio_request_enable(struct pinctrl_dev *pctldev, 740static int abx500_gpio_request_enable(struct pinctrl_dev *pctldev,
755 struct pinctrl_gpio_range *range, 741 struct pinctrl_gpio_range *range,
756 unsigned offset) 742 unsigned offset)
@@ -798,8 +784,7 @@ static const struct pinmux_ops abx500_pinmux_ops = {
798 .get_functions_count = abx500_pmx_get_funcs_cnt, 784 .get_functions_count = abx500_pmx_get_funcs_cnt,
799 .get_function_name = abx500_pmx_get_func_name, 785 .get_function_name = abx500_pmx_get_func_name,
800 .get_function_groups = abx500_pmx_get_func_groups, 786 .get_function_groups = abx500_pmx_get_func_groups,
801 .enable = abx500_pmx_enable, 787 .set_mux = abx500_pmx_set,
802 .disable = abx500_pmx_disable,
803 .gpio_request_enable = abx500_gpio_request_enable, 788 .gpio_request_enable = abx500_gpio_request_enable,
804 .gpio_disable_free = abx500_gpio_disable_free, 789 .gpio_disable_free = abx500_gpio_disable_free,
805}; 790};
@@ -842,41 +827,6 @@ static void abx500_pin_dbg_show(struct pinctrl_dev *pctldev,
842 chip->base + offset - 1); 827 chip->base + offset - 1);
843} 828}
844 829
845static void abx500_dt_free_map(struct pinctrl_dev *pctldev,
846 struct pinctrl_map *map, unsigned num_maps)
847{
848 int i;
849
850 for (i = 0; i < num_maps; i++)
851 if (map[i].type == PIN_MAP_TYPE_CONFIGS_PIN)
852 kfree(map[i].data.configs.configs);
853 kfree(map);
854}
855
856static int abx500_dt_reserve_map(struct pinctrl_map **map,
857 unsigned *reserved_maps,
858 unsigned *num_maps,
859 unsigned reserve)
860{
861 unsigned old_num = *reserved_maps;
862 unsigned new_num = *num_maps + reserve;
863 struct pinctrl_map *new_map;
864
865 if (old_num >= new_num)
866 return 0;
867
868 new_map = krealloc(*map, sizeof(*new_map) * new_num, GFP_KERNEL);
869 if (!new_map)
870 return -ENOMEM;
871
872 memset(new_map + old_num, 0, (new_num - old_num) * sizeof(*new_map));
873
874 *map = new_map;
875 *reserved_maps = new_num;
876
877 return 0;
878}
879
880static int abx500_dt_add_map_mux(struct pinctrl_map **map, 830static int abx500_dt_add_map_mux(struct pinctrl_map **map,
881 unsigned *reserved_maps, 831 unsigned *reserved_maps,
882 unsigned *num_maps, const char *group, 832 unsigned *num_maps, const char *group,
@@ -942,19 +892,32 @@ static int abx500_dt_subnode_to_map(struct pinctrl_dev *pctldev,
942 unsigned long *configs; 892 unsigned long *configs;
943 unsigned int nconfigs = 0; 893 unsigned int nconfigs = 0;
944 bool has_config = 0; 894 bool has_config = 0;
945 unsigned reserve = 0;
946 struct property *prop; 895 struct property *prop;
947 const char *group, *gpio_name; 896 const char *group, *gpio_name;
948 struct device_node *np_config; 897 struct device_node *np_config;
949 898
950 ret = of_property_read_string(np, "ste,function", &function); 899 ret = of_property_read_string(np, "ste,function", &function);
951 if (ret >= 0) 900 if (ret >= 0) {
952 reserve = 1; 901 ret = of_property_count_strings(np, "ste,pins");
902 if (ret < 0)
903 goto exit;
904
905 ret = pinctrl_utils_reserve_map(pctldev, map, reserved_maps,
906 num_maps, ret);
907 if (ret < 0)
908 goto exit;
909
910 of_property_for_each_string(np, "ste,pins", prop, group) {
911 ret = abx500_dt_add_map_mux(map, reserved_maps,
912 num_maps, group, function);
913 if (ret < 0)
914 goto exit;
915 }
916 }
953 917
954 ret = pinconf_generic_parse_dt_config(np, &configs, &nconfigs); 918 ret = pinconf_generic_parse_dt_config(np, &configs, &nconfigs);
955 if (nconfigs) 919 if (nconfigs)
956 has_config = 1; 920 has_config = 1;
957
958 np_config = of_parse_phandle(np, "ste,config", 0); 921 np_config = of_parse_phandle(np, "ste,config", 0);
959 if (np_config) { 922 if (np_config) {
960 ret = pinconf_generic_parse_dt_config(np_config, &configs, 923 ret = pinconf_generic_parse_dt_config(np_config, &configs,
@@ -963,28 +926,18 @@ static int abx500_dt_subnode_to_map(struct pinctrl_dev *pctldev,
963 goto exit; 926 goto exit;
964 has_config |= nconfigs; 927 has_config |= nconfigs;
965 } 928 }
929 if (has_config) {
930 ret = of_property_count_strings(np, "ste,pins");
931 if (ret < 0)
932 goto exit;
966 933
967 ret = of_property_count_strings(np, "ste,pins"); 934 ret = pinctrl_utils_reserve_map(pctldev, map,
968 if (ret < 0) 935 reserved_maps,
969 goto exit; 936 num_maps, ret);
970 937 if (ret < 0)
971 if (has_config) 938 goto exit;
972 reserve++;
973
974 reserve *= ret;
975
976 ret = abx500_dt_reserve_map(map, reserved_maps, num_maps, reserve);
977 if (ret < 0)
978 goto exit;
979 939
980 of_property_for_each_string(np, "ste,pins", prop, group) { 940 of_property_for_each_string(np, "ste,pins", prop, group) {
981 if (function) {
982 ret = abx500_dt_add_map_mux(map, reserved_maps,
983 num_maps, group, function);
984 if (ret < 0)
985 goto exit;
986 }
987 if (has_config) {
988 gpio_name = abx500_find_pin_name(pctldev, group); 941 gpio_name = abx500_find_pin_name(pctldev, group);
989 942
990 ret = abx500_dt_add_map_configs(map, reserved_maps, 943 ret = abx500_dt_add_map_configs(map, reserved_maps,
@@ -992,8 +945,8 @@ static int abx500_dt_subnode_to_map(struct pinctrl_dev *pctldev,
992 if (ret < 0) 945 if (ret < 0)
993 goto exit; 946 goto exit;
994 } 947 }
995
996 } 948 }
949
997exit: 950exit:
998 return ret; 951 return ret;
999} 952}
@@ -1014,7 +967,7 @@ static int abx500_dt_node_to_map(struct pinctrl_dev *pctldev,
1014 ret = abx500_dt_subnode_to_map(pctldev, np, map, 967 ret = abx500_dt_subnode_to_map(pctldev, np, map,
1015 &reserved_maps, num_maps); 968 &reserved_maps, num_maps);
1016 if (ret < 0) { 969 if (ret < 0) {
1017 abx500_dt_free_map(pctldev, *map, *num_maps); 970 pinctrl_utils_dt_free_map(pctldev, *map, *num_maps);
1018 return ret; 971 return ret;
1019 } 972 }
1020 } 973 }
@@ -1028,7 +981,7 @@ static const struct pinctrl_ops abx500_pinctrl_ops = {
1028 .get_group_pins = abx500_get_group_pins, 981 .get_group_pins = abx500_get_group_pins,
1029 .pin_dbg_show = abx500_pin_dbg_show, 982 .pin_dbg_show = abx500_pin_dbg_show,
1030 .dt_node_to_map = abx500_dt_node_to_map, 983 .dt_node_to_map = abx500_dt_node_to_map,
1031 .dt_free_map = abx500_dt_free_map, 984 .dt_free_map = pinctrl_utils_dt_free_map,
1032}; 985};
1033 986
1034static int abx500_pin_config_get(struct pinctrl_dev *pctldev, 987static int abx500_pin_config_get(struct pinctrl_dev *pctldev,
@@ -1221,7 +1174,7 @@ static int abx500_gpio_probe(struct platform_device *pdev)
1221 const struct of_device_id *match; 1174 const struct of_device_id *match;
1222 struct abx500_pinctrl *pct; 1175 struct abx500_pinctrl *pct;
1223 unsigned int id = -1; 1176 unsigned int id = -1;
1224 int ret, err; 1177 int ret;
1225 int i; 1178 int i;
1226 1179
1227 if (!np) { 1180 if (!np) {
@@ -1313,10 +1266,7 @@ static int abx500_gpio_probe(struct platform_device *pdev)
1313 return 0; 1266 return 0;
1314 1267
1315out_rem_chip: 1268out_rem_chip:
1316 err = gpiochip_remove(&pct->chip); 1269 gpiochip_remove(&pct->chip);
1317 if (err)
1318 dev_info(&pdev->dev, "failed to remove gpiochip\n");
1319
1320 return ret; 1270 return ret;
1321} 1271}
1322 1272
@@ -1327,15 +1277,8 @@ out_rem_chip:
1327static int abx500_gpio_remove(struct platform_device *pdev) 1277static int abx500_gpio_remove(struct platform_device *pdev)
1328{ 1278{
1329 struct abx500_pinctrl *pct = platform_get_drvdata(pdev); 1279 struct abx500_pinctrl *pct = platform_get_drvdata(pdev);
1330 int ret;
1331
1332 ret = gpiochip_remove(&pct->chip);
1333 if (ret < 0) {
1334 dev_err(pct->dev, "unable to remove gpiochip: %d\n",
1335 ret);
1336 return ret;
1337 }
1338 1280
1281 gpiochip_remove(&pct->chip);
1339 return 0; 1282 return 0;
1340} 1283}
1341 1284
diff --git a/drivers/pinctrl/pinctrl-abx500.h b/drivers/pinctrl/nomadik/pinctrl-abx500.h
index 2beef3bfe9ca..2beef3bfe9ca 100644
--- a/drivers/pinctrl/pinctrl-abx500.h
+++ b/drivers/pinctrl/nomadik/pinctrl-abx500.h
diff --git a/drivers/pinctrl/pinctrl-nomadik-db8500.c b/drivers/pinctrl/nomadik/pinctrl-nomadik-db8500.c
index c74840729648..c74840729648 100644
--- a/drivers/pinctrl/pinctrl-nomadik-db8500.c
+++ b/drivers/pinctrl/nomadik/pinctrl-nomadik-db8500.c
diff --git a/drivers/pinctrl/pinctrl-nomadik-db8540.c b/drivers/pinctrl/nomadik/pinctrl-nomadik-db8540.c
index d7ba5443bae0..d7ba5443bae0 100644
--- a/drivers/pinctrl/pinctrl-nomadik-db8540.c
+++ b/drivers/pinctrl/nomadik/pinctrl-nomadik-db8540.c
diff --git a/drivers/pinctrl/pinctrl-nomadik-stn8815.c b/drivers/pinctrl/nomadik/pinctrl-nomadik-stn8815.c
index ed39dcafd4f8..ed39dcafd4f8 100644
--- a/drivers/pinctrl/pinctrl-nomadik-stn8815.c
+++ b/drivers/pinctrl/nomadik/pinctrl-nomadik-stn8815.c
diff --git a/drivers/pinctrl/pinctrl-nomadik.c b/drivers/pinctrl/nomadik/pinctrl-nomadik.c
index 8f6f16ef73f3..746db6acf648 100644
--- a/drivers/pinctrl/pinctrl-nomadik.c
+++ b/drivers/pinctrl/nomadik/pinctrl-nomadik.c
@@ -31,7 +31,8 @@
31/* Since we request GPIOs from ourself */ 31/* Since we request GPIOs from ourself */
32#include <linux/pinctrl/consumer.h> 32#include <linux/pinctrl/consumer.h>
33#include "pinctrl-nomadik.h" 33#include "pinctrl-nomadik.h"
34#include "core.h" 34#include "../core.h"
35#include "../pinctrl-utils.h"
35 36
36/* 37/*
37 * The GPIO module in the Nomadik family of Systems-on-Chip is an 38 * The GPIO module in the Nomadik family of Systems-on-Chip is an
@@ -985,6 +986,7 @@ static void nmk_gpio_dbg_show_one(struct seq_file *s,
985 container_of(chip, struct nmk_gpio_chip, chip); 986 container_of(chip, struct nmk_gpio_chip, chip);
986 int mode; 987 int mode;
987 bool is_out; 988 bool is_out;
989 bool data_out;
988 bool pull; 990 bool pull;
989 u32 bit = 1 << offset; 991 u32 bit = 1 << offset;
990 const char *modes[] = { 992 const char *modes[] = {
@@ -997,28 +999,41 @@ static void nmk_gpio_dbg_show_one(struct seq_file *s,
997 [NMK_GPIO_ALT_C+3] = "altC3", 999 [NMK_GPIO_ALT_C+3] = "altC3",
998 [NMK_GPIO_ALT_C+4] = "altC4", 1000 [NMK_GPIO_ALT_C+4] = "altC4",
999 }; 1001 };
1002 const char *pulls[] = {
1003 "none ",
1004 "pull down",
1005 "pull up ",
1006 };
1000 1007
1001 clk_enable(nmk_chip->clk); 1008 clk_enable(nmk_chip->clk);
1002 is_out = !!(readl(nmk_chip->addr + NMK_GPIO_DIR) & bit); 1009 is_out = !!(readl(nmk_chip->addr + NMK_GPIO_DIR) & bit);
1003 pull = !(readl(nmk_chip->addr + NMK_GPIO_PDIS) & bit); 1010 pull = !(readl(nmk_chip->addr + NMK_GPIO_PDIS) & bit);
1011 data_out = !!(readl(nmk_chip->addr + NMK_GPIO_DAT) & bit);
1004 mode = nmk_gpio_get_mode(gpio); 1012 mode = nmk_gpio_get_mode(gpio);
1005 if ((mode == NMK_GPIO_ALT_C) && pctldev) 1013 if ((mode == NMK_GPIO_ALT_C) && pctldev)
1006 mode = nmk_prcm_gpiocr_get_mode(pctldev, gpio); 1014 mode = nmk_prcm_gpiocr_get_mode(pctldev, gpio);
1007 1015
1008 seq_printf(s, " gpio-%-3d (%-20.20s) %s %s %s %s", 1016 if (is_out) {
1009 gpio, label ?: "(none)", 1017 seq_printf(s, " gpio-%-3d (%-20.20s) out %s %s",
1010 is_out ? "out" : "in ", 1018 gpio,
1011 chip->get 1019 label ?: "(none)",
1012 ? (chip->get(chip, offset) ? "hi" : "lo") 1020 data_out ? "hi" : "lo",
1013 : "? ", 1021 (mode < 0) ? "unknown" : modes[mode]);
1014 (mode < 0) ? "unknown" : modes[mode], 1022 } else {
1015 pull ? "pull" : "none");
1016
1017 if (!is_out) {
1018 int irq = gpio_to_irq(gpio); 1023 int irq = gpio_to_irq(gpio);
1019 struct irq_desc *desc = irq_to_desc(irq); 1024 struct irq_desc *desc = irq_to_desc(irq);
1025 int pullidx = 0;
1026
1027 if (pull)
1028 pullidx = data_out ? 1 : 2;
1020 1029
1021 /* This races with request_irq(), set_irq_type(), 1030 seq_printf(s, " gpio-%-3d (%-20.20s) in %s %s",
1031 gpio,
1032 label ?: "(none)",
1033 pulls[pullidx],
1034 (mode < 0) ? "unknown" : modes[mode]);
1035 /*
1036 * This races with request_irq(), set_irq_type(),
1022 * and set_irq_wake() ... but those are "rare". 1037 * and set_irq_wake() ... but those are "rare".
1023 */ 1038 */
1024 if (irq > 0 && desc && desc->action) { 1039 if (irq > 0 && desc && desc->action) {
@@ -1261,7 +1276,7 @@ static int nmk_gpio_probe(struct platform_device *dev)
1261 IRQ_TYPE_EDGE_FALLING); 1276 IRQ_TYPE_EDGE_FALLING);
1262 if (ret) { 1277 if (ret) {
1263 dev_err(&dev->dev, "could not add irqchip\n"); 1278 dev_err(&dev->dev, "could not add irqchip\n");
1264 ret = gpiochip_remove(&nmk_chip->chip); 1279 gpiochip_remove(&nmk_chip->chip);
1265 return -ENODEV; 1280 return -ENODEV;
1266 } 1281 }
1267 /* Then register the chain on the parent IRQ */ 1282 /* Then register the chain on the parent IRQ */
@@ -1338,39 +1353,6 @@ static void nmk_pin_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s,
1338 nmk_gpio_dbg_show_one(s, pctldev, chip, offset - chip->base, offset); 1353 nmk_gpio_dbg_show_one(s, pctldev, chip, offset - chip->base, offset);
1339} 1354}
1340 1355
1341static void nmk_pinctrl_dt_free_map(struct pinctrl_dev *pctldev,
1342 struct pinctrl_map *map, unsigned num_maps)
1343{
1344 int i;
1345
1346 for (i = 0; i < num_maps; i++)
1347 if (map[i].type == PIN_MAP_TYPE_CONFIGS_PIN)
1348 kfree(map[i].data.configs.configs);
1349 kfree(map);
1350}
1351
1352static int nmk_dt_reserve_map(struct pinctrl_map **map, unsigned *reserved_maps,
1353 unsigned *num_maps, unsigned reserve)
1354{
1355 unsigned old_num = *reserved_maps;
1356 unsigned new_num = *num_maps + reserve;
1357 struct pinctrl_map *new_map;
1358
1359 if (old_num >= new_num)
1360 return 0;
1361
1362 new_map = krealloc(*map, sizeof(*new_map) * new_num, GFP_KERNEL);
1363 if (!new_map)
1364 return -ENOMEM;
1365
1366 memset(new_map + old_num, 0, (new_num - old_num) * sizeof(*new_map));
1367
1368 *map = new_map;
1369 *reserved_maps = new_num;
1370
1371 return 0;
1372}
1373
1374static int nmk_dt_add_map_mux(struct pinctrl_map **map, unsigned *reserved_maps, 1356static int nmk_dt_add_map_mux(struct pinctrl_map **map, unsigned *reserved_maps,
1375 unsigned *num_maps, const char *group, 1357 unsigned *num_maps, const char *group,
1376 const char *function) 1358 const char *function)
@@ -1537,51 +1519,55 @@ static int nmk_pinctrl_dt_subnode_to_map(struct pinctrl_dev *pctldev,
1537 const char *function = NULL; 1519 const char *function = NULL;
1538 unsigned long configs = 0; 1520 unsigned long configs = 0;
1539 bool has_config = 0; 1521 bool has_config = 0;
1540 unsigned reserve = 0;
1541 struct property *prop; 1522 struct property *prop;
1542 const char *group, *gpio_name; 1523 const char *group, *gpio_name;
1543 struct device_node *np_config; 1524 struct device_node *np_config;
1544 1525
1545 ret = of_property_read_string(np, "ste,function", &function); 1526 ret = of_property_read_string(np, "ste,function", &function);
1546 if (ret >= 0) 1527 if (ret >= 0) {
1547 reserve = 1; 1528 ret = of_property_count_strings(np, "ste,pins");
1548 1529 if (ret < 0)
1549 has_config = nmk_pinctrl_dt_get_config(np, &configs); 1530 goto exit;
1550 1531
1551 np_config = of_parse_phandle(np, "ste,config", 0); 1532 ret = pinctrl_utils_reserve_map(pctldev, map,
1552 if (np_config) 1533 reserved_maps,
1553 has_config |= nmk_pinctrl_dt_get_config(np_config, &configs); 1534 num_maps, ret);
1554 1535 if (ret < 0)
1555 ret = of_property_count_strings(np, "ste,pins"); 1536 goto exit;
1556 if (ret < 0) 1537
1557 goto exit; 1538 of_property_for_each_string(np, "ste,pins", prop, group) {
1558
1559 if (has_config)
1560 reserve++;
1561
1562 reserve *= ret;
1563
1564 ret = nmk_dt_reserve_map(map, reserved_maps, num_maps, reserve);
1565 if (ret < 0)
1566 goto exit;
1567
1568 of_property_for_each_string(np, "ste,pins", prop, group) {
1569 if (function) {
1570 ret = nmk_dt_add_map_mux(map, reserved_maps, num_maps, 1539 ret = nmk_dt_add_map_mux(map, reserved_maps, num_maps,
1571 group, function); 1540 group, function);
1572 if (ret < 0) 1541 if (ret < 0)
1573 goto exit; 1542 goto exit;
1574 } 1543 }
1575 if (has_config) { 1544 }
1545
1546 has_config = nmk_pinctrl_dt_get_config(np, &configs);
1547 np_config = of_parse_phandle(np, "ste,config", 0);
1548 if (np_config)
1549 has_config |= nmk_pinctrl_dt_get_config(np_config, &configs);
1550 if (has_config) {
1551 ret = of_property_count_strings(np, "ste,pins");
1552 if (ret < 0)
1553 goto exit;
1554 ret = pinctrl_utils_reserve_map(pctldev, map,
1555 reserved_maps,
1556 num_maps, ret);
1557 if (ret < 0)
1558 goto exit;
1559
1560 of_property_for_each_string(np, "ste,pins", prop, group) {
1576 gpio_name = nmk_find_pin_name(pctldev, group); 1561 gpio_name = nmk_find_pin_name(pctldev, group);
1577 1562
1578 ret = nmk_dt_add_map_configs(map, reserved_maps, num_maps, 1563 ret = nmk_dt_add_map_configs(map, reserved_maps,
1579 gpio_name, &configs, 1); 1564 num_maps,
1565 gpio_name, &configs, 1);
1580 if (ret < 0) 1566 if (ret < 0)
1581 goto exit; 1567 goto exit;
1582 } 1568 }
1583
1584 } 1569 }
1570
1585exit: 1571exit:
1586 return ret; 1572 return ret;
1587} 1573}
@@ -1602,7 +1588,7 @@ static int nmk_pinctrl_dt_node_to_map(struct pinctrl_dev *pctldev,
1602 ret = nmk_pinctrl_dt_subnode_to_map(pctldev, np, map, 1588 ret = nmk_pinctrl_dt_subnode_to_map(pctldev, np, map,
1603 &reserved_maps, num_maps); 1589 &reserved_maps, num_maps);
1604 if (ret < 0) { 1590 if (ret < 0) {
1605 nmk_pinctrl_dt_free_map(pctldev, *map, *num_maps); 1591 pinctrl_utils_dt_free_map(pctldev, *map, *num_maps);
1606 return ret; 1592 return ret;
1607 } 1593 }
1608 } 1594 }
@@ -1616,7 +1602,7 @@ static const struct pinctrl_ops nmk_pinctrl_ops = {
1616 .get_group_pins = nmk_get_group_pins, 1602 .get_group_pins = nmk_get_group_pins,
1617 .pin_dbg_show = nmk_pin_dbg_show, 1603 .pin_dbg_show = nmk_pin_dbg_show,
1618 .dt_node_to_map = nmk_pinctrl_dt_node_to_map, 1604 .dt_node_to_map = nmk_pinctrl_dt_node_to_map,
1619 .dt_free_map = nmk_pinctrl_dt_free_map, 1605 .dt_free_map = pinctrl_utils_dt_free_map,
1620}; 1606};
1621 1607
1622static int nmk_pmx_get_funcs_cnt(struct pinctrl_dev *pctldev) 1608static int nmk_pmx_get_funcs_cnt(struct pinctrl_dev *pctldev)
@@ -1647,8 +1633,8 @@ static int nmk_pmx_get_func_groups(struct pinctrl_dev *pctldev,
1647 return 0; 1633 return 0;
1648} 1634}
1649 1635
1650static int nmk_pmx_enable(struct pinctrl_dev *pctldev, unsigned function, 1636static int nmk_pmx_set(struct pinctrl_dev *pctldev, unsigned function,
1651 unsigned group) 1637 unsigned group)
1652{ 1638{
1653 struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev); 1639 struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev);
1654 const struct nmk_pingroup *g; 1640 const struct nmk_pingroup *g;
@@ -1765,21 +1751,6 @@ out_glitch:
1765 return ret; 1751 return ret;
1766} 1752}
1767 1753
1768static void nmk_pmx_disable(struct pinctrl_dev *pctldev,
1769 unsigned function, unsigned group)
1770{
1771 struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev);
1772 const struct nmk_pingroup *g;
1773
1774 g = &npct->soc->groups[group];
1775
1776 if (g->altsetting < 0)
1777 return;
1778
1779 /* Poke out the mux, set the pin to some default state? */
1780 dev_dbg(npct->dev, "disable group %s, %u pins\n", g->name, g->npins);
1781}
1782
1783static int nmk_gpio_request_enable(struct pinctrl_dev *pctldev, 1754static int nmk_gpio_request_enable(struct pinctrl_dev *pctldev,
1784 struct pinctrl_gpio_range *range, 1755 struct pinctrl_gpio_range *range,
1785 unsigned offset) 1756 unsigned offset)
@@ -1825,8 +1796,7 @@ static const struct pinmux_ops nmk_pinmux_ops = {
1825 .get_functions_count = nmk_pmx_get_funcs_cnt, 1796 .get_functions_count = nmk_pmx_get_funcs_cnt,
1826 .get_function_name = nmk_pmx_get_func_name, 1797 .get_function_name = nmk_pmx_get_func_name,
1827 .get_function_groups = nmk_pmx_get_func_groups, 1798 .get_function_groups = nmk_pmx_get_func_groups,
1828 .enable = nmk_pmx_enable, 1799 .set_mux = nmk_pmx_set,
1829 .disable = nmk_pmx_disable,
1830 .gpio_request_enable = nmk_gpio_request_enable, 1800 .gpio_request_enable = nmk_gpio_request_enable,
1831 .gpio_disable_free = nmk_gpio_disable_free, 1801 .gpio_disable_free = nmk_gpio_disable_free,
1832}; 1802};
diff --git a/drivers/pinctrl/pinctrl-nomadik.h b/drivers/pinctrl/nomadik/pinctrl-nomadik.h
index d8215f1e70c7..d8215f1e70c7 100644
--- a/drivers/pinctrl/pinctrl-nomadik.h
+++ b/drivers/pinctrl/nomadik/pinctrl-nomadik.h
diff --git a/drivers/pinctrl/pinctrl-adi2.c b/drivers/pinctrl/pinctrl-adi2.c
index 5c44feb54ebb..8434439c5017 100644
--- a/drivers/pinctrl/pinctrl-adi2.c
+++ b/drivers/pinctrl/pinctrl-adi2.c
@@ -401,7 +401,7 @@ static int adi_gpio_irq_type(struct irq_data *d, unsigned int type)
401 401
402 if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING | 402 if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING |
403 IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW)) { 403 IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW)) {
404 snprintf(buf, 16, "gpio-irq%d", irq); 404 snprintf(buf, 16, "gpio-irq%u", irq);
405 port_setup(port, d->hwirq, true); 405 port_setup(port, d->hwirq, true);
406 } else 406 } else
407 goto out; 407 goto out;
@@ -619,8 +619,8 @@ static struct pinctrl_ops adi_pctrl_ops = {
619 .get_group_pins = adi_get_group_pins, 619 .get_group_pins = adi_get_group_pins,
620}; 620};
621 621
622static int adi_pinmux_enable(struct pinctrl_dev *pctldev, unsigned func_id, 622static int adi_pinmux_set(struct pinctrl_dev *pctldev, unsigned func_id,
623 unsigned group_id) 623 unsigned group_id)
624{ 624{
625 struct adi_pinctrl *pinctrl = pinctrl_dev_get_drvdata(pctldev); 625 struct adi_pinctrl *pinctrl = pinctrl_dev_get_drvdata(pctldev);
626 struct gpio_port *port; 626 struct gpio_port *port;
@@ -652,35 +652,6 @@ static int adi_pinmux_enable(struct pinctrl_dev *pctldev, unsigned func_id,
652 return 0; 652 return 0;
653} 653}
654 654
655static void adi_pinmux_disable(struct pinctrl_dev *pctldev, unsigned func_id,
656 unsigned group_id)
657{
658 struct adi_pinctrl *pinctrl = pinctrl_dev_get_drvdata(pctldev);
659 struct gpio_port *port;
660 struct pinctrl_gpio_range *range;
661 unsigned long flags;
662 unsigned short *mux, pin;
663
664 mux = (unsigned short *)pinctrl->soc->groups[group_id].mux;
665
666 while (*mux) {
667 pin = P_IDENT(*mux);
668
669 range = pinctrl_find_gpio_range_from_pin(pctldev, pin);
670 if (range == NULL) /* should not happen */
671 return;
672
673 port = container_of(range->gc, struct gpio_port, chip);
674
675 spin_lock_irqsave(&port->lock, flags);
676
677 port_setup(port, pin_to_offset(range, pin), true);
678 mux++;
679
680 spin_unlock_irqrestore(&port->lock, flags);
681 }
682}
683
684static int adi_pinmux_get_funcs_count(struct pinctrl_dev *pctldev) 655static int adi_pinmux_get_funcs_count(struct pinctrl_dev *pctldev)
685{ 656{
686 struct adi_pinctrl *pinctrl = pinctrl_dev_get_drvdata(pctldev); 657 struct adi_pinctrl *pinctrl = pinctrl_dev_get_drvdata(pctldev);
@@ -727,8 +698,7 @@ static int adi_pinmux_request_gpio(struct pinctrl_dev *pctldev,
727} 698}
728 699
729static struct pinmux_ops adi_pinmux_ops = { 700static struct pinmux_ops adi_pinmux_ops = {
730 .enable = adi_pinmux_enable, 701 .set_mux = adi_pinmux_set,
731 .disable = adi_pinmux_disable,
732 .get_functions_count = adi_pinmux_get_funcs_count, 702 .get_functions_count = adi_pinmux_get_funcs_count,
733 .get_function_name = adi_pinmux_get_func_name, 703 .get_function_name = adi_pinmux_get_func_name,
734 .get_function_groups = adi_pinmux_get_groups, 704 .get_function_groups = adi_pinmux_get_groups,
@@ -979,7 +949,7 @@ static int adi_gpio_probe(struct platform_device *pdev)
979 struct gpio_port *port; 949 struct gpio_port *port;
980 char pinctrl_devname[DEVNAME_SIZE]; 950 char pinctrl_devname[DEVNAME_SIZE];
981 static int gpio; 951 static int gpio;
982 int ret = 0, ret1; 952 int ret = 0;
983 953
984 pdata = dev->platform_data; 954 pdata = dev->platform_data;
985 if (!pdata) 955 if (!pdata)
@@ -1057,7 +1027,7 @@ static int adi_gpio_probe(struct platform_device *pdev)
1057 return 0; 1027 return 0;
1058 1028
1059out_remove_gpiochip: 1029out_remove_gpiochip:
1060 ret1 = gpiochip_remove(&port->chip); 1030 gpiochip_remove(&port->chip);
1061out_remove_domain: 1031out_remove_domain:
1062 if (port->pint) 1032 if (port->pint)
1063 irq_domain_remove(port->domain); 1033 irq_domain_remove(port->domain);
@@ -1068,12 +1038,10 @@ out_remove_domain:
1068static int adi_gpio_remove(struct platform_device *pdev) 1038static int adi_gpio_remove(struct platform_device *pdev)
1069{ 1039{
1070 struct gpio_port *port = platform_get_drvdata(pdev); 1040 struct gpio_port *port = platform_get_drvdata(pdev);
1071 int ret;
1072 u8 offset; 1041 u8 offset;
1073 1042
1074 list_del(&port->node); 1043 list_del(&port->node);
1075 gpiochip_remove_pin_ranges(&port->chip); 1044 gpiochip_remove(&port->chip);
1076 ret = gpiochip_remove(&port->chip);
1077 if (port->pint) { 1045 if (port->pint) {
1078 for (offset = 0; offset < port->width; offset++) 1046 for (offset = 0; offset < port->width; offset++)
1079 irq_dispose_mapping(irq_find_mapping(port->domain, 1047 irq_dispose_mapping(irq_find_mapping(port->domain,
@@ -1081,7 +1049,7 @@ static int adi_gpio_remove(struct platform_device *pdev)
1081 irq_domain_remove(port->domain); 1049 irq_domain_remove(port->domain);
1082 } 1050 }
1083 1051
1084 return ret; 1052 return 0;
1085} 1053}
1086 1054
1087static int adi_pinctrl_probe(struct platform_device *pdev) 1055static int adi_pinctrl_probe(struct platform_device *pdev)
diff --git a/drivers/pinctrl/pinctrl-as3722.c b/drivers/pinctrl/pinctrl-as3722.c
index c862f9c0e9ce..1f790a4b83fe 100644
--- a/drivers/pinctrl/pinctrl-as3722.c
+++ b/drivers/pinctrl/pinctrl-as3722.c
@@ -230,7 +230,7 @@ static int as3722_pinctrl_get_func_groups(struct pinctrl_dev *pctldev,
230 return 0; 230 return 0;
231} 231}
232 232
233static int as3722_pinctrl_enable(struct pinctrl_dev *pctldev, unsigned function, 233static int as3722_pinctrl_set(struct pinctrl_dev *pctldev, unsigned function,
234 unsigned group) 234 unsigned group)
235{ 235{
236 struct as3722_pctrl_info *as_pci = pinctrl_dev_get_drvdata(pctldev); 236 struct as3722_pctrl_info *as_pci = pinctrl_dev_get_drvdata(pctldev);
@@ -327,7 +327,7 @@ static const struct pinmux_ops as3722_pinmux_ops = {
327 .get_functions_count = as3722_pinctrl_get_funcs_count, 327 .get_functions_count = as3722_pinctrl_get_funcs_count,
328 .get_function_name = as3722_pinctrl_get_func_name, 328 .get_function_name = as3722_pinctrl_get_func_name,
329 .get_function_groups = as3722_pinctrl_get_func_groups, 329 .get_function_groups = as3722_pinctrl_get_func_groups,
330 .enable = as3722_pinctrl_enable, 330 .set_mux = as3722_pinctrl_set,
331 .gpio_request_enable = as3722_pinctrl_gpio_request_enable, 331 .gpio_request_enable = as3722_pinctrl_gpio_request_enable,
332 .gpio_set_direction = as3722_pinctrl_gpio_set_direction, 332 .gpio_set_direction = as3722_pinctrl_gpio_set_direction,
333}; 333};
@@ -565,7 +565,6 @@ static int as3722_pinctrl_probe(struct platform_device *pdev)
565{ 565{
566 struct as3722_pctrl_info *as_pci; 566 struct as3722_pctrl_info *as_pci;
567 int ret; 567 int ret;
568 int tret;
569 568
570 as_pci = devm_kzalloc(&pdev->dev, sizeof(*as_pci), GFP_KERNEL); 569 as_pci = devm_kzalloc(&pdev->dev, sizeof(*as_pci), GFP_KERNEL);
571 if (!as_pci) 570 if (!as_pci)
@@ -611,10 +610,7 @@ static int as3722_pinctrl_probe(struct platform_device *pdev)
611 return 0; 610 return 0;
612 611
613fail_range_add: 612fail_range_add:
614 tret = gpiochip_remove(&as_pci->gpio_chip); 613 gpiochip_remove(&as_pci->gpio_chip);
615 if (tret < 0)
616 dev_warn(&pdev->dev, "Couldn't remove gpio chip, %d\n", tret);
617
618fail_chip_add: 614fail_chip_add:
619 pinctrl_unregister(as_pci->pctl); 615 pinctrl_unregister(as_pci->pctl);
620 return ret; 616 return ret;
@@ -623,11 +619,8 @@ fail_chip_add:
623static int as3722_pinctrl_remove(struct platform_device *pdev) 619static int as3722_pinctrl_remove(struct platform_device *pdev)
624{ 620{
625 struct as3722_pctrl_info *as_pci = platform_get_drvdata(pdev); 621 struct as3722_pctrl_info *as_pci = platform_get_drvdata(pdev);
626 int ret;
627 622
628 ret = gpiochip_remove(&as_pci->gpio_chip); 623 gpiochip_remove(&as_pci->gpio_chip);
629 if (ret < 0)
630 return ret;
631 pinctrl_unregister(as_pci->pctl); 624 pinctrl_unregister(as_pci->pctl);
632 return 0; 625 return 0;
633} 626}
diff --git a/drivers/pinctrl/pinctrl-at91.c b/drivers/pinctrl/pinctrl-at91.c
index 421493cb490c..354a81d40925 100644
--- a/drivers/pinctrl/pinctrl-at91.c
+++ b/drivers/pinctrl/pinctrl-at91.c
@@ -58,11 +58,28 @@ static int gpio_banks;
58#define DEGLITCH (1 << 2) 58#define DEGLITCH (1 << 2)
59#define PULL_DOWN (1 << 3) 59#define PULL_DOWN (1 << 3)
60#define DIS_SCHMIT (1 << 4) 60#define DIS_SCHMIT (1 << 4)
61#define DRIVE_STRENGTH_SHIFT 5
62#define DRIVE_STRENGTH_MASK 0x3
63#define DRIVE_STRENGTH (DRIVE_STRENGTH_MASK << DRIVE_STRENGTH_SHIFT)
61#define DEBOUNCE (1 << 16) 64#define DEBOUNCE (1 << 16)
62#define DEBOUNCE_VAL_SHIFT 17 65#define DEBOUNCE_VAL_SHIFT 17
63#define DEBOUNCE_VAL (0x3fff << DEBOUNCE_VAL_SHIFT) 66#define DEBOUNCE_VAL (0x3fff << DEBOUNCE_VAL_SHIFT)
64 67
65/** 68/**
69 * These defines will translated the dt binding settings to our internal
70 * settings. They are not necessarily the same value as the register setting.
71 * The actual drive strength current of low, medium and high must be looked up
72 * from the corresponding device datasheet. This value is different for pins
73 * that are even in the same banks. It is also dependent on VCC.
74 * DRIVE_STRENGTH_DEFAULT is just a placeholder to avoid changing the drive
75 * strength when there is no dt config for it.
76 */
77#define DRIVE_STRENGTH_DEFAULT (0 << DRIVE_STRENGTH_SHIFT)
78#define DRIVE_STRENGTH_LOW (1 << DRIVE_STRENGTH_SHIFT)
79#define DRIVE_STRENGTH_MED (2 << DRIVE_STRENGTH_SHIFT)
80#define DRIVE_STRENGTH_HI (3 << DRIVE_STRENGTH_SHIFT)
81
82/**
66 * struct at91_pmx_func - describes AT91 pinmux functions 83 * struct at91_pmx_func - describes AT91 pinmux functions
67 * @name: the name of this specific function 84 * @name: the name of this specific function
68 * @groups: corresponding pin groups 85 * @groups: corresponding pin groups
@@ -148,6 +165,9 @@ struct at91_pinctrl_mux_ops {
148 void (*set_pulldown)(void __iomem *pio, unsigned mask, bool is_on); 165 void (*set_pulldown)(void __iomem *pio, unsigned mask, bool is_on);
149 bool (*get_schmitt_trig)(void __iomem *pio, unsigned pin); 166 bool (*get_schmitt_trig)(void __iomem *pio, unsigned pin);
150 void (*disable_schmitt_trig)(void __iomem *pio, unsigned mask); 167 void (*disable_schmitt_trig)(void __iomem *pio, unsigned mask);
168 unsigned (*get_drivestrength)(void __iomem *pio, unsigned pin);
169 void (*set_drivestrength)(void __iomem *pio, unsigned pin,
170 u32 strength);
151 /* irq */ 171 /* irq */
152 int (*irq_type)(struct irq_data *d, unsigned type); 172 int (*irq_type)(struct irq_data *d, unsigned type);
153}; 173};
@@ -315,6 +335,30 @@ static unsigned pin_to_mask(unsigned int pin)
315 return 1 << pin; 335 return 1 << pin;
316} 336}
317 337
338static unsigned two_bit_pin_value_shift_amount(unsigned int pin)
339{
340 /* return the shift value for a pin for "two bit" per pin registers,
341 * i.e. drive strength */
342 return 2*((pin >= MAX_NB_GPIO_PER_BANK/2)
343 ? pin - MAX_NB_GPIO_PER_BANK/2 : pin);
344}
345
346static unsigned sama5d3_get_drive_register(unsigned int pin)
347{
348 /* drive strength is split between two registers
349 * with two bits per pin */
350 return (pin >= MAX_NB_GPIO_PER_BANK/2)
351 ? SAMA5D3_PIO_DRIVER2 : SAMA5D3_PIO_DRIVER1;
352}
353
354static unsigned at91sam9x5_get_drive_register(unsigned int pin)
355{
356 /* drive strength is split between two registers
357 * with two bits per pin */
358 return (pin >= MAX_NB_GPIO_PER_BANK/2)
359 ? AT91SAM9X5_PIO_DRIVER2 : AT91SAM9X5_PIO_DRIVER1;
360}
361
318static void at91_mux_disable_interrupt(void __iomem *pio, unsigned mask) 362static void at91_mux_disable_interrupt(void __iomem *pio, unsigned mask)
319{ 363{
320 writel_relaxed(mask, pio + PIO_IDR); 364 writel_relaxed(mask, pio + PIO_IDR);
@@ -327,6 +371,9 @@ static unsigned at91_mux_get_pullup(void __iomem *pio, unsigned pin)
327 371
328static void at91_mux_set_pullup(void __iomem *pio, unsigned mask, bool on) 372static void at91_mux_set_pullup(void __iomem *pio, unsigned mask, bool on)
329{ 373{
374 if (on)
375 writel_relaxed(mask, pio + PIO_PPDDR);
376
330 writel_relaxed(mask, pio + (on ? PIO_PUER : PIO_PUDR)); 377 writel_relaxed(mask, pio + (on ? PIO_PUER : PIO_PUDR));
331} 378}
332 379
@@ -455,6 +502,9 @@ static bool at91_mux_pio3_get_pulldown(void __iomem *pio, unsigned pin)
455 502
456static void at91_mux_pio3_set_pulldown(void __iomem *pio, unsigned mask, bool is_on) 503static void at91_mux_pio3_set_pulldown(void __iomem *pio, unsigned mask, bool is_on)
457{ 504{
505 if (is_on)
506 __raw_writel(mask, pio + PIO_PUDR);
507
458 __raw_writel(mask, pio + (is_on ? PIO_PPDER : PIO_PPDDR)); 508 __raw_writel(mask, pio + (is_on ? PIO_PPDER : PIO_PPDDR));
459} 509}
460 510
@@ -468,6 +518,79 @@ static bool at91_mux_pio3_get_schmitt_trig(void __iomem *pio, unsigned pin)
468 return (__raw_readl(pio + PIO_SCHMITT) >> pin) & 0x1; 518 return (__raw_readl(pio + PIO_SCHMITT) >> pin) & 0x1;
469} 519}
470 520
521static inline u32 read_drive_strength(void __iomem *reg, unsigned pin)
522{
523 unsigned tmp = __raw_readl(reg);
524
525 tmp = tmp >> two_bit_pin_value_shift_amount(pin);
526
527 return tmp & DRIVE_STRENGTH_MASK;
528}
529
530static unsigned at91_mux_sama5d3_get_drivestrength(void __iomem *pio,
531 unsigned pin)
532{
533 unsigned tmp = read_drive_strength(pio +
534 sama5d3_get_drive_register(pin), pin);
535
536 /* SAMA5 strength is 1:1 with our defines,
537 * except 0 is equivalent to low per datasheet */
538 if (!tmp)
539 tmp = DRIVE_STRENGTH_LOW;
540
541 return tmp;
542}
543
544static unsigned at91_mux_sam9x5_get_drivestrength(void __iomem *pio,
545 unsigned pin)
546{
547 unsigned tmp = read_drive_strength(pio +
548 at91sam9x5_get_drive_register(pin), pin);
549
550 /* strength is inverse in SAM9x5s hardware with the pinctrl defines
551 * hardware: 0 = hi, 1 = med, 2 = low, 3 = rsvd */
552 tmp = DRIVE_STRENGTH_HI - tmp;
553
554 return tmp;
555}
556
557static void set_drive_strength(void __iomem *reg, unsigned pin, u32 strength)
558{
559 unsigned tmp = __raw_readl(reg);
560 unsigned shift = two_bit_pin_value_shift_amount(pin);
561
562 tmp &= ~(DRIVE_STRENGTH_MASK << shift);
563 tmp |= strength << shift;
564
565 __raw_writel(tmp, reg);
566}
567
568static void at91_mux_sama5d3_set_drivestrength(void __iomem *pio, unsigned pin,
569 u32 setting)
570{
571 /* do nothing if setting is zero */
572 if (!setting)
573 return;
574
575 /* strength is 1 to 1 with setting for SAMA5 */
576 set_drive_strength(pio + sama5d3_get_drive_register(pin), pin, setting);
577}
578
579static void at91_mux_sam9x5_set_drivestrength(void __iomem *pio, unsigned pin,
580 u32 setting)
581{
582 /* do nothing if setting is zero */
583 if (!setting)
584 return;
585
586 /* strength is inverse on SAM9x5s with our defines
587 * 0 = hi, 1 = med, 2 = low, 3 = rsvd */
588 setting = DRIVE_STRENGTH_HI - setting;
589
590 set_drive_strength(pio + at91sam9x5_get_drive_register(pin), pin,
591 setting);
592}
593
471static struct at91_pinctrl_mux_ops at91rm9200_ops = { 594static struct at91_pinctrl_mux_ops at91rm9200_ops = {
472 .get_periph = at91_mux_get_periph, 595 .get_periph = at91_mux_get_periph,
473 .mux_A_periph = at91_mux_set_A_periph, 596 .mux_A_periph = at91_mux_set_A_periph,
@@ -491,16 +614,37 @@ static struct at91_pinctrl_mux_ops at91sam9x5_ops = {
491 .set_pulldown = at91_mux_pio3_set_pulldown, 614 .set_pulldown = at91_mux_pio3_set_pulldown,
492 .get_schmitt_trig = at91_mux_pio3_get_schmitt_trig, 615 .get_schmitt_trig = at91_mux_pio3_get_schmitt_trig,
493 .disable_schmitt_trig = at91_mux_pio3_disable_schmitt_trig, 616 .disable_schmitt_trig = at91_mux_pio3_disable_schmitt_trig,
617 .get_drivestrength = at91_mux_sam9x5_get_drivestrength,
618 .set_drivestrength = at91_mux_sam9x5_set_drivestrength,
619 .irq_type = alt_gpio_irq_type,
620};
621
622static struct at91_pinctrl_mux_ops sama5d3_ops = {
623 .get_periph = at91_mux_pio3_get_periph,
624 .mux_A_periph = at91_mux_pio3_set_A_periph,
625 .mux_B_periph = at91_mux_pio3_set_B_periph,
626 .mux_C_periph = at91_mux_pio3_set_C_periph,
627 .mux_D_periph = at91_mux_pio3_set_D_periph,
628 .get_deglitch = at91_mux_pio3_get_deglitch,
629 .set_deglitch = at91_mux_pio3_set_deglitch,
630 .get_debounce = at91_mux_pio3_get_debounce,
631 .set_debounce = at91_mux_pio3_set_debounce,
632 .get_pulldown = at91_mux_pio3_get_pulldown,
633 .set_pulldown = at91_mux_pio3_set_pulldown,
634 .get_schmitt_trig = at91_mux_pio3_get_schmitt_trig,
635 .disable_schmitt_trig = at91_mux_pio3_disable_schmitt_trig,
636 .get_drivestrength = at91_mux_sama5d3_get_drivestrength,
637 .set_drivestrength = at91_mux_sama5d3_set_drivestrength,
494 .irq_type = alt_gpio_irq_type, 638 .irq_type = alt_gpio_irq_type,
495}; 639};
496 640
497static void at91_pin_dbg(const struct device *dev, const struct at91_pmx_pin *pin) 641static void at91_pin_dbg(const struct device *dev, const struct at91_pmx_pin *pin)
498{ 642{
499 if (pin->mux) { 643 if (pin->mux) {
500 dev_dbg(dev, "pio%c%d configured as periph%c with conf = 0x%lu\n", 644 dev_dbg(dev, "pio%c%d configured as periph%c with conf = 0x%lx\n",
501 pin->bank + 'A', pin->pin, pin->mux - 1 + 'A', pin->conf); 645 pin->bank + 'A', pin->pin, pin->mux - 1 + 'A', pin->conf);
502 } else { 646 } else {
503 dev_dbg(dev, "pio%c%d configured as gpio with conf = 0x%lu\n", 647 dev_dbg(dev, "pio%c%d configured as gpio with conf = 0x%lx\n",
504 pin->bank + 'A', pin->pin, pin->conf); 648 pin->bank + 'A', pin->pin, pin->conf);
505 } 649 }
506} 650}
@@ -554,8 +698,8 @@ static void at91_mux_gpio_enable(void __iomem *pio, unsigned mask, bool input)
554 writel_relaxed(mask, pio + (input ? PIO_ODR : PIO_OER)); 698 writel_relaxed(mask, pio + (input ? PIO_ODR : PIO_OER));
555} 699}
556 700
557static int at91_pmx_enable(struct pinctrl_dev *pctldev, unsigned selector, 701static int at91_pmx_set(struct pinctrl_dev *pctldev, unsigned selector,
558 unsigned group) 702 unsigned group)
559{ 703{
560 struct at91_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 704 struct at91_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
561 const struct at91_pmx_pin *pins_conf = info->groups[group].pins_conf; 705 const struct at91_pmx_pin *pins_conf = info->groups[group].pins_conf;
@@ -611,26 +755,6 @@ static int at91_pmx_enable(struct pinctrl_dev *pctldev, unsigned selector,
611 return 0; 755 return 0;
612} 756}
613 757
614static void at91_pmx_disable(struct pinctrl_dev *pctldev, unsigned selector,
615 unsigned group)
616{
617 struct at91_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
618 const struct at91_pmx_pin *pins_conf = info->groups[group].pins_conf;
619 const struct at91_pmx_pin *pin;
620 uint32_t npins = info->groups[group].npins;
621 int i;
622 unsigned mask;
623 void __iomem *pio;
624
625 for (i = 0; i < npins; i++) {
626 pin = &pins_conf[i];
627 at91_pin_dbg(info->dev, pin);
628 pio = pin_to_controller(info, pin->bank);
629 mask = pin_to_mask(pin->pin);
630 at91_mux_gpio_enable(pio, mask, 1);
631 }
632}
633
634static int at91_pmx_get_funcs_count(struct pinctrl_dev *pctldev) 758static int at91_pmx_get_funcs_count(struct pinctrl_dev *pctldev)
635{ 759{
636 struct at91_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 760 struct at91_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
@@ -704,8 +828,7 @@ static const struct pinmux_ops at91_pmx_ops = {
704 .get_functions_count = at91_pmx_get_funcs_count, 828 .get_functions_count = at91_pmx_get_funcs_count,
705 .get_function_name = at91_pmx_get_func_name, 829 .get_function_name = at91_pmx_get_func_name,
706 .get_function_groups = at91_pmx_get_groups, 830 .get_function_groups = at91_pmx_get_groups,
707 .enable = at91_pmx_enable, 831 .set_mux = at91_pmx_set,
708 .disable = at91_pmx_disable,
709 .gpio_request_enable = at91_gpio_request_enable, 832 .gpio_request_enable = at91_gpio_request_enable,
710 .gpio_disable_free = at91_gpio_disable_free, 833 .gpio_disable_free = at91_gpio_disable_free,
711}; 834};
@@ -737,6 +860,9 @@ static int at91_pinconf_get(struct pinctrl_dev *pctldev,
737 *config |= PULL_DOWN; 860 *config |= PULL_DOWN;
738 if (info->ops->get_schmitt_trig && info->ops->get_schmitt_trig(pio, pin)) 861 if (info->ops->get_schmitt_trig && info->ops->get_schmitt_trig(pio, pin))
739 *config |= DIS_SCHMIT; 862 *config |= DIS_SCHMIT;
863 if (info->ops->get_drivestrength)
864 *config |= (info->ops->get_drivestrength(pio, pin)
865 << DRIVE_STRENGTH_SHIFT);
740 866
741 return 0; 867 return 0;
742} 868}
@@ -750,6 +876,7 @@ static int at91_pinconf_set(struct pinctrl_dev *pctldev,
750 void __iomem *pio; 876 void __iomem *pio;
751 int i; 877 int i;
752 unsigned long config; 878 unsigned long config;
879 unsigned pin;
753 880
754 for (i = 0; i < num_configs; i++) { 881 for (i = 0; i < num_configs; i++) {
755 config = configs[i]; 882 config = configs[i];
@@ -758,7 +885,8 @@ static int at91_pinconf_set(struct pinctrl_dev *pctldev,
758 "%s:%d, pin_id=%d, config=0x%lx", 885 "%s:%d, pin_id=%d, config=0x%lx",
759 __func__, __LINE__, pin_id, config); 886 __func__, __LINE__, pin_id, config);
760 pio = pin_to_controller(info, pin_to_bank(pin_id)); 887 pio = pin_to_controller(info, pin_to_bank(pin_id));
761 mask = pin_to_mask(pin_id % MAX_NB_GPIO_PER_BANK); 888 pin = pin_id % MAX_NB_GPIO_PER_BANK;
889 mask = pin_to_mask(pin);
762 890
763 if (config & PULL_UP && config & PULL_DOWN) 891 if (config & PULL_UP && config & PULL_DOWN)
764 return -EINVAL; 892 return -EINVAL;
@@ -774,6 +902,10 @@ static int at91_pinconf_set(struct pinctrl_dev *pctldev,
774 info->ops->set_pulldown(pio, mask, config & PULL_DOWN); 902 info->ops->set_pulldown(pio, mask, config & PULL_DOWN);
775 if (info->ops->disable_schmitt_trig && config & DIS_SCHMIT) 903 if (info->ops->disable_schmitt_trig && config & DIS_SCHMIT)
776 info->ops->disable_schmitt_trig(pio, mask); 904 info->ops->disable_schmitt_trig(pio, mask);
905 if (info->ops->set_drivestrength)
906 info->ops->set_drivestrength(pio, pin,
907 (config & DRIVE_STRENGTH)
908 >> DRIVE_STRENGTH_SHIFT);
777 909
778 } /* for each config */ 910 } /* for each config */
779 911
@@ -789,19 +921,31 @@ static int at91_pinconf_set(struct pinctrl_dev *pctldev,
789 } \ 921 } \
790} while (0) 922} while (0)
791 923
924#define DBG_SHOW_FLAG_MASKED(mask,flag) do { \
925 if ((config & mask) == flag) { \
926 if (num_conf) \
927 seq_puts(s, "|"); \
928 seq_puts(s, #flag); \
929 num_conf++; \
930 } \
931} while (0)
932
792static void at91_pinconf_dbg_show(struct pinctrl_dev *pctldev, 933static void at91_pinconf_dbg_show(struct pinctrl_dev *pctldev,
793 struct seq_file *s, unsigned pin_id) 934 struct seq_file *s, unsigned pin_id)
794{ 935{
795 unsigned long config; 936 unsigned long config;
796 int ret, val, num_conf = 0; 937 int val, num_conf = 0;
797 938
798 ret = at91_pinconf_get(pctldev, pin_id, &config); 939 at91_pinconf_get(pctldev, pin_id, &config);
799 940
800 DBG_SHOW_FLAG(MULTI_DRIVE); 941 DBG_SHOW_FLAG(MULTI_DRIVE);
801 DBG_SHOW_FLAG(PULL_UP); 942 DBG_SHOW_FLAG(PULL_UP);
802 DBG_SHOW_FLAG(PULL_DOWN); 943 DBG_SHOW_FLAG(PULL_DOWN);
803 DBG_SHOW_FLAG(DIS_SCHMIT); 944 DBG_SHOW_FLAG(DIS_SCHMIT);
804 DBG_SHOW_FLAG(DEGLITCH); 945 DBG_SHOW_FLAG(DEGLITCH);
946 DBG_SHOW_FLAG_MASKED(DRIVE_STRENGTH, DRIVE_STRENGTH_LOW);
947 DBG_SHOW_FLAG_MASKED(DRIVE_STRENGTH, DRIVE_STRENGTH_MED);
948 DBG_SHOW_FLAG_MASKED(DRIVE_STRENGTH, DRIVE_STRENGTH_HI);
805 DBG_SHOW_FLAG(DEBOUNCE); 949 DBG_SHOW_FLAG(DEBOUNCE);
806 if (config & DEBOUNCE) { 950 if (config & DEBOUNCE) {
807 val = config >> DEBOUNCE_VAL_SHIFT; 951 val = config >> DEBOUNCE_VAL_SHIFT;
@@ -945,7 +1089,7 @@ static int at91_pinctrl_parse_functions(struct device_node *np,
945 /* Initialise function */ 1089 /* Initialise function */
946 func->name = np->name; 1090 func->name = np->name;
947 func->ngroups = of_get_child_count(np); 1091 func->ngroups = of_get_child_count(np);
948 if (func->ngroups <= 0) { 1092 if (func->ngroups == 0) {
949 dev_err(info->dev, "no groups defined\n"); 1093 dev_err(info->dev, "no groups defined\n");
950 return -EINVAL; 1094 return -EINVAL;
951 } 1095 }
@@ -966,6 +1110,7 @@ static int at91_pinctrl_parse_functions(struct device_node *np,
966} 1110}
967 1111
968static struct of_device_id at91_pinctrl_of_match[] = { 1112static struct of_device_id at91_pinctrl_of_match[] = {
1113 { .compatible = "atmel,sama5d3-pinctrl", .data = &sama5d3_ops },
969 { .compatible = "atmel,at91sam9x5-pinctrl", .data = &at91sam9x5_ops }, 1114 { .compatible = "atmel,at91sam9x5-pinctrl", .data = &at91sam9x5_ops },
970 { .compatible = "atmel,at91rm9200-pinctrl", .data = &at91rm9200_ops }, 1115 { .compatible = "atmel,at91rm9200-pinctrl", .data = &at91rm9200_ops },
971 { /* sentinel */ } 1116 { /* sentinel */ }
@@ -1466,7 +1611,7 @@ static void gpio_irq_handler(unsigned irq, struct irq_desc *desc)
1466 /* now it may re-trigger */ 1611 /* now it may re-trigger */
1467} 1612}
1468 1613
1469static int at91_gpio_of_irq_setup(struct device_node *node, 1614static int at91_gpio_of_irq_setup(struct platform_device *pdev,
1470 struct at91_gpio_chip *at91_gpio) 1615 struct at91_gpio_chip *at91_gpio)
1471{ 1616{
1472 struct at91_gpio_chip *prev = NULL; 1617 struct at91_gpio_chip *prev = NULL;
@@ -1491,9 +1636,11 @@ static int at91_gpio_of_irq_setup(struct device_node *node,
1491 0, 1636 0,
1492 handle_edge_irq, 1637 handle_edge_irq,
1493 IRQ_TYPE_EDGE_BOTH); 1638 IRQ_TYPE_EDGE_BOTH);
1494 if (ret) 1639 if (ret) {
1495 panic("at91_gpio.%d: couldn't allocate irq domain (DT).\n", 1640 dev_err(&pdev->dev, "at91_gpio.%d: Couldn't add irqchip to gpiochip.\n",
1496 at91_gpio->pioc_idx); 1641 at91_gpio->pioc_idx);
1642 return ret;
1643 }
1497 1644
1498 /* Setup chained handler */ 1645 /* Setup chained handler */
1499 if (at91_gpio->pioc_idx) 1646 if (at91_gpio->pioc_idx)
@@ -1596,19 +1743,22 @@ static int at91_gpio_probe(struct platform_device *pdev)
1596 at91_chip->pioc_virq = irq; 1743 at91_chip->pioc_virq = irq;
1597 at91_chip->pioc_idx = alias_idx; 1744 at91_chip->pioc_idx = alias_idx;
1598 1745
1599 at91_chip->clock = clk_get(&pdev->dev, NULL); 1746 at91_chip->clock = devm_clk_get(&pdev->dev, NULL);
1600 if (IS_ERR(at91_chip->clock)) { 1747 if (IS_ERR(at91_chip->clock)) {
1601 dev_err(&pdev->dev, "failed to get clock, ignoring.\n"); 1748 dev_err(&pdev->dev, "failed to get clock, ignoring.\n");
1749 ret = PTR_ERR(at91_chip->clock);
1602 goto err; 1750 goto err;
1603 } 1751 }
1604 1752
1605 if (clk_prepare(at91_chip->clock)) 1753 ret = clk_prepare(at91_chip->clock);
1606 goto clk_prep_err; 1754 if (ret)
1755 goto clk_prepare_err;
1607 1756
1608 /* enable PIO controller's clock */ 1757 /* enable PIO controller's clock */
1609 if (clk_enable(at91_chip->clock)) { 1758 ret = clk_enable(at91_chip->clock);
1759 if (ret) {
1610 dev_err(&pdev->dev, "failed to enable clock, ignoring.\n"); 1760 dev_err(&pdev->dev, "failed to enable clock, ignoring.\n");
1611 goto clk_err; 1761 goto clk_enable_err;
1612 } 1762 }
1613 1763
1614 at91_chip->chip = at91_gpio_template; 1764 at91_chip->chip = at91_gpio_template;
@@ -1633,7 +1783,7 @@ static int at91_gpio_probe(struct platform_device *pdev)
1633 1783
1634 if (!names) { 1784 if (!names) {
1635 ret = -ENOMEM; 1785 ret = -ENOMEM;
1636 goto clk_err; 1786 goto clk_enable_err;
1637 } 1787 }
1638 1788
1639 for (i = 0; i < chip->ngpio; i++) 1789 for (i = 0; i < chip->ngpio; i++)
@@ -1651,23 +1801,28 @@ static int at91_gpio_probe(struct platform_device *pdev)
1651 1801
1652 ret = gpiochip_add(chip); 1802 ret = gpiochip_add(chip);
1653 if (ret) 1803 if (ret)
1654 goto clk_err; 1804 goto gpiochip_add_err;
1655 1805
1656 gpio_chips[alias_idx] = at91_chip; 1806 gpio_chips[alias_idx] = at91_chip;
1657 gpio_banks = max(gpio_banks, alias_idx + 1); 1807 gpio_banks = max(gpio_banks, alias_idx + 1);
1658 1808
1659 at91_gpio_probe_fixup(); 1809 at91_gpio_probe_fixup();
1660 1810
1661 at91_gpio_of_irq_setup(np, at91_chip); 1811 ret = at91_gpio_of_irq_setup(pdev, at91_chip);
1812 if (ret)
1813 goto irq_setup_err;
1662 1814
1663 dev_info(&pdev->dev, "at address %p\n", at91_chip->regbase); 1815 dev_info(&pdev->dev, "at address %p\n", at91_chip->regbase);
1664 1816
1665 return 0; 1817 return 0;
1666 1818
1667clk_err: 1819irq_setup_err:
1820 gpiochip_remove(chip);
1821gpiochip_add_err:
1822 clk_disable(at91_chip->clock);
1823clk_enable_err:
1668 clk_unprepare(at91_chip->clock); 1824 clk_unprepare(at91_chip->clock);
1669clk_prep_err: 1825clk_prepare_err:
1670 clk_put(at91_chip->clock);
1671err: 1826err:
1672 dev_err(&pdev->dev, "Failure %i for GPIO %i\n", ret, alias_idx); 1827 dev_err(&pdev->dev, "Failure %i for GPIO %i\n", ret, alias_idx);
1673 1828
diff --git a/drivers/pinctrl/pinctrl-baytrail.c b/drivers/pinctrl/pinctrl-baytrail.c
index 975572e2f260..9dc38140194b 100644
--- a/drivers/pinctrl/pinctrl-baytrail.c
+++ b/drivers/pinctrl/pinctrl-baytrail.c
@@ -25,9 +25,7 @@
25#include <linux/types.h> 25#include <linux/types.h>
26#include <linux/bitops.h> 26#include <linux/bitops.h>
27#include <linux/interrupt.h> 27#include <linux/interrupt.h>
28#include <linux/irq.h>
29#include <linux/gpio.h> 28#include <linux/gpio.h>
30#include <linux/irqdomain.h>
31#include <linux/acpi.h> 29#include <linux/acpi.h>
32#include <linux/platform_device.h> 30#include <linux/platform_device.h>
33#include <linux/seq_file.h> 31#include <linux/seq_file.h>
@@ -44,6 +42,7 @@
44 42
45/* BYT_CONF0_REG register bits */ 43/* BYT_CONF0_REG register bits */
46#define BYT_IODEN BIT(31) 44#define BYT_IODEN BIT(31)
45#define BYT_DIRECT_IRQ_EN BIT(27)
47#define BYT_TRIG_NEG BIT(26) 46#define BYT_TRIG_NEG BIT(26)
48#define BYT_TRIG_POS BIT(25) 47#define BYT_TRIG_POS BIT(25)
49#define BYT_TRIG_LVL BIT(24) 48#define BYT_TRIG_LVL BIT(24)
@@ -137,7 +136,6 @@ static struct pinctrl_gpio_range byt_ranges[] = {
137 136
138struct byt_gpio { 137struct byt_gpio {
139 struct gpio_chip chip; 138 struct gpio_chip chip;
140 struct irq_domain *domain;
141 struct platform_device *pdev; 139 struct platform_device *pdev;
142 spinlock_t lock; 140 spinlock_t lock;
143 void __iomem *reg_base; 141 void __iomem *reg_base;
@@ -217,7 +215,7 @@ static void byt_gpio_free(struct gpio_chip *chip, unsigned offset)
217 215
218static int byt_irq_type(struct irq_data *d, unsigned type) 216static int byt_irq_type(struct irq_data *d, unsigned type)
219{ 217{
220 struct byt_gpio *vg = irq_data_get_irq_chip_data(d); 218 struct byt_gpio *vg = to_byt_gpio(irq_data_get_irq_chip_data(d));
221 u32 offset = irqd_to_hwirq(d); 219 u32 offset = irqd_to_hwirq(d);
222 u32 value; 220 u32 value;
223 unsigned long flags; 221 unsigned long flags;
@@ -229,10 +227,14 @@ static int byt_irq_type(struct irq_data *d, unsigned type)
229 spin_lock_irqsave(&vg->lock, flags); 227 spin_lock_irqsave(&vg->lock, flags);
230 value = readl(reg); 228 value = readl(reg);
231 229
230 WARN(value & BYT_DIRECT_IRQ_EN,
231 "Bad pad config for io mode, force direct_irq_en bit clearing");
232
232 /* For level trigges the BYT_TRIG_POS and BYT_TRIG_NEG bits 233 /* For level trigges the BYT_TRIG_POS and BYT_TRIG_NEG bits
233 * are used to indicate high and low level triggering 234 * are used to indicate high and low level triggering
234 */ 235 */
235 value &= ~(BYT_TRIG_POS | BYT_TRIG_NEG | BYT_TRIG_LVL); 236 value &= ~(BYT_DIRECT_IRQ_EN | BYT_TRIG_POS | BYT_TRIG_NEG |
237 BYT_TRIG_LVL);
236 238
237 switch (type) { 239 switch (type) {
238 case IRQ_TYPE_LEVEL_HIGH: 240 case IRQ_TYPE_LEVEL_HIGH:
@@ -303,14 +305,24 @@ static int byt_gpio_direction_output(struct gpio_chip *chip,
303 unsigned gpio, int value) 305 unsigned gpio, int value)
304{ 306{
305 struct byt_gpio *vg = to_byt_gpio(chip); 307 struct byt_gpio *vg = to_byt_gpio(chip);
308 void __iomem *conf_reg = byt_gpio_reg(chip, gpio, BYT_CONF0_REG);
306 void __iomem *reg = byt_gpio_reg(chip, gpio, BYT_VAL_REG); 309 void __iomem *reg = byt_gpio_reg(chip, gpio, BYT_VAL_REG);
307 unsigned long flags; 310 unsigned long flags;
308 u32 reg_val; 311 u32 reg_val;
309 312
310 spin_lock_irqsave(&vg->lock, flags); 313 spin_lock_irqsave(&vg->lock, flags);
311 314
315 /*
316 * Before making any direction modifications, do a check if gpio
317 * is set for direct IRQ. On baytrail, setting GPIO to output does
318 * not make sense, so let's at least warn the caller before they shoot
319 * themselves in the foot.
320 */
321 WARN(readl(conf_reg) & BYT_DIRECT_IRQ_EN,
322 "Potential Error: Setting GPIO with direct_irq_en to output");
323
312 reg_val = readl(reg) | BYT_DIR_MASK; 324 reg_val = readl(reg) | BYT_DIR_MASK;
313 reg_val &= ~BYT_OUTPUT_EN; 325 reg_val &= ~(BYT_OUTPUT_EN | BYT_INPUT_EN);
314 326
315 if (value) 327 if (value)
316 writel(reg_val | BYT_LEVEL, reg); 328 writel(reg_val | BYT_LEVEL, reg);
@@ -393,16 +405,10 @@ static void byt_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip)
393 spin_unlock_irqrestore(&vg->lock, flags); 405 spin_unlock_irqrestore(&vg->lock, flags);
394} 406}
395 407
396static int byt_gpio_to_irq(struct gpio_chip *chip, unsigned offset)
397{
398 struct byt_gpio *vg = to_byt_gpio(chip);
399 return irq_create_mapping(vg->domain, offset);
400}
401
402static void byt_gpio_irq_handler(unsigned irq, struct irq_desc *desc) 408static void byt_gpio_irq_handler(unsigned irq, struct irq_desc *desc)
403{ 409{
404 struct irq_data *data = irq_desc_get_irq_data(desc); 410 struct irq_data *data = irq_desc_get_irq_data(desc);
405 struct byt_gpio *vg = irq_data_get_irq_handler_data(data); 411 struct byt_gpio *vg = to_byt_gpio(irq_desc_get_handler_data(desc));
406 struct irq_chip *chip = irq_data_get_irq_chip(data); 412 struct irq_chip *chip = irq_data_get_irq_chip(data);
407 u32 base, pin, mask; 413 u32 base, pin, mask;
408 void __iomem *reg; 414 void __iomem *reg;
@@ -421,7 +427,7 @@ static void byt_gpio_irq_handler(unsigned irq, struct irq_desc *desc)
421 /* Clear before handling so we can't lose an edge */ 427 /* Clear before handling so we can't lose an edge */
422 writel(mask, reg); 428 writel(mask, reg);
423 429
424 virq = irq_find_mapping(vg->domain, base + pin); 430 virq = irq_find_mapping(vg->chip.irqdomain, base + pin);
425 generic_handle_irq(virq); 431 generic_handle_irq(virq);
426 432
427 /* In case bios or user sets triggering incorretly a pin 433 /* In case bios or user sets triggering incorretly a pin
@@ -454,33 +460,12 @@ static void byt_irq_mask(struct irq_data *d)
454{ 460{
455} 461}
456 462
457static int byt_irq_reqres(struct irq_data *d)
458{
459 struct byt_gpio *vg = irq_data_get_irq_chip_data(d);
460
461 if (gpio_lock_as_irq(&vg->chip, irqd_to_hwirq(d))) {
462 dev_err(vg->chip.dev,
463 "unable to lock HW IRQ %lu for IRQ\n",
464 irqd_to_hwirq(d));
465 return -EINVAL;
466 }
467 return 0;
468}
469
470static void byt_irq_relres(struct irq_data *d)
471{
472 struct byt_gpio *vg = irq_data_get_irq_chip_data(d);
473
474 gpio_unlock_as_irq(&vg->chip, irqd_to_hwirq(d));
475}
476
477static struct irq_chip byt_irqchip = { 463static struct irq_chip byt_irqchip = {
478 .name = "BYT-GPIO", 464 .name = "BYT-GPIO",
479 .irq_mask = byt_irq_mask, 465 .irq_mask = byt_irq_mask,
480 .irq_unmask = byt_irq_unmask, 466 .irq_unmask = byt_irq_unmask,
481 .irq_set_type = byt_irq_type, 467 .irq_set_type = byt_irq_type,
482 .irq_request_resources = byt_irq_reqres, 468 .flags = IRQCHIP_SKIP_SET_WAKE,
483 .irq_release_resources = byt_irq_relres,
484}; 469};
485 470
486static void byt_gpio_irq_init_hw(struct byt_gpio *vg) 471static void byt_gpio_irq_init_hw(struct byt_gpio *vg)
@@ -501,23 +486,6 @@ static void byt_gpio_irq_init_hw(struct byt_gpio *vg)
501 } 486 }
502} 487}
503 488
504static int byt_gpio_irq_map(struct irq_domain *d, unsigned int virq,
505 irq_hw_number_t hw)
506{
507 struct byt_gpio *vg = d->host_data;
508
509 irq_set_chip_and_handler_name(virq, &byt_irqchip, handle_simple_irq,
510 "demux");
511 irq_set_chip_data(virq, vg);
512 irq_set_irq_type(virq, IRQ_TYPE_NONE);
513
514 return 0;
515}
516
517static const struct irq_domain_ops byt_gpio_irq_ops = {
518 .map = byt_gpio_irq_map,
519};
520
521static int byt_gpio_probe(struct platform_device *pdev) 489static int byt_gpio_probe(struct platform_device *pdev)
522{ 490{
523 struct byt_gpio *vg; 491 struct byt_gpio *vg;
@@ -527,7 +495,6 @@ static int byt_gpio_probe(struct platform_device *pdev)
527 struct acpi_device *acpi_dev; 495 struct acpi_device *acpi_dev;
528 struct pinctrl_gpio_range *range; 496 struct pinctrl_gpio_range *range;
529 acpi_handle handle = ACPI_HANDLE(dev); 497 acpi_handle handle = ACPI_HANDLE(dev);
530 unsigned hwirq;
531 int ret; 498 int ret;
532 499
533 if (acpi_bus_get_device(handle, &acpi_dev)) 500 if (acpi_bus_get_device(handle, &acpi_dev))
@@ -574,27 +541,27 @@ static int byt_gpio_probe(struct platform_device *pdev)
574 gc->can_sleep = false; 541 gc->can_sleep = false;
575 gc->dev = dev; 542 gc->dev = dev;
576 543
544 ret = gpiochip_add(gc);
545 if (ret) {
546 dev_err(&pdev->dev, "failed adding byt-gpio chip\n");
547 return ret;
548 }
549
577 /* set up interrupts */ 550 /* set up interrupts */
578 irq_rc = platform_get_resource(pdev, IORESOURCE_IRQ, 0); 551 irq_rc = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
579 if (irq_rc && irq_rc->start) { 552 if (irq_rc && irq_rc->start) {
580 hwirq = irq_rc->start;
581 gc->to_irq = byt_gpio_to_irq;
582
583 vg->domain = irq_domain_add_linear(NULL, gc->ngpio,
584 &byt_gpio_irq_ops, vg);
585 if (!vg->domain)
586 return -ENXIO;
587
588 byt_gpio_irq_init_hw(vg); 553 byt_gpio_irq_init_hw(vg);
554 ret = gpiochip_irqchip_add(gc, &byt_irqchip, 0,
555 handle_simple_irq, IRQ_TYPE_NONE);
556 if (ret) {
557 dev_err(dev, "failed to add irqchip\n");
558 gpiochip_remove(gc);
559 return ret;
560 }
589 561
590 irq_set_handler_data(hwirq, vg); 562 gpiochip_set_chained_irqchip(gc, &byt_irqchip,
591 irq_set_chained_handler(hwirq, byt_gpio_irq_handler); 563 (unsigned)irq_rc->start,
592 } 564 byt_gpio_irq_handler);
593
594 ret = gpiochip_add(gc);
595 if (ret) {
596 dev_err(&pdev->dev, "failed adding byt-gpio chip\n");
597 return ret;
598 } 565 }
599 566
600 pm_runtime_enable(dev); 567 pm_runtime_enable(dev);
@@ -627,12 +594,9 @@ MODULE_DEVICE_TABLE(acpi, byt_gpio_acpi_match);
627static int byt_gpio_remove(struct platform_device *pdev) 594static int byt_gpio_remove(struct platform_device *pdev)
628{ 595{
629 struct byt_gpio *vg = platform_get_drvdata(pdev); 596 struct byt_gpio *vg = platform_get_drvdata(pdev);
630 int err;
631 597
632 pm_runtime_disable(&pdev->dev); 598 pm_runtime_disable(&pdev->dev);
633 err = gpiochip_remove(&vg->chip); 599 gpiochip_remove(&vg->chip);
634 if (err)
635 dev_warn(&pdev->dev, "failed to remove gpio_chip.\n");
636 600
637 return 0; 601 return 0;
638} 602}
diff --git a/drivers/pinctrl/pinctrl-bcm281xx.c b/drivers/pinctrl/pinctrl-bcm281xx.c
index 3bed792b2c03..a26e0c2ba33e 100644
--- a/drivers/pinctrl/pinctrl-bcm281xx.c
+++ b/drivers/pinctrl/pinctrl-bcm281xx.c
@@ -1055,9 +1055,9 @@ static int bcm281xx_pinctrl_get_fcn_groups(struct pinctrl_dev *pctldev,
1055 return 0; 1055 return 0;
1056} 1056}
1057 1057
1058static int bcm281xx_pinmux_enable(struct pinctrl_dev *pctldev, 1058static int bcm281xx_pinmux_set(struct pinctrl_dev *pctldev,
1059 unsigned function, 1059 unsigned function,
1060 unsigned group) 1060 unsigned group)
1061{ 1061{
1062 struct bcm281xx_pinctrl_data *pdata = pinctrl_dev_get_drvdata(pctldev); 1062 struct bcm281xx_pinctrl_data *pdata = pinctrl_dev_get_drvdata(pctldev);
1063 const struct bcm281xx_pin_function *f = &pdata->functions[function]; 1063 const struct bcm281xx_pin_function *f = &pdata->functions[function];
@@ -1084,7 +1084,7 @@ static struct pinmux_ops bcm281xx_pinctrl_pinmux_ops = {
1084 .get_functions_count = bcm281xx_pinctrl_get_fcns_count, 1084 .get_functions_count = bcm281xx_pinctrl_get_fcns_count,
1085 .get_function_name = bcm281xx_pinctrl_get_fcn_name, 1085 .get_function_name = bcm281xx_pinctrl_get_fcn_name,
1086 .get_function_groups = bcm281xx_pinctrl_get_fcn_groups, 1086 .get_function_groups = bcm281xx_pinctrl_get_fcn_groups,
1087 .enable = bcm281xx_pinmux_enable, 1087 .set_mux = bcm281xx_pinmux_set,
1088}; 1088};
1089 1089
1090static int bcm281xx_pinctrl_pin_config_get(struct pinctrl_dev *pctldev, 1090static int bcm281xx_pinctrl_pin_config_get(struct pinctrl_dev *pctldev,
@@ -1396,7 +1396,7 @@ static struct pinctrl_desc bcm281xx_pinctrl_desc = {
1396 .owner = THIS_MODULE, 1396 .owner = THIS_MODULE,
1397}; 1397};
1398 1398
1399int __init bcm281xx_pinctrl_probe(struct platform_device *pdev) 1399static int __init bcm281xx_pinctrl_probe(struct platform_device *pdev)
1400{ 1400{
1401 struct bcm281xx_pinctrl_data *pdata = &bcm281xx_pinctrl; 1401 struct bcm281xx_pinctrl_data *pdata = &bcm281xx_pinctrl;
1402 struct resource *res; 1402 struct resource *res;
diff --git a/drivers/pinctrl/pinctrl-bcm2835.c b/drivers/pinctrl/pinctrl-bcm2835.c
index 3d907de9bc91..eabba02f71f9 100644
--- a/drivers/pinctrl/pinctrl-bcm2835.c
+++ b/drivers/pinctrl/pinctrl-bcm2835.c
@@ -830,7 +830,7 @@ static int bcm2835_pmx_get_function_groups(struct pinctrl_dev *pctldev,
830 return 0; 830 return 0;
831} 831}
832 832
833static int bcm2835_pmx_enable(struct pinctrl_dev *pctldev, 833static int bcm2835_pmx_set(struct pinctrl_dev *pctldev,
834 unsigned func_selector, 834 unsigned func_selector,
835 unsigned group_selector) 835 unsigned group_selector)
836{ 836{
@@ -841,16 +841,6 @@ static int bcm2835_pmx_enable(struct pinctrl_dev *pctldev,
841 return 0; 841 return 0;
842} 842}
843 843
844static void bcm2835_pmx_disable(struct pinctrl_dev *pctldev,
845 unsigned func_selector,
846 unsigned group_selector)
847{
848 struct bcm2835_pinctrl *pc = pinctrl_dev_get_drvdata(pctldev);
849
850 /* disable by setting to GPIO_IN */
851 bcm2835_pinctrl_fsel_set(pc, group_selector, BCM2835_FSEL_GPIO_IN);
852}
853
854static void bcm2835_pmx_gpio_disable_free(struct pinctrl_dev *pctldev, 844static void bcm2835_pmx_gpio_disable_free(struct pinctrl_dev *pctldev,
855 struct pinctrl_gpio_range *range, 845 struct pinctrl_gpio_range *range,
856 unsigned offset) 846 unsigned offset)
@@ -879,8 +869,7 @@ static const struct pinmux_ops bcm2835_pmx_ops = {
879 .get_functions_count = bcm2835_pmx_get_functions_count, 869 .get_functions_count = bcm2835_pmx_get_functions_count,
880 .get_function_name = bcm2835_pmx_get_function_name, 870 .get_function_name = bcm2835_pmx_get_function_name,
881 .get_function_groups = bcm2835_pmx_get_function_groups, 871 .get_function_groups = bcm2835_pmx_get_function_groups,
882 .enable = bcm2835_pmx_enable, 872 .set_mux = bcm2835_pmx_set,
883 .disable = bcm2835_pmx_disable,
884 .gpio_disable_free = bcm2835_pmx_gpio_disable_free, 873 .gpio_disable_free = bcm2835_pmx_gpio_disable_free,
885 .gpio_set_direction = bcm2835_pmx_gpio_set_direction, 874 .gpio_set_direction = bcm2835_pmx_gpio_set_direction,
886}; 875};
diff --git a/drivers/pinctrl/pinctrl-coh901.c b/drivers/pinctrl/pinctrl-coh901.c
index d182fdd2e715..29cbbab8c3a6 100644
--- a/drivers/pinctrl/pinctrl-coh901.c
+++ b/drivers/pinctrl/pinctrl-coh901.c
@@ -756,8 +756,7 @@ static int __init u300_gpio_probe(struct platform_device *pdev)
756 756
757err_no_range: 757err_no_range:
758err_no_irqchip: 758err_no_irqchip:
759 if (gpiochip_remove(&gpio->chip)) 759 gpiochip_remove(&gpio->chip);
760 dev_err(&pdev->dev, "failed to remove gpio chip\n");
761err_no_chip: 760err_no_chip:
762 clk_disable_unprepare(gpio->clk); 761 clk_disable_unprepare(gpio->clk);
763 dev_err(&pdev->dev, "module ERROR:%d\n", err); 762 dev_err(&pdev->dev, "module ERROR:%d\n", err);
@@ -767,16 +766,11 @@ err_no_chip:
767static int __exit u300_gpio_remove(struct platform_device *pdev) 766static int __exit u300_gpio_remove(struct platform_device *pdev)
768{ 767{
769 struct u300_gpio *gpio = platform_get_drvdata(pdev); 768 struct u300_gpio *gpio = platform_get_drvdata(pdev);
770 int err;
771 769
772 /* Turn off the GPIO block */ 770 /* Turn off the GPIO block */
773 writel(0x00000000U, gpio->base + U300_GPIO_CR); 771 writel(0x00000000U, gpio->base + U300_GPIO_CR);
774 772
775 err = gpiochip_remove(&gpio->chip); 773 gpiochip_remove(&gpio->chip);
776 if (err < 0) {
777 dev_err(gpio->dev, "unable to remove gpiochip: %d\n", err);
778 return err;
779 }
780 clk_disable_unprepare(gpio->clk); 774 clk_disable_unprepare(gpio->clk);
781 return 0; 775 return 0;
782} 776}
diff --git a/drivers/pinctrl/pinctrl-lantiq.c b/drivers/pinctrl/pinctrl-lantiq.c
index d22ca252b80d..296e5b37f768 100644
--- a/drivers/pinctrl/pinctrl-lantiq.c
+++ b/drivers/pinctrl/pinctrl-lantiq.c
@@ -257,9 +257,9 @@ static int match_group_mux(const struct ltq_pin_group *grp,
257 return ret; 257 return ret;
258} 258}
259 259
260static int ltq_pmx_enable(struct pinctrl_dev *pctrldev, 260static int ltq_pmx_set(struct pinctrl_dev *pctrldev,
261 unsigned func, 261 unsigned func,
262 unsigned group) 262 unsigned group)
263{ 263{
264 struct ltq_pinmux_info *info = pinctrl_dev_get_drvdata(pctrldev); 264 struct ltq_pinmux_info *info = pinctrl_dev_get_drvdata(pctrldev);
265 const struct ltq_pin_group *pin_grp = &info->grps[group]; 265 const struct ltq_pin_group *pin_grp = &info->grps[group];
@@ -316,7 +316,7 @@ static const struct pinmux_ops ltq_pmx_ops = {
316 .get_functions_count = ltq_pmx_func_count, 316 .get_functions_count = ltq_pmx_func_count,
317 .get_function_name = ltq_pmx_func_name, 317 .get_function_name = ltq_pmx_func_name,
318 .get_function_groups = ltq_pmx_get_groups, 318 .get_function_groups = ltq_pmx_get_groups,
319 .enable = ltq_pmx_enable, 319 .set_mux = ltq_pmx_set,
320 .gpio_request_enable = ltq_pmx_gpio_request_enable, 320 .gpio_request_enable = ltq_pmx_gpio_request_enable,
321}; 321};
322 322
diff --git a/drivers/pinctrl/pinctrl-palmas.c b/drivers/pinctrl/pinctrl-palmas.c
index f13d0e78a41c..e3079d3d19fe 100644
--- a/drivers/pinctrl/pinctrl-palmas.c
+++ b/drivers/pinctrl/pinctrl-palmas.c
@@ -685,7 +685,8 @@ static int palmas_pinctrl_get_func_groups(struct pinctrl_dev *pctldev,
685 return 0; 685 return 0;
686} 686}
687 687
688static int palmas_pinctrl_enable(struct pinctrl_dev *pctldev, unsigned function, 688static int palmas_pinctrl_set_mux(struct pinctrl_dev *pctldev,
689 unsigned function,
689 unsigned group) 690 unsigned group)
690{ 691{
691 struct palmas_pctrl_chip_info *pci = pinctrl_dev_get_drvdata(pctldev); 692 struct palmas_pctrl_chip_info *pci = pinctrl_dev_get_drvdata(pctldev);
@@ -742,7 +743,7 @@ static const struct pinmux_ops palmas_pinmux_ops = {
742 .get_functions_count = palmas_pinctrl_get_funcs_count, 743 .get_functions_count = palmas_pinctrl_get_funcs_count,
743 .get_function_name = palmas_pinctrl_get_func_name, 744 .get_function_name = palmas_pinctrl_get_func_name,
744 .get_function_groups = palmas_pinctrl_get_func_groups, 745 .get_function_groups = palmas_pinctrl_get_func_groups,
745 .enable = palmas_pinctrl_enable, 746 .set_mux = palmas_pinctrl_set_mux,
746}; 747};
747 748
748static int palmas_pinconf_get(struct pinctrl_dev *pctldev, 749static int palmas_pinconf_get(struct pinctrl_dev *pctldev,
diff --git a/drivers/pinctrl/pinctrl-rockchip.c b/drivers/pinctrl/pinctrl-rockchip.c
index bb805d5e9ff0..016f4578e494 100644
--- a/drivers/pinctrl/pinctrl-rockchip.c
+++ b/drivers/pinctrl/pinctrl-rockchip.c
@@ -62,11 +62,26 @@ enum rockchip_pinctrl_type {
62 RK2928, 62 RK2928,
63 RK3066B, 63 RK3066B,
64 RK3188, 64 RK3188,
65 RK3288,
65}; 66};
66 67
67enum rockchip_pin_bank_type { 68/**
68 COMMON_BANK, 69 * Encode variants of iomux registers into a type variable
69 RK3188_BANK0, 70 */
71#define IOMUX_GPIO_ONLY BIT(0)
72#define IOMUX_WIDTH_4BIT BIT(1)
73#define IOMUX_SOURCE_PMU BIT(2)
74#define IOMUX_UNROUTED BIT(3)
75
76/**
77 * @type: iomux variant using IOMUX_* constants
78 * @offset: if initialized to -1 it will be autocalculated, by specifying
79 * an initial offset value the relevant source offset can be reset
80 * to a new value for autocalculating the following iomux registers.
81 */
82struct rockchip_iomux {
83 int type;
84 int offset;
70}; 85};
71 86
72/** 87/**
@@ -78,6 +93,7 @@ enum rockchip_pin_bank_type {
78 * @nr_pins: number of pins in this bank 93 * @nr_pins: number of pins in this bank
79 * @name: name of the bank 94 * @name: name of the bank
80 * @bank_num: number of the bank, to account for holes 95 * @bank_num: number of the bank, to account for holes
96 * @iomux: array describing the 4 iomux sources of the bank
81 * @valid: are all necessary informations present 97 * @valid: are all necessary informations present
82 * @of_node: dt node of this bank 98 * @of_node: dt node of this bank
83 * @drvdata: common pinctrl basedata 99 * @drvdata: common pinctrl basedata
@@ -95,7 +111,7 @@ struct rockchip_pin_bank {
95 u8 nr_pins; 111 u8 nr_pins;
96 char *name; 112 char *name;
97 u8 bank_num; 113 u8 bank_num;
98 enum rockchip_pin_bank_type bank_type; 114 struct rockchip_iomux iomux[4];
99 bool valid; 115 bool valid;
100 struct device_node *of_node; 116 struct device_node *of_node;
101 struct rockchip_pinctrl *drvdata; 117 struct rockchip_pinctrl *drvdata;
@@ -111,6 +127,25 @@ struct rockchip_pin_bank {
111 .bank_num = id, \ 127 .bank_num = id, \
112 .nr_pins = pins, \ 128 .nr_pins = pins, \
113 .name = label, \ 129 .name = label, \
130 .iomux = { \
131 { .offset = -1 }, \
132 { .offset = -1 }, \
133 { .offset = -1 }, \
134 { .offset = -1 }, \
135 }, \
136 }
137
138#define PIN_BANK_IOMUX_FLAGS(id, pins, label, iom0, iom1, iom2, iom3) \
139 { \
140 .bank_num = id, \
141 .nr_pins = pins, \
142 .name = label, \
143 .iomux = { \
144 { .type = iom0, .offset = -1 }, \
145 { .type = iom1, .offset = -1 }, \
146 { .type = iom2, .offset = -1 }, \
147 { .type = iom3, .offset = -1 }, \
148 }, \
114 } 149 }
115 150
116/** 151/**
@@ -121,7 +156,8 @@ struct rockchip_pin_ctrl {
121 u32 nr_pins; 156 u32 nr_pins;
122 char *label; 157 char *label;
123 enum rockchip_pinctrl_type type; 158 enum rockchip_pinctrl_type type;
124 int mux_offset; 159 int grf_mux_offset;
160 int pmu_mux_offset;
125 void (*pull_calc_reg)(struct rockchip_pin_bank *bank, 161 void (*pull_calc_reg)(struct rockchip_pin_bank *bank,
126 int pin_num, struct regmap **regmap, 162 int pin_num, struct regmap **regmap,
127 int *reg, u8 *bit); 163 int *reg, u8 *bit);
@@ -343,24 +379,42 @@ static const struct pinctrl_ops rockchip_pctrl_ops = {
343static int rockchip_get_mux(struct rockchip_pin_bank *bank, int pin) 379static int rockchip_get_mux(struct rockchip_pin_bank *bank, int pin)
344{ 380{
345 struct rockchip_pinctrl *info = bank->drvdata; 381 struct rockchip_pinctrl *info = bank->drvdata;
382 int iomux_num = (pin / 8);
383 struct regmap *regmap;
346 unsigned int val; 384 unsigned int val;
347 int reg, ret; 385 int reg, ret, mask;
348 u8 bit; 386 u8 bit;
349 387
350 if (bank->bank_type == RK3188_BANK0 && pin < 16) 388 if (iomux_num > 3)
389 return -EINVAL;
390
391 if (bank->iomux[iomux_num].type & IOMUX_UNROUTED) {
392 dev_err(info->dev, "pin %d is unrouted\n", pin);
393 return -EINVAL;
394 }
395
396 if (bank->iomux[iomux_num].type & IOMUX_GPIO_ONLY)
351 return RK_FUNC_GPIO; 397 return RK_FUNC_GPIO;
352 398
399 regmap = (bank->iomux[iomux_num].type & IOMUX_SOURCE_PMU)
400 ? info->regmap_pmu : info->regmap_base;
401
353 /* get basic quadrupel of mux registers and the correct reg inside */ 402 /* get basic quadrupel of mux registers and the correct reg inside */
354 reg = info->ctrl->mux_offset; 403 mask = (bank->iomux[iomux_num].type & IOMUX_WIDTH_4BIT) ? 0xf : 0x3;
355 reg += bank->bank_num * 0x10; 404 reg = bank->iomux[iomux_num].offset;
356 reg += (pin / 8) * 4; 405 if (bank->iomux[iomux_num].type & IOMUX_WIDTH_4BIT) {
357 bit = (pin % 8) * 2; 406 if ((pin % 8) >= 4)
407 reg += 0x4;
408 bit = (pin % 4) * 4;
409 } else {
410 bit = (pin % 8) * 2;
411 }
358 412
359 ret = regmap_read(info->regmap_base, reg, &val); 413 ret = regmap_read(regmap, reg, &val);
360 if (ret) 414 if (ret)
361 return ret; 415 return ret;
362 416
363 return ((val >> bit) & 3); 417 return ((val >> bit) & mask);
364} 418}
365 419
366/* 420/*
@@ -379,16 +433,22 @@ static int rockchip_get_mux(struct rockchip_pin_bank *bank, int pin)
379static int rockchip_set_mux(struct rockchip_pin_bank *bank, int pin, int mux) 433static int rockchip_set_mux(struct rockchip_pin_bank *bank, int pin, int mux)
380{ 434{
381 struct rockchip_pinctrl *info = bank->drvdata; 435 struct rockchip_pinctrl *info = bank->drvdata;
382 int reg, ret; 436 int iomux_num = (pin / 8);
437 struct regmap *regmap;
438 int reg, ret, mask;
383 unsigned long flags; 439 unsigned long flags;
384 u8 bit; 440 u8 bit;
385 u32 data; 441 u32 data, rmask;
386 442
387 /* 443 if (iomux_num > 3)
388 * The first 16 pins of rk3188_bank0 are always gpios and do not have 444 return -EINVAL;
389 * a mux register at all. 445
390 */ 446 if (bank->iomux[iomux_num].type & IOMUX_UNROUTED) {
391 if (bank->bank_type == RK3188_BANK0 && pin < 16) { 447 dev_err(info->dev, "pin %d is unrouted\n", pin);
448 return -EINVAL;
449 }
450
451 if (bank->iomux[iomux_num].type & IOMUX_GPIO_ONLY) {
392 if (mux != RK_FUNC_GPIO) { 452 if (mux != RK_FUNC_GPIO) {
393 dev_err(info->dev, 453 dev_err(info->dev,
394 "pin %d only supports a gpio mux\n", pin); 454 "pin %d only supports a gpio mux\n", pin);
@@ -401,17 +461,26 @@ static int rockchip_set_mux(struct rockchip_pin_bank *bank, int pin, int mux)
401 dev_dbg(info->dev, "setting mux of GPIO%d-%d to %d\n", 461 dev_dbg(info->dev, "setting mux of GPIO%d-%d to %d\n",
402 bank->bank_num, pin, mux); 462 bank->bank_num, pin, mux);
403 463
464 regmap = (bank->iomux[iomux_num].type & IOMUX_SOURCE_PMU)
465 ? info->regmap_pmu : info->regmap_base;
466
404 /* get basic quadrupel of mux registers and the correct reg inside */ 467 /* get basic quadrupel of mux registers and the correct reg inside */
405 reg = info->ctrl->mux_offset; 468 mask = (bank->iomux[iomux_num].type & IOMUX_WIDTH_4BIT) ? 0xf : 0x3;
406 reg += bank->bank_num * 0x10; 469 reg = bank->iomux[iomux_num].offset;
407 reg += (pin / 8) * 4; 470 if (bank->iomux[iomux_num].type & IOMUX_WIDTH_4BIT) {
408 bit = (pin % 8) * 2; 471 if ((pin % 8) >= 4)
472 reg += 0x4;
473 bit = (pin % 4) * 4;
474 } else {
475 bit = (pin % 8) * 2;
476 }
409 477
410 spin_lock_irqsave(&bank->slock, flags); 478 spin_lock_irqsave(&bank->slock, flags);
411 479
412 data = (3 << (bit + 16)); 480 data = (mask << (bit + 16));
413 data |= (mux & 3) << bit; 481 rmask = data | (data >> 16);
414 ret = regmap_write(info->regmap_base, reg, data); 482 data |= (mux & mask) << bit;
483 ret = regmap_update_bits(regmap, reg, rmask, data);
415 484
416 spin_unlock_irqrestore(&bank->slock, flags); 485 spin_unlock_irqrestore(&bank->slock, flags);
417 486
@@ -449,7 +518,7 @@ static void rk3188_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
449 struct rockchip_pinctrl *info = bank->drvdata; 518 struct rockchip_pinctrl *info = bank->drvdata;
450 519
451 /* The first 12 pins of the first bank are located elsewhere */ 520 /* The first 12 pins of the first bank are located elsewhere */
452 if (bank->bank_type == RK3188_BANK0 && pin_num < 12) { 521 if (bank->bank_num == 0 && pin_num < 12) {
453 *regmap = info->regmap_pmu ? info->regmap_pmu 522 *regmap = info->regmap_pmu ? info->regmap_pmu
454 : bank->regmap_pull; 523 : bank->regmap_pull;
455 *reg = info->regmap_pmu ? RK3188_PULL_PMU_OFFSET : 0; 524 *reg = info->regmap_pmu ? RK3188_PULL_PMU_OFFSET : 0;
@@ -476,6 +545,128 @@ static void rk3188_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
476 } 545 }
477} 546}
478 547
548#define RK3288_PULL_OFFSET 0x140
549static void rk3288_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
550 int pin_num, struct regmap **regmap,
551 int *reg, u8 *bit)
552{
553 struct rockchip_pinctrl *info = bank->drvdata;
554
555 /* The first 24 pins of the first bank are located in PMU */
556 if (bank->bank_num == 0) {
557 *regmap = info->regmap_pmu;
558 *reg = RK3188_PULL_PMU_OFFSET;
559
560 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
561 *bit = pin_num % RK3188_PULL_PINS_PER_REG;
562 *bit *= RK3188_PULL_BITS_PER_PIN;
563 } else {
564 *regmap = info->regmap_base;
565 *reg = RK3288_PULL_OFFSET;
566
567 /* correct the offset, as we're starting with the 2nd bank */
568 *reg -= 0x10;
569 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE;
570 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
571
572 *bit = (pin_num % RK3188_PULL_PINS_PER_REG);
573 *bit *= RK3188_PULL_BITS_PER_PIN;
574 }
575}
576
577#define RK3288_DRV_PMU_OFFSET 0x70
578#define RK3288_DRV_GRF_OFFSET 0x1c0
579#define RK3288_DRV_BITS_PER_PIN 2
580#define RK3288_DRV_PINS_PER_REG 8
581#define RK3288_DRV_BANK_STRIDE 16
582static int rk3288_drv_list[] = { 2, 4, 8, 12 };
583
584static void rk3288_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
585 int pin_num, struct regmap **regmap,
586 int *reg, u8 *bit)
587{
588 struct rockchip_pinctrl *info = bank->drvdata;
589
590 /* The first 24 pins of the first bank are located in PMU */
591 if (bank->bank_num == 0) {
592 *regmap = info->regmap_pmu;
593 *reg = RK3288_DRV_PMU_OFFSET;
594
595 *reg += ((pin_num / RK3288_DRV_PINS_PER_REG) * 4);
596 *bit = pin_num % RK3288_DRV_PINS_PER_REG;
597 *bit *= RK3288_DRV_BITS_PER_PIN;
598 } else {
599 *regmap = info->regmap_base;
600 *reg = RK3288_DRV_GRF_OFFSET;
601
602 /* correct the offset, as we're starting with the 2nd bank */
603 *reg -= 0x10;
604 *reg += bank->bank_num * RK3288_DRV_BANK_STRIDE;
605 *reg += ((pin_num / RK3288_DRV_PINS_PER_REG) * 4);
606
607 *bit = (pin_num % RK3288_DRV_PINS_PER_REG);
608 *bit *= RK3288_DRV_BITS_PER_PIN;
609 }
610}
611
612static int rk3288_get_drive(struct rockchip_pin_bank *bank, int pin_num)
613{
614 struct regmap *regmap;
615 int reg, ret;
616 u32 data;
617 u8 bit;
618
619 rk3288_calc_drv_reg_and_bit(bank, pin_num, &regmap, &reg, &bit);
620
621 ret = regmap_read(regmap, reg, &data);
622 if (ret)
623 return ret;
624
625 data >>= bit;
626 data &= (1 << RK3288_DRV_BITS_PER_PIN) - 1;
627
628 return rk3288_drv_list[data];
629}
630
631static int rk3288_set_drive(struct rockchip_pin_bank *bank, int pin_num,
632 int strength)
633{
634 struct rockchip_pinctrl *info = bank->drvdata;
635 struct regmap *regmap;
636 unsigned long flags;
637 int reg, ret, i;
638 u32 data, rmask;
639 u8 bit;
640
641 rk3288_calc_drv_reg_and_bit(bank, pin_num, &regmap, &reg, &bit);
642
643 ret = -EINVAL;
644 for (i = 0; i < ARRAY_SIZE(rk3288_drv_list); i++) {
645 if (rk3288_drv_list[i] == strength) {
646 ret = i;
647 break;
648 }
649 }
650
651 if (ret < 0) {
652 dev_err(info->dev, "unsupported driver strength %d\n",
653 strength);
654 return ret;
655 }
656
657 spin_lock_irqsave(&bank->slock, flags);
658
659 /* enable the write to the equivalent lower bits */
660 data = ((1 << RK3288_DRV_BITS_PER_PIN) - 1) << (bit + 16);
661 rmask = data | (data >> 16);
662 data |= (ret << bit);
663
664 ret = regmap_update_bits(regmap, reg, rmask, data);
665 spin_unlock_irqrestore(&bank->slock, flags);
666
667 return ret;
668}
669
479static int rockchip_get_pull(struct rockchip_pin_bank *bank, int pin_num) 670static int rockchip_get_pull(struct rockchip_pin_bank *bank, int pin_num)
480{ 671{
481 struct rockchip_pinctrl *info = bank->drvdata; 672 struct rockchip_pinctrl *info = bank->drvdata;
@@ -501,6 +692,7 @@ static int rockchip_get_pull(struct rockchip_pin_bank *bank, int pin_num)
501 ? PIN_CONFIG_BIAS_PULL_PIN_DEFAULT 692 ? PIN_CONFIG_BIAS_PULL_PIN_DEFAULT
502 : PIN_CONFIG_BIAS_DISABLE; 693 : PIN_CONFIG_BIAS_DISABLE;
503 case RK3188: 694 case RK3188:
695 case RK3288:
504 data >>= bit; 696 data >>= bit;
505 data &= (1 << RK3188_PULL_BITS_PER_PIN) - 1; 697 data &= (1 << RK3188_PULL_BITS_PER_PIN) - 1;
506 698
@@ -532,7 +724,7 @@ static int rockchip_set_pull(struct rockchip_pin_bank *bank,
532 int reg, ret; 724 int reg, ret;
533 unsigned long flags; 725 unsigned long flags;
534 u8 bit; 726 u8 bit;
535 u32 data; 727 u32 data, rmask;
536 728
537 dev_dbg(info->dev, "setting pull of GPIO%d-%d to %d\n", 729 dev_dbg(info->dev, "setting pull of GPIO%d-%d to %d\n",
538 bank->bank_num, pin_num, pull); 730 bank->bank_num, pin_num, pull);
@@ -555,10 +747,12 @@ static int rockchip_set_pull(struct rockchip_pin_bank *bank,
555 spin_unlock_irqrestore(&bank->slock, flags); 747 spin_unlock_irqrestore(&bank->slock, flags);
556 break; 748 break;
557 case RK3188: 749 case RK3188:
750 case RK3288:
558 spin_lock_irqsave(&bank->slock, flags); 751 spin_lock_irqsave(&bank->slock, flags);
559 752
560 /* enable the write to the equivalent lower bits */ 753 /* enable the write to the equivalent lower bits */
561 data = ((1 << RK3188_PULL_BITS_PER_PIN) - 1) << (bit + 16); 754 data = ((1 << RK3188_PULL_BITS_PER_PIN) - 1) << (bit + 16);
755 rmask = data | (data >> 16);
562 756
563 switch (pull) { 757 switch (pull) {
564 case PIN_CONFIG_BIAS_DISABLE: 758 case PIN_CONFIG_BIAS_DISABLE:
@@ -579,7 +773,7 @@ static int rockchip_set_pull(struct rockchip_pin_bank *bank,
579 return -EINVAL; 773 return -EINVAL;
580 } 774 }
581 775
582 ret = regmap_write(regmap, reg, data); 776 ret = regmap_update_bits(regmap, reg, rmask, data);
583 777
584 spin_unlock_irqrestore(&bank->slock, flags); 778 spin_unlock_irqrestore(&bank->slock, flags);
585 break; 779 break;
@@ -622,8 +816,8 @@ static int rockchip_pmx_get_groups(struct pinctrl_dev *pctldev,
622 return 0; 816 return 0;
623} 817}
624 818
625static int rockchip_pmx_enable(struct pinctrl_dev *pctldev, unsigned selector, 819static int rockchip_pmx_set(struct pinctrl_dev *pctldev, unsigned selector,
626 unsigned group) 820 unsigned group)
627{ 821{
628 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 822 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
629 const unsigned int *pins = info->groups[group].pins; 823 const unsigned int *pins = info->groups[group].pins;
@@ -657,23 +851,6 @@ static int rockchip_pmx_enable(struct pinctrl_dev *pctldev, unsigned selector,
657 return 0; 851 return 0;
658} 852}
659 853
660static void rockchip_pmx_disable(struct pinctrl_dev *pctldev,
661 unsigned selector, unsigned group)
662{
663 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
664 const unsigned int *pins = info->groups[group].pins;
665 struct rockchip_pin_bank *bank;
666 int cnt;
667
668 dev_dbg(info->dev, "disable function %s group %s\n",
669 info->functions[selector].name, info->groups[group].name);
670
671 for (cnt = 0; cnt < info->groups[group].npins; cnt++) {
672 bank = pin_to_bank(info, pins[cnt]);
673 rockchip_set_mux(bank, pins[cnt] - bank->pin_base, 0);
674 }
675}
676
677/* 854/*
678 * The calls to gpio_direction_output() and gpio_direction_input() 855 * The calls to gpio_direction_output() and gpio_direction_input()
679 * leads to this function call (via the pinctrl_gpio_direction_{input|output}() 856 * leads to this function call (via the pinctrl_gpio_direction_{input|output}()
@@ -715,8 +892,7 @@ static const struct pinmux_ops rockchip_pmx_ops = {
715 .get_functions_count = rockchip_pmx_get_funcs_count, 892 .get_functions_count = rockchip_pmx_get_funcs_count,
716 .get_function_name = rockchip_pmx_get_func_name, 893 .get_function_name = rockchip_pmx_get_func_name,
717 .get_function_groups = rockchip_pmx_get_groups, 894 .get_function_groups = rockchip_pmx_get_groups,
718 .enable = rockchip_pmx_enable, 895 .set_mux = rockchip_pmx_set,
719 .disable = rockchip_pmx_disable,
720 .gpio_set_direction = rockchip_pmx_gpio_set_direction, 896 .gpio_set_direction = rockchip_pmx_gpio_set_direction,
721}; 897};
722 898
@@ -734,6 +910,7 @@ static bool rockchip_pinconf_pull_valid(struct rockchip_pin_ctrl *ctrl,
734 case RK3066B: 910 case RK3066B:
735 return pull ? false : true; 911 return pull ? false : true;
736 case RK3188: 912 case RK3188:
913 case RK3288:
737 return (pull != PIN_CONFIG_BIAS_PULL_PIN_DEFAULT); 914 return (pull != PIN_CONFIG_BIAS_PULL_PIN_DEFAULT);
738 } 915 }
739 916
@@ -788,6 +965,15 @@ static int rockchip_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin,
788 if (rc) 965 if (rc)
789 return rc; 966 return rc;
790 break; 967 break;
968 case PIN_CONFIG_DRIVE_STRENGTH:
969 /* rk3288 is the first with per-pin drive-strength */
970 if (info->ctrl->type != RK3288)
971 return -ENOTSUPP;
972
973 rc = rk3288_set_drive(bank, pin - bank->pin_base, arg);
974 if (rc < 0)
975 return rc;
976 break;
791 default: 977 default:
792 return -ENOTSUPP; 978 return -ENOTSUPP;
793 break; 979 break;
@@ -837,6 +1023,17 @@ static int rockchip_pinconf_get(struct pinctrl_dev *pctldev, unsigned int pin,
837 1023
838 arg = rc ? 1 : 0; 1024 arg = rc ? 1 : 0;
839 break; 1025 break;
1026 case PIN_CONFIG_DRIVE_STRENGTH:
1027 /* rk3288 is the first with per-pin drive-strength */
1028 if (info->ctrl->type != RK3288)
1029 return -ENOTSUPP;
1030
1031 rc = rk3288_get_drive(bank, pin - bank->pin_base);
1032 if (rc < 0)
1033 return rc;
1034
1035 arg = rc;
1036 break;
840 default: 1037 default:
841 return -ENOTSUPP; 1038 return -ENOTSUPP;
842 break; 1039 break;
@@ -850,6 +1047,7 @@ static int rockchip_pinconf_get(struct pinctrl_dev *pctldev, unsigned int pin,
850static const struct pinconf_ops rockchip_pinconf_ops = { 1047static const struct pinconf_ops rockchip_pinconf_ops = {
851 .pin_config_get = rockchip_pinconf_get, 1048 .pin_config_get = rockchip_pinconf_get,
852 .pin_config_set = rockchip_pinconf_set, 1049 .pin_config_set = rockchip_pinconf_set,
1050 .is_generic = true,
853}; 1051};
854 1052
855static const struct of_device_id rockchip_bank_match[] = { 1053static const struct of_device_id rockchip_bank_match[] = {
@@ -1414,10 +1612,7 @@ fail:
1414 for (--i, --bank; i >= 0; --i, --bank) { 1612 for (--i, --bank; i >= 0; --i, --bank) {
1415 if (!bank->valid) 1613 if (!bank->valid)
1416 continue; 1614 continue;
1417 1615 gpiochip_remove(&bank->gpio_chip);
1418 if (gpiochip_remove(&bank->gpio_chip))
1419 dev_err(&pdev->dev, "gpio chip %s remove failed\n",
1420 bank->gpio_chip.label);
1421 } 1616 }
1422 return ret; 1617 return ret;
1423} 1618}
@@ -1427,20 +1622,15 @@ static int rockchip_gpiolib_unregister(struct platform_device *pdev,
1427{ 1622{
1428 struct rockchip_pin_ctrl *ctrl = info->ctrl; 1623 struct rockchip_pin_ctrl *ctrl = info->ctrl;
1429 struct rockchip_pin_bank *bank = ctrl->pin_banks; 1624 struct rockchip_pin_bank *bank = ctrl->pin_banks;
1430 int ret = 0;
1431 int i; 1625 int i;
1432 1626
1433 for (i = 0; !ret && i < ctrl->nr_banks; ++i, ++bank) { 1627 for (i = 0; i < ctrl->nr_banks; ++i, ++bank) {
1434 if (!bank->valid) 1628 if (!bank->valid)
1435 continue; 1629 continue;
1436 1630 gpiochip_remove(&bank->gpio_chip);
1437 ret = gpiochip_remove(&bank->gpio_chip);
1438 } 1631 }
1439 1632
1440 if (ret) 1633 return 0;
1441 dev_err(&pdev->dev, "gpio chip remove failed\n");
1442
1443 return ret;
1444} 1634}
1445 1635
1446static int rockchip_get_bank_data(struct rockchip_pin_bank *bank, 1636static int rockchip_get_bank_data(struct rockchip_pin_bank *bank,
@@ -1466,8 +1656,6 @@ static int rockchip_get_bank_data(struct rockchip_pin_bank *bank,
1466 "rockchip,rk3188-gpio-bank0")) { 1656 "rockchip,rk3188-gpio-bank0")) {
1467 struct device_node *node; 1657 struct device_node *node;
1468 1658
1469 bank->bank_type = RK3188_BANK0;
1470
1471 node = of_parse_phandle(bank->of_node->parent, 1659 node = of_parse_phandle(bank->of_node->parent,
1472 "rockchip,pmu", 0); 1660 "rockchip,pmu", 0);
1473 if (!node) { 1661 if (!node) {
@@ -1487,9 +1675,6 @@ static int rockchip_get_bank_data(struct rockchip_pin_bank *bank,
1487 base, 1675 base,
1488 &rockchip_regmap_config); 1676 &rockchip_regmap_config);
1489 } 1677 }
1490
1491 } else {
1492 bank->bank_type = COMMON_BANK;
1493 } 1678 }
1494 1679
1495 bank->irq = irq_of_parse_and_map(bank->of_node, 0); 1680 bank->irq = irq_of_parse_and_map(bank->of_node, 0);
@@ -1513,7 +1698,7 @@ static struct rockchip_pin_ctrl *rockchip_pinctrl_get_soc_data(
1513 struct device_node *np; 1698 struct device_node *np;
1514 struct rockchip_pin_ctrl *ctrl; 1699 struct rockchip_pin_ctrl *ctrl;
1515 struct rockchip_pin_bank *bank; 1700 struct rockchip_pin_bank *bank;
1516 int i; 1701 int grf_offs, pmu_offs, i, j;
1517 1702
1518 match = of_match_node(rockchip_pinctrl_dt_match, node); 1703 match = of_match_node(rockchip_pinctrl_dt_match, node);
1519 ctrl = (struct rockchip_pin_ctrl *)match->data; 1704 ctrl = (struct rockchip_pin_ctrl *)match->data;
@@ -1535,12 +1720,51 @@ static struct rockchip_pin_ctrl *rockchip_pinctrl_get_soc_data(
1535 } 1720 }
1536 } 1721 }
1537 1722
1723 grf_offs = ctrl->grf_mux_offset;
1724 pmu_offs = ctrl->pmu_mux_offset;
1538 bank = ctrl->pin_banks; 1725 bank = ctrl->pin_banks;
1539 for (i = 0; i < ctrl->nr_banks; ++i, ++bank) { 1726 for (i = 0; i < ctrl->nr_banks; ++i, ++bank) {
1727 int bank_pins = 0;
1728
1540 spin_lock_init(&bank->slock); 1729 spin_lock_init(&bank->slock);
1541 bank->drvdata = d; 1730 bank->drvdata = d;
1542 bank->pin_base = ctrl->nr_pins; 1731 bank->pin_base = ctrl->nr_pins;
1543 ctrl->nr_pins += bank->nr_pins; 1732 ctrl->nr_pins += bank->nr_pins;
1733
1734 /* calculate iomux offsets */
1735 for (j = 0; j < 4; j++) {
1736 struct rockchip_iomux *iom = &bank->iomux[j];
1737 int inc;
1738
1739 if (bank_pins >= bank->nr_pins)
1740 break;
1741
1742 /* preset offset value, set new start value */
1743 if (iom->offset >= 0) {
1744 if (iom->type & IOMUX_SOURCE_PMU)
1745 pmu_offs = iom->offset;
1746 else
1747 grf_offs = iom->offset;
1748 } else { /* set current offset */
1749 iom->offset = (iom->type & IOMUX_SOURCE_PMU) ?
1750 pmu_offs : grf_offs;
1751 }
1752
1753 dev_dbg(d->dev, "bank %d, iomux %d has offset 0x%x\n",
1754 i, j, iom->offset);
1755
1756 /*
1757 * Increase offset according to iomux width.
1758 * 4bit iomux'es are spread over two registers.
1759 */
1760 inc = (iom->type & IOMUX_WIDTH_4BIT) ? 8 : 4;
1761 if (iom->type & IOMUX_SOURCE_PMU)
1762 pmu_offs += inc;
1763 else
1764 grf_offs += inc;
1765
1766 bank_pins += 8;
1767 }
1544 } 1768 }
1545 1769
1546 return ctrl; 1770 return ctrl;
@@ -1644,7 +1868,7 @@ static struct rockchip_pin_ctrl rk2928_pin_ctrl = {
1644 .nr_banks = ARRAY_SIZE(rk2928_pin_banks), 1868 .nr_banks = ARRAY_SIZE(rk2928_pin_banks),
1645 .label = "RK2928-GPIO", 1869 .label = "RK2928-GPIO",
1646 .type = RK2928, 1870 .type = RK2928,
1647 .mux_offset = 0xa8, 1871 .grf_mux_offset = 0xa8,
1648 .pull_calc_reg = rk2928_calc_pull_reg_and_bit, 1872 .pull_calc_reg = rk2928_calc_pull_reg_and_bit,
1649}; 1873};
1650 1874
@@ -1662,7 +1886,7 @@ static struct rockchip_pin_ctrl rk3066a_pin_ctrl = {
1662 .nr_banks = ARRAY_SIZE(rk3066a_pin_banks), 1886 .nr_banks = ARRAY_SIZE(rk3066a_pin_banks),
1663 .label = "RK3066a-GPIO", 1887 .label = "RK3066a-GPIO",
1664 .type = RK2928, 1888 .type = RK2928,
1665 .mux_offset = 0xa8, 1889 .grf_mux_offset = 0xa8,
1666 .pull_calc_reg = rk2928_calc_pull_reg_and_bit, 1890 .pull_calc_reg = rk2928_calc_pull_reg_and_bit,
1667}; 1891};
1668 1892
@@ -1678,11 +1902,11 @@ static struct rockchip_pin_ctrl rk3066b_pin_ctrl = {
1678 .nr_banks = ARRAY_SIZE(rk3066b_pin_banks), 1902 .nr_banks = ARRAY_SIZE(rk3066b_pin_banks),
1679 .label = "RK3066b-GPIO", 1903 .label = "RK3066b-GPIO",
1680 .type = RK3066B, 1904 .type = RK3066B,
1681 .mux_offset = 0x60, 1905 .grf_mux_offset = 0x60,
1682}; 1906};
1683 1907
1684static struct rockchip_pin_bank rk3188_pin_banks[] = { 1908static struct rockchip_pin_bank rk3188_pin_banks[] = {
1685 PIN_BANK(0, 32, "gpio0"), 1909 PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", IOMUX_GPIO_ONLY, 0, 0, 0),
1686 PIN_BANK(1, 32, "gpio1"), 1910 PIN_BANK(1, 32, "gpio1"),
1687 PIN_BANK(2, 32, "gpio2"), 1911 PIN_BANK(2, 32, "gpio2"),
1688 PIN_BANK(3, 32, "gpio3"), 1912 PIN_BANK(3, 32, "gpio3"),
@@ -1693,10 +1917,52 @@ static struct rockchip_pin_ctrl rk3188_pin_ctrl = {
1693 .nr_banks = ARRAY_SIZE(rk3188_pin_banks), 1917 .nr_banks = ARRAY_SIZE(rk3188_pin_banks),
1694 .label = "RK3188-GPIO", 1918 .label = "RK3188-GPIO",
1695 .type = RK3188, 1919 .type = RK3188,
1696 .mux_offset = 0x60, 1920 .grf_mux_offset = 0x60,
1697 .pull_calc_reg = rk3188_calc_pull_reg_and_bit, 1921 .pull_calc_reg = rk3188_calc_pull_reg_and_bit,
1698}; 1922};
1699 1923
1924static struct rockchip_pin_bank rk3288_pin_banks[] = {
1925 PIN_BANK_IOMUX_FLAGS(0, 24, "gpio0", IOMUX_SOURCE_PMU,
1926 IOMUX_SOURCE_PMU,
1927 IOMUX_SOURCE_PMU,
1928 IOMUX_UNROUTED
1929 ),
1930 PIN_BANK_IOMUX_FLAGS(1, 32, "gpio1", IOMUX_UNROUTED,
1931 IOMUX_UNROUTED,
1932 IOMUX_UNROUTED,
1933 0
1934 ),
1935 PIN_BANK_IOMUX_FLAGS(2, 32, "gpio2", 0, 0, 0, IOMUX_UNROUTED),
1936 PIN_BANK_IOMUX_FLAGS(3, 32, "gpio3", 0, 0, 0, IOMUX_WIDTH_4BIT),
1937 PIN_BANK_IOMUX_FLAGS(4, 32, "gpio4", IOMUX_WIDTH_4BIT,
1938 IOMUX_WIDTH_4BIT,
1939 0,
1940 0
1941 ),
1942 PIN_BANK_IOMUX_FLAGS(5, 32, "gpio5", IOMUX_UNROUTED,
1943 0,
1944 0,
1945 IOMUX_UNROUTED
1946 ),
1947 PIN_BANK_IOMUX_FLAGS(6, 32, "gpio6", 0, 0, 0, IOMUX_UNROUTED),
1948 PIN_BANK_IOMUX_FLAGS(7, 32, "gpio7", 0,
1949 0,
1950 IOMUX_WIDTH_4BIT,
1951 IOMUX_UNROUTED
1952 ),
1953 PIN_BANK(8, 16, "gpio8"),
1954};
1955
1956static struct rockchip_pin_ctrl rk3288_pin_ctrl = {
1957 .pin_banks = rk3288_pin_banks,
1958 .nr_banks = ARRAY_SIZE(rk3288_pin_banks),
1959 .label = "RK3288-GPIO",
1960 .type = RK3288,
1961 .grf_mux_offset = 0x0,
1962 .pmu_mux_offset = 0x84,
1963 .pull_calc_reg = rk3288_calc_pull_reg_and_bit,
1964};
1965
1700static const struct of_device_id rockchip_pinctrl_dt_match[] = { 1966static const struct of_device_id rockchip_pinctrl_dt_match[] = {
1701 { .compatible = "rockchip,rk2928-pinctrl", 1967 { .compatible = "rockchip,rk2928-pinctrl",
1702 .data = (void *)&rk2928_pin_ctrl }, 1968 .data = (void *)&rk2928_pin_ctrl },
@@ -1706,6 +1972,8 @@ static const struct of_device_id rockchip_pinctrl_dt_match[] = {
1706 .data = (void *)&rk3066b_pin_ctrl }, 1972 .data = (void *)&rk3066b_pin_ctrl },
1707 { .compatible = "rockchip,rk3188-pinctrl", 1973 { .compatible = "rockchip,rk3188-pinctrl",
1708 .data = (void *)&rk3188_pin_ctrl }, 1974 .data = (void *)&rk3188_pin_ctrl },
1975 { .compatible = "rockchip,rk3288-pinctrl",
1976 .data = (void *)&rk3288_pin_ctrl },
1709 {}, 1977 {},
1710}; 1978};
1711MODULE_DEVICE_TABLE(of, rockchip_pinctrl_dt_match); 1979MODULE_DEVICE_TABLE(of, rockchip_pinctrl_dt_match);
diff --git a/drivers/pinctrl/pinctrl-single.c b/drivers/pinctrl/pinctrl-single.c
index 2960557bfed9..fb94b772ad62 100644
--- a/drivers/pinctrl/pinctrl-single.c
+++ b/drivers/pinctrl/pinctrl-single.c
@@ -447,7 +447,7 @@ static int pcs_get_function(struct pinctrl_dev *pctldev, unsigned pin,
447 return 0; 447 return 0;
448} 448}
449 449
450static int pcs_enable(struct pinctrl_dev *pctldev, unsigned fselector, 450static int pcs_set_mux(struct pinctrl_dev *pctldev, unsigned fselector,
451 unsigned group) 451 unsigned group)
452{ 452{
453 struct pcs_device *pcs; 453 struct pcs_device *pcs;
@@ -488,61 +488,6 @@ static int pcs_enable(struct pinctrl_dev *pctldev, unsigned fselector,
488 return 0; 488 return 0;
489} 489}
490 490
491static void pcs_disable(struct pinctrl_dev *pctldev, unsigned fselector,
492 unsigned group)
493{
494 struct pcs_device *pcs;
495 struct pcs_function *func;
496 int i;
497
498 pcs = pinctrl_dev_get_drvdata(pctldev);
499 /* If function mask is null, needn't disable it. */
500 if (!pcs->fmask)
501 return;
502
503 func = radix_tree_lookup(&pcs->ftree, fselector);
504 if (!func) {
505 dev_err(pcs->dev, "%s could not find function%i\n",
506 __func__, fselector);
507 return;
508 }
509
510 /*
511 * Ignore disable if function-off is not specified. Some hardware
512 * does not have clearly defined disable function. For pin specific
513 * off modes, you can use alternate named states as described in
514 * pinctrl-bindings.txt.
515 */
516 if (pcs->foff == PCS_OFF_DISABLED) {
517 dev_dbg(pcs->dev, "ignoring disable for %s function%i\n",
518 func->name, fselector);
519 return;
520 }
521
522 dev_dbg(pcs->dev, "disabling function%i %s\n",
523 fselector, func->name);
524
525 for (i = 0; i < func->nvals; i++) {
526 struct pcs_func_vals *vals;
527 unsigned long flags;
528 unsigned val, mask;
529
530 vals = &func->vals[i];
531 raw_spin_lock_irqsave(&pcs->lock, flags);
532 val = pcs->read(vals->reg);
533
534 if (pcs->bits_per_mux)
535 mask = vals->mask;
536 else
537 mask = pcs->fmask;
538
539 val &= ~mask;
540 val |= pcs->foff << pcs->fshift;
541 pcs->write(val, vals->reg);
542 raw_spin_unlock_irqrestore(&pcs->lock, flags);
543 }
544}
545
546static int pcs_request_gpio(struct pinctrl_dev *pctldev, 491static int pcs_request_gpio(struct pinctrl_dev *pctldev,
547 struct pinctrl_gpio_range *range, unsigned pin) 492 struct pinctrl_gpio_range *range, unsigned pin)
548{ 493{
@@ -574,8 +519,7 @@ static const struct pinmux_ops pcs_pinmux_ops = {
574 .get_functions_count = pcs_get_functions_count, 519 .get_functions_count = pcs_get_functions_count,
575 .get_function_name = pcs_get_function_name, 520 .get_function_name = pcs_get_function_name,
576 .get_function_groups = pcs_get_function_groups, 521 .get_function_groups = pcs_get_function_groups,
577 .enable = pcs_enable, 522 .set_mux = pcs_set_mux,
578 .disable = pcs_disable,
579 .gpio_request_enable = pcs_request_gpio, 523 .gpio_request_enable = pcs_request_gpio,
580}; 524};
581 525
@@ -836,7 +780,7 @@ static int pcs_add_pin(struct pcs_device *pcs, unsigned offset,
836 780
837 pin = &pcs->pins.pa[i]; 781 pin = &pcs->pins.pa[i];
838 pn = &pcs->names[i]; 782 pn = &pcs->names[i];
839 sprintf(pn->name, "%lx.%d", 783 sprintf(pn->name, "%lx.%u",
840 (unsigned long)pcs->res->start + offset, pin_pos); 784 (unsigned long)pcs->res->start + offset, pin_pos);
841 pin->name = pn->name; 785 pin->name = pn->name;
842 pin->number = i; 786 pin->number = i;
@@ -1739,11 +1683,10 @@ static void pcs_irq_chain_handler(unsigned int irq, struct irq_desc *desc)
1739{ 1683{
1740 struct pcs_soc_data *pcs_soc = irq_desc_get_handler_data(desc); 1684 struct pcs_soc_data *pcs_soc = irq_desc_get_handler_data(desc);
1741 struct irq_chip *chip; 1685 struct irq_chip *chip;
1742 int res;
1743 1686
1744 chip = irq_get_chip(irq); 1687 chip = irq_get_chip(irq);
1745 chained_irq_enter(chip, desc); 1688 chained_irq_enter(chip, desc);
1746 res = pcs_irq_handle(pcs_soc); 1689 pcs_irq_handle(pcs_soc);
1747 /* REVISIT: export and add handle_bad_irq(irq, desc)? */ 1690 /* REVISIT: export and add handle_bad_irq(irq, desc)? */
1748 chained_irq_exit(chip, desc); 1691 chained_irq_exit(chip, desc);
1749 1692
@@ -2038,6 +1981,18 @@ static const struct pcs_soc_data pinctrl_single_omap_wkup = {
2038 .irq_status_mask = (1 << 15), /* OMAP_WAKEUP_EVENT */ 1981 .irq_status_mask = (1 << 15), /* OMAP_WAKEUP_EVENT */
2039}; 1982};
2040 1983
1984static const struct pcs_soc_data pinctrl_single_dra7 = {
1985 .flags = PCS_QUIRK_SHARED_IRQ,
1986 .irq_enable_mask = (1 << 24), /* WAKEUPENABLE */
1987 .irq_status_mask = (1 << 25), /* WAKEUPEVENT */
1988};
1989
1990static const struct pcs_soc_data pinctrl_single_am437x = {
1991 .flags = PCS_QUIRK_SHARED_IRQ,
1992 .irq_enable_mask = (1 << 29), /* OMAP_WAKEUP_EN */
1993 .irq_status_mask = (1 << 30), /* OMAP_WAKEUP_EVENT */
1994};
1995
2041static const struct pcs_soc_data pinctrl_single = { 1996static const struct pcs_soc_data pinctrl_single = {
2042}; 1997};
2043 1998
@@ -2049,6 +2004,8 @@ static struct of_device_id pcs_of_match[] = {
2049 { .compatible = "ti,omap3-padconf", .data = &pinctrl_single_omap_wkup }, 2004 { .compatible = "ti,omap3-padconf", .data = &pinctrl_single_omap_wkup },
2050 { .compatible = "ti,omap4-padconf", .data = &pinctrl_single_omap_wkup }, 2005 { .compatible = "ti,omap4-padconf", .data = &pinctrl_single_omap_wkup },
2051 { .compatible = "ti,omap5-padconf", .data = &pinctrl_single_omap_wkup }, 2006 { .compatible = "ti,omap5-padconf", .data = &pinctrl_single_omap_wkup },
2007 { .compatible = "ti,dra7-padconf", .data = &pinctrl_single_dra7 },
2008 { .compatible = "ti,am437-padconf", .data = &pinctrl_single_am437x },
2052 { .compatible = "pinctrl-single", .data = &pinctrl_single }, 2009 { .compatible = "pinctrl-single", .data = &pinctrl_single },
2053 { .compatible = "pinconf-single", .data = &pinconf_single }, 2010 { .compatible = "pinconf-single", .data = &pinconf_single },
2054 { }, 2011 { },
diff --git a/drivers/pinctrl/pinctrl-st.c b/drivers/pinctrl/pinctrl-st.c
index 9f43916637ca..4b1792aad3d8 100644
--- a/drivers/pinctrl/pinctrl-st.c
+++ b/drivers/pinctrl/pinctrl-st.c
@@ -914,8 +914,8 @@ static struct st_pio_control *st_get_pio_control(
914 return &bank->pc; 914 return &bank->pc;
915} 915}
916 916
917static int st_pmx_enable(struct pinctrl_dev *pctldev, unsigned fselector, 917static int st_pmx_set_mux(struct pinctrl_dev *pctldev, unsigned fselector,
918 unsigned group) 918 unsigned group)
919{ 919{
920 struct st_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 920 struct st_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
921 struct st_pinconf *conf = info->groups[group].pin_conf; 921 struct st_pinconf *conf = info->groups[group].pin_conf;
@@ -930,11 +930,6 @@ static int st_pmx_enable(struct pinctrl_dev *pctldev, unsigned fselector,
930 return 0; 930 return 0;
931} 931}
932 932
933static void st_pmx_disable(struct pinctrl_dev *pctldev, unsigned selector,
934 unsigned group)
935{
936}
937
938static int st_pmx_set_gpio_direction(struct pinctrl_dev *pctldev, 933static int st_pmx_set_gpio_direction(struct pinctrl_dev *pctldev,
939 struct pinctrl_gpio_range *range, unsigned gpio, 934 struct pinctrl_gpio_range *range, unsigned gpio,
940 bool input) 935 bool input)
@@ -956,8 +951,7 @@ static struct pinmux_ops st_pmxops = {
956 .get_functions_count = st_pmx_get_funcs_count, 951 .get_functions_count = st_pmx_get_funcs_count,
957 .get_function_name = st_pmx_get_fname, 952 .get_function_name = st_pmx_get_fname,
958 .get_function_groups = st_pmx_get_groups, 953 .get_function_groups = st_pmx_get_groups,
959 .enable = st_pmx_enable, 954 .set_mux = st_pmx_set_mux,
960 .disable = st_pmx_disable,
961 .gpio_set_direction = st_pmx_set_gpio_direction, 955 .gpio_set_direction = st_pmx_set_gpio_direction,
962}; 956};
963 957
@@ -1178,9 +1172,7 @@ static int st_pctl_dt_parse_groups(struct device_node *np,
1178 const __be32 *list; 1172 const __be32 *list;
1179 struct property *pp; 1173 struct property *pp;
1180 struct st_pinconf *conf; 1174 struct st_pinconf *conf;
1181 phandle phandle;
1182 struct device_node *pins; 1175 struct device_node *pins;
1183 u32 pin;
1184 int i = 0, npins = 0, nr_props; 1176 int i = 0, npins = 0, nr_props;
1185 1177
1186 pins = of_get_child_by_name(np, "st,pins"); 1178 pins = of_get_child_by_name(np, "st,pins");
@@ -1218,8 +1210,8 @@ static int st_pctl_dt_parse_groups(struct device_node *np,
1218 conf = &grp->pin_conf[i]; 1210 conf = &grp->pin_conf[i];
1219 1211
1220 /* bank & offset */ 1212 /* bank & offset */
1221 phandle = be32_to_cpup(list++); 1213 be32_to_cpup(list++);
1222 pin = be32_to_cpup(list++); 1214 be32_to_cpup(list++);
1223 conf->pin = of_get_named_gpio(pins, pp->name, 0); 1215 conf->pin = of_get_named_gpio(pins, pp->name, 0);
1224 conf->name = pp->name; 1216 conf->name = pp->name;
1225 grp->pins[i] = conf->pin; 1217 grp->pins[i] = conf->pin;
@@ -1256,7 +1248,7 @@ static int st_pctl_parse_functions(struct device_node *np,
1256 func = &info->functions[index]; 1248 func = &info->functions[index];
1257 func->name = np->name; 1249 func->name = np->name;
1258 func->ngroups = of_get_child_count(np); 1250 func->ngroups = of_get_child_count(np);
1259 if (func->ngroups <= 0) { 1251 if (func->ngroups == 0) {
1260 dev_err(info->dev, "No groups defined\n"); 1252 dev_err(info->dev, "No groups defined\n");
1261 return -EINVAL; 1253 return -EINVAL;
1262 } 1254 }
@@ -1454,6 +1446,7 @@ static struct irq_chip st_gpio_irqchip = {
1454 .irq_mask = st_gpio_irq_mask, 1446 .irq_mask = st_gpio_irq_mask,
1455 .irq_unmask = st_gpio_irq_unmask, 1447 .irq_unmask = st_gpio_irq_unmask,
1456 .irq_set_type = st_gpio_irq_set_type, 1448 .irq_set_type = st_gpio_irq_set_type,
1449 .flags = IRQCHIP_SKIP_SET_WAKE,
1457}; 1450};
1458 1451
1459static int st_gpiolib_register_bank(struct st_pinctrl *info, 1452static int st_gpiolib_register_bank(struct st_pinctrl *info,
@@ -1524,6 +1517,7 @@ static int st_gpiolib_register_bank(struct st_pinctrl *info,
1524 0, handle_simple_irq, 1517 0, handle_simple_irq,
1525 IRQ_TYPE_LEVEL_LOW); 1518 IRQ_TYPE_LEVEL_LOW);
1526 if (err) { 1519 if (err) {
1520 gpiochip_remove(&bank->gpio_chip);
1527 dev_info(dev, "could not add irqchip\n"); 1521 dev_info(dev, "could not add irqchip\n");
1528 return err; 1522 return err;
1529 } 1523 }
diff --git a/drivers/pinctrl/pinctrl-tb10x.c b/drivers/pinctrl/pinctrl-tb10x.c
index 26ca6855f478..3b9bfcf717ac 100644
--- a/drivers/pinctrl/pinctrl-tb10x.c
+++ b/drivers/pinctrl/pinctrl-tb10x.c
@@ -697,7 +697,7 @@ static void tb10x_gpio_disable_free(struct pinctrl_dev *pctl,
697 mutex_unlock(&state->mutex); 697 mutex_unlock(&state->mutex);
698} 698}
699 699
700static int tb10x_pctl_enable(struct pinctrl_dev *pctl, 700static int tb10x_pctl_set_mux(struct pinctrl_dev *pctl,
701 unsigned func_selector, unsigned group_selector) 701 unsigned func_selector, unsigned group_selector)
702{ 702{
703 struct tb10x_pinctrl *state = pinctrl_dev_get_drvdata(pctl); 703 struct tb10x_pinctrl *state = pinctrl_dev_get_drvdata(pctl);
@@ -738,30 +738,13 @@ static int tb10x_pctl_enable(struct pinctrl_dev *pctl,
738 return 0; 738 return 0;
739} 739}
740 740
741static void tb10x_pctl_disable(struct pinctrl_dev *pctl,
742 unsigned func_selector, unsigned group_selector)
743{
744 struct tb10x_pinctrl *state = pinctrl_dev_get_drvdata(pctl);
745 const struct tb10x_pinfuncgrp *grp = &state->pingroups[group_selector];
746
747 if (grp->port < 0)
748 return;
749
750 mutex_lock(&state->mutex);
751
752 state->ports[grp->port].count--;
753
754 mutex_unlock(&state->mutex);
755}
756
757static struct pinmux_ops tb10x_pinmux_ops = { 741static struct pinmux_ops tb10x_pinmux_ops = {
758 .get_functions_count = tb10x_get_functions_count, 742 .get_functions_count = tb10x_get_functions_count,
759 .get_function_name = tb10x_get_function_name, 743 .get_function_name = tb10x_get_function_name,
760 .get_function_groups = tb10x_get_function_groups, 744 .get_function_groups = tb10x_get_function_groups,
761 .gpio_request_enable = tb10x_gpio_request_enable, 745 .gpio_request_enable = tb10x_gpio_request_enable,
762 .gpio_disable_free = tb10x_gpio_disable_free, 746 .gpio_disable_free = tb10x_gpio_disable_free,
763 .enable = tb10x_pctl_enable, 747 .set_mux = tb10x_pctl_set_mux,
764 .disable = tb10x_pctl_disable,
765}; 748};
766 749
767static struct pinctrl_desc tb10x_pindesc = { 750static struct pinctrl_desc tb10x_pindesc = {
diff --git a/drivers/pinctrl/pinctrl-tegra-xusb.c b/drivers/pinctrl/pinctrl-tegra-xusb.c
new file mode 100644
index 000000000000..1631ec94fb02
--- /dev/null
+++ b/drivers/pinctrl/pinctrl-tegra-xusb.c
@@ -0,0 +1,974 @@
1/*
2 * Copyright (c) 2014, NVIDIA CORPORATION. All rights reserved.
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
11 * more details.
12 */
13
14#include <linux/delay.h>
15#include <linux/io.h>
16#include <linux/module.h>
17#include <linux/of.h>
18#include <linux/phy/phy.h>
19#include <linux/pinctrl/pinctrl.h>
20#include <linux/pinctrl/pinmux.h>
21#include <linux/platform_device.h>
22#include <linux/reset.h>
23
24#include <dt-bindings/pinctrl/pinctrl-tegra-xusb.h>
25
26#include "core.h"
27#include "pinctrl-utils.h"
28
29#define XUSB_PADCTL_ELPG_PROGRAM 0x01c
30#define XUSB_PADCTL_ELPG_PROGRAM_AUX_MUX_LP0_VCORE_DOWN (1 << 26)
31#define XUSB_PADCTL_ELPG_PROGRAM_AUX_MUX_LP0_CLAMP_EN_EARLY (1 << 25)
32#define XUSB_PADCTL_ELPG_PROGRAM_AUX_MUX_LP0_CLAMP_EN (1 << 24)
33
34#define XUSB_PADCTL_IOPHY_PLL_P0_CTL1 0x040
35#define XUSB_PADCTL_IOPHY_PLL_P0_CTL1_PLL0_LOCKDET (1 << 19)
36#define XUSB_PADCTL_IOPHY_PLL_P0_CTL1_REFCLK_SEL_MASK (0xf << 12)
37#define XUSB_PADCTL_IOPHY_PLL_P0_CTL1_PLL_RST (1 << 1)
38
39#define XUSB_PADCTL_IOPHY_PLL_P0_CTL2 0x044
40#define XUSB_PADCTL_IOPHY_PLL_P0_CTL2_REFCLKBUF_EN (1 << 6)
41#define XUSB_PADCTL_IOPHY_PLL_P0_CTL2_TXCLKREF_EN (1 << 5)
42#define XUSB_PADCTL_IOPHY_PLL_P0_CTL2_TXCLKREF_SEL (1 << 4)
43
44#define XUSB_PADCTL_IOPHY_PLL_S0_CTL1 0x138
45#define XUSB_PADCTL_IOPHY_PLL_S0_CTL1_PLL1_LOCKDET (1 << 27)
46#define XUSB_PADCTL_IOPHY_PLL_S0_CTL1_PLL1_MODE (1 << 24)
47#define XUSB_PADCTL_IOPHY_PLL_S0_CTL1_PLL_PWR_OVRD (1 << 3)
48#define XUSB_PADCTL_IOPHY_PLL_S0_CTL1_PLL_RST (1 << 1)
49#define XUSB_PADCTL_IOPHY_PLL_S0_CTL1_PLL_IDDQ (1 << 0)
50
51#define XUSB_PADCTL_IOPHY_MISC_PAD_S0_CTL1 0x148
52#define XUSB_PADCTL_IOPHY_MISC_PAD_S0_CTL1_IDDQ_OVRD (1 << 1)
53#define XUSB_PADCTL_IOPHY_MISC_PAD_S0_CTL1_IDDQ (1 << 0)
54
55struct tegra_xusb_padctl_function {
56 const char *name;
57 const char * const *groups;
58 unsigned int num_groups;
59};
60
61struct tegra_xusb_padctl_group {
62 const unsigned int *funcs;
63 unsigned int num_funcs;
64};
65
66struct tegra_xusb_padctl_soc {
67 const struct pinctrl_pin_desc *pins;
68 unsigned int num_pins;
69
70 const struct tegra_xusb_padctl_function *functions;
71 unsigned int num_functions;
72
73 const struct tegra_xusb_padctl_lane *lanes;
74 unsigned int num_lanes;
75};
76
77struct tegra_xusb_padctl_lane {
78 const char *name;
79
80 unsigned int offset;
81 unsigned int shift;
82 unsigned int mask;
83 unsigned int iddq;
84
85 const unsigned int *funcs;
86 unsigned int num_funcs;
87};
88
89struct tegra_xusb_padctl {
90 struct device *dev;
91 void __iomem *regs;
92 struct mutex lock;
93 struct reset_control *rst;
94
95 const struct tegra_xusb_padctl_soc *soc;
96 struct pinctrl_dev *pinctrl;
97 struct pinctrl_desc desc;
98
99 struct phy_provider *provider;
100 struct phy *phys[2];
101
102 unsigned int enable;
103};
104
105static inline void padctl_writel(struct tegra_xusb_padctl *padctl, u32 value,
106 unsigned long offset)
107{
108 writel(value, padctl->regs + offset);
109}
110
111static inline u32 padctl_readl(struct tegra_xusb_padctl *padctl,
112 unsigned long offset)
113{
114 return readl(padctl->regs + offset);
115}
116
117static int tegra_xusb_padctl_get_groups_count(struct pinctrl_dev *pinctrl)
118{
119 struct tegra_xusb_padctl *padctl = pinctrl_dev_get_drvdata(pinctrl);
120
121 return padctl->soc->num_pins;
122}
123
124static const char *tegra_xusb_padctl_get_group_name(struct pinctrl_dev *pinctrl,
125 unsigned int group)
126{
127 struct tegra_xusb_padctl *padctl = pinctrl_dev_get_drvdata(pinctrl);
128
129 return padctl->soc->pins[group].name;
130}
131
132enum tegra_xusb_padctl_param {
133 TEGRA_XUSB_PADCTL_IDDQ,
134};
135
136static const struct tegra_xusb_padctl_property {
137 const char *name;
138 enum tegra_xusb_padctl_param param;
139} properties[] = {
140 { "nvidia,iddq", TEGRA_XUSB_PADCTL_IDDQ },
141};
142
143#define TEGRA_XUSB_PADCTL_PACK(param, value) ((param) << 16 | (value))
144#define TEGRA_XUSB_PADCTL_UNPACK_PARAM(config) ((config) >> 16)
145#define TEGRA_XUSB_PADCTL_UNPACK_VALUE(config) ((config) & 0xffff)
146
147static int tegra_xusb_padctl_parse_subnode(struct tegra_xusb_padctl *padctl,
148 struct device_node *np,
149 struct pinctrl_map **maps,
150 unsigned int *reserved_maps,
151 unsigned int *num_maps)
152{
153 unsigned int i, reserve = 0, num_configs = 0;
154 unsigned long config, *configs = NULL;
155 const char *function, *group;
156 struct property *prop;
157 int err = 0;
158 u32 value;
159
160 err = of_property_read_string(np, "nvidia,function", &function);
161 if (err < 0) {
162 if (err != -EINVAL)
163 return err;
164
165 function = NULL;
166 }
167
168 for (i = 0; i < ARRAY_SIZE(properties); i++) {
169 err = of_property_read_u32(np, properties[i].name, &value);
170 if (err < 0) {
171 if (err == -EINVAL)
172 continue;
173
174 return err;
175 }
176
177 config = TEGRA_XUSB_PADCTL_PACK(properties[i].param, value);
178
179 err = pinctrl_utils_add_config(padctl->pinctrl, &configs,
180 &num_configs, config);
181 if (err < 0)
182 return err;
183 }
184
185 if (function)
186 reserve++;
187
188 if (num_configs)
189 reserve++;
190
191 err = of_property_count_strings(np, "nvidia,lanes");
192 if (err < 0)
193 return err;
194
195 reserve *= err;
196
197 err = pinctrl_utils_reserve_map(padctl->pinctrl, maps, reserved_maps,
198 num_maps, reserve);
199 if (err < 0)
200 return err;
201
202 of_property_for_each_string(np, "nvidia,lanes", prop, group) {
203 if (function) {
204 err = pinctrl_utils_add_map_mux(padctl->pinctrl, maps,
205 reserved_maps, num_maps, group,
206 function);
207 if (err < 0)
208 return err;
209 }
210
211 if (num_configs) {
212 err = pinctrl_utils_add_map_configs(padctl->pinctrl,
213 maps, reserved_maps, num_maps, group,
214 configs, num_configs,
215 PIN_MAP_TYPE_CONFIGS_GROUP);
216 if (err < 0)
217 return err;
218 }
219 }
220
221 return 0;
222}
223
224static int tegra_xusb_padctl_dt_node_to_map(struct pinctrl_dev *pinctrl,
225 struct device_node *parent,
226 struct pinctrl_map **maps,
227 unsigned int *num_maps)
228{
229 struct tegra_xusb_padctl *padctl = pinctrl_dev_get_drvdata(pinctrl);
230 unsigned int reserved_maps = 0;
231 struct device_node *np;
232 int err;
233
234 *num_maps = 0;
235 *maps = NULL;
236
237 for_each_child_of_node(parent, np) {
238 err = tegra_xusb_padctl_parse_subnode(padctl, np, maps,
239 &reserved_maps,
240 num_maps);
241 if (err < 0)
242 return err;
243 }
244
245 return 0;
246}
247
248static const struct pinctrl_ops tegra_xusb_padctl_pinctrl_ops = {
249 .get_groups_count = tegra_xusb_padctl_get_groups_count,
250 .get_group_name = tegra_xusb_padctl_get_group_name,
251 .dt_node_to_map = tegra_xusb_padctl_dt_node_to_map,
252 .dt_free_map = pinctrl_utils_dt_free_map,
253};
254
255static int tegra_xusb_padctl_get_functions_count(struct pinctrl_dev *pinctrl)
256{
257 struct tegra_xusb_padctl *padctl = pinctrl_dev_get_drvdata(pinctrl);
258
259 return padctl->soc->num_functions;
260}
261
262static const char *
263tegra_xusb_padctl_get_function_name(struct pinctrl_dev *pinctrl,
264 unsigned int function)
265{
266 struct tegra_xusb_padctl *padctl = pinctrl_dev_get_drvdata(pinctrl);
267
268 return padctl->soc->functions[function].name;
269}
270
271static int tegra_xusb_padctl_get_function_groups(struct pinctrl_dev *pinctrl,
272 unsigned int function,
273 const char * const **groups,
274 unsigned * const num_groups)
275{
276 struct tegra_xusb_padctl *padctl = pinctrl_dev_get_drvdata(pinctrl);
277
278 *num_groups = padctl->soc->functions[function].num_groups;
279 *groups = padctl->soc->functions[function].groups;
280
281 return 0;
282}
283
284static int tegra_xusb_padctl_pinmux_set(struct pinctrl_dev *pinctrl,
285 unsigned int function,
286 unsigned int group)
287{
288 struct tegra_xusb_padctl *padctl = pinctrl_dev_get_drvdata(pinctrl);
289 const struct tegra_xusb_padctl_lane *lane;
290 unsigned int i;
291 u32 value;
292
293 lane = &padctl->soc->lanes[group];
294
295 for (i = 0; i < lane->num_funcs; i++)
296 if (lane->funcs[i] == function)
297 break;
298
299 if (i >= lane->num_funcs)
300 return -EINVAL;
301
302 value = padctl_readl(padctl, lane->offset);
303 value &= ~(lane->mask << lane->shift);
304 value |= i << lane->shift;
305 padctl_writel(padctl, value, lane->offset);
306
307 return 0;
308}
309
310static const struct pinmux_ops tegra_xusb_padctl_pinmux_ops = {
311 .get_functions_count = tegra_xusb_padctl_get_functions_count,
312 .get_function_name = tegra_xusb_padctl_get_function_name,
313 .get_function_groups = tegra_xusb_padctl_get_function_groups,
314 .set_mux = tegra_xusb_padctl_pinmux_set,
315};
316
317static int tegra_xusb_padctl_pinconf_group_get(struct pinctrl_dev *pinctrl,
318 unsigned int group,
319 unsigned long *config)
320{
321 struct tegra_xusb_padctl *padctl = pinctrl_dev_get_drvdata(pinctrl);
322 const struct tegra_xusb_padctl_lane *lane;
323 enum tegra_xusb_padctl_param param;
324 u32 value;
325
326 param = TEGRA_XUSB_PADCTL_UNPACK_PARAM(*config);
327 lane = &padctl->soc->lanes[group];
328
329 switch (param) {
330 case TEGRA_XUSB_PADCTL_IDDQ:
331 /* lanes with iddq == 0 don't support this parameter */
332 if (lane->iddq == 0)
333 return -EINVAL;
334
335 value = padctl_readl(padctl, lane->offset);
336
337 if (value & BIT(lane->iddq))
338 value = 0;
339 else
340 value = 1;
341
342 *config = TEGRA_XUSB_PADCTL_PACK(param, value);
343 break;
344
345 default:
346 dev_err(padctl->dev, "invalid configuration parameter: %04x\n",
347 param);
348 return -ENOTSUPP;
349 }
350
351 return 0;
352}
353
354static int tegra_xusb_padctl_pinconf_group_set(struct pinctrl_dev *pinctrl,
355 unsigned int group,
356 unsigned long *configs,
357 unsigned int num_configs)
358{
359 struct tegra_xusb_padctl *padctl = pinctrl_dev_get_drvdata(pinctrl);
360 const struct tegra_xusb_padctl_lane *lane;
361 enum tegra_xusb_padctl_param param;
362 unsigned long value;
363 unsigned int i;
364 u32 regval;
365
366 lane = &padctl->soc->lanes[group];
367
368 for (i = 0; i < num_configs; i++) {
369 param = TEGRA_XUSB_PADCTL_UNPACK_PARAM(configs[i]);
370 value = TEGRA_XUSB_PADCTL_UNPACK_VALUE(configs[i]);
371
372 switch (param) {
373 case TEGRA_XUSB_PADCTL_IDDQ:
374 /* lanes with iddq == 0 don't support this parameter */
375 if (lane->iddq == 0)
376 return -EINVAL;
377
378 regval = padctl_readl(padctl, lane->offset);
379
380 if (value)
381 regval &= ~BIT(lane->iddq);
382 else
383 regval |= BIT(lane->iddq);
384
385 padctl_writel(padctl, regval, lane->offset);
386 break;
387
388 default:
389 dev_err(padctl->dev,
390 "invalid configuration parameter: %04x\n",
391 param);
392 return -ENOTSUPP;
393 }
394 }
395
396 return 0;
397}
398
399#ifdef CONFIG_DEBUG_FS
400static const char *strip_prefix(const char *s)
401{
402 const char *comma = strchr(s, ',');
403 if (!comma)
404 return s;
405
406 return comma + 1;
407}
408
409static void
410tegra_xusb_padctl_pinconf_group_dbg_show(struct pinctrl_dev *pinctrl,
411 struct seq_file *s,
412 unsigned int group)
413{
414 unsigned int i;
415
416 for (i = 0; i < ARRAY_SIZE(properties); i++) {
417 unsigned long config, value;
418 int err;
419
420 config = TEGRA_XUSB_PADCTL_PACK(properties[i].param, 0);
421
422 err = tegra_xusb_padctl_pinconf_group_get(pinctrl, group,
423 &config);
424 if (err < 0)
425 continue;
426
427 value = TEGRA_XUSB_PADCTL_UNPACK_VALUE(config);
428
429 seq_printf(s, "\n\t%s=%lu\n", strip_prefix(properties[i].name),
430 value);
431 }
432}
433
434static void
435tegra_xusb_padctl_pinconf_config_dbg_show(struct pinctrl_dev *pinctrl,
436 struct seq_file *s,
437 unsigned long config)
438{
439 enum tegra_xusb_padctl_param param;
440 const char *name = "unknown";
441 unsigned long value;
442 unsigned int i;
443
444 param = TEGRA_XUSB_PADCTL_UNPACK_PARAM(config);
445 value = TEGRA_XUSB_PADCTL_UNPACK_VALUE(config);
446
447 for (i = 0; i < ARRAY_SIZE(properties); i++) {
448 if (properties[i].param == param) {
449 name = properties[i].name;
450 break;
451 }
452 }
453
454 seq_printf(s, "%s=%lu", strip_prefix(name), value);
455}
456#endif
457
458static const struct pinconf_ops tegra_xusb_padctl_pinconf_ops = {
459 .pin_config_group_get = tegra_xusb_padctl_pinconf_group_get,
460 .pin_config_group_set = tegra_xusb_padctl_pinconf_group_set,
461#ifdef CONFIG_DEBUG_FS
462 .pin_config_group_dbg_show = tegra_xusb_padctl_pinconf_group_dbg_show,
463 .pin_config_config_dbg_show = tegra_xusb_padctl_pinconf_config_dbg_show,
464#endif
465};
466
467static int tegra_xusb_padctl_enable(struct tegra_xusb_padctl *padctl)
468{
469 u32 value;
470
471 mutex_lock(&padctl->lock);
472
473 if (padctl->enable++ > 0)
474 goto out;
475
476 value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM);
477 value &= ~XUSB_PADCTL_ELPG_PROGRAM_AUX_MUX_LP0_CLAMP_EN;
478 padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM);
479
480 usleep_range(100, 200);
481
482 value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM);
483 value &= ~XUSB_PADCTL_ELPG_PROGRAM_AUX_MUX_LP0_CLAMP_EN_EARLY;
484 padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM);
485
486 usleep_range(100, 200);
487
488 value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM);
489 value &= ~XUSB_PADCTL_ELPG_PROGRAM_AUX_MUX_LP0_VCORE_DOWN;
490 padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM);
491
492out:
493 mutex_unlock(&padctl->lock);
494 return 0;
495}
496
497static int tegra_xusb_padctl_disable(struct tegra_xusb_padctl *padctl)
498{
499 u32 value;
500
501 mutex_lock(&padctl->lock);
502
503 if (WARN_ON(padctl->enable == 0))
504 goto out;
505
506 if (--padctl->enable > 0)
507 goto out;
508
509 value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM);
510 value |= XUSB_PADCTL_ELPG_PROGRAM_AUX_MUX_LP0_VCORE_DOWN;
511 padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM);
512
513 usleep_range(100, 200);
514
515 value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM);
516 value |= XUSB_PADCTL_ELPG_PROGRAM_AUX_MUX_LP0_CLAMP_EN_EARLY;
517 padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM);
518
519 usleep_range(100, 200);
520
521 value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM);
522 value |= XUSB_PADCTL_ELPG_PROGRAM_AUX_MUX_LP0_CLAMP_EN;
523 padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM);
524
525out:
526 mutex_unlock(&padctl->lock);
527 return 0;
528}
529
530static int tegra_xusb_phy_init(struct phy *phy)
531{
532 struct tegra_xusb_padctl *padctl = phy_get_drvdata(phy);
533
534 return tegra_xusb_padctl_enable(padctl);
535}
536
537static int tegra_xusb_phy_exit(struct phy *phy)
538{
539 struct tegra_xusb_padctl *padctl = phy_get_drvdata(phy);
540
541 return tegra_xusb_padctl_disable(padctl);
542}
543
544static int pcie_phy_power_on(struct phy *phy)
545{
546 struct tegra_xusb_padctl *padctl = phy_get_drvdata(phy);
547 unsigned long timeout;
548 int err = -ETIMEDOUT;
549 u32 value;
550
551 value = padctl_readl(padctl, XUSB_PADCTL_IOPHY_PLL_P0_CTL1);
552 value &= ~XUSB_PADCTL_IOPHY_PLL_P0_CTL1_REFCLK_SEL_MASK;
553 padctl_writel(padctl, value, XUSB_PADCTL_IOPHY_PLL_P0_CTL1);
554
555 value = padctl_readl(padctl, XUSB_PADCTL_IOPHY_PLL_P0_CTL2);
556 value |= XUSB_PADCTL_IOPHY_PLL_P0_CTL2_REFCLKBUF_EN |
557 XUSB_PADCTL_IOPHY_PLL_P0_CTL2_TXCLKREF_EN |
558 XUSB_PADCTL_IOPHY_PLL_P0_CTL2_TXCLKREF_SEL;
559 padctl_writel(padctl, value, XUSB_PADCTL_IOPHY_PLL_P0_CTL2);
560
561 value = padctl_readl(padctl, XUSB_PADCTL_IOPHY_PLL_P0_CTL1);
562 value |= XUSB_PADCTL_IOPHY_PLL_P0_CTL1_PLL_RST;
563 padctl_writel(padctl, value, XUSB_PADCTL_IOPHY_PLL_P0_CTL1);
564
565 timeout = jiffies + msecs_to_jiffies(50);
566
567 while (time_before(jiffies, timeout)) {
568 value = padctl_readl(padctl, XUSB_PADCTL_IOPHY_PLL_P0_CTL1);
569 if (value & XUSB_PADCTL_IOPHY_PLL_P0_CTL1_PLL0_LOCKDET) {
570 err = 0;
571 break;
572 }
573
574 usleep_range(100, 200);
575 }
576
577 return err;
578}
579
580static int pcie_phy_power_off(struct phy *phy)
581{
582 struct tegra_xusb_padctl *padctl = phy_get_drvdata(phy);
583 u32 value;
584
585 value = padctl_readl(padctl, XUSB_PADCTL_IOPHY_PLL_P0_CTL1);
586 value &= ~XUSB_PADCTL_IOPHY_PLL_P0_CTL1_PLL_RST;
587 padctl_writel(padctl, value, XUSB_PADCTL_IOPHY_PLL_P0_CTL1);
588
589 return 0;
590}
591
592static const struct phy_ops pcie_phy_ops = {
593 .init = tegra_xusb_phy_init,
594 .exit = tegra_xusb_phy_exit,
595 .power_on = pcie_phy_power_on,
596 .power_off = pcie_phy_power_off,
597 .owner = THIS_MODULE,
598};
599
600static int sata_phy_power_on(struct phy *phy)
601{
602 struct tegra_xusb_padctl *padctl = phy_get_drvdata(phy);
603 unsigned long timeout;
604 int err = -ETIMEDOUT;
605 u32 value;
606
607 value = padctl_readl(padctl, XUSB_PADCTL_IOPHY_MISC_PAD_S0_CTL1);
608 value &= ~XUSB_PADCTL_IOPHY_MISC_PAD_S0_CTL1_IDDQ_OVRD;
609 value &= ~XUSB_PADCTL_IOPHY_MISC_PAD_S0_CTL1_IDDQ;
610 padctl_writel(padctl, value, XUSB_PADCTL_IOPHY_MISC_PAD_S0_CTL1);
611
612 value = padctl_readl(padctl, XUSB_PADCTL_IOPHY_PLL_S0_CTL1);
613 value &= ~XUSB_PADCTL_IOPHY_PLL_S0_CTL1_PLL_PWR_OVRD;
614 value &= ~XUSB_PADCTL_IOPHY_PLL_S0_CTL1_PLL_IDDQ;
615 padctl_writel(padctl, value, XUSB_PADCTL_IOPHY_PLL_S0_CTL1);
616
617 value = padctl_readl(padctl, XUSB_PADCTL_IOPHY_PLL_S0_CTL1);
618 value |= XUSB_PADCTL_IOPHY_PLL_S0_CTL1_PLL1_MODE;
619 padctl_writel(padctl, value, XUSB_PADCTL_IOPHY_PLL_S0_CTL1);
620
621 value = padctl_readl(padctl, XUSB_PADCTL_IOPHY_PLL_S0_CTL1);
622 value |= XUSB_PADCTL_IOPHY_PLL_S0_CTL1_PLL_RST;
623 padctl_writel(padctl, value, XUSB_PADCTL_IOPHY_PLL_S0_CTL1);
624
625 timeout = jiffies + msecs_to_jiffies(50);
626
627 while (time_before(jiffies, timeout)) {
628 value = padctl_readl(padctl, XUSB_PADCTL_IOPHY_PLL_S0_CTL1);
629 if (value & XUSB_PADCTL_IOPHY_PLL_S0_CTL1_PLL1_LOCKDET) {
630 err = 0;
631 break;
632 }
633
634 usleep_range(100, 200);
635 }
636
637 return err;
638}
639
640static int sata_phy_power_off(struct phy *phy)
641{
642 struct tegra_xusb_padctl *padctl = phy_get_drvdata(phy);
643 u32 value;
644
645 value = padctl_readl(padctl, XUSB_PADCTL_IOPHY_PLL_S0_CTL1);
646 value &= ~XUSB_PADCTL_IOPHY_PLL_S0_CTL1_PLL_RST;
647 padctl_writel(padctl, value, XUSB_PADCTL_IOPHY_PLL_S0_CTL1);
648
649 value = padctl_readl(padctl, XUSB_PADCTL_IOPHY_PLL_S0_CTL1);
650 value &= ~XUSB_PADCTL_IOPHY_PLL_S0_CTL1_PLL1_MODE;
651 padctl_writel(padctl, value, XUSB_PADCTL_IOPHY_PLL_S0_CTL1);
652
653 value = padctl_readl(padctl, XUSB_PADCTL_IOPHY_PLL_S0_CTL1);
654 value |= XUSB_PADCTL_IOPHY_PLL_S0_CTL1_PLL_PWR_OVRD;
655 value |= XUSB_PADCTL_IOPHY_PLL_S0_CTL1_PLL_IDDQ;
656 padctl_writel(padctl, value, XUSB_PADCTL_IOPHY_PLL_S0_CTL1);
657
658 value = padctl_readl(padctl, XUSB_PADCTL_IOPHY_MISC_PAD_S0_CTL1);
659 value |= ~XUSB_PADCTL_IOPHY_MISC_PAD_S0_CTL1_IDDQ_OVRD;
660 value |= ~XUSB_PADCTL_IOPHY_MISC_PAD_S0_CTL1_IDDQ;
661 padctl_writel(padctl, value, XUSB_PADCTL_IOPHY_MISC_PAD_S0_CTL1);
662
663 return 0;
664}
665
666static const struct phy_ops sata_phy_ops = {
667 .init = tegra_xusb_phy_init,
668 .exit = tegra_xusb_phy_exit,
669 .power_on = sata_phy_power_on,
670 .power_off = sata_phy_power_off,
671 .owner = THIS_MODULE,
672};
673
674static struct phy *tegra_xusb_padctl_xlate(struct device *dev,
675 struct of_phandle_args *args)
676{
677 struct tegra_xusb_padctl *padctl = dev_get_drvdata(dev);
678 unsigned int index = args->args[0];
679
680 if (args->args_count <= 0)
681 return ERR_PTR(-EINVAL);
682
683 if (index >= ARRAY_SIZE(padctl->phys))
684 return ERR_PTR(-EINVAL);
685
686 return padctl->phys[index];
687}
688
689#define PIN_OTG_0 0
690#define PIN_OTG_1 1
691#define PIN_OTG_2 2
692#define PIN_ULPI_0 3
693#define PIN_HSIC_0 4
694#define PIN_HSIC_1 5
695#define PIN_PCIE_0 6
696#define PIN_PCIE_1 7
697#define PIN_PCIE_2 8
698#define PIN_PCIE_3 9
699#define PIN_PCIE_4 10
700#define PIN_SATA_0 11
701
702static const struct pinctrl_pin_desc tegra124_pins[] = {
703 PINCTRL_PIN(PIN_OTG_0, "otg-0"),
704 PINCTRL_PIN(PIN_OTG_1, "otg-1"),
705 PINCTRL_PIN(PIN_OTG_2, "otg-2"),
706 PINCTRL_PIN(PIN_ULPI_0, "ulpi-0"),
707 PINCTRL_PIN(PIN_HSIC_0, "hsic-0"),
708 PINCTRL_PIN(PIN_HSIC_1, "hsic-1"),
709 PINCTRL_PIN(PIN_PCIE_0, "pcie-0"),
710 PINCTRL_PIN(PIN_PCIE_1, "pcie-1"),
711 PINCTRL_PIN(PIN_PCIE_2, "pcie-2"),
712 PINCTRL_PIN(PIN_PCIE_3, "pcie-3"),
713 PINCTRL_PIN(PIN_PCIE_4, "pcie-4"),
714 PINCTRL_PIN(PIN_SATA_0, "sata-0"),
715};
716
717static const char * const tegra124_snps_groups[] = {
718 "otg-0",
719 "otg-1",
720 "otg-2",
721 "ulpi-0",
722 "hsic-0",
723 "hsic-1",
724};
725
726static const char * const tegra124_xusb_groups[] = {
727 "otg-0",
728 "otg-1",
729 "otg-2",
730 "ulpi-0",
731 "hsic-0",
732 "hsic-1",
733};
734
735static const char * const tegra124_uart_groups[] = {
736 "otg-0",
737 "otg-1",
738 "otg-2",
739};
740
741static const char * const tegra124_pcie_groups[] = {
742 "pcie-0",
743 "pcie-1",
744 "pcie-2",
745 "pcie-3",
746 "pcie-4",
747 "sata-0",
748};
749
750static const char * const tegra124_usb3_groups[] = {
751 "pcie-0",
752 "pcie-1",
753 "pcie-2",
754 "pcie-3",
755 "pcie-4",
756 "sata-0",
757};
758
759static const char * const tegra124_sata_groups[] = {
760 "pcie-0",
761 "pcie-1",
762 "pcie-2",
763 "pcie-3",
764 "pcie-4",
765 "sata-0",
766};
767
768static const char * const tegra124_rsvd_groups[] = {
769 "otg-0",
770 "otg-1",
771 "otg-2",
772 "pcie-0",
773 "pcie-1",
774 "pcie-2",
775 "pcie-3",
776 "pcie-4",
777 "sata-0",
778};
779
780#define TEGRA124_FUNCTION(_name) \
781 { \
782 .name = #_name, \
783 .num_groups = ARRAY_SIZE(tegra124_##_name##_groups), \
784 .groups = tegra124_##_name##_groups, \
785 }
786
787static struct tegra_xusb_padctl_function tegra124_functions[] = {
788 TEGRA124_FUNCTION(snps),
789 TEGRA124_FUNCTION(xusb),
790 TEGRA124_FUNCTION(uart),
791 TEGRA124_FUNCTION(pcie),
792 TEGRA124_FUNCTION(usb3),
793 TEGRA124_FUNCTION(sata),
794 TEGRA124_FUNCTION(rsvd),
795};
796
797enum tegra124_function {
798 TEGRA124_FUNC_SNPS,
799 TEGRA124_FUNC_XUSB,
800 TEGRA124_FUNC_UART,
801 TEGRA124_FUNC_PCIE,
802 TEGRA124_FUNC_USB3,
803 TEGRA124_FUNC_SATA,
804 TEGRA124_FUNC_RSVD,
805};
806
807static const unsigned int tegra124_otg_functions[] = {
808 TEGRA124_FUNC_SNPS,
809 TEGRA124_FUNC_XUSB,
810 TEGRA124_FUNC_UART,
811 TEGRA124_FUNC_RSVD,
812};
813
814static const unsigned int tegra124_usb_functions[] = {
815 TEGRA124_FUNC_SNPS,
816 TEGRA124_FUNC_XUSB,
817};
818
819static const unsigned int tegra124_pci_functions[] = {
820 TEGRA124_FUNC_PCIE,
821 TEGRA124_FUNC_USB3,
822 TEGRA124_FUNC_SATA,
823 TEGRA124_FUNC_RSVD,
824};
825
826#define TEGRA124_LANE(_name, _offset, _shift, _mask, _iddq, _funcs) \
827 { \
828 .name = _name, \
829 .offset = _offset, \
830 .shift = _shift, \
831 .mask = _mask, \
832 .iddq = _iddq, \
833 .num_funcs = ARRAY_SIZE(tegra124_##_funcs##_functions), \
834 .funcs = tegra124_##_funcs##_functions, \
835 }
836
837static const struct tegra_xusb_padctl_lane tegra124_lanes[] = {
838 TEGRA124_LANE("otg-0", 0x004, 0, 0x3, 0, otg),
839 TEGRA124_LANE("otg-1", 0x004, 2, 0x3, 0, otg),
840 TEGRA124_LANE("otg-2", 0x004, 4, 0x3, 0, otg),
841 TEGRA124_LANE("ulpi-0", 0x004, 12, 0x1, 0, usb),
842 TEGRA124_LANE("hsic-0", 0x004, 14, 0x1, 0, usb),
843 TEGRA124_LANE("hsic-1", 0x004, 15, 0x1, 0, usb),
844 TEGRA124_LANE("pcie-0", 0x134, 16, 0x3, 1, pci),
845 TEGRA124_LANE("pcie-1", 0x134, 18, 0x3, 2, pci),
846 TEGRA124_LANE("pcie-2", 0x134, 20, 0x3, 3, pci),
847 TEGRA124_LANE("pcie-3", 0x134, 22, 0x3, 4, pci),
848 TEGRA124_LANE("pcie-4", 0x134, 24, 0x3, 5, pci),
849 TEGRA124_LANE("sata-0", 0x134, 26, 0x3, 6, pci),
850};
851
852static const struct tegra_xusb_padctl_soc tegra124_soc = {
853 .num_pins = ARRAY_SIZE(tegra124_pins),
854 .pins = tegra124_pins,
855 .num_functions = ARRAY_SIZE(tegra124_functions),
856 .functions = tegra124_functions,
857 .num_lanes = ARRAY_SIZE(tegra124_lanes),
858 .lanes = tegra124_lanes,
859};
860
861static const struct of_device_id tegra_xusb_padctl_of_match[] = {
862 { .compatible = "nvidia,tegra124-xusb-padctl", .data = &tegra124_soc },
863 { }
864};
865MODULE_DEVICE_TABLE(of, tegra_xusb_padctl_of_match);
866
867static int tegra_xusb_padctl_probe(struct platform_device *pdev)
868{
869 struct tegra_xusb_padctl *padctl;
870 const struct of_device_id *match;
871 struct resource *res;
872 struct phy *phy;
873 int err;
874
875 padctl = devm_kzalloc(&pdev->dev, sizeof(*padctl), GFP_KERNEL);
876 if (!padctl)
877 return -ENOMEM;
878
879 platform_set_drvdata(pdev, padctl);
880 mutex_init(&padctl->lock);
881 padctl->dev = &pdev->dev;
882
883 match = of_match_node(tegra_xusb_padctl_of_match, pdev->dev.of_node);
884 padctl->soc = match->data;
885
886 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
887 padctl->regs = devm_ioremap_resource(&pdev->dev, res);
888 if (IS_ERR(padctl->regs))
889 return PTR_ERR(padctl->regs);
890
891 padctl->rst = devm_reset_control_get(&pdev->dev, NULL);
892 if (IS_ERR(padctl->rst))
893 return PTR_ERR(padctl->rst);
894
895 err = reset_control_deassert(padctl->rst);
896 if (err < 0)
897 return err;
898
899 memset(&padctl->desc, 0, sizeof(padctl->desc));
900 padctl->desc.name = dev_name(padctl->dev);
901 padctl->desc.pctlops = &tegra_xusb_padctl_pinctrl_ops;
902 padctl->desc.pmxops = &tegra_xusb_padctl_pinmux_ops;
903 padctl->desc.confops = &tegra_xusb_padctl_pinconf_ops;
904 padctl->desc.owner = THIS_MODULE;
905
906 padctl->pinctrl = pinctrl_register(&padctl->desc, &pdev->dev, padctl);
907 if (!padctl->pinctrl) {
908 dev_err(&pdev->dev, "failed to register pincontrol\n");
909 err = -ENODEV;
910 goto reset;
911 }
912
913 phy = devm_phy_create(&pdev->dev, NULL, &pcie_phy_ops, NULL);
914 if (IS_ERR(phy)) {
915 err = PTR_ERR(phy);
916 goto unregister;
917 }
918
919 padctl->phys[TEGRA_XUSB_PADCTL_PCIE] = phy;
920 phy_set_drvdata(phy, padctl);
921
922 phy = devm_phy_create(&pdev->dev, NULL, &sata_phy_ops, NULL);
923 if (IS_ERR(phy)) {
924 err = PTR_ERR(phy);
925 goto unregister;
926 }
927
928 padctl->phys[TEGRA_XUSB_PADCTL_SATA] = phy;
929 phy_set_drvdata(phy, padctl);
930
931 padctl->provider = devm_of_phy_provider_register(&pdev->dev,
932 tegra_xusb_padctl_xlate);
933 if (IS_ERR(padctl->provider)) {
934 err = PTR_ERR(padctl->provider);
935 dev_err(&pdev->dev, "failed to register PHYs: %d\n", err);
936 goto unregister;
937 }
938
939 return 0;
940
941unregister:
942 pinctrl_unregister(padctl->pinctrl);
943reset:
944 reset_control_assert(padctl->rst);
945 return err;
946}
947
948static int tegra_xusb_padctl_remove(struct platform_device *pdev)
949{
950 struct tegra_xusb_padctl *padctl = platform_get_drvdata(pdev);
951 int err;
952
953 pinctrl_unregister(padctl->pinctrl);
954
955 err = reset_control_assert(padctl->rst);
956 if (err < 0)
957 dev_err(&pdev->dev, "failed to assert reset: %d\n", err);
958
959 return err;
960}
961
962static struct platform_driver tegra_xusb_padctl_driver = {
963 .driver = {
964 .name = "tegra-xusb-padctl",
965 .of_match_table = tegra_xusb_padctl_of_match,
966 },
967 .probe = tegra_xusb_padctl_probe,
968 .remove = tegra_xusb_padctl_remove,
969};
970module_platform_driver(tegra_xusb_padctl_driver);
971
972MODULE_AUTHOR("Thierry Reding <treding@nvidia.com>");
973MODULE_DESCRIPTION("Tegra 124 XUSB Pad Control driver");
974MODULE_LICENSE("GPL v2");
diff --git a/drivers/pinctrl/pinctrl-tegra.c b/drivers/pinctrl/pinctrl-tegra.c
index 2d43bff74f59..e5949d51bc52 100644
--- a/drivers/pinctrl/pinctrl-tegra.c
+++ b/drivers/pinctrl/pinctrl-tegra.c
@@ -262,8 +262,9 @@ static int tegra_pinctrl_get_func_groups(struct pinctrl_dev *pctldev,
262 return 0; 262 return 0;
263} 263}
264 264
265static int tegra_pinctrl_enable(struct pinctrl_dev *pctldev, unsigned function, 265static int tegra_pinctrl_set_mux(struct pinctrl_dev *pctldev,
266 unsigned group) 266 unsigned function,
267 unsigned group)
267{ 268{
268 struct tegra_pmx *pmx = pinctrl_dev_get_drvdata(pctldev); 269 struct tegra_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
269 const struct tegra_pingroup *g; 270 const struct tegra_pingroup *g;
@@ -290,24 +291,11 @@ static int tegra_pinctrl_enable(struct pinctrl_dev *pctldev, unsigned function,
290 return 0; 291 return 0;
291} 292}
292 293
293static void tegra_pinctrl_disable(struct pinctrl_dev *pctldev,
294 unsigned function, unsigned group)
295{
296 struct tegra_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
297 const struct tegra_pingroup *g;
298
299 g = &pmx->soc->groups[group];
300
301 if (WARN_ON(g->mux_reg < 0))
302 return;
303}
304
305static const struct pinmux_ops tegra_pinmux_ops = { 294static const struct pinmux_ops tegra_pinmux_ops = {
306 .get_functions_count = tegra_pinctrl_get_funcs_count, 295 .get_functions_count = tegra_pinctrl_get_funcs_count,
307 .get_function_name = tegra_pinctrl_get_func_name, 296 .get_function_name = tegra_pinctrl_get_func_name,
308 .get_function_groups = tegra_pinctrl_get_func_groups, 297 .get_function_groups = tegra_pinctrl_get_func_groups,
309 .enable = tegra_pinctrl_enable, 298 .set_mux = tegra_pinctrl_set_mux,
310 .disable = tegra_pinctrl_disable,
311}; 299};
312 300
313static int tegra_pinconf_reg(struct tegra_pmx *pmx, 301static int tegra_pinconf_reg(struct tegra_pmx *pmx,
diff --git a/drivers/pinctrl/pinctrl-tegra114.c b/drivers/pinctrl/pinctrl-tegra114.c
index 33614baab4c0..a3db85b0b75f 100644
--- a/drivers/pinctrl/pinctrl-tegra114.c
+++ b/drivers/pinctrl/pinctrl-tegra114.c
@@ -1850,7 +1850,7 @@ static int tegra114_pinctrl_probe(struct platform_device *pdev)
1850 return tegra_pinctrl_probe(pdev, &tegra114_pinctrl); 1850 return tegra_pinctrl_probe(pdev, &tegra114_pinctrl);
1851} 1851}
1852 1852
1853static struct of_device_id tegra114_pinctrl_of_match[] = { 1853static const struct of_device_id tegra114_pinctrl_of_match[] = {
1854 { .compatible = "nvidia,tegra114-pinmux", }, 1854 { .compatible = "nvidia,tegra114-pinmux", },
1855 { }, 1855 { },
1856}; 1856};
diff --git a/drivers/pinctrl/pinctrl-tegra124.c b/drivers/pinctrl/pinctrl-tegra124.c
index e80797e20017..2f9b75c14967 100644
--- a/drivers/pinctrl/pinctrl-tegra124.c
+++ b/drivers/pinctrl/pinctrl-tegra124.c
@@ -224,6 +224,16 @@
224#define TEGRA_PIN_OWR _PIN(5) 224#define TEGRA_PIN_OWR _PIN(5)
225#define TEGRA_PIN_CLK_32K_IN _PIN(6) 225#define TEGRA_PIN_CLK_32K_IN _PIN(6)
226#define TEGRA_PIN_JTAG_RTCK _PIN(7) 226#define TEGRA_PIN_JTAG_RTCK _PIN(7)
227#define TEGRA_PIN_DSI_B_CLK_P _PIN(8)
228#define TEGRA_PIN_DSI_B_CLK_N _PIN(9)
229#define TEGRA_PIN_DSI_B_D0_P _PIN(10)
230#define TEGRA_PIN_DSI_B_D0_N _PIN(11)
231#define TEGRA_PIN_DSI_B_D1_P _PIN(12)
232#define TEGRA_PIN_DSI_B_D1_N _PIN(13)
233#define TEGRA_PIN_DSI_B_D2_P _PIN(14)
234#define TEGRA_PIN_DSI_B_D2_N _PIN(15)
235#define TEGRA_PIN_DSI_B_D3_P _PIN(16)
236#define TEGRA_PIN_DSI_B_D3_N _PIN(17)
227 237
228static const struct pinctrl_pin_desc tegra124_pins[] = { 238static const struct pinctrl_pin_desc tegra124_pins[] = {
229 PINCTRL_PIN(TEGRA_PIN_CLK_32K_OUT_PA0, "CLK_32K_OUT PA0"), 239 PINCTRL_PIN(TEGRA_PIN_CLK_32K_OUT_PA0, "CLK_32K_OUT PA0"),
@@ -417,6 +427,16 @@ static const struct pinctrl_pin_desc tegra124_pins[] = {
417 PINCTRL_PIN(TEGRA_PIN_OWR, "OWR"), 427 PINCTRL_PIN(TEGRA_PIN_OWR, "OWR"),
418 PINCTRL_PIN(TEGRA_PIN_CLK_32K_IN, "CLK_32K_IN"), 428 PINCTRL_PIN(TEGRA_PIN_CLK_32K_IN, "CLK_32K_IN"),
419 PINCTRL_PIN(TEGRA_PIN_JTAG_RTCK, "JTAG_RTCK"), 429 PINCTRL_PIN(TEGRA_PIN_JTAG_RTCK, "JTAG_RTCK"),
430 PINCTRL_PIN(TEGRA_PIN_DSI_B_CLK_P, "DSI_B_CLK_P"),
431 PINCTRL_PIN(TEGRA_PIN_DSI_B_CLK_N, "DSI_B_CLK_N"),
432 PINCTRL_PIN(TEGRA_PIN_DSI_B_D0_P, "DSI_B_D0_P"),
433 PINCTRL_PIN(TEGRA_PIN_DSI_B_D0_N, "DSI_B_D0_N"),
434 PINCTRL_PIN(TEGRA_PIN_DSI_B_D1_P, "DSI_B_D1_P"),
435 PINCTRL_PIN(TEGRA_PIN_DSI_B_D1_N, "DSI_B_D1_N"),
436 PINCTRL_PIN(TEGRA_PIN_DSI_B_D2_P, "DSI_B_D2_P"),
437 PINCTRL_PIN(TEGRA_PIN_DSI_B_D2_N, "DSI_B_D2_N"),
438 PINCTRL_PIN(TEGRA_PIN_DSI_B_D3_P, "DSI_B_D3_P"),
439 PINCTRL_PIN(TEGRA_PIN_DSI_B_D3_N, "DSI_B_D3_N"),
420}; 440};
421 441
422static const unsigned clk_32k_out_pa0_pins[] = { 442static const unsigned clk_32k_out_pa0_pins[] = {
@@ -1495,6 +1515,19 @@ static const unsigned drive_ao4_pins[] = {
1495 TEGRA_PIN_JTAG_RTCK, 1515 TEGRA_PIN_JTAG_RTCK,
1496}; 1516};
1497 1517
1518static const unsigned mipi_pad_ctrl_dsi_b_pins[] = {
1519 TEGRA_PIN_DSI_B_CLK_P,
1520 TEGRA_PIN_DSI_B_CLK_N,
1521 TEGRA_PIN_DSI_B_D0_P,
1522 TEGRA_PIN_DSI_B_D0_N,
1523 TEGRA_PIN_DSI_B_D1_P,
1524 TEGRA_PIN_DSI_B_D1_N,
1525 TEGRA_PIN_DSI_B_D2_P,
1526 TEGRA_PIN_DSI_B_D2_N,
1527 TEGRA_PIN_DSI_B_D3_P,
1528 TEGRA_PIN_DSI_B_D3_N,
1529};
1530
1498enum tegra_mux { 1531enum tegra_mux {
1499 TEGRA_MUX_BLINK, 1532 TEGRA_MUX_BLINK,
1500 TEGRA_MUX_CCLA, 1533 TEGRA_MUX_CCLA,
@@ -1580,6 +1613,8 @@ enum tegra_mux {
1580 TEGRA_MUX_VI_ALT3, 1613 TEGRA_MUX_VI_ALT3,
1581 TEGRA_MUX_VIMCLK2, 1614 TEGRA_MUX_VIMCLK2,
1582 TEGRA_MUX_VIMCLK2_ALT, 1615 TEGRA_MUX_VIMCLK2_ALT,
1616 TEGRA_MUX_CSI,
1617 TEGRA_MUX_DSI_B,
1583}; 1618};
1584 1619
1585#define FUNCTION(fname) \ 1620#define FUNCTION(fname) \
@@ -1672,10 +1707,13 @@ static struct tegra_function tegra124_functions[] = {
1672 FUNCTION(vi_alt3), 1707 FUNCTION(vi_alt3),
1673 FUNCTION(vimclk2), 1708 FUNCTION(vimclk2),
1674 FUNCTION(vimclk2_alt), 1709 FUNCTION(vimclk2_alt),
1710 FUNCTION(csi),
1711 FUNCTION(dsi_b),
1675}; 1712};
1676 1713
1677#define DRV_PINGROUP_REG_A 0x868 /* bank 0 */ 1714#define DRV_PINGROUP_REG_A 0x868 /* bank 0 */
1678#define PINGROUP_REG_A 0x3000 /* bank 1 */ 1715#define PINGROUP_REG_A 0x3000 /* bank 1 */
1716#define MIPI_PAD_CTRL_PINGROUP_REG_A 0x820 /* bank 2 */
1679 1717
1680#define PINGROUP_REG(r) ((r) - PINGROUP_REG_A) 1718#define PINGROUP_REG(r) ((r) - PINGROUP_REG_A)
1681 1719
@@ -1744,6 +1782,32 @@ static struct tegra_function tegra124_functions[] = {
1744 .drvtype_bit = PINGROUP_BIT_##drvtype(6), \ 1782 .drvtype_bit = PINGROUP_BIT_##drvtype(6), \
1745 } 1783 }
1746 1784
1785#define MIPI_PAD_CTRL_PINGROUP_REG_Y(r) ((r) - MIPI_PAD_CTRL_PINGROUP_REG_A)
1786
1787#define MIPI_PAD_CTRL_PINGROUP(pg_name, r, b, f0, f1) \
1788 { \
1789 .name = "mipi_pad_ctrl_" #pg_name, \
1790 .pins = mipi_pad_ctrl_##pg_name##_pins, \
1791 .npins = ARRAY_SIZE(mipi_pad_ctrl_##pg_name##_pins), \
1792 .funcs = { \
1793 TEGRA_MUX_ ## f0, \
1794 TEGRA_MUX_ ## f1, \
1795 TEGRA_MUX_RSVD3, \
1796 TEGRA_MUX_RSVD4, \
1797 }, \
1798 .mux_reg = MIPI_PAD_CTRL_PINGROUP_REG_Y(r), \
1799 .mux_bank = 2, \
1800 .mux_bit = b, \
1801 .pupd_reg = -1, \
1802 .tri_reg = -1, \
1803 .einput_bit = -1, \
1804 .odrain_bit = -1, \
1805 .lock_bit = -1, \
1806 .ioreset_bit = -1, \
1807 .rcv_sel_bit = -1, \
1808 .drv_reg = -1, \
1809 }
1810
1747static const struct tegra_pingroup tegra124_groups[] = { 1811static const struct tegra_pingroup tegra124_groups[] = {
1748 /* pg_name, f0, f1, f2, f3, r, od, ior, rcv_sel */ 1812 /* pg_name, f0, f1, f2, f3, r, od, ior, rcv_sel */
1749 PINGROUP(ulpi_data0_po1, SPI3, HSI, UARTA, ULPI, 0x3000, N, N, N), 1813 PINGROUP(ulpi_data0_po1, SPI3, HSI, UARTA, ULPI, 0x3000, N, N, N),
@@ -1979,6 +2043,9 @@ static const struct tegra_pingroup tegra124_groups[] = {
1979 DRV_PINGROUP(hv0, 0x9b4, 2, 3, 4, 12, 5, -1, -1, 28, 2, -1, -1, N), 2043 DRV_PINGROUP(hv0, 0x9b4, 2, 3, 4, 12, 5, -1, -1, 28, 2, -1, -1, N),
1980 DRV_PINGROUP(sdio4, 0x9c4, 2, 3, 4, 12, 5, 20, 5, 28, 2, 30, 2, N), 2044 DRV_PINGROUP(sdio4, 0x9c4, 2, 3, 4, 12, 5, 20, 5, 28, 2, 30, 2, N),
1981 DRV_PINGROUP(ao4, 0x9c8, 2, 3, 4, 12, 7, 20, 7, 28, 2, 30, 2, Y), 2045 DRV_PINGROUP(ao4, 0x9c8, 2, 3, 4, 12, 7, 20, 7, 28, 2, 30, 2, Y),
2046
2047 /* pg_name, r b f0, f1 */
2048 MIPI_PAD_CTRL_PINGROUP(dsi_b, 0x820, 1, CSI, DSI_B)
1982}; 2049};
1983 2050
1984static const struct tegra_pinctrl_soc_data tegra124_pinctrl = { 2051static const struct tegra_pinctrl_soc_data tegra124_pinctrl = {
@@ -1996,7 +2063,7 @@ static int tegra124_pinctrl_probe(struct platform_device *pdev)
1996 return tegra_pinctrl_probe(pdev, &tegra124_pinctrl); 2063 return tegra_pinctrl_probe(pdev, &tegra124_pinctrl);
1997} 2064}
1998 2065
1999static struct of_device_id tegra124_pinctrl_of_match[] = { 2066static const struct of_device_id tegra124_pinctrl_of_match[] = {
2000 { .compatible = "nvidia,tegra124-pinmux", }, 2067 { .compatible = "nvidia,tegra124-pinmux", },
2001 { }, 2068 { },
2002}; 2069};
diff --git a/drivers/pinctrl/pinctrl-tegra20.c b/drivers/pinctrl/pinctrl-tegra20.c
index 7563ebc9c791..c9805d2e71b0 100644
--- a/drivers/pinctrl/pinctrl-tegra20.c
+++ b/drivers/pinctrl/pinctrl-tegra20.c
@@ -2228,7 +2228,7 @@ static int tegra20_pinctrl_probe(struct platform_device *pdev)
2228 return tegra_pinctrl_probe(pdev, &tegra20_pinctrl); 2228 return tegra_pinctrl_probe(pdev, &tegra20_pinctrl);
2229} 2229}
2230 2230
2231static struct of_device_id tegra20_pinctrl_of_match[] = { 2231static const struct of_device_id tegra20_pinctrl_of_match[] = {
2232 { .compatible = "nvidia,tegra20-pinmux", }, 2232 { .compatible = "nvidia,tegra20-pinmux", },
2233 { }, 2233 { },
2234}; 2234};
diff --git a/drivers/pinctrl/pinctrl-tegra30.c b/drivers/pinctrl/pinctrl-tegra30.c
index fe2d2cf78ad9..e7b72e916558 100644
--- a/drivers/pinctrl/pinctrl-tegra30.c
+++ b/drivers/pinctrl/pinctrl-tegra30.c
@@ -2484,7 +2484,7 @@ static int tegra30_pinctrl_probe(struct platform_device *pdev)
2484 return tegra_pinctrl_probe(pdev, &tegra30_pinctrl); 2484 return tegra_pinctrl_probe(pdev, &tegra30_pinctrl);
2485} 2485}
2486 2486
2487static struct of_device_id tegra30_pinctrl_of_match[] = { 2487static const struct of_device_id tegra30_pinctrl_of_match[] = {
2488 { .compatible = "nvidia,tegra30-pinmux", }, 2488 { .compatible = "nvidia,tegra30-pinmux", },
2489 { }, 2489 { },
2490}; 2490};
diff --git a/drivers/pinctrl/pinctrl-tz1090-pdc.c b/drivers/pinctrl/pinctrl-tz1090-pdc.c
index 5bf01c28925e..3bb6a3b78864 100644
--- a/drivers/pinctrl/pinctrl-tz1090-pdc.c
+++ b/drivers/pinctrl/pinctrl-tz1090-pdc.c
@@ -547,8 +547,9 @@ static void tz1090_pdc_pinctrl_mux(struct tz1090_pdc_pmx *pmx,
547 __global_unlock2(flags); 547 __global_unlock2(flags);
548} 548}
549 549
550static int tz1090_pdc_pinctrl_enable(struct pinctrl_dev *pctldev, 550static int tz1090_pdc_pinctrl_set_mux(struct pinctrl_dev *pctldev,
551 unsigned int function, unsigned int group) 551 unsigned int function,
552 unsigned int group)
552{ 553{
553 struct tz1090_pdc_pmx *pmx = pinctrl_dev_get_drvdata(pctldev); 554 struct tz1090_pdc_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
554 const struct tz1090_pdc_pingroup *grp = &tz1090_pdc_groups[group]; 555 const struct tz1090_pdc_pingroup *grp = &tz1090_pdc_groups[group];
@@ -574,33 +575,6 @@ static int tz1090_pdc_pinctrl_enable(struct pinctrl_dev *pctldev,
574 return 0; 575 return 0;
575} 576}
576 577
577static void tz1090_pdc_pinctrl_disable(struct pinctrl_dev *pctldev,
578 unsigned int function,
579 unsigned int group)
580{
581 struct tz1090_pdc_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
582 const struct tz1090_pdc_pingroup *grp = &tz1090_pdc_groups[group];
583
584 dev_dbg(pctldev->dev, "%s(func=%u (%s), group=%u (%s))\n",
585 __func__,
586 function, tz1090_pdc_functions[function].name,
587 group, tz1090_pdc_groups[group].name);
588
589 /* is it even a mux? */
590 if (grp->drv)
591 return;
592
593 /* does this group even control the function? */
594 if (function != grp->func)
595 return;
596
597 /* record the pin being unmuxed and update mux bit */
598 spin_lock(&pmx->lock);
599 pmx->mux_en &= ~BIT(grp->pins[0]);
600 tz1090_pdc_pinctrl_mux(pmx, grp);
601 spin_unlock(&pmx->lock);
602}
603
604static const struct tz1090_pdc_pingroup *find_mux_group( 578static const struct tz1090_pdc_pingroup *find_mux_group(
605 struct tz1090_pdc_pmx *pmx, 579 struct tz1090_pdc_pmx *pmx,
606 unsigned int pin) 580 unsigned int pin)
@@ -661,8 +635,7 @@ static struct pinmux_ops tz1090_pdc_pinmux_ops = {
661 .get_functions_count = tz1090_pdc_pinctrl_get_funcs_count, 635 .get_functions_count = tz1090_pdc_pinctrl_get_funcs_count,
662 .get_function_name = tz1090_pdc_pinctrl_get_func_name, 636 .get_function_name = tz1090_pdc_pinctrl_get_func_name,
663 .get_function_groups = tz1090_pdc_pinctrl_get_func_groups, 637 .get_function_groups = tz1090_pdc_pinctrl_get_func_groups,
664 .enable = tz1090_pdc_pinctrl_enable, 638 .set_mux = tz1090_pdc_pinctrl_set_mux,
665 .disable = tz1090_pdc_pinctrl_disable,
666 .gpio_request_enable = tz1090_pdc_pinctrl_gpio_request_enable, 639 .gpio_request_enable = tz1090_pdc_pinctrl_gpio_request_enable,
667 .gpio_disable_free = tz1090_pdc_pinctrl_gpio_disable_free, 640 .gpio_disable_free = tz1090_pdc_pinctrl_gpio_disable_free,
668}; 641};
diff --git a/drivers/pinctrl/pinctrl-tz1090.c b/drivers/pinctrl/pinctrl-tz1090.c
index bc9cd7a7602e..48d36413b99f 100644
--- a/drivers/pinctrl/pinctrl-tz1090.c
+++ b/drivers/pinctrl/pinctrl-tz1090.c
@@ -1415,8 +1415,8 @@ found_mux:
1415 * the effect is the same as enabling the function on each individual pin in the 1415 * the effect is the same as enabling the function on each individual pin in the
1416 * group. 1416 * group.
1417 */ 1417 */
1418static int tz1090_pinctrl_enable(struct pinctrl_dev *pctldev, 1418static int tz1090_pinctrl_set_mux(struct pinctrl_dev *pctldev,
1419 unsigned int function, unsigned int group) 1419 unsigned int function, unsigned int group)
1420{ 1420{
1421 struct tz1090_pmx *pmx = pinctrl_dev_get_drvdata(pctldev); 1421 struct tz1090_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
1422 struct tz1090_pingroup *grp; 1422 struct tz1090_pingroup *grp;
@@ -1479,63 +1479,6 @@ mux_pins:
1479} 1479}
1480 1480
1481/** 1481/**
1482 * tz1090_pinctrl_disable() - Disable a function on a pin group.
1483 * @pctldev: Pin control data
1484 * @function: Function index to disable
1485 * @group: Group index to disable
1486 *
1487 * Disable a particular function on a group of pins. The per GPIO pin pseudo pin
1488 * groups can be used (in which case the pin will be taken out of peripheral
1489 * mode. Some convenience pin groups can also be used in which case the effect
1490 * is the same as enabling the function on each individual pin in the group.
1491 */
1492static void tz1090_pinctrl_disable(struct pinctrl_dev *pctldev,
1493 unsigned int function, unsigned int group)
1494{
1495 struct tz1090_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
1496 struct tz1090_pingroup *grp;
1497 unsigned int pin_num, mux_group, i, npins;
1498 const unsigned int *pins;
1499
1500 /* group of pins? */
1501 if (group < ARRAY_SIZE(tz1090_groups)) {
1502 grp = &tz1090_groups[group];
1503 npins = grp->npins;
1504 pins = grp->pins;
1505 /*
1506 * All pins in the group must belong to the same mux group,
1507 * which allows us to just use the mux group of the first pin.
1508 * By explicitly listing permitted pingroups for each function
1509 * the pinmux core should ensure this is always the case.
1510 */
1511 } else {
1512 pin_num = group - ARRAY_SIZE(tz1090_groups);
1513 npins = 1;
1514 pins = &pin_num;
1515 }
1516 mux_group = tz1090_mux_pins[*pins];
1517
1518 /* no mux group, but can still be individually muxed to peripheral */
1519 if (mux_group >= TZ1090_MUX_GROUP_MAX) {
1520 if (function == TZ1090_MUX_PERIP)
1521 goto unmux_pins;
1522 return;
1523 }
1524
1525 /* mux group already set to a different function? */
1526 grp = &tz1090_mux_groups[mux_group];
1527 dev_dbg(pctldev->dev, "%s: unmuxing %u pin(s) in '%s' from '%s'\n",
1528 __func__, npins, grp->name, tz1090_functions[function].name);
1529
1530 /* subtract pins from ref count and unmux individually */
1531 WARN_ON(grp->func_count < npins);
1532 grp->func_count -= npins;
1533unmux_pins:
1534 for (i = 0; i < npins; ++i)
1535 tz1090_pinctrl_perip_select(pmx, pins[i], false);
1536}
1537
1538/**
1539 * tz1090_pinctrl_gpio_request_enable() - Put pin in GPIO mode. 1482 * tz1090_pinctrl_gpio_request_enable() - Put pin in GPIO mode.
1540 * @pctldev: Pin control data 1483 * @pctldev: Pin control data
1541 * @range: GPIO range 1484 * @range: GPIO range
@@ -1574,8 +1517,7 @@ static struct pinmux_ops tz1090_pinmux_ops = {
1574 .get_functions_count = tz1090_pinctrl_get_funcs_count, 1517 .get_functions_count = tz1090_pinctrl_get_funcs_count,
1575 .get_function_name = tz1090_pinctrl_get_func_name, 1518 .get_function_name = tz1090_pinctrl_get_func_name,
1576 .get_function_groups = tz1090_pinctrl_get_func_groups, 1519 .get_function_groups = tz1090_pinctrl_get_func_groups,
1577 .enable = tz1090_pinctrl_enable, 1520 .set_mux = tz1090_pinctrl_set_mux,
1578 .disable = tz1090_pinctrl_disable,
1579 .gpio_request_enable = tz1090_pinctrl_gpio_request_enable, 1521 .gpio_request_enable = tz1090_pinctrl_gpio_request_enable,
1580 .gpio_disable_free = tz1090_pinctrl_gpio_disable_free, 1522 .gpio_disable_free = tz1090_pinctrl_gpio_disable_free,
1581}; 1523};
diff --git a/drivers/pinctrl/pinctrl-u300.c b/drivers/pinctrl/pinctrl-u300.c
index 209a01b8bd3b..e9c7113d81f2 100644
--- a/drivers/pinctrl/pinctrl-u300.c
+++ b/drivers/pinctrl/pinctrl-u300.c
@@ -955,8 +955,8 @@ static void u300_pmx_endisable(struct u300_pmx *upmx, unsigned selector,
955 } 955 }
956} 956}
957 957
958static int u300_pmx_enable(struct pinctrl_dev *pctldev, unsigned selector, 958static int u300_pmx_set_mux(struct pinctrl_dev *pctldev, unsigned selector,
959 unsigned group) 959 unsigned group)
960{ 960{
961 struct u300_pmx *upmx; 961 struct u300_pmx *upmx;
962 962
@@ -970,19 +970,6 @@ static int u300_pmx_enable(struct pinctrl_dev *pctldev, unsigned selector,
970 return 0; 970 return 0;
971} 971}
972 972
973static void u300_pmx_disable(struct pinctrl_dev *pctldev, unsigned selector,
974 unsigned group)
975{
976 struct u300_pmx *upmx;
977
978 /* There is nothing to do with the power pins */
979 if (selector == 0)
980 return;
981
982 upmx = pinctrl_dev_get_drvdata(pctldev);
983 u300_pmx_endisable(upmx, selector, false);
984}
985
986static int u300_pmx_get_funcs_count(struct pinctrl_dev *pctldev) 973static int u300_pmx_get_funcs_count(struct pinctrl_dev *pctldev)
987{ 974{
988 return ARRAY_SIZE(u300_pmx_functions); 975 return ARRAY_SIZE(u300_pmx_functions);
@@ -1007,8 +994,7 @@ static const struct pinmux_ops u300_pmx_ops = {
1007 .get_functions_count = u300_pmx_get_funcs_count, 994 .get_functions_count = u300_pmx_get_funcs_count,
1008 .get_function_name = u300_pmx_get_func_name, 995 .get_function_name = u300_pmx_get_func_name,
1009 .get_function_groups = u300_pmx_get_groups, 996 .get_function_groups = u300_pmx_get_groups,
1010 .enable = u300_pmx_enable, 997 .set_mux = u300_pmx_set_mux,
1011 .disable = u300_pmx_disable,
1012}; 998};
1013 999
1014static int u300_pin_config_get(struct pinctrl_dev *pctldev, unsigned pin, 1000static int u300_pin_config_get(struct pinctrl_dev *pctldev, unsigned pin,
diff --git a/drivers/pinctrl/pinctrl-xway.c b/drivers/pinctrl/pinctrl-xway.c
index e66f4cae7633..37040ab42890 100644
--- a/drivers/pinctrl/pinctrl-xway.c
+++ b/drivers/pinctrl/pinctrl-xway.c
@@ -801,6 +801,7 @@ static int pinmux_xway_probe(struct platform_device *pdev)
801 of_gpiochip_add(&xway_chip); 801 of_gpiochip_add(&xway_chip);
802 ret = gpiochip_add(&xway_chip); 802 ret = gpiochip_add(&xway_chip);
803 if (ret) { 803 if (ret) {
804 of_gpiochip_remove(&xway_chip);
804 dev_err(&pdev->dev, "Failed to register gpio chip\n"); 805 dev_err(&pdev->dev, "Failed to register gpio chip\n");
805 return ret; 806 return ret;
806 } 807 }
@@ -822,6 +823,7 @@ static int pinmux_xway_probe(struct platform_device *pdev)
822 /* register with the generic lantiq layer */ 823 /* register with the generic lantiq layer */
823 ret = ltq_pinctrl_register(pdev, &xway_info); 824 ret = ltq_pinctrl_register(pdev, &xway_info);
824 if (ret) { 825 if (ret) {
826 gpiochip_remove(&xway_chip);
825 dev_err(&pdev->dev, "Failed to register pinctrl driver\n"); 827 dev_err(&pdev->dev, "Failed to register pinctrl driver\n");
826 return ret; 828 return ret;
827 } 829 }
diff --git a/drivers/pinctrl/pinmux.c b/drivers/pinctrl/pinmux.c
index 051e8592990e..b874458dcb88 100644
--- a/drivers/pinctrl/pinmux.c
+++ b/drivers/pinctrl/pinmux.c
@@ -41,7 +41,7 @@ int pinmux_check_ops(struct pinctrl_dev *pctldev)
41 !ops->get_functions_count || 41 !ops->get_functions_count ||
42 !ops->get_function_name || 42 !ops->get_function_name ||
43 !ops->get_function_groups || 43 !ops->get_function_groups ||
44 !ops->enable) { 44 !ops->set_mux) {
45 dev_err(pctldev->dev, "pinmux ops lacks necessary functions\n"); 45 dev_err(pctldev->dev, "pinmux ops lacks necessary functions\n");
46 return -EINVAL; 46 return -EINVAL;
47 } 47 }
@@ -445,15 +445,15 @@ int pinmux_enable_setting(struct pinctrl_setting const *setting)
445 desc->mux_setting = &(setting->data.mux); 445 desc->mux_setting = &(setting->data.mux);
446 } 446 }
447 447
448 ret = ops->enable(pctldev, setting->data.mux.func, 448 ret = ops->set_mux(pctldev, setting->data.mux.func,
449 setting->data.mux.group); 449 setting->data.mux.group);
450 450
451 if (ret) 451 if (ret)
452 goto err_enable; 452 goto err_set_mux;
453 453
454 return 0; 454 return 0;
455 455
456err_enable: 456err_set_mux:
457 for (i = 0; i < num_pins; i++) { 457 for (i = 0; i < num_pins; i++) {
458 desc = pin_desc_get(pctldev, pins[i]); 458 desc = pin_desc_get(pctldev, pins[i]);
459 if (desc) 459 if (desc)
@@ -471,7 +471,6 @@ void pinmux_disable_setting(struct pinctrl_setting const *setting)
471{ 471{
472 struct pinctrl_dev *pctldev = setting->pctldev; 472 struct pinctrl_dev *pctldev = setting->pctldev;
473 const struct pinctrl_ops *pctlops = pctldev->desc->pctlops; 473 const struct pinctrl_ops *pctlops = pctldev->desc->pctlops;
474 const struct pinmux_ops *ops = pctldev->desc->pmxops;
475 int ret = 0; 474 int ret = 0;
476 const unsigned *pins = NULL; 475 const unsigned *pins = NULL;
477 unsigned num_pins = 0; 476 unsigned num_pins = 0;
@@ -518,9 +517,6 @@ void pinmux_disable_setting(struct pinctrl_setting const *setting)
518 pins[i], desc->name, gname); 517 pins[i], desc->name, gname);
519 } 518 }
520 } 519 }
521
522 if (ops->disable)
523 ops->disable(pctldev, setting->data.mux.func, setting->data.mux.group);
524} 520}
525 521
526#ifdef CONFIG_DEBUG_FS 522#ifdef CONFIG_DEBUG_FS
diff --git a/drivers/pinctrl/qcom/Kconfig b/drivers/pinctrl/qcom/Kconfig
new file mode 100644
index 000000000000..81275af9638b
--- /dev/null
+++ b/drivers/pinctrl/qcom/Kconfig
@@ -0,0 +1,50 @@
1if (ARCH_QCOM || COMPILE_TEST)
2
3config PINCTRL_MSM
4 bool
5 select PINMUX
6 select PINCONF
7 select GENERIC_PINCONF
8 select GPIOLIB_IRQCHIP
9
10config PINCTRL_APQ8064
11 tristate "Qualcomm APQ8064 pin controller driver"
12 depends on GPIOLIB && OF
13 select PINCTRL_MSM
14 help
15 This is the pinctrl, pinmux, pinconf and gpiolib driver for the
16 Qualcomm TLMM block found in the Qualcomm APQ8064 platform.
17
18config PINCTRL_APQ8084
19 tristate "Qualcomm APQ8084 pin controller driver"
20 depends on GPIOLIB && OF
21 select PINCTRL_MSM
22 help
23 This is the pinctrl, pinmux, pinconf and gpiolib driver for the
24 Qualcomm TLMM block found in the Qualcomm APQ8084 platform.
25
26config PINCTRL_IPQ8064
27 tristate "Qualcomm IPQ8064 pin controller driver"
28 depends on GPIOLIB && OF
29 select PINCTRL_MSM
30 help
31 This is the pinctrl, pinmux, pinconf and gpiolib driver for the
32 Qualcomm TLMM block found in the Qualcomm IPQ8064 platform.
33
34config PINCTRL_MSM8960
35 tristate "Qualcomm 8960 pin controller driver"
36 depends on GPIOLIB && OF
37 select PINCTRL_MSM
38 help
39 This is the pinctrl, pinmux, pinconf and gpiolib driver for the
40 Qualcomm TLMM block found in the Qualcomm 8960 platform.
41
42config PINCTRL_MSM8X74
43 tristate "Qualcomm 8x74 pin controller driver"
44 depends on GPIOLIB && OF
45 select PINCTRL_MSM
46 help
47 This is the pinctrl, pinmux, pinconf and gpiolib driver for the
48 Qualcomm TLMM block found in the Qualcomm 8974 platform.
49
50endif
diff --git a/drivers/pinctrl/qcom/Makefile b/drivers/pinctrl/qcom/Makefile
new file mode 100644
index 000000000000..ba8519fcd8d3
--- /dev/null
+++ b/drivers/pinctrl/qcom/Makefile
@@ -0,0 +1,7 @@
1# Qualcomm pin control drivers
2obj-$(CONFIG_PINCTRL_MSM) += pinctrl-msm.o
3obj-$(CONFIG_PINCTRL_APQ8064) += pinctrl-apq8064.o
4obj-$(CONFIG_PINCTRL_APQ8084) += pinctrl-apq8084.o
5obj-$(CONFIG_PINCTRL_IPQ8064) += pinctrl-ipq8064.o
6obj-$(CONFIG_PINCTRL_MSM8960) += pinctrl-msm8960.o
7obj-$(CONFIG_PINCTRL_MSM8X74) += pinctrl-msm8x74.o
diff --git a/drivers/pinctrl/pinctrl-apq8064.c b/drivers/pinctrl/qcom/pinctrl-apq8064.c
index 519f7886b0f1..c832d7d6b912 100644
--- a/drivers/pinctrl/pinctrl-apq8064.c
+++ b/drivers/pinctrl/qcom/pinctrl-apq8064.c
@@ -230,7 +230,7 @@ static const unsigned int sdc3_data_pins[] = { 95 };
230 .pins = gpio##id##_pins, \ 230 .pins = gpio##id##_pins, \
231 .npins = ARRAY_SIZE(gpio##id##_pins), \ 231 .npins = ARRAY_SIZE(gpio##id##_pins), \
232 .funcs = (int[]){ \ 232 .funcs = (int[]){ \
233 APQ_MUX_NA, /* gpio mode */ \ 233 APQ_MUX_gpio, \
234 APQ_MUX_##f1, \ 234 APQ_MUX_##f1, \
235 APQ_MUX_##f2, \ 235 APQ_MUX_##f2, \
236 APQ_MUX_##f3, \ 236 APQ_MUX_##f3, \
@@ -258,6 +258,7 @@ static const unsigned int sdc3_data_pins[] = { 95 };
258 .intr_status_bit = 0, \ 258 .intr_status_bit = 0, \
259 .intr_ack_high = 1, \ 259 .intr_ack_high = 1, \
260 .intr_target_bit = 0, \ 260 .intr_target_bit = 0, \
261 .intr_target_kpss_val = 4, \
261 .intr_raw_status_bit = 3, \ 262 .intr_raw_status_bit = 3, \
262 .intr_polarity_bit = 1, \ 263 .intr_polarity_bit = 1, \
263 .intr_detection_bit = 2, \ 264 .intr_detection_bit = 2, \
@@ -283,6 +284,7 @@ static const unsigned int sdc3_data_pins[] = { 95 };
283 .intr_enable_bit = -1, \ 284 .intr_enable_bit = -1, \
284 .intr_status_bit = -1, \ 285 .intr_status_bit = -1, \
285 .intr_target_bit = -1, \ 286 .intr_target_bit = -1, \
287 .intr_target_kpss_val = -1, \
286 .intr_raw_status_bit = -1, \ 288 .intr_raw_status_bit = -1, \
287 .intr_polarity_bit = -1, \ 289 .intr_polarity_bit = -1, \
288 .intr_detection_bit = -1, \ 290 .intr_detection_bit = -1, \
@@ -293,6 +295,7 @@ enum apq8064_functions {
293 APQ_MUX_cam_mclk, 295 APQ_MUX_cam_mclk,
294 APQ_MUX_codec_mic_i2s, 296 APQ_MUX_codec_mic_i2s,
295 APQ_MUX_codec_spkr_i2s, 297 APQ_MUX_codec_spkr_i2s,
298 APQ_MUX_gpio,
296 APQ_MUX_gsbi1, 299 APQ_MUX_gsbi1,
297 APQ_MUX_gsbi2, 300 APQ_MUX_gsbi2,
298 APQ_MUX_gsbi3, 301 APQ_MUX_gsbi3,
@@ -323,6 +326,7 @@ enum apq8064_functions {
323 APQ_MUX_tsif1, 326 APQ_MUX_tsif1,
324 APQ_MUX_tsif2, 327 APQ_MUX_tsif2,
325 APQ_MUX_usb2_hsic, 328 APQ_MUX_usb2_hsic,
329 APQ_MUX_ps_hold,
326 APQ_MUX_NA, 330 APQ_MUX_NA,
327}; 331};
328 332
@@ -335,6 +339,24 @@ static const char * const codec_mic_i2s_groups[] = {
335static const char * const codec_spkr_i2s_groups[] = { 339static const char * const codec_spkr_i2s_groups[] = {
336 "gpio39", "gpio40", "gpio41", "gpio42" 340 "gpio39", "gpio40", "gpio41", "gpio42"
337}; 341};
342static const char * const gpio_groups[] = {
343 "gpio0", "gpio1", "gpio2", "gpio3", "gpio4", "gpio5", "gpio6", "gpio7",
344 "gpio8", "gpio9", "gpio10", "gpio11", "gpio12", "gpio13", "gpio14",
345 "gpio15", "gpio16", "gpio17", "gpio18", "gpio19", "gpio20", "gpio21",
346 "gpio22", "gpio23", "gpio24", "gpio25", "gpio26", "gpio27", "gpio28",
347 "gpio29", "gpio30", "gpio31", "gpio32", "gpio33", "gpio34", "gpio35",
348 "gpio36", "gpio37", "gpio38", "gpio39", "gpio40", "gpio41", "gpio42",
349 "gpio43", "gpio44", "gpio45", "gpio46", "gpio47", "gpio48", "gpio49",
350 "gpio50", "gpio51", "gpio52", "gpio53", "gpio54", "gpio55", "gpio56",
351 "gpio57", "gpio58", "gpio59", "gpio60", "gpio61", "gpio62", "gpio63",
352 "gpio64", "gpio65", "gpio66", "gpio67", "gpio68", "gpio69", "gpio70",
353 "gpio71", "gpio72", "gpio73", "gpio74", "gpio75", "gpio76", "gpio77",
354 "gpio78", "gpio79", "gpio80", "gpio81", "gpio82", "gpio83", "gpio84",
355 "gpio85", "gpio86", "gpio87", "gpio88", "gpio89"
356};
357static const char * const ps_hold_groups[] = {
358 "gpio78"
359};
338static const char * const gsbi1_groups[] = { 360static const char * const gsbi1_groups[] = {
339 "gpio18", "gpio19", "gpio20", "gpio21" 361 "gpio18", "gpio19", "gpio20", "gpio21"
340}; 362};
@@ -430,6 +452,7 @@ static const struct msm_function apq8064_functions[] = {
430 FUNCTION(cam_mclk), 452 FUNCTION(cam_mclk),
431 FUNCTION(codec_mic_i2s), 453 FUNCTION(codec_mic_i2s),
432 FUNCTION(codec_spkr_i2s), 454 FUNCTION(codec_spkr_i2s),
455 FUNCTION(gpio),
433 FUNCTION(gsbi1), 456 FUNCTION(gsbi1),
434 FUNCTION(gsbi2), 457 FUNCTION(gsbi2),
435 FUNCTION(gsbi3), 458 FUNCTION(gsbi3),
@@ -460,6 +483,7 @@ static const struct msm_function apq8064_functions[] = {
460 FUNCTION(tsif1), 483 FUNCTION(tsif1),
461 FUNCTION(tsif2), 484 FUNCTION(tsif2),
462 FUNCTION(usb2_hsic), 485 FUNCTION(usb2_hsic),
486 FUNCTION(ps_hold),
463}; 487};
464 488
465static const struct msm_pingroup apq8064_groups[] = { 489static const struct msm_pingroup apq8064_groups[] = {
@@ -541,7 +565,7 @@ static const struct msm_pingroup apq8064_groups[] = {
541 PINGROUP(75, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), 565 PINGROUP(75, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
542 PINGROUP(76, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), 566 PINGROUP(76, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
543 PINGROUP(77, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), 567 PINGROUP(77, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
544 PINGROUP(78, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), 568 PINGROUP(78, ps_hold, NA, NA, NA, NA, NA, NA, NA, NA, NA),
545 PINGROUP(79, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), 569 PINGROUP(79, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
546 PINGROUP(80, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), 570 PINGROUP(80, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
547 PINGROUP(81, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), 571 PINGROUP(81, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
diff --git a/drivers/pinctrl/qcom/pinctrl-apq8084.c b/drivers/pinctrl/qcom/pinctrl-apq8084.c
new file mode 100644
index 000000000000..138cbf6134a5
--- /dev/null
+++ b/drivers/pinctrl/qcom/pinctrl-apq8084.c
@@ -0,0 +1,1245 @@
1/*
2 * Copyright (c) 2014, The Linux Foundation. All rights reserved.
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 and
6 * only version 2 as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
12 *
13 */
14
15#include <linux/module.h>
16#include <linux/of.h>
17#include <linux/platform_device.h>
18#include <linux/pinctrl/pinctrl.h>
19
20#include "pinctrl-msm.h"
21
22static const struct pinctrl_pin_desc apq8084_pins[] = {
23 PINCTRL_PIN(0, "GPIO_0"),
24 PINCTRL_PIN(1, "GPIO_1"),
25 PINCTRL_PIN(2, "GPIO_2"),
26 PINCTRL_PIN(3, "GPIO_3"),
27 PINCTRL_PIN(4, "GPIO_4"),
28 PINCTRL_PIN(5, "GPIO_5"),
29 PINCTRL_PIN(6, "GPIO_6"),
30 PINCTRL_PIN(7, "GPIO_7"),
31 PINCTRL_PIN(8, "GPIO_8"),
32 PINCTRL_PIN(9, "GPIO_9"),
33 PINCTRL_PIN(10, "GPIO_10"),
34 PINCTRL_PIN(11, "GPIO_11"),
35 PINCTRL_PIN(12, "GPIO_12"),
36 PINCTRL_PIN(13, "GPIO_13"),
37 PINCTRL_PIN(14, "GPIO_14"),
38 PINCTRL_PIN(15, "GPIO_15"),
39 PINCTRL_PIN(16, "GPIO_16"),
40 PINCTRL_PIN(17, "GPIO_17"),
41 PINCTRL_PIN(18, "GPIO_18"),
42 PINCTRL_PIN(19, "GPIO_19"),
43 PINCTRL_PIN(20, "GPIO_20"),
44 PINCTRL_PIN(21, "GPIO_21"),
45 PINCTRL_PIN(22, "GPIO_22"),
46 PINCTRL_PIN(23, "GPIO_23"),
47 PINCTRL_PIN(24, "GPIO_24"),
48 PINCTRL_PIN(25, "GPIO_25"),
49 PINCTRL_PIN(26, "GPIO_26"),
50 PINCTRL_PIN(27, "GPIO_27"),
51 PINCTRL_PIN(28, "GPIO_28"),
52 PINCTRL_PIN(29, "GPIO_29"),
53 PINCTRL_PIN(30, "GPIO_30"),
54 PINCTRL_PIN(31, "GPIO_31"),
55 PINCTRL_PIN(32, "GPIO_32"),
56 PINCTRL_PIN(33, "GPIO_33"),
57 PINCTRL_PIN(34, "GPIO_34"),
58 PINCTRL_PIN(35, "GPIO_35"),
59 PINCTRL_PIN(36, "GPIO_36"),
60 PINCTRL_PIN(37, "GPIO_37"),
61 PINCTRL_PIN(38, "GPIO_38"),
62 PINCTRL_PIN(39, "GPIO_39"),
63 PINCTRL_PIN(40, "GPIO_40"),
64 PINCTRL_PIN(41, "GPIO_41"),
65 PINCTRL_PIN(42, "GPIO_42"),
66 PINCTRL_PIN(43, "GPIO_43"),
67 PINCTRL_PIN(44, "GPIO_44"),
68 PINCTRL_PIN(45, "GPIO_45"),
69 PINCTRL_PIN(46, "GPIO_46"),
70 PINCTRL_PIN(47, "GPIO_47"),
71 PINCTRL_PIN(48, "GPIO_48"),
72 PINCTRL_PIN(49, "GPIO_49"),
73 PINCTRL_PIN(50, "GPIO_50"),
74 PINCTRL_PIN(51, "GPIO_51"),
75 PINCTRL_PIN(52, "GPIO_52"),
76 PINCTRL_PIN(53, "GPIO_53"),
77 PINCTRL_PIN(54, "GPIO_54"),
78 PINCTRL_PIN(55, "GPIO_55"),
79 PINCTRL_PIN(56, "GPIO_56"),
80 PINCTRL_PIN(57, "GPIO_57"),
81 PINCTRL_PIN(58, "GPIO_58"),
82 PINCTRL_PIN(59, "GPIO_59"),
83 PINCTRL_PIN(60, "GPIO_60"),
84 PINCTRL_PIN(61, "GPIO_61"),
85 PINCTRL_PIN(62, "GPIO_62"),
86 PINCTRL_PIN(63, "GPIO_63"),
87 PINCTRL_PIN(64, "GPIO_64"),
88 PINCTRL_PIN(65, "GPIO_65"),
89 PINCTRL_PIN(66, "GPIO_66"),
90 PINCTRL_PIN(67, "GPIO_67"),
91 PINCTRL_PIN(68, "GPIO_68"),
92 PINCTRL_PIN(69, "GPIO_69"),
93 PINCTRL_PIN(70, "GPIO_70"),
94 PINCTRL_PIN(71, "GPIO_71"),
95 PINCTRL_PIN(72, "GPIO_72"),
96 PINCTRL_PIN(73, "GPIO_73"),
97 PINCTRL_PIN(74, "GPIO_74"),
98 PINCTRL_PIN(75, "GPIO_75"),
99 PINCTRL_PIN(76, "GPIO_76"),
100 PINCTRL_PIN(77, "GPIO_77"),
101 PINCTRL_PIN(78, "GPIO_78"),
102 PINCTRL_PIN(79, "GPIO_79"),
103 PINCTRL_PIN(80, "GPIO_80"),
104 PINCTRL_PIN(81, "GPIO_81"),
105 PINCTRL_PIN(82, "GPIO_82"),
106 PINCTRL_PIN(83, "GPIO_83"),
107 PINCTRL_PIN(84, "GPIO_84"),
108 PINCTRL_PIN(85, "GPIO_85"),
109 PINCTRL_PIN(86, "GPIO_86"),
110 PINCTRL_PIN(87, "GPIO_87"),
111 PINCTRL_PIN(88, "GPIO_88"),
112 PINCTRL_PIN(89, "GPIO_89"),
113 PINCTRL_PIN(90, "GPIO_90"),
114 PINCTRL_PIN(91, "GPIO_91"),
115 PINCTRL_PIN(92, "GPIO_92"),
116 PINCTRL_PIN(93, "GPIO_93"),
117 PINCTRL_PIN(94, "GPIO_94"),
118 PINCTRL_PIN(95, "GPIO_95"),
119 PINCTRL_PIN(96, "GPIO_96"),
120 PINCTRL_PIN(97, "GPIO_97"),
121 PINCTRL_PIN(98, "GPIO_98"),
122 PINCTRL_PIN(99, "GPIO_99"),
123 PINCTRL_PIN(100, "GPIO_100"),
124 PINCTRL_PIN(101, "GPIO_101"),
125 PINCTRL_PIN(102, "GPIO_102"),
126 PINCTRL_PIN(103, "GPIO_103"),
127 PINCTRL_PIN(104, "GPIO_104"),
128 PINCTRL_PIN(105, "GPIO_105"),
129 PINCTRL_PIN(106, "GPIO_106"),
130 PINCTRL_PIN(107, "GPIO_107"),
131 PINCTRL_PIN(108, "GPIO_108"),
132 PINCTRL_PIN(109, "GPIO_109"),
133 PINCTRL_PIN(110, "GPIO_110"),
134 PINCTRL_PIN(111, "GPIO_111"),
135 PINCTRL_PIN(112, "GPIO_112"),
136 PINCTRL_PIN(113, "GPIO_113"),
137 PINCTRL_PIN(114, "GPIO_114"),
138 PINCTRL_PIN(115, "GPIO_115"),
139 PINCTRL_PIN(116, "GPIO_116"),
140 PINCTRL_PIN(117, "GPIO_117"),
141 PINCTRL_PIN(118, "GPIO_118"),
142 PINCTRL_PIN(119, "GPIO_119"),
143 PINCTRL_PIN(120, "GPIO_120"),
144 PINCTRL_PIN(121, "GPIO_121"),
145 PINCTRL_PIN(122, "GPIO_122"),
146 PINCTRL_PIN(123, "GPIO_123"),
147 PINCTRL_PIN(124, "GPIO_124"),
148 PINCTRL_PIN(125, "GPIO_125"),
149 PINCTRL_PIN(126, "GPIO_126"),
150 PINCTRL_PIN(127, "GPIO_127"),
151 PINCTRL_PIN(128, "GPIO_128"),
152 PINCTRL_PIN(129, "GPIO_129"),
153 PINCTRL_PIN(130, "GPIO_130"),
154 PINCTRL_PIN(131, "GPIO_131"),
155 PINCTRL_PIN(132, "GPIO_132"),
156 PINCTRL_PIN(133, "GPIO_133"),
157 PINCTRL_PIN(134, "GPIO_134"),
158 PINCTRL_PIN(135, "GPIO_135"),
159 PINCTRL_PIN(136, "GPIO_136"),
160 PINCTRL_PIN(137, "GPIO_137"),
161 PINCTRL_PIN(138, "GPIO_138"),
162 PINCTRL_PIN(139, "GPIO_139"),
163 PINCTRL_PIN(140, "GPIO_140"),
164 PINCTRL_PIN(141, "GPIO_141"),
165 PINCTRL_PIN(142, "GPIO_142"),
166 PINCTRL_PIN(143, "GPIO_143"),
167 PINCTRL_PIN(144, "GPIO_144"),
168 PINCTRL_PIN(145, "GPIO_145"),
169 PINCTRL_PIN(146, "GPIO_146"),
170
171 PINCTRL_PIN(147, "SDC1_CLK"),
172 PINCTRL_PIN(148, "SDC1_CMD"),
173 PINCTRL_PIN(149, "SDC1_DATA"),
174 PINCTRL_PIN(150, "SDC2_CLK"),
175 PINCTRL_PIN(151, "SDC2_CMD"),
176 PINCTRL_PIN(152, "SDC2_DATA"),
177};
178
179#define DECLARE_APQ_GPIO_PINS(pin) static const unsigned int gpio##pin##_pins[] = { pin }
180
181DECLARE_APQ_GPIO_PINS(0);
182DECLARE_APQ_GPIO_PINS(1);
183DECLARE_APQ_GPIO_PINS(2);
184DECLARE_APQ_GPIO_PINS(3);
185DECLARE_APQ_GPIO_PINS(4);
186DECLARE_APQ_GPIO_PINS(5);
187DECLARE_APQ_GPIO_PINS(6);
188DECLARE_APQ_GPIO_PINS(7);
189DECLARE_APQ_GPIO_PINS(8);
190DECLARE_APQ_GPIO_PINS(9);
191DECLARE_APQ_GPIO_PINS(10);
192DECLARE_APQ_GPIO_PINS(11);
193DECLARE_APQ_GPIO_PINS(12);
194DECLARE_APQ_GPIO_PINS(13);
195DECLARE_APQ_GPIO_PINS(14);
196DECLARE_APQ_GPIO_PINS(15);
197DECLARE_APQ_GPIO_PINS(16);
198DECLARE_APQ_GPIO_PINS(17);
199DECLARE_APQ_GPIO_PINS(18);
200DECLARE_APQ_GPIO_PINS(19);
201DECLARE_APQ_GPIO_PINS(20);
202DECLARE_APQ_GPIO_PINS(21);
203DECLARE_APQ_GPIO_PINS(22);
204DECLARE_APQ_GPIO_PINS(23);
205DECLARE_APQ_GPIO_PINS(24);
206DECLARE_APQ_GPIO_PINS(25);
207DECLARE_APQ_GPIO_PINS(26);
208DECLARE_APQ_GPIO_PINS(27);
209DECLARE_APQ_GPIO_PINS(28);
210DECLARE_APQ_GPIO_PINS(29);
211DECLARE_APQ_GPIO_PINS(30);
212DECLARE_APQ_GPIO_PINS(31);
213DECLARE_APQ_GPIO_PINS(32);
214DECLARE_APQ_GPIO_PINS(33);
215DECLARE_APQ_GPIO_PINS(34);
216DECLARE_APQ_GPIO_PINS(35);
217DECLARE_APQ_GPIO_PINS(36);
218DECLARE_APQ_GPIO_PINS(37);
219DECLARE_APQ_GPIO_PINS(38);
220DECLARE_APQ_GPIO_PINS(39);
221DECLARE_APQ_GPIO_PINS(40);
222DECLARE_APQ_GPIO_PINS(41);
223DECLARE_APQ_GPIO_PINS(42);
224DECLARE_APQ_GPIO_PINS(43);
225DECLARE_APQ_GPIO_PINS(44);
226DECLARE_APQ_GPIO_PINS(45);
227DECLARE_APQ_GPIO_PINS(46);
228DECLARE_APQ_GPIO_PINS(47);
229DECLARE_APQ_GPIO_PINS(48);
230DECLARE_APQ_GPIO_PINS(49);
231DECLARE_APQ_GPIO_PINS(50);
232DECLARE_APQ_GPIO_PINS(51);
233DECLARE_APQ_GPIO_PINS(52);
234DECLARE_APQ_GPIO_PINS(53);
235DECLARE_APQ_GPIO_PINS(54);
236DECLARE_APQ_GPIO_PINS(55);
237DECLARE_APQ_GPIO_PINS(56);
238DECLARE_APQ_GPIO_PINS(57);
239DECLARE_APQ_GPIO_PINS(58);
240DECLARE_APQ_GPIO_PINS(59);
241DECLARE_APQ_GPIO_PINS(60);
242DECLARE_APQ_GPIO_PINS(61);
243DECLARE_APQ_GPIO_PINS(62);
244DECLARE_APQ_GPIO_PINS(63);
245DECLARE_APQ_GPIO_PINS(64);
246DECLARE_APQ_GPIO_PINS(65);
247DECLARE_APQ_GPIO_PINS(66);
248DECLARE_APQ_GPIO_PINS(67);
249DECLARE_APQ_GPIO_PINS(68);
250DECLARE_APQ_GPIO_PINS(69);
251DECLARE_APQ_GPIO_PINS(70);
252DECLARE_APQ_GPIO_PINS(71);
253DECLARE_APQ_GPIO_PINS(72);
254DECLARE_APQ_GPIO_PINS(73);
255DECLARE_APQ_GPIO_PINS(74);
256DECLARE_APQ_GPIO_PINS(75);
257DECLARE_APQ_GPIO_PINS(76);
258DECLARE_APQ_GPIO_PINS(77);
259DECLARE_APQ_GPIO_PINS(78);
260DECLARE_APQ_GPIO_PINS(79);
261DECLARE_APQ_GPIO_PINS(80);
262DECLARE_APQ_GPIO_PINS(81);
263DECLARE_APQ_GPIO_PINS(82);
264DECLARE_APQ_GPIO_PINS(83);
265DECLARE_APQ_GPIO_PINS(84);
266DECLARE_APQ_GPIO_PINS(85);
267DECLARE_APQ_GPIO_PINS(86);
268DECLARE_APQ_GPIO_PINS(87);
269DECLARE_APQ_GPIO_PINS(88);
270DECLARE_APQ_GPIO_PINS(89);
271DECLARE_APQ_GPIO_PINS(90);
272DECLARE_APQ_GPIO_PINS(91);
273DECLARE_APQ_GPIO_PINS(92);
274DECLARE_APQ_GPIO_PINS(93);
275DECLARE_APQ_GPIO_PINS(94);
276DECLARE_APQ_GPIO_PINS(95);
277DECLARE_APQ_GPIO_PINS(96);
278DECLARE_APQ_GPIO_PINS(97);
279DECLARE_APQ_GPIO_PINS(98);
280DECLARE_APQ_GPIO_PINS(99);
281DECLARE_APQ_GPIO_PINS(100);
282DECLARE_APQ_GPIO_PINS(101);
283DECLARE_APQ_GPIO_PINS(102);
284DECLARE_APQ_GPIO_PINS(103);
285DECLARE_APQ_GPIO_PINS(104);
286DECLARE_APQ_GPIO_PINS(105);
287DECLARE_APQ_GPIO_PINS(106);
288DECLARE_APQ_GPIO_PINS(107);
289DECLARE_APQ_GPIO_PINS(108);
290DECLARE_APQ_GPIO_PINS(109);
291DECLARE_APQ_GPIO_PINS(110);
292DECLARE_APQ_GPIO_PINS(111);
293DECLARE_APQ_GPIO_PINS(112);
294DECLARE_APQ_GPIO_PINS(113);
295DECLARE_APQ_GPIO_PINS(114);
296DECLARE_APQ_GPIO_PINS(115);
297DECLARE_APQ_GPIO_PINS(116);
298DECLARE_APQ_GPIO_PINS(117);
299DECLARE_APQ_GPIO_PINS(118);
300DECLARE_APQ_GPIO_PINS(119);
301DECLARE_APQ_GPIO_PINS(120);
302DECLARE_APQ_GPIO_PINS(121);
303DECLARE_APQ_GPIO_PINS(122);
304DECLARE_APQ_GPIO_PINS(123);
305DECLARE_APQ_GPIO_PINS(124);
306DECLARE_APQ_GPIO_PINS(125);
307DECLARE_APQ_GPIO_PINS(126);
308DECLARE_APQ_GPIO_PINS(127);
309DECLARE_APQ_GPIO_PINS(128);
310DECLARE_APQ_GPIO_PINS(129);
311DECLARE_APQ_GPIO_PINS(130);
312DECLARE_APQ_GPIO_PINS(131);
313DECLARE_APQ_GPIO_PINS(132);
314DECLARE_APQ_GPIO_PINS(133);
315DECLARE_APQ_GPIO_PINS(134);
316DECLARE_APQ_GPIO_PINS(135);
317DECLARE_APQ_GPIO_PINS(136);
318DECLARE_APQ_GPIO_PINS(137);
319DECLARE_APQ_GPIO_PINS(138);
320DECLARE_APQ_GPIO_PINS(139);
321DECLARE_APQ_GPIO_PINS(140);
322DECLARE_APQ_GPIO_PINS(141);
323DECLARE_APQ_GPIO_PINS(142);
324DECLARE_APQ_GPIO_PINS(143);
325DECLARE_APQ_GPIO_PINS(144);
326DECLARE_APQ_GPIO_PINS(145);
327DECLARE_APQ_GPIO_PINS(146);
328
329static const unsigned int sdc1_clk_pins[] = { 147 };
330static const unsigned int sdc1_cmd_pins[] = { 148 };
331static const unsigned int sdc1_data_pins[] = { 149 };
332static const unsigned int sdc2_clk_pins[] = { 150 };
333static const unsigned int sdc2_cmd_pins[] = { 151 };
334static const unsigned int sdc2_data_pins[] = { 152 };
335
336#define FUNCTION(fname) \
337 [APQ_MUX_##fname] = { \
338 .name = #fname, \
339 .groups = fname##_groups, \
340 .ngroups = ARRAY_SIZE(fname##_groups), \
341 }
342
343#define PINGROUP(id, f1, f2, f3, f4, f5, f6, f7) \
344 { \
345 .name = "gpio" #id, \
346 .pins = gpio##id##_pins, \
347 .npins = ARRAY_SIZE(gpio##id##_pins), \
348 .funcs = (int[]){ \
349 APQ_MUX_gpio, \
350 APQ_MUX_##f1, \
351 APQ_MUX_##f2, \
352 APQ_MUX_##f3, \
353 APQ_MUX_##f4, \
354 APQ_MUX_##f5, \
355 APQ_MUX_##f6, \
356 APQ_MUX_##f7 \
357 }, \
358 .nfuncs = 8, \
359 .ctl_reg = 0x1000 + 0x10 * id, \
360 .io_reg = 0x1004 + 0x10 * id, \
361 .intr_cfg_reg = 0x1008 + 0x10 * id, \
362 .intr_status_reg = 0x100c + 0x10 * id, \
363 .intr_target_reg = 0x1008 + 0x10 * id, \
364 .mux_bit = 2, \
365 .pull_bit = 0, \
366 .drv_bit = 6, \
367 .oe_bit = 9, \
368 .in_bit = 0, \
369 .out_bit = 1, \
370 .intr_enable_bit = 0, \
371 .intr_status_bit = 0, \
372 .intr_ack_high = 0, \
373 .intr_target_bit = 5, \
374 .intr_target_kpss_val = 3, \
375 .intr_raw_status_bit = 4, \
376 .intr_polarity_bit = 1, \
377 .intr_detection_bit = 2, \
378 .intr_detection_width = 2, \
379 }
380
381#define SDC_PINGROUP(pg_name, ctl, pull, drv) \
382 { \
383 .name = #pg_name, \
384 .pins = pg_name##_pins, \
385 .npins = ARRAY_SIZE(pg_name##_pins), \
386 .ctl_reg = ctl, \
387 .io_reg = 0, \
388 .intr_cfg_reg = 0, \
389 .intr_status_reg = 0, \
390 .intr_target_reg = 0, \
391 .mux_bit = -1, \
392 .pull_bit = pull, \
393 .drv_bit = drv, \
394 .oe_bit = -1, \
395 .in_bit = -1, \
396 .out_bit = -1, \
397 .intr_enable_bit = -1, \
398 .intr_status_bit = -1, \
399 .intr_target_bit = -1, \
400 .intr_target_kpss_val = -1, \
401 .intr_raw_status_bit = -1, \
402 .intr_polarity_bit = -1, \
403 .intr_detection_bit = -1, \
404 .intr_detection_width = -1, \
405 }
406
407enum apq8084_functions {
408 APQ_MUX_adsp_ext,
409 APQ_MUX_audio_ref,
410 APQ_MUX_blsp_i2c1,
411 APQ_MUX_blsp_i2c2,
412 APQ_MUX_blsp_i2c3,
413 APQ_MUX_blsp_i2c4,
414 APQ_MUX_blsp_i2c5,
415 APQ_MUX_blsp_i2c6,
416 APQ_MUX_blsp_i2c7,
417 APQ_MUX_blsp_i2c8,
418 APQ_MUX_blsp_i2c9,
419 APQ_MUX_blsp_i2c10,
420 APQ_MUX_blsp_i2c11,
421 APQ_MUX_blsp_i2c12,
422 APQ_MUX_blsp_spi1,
423 APQ_MUX_blsp_spi1_cs1,
424 APQ_MUX_blsp_spi1_cs2,
425 APQ_MUX_blsp_spi1_cs3,
426 APQ_MUX_blsp_spi2,
427 APQ_MUX_blsp_spi3,
428 APQ_MUX_blsp_spi3_cs1,
429 APQ_MUX_blsp_spi3_cs2,
430 APQ_MUX_blsp_spi3_cs3,
431 APQ_MUX_blsp_spi4,
432 APQ_MUX_blsp_spi5,
433 APQ_MUX_blsp_spi6,
434 APQ_MUX_blsp_spi7,
435 APQ_MUX_blsp_spi8,
436 APQ_MUX_blsp_spi9,
437 APQ_MUX_blsp_spi10,
438 APQ_MUX_blsp_spi10_cs1,
439 APQ_MUX_blsp_spi10_cs2,
440 APQ_MUX_blsp_spi10_cs3,
441 APQ_MUX_blsp_spi11,
442 APQ_MUX_blsp_spi12,
443 APQ_MUX_blsp_uart1,
444 APQ_MUX_blsp_uart2,
445 APQ_MUX_blsp_uart3,
446 APQ_MUX_blsp_uart4,
447 APQ_MUX_blsp_uart5,
448 APQ_MUX_blsp_uart6,
449 APQ_MUX_blsp_uart7,
450 APQ_MUX_blsp_uart8,
451 APQ_MUX_blsp_uart9,
452 APQ_MUX_blsp_uart10,
453 APQ_MUX_blsp_uart11,
454 APQ_MUX_blsp_uart12,
455 APQ_MUX_blsp_uim1,
456 APQ_MUX_blsp_uim2,
457 APQ_MUX_blsp_uim3,
458 APQ_MUX_blsp_uim4,
459 APQ_MUX_blsp_uim5,
460 APQ_MUX_blsp_uim6,
461 APQ_MUX_blsp_uim7,
462 APQ_MUX_blsp_uim8,
463 APQ_MUX_blsp_uim9,
464 APQ_MUX_blsp_uim10,
465 APQ_MUX_blsp_uim11,
466 APQ_MUX_blsp_uim12,
467 APQ_MUX_cam_mclk0,
468 APQ_MUX_cam_mclk1,
469 APQ_MUX_cam_mclk2,
470 APQ_MUX_cam_mclk3,
471 APQ_MUX_cci_async,
472 APQ_MUX_cci_async_in0,
473 APQ_MUX_cci_i2c0,
474 APQ_MUX_cci_i2c1,
475 APQ_MUX_cci_timer0,
476 APQ_MUX_cci_timer1,
477 APQ_MUX_cci_timer2,
478 APQ_MUX_cci_timer3,
479 APQ_MUX_cci_timer4,
480 APQ_MUX_edp_hpd,
481 APQ_MUX_gcc_gp1,
482 APQ_MUX_gcc_gp2,
483 APQ_MUX_gcc_gp3,
484 APQ_MUX_gcc_obt,
485 APQ_MUX_gcc_vtt,
486 APQ_MUX_gp_mn,
487 APQ_MUX_gp_pdm0,
488 APQ_MUX_gp_pdm1,
489 APQ_MUX_gp_pdm2,
490 APQ_MUX_gp0_clk,
491 APQ_MUX_gp1_clk,
492 APQ_MUX_gpio,
493 APQ_MUX_hdmi_cec,
494 APQ_MUX_hdmi_ddc,
495 APQ_MUX_hdmi_dtest,
496 APQ_MUX_hdmi_hpd,
497 APQ_MUX_hdmi_rcv,
498 APQ_MUX_hsic,
499 APQ_MUX_ldo_en,
500 APQ_MUX_ldo_update,
501 APQ_MUX_mdp_vsync,
502 APQ_MUX_pci_e0,
503 APQ_MUX_pci_e0_n,
504 APQ_MUX_pci_e0_rst,
505 APQ_MUX_pci_e1,
506 APQ_MUX_pci_e1_rst,
507 APQ_MUX_pci_e1_rst_n,
508 APQ_MUX_pci_e1_clkreq_n,
509 APQ_MUX_pri_mi2s,
510 APQ_MUX_qua_mi2s,
511 APQ_MUX_sata_act,
512 APQ_MUX_sata_devsleep,
513 APQ_MUX_sata_devsleep_n,
514 APQ_MUX_sd_write,
515 APQ_MUX_sdc_emmc_mode,
516 APQ_MUX_sdc3,
517 APQ_MUX_sdc4,
518 APQ_MUX_sec_mi2s,
519 APQ_MUX_slimbus,
520 APQ_MUX_spdif_tx,
521 APQ_MUX_spkr_i2s,
522 APQ_MUX_spkr_i2s_ws,
523 APQ_MUX_spss_geni,
524 APQ_MUX_ter_mi2s,
525 APQ_MUX_tsif1,
526 APQ_MUX_tsif2,
527 APQ_MUX_uim,
528 APQ_MUX_uim_batt_alarm,
529 APQ_MUX_NA,
530};
531
532static const char * const gpio_groups[] = {
533 "gpio0", "gpio1", "gpio2", "gpio3", "gpio4", "gpio5", "gpio6", "gpio7",
534 "gpio8", "gpio9", "gpio10", "gpio11", "gpio12", "gpio13", "gpio14",
535 "gpio15", "gpio16", "gpio17", "gpio18", "gpio19", "gpio20", "gpio21",
536 "gpio22", "gpio23", "gpio24", "gpio25", "gpio26", "gpio27", "gpio28",
537 "gpio29", "gpio30", "gpio31", "gpio32", "gpio33", "gpio34", "gpio35",
538 "gpio36", "gpio37", "gpio38", "gpio39", "gpio40", "gpio41", "gpio42",
539 "gpio43", "gpio44", "gpio45", "gpio46", "gpio47", "gpio48", "gpio49",
540 "gpio50", "gpio51", "gpio52", "gpio53", "gpio54", "gpio55", "gpio56",
541 "gpio57", "gpio58", "gpio59", "gpio60", "gpio61", "gpio62", "gpio63",
542 "gpio64", "gpio65", "gpio66", "gpio67", "gpio68", "gpio69", "gpio70",
543 "gpio71", "gpio72", "gpio73", "gpio74", "gpio75", "gpio76", "gpio77",
544 "gpio78", "gpio79", "gpio80", "gpio81", "gpio82", "gpio83", "gpio84",
545 "gpio85", "gpio86", "gpio87", "gpio88", "gpio89", "gpio90", "gpio91",
546 "gpio92", "gpio93", "gpio94", "gpio95", "gpio96", "gpio97", "gpio98",
547 "gpio99", "gpio100", "gpio101", "gpio102", "gpio103", "gpio104",
548 "gpio105", "gpio106", "gpio107", "gpio108", "gpio109", "gpio110",
549 "gpio111", "gpio112", "gpio113", "gpio114", "gpio115", "gpio116",
550 "gpio117", "gpio118", "gpio119", "gpio120", "gpio121", "gpio122",
551 "gpio123", "gpio124", "gpio125", "gpio126", "gpio127", "gpio128",
552 "gpio129", "gpio130", "gpio131", "gpio132", "gpio133", "gpio134",
553 "gpio135", "gpio136", "gpio137", "gpio138", "gpio139", "gpio140",
554 "gpio141", "gpio142", "gpio143", "gpio144", "gpio145", "gpio146"
555};
556
557static const char * const adsp_ext_groups[] = {
558 "gpio34"
559};
560static const char * const audio_ref_groups[] = {
561 "gpio100"
562};
563static const char * const blsp_i2c1_groups[] = {
564 "gpio2", "gpio3"
565};
566static const char * const blsp_i2c2_groups[] = {
567 "gpio6", "gpio7"
568};
569static const char * const blsp_i2c3_groups[] = {
570 "gpio10", "gpio11"
571};
572static const char * const blsp_i2c4_groups[] = {
573 "gpio29", "gpio30"
574};
575static const char * const blsp_i2c5_groups[] = {
576 "gpio41", "gpio42"
577};
578static const char * const blsp_i2c6_groups[] = {
579 "gpio45", "gpio46"
580};
581static const char * const blsp_i2c7_groups[] = {
582 "gpio132", "gpio133"
583};
584static const char * const blsp_i2c8_groups[] = {
585 "gpio53", "gpio54"
586};
587static const char * const blsp_i2c9_groups[] = {
588 "gpio57", "gpio58"
589};
590static const char * const blsp_i2c10_groups[] = {
591 "gpio61", "gpio62"
592};
593static const char * const blsp_i2c11_groups[] = {
594 "gpio65", "gpio66"
595};
596static const char * const blsp_i2c12_groups[] = {
597 "gpio49", "gpio50"
598};
599static const char * const blsp_spi1_groups[] = {
600 "gpio0", "gpio1", "gpio2", "gpio3"
601};
602static const char * const blsp_spi2_groups[] = {
603 "gpio4", "gpio5", "gpio6", "gpio7"
604};
605static const char * const blsp_spi3_groups[] = {
606 "gpio8", "gpio9", "gpio10", "gpio11"
607};
608static const char * const blsp_spi4_groups[] = {
609 "gpio27", "gpio28", "gpio29", "gpio30"
610};
611static const char * const blsp_spi5_groups[] = {
612 "gpio39", "gpio40", "gpio41", "gpio42"
613};
614static const char * const blsp_spi6_groups[] = {
615 "gpio43", "gpio44", "gpio45", "gpio46"
616};
617static const char * const blsp_spi7_groups[] = {
618 "gpio130", "gpio131", "gpio132", "gpio133"
619};
620static const char * const blsp_spi8_groups[] = {
621 "gpio51", "gpio52", "gpio53", "gpio54"
622};
623static const char * const blsp_spi9_groups[] = {
624 "gpio55", "gpio56", "gpio57", "gpio58"
625};
626static const char * const blsp_spi10_groups[] = {
627 "gpio59", "gpio60", "gpio61", "gpio62"
628};
629static const char * const blsp_spi11_groups[] = {
630 "gpio63", "gpio64", "gpio65", "gpio66"
631};
632static const char * const blsp_spi12_groups[] = {
633 "gpio47", "gpio48", "gpio49", "gpio50"
634};
635static const char * const blsp_uart1_groups[] = {
636 "gpio0", "gpio1", "gpio2", "gpio3"
637};
638static const char * const blsp_uart2_groups[] = {
639 "gpio4", "gpio5", "gpio6", "gpio7"
640};
641static const char * const blsp_uart3_groups[] = {
642 "gpio8"
643};
644static const char * const blsp_uart4_groups[] = {
645 "gpio27", "gpio28", "gpio29", "gpio30"
646};
647static const char * const blsp_uart5_groups[] = {
648 "gpio39", "gpio40", "gpio41", "gpio42"
649};
650static const char * const blsp_uart6_groups[] = {
651 "gpio43", "gpio44", "gpio45", "gpio46"
652};
653static const char * const blsp_uart7_groups[] = {
654 "gpio130", "gpio131", "gpio132", "gpio133"
655};
656static const char * const blsp_uart8_groups[] = {
657 "gpio51", "gpio52", "gpio53", "gpio54"
658};
659static const char * const blsp_uart9_groups[] = {
660 "gpio55", "gpio56", "gpio57", "gpio58"
661};
662static const char * const blsp_uart10_groups[] = {
663 "gpio59", "gpio60", "gpio61", "gpio62"
664};
665static const char * const blsp_uart11_groups[] = {
666 "gpio63", "gpio64", "gpio65", "gpio66"
667};
668static const char * const blsp_uart12_groups[] = {
669 "gpio47", "gpio48", "gpio49", "gpio50"
670};
671static const char * const blsp_uim1_groups[] = {
672 "gpio0", "gpio1"
673};
674static const char * const blsp_uim2_groups[] = {
675 "gpio4", "gpio5"
676};
677static const char * const blsp_uim3_groups[] = {
678 "gpio8", "gpio9"
679};
680static const char * const blsp_uim4_groups[] = {
681 "gpio27", "gpio28"
682};
683static const char * const blsp_uim5_groups[] = {
684 "gpio39", "gpio40"
685};
686static const char * const blsp_uim6_groups[] = {
687 "gpio43", "gpio44"
688};
689static const char * const blsp_uim7_groups[] = {
690 "gpio130", "gpio131"
691};
692static const char * const blsp_uim8_groups[] = {
693 "gpio51", "gpio52"
694};
695static const char * const blsp_uim9_groups[] = {
696 "gpio55", "gpio56"
697};
698static const char * const blsp_uim10_groups[] = {
699 "gpio59", "gpio60"
700};
701static const char * const blsp_uim11_groups[] = {
702 "gpio63", "gpio64"
703};
704static const char * const blsp_uim12_groups[] = {
705 "gpio47", "gpio48"
706};
707static const char * const blsp_spi1_cs1_groups[] = {
708 "gpio116"
709};
710static const char * const blsp_spi1_cs2_groups[] = {
711 "gpio117"
712};
713static const char * const blsp_spi1_cs3_groups[] = {
714 "gpio118"
715};
716static const char * const blsp_spi3_cs1_groups[] = {
717 "gpio67"
718};
719static const char * const blsp_spi3_cs2_groups[] = {
720 "gpio71"
721};
722static const char * const blsp_spi3_cs3_groups[] = {
723 "gpio72"
724};
725static const char * const blsp_spi10_cs1_groups[] = {
726 "gpio106"
727};
728static const char * const blsp_spi10_cs2_groups[] = {
729 "gpio111"
730};
731static const char * const blsp_spi10_cs3_groups[] = {
732 "gpio128"
733};
734static const char * const cam_mclk0_groups[] = {
735 "gpio15"
736};
737static const char * const cam_mclk1_groups[] = {
738 "gpio16"
739};
740static const char * const cam_mclk2_groups[] = {
741 "gpio17"
742};
743static const char * const cam_mclk3_groups[] = {
744 "gpio18"
745};
746static const char * const cci_async_groups[] = {
747 "gpio26", "gpio119"
748};
749static const char * const cci_async_in0_groups[] = {
750 "gpio120"
751};
752static const char * const cci_i2c0_groups[] = {
753 "gpio19", "gpio20"
754};
755static const char * const cci_i2c1_groups[] = {
756 "gpio21", "gpio22"
757};
758static const char * const cci_timer0_groups[] = {
759 "gpio23"
760};
761static const char * const cci_timer1_groups[] = {
762 "gpio24"
763};
764static const char * const cci_timer2_groups[] = {
765 "gpio25"
766};
767static const char * const cci_timer3_groups[] = {
768 "gpio26"
769};
770static const char * const cci_timer4_groups[] = {
771 "gpio119"
772};
773static const char * const edp_hpd_groups[] = {
774 "gpio103"
775};
776static const char * const gcc_gp1_groups[] = {
777 "gpio37"
778};
779static const char * const gcc_gp2_groups[] = {
780 "gpio38"
781};
782static const char * const gcc_gp3_groups[] = {
783 "gpio86"
784};
785static const char * const gcc_obt_groups[] = {
786 "gpio127"
787};
788static const char * const gcc_vtt_groups[] = {
789 "gpio126"
790};
791static const char * const gp_mn_groups[] = {
792 "gpio29"
793};
794static const char * const gp_pdm0_groups[] = {
795 "gpio48", "gpio83"
796};
797static const char * const gp_pdm1_groups[] = {
798 "gpio84", "gpio101"
799};
800static const char * const gp_pdm2_groups[] = {
801 "gpio85", "gpio110"
802};
803static const char * const gp0_clk_groups[] = {
804 "gpio25"
805};
806static const char * const gp1_clk_groups[] = {
807 "gpio26"
808};
809static const char * const hdmi_cec_groups[] = {
810 "gpio31"
811};
812static const char * const hdmi_ddc_groups[] = {
813 "gpio32", "gpio33"
814};
815static const char * const hdmi_dtest_groups[] = {
816 "gpio123"
817};
818static const char * const hdmi_hpd_groups[] = {
819 "gpio34"
820};
821static const char * const hdmi_rcv_groups[] = {
822 "gpio125"
823};
824static const char * const hsic_groups[] = {
825 "gpio134", "gpio135"
826};
827static const char * const ldo_en_groups[] = {
828 "gpio124"
829};
830static const char * const ldo_update_groups[] = {
831 "gpio125"
832};
833static const char * const mdp_vsync_groups[] = {
834 "gpio12", "gpio13", "gpio14"
835};
836static const char * const pci_e0_groups[] = {
837 "gpio68", "gpio70"
838};
839static const char * const pci_e0_n_groups[] = {
840 "gpio68", "gpio70"
841};
842static const char * const pci_e0_rst_groups[] = {
843 "gpio70"
844};
845static const char * const pci_e1_groups[] = {
846 "gpio140"
847};
848static const char * const pci_e1_rst_groups[] = {
849 "gpio140"
850};
851static const char * const pci_e1_rst_n_groups[] = {
852 "gpio140"
853};
854static const char * const pci_e1_clkreq_n_groups[] = {
855 "gpio141"
856};
857static const char * const pri_mi2s_groups[] = {
858 "gpio76", "gpio77", "gpio78", "gpio79", "gpio80"
859};
860static const char * const qua_mi2s_groups[] = {
861 "gpio91", "gpio92", "gpio93", "gpio94", "gpio95", "gpio96", "gpio97"
862};
863static const char * const sata_act_groups[] = {
864 "gpio129"
865};
866static const char * const sata_devsleep_groups[] = {
867 "gpio119"
868};
869static const char * const sata_devsleep_n_groups[] = {
870 "gpio119"
871};
872static const char * const sd_write_groups[] = {
873 "gpio75"
874};
875static const char * const sdc_emmc_mode_groups[] = {
876 "gpio146"
877};
878static const char * const sdc3_groups[] = {
879 "gpio67", "gpio68", "gpio69", "gpio70", "gpio71", "gpio72"
880};
881static const char * const sdc4_groups[] = {
882 "gpio82", "gpio83", "gpio84", "gpio85", "gpio86",
883 "gpio91", "gpio95", "gpio96", "gpio97", "gpio101"
884};
885static const char * const sec_mi2s_groups[] = {
886 "gpio81", "gpio82", "gpio83", "gpio84", "gpio85"
887};
888static const char * const slimbus_groups[] = {
889 "gpio98", "gpio99"
890};
891static const char * const spdif_tx_groups[] = {
892 "gpio124", "gpio136", "gpio142"
893};
894static const char * const spkr_i2s_groups[] = {
895 "gpio98", "gpio99", "gpio100"
896};
897static const char * const spkr_i2s_ws_groups[] = {
898 "gpio104"
899};
900static const char * const spss_geni_groups[] = {
901 "gpio8", "gpio9"
902};
903static const char * const ter_mi2s_groups[] = {
904 "gpio86", "gpio87", "gpio88", "gpio89", "gpio90"
905};
906static const char * const tsif1_groups[] = {
907 "gpio82", "gpio83", "gpio84", "gpio85", "gpio86"
908};
909static const char * const tsif2_groups[] = {
910 "gpio91", "gpio95", "gpio96", "gpio97", "gpio101"
911};
912static const char * const uim_groups[] = {
913 "gpio130", "gpio131", "gpio132", "gpio133"
914};
915static const char * const uim_batt_alarm_groups[] = {
916 "gpio102"
917};
918static const struct msm_function apq8084_functions[] = {
919 FUNCTION(adsp_ext),
920 FUNCTION(audio_ref),
921 FUNCTION(blsp_i2c1),
922 FUNCTION(blsp_i2c2),
923 FUNCTION(blsp_i2c3),
924 FUNCTION(blsp_i2c4),
925 FUNCTION(blsp_i2c5),
926 FUNCTION(blsp_i2c6),
927 FUNCTION(blsp_i2c7),
928 FUNCTION(blsp_i2c8),
929 FUNCTION(blsp_i2c9),
930 FUNCTION(blsp_i2c10),
931 FUNCTION(blsp_i2c11),
932 FUNCTION(blsp_i2c12),
933 FUNCTION(blsp_spi1),
934 FUNCTION(blsp_spi1_cs1),
935 FUNCTION(blsp_spi1_cs2),
936 FUNCTION(blsp_spi1_cs3),
937 FUNCTION(blsp_spi2),
938 FUNCTION(blsp_spi3),
939 FUNCTION(blsp_spi3_cs1),
940 FUNCTION(blsp_spi3_cs2),
941 FUNCTION(blsp_spi3_cs3),
942 FUNCTION(blsp_spi4),
943 FUNCTION(blsp_spi5),
944 FUNCTION(blsp_spi6),
945 FUNCTION(blsp_spi7),
946 FUNCTION(blsp_spi8),
947 FUNCTION(blsp_spi9),
948 FUNCTION(blsp_spi10),
949 FUNCTION(blsp_spi10_cs1),
950 FUNCTION(blsp_spi10_cs2),
951 FUNCTION(blsp_spi10_cs3),
952 FUNCTION(blsp_spi11),
953 FUNCTION(blsp_spi12),
954 FUNCTION(blsp_uart1),
955 FUNCTION(blsp_uart2),
956 FUNCTION(blsp_uart3),
957 FUNCTION(blsp_uart4),
958 FUNCTION(blsp_uart5),
959 FUNCTION(blsp_uart6),
960 FUNCTION(blsp_uart7),
961 FUNCTION(blsp_uart8),
962 FUNCTION(blsp_uart9),
963 FUNCTION(blsp_uart10),
964 FUNCTION(blsp_uart11),
965 FUNCTION(blsp_uart12),
966 FUNCTION(blsp_uim1),
967 FUNCTION(blsp_uim2),
968 FUNCTION(blsp_uim3),
969 FUNCTION(blsp_uim4),
970 FUNCTION(blsp_uim5),
971 FUNCTION(blsp_uim6),
972 FUNCTION(blsp_uim7),
973 FUNCTION(blsp_uim8),
974 FUNCTION(blsp_uim9),
975 FUNCTION(blsp_uim10),
976 FUNCTION(blsp_uim11),
977 FUNCTION(blsp_uim12),
978 FUNCTION(cam_mclk0),
979 FUNCTION(cam_mclk1),
980 FUNCTION(cam_mclk2),
981 FUNCTION(cam_mclk3),
982 FUNCTION(cci_async),
983 FUNCTION(cci_async_in0),
984 FUNCTION(cci_i2c0),
985 FUNCTION(cci_i2c1),
986 FUNCTION(cci_timer0),
987 FUNCTION(cci_timer1),
988 FUNCTION(cci_timer2),
989 FUNCTION(cci_timer3),
990 FUNCTION(cci_timer4),
991 FUNCTION(edp_hpd),
992 FUNCTION(gcc_gp1),
993 FUNCTION(gcc_gp2),
994 FUNCTION(gcc_gp3),
995 FUNCTION(gcc_obt),
996 FUNCTION(gcc_vtt),
997 FUNCTION(gp_mn),
998 FUNCTION(gp_pdm0),
999 FUNCTION(gp_pdm1),
1000 FUNCTION(gp_pdm2),
1001 FUNCTION(gp0_clk),
1002 FUNCTION(gp1_clk),
1003 FUNCTION(gpio),
1004 FUNCTION(hdmi_cec),
1005 FUNCTION(hdmi_ddc),
1006 FUNCTION(hdmi_dtest),
1007 FUNCTION(hdmi_hpd),
1008 FUNCTION(hdmi_rcv),
1009 FUNCTION(hsic),
1010 FUNCTION(ldo_en),
1011 FUNCTION(ldo_update),
1012 FUNCTION(mdp_vsync),
1013 FUNCTION(pci_e0),
1014 FUNCTION(pci_e0_n),
1015 FUNCTION(pci_e0_rst),
1016 FUNCTION(pci_e1),
1017 FUNCTION(pci_e1_rst),
1018 FUNCTION(pci_e1_rst_n),
1019 FUNCTION(pci_e1_clkreq_n),
1020 FUNCTION(pri_mi2s),
1021 FUNCTION(qua_mi2s),
1022 FUNCTION(sata_act),
1023 FUNCTION(sata_devsleep),
1024 FUNCTION(sata_devsleep_n),
1025 FUNCTION(sd_write),
1026 FUNCTION(sdc_emmc_mode),
1027 FUNCTION(sdc3),
1028 FUNCTION(sdc4),
1029 FUNCTION(sec_mi2s),
1030 FUNCTION(slimbus),
1031 FUNCTION(spdif_tx),
1032 FUNCTION(spkr_i2s),
1033 FUNCTION(spkr_i2s_ws),
1034 FUNCTION(spss_geni),
1035 FUNCTION(ter_mi2s),
1036 FUNCTION(tsif1),
1037 FUNCTION(tsif2),
1038 FUNCTION(uim),
1039 FUNCTION(uim_batt_alarm),
1040};
1041
1042static const struct msm_pingroup apq8084_groups[] = {
1043 PINGROUP(0, blsp_spi1, blsp_uart1, blsp_uim1, NA, NA, NA, NA),
1044 PINGROUP(1, blsp_spi1, blsp_uart1, blsp_uim1, NA, NA, NA, NA),
1045 PINGROUP(2, blsp_spi1, blsp_uart1, blsp_i2c1, NA, NA, NA, NA),
1046 PINGROUP(3, blsp_spi1, blsp_uart1, blsp_i2c1, NA, NA, NA, NA),
1047 PINGROUP(4, blsp_spi2, blsp_uart2, blsp_uim2, NA, NA, NA, NA),
1048 PINGROUP(5, blsp_spi2, blsp_uart2, blsp_uim2, NA, NA, NA, NA),
1049 PINGROUP(6, blsp_spi2, blsp_uart2, blsp_i2c2, NA, NA, NA, NA),
1050 PINGROUP(7, blsp_spi2, blsp_uart2, blsp_i2c2, NA, NA, NA, NA),
1051 PINGROUP(8, blsp_spi3, blsp_uart3, blsp_uim3, spss_geni, NA, NA, NA),
1052 PINGROUP(9, blsp_spi3, blsp_uim3, blsp_uart3, spss_geni, NA, NA, NA),
1053 PINGROUP(10, blsp_spi3, blsp_uart3, blsp_i2c3, NA, NA, NA, NA),
1054 PINGROUP(11, blsp_spi3, blsp_uart3, blsp_i2c3, NA, NA, NA, NA),
1055 PINGROUP(12, mdp_vsync, NA, NA, NA, NA, NA, NA),
1056 PINGROUP(13, mdp_vsync, NA, NA, NA, NA, NA, NA),
1057 PINGROUP(14, mdp_vsync, NA, NA, NA, NA, NA, NA),
1058 PINGROUP(15, cam_mclk0, NA, NA, NA, NA, NA, NA),
1059 PINGROUP(16, cam_mclk1, NA, NA, NA, NA, NA, NA),
1060 PINGROUP(17, cam_mclk2, NA, NA, NA, NA, NA, NA),
1061 PINGROUP(18, cam_mclk3, NA, NA, NA, NA, NA, NA),
1062 PINGROUP(19, cci_i2c0, NA, NA, NA, NA, NA, NA),
1063 PINGROUP(20, cci_i2c0, NA, NA, NA, NA, NA, NA),
1064 PINGROUP(21, cci_i2c1, NA, NA, NA, NA, NA, NA),
1065 PINGROUP(22, cci_i2c1, NA, NA, NA, NA, NA, NA),
1066 PINGROUP(23, cci_timer0, NA, NA, NA, NA, NA, NA),
1067 PINGROUP(24, cci_timer1, NA, NA, NA, NA, NA, NA),
1068 PINGROUP(25, cci_timer2, gp0_clk, NA, NA, NA, NA, NA),
1069 PINGROUP(26, cci_timer3, cci_async, gp1_clk, NA, NA, NA, NA),
1070 PINGROUP(27, blsp_spi4, blsp_uart4, blsp_uim4, NA, NA, NA, NA),
1071 PINGROUP(28, blsp_spi4, blsp_uart4, blsp_uim4, NA, NA, NA, NA),
1072 PINGROUP(29, blsp_spi4, blsp_uart4, blsp_i2c4, gp_mn, NA, NA, NA),
1073 PINGROUP(30, blsp_spi4, blsp_uart4, blsp_i2c4, NA, NA, NA, NA),
1074 PINGROUP(31, hdmi_cec, NA, NA, NA, NA, NA, NA),
1075 PINGROUP(32, hdmi_ddc, NA, NA, NA, NA, NA, NA),
1076 PINGROUP(33, hdmi_ddc, NA, NA, NA, NA, NA, NA),
1077 PINGROUP(34, hdmi_hpd, NA, adsp_ext, NA, NA, NA, NA),
1078 PINGROUP(35, NA, NA, NA, NA, NA, NA, NA),
1079 PINGROUP(36, NA, NA, NA, NA, NA, NA, NA),
1080 PINGROUP(37, gcc_gp1, NA, NA, NA, NA, NA, NA),
1081 PINGROUP(38, gcc_gp2, NA, NA, NA, NA, NA, NA),
1082 PINGROUP(39, blsp_spi5, blsp_uart5, blsp_uim5, NA, NA, NA, NA),
1083 PINGROUP(40, blsp_spi5, blsp_uart5, blsp_uim5, NA, NA, NA, NA),
1084 PINGROUP(41, blsp_spi5, blsp_uart5, blsp_i2c5, NA, NA, NA, NA),
1085 PINGROUP(42, blsp_spi5, blsp_uart5, blsp_i2c5, NA, NA, NA, NA),
1086 PINGROUP(43, blsp_spi6, blsp_uart6, blsp_uim6, NA, NA, NA, NA),
1087 PINGROUP(44, blsp_spi6, blsp_uart6, blsp_uim6, NA, NA, NA, NA),
1088 PINGROUP(45, blsp_spi6, blsp_uart6, blsp_i2c6, NA, NA, NA, NA),
1089 PINGROUP(46, blsp_spi6, blsp_uart6, blsp_i2c6, NA, NA, NA, NA),
1090 PINGROUP(47, blsp_spi12, blsp_uart12, blsp_uim12, NA, NA, NA, NA),
1091 PINGROUP(48, blsp_spi12, blsp_uart12, blsp_uim12, gp_pdm0, NA, NA, NA),
1092 PINGROUP(49, blsp_spi12, blsp_uart12, blsp_i2c12, NA, NA, NA, NA),
1093 PINGROUP(50, blsp_spi12, blsp_uart12, blsp_i2c12, NA, NA, NA, NA),
1094 PINGROUP(51, blsp_spi8, blsp_uart8, blsp_uim8, NA, NA, NA, NA),
1095 PINGROUP(52, blsp_spi8, blsp_uart8, blsp_uim8, NA, NA, NA, NA),
1096 PINGROUP(53, blsp_spi8, blsp_uart8, blsp_i2c8, NA, NA, NA, NA),
1097 PINGROUP(54, blsp_spi8, blsp_uart8, blsp_i2c8, NA, NA, NA, NA),
1098 PINGROUP(55, blsp_spi9, blsp_uart9, blsp_uim9, NA, NA, NA, NA),
1099 PINGROUP(56, blsp_spi9, blsp_uart9, blsp_uim9, NA, NA, NA, NA),
1100 PINGROUP(57, blsp_spi9, blsp_uart9, blsp_i2c9, NA, NA, NA, NA),
1101 PINGROUP(58, blsp_spi9, blsp_uart9, blsp_i2c9, NA, NA, NA, NA),
1102 PINGROUP(59, blsp_spi10, blsp_uart10, blsp_uim10, NA, NA, NA, NA),
1103 PINGROUP(60, blsp_spi10, blsp_uart10, blsp_uim10, NA, NA, NA, NA),
1104 PINGROUP(61, blsp_spi10, blsp_uart10, blsp_i2c10, NA, NA, NA, NA),
1105 PINGROUP(62, blsp_spi10, blsp_uart10, blsp_i2c10, NA, NA, NA, NA),
1106 PINGROUP(63, blsp_spi11, blsp_uart11, blsp_uim11, NA, NA, NA, NA),
1107 PINGROUP(64, blsp_spi11, blsp_uart11, blsp_uim11, NA, NA, NA, NA),
1108 PINGROUP(65, blsp_spi11, blsp_uart11, blsp_i2c11, NA, NA, NA, NA),
1109 PINGROUP(66, blsp_spi11, blsp_uart11, blsp_i2c11, NA, NA, NA, NA),
1110 PINGROUP(67, sdc3, blsp_spi3_cs1, NA, NA, NA, NA, NA),
1111 PINGROUP(68, sdc3, pci_e0, NA, NA, NA, NA, NA),
1112 PINGROUP(69, sdc3, NA, NA, NA, NA, NA, NA),
1113 PINGROUP(70, sdc3, pci_e0_n, pci_e0, NA, NA, NA, NA),
1114 PINGROUP(71, sdc3, blsp_spi3_cs2, NA, NA, NA, NA, NA),
1115 PINGROUP(72, sdc3, blsp_spi3_cs3, NA, NA, NA, NA, NA),
1116 PINGROUP(73, NA, NA, NA, NA, NA, NA, NA),
1117 PINGROUP(74, NA, NA, NA, NA, NA, NA, NA),
1118 PINGROUP(75, sd_write, NA, NA, NA, NA, NA, NA),
1119 PINGROUP(76, pri_mi2s, NA, NA, NA, NA, NA, NA),
1120 PINGROUP(77, pri_mi2s, NA, NA, NA, NA, NA, NA),
1121 PINGROUP(78, pri_mi2s, NA, NA, NA, NA, NA, NA),
1122 PINGROUP(79, pri_mi2s, NA, NA, NA, NA, NA, NA),
1123 PINGROUP(80, pri_mi2s, NA, NA, NA, NA, NA, NA),
1124 PINGROUP(81, sec_mi2s, NA, NA, NA, NA, NA, NA),
1125 PINGROUP(82, sec_mi2s, sdc4, tsif1, NA, NA, NA, NA),
1126 PINGROUP(83, sec_mi2s, sdc4, tsif1, NA, NA, NA, gp_pdm0),
1127 PINGROUP(84, sec_mi2s, sdc4, tsif1, NA, NA, NA, gp_pdm1),
1128 PINGROUP(85, sec_mi2s, sdc4, tsif1, NA, gp_pdm2, NA, NA),
1129 PINGROUP(86, ter_mi2s, sdc4, tsif1, NA, NA, NA, gcc_gp3),
1130 PINGROUP(87, ter_mi2s, NA, NA, NA, NA, NA, NA),
1131 PINGROUP(88, ter_mi2s, NA, NA, NA, NA, NA, NA),
1132 PINGROUP(89, ter_mi2s, NA, NA, NA, NA, NA, NA),
1133 PINGROUP(90, ter_mi2s, NA, NA, NA, NA, NA, NA),
1134 PINGROUP(91, qua_mi2s, sdc4, tsif2, NA, NA, NA, NA),
1135 PINGROUP(92, qua_mi2s, NA, NA, NA, NA, NA, NA),
1136 PINGROUP(93, qua_mi2s, NA, NA, NA, NA, NA, NA),
1137 PINGROUP(94, qua_mi2s, NA, NA, NA, NA, NA, NA),
1138 PINGROUP(95, qua_mi2s, sdc4, tsif2, NA, NA, NA, gcc_gp1),
1139 PINGROUP(96, qua_mi2s, sdc4, tsif2, NA, NA, NA, gcc_gp2),
1140 PINGROUP(97, qua_mi2s, sdc4, tsif2, NA, gcc_gp3, NA, NA),
1141 PINGROUP(98, slimbus, spkr_i2s, NA, NA, NA, NA, NA),
1142 PINGROUP(99, slimbus, spkr_i2s, NA, NA, NA, NA, NA),
1143 PINGROUP(100, audio_ref, spkr_i2s, NA, NA, NA, NA, NA),
1144 PINGROUP(101, sdc4, tsif2, gp_pdm1, NA, NA, NA, NA),
1145 PINGROUP(102, uim_batt_alarm, NA, NA, NA, NA, NA, NA),
1146 PINGROUP(103, edp_hpd, NA, NA, NA, NA, NA, NA),
1147 PINGROUP(104, spkr_i2s, NA, NA, NA, NA, NA, NA),
1148 PINGROUP(105, NA, NA, NA, NA, NA, NA, NA),
1149 PINGROUP(106, blsp_spi10_cs1, NA, NA, NA, NA, NA, NA),
1150 PINGROUP(107, NA, NA, NA, NA, NA, NA, NA),
1151 PINGROUP(108, NA, NA, NA, NA, NA, NA, NA),
1152 PINGROUP(109, NA, NA, NA, NA, NA, NA, NA),
1153 PINGROUP(110, gp_pdm2, NA, NA, NA, NA, NA, NA),
1154 PINGROUP(111, blsp_spi10_cs2, NA, NA, NA, NA, NA, NA),
1155 PINGROUP(112, NA, NA, NA, NA, NA, NA, NA),
1156 PINGROUP(113, NA, NA, NA, NA, NA, NA, NA),
1157 PINGROUP(114, NA, NA, NA, NA, NA, NA, NA),
1158 PINGROUP(115, NA, NA, NA, NA, NA, NA, NA),
1159 PINGROUP(116, blsp_spi1_cs1, NA, NA, NA, NA, NA, NA),
1160 PINGROUP(117, blsp_spi1_cs2, NA, NA, NA, NA, NA, NA),
1161 PINGROUP(118, blsp_spi1_cs3, NA, NA, NA, NA, NA, NA),
1162 PINGROUP(119, cci_timer4, cci_async, sata_devsleep, sata_devsleep_n, NA, NA, NA),
1163 PINGROUP(120, cci_async, NA, NA, NA, NA, NA, NA),
1164 PINGROUP(121, NA, NA, NA, NA, NA, NA, NA),
1165 PINGROUP(122, NA, NA, NA, NA, NA, NA, NA),
1166 PINGROUP(123, hdmi_dtest, NA, NA, NA, NA, NA, NA),
1167 PINGROUP(124, spdif_tx, ldo_en, NA, NA, NA, NA, NA),
1168 PINGROUP(125, ldo_update, hdmi_rcv, NA, NA, NA, NA, NA),
1169 PINGROUP(126, gcc_vtt, NA, NA, NA, NA, NA, NA),
1170 PINGROUP(127, gcc_obt, NA, NA, NA, NA, NA, NA),
1171 PINGROUP(128, blsp_spi10_cs3, NA, NA, NA, NA, NA, NA),
1172 PINGROUP(129, sata_act, NA, NA, NA, NA, NA, NA),
1173 PINGROUP(130, uim, blsp_spi7, blsp_uart7, blsp_uim7, NA, NA, NA),
1174 PINGROUP(131, uim, blsp_spi7, blsp_uart7, blsp_uim7, NA, NA, NA),
1175 PINGROUP(132, uim, blsp_spi7, blsp_uart7, blsp_i2c7, NA, NA, NA),
1176 PINGROUP(133, uim, blsp_spi7, blsp_uart7, blsp_i2c7, NA, NA, NA),
1177 PINGROUP(134, hsic, NA, NA, NA, NA, NA, NA),
1178 PINGROUP(135, hsic, NA, NA, NA, NA, NA, NA),
1179 PINGROUP(136, spdif_tx, NA, NA, NA, NA, NA, NA),
1180 PINGROUP(137, NA, NA, NA, NA, NA, NA, NA),
1181 PINGROUP(138, NA, NA, NA, NA, NA, NA, NA),
1182 PINGROUP(139, NA, NA, NA, NA, NA, NA, NA),
1183 PINGROUP(140, pci_e1_rst_n, pci_e1_rst, NA, NA, NA, NA, NA),
1184 PINGROUP(141, pci_e1_clkreq_n, NA, NA, NA, NA, NA, NA),
1185 PINGROUP(142, spdif_tx, NA, NA, NA, NA, NA, NA),
1186 PINGROUP(143, NA, NA, NA, NA, NA, NA, NA),
1187 PINGROUP(144, NA, NA, NA, NA, NA, NA, NA),
1188 PINGROUP(145, NA, NA, NA, NA, NA, NA, NA),
1189 PINGROUP(146, sdc_emmc_mode, NA, NA, NA, NA, NA, NA),
1190
1191 SDC_PINGROUP(sdc1_clk, 0x2044, 13, 6),
1192 SDC_PINGROUP(sdc1_cmd, 0x2044, 11, 3),
1193 SDC_PINGROUP(sdc1_data, 0x2044, 9, 0),
1194 SDC_PINGROUP(sdc2_clk, 0x2048, 14, 6),
1195 SDC_PINGROUP(sdc2_cmd, 0x2048, 11, 3),
1196 SDC_PINGROUP(sdc2_data, 0x2048, 9, 0),
1197};
1198
1199#define NUM_GPIO_PINGROUPS 147
1200
1201static const struct msm_pinctrl_soc_data apq8084_pinctrl = {
1202 .pins = apq8084_pins,
1203 .npins = ARRAY_SIZE(apq8084_pins),
1204 .functions = apq8084_functions,
1205 .nfunctions = ARRAY_SIZE(apq8084_functions),
1206 .groups = apq8084_groups,
1207 .ngroups = ARRAY_SIZE(apq8084_groups),
1208 .ngpios = NUM_GPIO_PINGROUPS,
1209};
1210
1211static int apq8084_pinctrl_probe(struct platform_device *pdev)
1212{
1213 return msm_pinctrl_probe(pdev, &apq8084_pinctrl);
1214}
1215
1216static const struct of_device_id apq8084_pinctrl_of_match[] = {
1217 { .compatible = "qcom,apq8084-pinctrl", },
1218 { },
1219};
1220
1221static struct platform_driver apq8084_pinctrl_driver = {
1222 .driver = {
1223 .name = "apq8084-pinctrl",
1224 .owner = THIS_MODULE,
1225 .of_match_table = apq8084_pinctrl_of_match,
1226 },
1227 .probe = apq8084_pinctrl_probe,
1228 .remove = msm_pinctrl_remove,
1229};
1230
1231static int __init apq8084_pinctrl_init(void)
1232{
1233 return platform_driver_register(&apq8084_pinctrl_driver);
1234}
1235arch_initcall(apq8084_pinctrl_init);
1236
1237static void __exit apq8084_pinctrl_exit(void)
1238{
1239 platform_driver_unregister(&apq8084_pinctrl_driver);
1240}
1241module_exit(apq8084_pinctrl_exit);
1242
1243MODULE_DESCRIPTION("Qualcomm APQ8084 pinctrl driver");
1244MODULE_LICENSE("GPL v2");
1245MODULE_DEVICE_TABLE(of, apq8084_pinctrl_of_match);
diff --git a/drivers/pinctrl/pinctrl-ipq8064.c b/drivers/pinctrl/qcom/pinctrl-ipq8064.c
index acafea4c3a33..81f49a9b4dbe 100644
--- a/drivers/pinctrl/pinctrl-ipq8064.c
+++ b/drivers/pinctrl/qcom/pinctrl-ipq8064.c
@@ -183,7 +183,7 @@ static const unsigned int sdc3_data_pins[] = { 71 };
183 .pins = gpio##id##_pins, \ 183 .pins = gpio##id##_pins, \
184 .npins = ARRAY_SIZE(gpio##id##_pins), \ 184 .npins = ARRAY_SIZE(gpio##id##_pins), \
185 .funcs = (int[]){ \ 185 .funcs = (int[]){ \
186 IPQ_MUX_NA, /* gpio mode */ \ 186 IPQ_MUX_gpio, \
187 IPQ_MUX_##f1, \ 187 IPQ_MUX_##f1, \
188 IPQ_MUX_##f2, \ 188 IPQ_MUX_##f2, \
189 IPQ_MUX_##f3, \ 189 IPQ_MUX_##f3, \
@@ -211,6 +211,7 @@ static const unsigned int sdc3_data_pins[] = { 71 };
211 .intr_status_bit = 0, \ 211 .intr_status_bit = 0, \
212 .intr_ack_high = 1, \ 212 .intr_ack_high = 1, \
213 .intr_target_bit = 0, \ 213 .intr_target_bit = 0, \
214 .intr_target_kpss_val = 4, \
214 .intr_raw_status_bit = 3, \ 215 .intr_raw_status_bit = 3, \
215 .intr_polarity_bit = 1, \ 216 .intr_polarity_bit = 1, \
216 .intr_detection_bit = 2, \ 217 .intr_detection_bit = 2, \
@@ -236,6 +237,7 @@ static const unsigned int sdc3_data_pins[] = { 71 };
236 .intr_enable_bit = -1, \ 237 .intr_enable_bit = -1, \
237 .intr_status_bit = -1, \ 238 .intr_status_bit = -1, \
238 .intr_target_bit = -1, \ 239 .intr_target_bit = -1, \
240 .intr_target_kpss_val = -1, \
239 .intr_raw_status_bit = -1, \ 241 .intr_raw_status_bit = -1, \
240 .intr_polarity_bit = -1, \ 242 .intr_polarity_bit = -1, \
241 .intr_detection_bit = -1, \ 243 .intr_detection_bit = -1, \
@@ -243,6 +245,7 @@ static const unsigned int sdc3_data_pins[] = { 71 };
243 } 245 }
244 246
245enum ipq8064_functions { 247enum ipq8064_functions {
248 IPQ_MUX_gpio,
246 IPQ_MUX_mdio, 249 IPQ_MUX_mdio,
247 IPQ_MUX_mi2s, 250 IPQ_MUX_mi2s,
248 IPQ_MUX_pdm, 251 IPQ_MUX_pdm,
@@ -291,6 +294,19 @@ enum ipq8064_functions {
291 IPQ_MUX_NA, 294 IPQ_MUX_NA,
292}; 295};
293 296
297static const char * const gpio_groups[] = {
298 "gpio0", "gpio1", "gpio2", "gpio3", "gpio4", "gpio5", "gpio6", "gpio7",
299 "gpio8", "gpio9", "gpio10", "gpio11", "gpio12", "gpio13", "gpio14",
300 "gpio15", "gpio16", "gpio17", "gpio18", "gpio19", "gpio20", "gpio21",
301 "gpio22", "gpio23", "gpio24", "gpio25", "gpio26", "gpio27", "gpio28",
302 "gpio29", "gpio30", "gpio31", "gpio32", "gpio33", "gpio34", "gpio35",
303 "gpio36", "gpio37", "gpio38", "gpio39", "gpio40", "gpio41", "gpio42",
304 "gpio43", "gpio44", "gpio45", "gpio46", "gpio47", "gpio48", "gpio49",
305 "gpio50", "gpio51", "gpio52", "gpio53", "gpio54", "gpio55", "gpio56",
306 "gpio57", "gpio58", "gpio59", "gpio60", "gpio61", "gpio62", "gpio63",
307 "gpio64", "gpio65", "gpio66", "gpio67", "gpio68"
308};
309
294static const char * const mdio_groups[] = { 310static const char * const mdio_groups[] = {
295 "gpio0", "gpio1", "gpio10", "gpio11", 311 "gpio0", "gpio1", "gpio10", "gpio11",
296}; 312};
@@ -481,6 +497,7 @@ static const char * const ps_hold_groups[] = {
481}; 497};
482 498
483static const struct msm_function ipq8064_functions[] = { 499static const struct msm_function ipq8064_functions[] = {
500 FUNCTION(gpio),
484 FUNCTION(mdio), 501 FUNCTION(mdio),
485 FUNCTION(ssbi), 502 FUNCTION(ssbi),
486 FUNCTION(spmi), 503 FUNCTION(spmi),
diff --git a/drivers/pinctrl/pinctrl-msm.c b/drivers/pinctrl/qcom/pinctrl-msm.c
index df6dda4ce803..e730935fa457 100644
--- a/drivers/pinctrl/pinctrl-msm.c
+++ b/drivers/pinctrl/qcom/pinctrl-msm.c
@@ -12,6 +12,7 @@
12 * GNU General Public License for more details. 12 * GNU General Public License for more details.
13 */ 13 */
14 14
15#include <linux/delay.h>
15#include <linux/err.h> 16#include <linux/err.h>
16#include <linux/io.h> 17#include <linux/io.h>
17#include <linux/module.h> 18#include <linux/module.h>
@@ -26,19 +27,22 @@
26#include <linux/gpio.h> 27#include <linux/gpio.h>
27#include <linux/interrupt.h> 28#include <linux/interrupt.h>
28#include <linux/spinlock.h> 29#include <linux/spinlock.h>
30#include <linux/reboot.h>
29 31
30#include "core.h" 32#include "../core.h"
31#include "pinconf.h" 33#include "../pinconf.h"
32#include "pinctrl-msm.h" 34#include "pinctrl-msm.h"
33#include "pinctrl-utils.h" 35#include "../pinctrl-utils.h"
34 36
35#define MAX_NR_GPIO 300 37#define MAX_NR_GPIO 300
38#define PS_HOLD_OFFSET 0x820
36 39
37/** 40/**
38 * struct msm_pinctrl - state for a pinctrl-msm device 41 * struct msm_pinctrl - state for a pinctrl-msm device
39 * @dev: device handle. 42 * @dev: device handle.
40 * @pctrl: pinctrl handle. 43 * @pctrl: pinctrl handle.
41 * @chip: gpiochip handle. 44 * @chip: gpiochip handle.
45 * @restart_nb: restart notifier block.
42 * @irq: parent irq for the TLMM irq_chip. 46 * @irq: parent irq for the TLMM irq_chip.
43 * @lock: Spinlock to protect register resources as well 47 * @lock: Spinlock to protect register resources as well
44 * as msm_pinctrl data structures. 48 * as msm_pinctrl data structures.
@@ -52,6 +56,7 @@ struct msm_pinctrl {
52 struct device *dev; 56 struct device *dev;
53 struct pinctrl_dev *pctrl; 57 struct pinctrl_dev *pctrl;
54 struct gpio_chip chip; 58 struct gpio_chip chip;
59 struct notifier_block restart_nb;
55 int irq; 60 int irq;
56 61
57 spinlock_t lock; 62 spinlock_t lock;
@@ -130,9 +135,9 @@ static int msm_get_function_groups(struct pinctrl_dev *pctldev,
130 return 0; 135 return 0;
131} 136}
132 137
133static int msm_pinmux_enable(struct pinctrl_dev *pctldev, 138static int msm_pinmux_set_mux(struct pinctrl_dev *pctldev,
134 unsigned function, 139 unsigned function,
135 unsigned group) 140 unsigned group)
136{ 141{
137 struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); 142 struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
138 const struct msm_pingroup *g; 143 const struct msm_pingroup *g;
@@ -142,9 +147,6 @@ static int msm_pinmux_enable(struct pinctrl_dev *pctldev,
142 147
143 g = &pctrl->soc->groups[group]; 148 g = &pctrl->soc->groups[group];
144 149
145 if (WARN_ON(g->mux_bit < 0))
146 return -EINVAL;
147
148 for (i = 0; i < g->nfuncs; i++) { 150 for (i = 0; i < g->nfuncs; i++) {
149 if (g->funcs[i] == function) 151 if (g->funcs[i] == function)
150 break; 152 break;
@@ -165,36 +167,11 @@ static int msm_pinmux_enable(struct pinctrl_dev *pctldev,
165 return 0; 167 return 0;
166} 168}
167 169
168static void msm_pinmux_disable(struct pinctrl_dev *pctldev,
169 unsigned function,
170 unsigned group)
171{
172 struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
173 const struct msm_pingroup *g;
174 unsigned long flags;
175 u32 val;
176
177 g = &pctrl->soc->groups[group];
178
179 if (WARN_ON(g->mux_bit < 0))
180 return;
181
182 spin_lock_irqsave(&pctrl->lock, flags);
183
184 /* Clear the mux bits to select gpio mode */
185 val = readl(pctrl->regs + g->ctl_reg);
186 val &= ~(0x7 << g->mux_bit);
187 writel(val, pctrl->regs + g->ctl_reg);
188
189 spin_unlock_irqrestore(&pctrl->lock, flags);
190}
191
192static const struct pinmux_ops msm_pinmux_ops = { 170static const struct pinmux_ops msm_pinmux_ops = {
193 .get_functions_count = msm_get_functions_count, 171 .get_functions_count = msm_get_functions_count,
194 .get_function_name = msm_get_function_name, 172 .get_function_name = msm_get_function_name,
195 .get_function_groups = msm_get_function_groups, 173 .get_function_groups = msm_get_function_groups,
196 .enable = msm_pinmux_enable, 174 .set_mux = msm_pinmux_set_mux,
197 .disable = msm_pinmux_disable,
198}; 175};
199 176
200static int msm_config_reg(struct msm_pinctrl *pctrl, 177static int msm_config_reg(struct msm_pinctrl *pctrl,
@@ -206,6 +183,7 @@ static int msm_config_reg(struct msm_pinctrl *pctrl,
206 switch (param) { 183 switch (param) {
207 case PIN_CONFIG_BIAS_DISABLE: 184 case PIN_CONFIG_BIAS_DISABLE:
208 case PIN_CONFIG_BIAS_PULL_DOWN: 185 case PIN_CONFIG_BIAS_PULL_DOWN:
186 case PIN_CONFIG_BIAS_BUS_HOLD:
209 case PIN_CONFIG_BIAS_PULL_UP: 187 case PIN_CONFIG_BIAS_PULL_UP:
210 *bit = g->pull_bit; 188 *bit = g->pull_bit;
211 *mask = 3; 189 *mask = 3;
@@ -243,6 +221,7 @@ static int msm_config_set(struct pinctrl_dev *pctldev, unsigned int pin,
243 221
244#define MSM_NO_PULL 0 222#define MSM_NO_PULL 0
245#define MSM_PULL_DOWN 1 223#define MSM_PULL_DOWN 1
224#define MSM_KEEPER 2
246#define MSM_PULL_UP 3 225#define MSM_PULL_UP 3
247 226
248static unsigned msm_regval_to_drive(u32 val) 227static unsigned msm_regval_to_drive(u32 val)
@@ -280,6 +259,9 @@ static int msm_config_group_get(struct pinctrl_dev *pctldev,
280 case PIN_CONFIG_BIAS_PULL_DOWN: 259 case PIN_CONFIG_BIAS_PULL_DOWN:
281 arg = arg == MSM_PULL_DOWN; 260 arg = arg == MSM_PULL_DOWN;
282 break; 261 break;
262 case PIN_CONFIG_BIAS_BUS_HOLD:
263 arg = arg == MSM_KEEPER;
264 break;
283 case PIN_CONFIG_BIAS_PULL_UP: 265 case PIN_CONFIG_BIAS_PULL_UP:
284 arg = arg == MSM_PULL_UP; 266 arg = arg == MSM_PULL_UP;
285 break; 267 break;
@@ -339,6 +321,9 @@ static int msm_config_group_set(struct pinctrl_dev *pctldev,
339 case PIN_CONFIG_BIAS_PULL_DOWN: 321 case PIN_CONFIG_BIAS_PULL_DOWN:
340 arg = MSM_PULL_DOWN; 322 arg = MSM_PULL_DOWN;
341 break; 323 break;
324 case PIN_CONFIG_BIAS_BUS_HOLD:
325 arg = MSM_KEEPER;
326 break;
342 case PIN_CONFIG_BIAS_PULL_UP: 327 case PIN_CONFIG_BIAS_PULL_UP:
343 arg = MSM_PULL_UP; 328 arg = MSM_PULL_UP;
344 break; 329 break;
@@ -669,8 +654,6 @@ static void msm_gpio_irq_ack(struct irq_data *d)
669 spin_unlock_irqrestore(&pctrl->lock, flags); 654 spin_unlock_irqrestore(&pctrl->lock, flags);
670} 655}
671 656
672#define INTR_TARGET_PROC_APPS 4
673
674static int msm_gpio_irq_set_type(struct irq_data *d, unsigned int type) 657static int msm_gpio_irq_set_type(struct irq_data *d, unsigned int type)
675{ 658{
676 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 659 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
@@ -694,7 +677,7 @@ static int msm_gpio_irq_set_type(struct irq_data *d, unsigned int type)
694 /* Route interrupts to application cpu */ 677 /* Route interrupts to application cpu */
695 val = readl(pctrl->regs + g->intr_target_reg); 678 val = readl(pctrl->regs + g->intr_target_reg);
696 val &= ~(7 << g->intr_target_bit); 679 val &= ~(7 << g->intr_target_bit);
697 val |= INTR_TARGET_PROC_APPS << g->intr_target_bit; 680 val |= g->intr_target_kpss_val << g->intr_target_bit;
698 writel(val, pctrl->regs + g->intr_target_reg); 681 writel(val, pctrl->regs + g->intr_target_reg);
699 682
700 /* Update configuration for gpio. 683 /* Update configuration for gpio.
@@ -849,6 +832,7 @@ static int msm_gpio_init(struct msm_pinctrl *pctrl)
849 ret = gpiochip_add_pin_range(&pctrl->chip, dev_name(pctrl->dev), 0, 0, chip->ngpio); 832 ret = gpiochip_add_pin_range(&pctrl->chip, dev_name(pctrl->dev), 0, 0, chip->ngpio);
850 if (ret) { 833 if (ret) {
851 dev_err(pctrl->dev, "Failed to add pin range\n"); 834 dev_err(pctrl->dev, "Failed to add pin range\n");
835 gpiochip_remove(&pctrl->chip);
852 return ret; 836 return ret;
853 } 837 }
854 838
@@ -859,6 +843,7 @@ static int msm_gpio_init(struct msm_pinctrl *pctrl)
859 IRQ_TYPE_NONE); 843 IRQ_TYPE_NONE);
860 if (ret) { 844 if (ret) {
861 dev_err(pctrl->dev, "Failed to add irqchip to gpiochip\n"); 845 dev_err(pctrl->dev, "Failed to add irqchip to gpiochip\n");
846 gpiochip_remove(&pctrl->chip);
862 return -ENOSYS; 847 return -ENOSYS;
863 } 848 }
864 849
@@ -868,6 +853,32 @@ static int msm_gpio_init(struct msm_pinctrl *pctrl)
868 return 0; 853 return 0;
869} 854}
870 855
856static int msm_ps_hold_restart(struct notifier_block *nb, unsigned long action,
857 void *data)
858{
859 struct msm_pinctrl *pctrl = container_of(nb, struct msm_pinctrl, restart_nb);
860
861 writel(0, pctrl->regs + PS_HOLD_OFFSET);
862 mdelay(1000);
863 return NOTIFY_DONE;
864}
865
866static void msm_pinctrl_setup_pm_reset(struct msm_pinctrl *pctrl)
867{
868 int i = 0;
869 const struct msm_function *func = pctrl->soc->functions;
870
871 for (; i <= pctrl->soc->nfunctions; i++)
872 if (!strcmp(func[i].name, "ps_hold")) {
873 pctrl->restart_nb.notifier_call = msm_ps_hold_restart;
874 pctrl->restart_nb.priority = 128;
875 if (register_restart_handler(&pctrl->restart_nb))
876 dev_err(pctrl->dev,
877 "failed to setup restart handler.\n");
878 break;
879 }
880}
881
871int msm_pinctrl_probe(struct platform_device *pdev, 882int msm_pinctrl_probe(struct platform_device *pdev,
872 const struct msm_pinctrl_soc_data *soc_data) 883 const struct msm_pinctrl_soc_data *soc_data)
873{ 884{
@@ -891,6 +902,8 @@ int msm_pinctrl_probe(struct platform_device *pdev,
891 if (IS_ERR(pctrl->regs)) 902 if (IS_ERR(pctrl->regs))
892 return PTR_ERR(pctrl->regs); 903 return PTR_ERR(pctrl->regs);
893 904
905 msm_pinctrl_setup_pm_reset(pctrl);
906
894 pctrl->irq = platform_get_irq(pdev, 0); 907 pctrl->irq = platform_get_irq(pdev, 0);
895 if (pctrl->irq < 0) { 908 if (pctrl->irq < 0) {
896 dev_err(&pdev->dev, "No interrupt defined for msmgpio\n"); 909 dev_err(&pdev->dev, "No interrupt defined for msmgpio\n");
@@ -923,16 +936,12 @@ EXPORT_SYMBOL(msm_pinctrl_probe);
923int msm_pinctrl_remove(struct platform_device *pdev) 936int msm_pinctrl_remove(struct platform_device *pdev)
924{ 937{
925 struct msm_pinctrl *pctrl = platform_get_drvdata(pdev); 938 struct msm_pinctrl *pctrl = platform_get_drvdata(pdev);
926 int ret;
927
928 ret = gpiochip_remove(&pctrl->chip);
929 if (ret) {
930 dev_err(&pdev->dev, "Failed to remove gpiochip\n");
931 return ret;
932 }
933 939
940 gpiochip_remove(&pctrl->chip);
934 pinctrl_unregister(pctrl->pctrl); 941 pinctrl_unregister(pctrl->pctrl);
935 942
943 unregister_restart_handler(&pctrl->restart_nb);
944
936 return 0; 945 return 0;
937} 946}
938EXPORT_SYMBOL(msm_pinctrl_remove); 947EXPORT_SYMBOL(msm_pinctrl_remove);
diff --git a/drivers/pinctrl/pinctrl-msm.h b/drivers/pinctrl/qcom/pinctrl-msm.h
index 7b2a227a590a..b952c4b4a8e9 100644
--- a/drivers/pinctrl/pinctrl-msm.h
+++ b/drivers/pinctrl/qcom/pinctrl-msm.h
@@ -53,6 +53,8 @@ struct msm_function {
53 * @intr_status_bit: Offset in @intr_status_reg for reading and acking the interrupt 53 * @intr_status_bit: Offset in @intr_status_reg for reading and acking the interrupt
54 * status. 54 * status.
55 * @intr_target_bit: Offset in @intr_target_reg for configuring the interrupt routing. 55 * @intr_target_bit: Offset in @intr_target_reg for configuring the interrupt routing.
56 * @intr_target_kpss_val: Value in @intr_target_bit for specifying that the interrupt from
57 * this gpio should get routed to the KPSS processor.
56 * @intr_raw_status_bit: Offset in @intr_cfg_reg for the raw status bit. 58 * @intr_raw_status_bit: Offset in @intr_cfg_reg for the raw status bit.
57 * @intr_polarity_bit: Offset in @intr_cfg_reg for specifying polarity of the interrupt. 59 * @intr_polarity_bit: Offset in @intr_cfg_reg for specifying polarity of the interrupt.
58 * @intr_detection_bit: Offset in @intr_cfg_reg for specifying interrupt type. 60 * @intr_detection_bit: Offset in @intr_cfg_reg for specifying interrupt type.
@@ -88,6 +90,7 @@ struct msm_pingroup {
88 unsigned intr_ack_high:1; 90 unsigned intr_ack_high:1;
89 91
90 unsigned intr_target_bit:5; 92 unsigned intr_target_bit:5;
93 unsigned intr_target_kpss_val:5;
91 unsigned intr_raw_status_bit:5; 94 unsigned intr_raw_status_bit:5;
92 unsigned intr_polarity_bit:5; 95 unsigned intr_polarity_bit:5;
93 unsigned intr_detection_bit:5; 96 unsigned intr_detection_bit:5;
diff --git a/drivers/pinctrl/qcom/pinctrl-msm8960.c b/drivers/pinctrl/qcom/pinctrl-msm8960.c
new file mode 100644
index 000000000000..2ab21ce5575a
--- /dev/null
+++ b/drivers/pinctrl/qcom/pinctrl-msm8960.c
@@ -0,0 +1,1284 @@
1/*
2 * Copyright (c) 2014, Sony Mobile Communications AB.
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 and
6 * only version 2 as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
12 */
13
14#include <linux/module.h>
15#include <linux/of.h>
16#include <linux/platform_device.h>
17#include <linux/pinctrl/pinctrl.h>
18#include <linux/pinctrl/pinmux.h>
19
20#include "pinctrl-msm.h"
21
22static const struct pinctrl_pin_desc msm8960_pins[] = {
23 PINCTRL_PIN(0, "GPIO_0"),
24 PINCTRL_PIN(1, "GPIO_1"),
25 PINCTRL_PIN(2, "GPIO_2"),
26 PINCTRL_PIN(3, "GPIO_3"),
27 PINCTRL_PIN(4, "GPIO_4"),
28 PINCTRL_PIN(5, "GPIO_5"),
29 PINCTRL_PIN(6, "GPIO_6"),
30 PINCTRL_PIN(7, "GPIO_7"),
31 PINCTRL_PIN(8, "GPIO_8"),
32 PINCTRL_PIN(9, "GPIO_9"),
33 PINCTRL_PIN(10, "GPIO_10"),
34 PINCTRL_PIN(11, "GPIO_11"),
35 PINCTRL_PIN(12, "GPIO_12"),
36 PINCTRL_PIN(13, "GPIO_13"),
37 PINCTRL_PIN(14, "GPIO_14"),
38 PINCTRL_PIN(15, "GPIO_15"),
39 PINCTRL_PIN(16, "GPIO_16"),
40 PINCTRL_PIN(17, "GPIO_17"),
41 PINCTRL_PIN(18, "GPIO_18"),
42 PINCTRL_PIN(19, "GPIO_19"),
43 PINCTRL_PIN(20, "GPIO_20"),
44 PINCTRL_PIN(21, "GPIO_21"),
45 PINCTRL_PIN(22, "GPIO_22"),
46 PINCTRL_PIN(23, "GPIO_23"),
47 PINCTRL_PIN(24, "GPIO_24"),
48 PINCTRL_PIN(25, "GPIO_25"),
49 PINCTRL_PIN(26, "GPIO_26"),
50 PINCTRL_PIN(27, "GPIO_27"),
51 PINCTRL_PIN(28, "GPIO_28"),
52 PINCTRL_PIN(29, "GPIO_29"),
53 PINCTRL_PIN(30, "GPIO_30"),
54 PINCTRL_PIN(31, "GPIO_31"),
55 PINCTRL_PIN(32, "GPIO_32"),
56 PINCTRL_PIN(33, "GPIO_33"),
57 PINCTRL_PIN(34, "GPIO_34"),
58 PINCTRL_PIN(35, "GPIO_35"),
59 PINCTRL_PIN(36, "GPIO_36"),
60 PINCTRL_PIN(37, "GPIO_37"),
61 PINCTRL_PIN(38, "GPIO_38"),
62 PINCTRL_PIN(39, "GPIO_39"),
63 PINCTRL_PIN(40, "GPIO_40"),
64 PINCTRL_PIN(41, "GPIO_41"),
65 PINCTRL_PIN(42, "GPIO_42"),
66 PINCTRL_PIN(43, "GPIO_43"),
67 PINCTRL_PIN(44, "GPIO_44"),
68 PINCTRL_PIN(45, "GPIO_45"),
69 PINCTRL_PIN(46, "GPIO_46"),
70 PINCTRL_PIN(47, "GPIO_47"),
71 PINCTRL_PIN(48, "GPIO_48"),
72 PINCTRL_PIN(49, "GPIO_49"),
73 PINCTRL_PIN(50, "GPIO_50"),
74 PINCTRL_PIN(51, "GPIO_51"),
75 PINCTRL_PIN(52, "GPIO_52"),
76 PINCTRL_PIN(53, "GPIO_53"),
77 PINCTRL_PIN(54, "GPIO_54"),
78 PINCTRL_PIN(55, "GPIO_55"),
79 PINCTRL_PIN(56, "GPIO_56"),
80 PINCTRL_PIN(57, "GPIO_57"),
81 PINCTRL_PIN(58, "GPIO_58"),
82 PINCTRL_PIN(59, "GPIO_59"),
83 PINCTRL_PIN(60, "GPIO_60"),
84 PINCTRL_PIN(61, "GPIO_61"),
85 PINCTRL_PIN(62, "GPIO_62"),
86 PINCTRL_PIN(63, "GPIO_63"),
87 PINCTRL_PIN(64, "GPIO_64"),
88 PINCTRL_PIN(65, "GPIO_65"),
89 PINCTRL_PIN(66, "GPIO_66"),
90 PINCTRL_PIN(67, "GPIO_67"),
91 PINCTRL_PIN(68, "GPIO_68"),
92 PINCTRL_PIN(69, "GPIO_69"),
93 PINCTRL_PIN(70, "GPIO_70"),
94 PINCTRL_PIN(71, "GPIO_71"),
95 PINCTRL_PIN(72, "GPIO_72"),
96 PINCTRL_PIN(73, "GPIO_73"),
97 PINCTRL_PIN(74, "GPIO_74"),
98 PINCTRL_PIN(75, "GPIO_75"),
99 PINCTRL_PIN(76, "GPIO_76"),
100 PINCTRL_PIN(77, "GPIO_77"),
101 PINCTRL_PIN(78, "GPIO_78"),
102 PINCTRL_PIN(79, "GPIO_79"),
103 PINCTRL_PIN(80, "GPIO_80"),
104 PINCTRL_PIN(81, "GPIO_81"),
105 PINCTRL_PIN(82, "GPIO_82"),
106 PINCTRL_PIN(83, "GPIO_83"),
107 PINCTRL_PIN(84, "GPIO_84"),
108 PINCTRL_PIN(85, "GPIO_85"),
109 PINCTRL_PIN(86, "GPIO_86"),
110 PINCTRL_PIN(87, "GPIO_87"),
111 PINCTRL_PIN(88, "GPIO_88"),
112 PINCTRL_PIN(89, "GPIO_89"),
113 PINCTRL_PIN(90, "GPIO_90"),
114 PINCTRL_PIN(91, "GPIO_91"),
115 PINCTRL_PIN(92, "GPIO_92"),
116 PINCTRL_PIN(93, "GPIO_93"),
117 PINCTRL_PIN(94, "GPIO_94"),
118 PINCTRL_PIN(95, "GPIO_95"),
119 PINCTRL_PIN(96, "GPIO_96"),
120 PINCTRL_PIN(97, "GPIO_97"),
121 PINCTRL_PIN(98, "GPIO_98"),
122 PINCTRL_PIN(99, "GPIO_99"),
123 PINCTRL_PIN(100, "GPIO_100"),
124 PINCTRL_PIN(101, "GPIO_101"),
125 PINCTRL_PIN(102, "GPIO_102"),
126 PINCTRL_PIN(103, "GPIO_103"),
127 PINCTRL_PIN(104, "GPIO_104"),
128 PINCTRL_PIN(105, "GPIO_105"),
129 PINCTRL_PIN(106, "GPIO_106"),
130 PINCTRL_PIN(107, "GPIO_107"),
131 PINCTRL_PIN(108, "GPIO_108"),
132 PINCTRL_PIN(109, "GPIO_109"),
133 PINCTRL_PIN(110, "GPIO_110"),
134 PINCTRL_PIN(111, "GPIO_111"),
135 PINCTRL_PIN(112, "GPIO_112"),
136 PINCTRL_PIN(113, "GPIO_113"),
137 PINCTRL_PIN(114, "GPIO_114"),
138 PINCTRL_PIN(115, "GPIO_115"),
139 PINCTRL_PIN(116, "GPIO_116"),
140 PINCTRL_PIN(117, "GPIO_117"),
141 PINCTRL_PIN(118, "GPIO_118"),
142 PINCTRL_PIN(119, "GPIO_119"),
143 PINCTRL_PIN(120, "GPIO_120"),
144 PINCTRL_PIN(121, "GPIO_121"),
145 PINCTRL_PIN(122, "GPIO_122"),
146 PINCTRL_PIN(123, "GPIO_123"),
147 PINCTRL_PIN(124, "GPIO_124"),
148 PINCTRL_PIN(125, "GPIO_125"),
149 PINCTRL_PIN(126, "GPIO_126"),
150 PINCTRL_PIN(127, "GPIO_127"),
151 PINCTRL_PIN(128, "GPIO_128"),
152 PINCTRL_PIN(129, "GPIO_129"),
153 PINCTRL_PIN(130, "GPIO_130"),
154 PINCTRL_PIN(131, "GPIO_131"),
155 PINCTRL_PIN(132, "GPIO_132"),
156 PINCTRL_PIN(133, "GPIO_133"),
157 PINCTRL_PIN(134, "GPIO_134"),
158 PINCTRL_PIN(135, "GPIO_135"),
159 PINCTRL_PIN(136, "GPIO_136"),
160 PINCTRL_PIN(137, "GPIO_137"),
161 PINCTRL_PIN(138, "GPIO_138"),
162 PINCTRL_PIN(139, "GPIO_139"),
163 PINCTRL_PIN(140, "GPIO_140"),
164 PINCTRL_PIN(141, "GPIO_141"),
165 PINCTRL_PIN(142, "GPIO_142"),
166 PINCTRL_PIN(143, "GPIO_143"),
167 PINCTRL_PIN(144, "GPIO_144"),
168 PINCTRL_PIN(145, "GPIO_145"),
169 PINCTRL_PIN(146, "GPIO_146"),
170 PINCTRL_PIN(147, "GPIO_147"),
171 PINCTRL_PIN(148, "GPIO_148"),
172 PINCTRL_PIN(149, "GPIO_149"),
173 PINCTRL_PIN(150, "GPIO_150"),
174 PINCTRL_PIN(151, "GPIO_151"),
175
176 PINCTRL_PIN(152, "SDC1_CLK"),
177 PINCTRL_PIN(153, "SDC1_CMD"),
178 PINCTRL_PIN(154, "SDC1_DATA"),
179 PINCTRL_PIN(155, "SDC3_CLK"),
180 PINCTRL_PIN(156, "SDC3_CMD"),
181 PINCTRL_PIN(157, "SDC3_DATA"),
182};
183
184#define DECLARE_MSM_GPIO_PINS(pin) static const unsigned int gpio##pin##_pins[] = { pin }
185DECLARE_MSM_GPIO_PINS(0);
186DECLARE_MSM_GPIO_PINS(1);
187DECLARE_MSM_GPIO_PINS(2);
188DECLARE_MSM_GPIO_PINS(3);
189DECLARE_MSM_GPIO_PINS(4);
190DECLARE_MSM_GPIO_PINS(5);
191DECLARE_MSM_GPIO_PINS(6);
192DECLARE_MSM_GPIO_PINS(7);
193DECLARE_MSM_GPIO_PINS(8);
194DECLARE_MSM_GPIO_PINS(9);
195DECLARE_MSM_GPIO_PINS(10);
196DECLARE_MSM_GPIO_PINS(11);
197DECLARE_MSM_GPIO_PINS(12);
198DECLARE_MSM_GPIO_PINS(13);
199DECLARE_MSM_GPIO_PINS(14);
200DECLARE_MSM_GPIO_PINS(15);
201DECLARE_MSM_GPIO_PINS(16);
202DECLARE_MSM_GPIO_PINS(17);
203DECLARE_MSM_GPIO_PINS(18);
204DECLARE_MSM_GPIO_PINS(19);
205DECLARE_MSM_GPIO_PINS(20);
206DECLARE_MSM_GPIO_PINS(21);
207DECLARE_MSM_GPIO_PINS(22);
208DECLARE_MSM_GPIO_PINS(23);
209DECLARE_MSM_GPIO_PINS(24);
210DECLARE_MSM_GPIO_PINS(25);
211DECLARE_MSM_GPIO_PINS(26);
212DECLARE_MSM_GPIO_PINS(27);
213DECLARE_MSM_GPIO_PINS(28);
214DECLARE_MSM_GPIO_PINS(29);
215DECLARE_MSM_GPIO_PINS(30);
216DECLARE_MSM_GPIO_PINS(31);
217DECLARE_MSM_GPIO_PINS(32);
218DECLARE_MSM_GPIO_PINS(33);
219DECLARE_MSM_GPIO_PINS(34);
220DECLARE_MSM_GPIO_PINS(35);
221DECLARE_MSM_GPIO_PINS(36);
222DECLARE_MSM_GPIO_PINS(37);
223DECLARE_MSM_GPIO_PINS(38);
224DECLARE_MSM_GPIO_PINS(39);
225DECLARE_MSM_GPIO_PINS(40);
226DECLARE_MSM_GPIO_PINS(41);
227DECLARE_MSM_GPIO_PINS(42);
228DECLARE_MSM_GPIO_PINS(43);
229DECLARE_MSM_GPIO_PINS(44);
230DECLARE_MSM_GPIO_PINS(45);
231DECLARE_MSM_GPIO_PINS(46);
232DECLARE_MSM_GPIO_PINS(47);
233DECLARE_MSM_GPIO_PINS(48);
234DECLARE_MSM_GPIO_PINS(49);
235DECLARE_MSM_GPIO_PINS(50);
236DECLARE_MSM_GPIO_PINS(51);
237DECLARE_MSM_GPIO_PINS(52);
238DECLARE_MSM_GPIO_PINS(53);
239DECLARE_MSM_GPIO_PINS(54);
240DECLARE_MSM_GPIO_PINS(55);
241DECLARE_MSM_GPIO_PINS(56);
242DECLARE_MSM_GPIO_PINS(57);
243DECLARE_MSM_GPIO_PINS(58);
244DECLARE_MSM_GPIO_PINS(59);
245DECLARE_MSM_GPIO_PINS(60);
246DECLARE_MSM_GPIO_PINS(61);
247DECLARE_MSM_GPIO_PINS(62);
248DECLARE_MSM_GPIO_PINS(63);
249DECLARE_MSM_GPIO_PINS(64);
250DECLARE_MSM_GPIO_PINS(65);
251DECLARE_MSM_GPIO_PINS(66);
252DECLARE_MSM_GPIO_PINS(67);
253DECLARE_MSM_GPIO_PINS(68);
254DECLARE_MSM_GPIO_PINS(69);
255DECLARE_MSM_GPIO_PINS(70);
256DECLARE_MSM_GPIO_PINS(71);
257DECLARE_MSM_GPIO_PINS(72);
258DECLARE_MSM_GPIO_PINS(73);
259DECLARE_MSM_GPIO_PINS(74);
260DECLARE_MSM_GPIO_PINS(75);
261DECLARE_MSM_GPIO_PINS(76);
262DECLARE_MSM_GPIO_PINS(77);
263DECLARE_MSM_GPIO_PINS(78);
264DECLARE_MSM_GPIO_PINS(79);
265DECLARE_MSM_GPIO_PINS(80);
266DECLARE_MSM_GPIO_PINS(81);
267DECLARE_MSM_GPIO_PINS(82);
268DECLARE_MSM_GPIO_PINS(83);
269DECLARE_MSM_GPIO_PINS(84);
270DECLARE_MSM_GPIO_PINS(85);
271DECLARE_MSM_GPIO_PINS(86);
272DECLARE_MSM_GPIO_PINS(87);
273DECLARE_MSM_GPIO_PINS(88);
274DECLARE_MSM_GPIO_PINS(89);
275DECLARE_MSM_GPIO_PINS(90);
276DECLARE_MSM_GPIO_PINS(91);
277DECLARE_MSM_GPIO_PINS(92);
278DECLARE_MSM_GPIO_PINS(93);
279DECLARE_MSM_GPIO_PINS(94);
280DECLARE_MSM_GPIO_PINS(95);
281DECLARE_MSM_GPIO_PINS(96);
282DECLARE_MSM_GPIO_PINS(97);
283DECLARE_MSM_GPIO_PINS(98);
284DECLARE_MSM_GPIO_PINS(99);
285DECLARE_MSM_GPIO_PINS(100);
286DECLARE_MSM_GPIO_PINS(101);
287DECLARE_MSM_GPIO_PINS(102);
288DECLARE_MSM_GPIO_PINS(103);
289DECLARE_MSM_GPIO_PINS(104);
290DECLARE_MSM_GPIO_PINS(105);
291DECLARE_MSM_GPIO_PINS(106);
292DECLARE_MSM_GPIO_PINS(107);
293DECLARE_MSM_GPIO_PINS(108);
294DECLARE_MSM_GPIO_PINS(109);
295DECLARE_MSM_GPIO_PINS(110);
296DECLARE_MSM_GPIO_PINS(111);
297DECLARE_MSM_GPIO_PINS(112);
298DECLARE_MSM_GPIO_PINS(113);
299DECLARE_MSM_GPIO_PINS(114);
300DECLARE_MSM_GPIO_PINS(115);
301DECLARE_MSM_GPIO_PINS(116);
302DECLARE_MSM_GPIO_PINS(117);
303DECLARE_MSM_GPIO_PINS(118);
304DECLARE_MSM_GPIO_PINS(119);
305DECLARE_MSM_GPIO_PINS(120);
306DECLARE_MSM_GPIO_PINS(121);
307DECLARE_MSM_GPIO_PINS(122);
308DECLARE_MSM_GPIO_PINS(123);
309DECLARE_MSM_GPIO_PINS(124);
310DECLARE_MSM_GPIO_PINS(125);
311DECLARE_MSM_GPIO_PINS(126);
312DECLARE_MSM_GPIO_PINS(127);
313DECLARE_MSM_GPIO_PINS(128);
314DECLARE_MSM_GPIO_PINS(129);
315DECLARE_MSM_GPIO_PINS(130);
316DECLARE_MSM_GPIO_PINS(131);
317DECLARE_MSM_GPIO_PINS(132);
318DECLARE_MSM_GPIO_PINS(133);
319DECLARE_MSM_GPIO_PINS(134);
320DECLARE_MSM_GPIO_PINS(135);
321DECLARE_MSM_GPIO_PINS(136);
322DECLARE_MSM_GPIO_PINS(137);
323DECLARE_MSM_GPIO_PINS(138);
324DECLARE_MSM_GPIO_PINS(139);
325DECLARE_MSM_GPIO_PINS(140);
326DECLARE_MSM_GPIO_PINS(141);
327DECLARE_MSM_GPIO_PINS(142);
328DECLARE_MSM_GPIO_PINS(143);
329DECLARE_MSM_GPIO_PINS(144);
330DECLARE_MSM_GPIO_PINS(145);
331DECLARE_MSM_GPIO_PINS(146);
332DECLARE_MSM_GPIO_PINS(147);
333DECLARE_MSM_GPIO_PINS(148);
334DECLARE_MSM_GPIO_PINS(149);
335DECLARE_MSM_GPIO_PINS(150);
336DECLARE_MSM_GPIO_PINS(151);
337
338static const unsigned int sdc1_clk_pins[] = { 152 };
339static const unsigned int sdc1_cmd_pins[] = { 153 };
340static const unsigned int sdc1_data_pins[] = { 154 };
341static const unsigned int sdc3_clk_pins[] = { 155 };
342static const unsigned int sdc3_cmd_pins[] = { 156 };
343static const unsigned int sdc3_data_pins[] = { 157 };
344
345#define FUNCTION(fname) \
346 [MSM_MUX_##fname] = { \
347 .name = #fname, \
348 .groups = fname##_groups, \
349 .ngroups = ARRAY_SIZE(fname##_groups), \
350 }
351
352#define PINGROUP(id, f1, f2, f3, f4, f5, f6, f7, f8, f9, f10, f11) \
353 { \
354 .name = "gpio" #id, \
355 .pins = gpio##id##_pins, \
356 .npins = ARRAY_SIZE(gpio##id##_pins), \
357 .funcs = (int[]){ \
358 MSM_MUX_gpio, \
359 MSM_MUX_##f1, \
360 MSM_MUX_##f2, \
361 MSM_MUX_##f3, \
362 MSM_MUX_##f4, \
363 MSM_MUX_##f5, \
364 MSM_MUX_##f6, \
365 MSM_MUX_##f7, \
366 MSM_MUX_##f8, \
367 MSM_MUX_##f9, \
368 MSM_MUX_##f10, \
369 MSM_MUX_##f11 \
370 }, \
371 .nfuncs = 12, \
372 .ctl_reg = 0x1000 + 0x10 * id, \
373 .io_reg = 0x1004 + 0x10 * id, \
374 .intr_cfg_reg = 0x1008 + 0x10 * id, \
375 .intr_status_reg = 0x100c + 0x10 * id, \
376 .intr_target_reg = 0x400 + 0x4 * id, \
377 .mux_bit = 2, \
378 .pull_bit = 0, \
379 .drv_bit = 6, \
380 .oe_bit = 9, \
381 .in_bit = 0, \
382 .out_bit = 1, \
383 .intr_enable_bit = 0, \
384 .intr_status_bit = 0, \
385 .intr_ack_high = 1, \
386 .intr_target_bit = 0, \
387 .intr_target_kpss_val = 4, \
388 .intr_raw_status_bit = 3, \
389 .intr_polarity_bit = 1, \
390 .intr_detection_bit = 2, \
391 .intr_detection_width = 1, \
392 }
393
394#define SDC_PINGROUP(pg_name, ctl, pull, drv) \
395 { \
396 .name = #pg_name, \
397 .pins = pg_name##_pins, \
398 .npins = ARRAY_SIZE(pg_name##_pins), \
399 .ctl_reg = ctl, \
400 .io_reg = 0, \
401 .intr_cfg_reg = 0, \
402 .intr_status_reg = 0, \
403 .intr_target_reg = 0, \
404 .mux_bit = -1, \
405 .pull_bit = pull, \
406 .drv_bit = drv, \
407 .oe_bit = -1, \
408 .in_bit = -1, \
409 .out_bit = -1, \
410 .intr_enable_bit = -1, \
411 .intr_status_bit = -1, \
412 .intr_target_bit = -1, \
413 .intr_target_kpss_val = -1, \
414 .intr_raw_status_bit = -1, \
415 .intr_polarity_bit = -1, \
416 .intr_detection_bit = -1, \
417 .intr_detection_width = -1, \
418 }
419
420enum msm8960_functions {
421 MSM_MUX_audio_pcm,
422 MSM_MUX_bt,
423 MSM_MUX_cam_mclk0,
424 MSM_MUX_cam_mclk1,
425 MSM_MUX_cam_mclk2,
426 MSM_MUX_codec_mic_i2s,
427 MSM_MUX_codec_spkr_i2s,
428 MSM_MUX_ext_gps,
429 MSM_MUX_fm,
430 MSM_MUX_gps_blanking,
431 MSM_MUX_gps_pps_in,
432 MSM_MUX_gps_pps_out,
433 MSM_MUX_gp_clk_0a,
434 MSM_MUX_gp_clk_0b,
435 MSM_MUX_gp_clk_1a,
436 MSM_MUX_gp_clk_1b,
437 MSM_MUX_gp_clk_2a,
438 MSM_MUX_gp_clk_2b,
439 MSM_MUX_gp_mn,
440 MSM_MUX_gp_pdm_0a,
441 MSM_MUX_gp_pdm_0b,
442 MSM_MUX_gp_pdm_1a,
443 MSM_MUX_gp_pdm_1b,
444 MSM_MUX_gp_pdm_2a,
445 MSM_MUX_gp_pdm_2b,
446 MSM_MUX_gpio,
447 MSM_MUX_gsbi1,
448 MSM_MUX_gsbi1_spi_cs1_n,
449 MSM_MUX_gsbi1_spi_cs2a_n,
450 MSM_MUX_gsbi1_spi_cs2b_n,
451 MSM_MUX_gsbi1_spi_cs3_n,
452 MSM_MUX_gsbi2,
453 MSM_MUX_gsbi2_spi_cs1_n,
454 MSM_MUX_gsbi2_spi_cs2_n,
455 MSM_MUX_gsbi2_spi_cs3_n,
456 MSM_MUX_gsbi3,
457 MSM_MUX_gsbi4,
458 MSM_MUX_gsbi4_3d_cam_i2c_l,
459 MSM_MUX_gsbi4_3d_cam_i2c_r,
460 MSM_MUX_gsbi5,
461 MSM_MUX_gsbi5_3d_cam_i2c_l,
462 MSM_MUX_gsbi5_3d_cam_i2c_r,
463 MSM_MUX_gsbi6,
464 MSM_MUX_gsbi7,
465 MSM_MUX_gsbi8,
466 MSM_MUX_gsbi9,
467 MSM_MUX_gsbi10,
468 MSM_MUX_gsbi11,
469 MSM_MUX_gsbi11_spi_cs1a_n,
470 MSM_MUX_gsbi11_spi_cs1b_n,
471 MSM_MUX_gsbi11_spi_cs2a_n,
472 MSM_MUX_gsbi11_spi_cs2b_n,
473 MSM_MUX_gsbi11_spi_cs3_n,
474 MSM_MUX_gsbi12,
475 MSM_MUX_hdmi_cec,
476 MSM_MUX_hdmi_ddc_clock,
477 MSM_MUX_hdmi_ddc_data,
478 MSM_MUX_hdmi_hot_plug_detect,
479 MSM_MUX_hsic,
480 MSM_MUX_mdp_vsync,
481 MSM_MUX_mi2s,
482 MSM_MUX_mic_i2s,
483 MSM_MUX_pmb_clk,
484 MSM_MUX_pmb_ext_ctrl,
485 MSM_MUX_ps_hold,
486 MSM_MUX_rpm_wdog,
487 MSM_MUX_sdc2,
488 MSM_MUX_sdc4,
489 MSM_MUX_sdc5,
490 MSM_MUX_slimbus1,
491 MSM_MUX_slimbus2,
492 MSM_MUX_spkr_i2s,
493 MSM_MUX_ssbi1,
494 MSM_MUX_ssbi2,
495 MSM_MUX_ssbi_ext_gps,
496 MSM_MUX_ssbi_pmic2,
497 MSM_MUX_ssbi_qpa1,
498 MSM_MUX_ssbi_ts,
499 MSM_MUX_tsif1,
500 MSM_MUX_tsif2,
501 MSM_MUX_ts_eoc,
502 MSM_MUX_usb_fs1,
503 MSM_MUX_usb_fs1_oe,
504 MSM_MUX_usb_fs1_oe_n,
505 MSM_MUX_usb_fs2,
506 MSM_MUX_usb_fs2_oe,
507 MSM_MUX_usb_fs2_oe_n,
508 MSM_MUX_vfe_camif_timer1_a,
509 MSM_MUX_vfe_camif_timer1_b,
510 MSM_MUX_vfe_camif_timer2,
511 MSM_MUX_vfe_camif_timer3_a,
512 MSM_MUX_vfe_camif_timer3_b,
513 MSM_MUX_vfe_camif_timer4_a,
514 MSM_MUX_vfe_camif_timer4_b,
515 MSM_MUX_vfe_camif_timer4_c,
516 MSM_MUX_vfe_camif_timer5_a,
517 MSM_MUX_vfe_camif_timer5_b,
518 MSM_MUX_vfe_camif_timer6_a,
519 MSM_MUX_vfe_camif_timer6_b,
520 MSM_MUX_vfe_camif_timer6_c,
521 MSM_MUX_vfe_camif_timer7_a,
522 MSM_MUX_vfe_camif_timer7_b,
523 MSM_MUX_vfe_camif_timer7_c,
524 MSM_MUX_wlan,
525 MSM_MUX_NA,
526};
527
528static const char * const audio_pcm_groups[] = {
529 "gpio63", "gpio64", "gpio65", "gpio66"
530};
531
532static const char * const bt_groups[] = {
533 "gpio28", "gpio29", "gpio83"
534};
535
536static const char * const cam_mclk0_groups[] = {
537 "gpio5"
538};
539
540static const char * const cam_mclk1_groups[] = {
541 "gpio4"
542};
543
544static const char * const cam_mclk2_groups[] = {
545 "gpio2"
546};
547
548static const char * const codec_mic_i2s_groups[] = {
549 "gpio54", "gpio55", "gpio56", "gpio57", "gpio58"
550};
551
552static const char * const codec_spkr_i2s_groups[] = {
553 "gpio59", "gpio60", "gpio61", "gpio62"
554};
555
556static const char * const ext_gps_groups[] = {
557 "gpio22", "gpio23", "gpio24", "gpio25"
558};
559
560static const char * const fm_groups[] = {
561 "gpio26", "gpio27"
562};
563
564static const char * const gps_blanking_groups[] = {
565 "gpio137"
566};
567
568static const char * const gps_pps_in_groups[] = {
569 "gpio37"
570};
571
572static const char * const gps_pps_out_groups[] = {
573 "gpio37"
574};
575
576static const char * const gp_clk_0a_groups[] = {
577 "gpio3"
578};
579
580static const char * const gp_clk_0b_groups[] = {
581 "gpio54"
582};
583
584static const char * const gp_clk_1a_groups[] = {
585 "gpio4"
586};
587
588static const char * const gp_clk_1b_groups[] = {
589 "gpio70"
590};
591
592static const char * const gp_clk_2a_groups[] = {
593 "gpio52"
594};
595
596static const char * const gp_clk_2b_groups[] = {
597 "gpio37"
598};
599
600static const char * const gp_mn_groups[] = {
601 "gpio2"
602};
603
604static const char * const gp_pdm_0a_groups[] = {
605 "gpio58"
606};
607
608static const char * const gp_pdm_0b_groups[] = {
609 "gpio39"
610};
611
612static const char * const gp_pdm_1a_groups[] = {
613 "gpio94"
614};
615
616static const char * const gp_pdm_1b_groups[] = {
617 "gpio64"
618};
619
620static const char * const gp_pdm_2a_groups[] = {
621 "gpio69"
622};
623
624static const char * const gp_pdm_2b_groups[] = {
625 "gpio53"
626};
627
628static const char * const gpio_groups[] = {
629 "gpio0", "gpio1", "gpio2", "gpio3", "gpio4", "gpio5", "gpio6", "gpio7",
630 "gpio8", "gpio9", "gpio10", "gpio11", "gpio12", "gpio13", "gpio14",
631 "gpio15", "gpio16", "gpio17", "gpio18", "gpio19", "gpio20", "gpio21",
632 "gpio22", "gpio23", "gpio24", "gpio25", "gpio26", "gpio27", "gpio28",
633 "gpio29", "gpio30", "gpio31", "gpio32", "gpio33", "gpio34", "gpio35",
634 "gpio36", "gpio37", "gpio38", "gpio39", "gpio40", "gpio41", "gpio42",
635 "gpio43", "gpio44", "gpio45", "gpio46", "gpio47", "gpio48", "gpio49",
636 "gpio50", "gpio51", "gpio52", "gpio53", "gpio54", "gpio55", "gpio56",
637 "gpio57", "gpio58", "gpio59", "gpio60", "gpio61", "gpio62", "gpio63",
638 "gpio64", "gpio65", "gpio66", "gpio67", "gpio68", "gpio69", "gpio70",
639 "gpio71", "gpio72", "gpio73", "gpio74", "gpio75", "gpio76", "gpio77",
640 "gpio78", "gpio79", "gpio80", "gpio81", "gpio82", "gpio83", "gpio84",
641 "gpio85", "gpio86", "gpio87", "gpio88", "gpio89", "gpio90", "gpio91",
642 "gpio92", "gpio93", "gpio94", "gpio95", "gpio96", "gpio97", "gpio98",
643 "gpio99", "gpio100", "gpio101", "gpio102", "gpio103", "gpio104",
644 "gpio105", "gpio106", "gpio107", "gpio108", "gpio109", "gpio110",
645 "gpio111", "gpio112", "gpio113", "gpio114", "gpio115", "gpio116",
646 "gpio117", "gpio118", "gpio119", "gpio120", "gpio121", "gpio122",
647 "gpio123", "gpio124", "gpio125", "gpio126", "gpio127", "gpio128",
648 "gpio129", "gpio130", "gpio131", "gpio132", "gpio133", "gpio134",
649 "gpio135", "gpio136", "gpio137", "gpio138", "gpio139", "gpio140",
650 "gpio141", "gpio142", "gpio143", "gpio144", "gpio145", "gpio146",
651 "gpio147", "gpio148", "gpio149", "gpio150", "gpio151"
652};
653
654static const char * const gsbi1_groups[] = {
655 "gpio6", "gpio7", "gpio8", "gpio9"
656};
657
658static const char * const gsbi1_spi_cs1_n_groups[] = {
659 "gpio14"
660};
661
662static const char * const gsbi1_spi_cs2a_n_groups[] = {
663 "gpio15"
664};
665
666static const char * const gsbi1_spi_cs2b_n_groups[] = {
667 "gpio17"
668};
669
670static const char * const gsbi1_spi_cs3_n_groups[] = {
671 "gpio16"
672};
673
674static const char * const gsbi2_groups[] = {
675 "gpio10", "gpio11", "gpio12", "gpio13"
676};
677
678static const char * const gsbi2_spi_cs1_n_groups[] = {
679 "gpio52"
680};
681
682static const char * const gsbi2_spi_cs2_n_groups[] = {
683 "gpio68"
684};
685
686static const char * const gsbi2_spi_cs3_n_groups[] = {
687 "gpio56"
688};
689
690static const char * const gsbi3_groups[] = {
691 "gpio14", "gpio15", "gpio16", "gpio17"
692};
693
694static const char * const gsbi4_groups[] = {
695 "gpio18", "gpio19", "gpio20", "gpio21"
696};
697
698static const char * const gsbi4_3d_cam_i2c_l_groups[] = {
699 "gpio18", "gpio19"
700};
701
702static const char * const gsbi4_3d_cam_i2c_r_groups[] = {
703 "gpio20", "gpio21"
704};
705
706static const char * const gsbi5_groups[] = {
707 "gpio22", "gpio23", "gpio24", "gpio25"
708};
709
710static const char * const gsbi5_3d_cam_i2c_l_groups[] = {
711 "gpio22", "gpio23"
712};
713
714static const char * const gsbi5_3d_cam_i2c_r_groups[] = {
715 "gpio24", "gpio25"
716};
717
718static const char * const gsbi6_groups[] = {
719 "gpio26", "gpio27", "gpio28", "gpio29"
720};
721
722static const char * const gsbi7_groups[] = {
723 "gpio30", "gpio31", "gpio32", "gpio33"
724};
725
726static const char * const gsbi8_groups[] = {
727 "gpio34", "gpio35", "gpio36", "gpio37"
728};
729
730static const char * const gsbi9_groups[] = {
731 "gpio93", "gpio94", "gpio95", "gpio96"
732};
733
734static const char * const gsbi10_groups[] = {
735 "gpio71", "gpio72", "gpio73", "gpio74"
736};
737
738static const char * const gsbi11_groups[] = {
739 "gpio38", "gpio39", "gpio40", "gpio41"
740};
741
742static const char * const gsbi11_spi_cs1a_n_groups[] = {
743 "gpio36"
744};
745
746static const char * const gsbi11_spi_cs1b_n_groups[] = {
747 "gpio18"
748};
749
750static const char * const gsbi11_spi_cs2a_n_groups[] = {
751 "gpio37"
752};
753
754static const char * const gsbi11_spi_cs2b_n_groups[] = {
755 "gpio19"
756};
757
758static const char * const gsbi11_spi_cs3_n_groups[] = {
759 "gpio76"
760};
761
762static const char * const gsbi12_groups[] = {
763 "gpio42", "gpio43", "gpio44", "gpio45"
764};
765
766static const char * const hdmi_cec_groups[] = {
767 "gpio99"
768};
769
770static const char * const hdmi_ddc_clock_groups[] = {
771 "gpio100"
772};
773
774static const char * const hdmi_ddc_data_groups[] = {
775 "gpio101"
776};
777
778static const char * const hdmi_hot_plug_detect_groups[] = {
779 "gpio102"
780};
781
782static const char * const hsic_groups[] = {
783 "gpio150", "gpio151"
784};
785
786static const char * const mdp_vsync_groups[] = {
787 "gpio0", "gpio1", "gpio19"
788};
789
790static const char * const mi2s_groups[] = {
791 "gpio47", "gpio48", "gpio49", "gpio50", "gpio51", "gpio52", "gpio53"
792};
793
794static const char * const mic_i2s_groups[] = {
795 "gpio71", "gpio72", "gpio73", "gpio74"
796};
797
798static const char * const pmb_clk_groups[] = {
799 "gpio21", "gpio86", "gpio112"
800};
801
802static const char * const pmb_ext_ctrl_groups[] = {
803 "gpio4", "gpio5"
804};
805
806static const char * const ps_hold_groups[] = {
807 "gpio108"
808};
809
810static const char * const rpm_wdog_groups[] = {
811 "gpio12"
812};
813
814static const char * const sdc2_groups[] = {
815 "gpio89", "gpio90", "gpio91", "gpio92", "gpio93", "gpio94", "gpio95",
816 "gpio96", "gpio97", "gpio98"
817};
818
819static const char * const sdc4_groups[] = {
820 "gpio83", "gpio84", "gpio85", "gpio86", "gpio87", "gpio88"
821};
822
823static const char * const sdc5_groups[] = {
824 "gpio77", "gpio78", "gpio79", "gpio80", "gpio81", "gpio82"
825};
826
827static const char * const slimbus1_groups[] = {
828 "gpio50", "gpio51", "gpio60", "gpio61"
829};
830
831static const char * const slimbus2_groups[] = {
832 "gpio42", "gpio43"
833};
834
835static const char * const spkr_i2s_groups[] = {
836 "gpio67", "gpio68", "gpio69", "gpio70"
837};
838
839static const char * const ssbi1_groups[] = {
840 "gpio141", "gpio143"
841};
842
843static const char * const ssbi2_groups[] = {
844 "gpio140", "gpio142"
845};
846
847static const char * const ssbi_ext_gps_groups[] = {
848 "gpio23"
849};
850
851static const char * const ssbi_pmic2_groups[] = {
852 "gpio149"
853};
854
855static const char * const ssbi_qpa1_groups[] = {
856 "gpio131"
857};
858
859static const char * const ssbi_ts_groups[] = {
860 "gpio10"
861};
862
863static const char * const tsif1_groups[] = {
864 "gpio75", "gpio76", "gpio77", "gpio82"
865};
866
867static const char * const tsif2_groups[] = {
868 "gpio78", "gpio79", "gpio80", "gpio81"
869};
870
871static const char * const ts_eoc_groups[] = {
872 "gpio11"
873};
874
875static const char * const usb_fs1_groups[] = {
876 "gpio32", "gpio33"
877};
878
879static const char * const usb_fs1_oe_groups[] = {
880 "gpio31"
881};
882
883static const char * const usb_fs1_oe_n_groups[] = {
884 "gpio31"
885};
886
887static const char * const usb_fs2_groups[] = {
888 "gpio34", "gpio35"
889};
890
891static const char * const usb_fs2_oe_groups[] = {
892 "gpio36"
893};
894
895static const char * const usb_fs2_oe_n_groups[] = {
896 "gpio36"
897};
898
899static const char * const vfe_camif_timer1_a_groups[] = {
900 "gpio2"
901};
902
903static const char * const vfe_camif_timer1_b_groups[] = {
904 "gpio38"
905};
906
907static const char * const vfe_camif_timer2_groups[] = {
908 "gpio3"
909};
910
911static const char * const vfe_camif_timer3_a_groups[] = {
912 "gpio4"
913};
914
915static const char * const vfe_camif_timer3_b_groups[] = {
916 "gpio151"
917};
918
919static const char * const vfe_camif_timer4_a_groups[] = {
920 "gpio65"
921};
922
923static const char * const vfe_camif_timer4_b_groups[] = {
924 "gpio150"
925};
926
927static const char * const vfe_camif_timer4_c_groups[] = {
928 "gpio10"
929};
930
931static const char * const vfe_camif_timer5_a_groups[] = {
932 "gpio66"
933};
934
935static const char * const vfe_camif_timer5_b_groups[] = {
936 "gpio39"
937};
938
939static const char * const vfe_camif_timer6_a_groups[] = {
940 "gpio71"
941};
942
943static const char * const vfe_camif_timer6_b_groups[] = {
944 "gpio0"
945};
946
947static const char * const vfe_camif_timer6_c_groups[] = {
948 "gpio18"
949};
950
951static const char * const vfe_camif_timer7_a_groups[] = {
952 "gpio67"
953};
954
955static const char * const vfe_camif_timer7_b_groups[] = {
956 "gpio1"
957};
958
959static const char * const vfe_camif_timer7_c_groups[] = {
960 "gpio19"
961};
962
963static const char * const wlan_groups[] = {
964 "gpio84", "gpio85", "gpio86", "gpio87", "gpio88"
965};
966
967static const struct msm_function msm8960_functions[] = {
968 FUNCTION(audio_pcm),
969 FUNCTION(bt),
970 FUNCTION(cam_mclk0),
971 FUNCTION(cam_mclk1),
972 FUNCTION(cam_mclk2),
973 FUNCTION(codec_mic_i2s),
974 FUNCTION(codec_spkr_i2s),
975 FUNCTION(ext_gps),
976 FUNCTION(fm),
977 FUNCTION(gps_blanking),
978 FUNCTION(gps_pps_in),
979 FUNCTION(gps_pps_out),
980 FUNCTION(gp_clk_0a),
981 FUNCTION(gp_clk_0b),
982 FUNCTION(gp_clk_1a),
983 FUNCTION(gp_clk_1b),
984 FUNCTION(gp_clk_2a),
985 FUNCTION(gp_clk_2b),
986 FUNCTION(gp_mn),
987 FUNCTION(gp_pdm_0a),
988 FUNCTION(gp_pdm_0b),
989 FUNCTION(gp_pdm_1a),
990 FUNCTION(gp_pdm_1b),
991 FUNCTION(gp_pdm_2a),
992 FUNCTION(gp_pdm_2b),
993 FUNCTION(gpio),
994 FUNCTION(gsbi1),
995 FUNCTION(gsbi1_spi_cs1_n),
996 FUNCTION(gsbi1_spi_cs2a_n),
997 FUNCTION(gsbi1_spi_cs2b_n),
998 FUNCTION(gsbi1_spi_cs3_n),
999 FUNCTION(gsbi2),
1000 FUNCTION(gsbi2_spi_cs1_n),
1001 FUNCTION(gsbi2_spi_cs2_n),
1002 FUNCTION(gsbi2_spi_cs3_n),
1003 FUNCTION(gsbi3),
1004 FUNCTION(gsbi4),
1005 FUNCTION(gsbi4_3d_cam_i2c_l),
1006 FUNCTION(gsbi4_3d_cam_i2c_r),
1007 FUNCTION(gsbi5),
1008 FUNCTION(gsbi5_3d_cam_i2c_l),
1009 FUNCTION(gsbi5_3d_cam_i2c_r),
1010 FUNCTION(gsbi6),
1011 FUNCTION(gsbi7),
1012 FUNCTION(gsbi8),
1013 FUNCTION(gsbi9),
1014 FUNCTION(gsbi10),
1015 FUNCTION(gsbi11),
1016 FUNCTION(gsbi11_spi_cs1a_n),
1017 FUNCTION(gsbi11_spi_cs1b_n),
1018 FUNCTION(gsbi11_spi_cs2a_n),
1019 FUNCTION(gsbi11_spi_cs2b_n),
1020 FUNCTION(gsbi11_spi_cs3_n),
1021 FUNCTION(gsbi12),
1022 FUNCTION(hdmi_cec),
1023 FUNCTION(hdmi_ddc_clock),
1024 FUNCTION(hdmi_ddc_data),
1025 FUNCTION(hdmi_hot_plug_detect),
1026 FUNCTION(hsic),
1027 FUNCTION(mdp_vsync),
1028 FUNCTION(mi2s),
1029 FUNCTION(mic_i2s),
1030 FUNCTION(pmb_clk),
1031 FUNCTION(pmb_ext_ctrl),
1032 FUNCTION(ps_hold),
1033 FUNCTION(rpm_wdog),
1034 FUNCTION(sdc2),
1035 FUNCTION(sdc4),
1036 FUNCTION(sdc5),
1037 FUNCTION(slimbus1),
1038 FUNCTION(slimbus2),
1039 FUNCTION(spkr_i2s),
1040 FUNCTION(ssbi1),
1041 FUNCTION(ssbi2),
1042 FUNCTION(ssbi_ext_gps),
1043 FUNCTION(ssbi_pmic2),
1044 FUNCTION(ssbi_qpa1),
1045 FUNCTION(ssbi_ts),
1046 FUNCTION(tsif1),
1047 FUNCTION(tsif2),
1048 FUNCTION(ts_eoc),
1049 FUNCTION(usb_fs1),
1050 FUNCTION(usb_fs1_oe),
1051 FUNCTION(usb_fs1_oe_n),
1052 FUNCTION(usb_fs2),
1053 FUNCTION(usb_fs2_oe),
1054 FUNCTION(usb_fs2_oe_n),
1055 FUNCTION(vfe_camif_timer1_a),
1056 FUNCTION(vfe_camif_timer1_b),
1057 FUNCTION(vfe_camif_timer2),
1058 FUNCTION(vfe_camif_timer3_a),
1059 FUNCTION(vfe_camif_timer3_b),
1060 FUNCTION(vfe_camif_timer4_a),
1061 FUNCTION(vfe_camif_timer4_b),
1062 FUNCTION(vfe_camif_timer4_c),
1063 FUNCTION(vfe_camif_timer5_a),
1064 FUNCTION(vfe_camif_timer5_b),
1065 FUNCTION(vfe_camif_timer6_a),
1066 FUNCTION(vfe_camif_timer6_b),
1067 FUNCTION(vfe_camif_timer6_c),
1068 FUNCTION(vfe_camif_timer7_a),
1069 FUNCTION(vfe_camif_timer7_b),
1070 FUNCTION(vfe_camif_timer7_c),
1071 FUNCTION(wlan),
1072};
1073
1074static const struct msm_pingroup msm8960_groups[] = {
1075 PINGROUP(0, mdp_vsync, vfe_camif_timer6_b, NA, NA, NA, NA, NA, NA, NA, NA, NA),
1076 PINGROUP(1, mdp_vsync, vfe_camif_timer7_b, NA, NA, NA, NA, NA, NA, NA, NA, NA),
1077 PINGROUP(2, vfe_camif_timer1_a, gp_mn, NA, cam_mclk2, NA, NA, NA, NA, NA, NA, NA),
1078 PINGROUP(3, vfe_camif_timer2, gp_clk_0a, NA, NA, NA, NA, NA, NA, NA, NA, NA),
1079 PINGROUP(4, vfe_camif_timer3_a, cam_mclk1, gp_clk_1a, pmb_ext_ctrl, NA, NA, NA, NA, NA, NA, NA),
1080 PINGROUP(5, cam_mclk0, pmb_ext_ctrl, NA, NA, NA, NA, NA, NA, NA, NA, NA),
1081 PINGROUP(6, gsbi1, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
1082 PINGROUP(7, gsbi1, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
1083 PINGROUP(8, gsbi1, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
1084 PINGROUP(9, gsbi1, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
1085 PINGROUP(10, gsbi2, ssbi_ts, NA, vfe_camif_timer4_c, NA, NA, NA, NA, NA, NA, NA),
1086 PINGROUP(11, gsbi2, ts_eoc, NA, NA, NA, NA, NA, NA, NA, NA, NA),
1087 PINGROUP(12, gsbi2, rpm_wdog, NA, NA, NA, NA, NA, NA, NA, NA, NA),
1088 PINGROUP(13, gsbi2, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
1089 PINGROUP(14, gsbi3, gsbi1_spi_cs1_n, NA, NA, NA, NA, NA, NA, NA, NA, NA),
1090 PINGROUP(15, gsbi3, gsbi1_spi_cs2a_n, NA, NA, NA, NA, NA, NA, NA, NA, NA),
1091 PINGROUP(16, gsbi3, gsbi1_spi_cs3_n, NA, NA, NA, NA, NA, NA, NA, NA, NA),
1092 PINGROUP(17, gsbi3, gsbi1_spi_cs2b_n, NA, NA, NA, NA, NA, NA, NA, NA, NA),
1093 PINGROUP(18, gsbi4, gsbi11_spi_cs1b_n, NA, NA, gsbi4_3d_cam_i2c_l, vfe_camif_timer6_c, NA, NA, NA, NA, NA),
1094 PINGROUP(19, gsbi4, gsbi11_spi_cs2b_n, NA, mdp_vsync, NA, gsbi4_3d_cam_i2c_l, vfe_camif_timer7_c, NA, NA, NA, NA),
1095 PINGROUP(20, gsbi4, gsbi4_3d_cam_i2c_r, NA, NA, NA, NA, NA, NA, NA, NA, NA),
1096 PINGROUP(21, gsbi4, pmb_clk, gsbi4_3d_cam_i2c_r, NA, NA, NA, NA, NA, NA, NA, NA),
1097 PINGROUP(22, gsbi5, ext_gps, NA, NA, NA, NA, NA, NA, NA, gsbi5_3d_cam_i2c_l, NA),
1098 PINGROUP(23, gsbi5, ssbi_ext_gps, NA, NA, NA, NA, NA, NA, NA, gsbi5_3d_cam_i2c_l, NA),
1099 PINGROUP(24, gsbi5, ext_gps, NA, NA, NA, NA, NA, NA, NA, gsbi5_3d_cam_i2c_r, NA),
1100 PINGROUP(25, gsbi5, ext_gps, NA, NA, NA, NA, NA, NA, NA, gsbi5_3d_cam_i2c_r, NA),
1101 PINGROUP(26, fm, gsbi6, NA, NA, NA, NA, NA, NA, NA, NA, NA),
1102 PINGROUP(27, fm, gsbi6, NA, NA, NA, NA, NA, NA, NA, NA, NA),
1103 PINGROUP(28, bt, gsbi6, NA, NA, NA, NA, NA, NA, NA, NA, NA),
1104 PINGROUP(29, bt, gsbi6, NA, NA, NA, NA, NA, NA, NA, NA, NA),
1105 PINGROUP(30, gsbi7, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
1106 PINGROUP(31, gsbi7, usb_fs1_oe, usb_fs1_oe_n, NA, NA, NA, NA, NA, NA, NA, NA),
1107 PINGROUP(32, gsbi7, usb_fs1, NA, NA, NA, NA, NA, NA, NA, NA, NA),
1108 PINGROUP(33, gsbi7, usb_fs1, NA, NA, NA, NA, NA, NA, NA, NA, NA),
1109 PINGROUP(34, gsbi8, usb_fs2, NA, NA, NA, NA, NA, NA, NA, NA, NA),
1110 PINGROUP(35, gsbi8, usb_fs2, NA, NA, NA, NA, NA, NA, NA, NA, NA),
1111 PINGROUP(36, gsbi8, usb_fs2_oe, usb_fs2_oe_n, gsbi11_spi_cs1a_n, NA, NA, NA, NA, NA, NA, NA),
1112 PINGROUP(37, gsbi8, gps_pps_out, gps_pps_in, gsbi11_spi_cs2a_n, gp_clk_2b, NA, NA, NA, NA, NA, NA),
1113 PINGROUP(38, gsbi11, NA, NA, NA, NA, NA, NA, NA, NA, vfe_camif_timer1_b, NA),
1114 PINGROUP(39, gsbi11, gp_pdm_0b, NA, NA, NA, NA, NA, NA, NA, NA, vfe_camif_timer5_b),
1115 PINGROUP(40, gsbi11, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
1116 PINGROUP(41, gsbi11, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
1117 PINGROUP(42, gsbi12, slimbus2, NA, NA, NA, NA, NA, NA, NA, NA, NA),
1118 PINGROUP(43, gsbi12, slimbus2, NA, NA, NA, NA, NA, NA, NA, NA, NA),
1119 PINGROUP(44, gsbi12, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
1120 PINGROUP(45, gsbi12, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
1121 PINGROUP(46, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
1122 PINGROUP(47, mi2s, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
1123 PINGROUP(48, mi2s, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
1124 PINGROUP(49, mi2s, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
1125 PINGROUP(50, mi2s, slimbus1, NA, NA, NA, NA, NA, NA, NA, NA, NA),
1126 PINGROUP(51, mi2s, slimbus1, NA, NA, NA, NA, NA, NA, NA, NA, NA),
1127 PINGROUP(52, mi2s, gp_clk_2a, gsbi2_spi_cs1_n, NA, NA, NA, NA, NA, NA, NA, NA),
1128 PINGROUP(53, mi2s, gp_pdm_2b, NA, NA, NA, NA, NA, NA, NA, NA, NA),
1129 PINGROUP(54, codec_mic_i2s, gp_clk_0b, NA, NA, NA, NA, NA, NA, NA, NA, NA),
1130 PINGROUP(55, codec_mic_i2s, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
1131 PINGROUP(56, codec_mic_i2s, gsbi2_spi_cs3_n, NA, NA, NA, NA, NA, NA, NA, NA, NA),
1132 PINGROUP(57, codec_mic_i2s, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
1133 PINGROUP(58, codec_mic_i2s, gp_pdm_0a, NA, NA, NA, NA, NA, NA, NA, NA, NA),
1134 PINGROUP(59, codec_spkr_i2s, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
1135 PINGROUP(60, slimbus1, codec_spkr_i2s, NA, NA, NA, NA, NA, NA, NA, NA, NA),
1136 PINGROUP(61, slimbus1, codec_spkr_i2s, NA, NA, NA, NA, NA, NA, NA, NA, NA),
1137 PINGROUP(62, codec_spkr_i2s, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
1138 PINGROUP(63, audio_pcm, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
1139 PINGROUP(64, audio_pcm, gp_pdm_1b, NA, NA, NA, NA, NA, NA, NA, NA, NA),
1140 PINGROUP(65, audio_pcm, vfe_camif_timer4_a, NA, NA, NA, NA, NA, NA, NA, NA, NA),
1141 PINGROUP(66, audio_pcm, vfe_camif_timer5_a, NA, NA, NA, NA, NA, NA, NA, NA, NA),
1142 PINGROUP(67, spkr_i2s, vfe_camif_timer7_a, NA, NA, NA, NA, NA, NA, NA, NA, NA),
1143 PINGROUP(68, spkr_i2s, gsbi2_spi_cs2_n, NA, NA, NA, NA, NA, NA, NA, NA, NA),
1144 PINGROUP(69, spkr_i2s, gp_pdm_2a, NA, NA, NA, NA, NA, NA, NA, NA, NA),
1145 PINGROUP(70, spkr_i2s, gp_clk_1b, NA, NA, NA, NA, NA, NA, NA, NA, NA),
1146 PINGROUP(71, mic_i2s, gsbi10, vfe_camif_timer6_a, NA, NA, NA, NA, NA, NA, NA, NA),
1147 PINGROUP(72, mic_i2s, gsbi10, NA, NA, NA, NA, NA, NA, NA, NA, NA),
1148 PINGROUP(73, mic_i2s, gsbi10, NA, NA, NA, NA, NA, NA, NA, NA, NA),
1149 PINGROUP(74, mic_i2s, gsbi10, NA, NA, NA, NA, NA, NA, NA, NA, NA),
1150 PINGROUP(75, tsif1, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
1151 PINGROUP(76, tsif1, gsbi11_spi_cs3_n, NA, NA, NA, NA, NA, NA, NA, NA, NA),
1152 PINGROUP(77, tsif1, sdc5, NA, NA, NA, NA, NA, NA, NA, NA, NA),
1153 PINGROUP(78, tsif2, sdc5, NA, NA, NA, NA, NA, NA, NA, NA, NA),
1154 PINGROUP(79, tsif2, sdc5, NA, NA, NA, NA, NA, NA, NA, NA, NA),
1155 PINGROUP(80, tsif2, sdc5, NA, NA, NA, NA, NA, NA, NA, NA, NA),
1156 PINGROUP(81, tsif2, sdc5, NA, NA, NA, NA, NA, NA, NA, NA, NA),
1157 PINGROUP(82, tsif1, sdc5, NA, NA, NA, NA, NA, NA, NA, NA, NA),
1158 PINGROUP(83, bt, sdc4, NA, NA, NA, NA, NA, NA, NA, NA, NA),
1159 PINGROUP(84, wlan, sdc4, NA, NA, NA, NA, NA, NA, NA, NA, NA),
1160 PINGROUP(85, wlan, sdc4, NA, NA, NA, NA, NA, NA, NA, NA, NA),
1161 PINGROUP(86, wlan, sdc4, pmb_clk, NA, NA, NA, NA, NA, NA, NA, NA),
1162 PINGROUP(87, wlan, sdc4, NA, NA, NA, NA, NA, NA, NA, NA, NA),
1163 PINGROUP(88, wlan, sdc4, NA, NA, NA, NA, NA, NA, NA, NA, NA),
1164 PINGROUP(89, sdc2, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
1165 PINGROUP(90, sdc2, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
1166 PINGROUP(91, sdc2, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
1167 PINGROUP(92, sdc2, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
1168 PINGROUP(93, sdc2, gsbi9, NA, NA, NA, NA, NA, NA, NA, NA, NA),
1169 PINGROUP(94, sdc2, gsbi9, gp_pdm_1a, NA, NA, NA, NA, NA, NA, NA, NA),
1170 PINGROUP(95, sdc2, gsbi9, NA, NA, NA, NA, NA, NA, NA, NA, NA),
1171 PINGROUP(96, sdc2, gsbi9, NA, NA, NA, NA, NA, NA, NA, NA, NA),
1172 PINGROUP(97, sdc2, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
1173 PINGROUP(98, sdc2, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
1174 PINGROUP(99, hdmi_cec, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
1175 PINGROUP(100, hdmi_ddc_clock, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
1176 PINGROUP(101, hdmi_ddc_data, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
1177 PINGROUP(102, hdmi_hot_plug_detect, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
1178 PINGROUP(103, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
1179 PINGROUP(104, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
1180 PINGROUP(105, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
1181 PINGROUP(106, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
1182 PINGROUP(107, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
1183 PINGROUP(108, ps_hold, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
1184 PINGROUP(109, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
1185 PINGROUP(110, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
1186 PINGROUP(111, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
1187 PINGROUP(112, NA, pmb_clk, NA, NA, NA, NA, NA, NA, NA, NA, NA),
1188 PINGROUP(113, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
1189 PINGROUP(114, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
1190 PINGROUP(115, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
1191 PINGROUP(116, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
1192 PINGROUP(117, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
1193 PINGROUP(118, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
1194 PINGROUP(119, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
1195 PINGROUP(120, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
1196 PINGROUP(121, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
1197 PINGROUP(122, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
1198 PINGROUP(123, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
1199 PINGROUP(124, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
1200 PINGROUP(125, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
1201 PINGROUP(126, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
1202 PINGROUP(127, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
1203 PINGROUP(128, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
1204 PINGROUP(129, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
1205 PINGROUP(130, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
1206 PINGROUP(131, NA, ssbi_qpa1, NA, NA, NA, NA, NA, NA, NA, NA, NA),
1207 PINGROUP(132, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
1208 PINGROUP(133, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
1209 PINGROUP(134, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
1210 PINGROUP(135, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
1211 PINGROUP(136, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
1212 PINGROUP(137, gps_blanking, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
1213 PINGROUP(138, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
1214 PINGROUP(139, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
1215 PINGROUP(140, ssbi2, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
1216 PINGROUP(141, ssbi1, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
1217 PINGROUP(142, ssbi2, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
1218 PINGROUP(143, ssbi1, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
1219 PINGROUP(144, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
1220 PINGROUP(145, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
1221 PINGROUP(146, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
1222 PINGROUP(147, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
1223 PINGROUP(148, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
1224 PINGROUP(149, ssbi_pmic2, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
1225 PINGROUP(150, hsic, NA, vfe_camif_timer4_b, NA, NA, NA, NA, NA, NA, NA, NA),
1226 PINGROUP(151, hsic, NA, vfe_camif_timer3_b, NA, NA, NA, NA, NA, NA, NA, NA),
1227
1228 SDC_PINGROUP(sdc1_clk, 0x20a0, 13, 6),
1229 SDC_PINGROUP(sdc1_cmd, 0x20a0, 11, 3),
1230 SDC_PINGROUP(sdc1_data, 0x20a0, 9, 0),
1231
1232 SDC_PINGROUP(sdc3_clk, 0x20a4, 14, 6),
1233 SDC_PINGROUP(sdc3_cmd, 0x20a4, 11, 3),
1234 SDC_PINGROUP(sdc3_data, 0x20a4, 9, 0),
1235};
1236
1237#define NUM_GPIO_PINGROUPS 152
1238
1239static const struct msm_pinctrl_soc_data msm8960_pinctrl = {
1240 .pins = msm8960_pins,
1241 .npins = ARRAY_SIZE(msm8960_pins),
1242 .functions = msm8960_functions,
1243 .nfunctions = ARRAY_SIZE(msm8960_functions),
1244 .groups = msm8960_groups,
1245 .ngroups = ARRAY_SIZE(msm8960_groups),
1246 .ngpios = NUM_GPIO_PINGROUPS,
1247};
1248
1249static int msm8960_pinctrl_probe(struct platform_device *pdev)
1250{
1251 return msm_pinctrl_probe(pdev, &msm8960_pinctrl);
1252}
1253
1254static const struct of_device_id msm8960_pinctrl_of_match[] = {
1255 { .compatible = "qcom,msm8960-pinctrl", },
1256 { },
1257};
1258
1259static struct platform_driver msm8960_pinctrl_driver = {
1260 .driver = {
1261 .name = "msm8960-pinctrl",
1262 .owner = THIS_MODULE,
1263 .of_match_table = msm8960_pinctrl_of_match,
1264 },
1265 .probe = msm8960_pinctrl_probe,
1266 .remove = msm_pinctrl_remove,
1267};
1268
1269static int __init msm8960_pinctrl_init(void)
1270{
1271 return platform_driver_register(&msm8960_pinctrl_driver);
1272}
1273arch_initcall(msm8960_pinctrl_init);
1274
1275static void __exit msm8960_pinctrl_exit(void)
1276{
1277 platform_driver_unregister(&msm8960_pinctrl_driver);
1278}
1279module_exit(msm8960_pinctrl_exit);
1280
1281MODULE_AUTHOR("Bjorn Andersson <bjorn.andersson@sonymobile.com>");
1282MODULE_DESCRIPTION("Qualcomm MSM8960 pinctrl driver");
1283MODULE_LICENSE("GPL v2");
1284MODULE_DEVICE_TABLE(of, msm8960_pinctrl_of_match);
diff --git a/drivers/pinctrl/pinctrl-msm8x74.c b/drivers/pinctrl/qcom/pinctrl-msm8x74.c
index 418306911a6f..3c858384d041 100644
--- a/drivers/pinctrl/pinctrl-msm8x74.c
+++ b/drivers/pinctrl/qcom/pinctrl-msm8x74.c
@@ -342,7 +342,7 @@ static const unsigned int sdc2_data_pins[] = { 151 };
342 .pins = gpio##id##_pins, \ 342 .pins = gpio##id##_pins, \
343 .npins = ARRAY_SIZE(gpio##id##_pins), \ 343 .npins = ARRAY_SIZE(gpio##id##_pins), \
344 .funcs = (int[]){ \ 344 .funcs = (int[]){ \
345 MSM_MUX_NA, /* gpio mode */ \ 345 MSM_MUX_gpio, \
346 MSM_MUX_##f1, \ 346 MSM_MUX_##f1, \
347 MSM_MUX_##f2, \ 347 MSM_MUX_##f2, \
348 MSM_MUX_##f3, \ 348 MSM_MUX_##f3, \
@@ -366,6 +366,7 @@ static const unsigned int sdc2_data_pins[] = { 151 };
366 .intr_enable_bit = 0, \ 366 .intr_enable_bit = 0, \
367 .intr_status_bit = 0, \ 367 .intr_status_bit = 0, \
368 .intr_target_bit = 5, \ 368 .intr_target_bit = 5, \
369 .intr_target_kpss_val = 4, \
369 .intr_raw_status_bit = 4, \ 370 .intr_raw_status_bit = 4, \
370 .intr_polarity_bit = 1, \ 371 .intr_polarity_bit = 1, \
371 .intr_detection_bit = 2, \ 372 .intr_detection_bit = 2, \
@@ -391,6 +392,7 @@ static const unsigned int sdc2_data_pins[] = { 151 };
391 .intr_enable_bit = -1, \ 392 .intr_enable_bit = -1, \
392 .intr_status_bit = -1, \ 393 .intr_status_bit = -1, \
393 .intr_target_bit = -1, \ 394 .intr_target_bit = -1, \
395 .intr_target_kpss_val = -1, \
394 .intr_raw_status_bit = -1, \ 396 .intr_raw_status_bit = -1, \
395 .intr_polarity_bit = -1, \ 397 .intr_polarity_bit = -1, \
396 .intr_detection_bit = -1, \ 398 .intr_detection_bit = -1, \
@@ -402,6 +404,7 @@ static const unsigned int sdc2_data_pins[] = { 151 };
402 * the pingroup table below. 404 * the pingroup table below.
403 */ 405 */
404enum msm8x74_functions { 406enum msm8x74_functions {
407 MSM_MUX_gpio,
405 MSM_MUX_cci_i2c0, 408 MSM_MUX_cci_i2c0,
406 MSM_MUX_cci_i2c1, 409 MSM_MUX_cci_i2c1,
407 MSM_MUX_blsp_i2c1, 410 MSM_MUX_blsp_i2c1,
@@ -509,6 +512,31 @@ enum msm8x74_functions {
509 MSM_MUX_NA, 512 MSM_MUX_NA,
510}; 513};
511 514
515static const char * const gpio_groups[] = {
516 "gpio0", "gpio1", "gpio2", "gpio3", "gpio4", "gpio5", "gpio6", "gpio7",
517 "gpio8", "gpio9", "gpio10", "gpio11", "gpio12", "gpio13", "gpio14",
518 "gpio15", "gpio16", "gpio17", "gpio18", "gpio19", "gpio20", "gpio21",
519 "gpio22", "gpio23", "gpio24", "gpio25", "gpio26", "gpio27", "gpio28",
520 "gpio29", "gpio30", "gpio31", "gpio32", "gpio33", "gpio34", "gpio35",
521 "gpio36", "gpio37", "gpio38", "gpio39", "gpio40", "gpio41", "gpio42",
522 "gpio43", "gpio44", "gpio45", "gpio46", "gpio47", "gpio48", "gpio49",
523 "gpio50", "gpio51", "gpio52", "gpio53", "gpio54", "gpio55", "gpio56",
524 "gpio57", "gpio58", "gpio59", "gpio60", "gpio61", "gpio62", "gpio63",
525 "gpio64", "gpio65", "gpio66", "gpio67", "gpio68", "gpio69", "gpio70",
526 "gpio71", "gpio72", "gpio73", "gpio74", "gpio75", "gpio76", "gpio77",
527 "gpio78", "gpio79", "gpio80", "gpio81", "gpio82", "gpio83", "gpio84",
528 "gpio85", "gpio86", "gpio87", "gpio88", "gpio89", "gpio90", "gpio91",
529 "gpio92", "gpio93", "gpio94", "gpio95", "gpio96", "gpio97", "gpio98",
530 "gpio99", "gpio100", "gpio101", "gpio102", "gpio103", "gpio104",
531 "gpio105", "gpio106", "gpio107", "gpio108", "gpio109", "gpio110",
532 "gpio111", "gpio112", "gpio113", "gpio114", "gpio115", "gpio116",
533 "gpio117", "gpio118", "gpio119", "gpio120", "gpio121", "gpio122",
534 "gpio123", "gpio124", "gpio125", "gpio126", "gpio127", "gpio128",
535 "gpio129", "gpio130", "gpio131", "gpio132", "gpio133", "gpio134",
536 "gpio135", "gpio136", "gpio137", "gpio138", "gpio139", "gpio140",
537 "gpio141", "gpio142", "gpio143", "gpio144", "gpio145"
538};
539
512static const char * const blsp_uart1_groups[] = { 540static const char * const blsp_uart1_groups[] = {
513 "gpio0", "gpio1", "gpio2", "gpio3" 541 "gpio0", "gpio1", "gpio2", "gpio3"
514}; 542};
@@ -728,6 +756,7 @@ static const char * const wlan_groups[] = {
728static const char * const slimbus_groups[] = { "gpio70", "gpio71" }; 756static const char * const slimbus_groups[] = { "gpio70", "gpio71" };
729 757
730static const struct msm_function msm8x74_functions[] = { 758static const struct msm_function msm8x74_functions[] = {
759 FUNCTION(gpio),
731 FUNCTION(cci_i2c0), 760 FUNCTION(cci_i2c0),
732 FUNCTION(cci_i2c1), 761 FUNCTION(cci_i2c1),
733 FUNCTION(uim1), 762 FUNCTION(uim1),
diff --git a/drivers/pinctrl/samsung/Kconfig b/drivers/pinctrl/samsung/Kconfig
new file mode 100644
index 000000000000..d0461cd5d707
--- /dev/null
+++ b/drivers/pinctrl/samsung/Kconfig
@@ -0,0 +1,28 @@
1#
2# Samsung Pin control drivers
3#
4config PINCTRL_SAMSUNG
5 bool
6 select PINMUX
7 select PINCONF
8
9config PINCTRL_EXYNOS
10 bool "Pinctrl driver data for Samsung EXYNOS SoCs other than 5440"
11 depends on OF && GPIOLIB && (ARCH_EXYNOS || ARCH_S5PV210)
12 select PINCTRL_SAMSUNG
13
14config PINCTRL_EXYNOS5440
15 bool "Samsung EXYNOS5440 SoC pinctrl driver"
16 depends on SOC_EXYNOS5440
17 select PINMUX
18 select PINCONF
19
20config PINCTRL_S3C24XX
21 bool "Samsung S3C24XX SoC pinctrl driver"
22 depends on ARCH_S3C24XX
23 select PINCTRL_SAMSUNG
24
25config PINCTRL_S3C64XX
26 bool "Samsung S3C64XX SoC pinctrl driver"
27 depends on ARCH_S3C64XX
28 select PINCTRL_SAMSUNG
diff --git a/drivers/pinctrl/samsung/Makefile b/drivers/pinctrl/samsung/Makefile
new file mode 100644
index 000000000000..70160c059edd
--- /dev/null
+++ b/drivers/pinctrl/samsung/Makefile
@@ -0,0 +1,7 @@
1# Samsung pin control drivers
2
3obj-$(CONFIG_PINCTRL_SAMSUNG) += pinctrl-samsung.o
4obj-$(CONFIG_PINCTRL_EXYNOS) += pinctrl-exynos.o
5obj-$(CONFIG_PINCTRL_EXYNOS5440) += pinctrl-exynos5440.o
6obj-$(CONFIG_PINCTRL_S3C24XX) += pinctrl-s3c24xx.o
7obj-$(CONFIG_PINCTRL_S3C64XX) += pinctrl-s3c64xx.o
diff --git a/drivers/pinctrl/pinctrl-exynos.c b/drivers/pinctrl/samsung/pinctrl-exynos.c
index 9609c23834ce..d7154ed0b0eb 100644
--- a/drivers/pinctrl/pinctrl-exynos.c
+++ b/drivers/pinctrl/samsung/pinctrl-exynos.c
@@ -33,6 +33,18 @@
33#include "pinctrl-samsung.h" 33#include "pinctrl-samsung.h"
34#include "pinctrl-exynos.h" 34#include "pinctrl-exynos.h"
35 35
36struct exynos_irq_chip {
37 struct irq_chip chip;
38
39 u32 eint_con;
40 u32 eint_mask;
41 u32 eint_pend;
42};
43
44static inline struct exynos_irq_chip *to_exynos_irq_chip(struct irq_chip *chip)
45{
46 return container_of(chip, struct exynos_irq_chip, chip);
47}
36 48
37static struct samsung_pin_bank_type bank_type_off = { 49static struct samsung_pin_bank_type bank_type_off = {
38 .fld_width = { 4, 1, 2, 2, 2, 2, }, 50 .fld_width = { 4, 1, 2, 2, 2, 2, },
@@ -50,11 +62,13 @@ static const struct of_device_id exynos_wkup_irq_ids[] = {
50 { } 62 { }
51}; 63};
52 64
53static void exynos_gpio_irq_mask(struct irq_data *irqd) 65static void exynos_irq_mask(struct irq_data *irqd)
54{ 66{
67 struct irq_chip *chip = irq_data_get_irq_chip(irqd);
68 struct exynos_irq_chip *our_chip = to_exynos_irq_chip(chip);
55 struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(irqd); 69 struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(irqd);
56 struct samsung_pinctrl_drv_data *d = bank->drvdata; 70 struct samsung_pinctrl_drv_data *d = bank->drvdata;
57 unsigned long reg_mask = d->ctrl->geint_mask + bank->eint_offset; 71 unsigned long reg_mask = our_chip->eint_mask + bank->eint_offset;
58 unsigned long mask; 72 unsigned long mask;
59 unsigned long flags; 73 unsigned long flags;
60 74
@@ -67,20 +81,24 @@ static void exynos_gpio_irq_mask(struct irq_data *irqd)
67 spin_unlock_irqrestore(&bank->slock, flags); 81 spin_unlock_irqrestore(&bank->slock, flags);
68} 82}
69 83
70static void exynos_gpio_irq_ack(struct irq_data *irqd) 84static void exynos_irq_ack(struct irq_data *irqd)
71{ 85{
86 struct irq_chip *chip = irq_data_get_irq_chip(irqd);
87 struct exynos_irq_chip *our_chip = to_exynos_irq_chip(chip);
72 struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(irqd); 88 struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(irqd);
73 struct samsung_pinctrl_drv_data *d = bank->drvdata; 89 struct samsung_pinctrl_drv_data *d = bank->drvdata;
74 unsigned long reg_pend = d->ctrl->geint_pend + bank->eint_offset; 90 unsigned long reg_pend = our_chip->eint_pend + bank->eint_offset;
75 91
76 writel(1 << irqd->hwirq, d->virt_base + reg_pend); 92 writel(1 << irqd->hwirq, d->virt_base + reg_pend);
77} 93}
78 94
79static void exynos_gpio_irq_unmask(struct irq_data *irqd) 95static void exynos_irq_unmask(struct irq_data *irqd)
80{ 96{
97 struct irq_chip *chip = irq_data_get_irq_chip(irqd);
98 struct exynos_irq_chip *our_chip = to_exynos_irq_chip(chip);
81 struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(irqd); 99 struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(irqd);
82 struct samsung_pinctrl_drv_data *d = bank->drvdata; 100 struct samsung_pinctrl_drv_data *d = bank->drvdata;
83 unsigned long reg_mask = d->ctrl->geint_mask + bank->eint_offset; 101 unsigned long reg_mask = our_chip->eint_mask + bank->eint_offset;
84 unsigned long mask; 102 unsigned long mask;
85 unsigned long flags; 103 unsigned long flags;
86 104
@@ -93,7 +111,7 @@ static void exynos_gpio_irq_unmask(struct irq_data *irqd)
93 * masked. 111 * masked.
94 */ 112 */
95 if (irqd_get_trigger_type(irqd) & IRQ_TYPE_LEVEL_MASK) 113 if (irqd_get_trigger_type(irqd) & IRQ_TYPE_LEVEL_MASK)
96 exynos_gpio_irq_ack(irqd); 114 exynos_irq_ack(irqd);
97 115
98 spin_lock_irqsave(&bank->slock, flags); 116 spin_lock_irqsave(&bank->slock, flags);
99 117
@@ -104,18 +122,15 @@ static void exynos_gpio_irq_unmask(struct irq_data *irqd)
104 spin_unlock_irqrestore(&bank->slock, flags); 122 spin_unlock_irqrestore(&bank->slock, flags);
105} 123}
106 124
107static int exynos_gpio_irq_set_type(struct irq_data *irqd, unsigned int type) 125static int exynos_irq_set_type(struct irq_data *irqd, unsigned int type)
108{ 126{
127 struct irq_chip *chip = irq_data_get_irq_chip(irqd);
128 struct exynos_irq_chip *our_chip = to_exynos_irq_chip(chip);
109 struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(irqd); 129 struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(irqd);
110 struct samsung_pin_bank_type *bank_type = bank->type;
111 struct samsung_pinctrl_drv_data *d = bank->drvdata; 130 struct samsung_pinctrl_drv_data *d = bank->drvdata;
112 struct samsung_pin_ctrl *ctrl = d->ctrl; 131 unsigned int shift = EXYNOS_EINT_CON_LEN * irqd->hwirq;
113 unsigned int pin = irqd->hwirq;
114 unsigned int shift = EXYNOS_EINT_CON_LEN * pin;
115 unsigned int con, trig_type; 132 unsigned int con, trig_type;
116 unsigned long reg_con = ctrl->geint_con + bank->eint_offset; 133 unsigned long reg_con = our_chip->eint_con + bank->eint_offset;
117 unsigned long flags;
118 unsigned int mask;
119 134
120 switch (type) { 135 switch (type) {
121 case IRQ_TYPE_EDGE_RISING: 136 case IRQ_TYPE_EDGE_RISING:
@@ -148,8 +163,32 @@ static int exynos_gpio_irq_set_type(struct irq_data *irqd, unsigned int type)
148 con |= trig_type << shift; 163 con |= trig_type << shift;
149 writel(con, d->virt_base + reg_con); 164 writel(con, d->virt_base + reg_con);
150 165
166 return 0;
167}
168
169static int exynos_irq_request_resources(struct irq_data *irqd)
170{
171 struct irq_chip *chip = irq_data_get_irq_chip(irqd);
172 struct exynos_irq_chip *our_chip = to_exynos_irq_chip(chip);
173 struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(irqd);
174 struct samsung_pin_bank_type *bank_type = bank->type;
175 struct samsung_pinctrl_drv_data *d = bank->drvdata;
176 unsigned int shift = EXYNOS_EINT_CON_LEN * irqd->hwirq;
177 unsigned long reg_con = our_chip->eint_con + bank->eint_offset;
178 unsigned long flags;
179 unsigned int mask;
180 unsigned int con;
181 int ret;
182
183 ret = gpio_lock_as_irq(&bank->gpio_chip, irqd->hwirq);
184 if (ret) {
185 dev_err(bank->gpio_chip.dev, "unable to lock pin %s-%lu IRQ\n",
186 bank->name, irqd->hwirq);
187 return ret;
188 }
189
151 reg_con = bank->pctl_offset + bank_type->reg_offset[PINCFG_TYPE_FUNC]; 190 reg_con = bank->pctl_offset + bank_type->reg_offset[PINCFG_TYPE_FUNC];
152 shift = pin * bank_type->fld_width[PINCFG_TYPE_FUNC]; 191 shift = irqd->hwirq * bank_type->fld_width[PINCFG_TYPE_FUNC];
153 mask = (1 << bank_type->fld_width[PINCFG_TYPE_FUNC]) - 1; 192 mask = (1 << bank_type->fld_width[PINCFG_TYPE_FUNC]) - 1;
154 193
155 spin_lock_irqsave(&bank->slock, flags); 194 spin_lock_irqsave(&bank->slock, flags);
@@ -161,18 +200,58 @@ static int exynos_gpio_irq_set_type(struct irq_data *irqd, unsigned int type)
161 200
162 spin_unlock_irqrestore(&bank->slock, flags); 201 spin_unlock_irqrestore(&bank->slock, flags);
163 202
203 exynos_irq_unmask(irqd);
204
164 return 0; 205 return 0;
165} 206}
166 207
208static void exynos_irq_release_resources(struct irq_data *irqd)
209{
210 struct irq_chip *chip = irq_data_get_irq_chip(irqd);
211 struct exynos_irq_chip *our_chip = to_exynos_irq_chip(chip);
212 struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(irqd);
213 struct samsung_pin_bank_type *bank_type = bank->type;
214 struct samsung_pinctrl_drv_data *d = bank->drvdata;
215 unsigned int shift = EXYNOS_EINT_CON_LEN * irqd->hwirq;
216 unsigned long reg_con = our_chip->eint_con + bank->eint_offset;
217 unsigned long flags;
218 unsigned int mask;
219 unsigned int con;
220
221 reg_con = bank->pctl_offset + bank_type->reg_offset[PINCFG_TYPE_FUNC];
222 shift = irqd->hwirq * bank_type->fld_width[PINCFG_TYPE_FUNC];
223 mask = (1 << bank_type->fld_width[PINCFG_TYPE_FUNC]) - 1;
224
225 exynos_irq_mask(irqd);
226
227 spin_lock_irqsave(&bank->slock, flags);
228
229 con = readl(d->virt_base + reg_con);
230 con &= ~(mask << shift);
231 con |= FUNC_INPUT << shift;
232 writel(con, d->virt_base + reg_con);
233
234 spin_unlock_irqrestore(&bank->slock, flags);
235
236 gpio_unlock_as_irq(&bank->gpio_chip, irqd->hwirq);
237}
238
167/* 239/*
168 * irq_chip for gpio interrupts. 240 * irq_chip for gpio interrupts.
169 */ 241 */
170static struct irq_chip exynos_gpio_irq_chip = { 242static struct exynos_irq_chip exynos_gpio_irq_chip = {
171 .name = "exynos_gpio_irq_chip", 243 .chip = {
172 .irq_unmask = exynos_gpio_irq_unmask, 244 .name = "exynos_gpio_irq_chip",
173 .irq_mask = exynos_gpio_irq_mask, 245 .irq_unmask = exynos_irq_unmask,
174 .irq_ack = exynos_gpio_irq_ack, 246 .irq_mask = exynos_irq_mask,
175 .irq_set_type = exynos_gpio_irq_set_type, 247 .irq_ack = exynos_irq_ack,
248 .irq_set_type = exynos_irq_set_type,
249 .irq_request_resources = exynos_irq_request_resources,
250 .irq_release_resources = exynos_irq_release_resources,
251 },
252 .eint_con = EXYNOS_GPIO_ECON_OFFSET,
253 .eint_mask = EXYNOS_GPIO_EMASK_OFFSET,
254 .eint_pend = EXYNOS_GPIO_EPEND_OFFSET,
176}; 255};
177 256
178static int exynos_gpio_irq_map(struct irq_domain *h, unsigned int virq, 257static int exynos_gpio_irq_map(struct irq_domain *h, unsigned int virq,
@@ -181,7 +260,7 @@ static int exynos_gpio_irq_map(struct irq_domain *h, unsigned int virq,
181 struct samsung_pin_bank *b = h->host_data; 260 struct samsung_pin_bank *b = h->host_data;
182 261
183 irq_set_chip_data(virq, b); 262 irq_set_chip_data(virq, b);
184 irq_set_chip_and_handler(virq, &exynos_gpio_irq_chip, 263 irq_set_chip_and_handler(virq, &exynos_gpio_irq_chip.chip,
185 handle_level_irq); 264 handle_level_irq);
186 set_irq_flags(virq, IRQF_VALID); 265 set_irq_flags(virq, IRQF_VALID);
187 return 0; 266 return 0;
@@ -202,7 +281,7 @@ static irqreturn_t exynos_eint_gpio_irq(int irq, void *data)
202 struct samsung_pin_bank *bank = ctrl->pin_banks; 281 struct samsung_pin_bank *bank = ctrl->pin_banks;
203 unsigned int svc, group, pin, virq; 282 unsigned int svc, group, pin, virq;
204 283
205 svc = readl(d->virt_base + ctrl->svc); 284 svc = readl(d->virt_base + EXYNOS_SVC_OFFSET);
206 group = EXYNOS_SVC_GROUP(svc); 285 group = EXYNOS_SVC_GROUP(svc);
207 pin = svc & EXYNOS_SVC_NUM_MASK; 286 pin = svc & EXYNOS_SVC_NUM_MASK;
208 287
@@ -279,119 +358,6 @@ err_domains:
279 return ret; 358 return ret;
280} 359}
281 360
282static void exynos_wkup_irq_mask(struct irq_data *irqd)
283{
284 struct samsung_pin_bank *b = irq_data_get_irq_chip_data(irqd);
285 struct samsung_pinctrl_drv_data *d = b->drvdata;
286 unsigned long reg_mask = d->ctrl->weint_mask + b->eint_offset;
287 unsigned long mask;
288 unsigned long flags;
289
290 spin_lock_irqsave(&b->slock, flags);
291
292 mask = readl(d->virt_base + reg_mask);
293 mask |= 1 << irqd->hwirq;
294 writel(mask, d->virt_base + reg_mask);
295
296 spin_unlock_irqrestore(&b->slock, flags);
297}
298
299static void exynos_wkup_irq_ack(struct irq_data *irqd)
300{
301 struct samsung_pin_bank *b = irq_data_get_irq_chip_data(irqd);
302 struct samsung_pinctrl_drv_data *d = b->drvdata;
303 unsigned long pend = d->ctrl->weint_pend + b->eint_offset;
304
305 writel(1 << irqd->hwirq, d->virt_base + pend);
306}
307
308static void exynos_wkup_irq_unmask(struct irq_data *irqd)
309{
310 struct samsung_pin_bank *b = irq_data_get_irq_chip_data(irqd);
311 struct samsung_pinctrl_drv_data *d = b->drvdata;
312 unsigned long reg_mask = d->ctrl->weint_mask + b->eint_offset;
313 unsigned long mask;
314 unsigned long flags;
315
316 /*
317 * Ack level interrupts right before unmask
318 *
319 * If we don't do this we'll get a double-interrupt. Level triggered
320 * interrupts must not fire an interrupt if the level is not
321 * _currently_ active, even if it was active while the interrupt was
322 * masked.
323 */
324 if (irqd_get_trigger_type(irqd) & IRQ_TYPE_LEVEL_MASK)
325 exynos_wkup_irq_ack(irqd);
326
327 spin_lock_irqsave(&b->slock, flags);
328
329 mask = readl(d->virt_base + reg_mask);
330 mask &= ~(1 << irqd->hwirq);
331 writel(mask, d->virt_base + reg_mask);
332
333 spin_unlock_irqrestore(&b->slock, flags);
334}
335
336static int exynos_wkup_irq_set_type(struct irq_data *irqd, unsigned int type)
337{
338 struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(irqd);
339 struct samsung_pin_bank_type *bank_type = bank->type;
340 struct samsung_pinctrl_drv_data *d = bank->drvdata;
341 unsigned int pin = irqd->hwirq;
342 unsigned long reg_con = d->ctrl->weint_con + bank->eint_offset;
343 unsigned long shift = EXYNOS_EINT_CON_LEN * pin;
344 unsigned long con, trig_type;
345 unsigned long flags;
346 unsigned int mask;
347
348 switch (type) {
349 case IRQ_TYPE_EDGE_RISING:
350 trig_type = EXYNOS_EINT_EDGE_RISING;
351 break;
352 case IRQ_TYPE_EDGE_FALLING:
353 trig_type = EXYNOS_EINT_EDGE_FALLING;
354 break;
355 case IRQ_TYPE_EDGE_BOTH:
356 trig_type = EXYNOS_EINT_EDGE_BOTH;
357 break;
358 case IRQ_TYPE_LEVEL_HIGH:
359 trig_type = EXYNOS_EINT_LEVEL_HIGH;
360 break;
361 case IRQ_TYPE_LEVEL_LOW:
362 trig_type = EXYNOS_EINT_LEVEL_LOW;
363 break;
364 default:
365 pr_err("unsupported external interrupt type\n");
366 return -EINVAL;
367 }
368
369 if (type & IRQ_TYPE_EDGE_BOTH)
370 __irq_set_handler_locked(irqd->irq, handle_edge_irq);
371 else
372 __irq_set_handler_locked(irqd->irq, handle_level_irq);
373
374 con = readl(d->virt_base + reg_con);
375 con &= ~(EXYNOS_EINT_CON_MASK << shift);
376 con |= trig_type << shift;
377 writel(con, d->virt_base + reg_con);
378
379 reg_con = bank->pctl_offset + bank_type->reg_offset[PINCFG_TYPE_FUNC];
380 shift = pin * bank_type->fld_width[PINCFG_TYPE_FUNC];
381 mask = (1 << bank_type->fld_width[PINCFG_TYPE_FUNC]) - 1;
382
383 spin_lock_irqsave(&bank->slock, flags);
384
385 con = readl(d->virt_base + reg_con);
386 con &= ~(mask << shift);
387 con |= EXYNOS_EINT_FUNC << shift;
388 writel(con, d->virt_base + reg_con);
389
390 spin_unlock_irqrestore(&bank->slock, flags);
391
392 return 0;
393}
394
395static u32 exynos_eint_wake_mask = 0xffffffff; 361static u32 exynos_eint_wake_mask = 0xffffffff;
396 362
397u32 exynos_get_eint_wake_mask(void) 363u32 exynos_get_eint_wake_mask(void)
@@ -417,13 +383,20 @@ static int exynos_wkup_irq_set_wake(struct irq_data *irqd, unsigned int on)
417/* 383/*
418 * irq_chip for wakeup interrupts 384 * irq_chip for wakeup interrupts
419 */ 385 */
420static struct irq_chip exynos_wkup_irq_chip = { 386static struct exynos_irq_chip exynos_wkup_irq_chip = {
421 .name = "exynos_wkup_irq_chip", 387 .chip = {
422 .irq_unmask = exynos_wkup_irq_unmask, 388 .name = "exynos_wkup_irq_chip",
423 .irq_mask = exynos_wkup_irq_mask, 389 .irq_unmask = exynos_irq_unmask,
424 .irq_ack = exynos_wkup_irq_ack, 390 .irq_mask = exynos_irq_mask,
425 .irq_set_type = exynos_wkup_irq_set_type, 391 .irq_ack = exynos_irq_ack,
426 .irq_set_wake = exynos_wkup_irq_set_wake, 392 .irq_set_type = exynos_irq_set_type,
393 .irq_set_wake = exynos_wkup_irq_set_wake,
394 .irq_request_resources = exynos_irq_request_resources,
395 .irq_release_resources = exynos_irq_release_resources,
396 },
397 .eint_con = EXYNOS_WKUP_ECON_OFFSET,
398 .eint_mask = EXYNOS_WKUP_EMASK_OFFSET,
399 .eint_pend = EXYNOS_WKUP_EPEND_OFFSET,
427}; 400};
428 401
429/* interrupt handler for wakeup interrupts 0..15 */ 402/* interrupt handler for wakeup interrupts 0..15 */
@@ -464,7 +437,6 @@ static void exynos_irq_demux_eint16_31(unsigned int irq, struct irq_desc *desc)
464 struct irq_chip *chip = irq_get_chip(irq); 437 struct irq_chip *chip = irq_get_chip(irq);
465 struct exynos_muxed_weint_data *eintd = irq_get_handler_data(irq); 438 struct exynos_muxed_weint_data *eintd = irq_get_handler_data(irq);
466 struct samsung_pinctrl_drv_data *d = eintd->banks[0]->drvdata; 439 struct samsung_pinctrl_drv_data *d = eintd->banks[0]->drvdata;
467 struct samsung_pin_ctrl *ctrl = d->ctrl;
468 unsigned long pend; 440 unsigned long pend;
469 unsigned long mask; 441 unsigned long mask;
470 int i; 442 int i;
@@ -473,8 +445,10 @@ static void exynos_irq_demux_eint16_31(unsigned int irq, struct irq_desc *desc)
473 445
474 for (i = 0; i < eintd->nr_banks; ++i) { 446 for (i = 0; i < eintd->nr_banks; ++i) {
475 struct samsung_pin_bank *b = eintd->banks[i]; 447 struct samsung_pin_bank *b = eintd->banks[i];
476 pend = readl(d->virt_base + ctrl->weint_pend + b->eint_offset); 448 pend = readl(d->virt_base + EXYNOS_WKUP_EPEND_OFFSET
477 mask = readl(d->virt_base + ctrl->weint_mask + b->eint_offset); 449 + b->eint_offset);
450 mask = readl(d->virt_base + EXYNOS_WKUP_EMASK_OFFSET
451 + b->eint_offset);
478 exynos_irq_demux_eint(pend & ~mask, b->irq_domain); 452 exynos_irq_demux_eint(pend & ~mask, b->irq_domain);
479 } 453 }
480 454
@@ -484,7 +458,8 @@ static void exynos_irq_demux_eint16_31(unsigned int irq, struct irq_desc *desc)
484static int exynos_wkup_irq_map(struct irq_domain *h, unsigned int virq, 458static int exynos_wkup_irq_map(struct irq_domain *h, unsigned int virq,
485 irq_hw_number_t hw) 459 irq_hw_number_t hw)
486{ 460{
487 irq_set_chip_and_handler(virq, &exynos_wkup_irq_chip, handle_level_irq); 461 irq_set_chip_and_handler(virq, &exynos_wkup_irq_chip.chip,
462 handle_level_irq);
488 irq_set_chip_data(virq, h->host_data); 463 irq_set_chip_data(virq, h->host_data);
489 set_irq_flags(virq, IRQF_VALID); 464 set_irq_flags(virq, IRQF_VALID);
490 return 0; 465 return 0;
@@ -703,13 +678,6 @@ struct samsung_pin_ctrl s5pv210_pin_ctrl[] = {
703 /* pin-controller instance 0 data */ 678 /* pin-controller instance 0 data */
704 .pin_banks = s5pv210_pin_bank, 679 .pin_banks = s5pv210_pin_bank,
705 .nr_banks = ARRAY_SIZE(s5pv210_pin_bank), 680 .nr_banks = ARRAY_SIZE(s5pv210_pin_bank),
706 .geint_con = EXYNOS_GPIO_ECON_OFFSET,
707 .geint_mask = EXYNOS_GPIO_EMASK_OFFSET,
708 .geint_pend = EXYNOS_GPIO_EPEND_OFFSET,
709 .weint_con = EXYNOS_WKUP_ECON_OFFSET,
710 .weint_mask = EXYNOS_WKUP_EMASK_OFFSET,
711 .weint_pend = EXYNOS_WKUP_EPEND_OFFSET,
712 .svc = EXYNOS_SVC_OFFSET,
713 .eint_gpio_init = exynos_eint_gpio_init, 681 .eint_gpio_init = exynos_eint_gpio_init,
714 .eint_wkup_init = exynos_eint_wkup_init, 682 .eint_wkup_init = exynos_eint_wkup_init,
715 .suspend = exynos_pinctrl_suspend, 683 .suspend = exynos_pinctrl_suspend,
@@ -758,10 +726,6 @@ struct samsung_pin_ctrl exynos3250_pin_ctrl[] = {
758 /* pin-controller instance 0 data */ 726 /* pin-controller instance 0 data */
759 .pin_banks = exynos3250_pin_banks0, 727 .pin_banks = exynos3250_pin_banks0,
760 .nr_banks = ARRAY_SIZE(exynos3250_pin_banks0), 728 .nr_banks = ARRAY_SIZE(exynos3250_pin_banks0),
761 .geint_con = EXYNOS_GPIO_ECON_OFFSET,
762 .geint_mask = EXYNOS_GPIO_EMASK_OFFSET,
763 .geint_pend = EXYNOS_GPIO_EPEND_OFFSET,
764 .svc = EXYNOS_SVC_OFFSET,
765 .eint_gpio_init = exynos_eint_gpio_init, 729 .eint_gpio_init = exynos_eint_gpio_init,
766 .suspend = exynos_pinctrl_suspend, 730 .suspend = exynos_pinctrl_suspend,
767 .resume = exynos_pinctrl_resume, 731 .resume = exynos_pinctrl_resume,
@@ -770,13 +734,6 @@ struct samsung_pin_ctrl exynos3250_pin_ctrl[] = {
770 /* pin-controller instance 1 data */ 734 /* pin-controller instance 1 data */
771 .pin_banks = exynos3250_pin_banks1, 735 .pin_banks = exynos3250_pin_banks1,
772 .nr_banks = ARRAY_SIZE(exynos3250_pin_banks1), 736 .nr_banks = ARRAY_SIZE(exynos3250_pin_banks1),
773 .geint_con = EXYNOS_GPIO_ECON_OFFSET,
774 .geint_mask = EXYNOS_GPIO_EMASK_OFFSET,
775 .geint_pend = EXYNOS_GPIO_EPEND_OFFSET,
776 .weint_con = EXYNOS_WKUP_ECON_OFFSET,
777 .weint_mask = EXYNOS_WKUP_EMASK_OFFSET,
778 .weint_pend = EXYNOS_WKUP_EPEND_OFFSET,
779 .svc = EXYNOS_SVC_OFFSET,
780 .eint_gpio_init = exynos_eint_gpio_init, 737 .eint_gpio_init = exynos_eint_gpio_init,
781 .eint_wkup_init = exynos_eint_wkup_init, 738 .eint_wkup_init = exynos_eint_wkup_init,
782 .suspend = exynos_pinctrl_suspend, 739 .suspend = exynos_pinctrl_suspend,
@@ -843,10 +800,6 @@ struct samsung_pin_ctrl exynos4210_pin_ctrl[] = {
843 /* pin-controller instance 0 data */ 800 /* pin-controller instance 0 data */
844 .pin_banks = exynos4210_pin_banks0, 801 .pin_banks = exynos4210_pin_banks0,
845 .nr_banks = ARRAY_SIZE(exynos4210_pin_banks0), 802 .nr_banks = ARRAY_SIZE(exynos4210_pin_banks0),
846 .geint_con = EXYNOS_GPIO_ECON_OFFSET,
847 .geint_mask = EXYNOS_GPIO_EMASK_OFFSET,
848 .geint_pend = EXYNOS_GPIO_EPEND_OFFSET,
849 .svc = EXYNOS_SVC_OFFSET,
850 .eint_gpio_init = exynos_eint_gpio_init, 803 .eint_gpio_init = exynos_eint_gpio_init,
851 .suspend = exynos_pinctrl_suspend, 804 .suspend = exynos_pinctrl_suspend,
852 .resume = exynos_pinctrl_resume, 805 .resume = exynos_pinctrl_resume,
@@ -855,13 +808,6 @@ struct samsung_pin_ctrl exynos4210_pin_ctrl[] = {
855 /* pin-controller instance 1 data */ 808 /* pin-controller instance 1 data */
856 .pin_banks = exynos4210_pin_banks1, 809 .pin_banks = exynos4210_pin_banks1,
857 .nr_banks = ARRAY_SIZE(exynos4210_pin_banks1), 810 .nr_banks = ARRAY_SIZE(exynos4210_pin_banks1),
858 .geint_con = EXYNOS_GPIO_ECON_OFFSET,
859 .geint_mask = EXYNOS_GPIO_EMASK_OFFSET,
860 .geint_pend = EXYNOS_GPIO_EPEND_OFFSET,
861 .weint_con = EXYNOS_WKUP_ECON_OFFSET,
862 .weint_mask = EXYNOS_WKUP_EMASK_OFFSET,
863 .weint_pend = EXYNOS_WKUP_EPEND_OFFSET,
864 .svc = EXYNOS_SVC_OFFSET,
865 .eint_gpio_init = exynos_eint_gpio_init, 811 .eint_gpio_init = exynos_eint_gpio_init,
866 .eint_wkup_init = exynos_eint_wkup_init, 812 .eint_wkup_init = exynos_eint_wkup_init,
867 .suspend = exynos_pinctrl_suspend, 813 .suspend = exynos_pinctrl_suspend,
@@ -942,10 +888,6 @@ struct samsung_pin_ctrl exynos4x12_pin_ctrl[] = {
942 /* pin-controller instance 0 data */ 888 /* pin-controller instance 0 data */
943 .pin_banks = exynos4x12_pin_banks0, 889 .pin_banks = exynos4x12_pin_banks0,
944 .nr_banks = ARRAY_SIZE(exynos4x12_pin_banks0), 890 .nr_banks = ARRAY_SIZE(exynos4x12_pin_banks0),
945 .geint_con = EXYNOS_GPIO_ECON_OFFSET,
946 .geint_mask = EXYNOS_GPIO_EMASK_OFFSET,
947 .geint_pend = EXYNOS_GPIO_EPEND_OFFSET,
948 .svc = EXYNOS_SVC_OFFSET,
949 .eint_gpio_init = exynos_eint_gpio_init, 891 .eint_gpio_init = exynos_eint_gpio_init,
950 .suspend = exynos_pinctrl_suspend, 892 .suspend = exynos_pinctrl_suspend,
951 .resume = exynos_pinctrl_resume, 893 .resume = exynos_pinctrl_resume,
@@ -954,13 +896,6 @@ struct samsung_pin_ctrl exynos4x12_pin_ctrl[] = {
954 /* pin-controller instance 1 data */ 896 /* pin-controller instance 1 data */
955 .pin_banks = exynos4x12_pin_banks1, 897 .pin_banks = exynos4x12_pin_banks1,
956 .nr_banks = ARRAY_SIZE(exynos4x12_pin_banks1), 898 .nr_banks = ARRAY_SIZE(exynos4x12_pin_banks1),
957 .geint_con = EXYNOS_GPIO_ECON_OFFSET,
958 .geint_mask = EXYNOS_GPIO_EMASK_OFFSET,
959 .geint_pend = EXYNOS_GPIO_EPEND_OFFSET,
960 .weint_con = EXYNOS_WKUP_ECON_OFFSET,
961 .weint_mask = EXYNOS_WKUP_EMASK_OFFSET,
962 .weint_pend = EXYNOS_WKUP_EPEND_OFFSET,
963 .svc = EXYNOS_SVC_OFFSET,
964 .eint_gpio_init = exynos_eint_gpio_init, 899 .eint_gpio_init = exynos_eint_gpio_init,
965 .eint_wkup_init = exynos_eint_wkup_init, 900 .eint_wkup_init = exynos_eint_wkup_init,
966 .suspend = exynos_pinctrl_suspend, 901 .suspend = exynos_pinctrl_suspend,
@@ -970,10 +905,6 @@ struct samsung_pin_ctrl exynos4x12_pin_ctrl[] = {
970 /* pin-controller instance 2 data */ 905 /* pin-controller instance 2 data */
971 .pin_banks = exynos4x12_pin_banks2, 906 .pin_banks = exynos4x12_pin_banks2,
972 .nr_banks = ARRAY_SIZE(exynos4x12_pin_banks2), 907 .nr_banks = ARRAY_SIZE(exynos4x12_pin_banks2),
973 .geint_con = EXYNOS_GPIO_ECON_OFFSET,
974 .geint_mask = EXYNOS_GPIO_EMASK_OFFSET,
975 .geint_pend = EXYNOS_GPIO_EPEND_OFFSET,
976 .svc = EXYNOS_SVC_OFFSET,
977 .eint_gpio_init = exynos_eint_gpio_init, 908 .eint_gpio_init = exynos_eint_gpio_init,
978 .suspend = exynos_pinctrl_suspend, 909 .suspend = exynos_pinctrl_suspend,
979 .resume = exynos_pinctrl_resume, 910 .resume = exynos_pinctrl_resume,
@@ -982,10 +913,6 @@ struct samsung_pin_ctrl exynos4x12_pin_ctrl[] = {
982 /* pin-controller instance 3 data */ 913 /* pin-controller instance 3 data */
983 .pin_banks = exynos4x12_pin_banks3, 914 .pin_banks = exynos4x12_pin_banks3,
984 .nr_banks = ARRAY_SIZE(exynos4x12_pin_banks3), 915 .nr_banks = ARRAY_SIZE(exynos4x12_pin_banks3),
985 .geint_con = EXYNOS_GPIO_ECON_OFFSET,
986 .geint_mask = EXYNOS_GPIO_EMASK_OFFSET,
987 .geint_pend = EXYNOS_GPIO_EPEND_OFFSET,
988 .svc = EXYNOS_SVC_OFFSET,
989 .eint_gpio_init = exynos_eint_gpio_init, 916 .eint_gpio_init = exynos_eint_gpio_init,
990 .suspend = exynos_pinctrl_suspend, 917 .suspend = exynos_pinctrl_suspend,
991 .resume = exynos_pinctrl_resume, 918 .resume = exynos_pinctrl_resume,
@@ -1058,13 +985,6 @@ struct samsung_pin_ctrl exynos5250_pin_ctrl[] = {
1058 /* pin-controller instance 0 data */ 985 /* pin-controller instance 0 data */
1059 .pin_banks = exynos5250_pin_banks0, 986 .pin_banks = exynos5250_pin_banks0,
1060 .nr_banks = ARRAY_SIZE(exynos5250_pin_banks0), 987 .nr_banks = ARRAY_SIZE(exynos5250_pin_banks0),
1061 .geint_con = EXYNOS_GPIO_ECON_OFFSET,
1062 .geint_mask = EXYNOS_GPIO_EMASK_OFFSET,
1063 .geint_pend = EXYNOS_GPIO_EPEND_OFFSET,
1064 .weint_con = EXYNOS_WKUP_ECON_OFFSET,
1065 .weint_mask = EXYNOS_WKUP_EMASK_OFFSET,
1066 .weint_pend = EXYNOS_WKUP_EPEND_OFFSET,
1067 .svc = EXYNOS_SVC_OFFSET,
1068 .eint_gpio_init = exynos_eint_gpio_init, 988 .eint_gpio_init = exynos_eint_gpio_init,
1069 .eint_wkup_init = exynos_eint_wkup_init, 989 .eint_wkup_init = exynos_eint_wkup_init,
1070 .suspend = exynos_pinctrl_suspend, 990 .suspend = exynos_pinctrl_suspend,
@@ -1074,10 +994,6 @@ struct samsung_pin_ctrl exynos5250_pin_ctrl[] = {
1074 /* pin-controller instance 1 data */ 994 /* pin-controller instance 1 data */
1075 .pin_banks = exynos5250_pin_banks1, 995 .pin_banks = exynos5250_pin_banks1,
1076 .nr_banks = ARRAY_SIZE(exynos5250_pin_banks1), 996 .nr_banks = ARRAY_SIZE(exynos5250_pin_banks1),
1077 .geint_con = EXYNOS_GPIO_ECON_OFFSET,
1078 .geint_mask = EXYNOS_GPIO_EMASK_OFFSET,
1079 .geint_pend = EXYNOS_GPIO_EPEND_OFFSET,
1080 .svc = EXYNOS_SVC_OFFSET,
1081 .eint_gpio_init = exynos_eint_gpio_init, 997 .eint_gpio_init = exynos_eint_gpio_init,
1082 .suspend = exynos_pinctrl_suspend, 998 .suspend = exynos_pinctrl_suspend,
1083 .resume = exynos_pinctrl_resume, 999 .resume = exynos_pinctrl_resume,
@@ -1086,10 +1002,6 @@ struct samsung_pin_ctrl exynos5250_pin_ctrl[] = {
1086 /* pin-controller instance 2 data */ 1002 /* pin-controller instance 2 data */
1087 .pin_banks = exynos5250_pin_banks2, 1003 .pin_banks = exynos5250_pin_banks2,
1088 .nr_banks = ARRAY_SIZE(exynos5250_pin_banks2), 1004 .nr_banks = ARRAY_SIZE(exynos5250_pin_banks2),
1089 .geint_con = EXYNOS_GPIO_ECON_OFFSET,
1090 .geint_mask = EXYNOS_GPIO_EMASK_OFFSET,
1091 .geint_pend = EXYNOS_GPIO_EPEND_OFFSET,
1092 .svc = EXYNOS_SVC_OFFSET,
1093 .eint_gpio_init = exynos_eint_gpio_init, 1005 .eint_gpio_init = exynos_eint_gpio_init,
1094 .suspend = exynos_pinctrl_suspend, 1006 .suspend = exynos_pinctrl_suspend,
1095 .resume = exynos_pinctrl_resume, 1007 .resume = exynos_pinctrl_resume,
@@ -1098,10 +1010,6 @@ struct samsung_pin_ctrl exynos5250_pin_ctrl[] = {
1098 /* pin-controller instance 3 data */ 1010 /* pin-controller instance 3 data */
1099 .pin_banks = exynos5250_pin_banks3, 1011 .pin_banks = exynos5250_pin_banks3,
1100 .nr_banks = ARRAY_SIZE(exynos5250_pin_banks3), 1012 .nr_banks = ARRAY_SIZE(exynos5250_pin_banks3),
1101 .geint_con = EXYNOS_GPIO_ECON_OFFSET,
1102 .geint_mask = EXYNOS_GPIO_EMASK_OFFSET,
1103 .geint_pend = EXYNOS_GPIO_EPEND_OFFSET,
1104 .svc = EXYNOS_SVC_OFFSET,
1105 .eint_gpio_init = exynos_eint_gpio_init, 1013 .eint_gpio_init = exynos_eint_gpio_init,
1106 .suspend = exynos_pinctrl_suspend, 1014 .suspend = exynos_pinctrl_suspend,
1107 .resume = exynos_pinctrl_resume, 1015 .resume = exynos_pinctrl_resume,
@@ -1158,13 +1066,6 @@ struct samsung_pin_ctrl exynos5260_pin_ctrl[] = {
1158 /* pin-controller instance 0 data */ 1066 /* pin-controller instance 0 data */
1159 .pin_banks = exynos5260_pin_banks0, 1067 .pin_banks = exynos5260_pin_banks0,
1160 .nr_banks = ARRAY_SIZE(exynos5260_pin_banks0), 1068 .nr_banks = ARRAY_SIZE(exynos5260_pin_banks0),
1161 .geint_con = EXYNOS_GPIO_ECON_OFFSET,
1162 .geint_mask = EXYNOS_GPIO_EMASK_OFFSET,
1163 .geint_pend = EXYNOS_GPIO_EPEND_OFFSET,
1164 .weint_con = EXYNOS_WKUP_ECON_OFFSET,
1165 .weint_mask = EXYNOS_WKUP_EMASK_OFFSET,
1166 .weint_pend = EXYNOS_WKUP_EPEND_OFFSET,
1167 .svc = EXYNOS_SVC_OFFSET,
1168 .eint_gpio_init = exynos_eint_gpio_init, 1069 .eint_gpio_init = exynos_eint_gpio_init,
1169 .eint_wkup_init = exynos_eint_wkup_init, 1070 .eint_wkup_init = exynos_eint_wkup_init,
1170 .label = "exynos5260-gpio-ctrl0", 1071 .label = "exynos5260-gpio-ctrl0",
@@ -1172,20 +1073,12 @@ struct samsung_pin_ctrl exynos5260_pin_ctrl[] = {
1172 /* pin-controller instance 1 data */ 1073 /* pin-controller instance 1 data */
1173 .pin_banks = exynos5260_pin_banks1, 1074 .pin_banks = exynos5260_pin_banks1,
1174 .nr_banks = ARRAY_SIZE(exynos5260_pin_banks1), 1075 .nr_banks = ARRAY_SIZE(exynos5260_pin_banks1),
1175 .geint_con = EXYNOS_GPIO_ECON_OFFSET,
1176 .geint_mask = EXYNOS_GPIO_EMASK_OFFSET,
1177 .geint_pend = EXYNOS_GPIO_EPEND_OFFSET,
1178 .svc = EXYNOS_SVC_OFFSET,
1179 .eint_gpio_init = exynos_eint_gpio_init, 1076 .eint_gpio_init = exynos_eint_gpio_init,
1180 .label = "exynos5260-gpio-ctrl1", 1077 .label = "exynos5260-gpio-ctrl1",
1181 }, { 1078 }, {
1182 /* pin-controller instance 2 data */ 1079 /* pin-controller instance 2 data */
1183 .pin_banks = exynos5260_pin_banks2, 1080 .pin_banks = exynos5260_pin_banks2,
1184 .nr_banks = ARRAY_SIZE(exynos5260_pin_banks2), 1081 .nr_banks = ARRAY_SIZE(exynos5260_pin_banks2),
1185 .geint_con = EXYNOS_GPIO_ECON_OFFSET,
1186 .geint_mask = EXYNOS_GPIO_EMASK_OFFSET,
1187 .geint_pend = EXYNOS_GPIO_EPEND_OFFSET,
1188 .svc = EXYNOS_SVC_OFFSET,
1189 .eint_gpio_init = exynos_eint_gpio_init, 1082 .eint_gpio_init = exynos_eint_gpio_init,
1190 .label = "exynos5260-gpio-ctrl2", 1083 .label = "exynos5260-gpio-ctrl2",
1191 }, 1084 },
@@ -1256,13 +1149,6 @@ struct samsung_pin_ctrl exynos5420_pin_ctrl[] = {
1256 /* pin-controller instance 0 data */ 1149 /* pin-controller instance 0 data */
1257 .pin_banks = exynos5420_pin_banks0, 1150 .pin_banks = exynos5420_pin_banks0,
1258 .nr_banks = ARRAY_SIZE(exynos5420_pin_banks0), 1151 .nr_banks = ARRAY_SIZE(exynos5420_pin_banks0),
1259 .geint_con = EXYNOS_GPIO_ECON_OFFSET,
1260 .geint_mask = EXYNOS_GPIO_EMASK_OFFSET,
1261 .geint_pend = EXYNOS_GPIO_EPEND_OFFSET,
1262 .weint_con = EXYNOS_WKUP_ECON_OFFSET,
1263 .weint_mask = EXYNOS_WKUP_EMASK_OFFSET,
1264 .weint_pend = EXYNOS_WKUP_EPEND_OFFSET,
1265 .svc = EXYNOS_SVC_OFFSET,
1266 .eint_gpio_init = exynos_eint_gpio_init, 1152 .eint_gpio_init = exynos_eint_gpio_init,
1267 .eint_wkup_init = exynos_eint_wkup_init, 1153 .eint_wkup_init = exynos_eint_wkup_init,
1268 .label = "exynos5420-gpio-ctrl0", 1154 .label = "exynos5420-gpio-ctrl0",
@@ -1270,40 +1156,24 @@ struct samsung_pin_ctrl exynos5420_pin_ctrl[] = {
1270 /* pin-controller instance 1 data */ 1156 /* pin-controller instance 1 data */
1271 .pin_banks = exynos5420_pin_banks1, 1157 .pin_banks = exynos5420_pin_banks1,
1272 .nr_banks = ARRAY_SIZE(exynos5420_pin_banks1), 1158 .nr_banks = ARRAY_SIZE(exynos5420_pin_banks1),
1273 .geint_con = EXYNOS_GPIO_ECON_OFFSET,
1274 .geint_mask = EXYNOS_GPIO_EMASK_OFFSET,
1275 .geint_pend = EXYNOS_GPIO_EPEND_OFFSET,
1276 .svc = EXYNOS_SVC_OFFSET,
1277 .eint_gpio_init = exynos_eint_gpio_init, 1159 .eint_gpio_init = exynos_eint_gpio_init,
1278 .label = "exynos5420-gpio-ctrl1", 1160 .label = "exynos5420-gpio-ctrl1",
1279 }, { 1161 }, {
1280 /* pin-controller instance 2 data */ 1162 /* pin-controller instance 2 data */
1281 .pin_banks = exynos5420_pin_banks2, 1163 .pin_banks = exynos5420_pin_banks2,
1282 .nr_banks = ARRAY_SIZE(exynos5420_pin_banks2), 1164 .nr_banks = ARRAY_SIZE(exynos5420_pin_banks2),
1283 .geint_con = EXYNOS_GPIO_ECON_OFFSET,
1284 .geint_mask = EXYNOS_GPIO_EMASK_OFFSET,
1285 .geint_pend = EXYNOS_GPIO_EPEND_OFFSET,
1286 .svc = EXYNOS_SVC_OFFSET,
1287 .eint_gpio_init = exynos_eint_gpio_init, 1165 .eint_gpio_init = exynos_eint_gpio_init,
1288 .label = "exynos5420-gpio-ctrl2", 1166 .label = "exynos5420-gpio-ctrl2",
1289 }, { 1167 }, {
1290 /* pin-controller instance 3 data */ 1168 /* pin-controller instance 3 data */
1291 .pin_banks = exynos5420_pin_banks3, 1169 .pin_banks = exynos5420_pin_banks3,
1292 .nr_banks = ARRAY_SIZE(exynos5420_pin_banks3), 1170 .nr_banks = ARRAY_SIZE(exynos5420_pin_banks3),
1293 .geint_con = EXYNOS_GPIO_ECON_OFFSET,
1294 .geint_mask = EXYNOS_GPIO_EMASK_OFFSET,
1295 .geint_pend = EXYNOS_GPIO_EPEND_OFFSET,
1296 .svc = EXYNOS_SVC_OFFSET,
1297 .eint_gpio_init = exynos_eint_gpio_init, 1171 .eint_gpio_init = exynos_eint_gpio_init,
1298 .label = "exynos5420-gpio-ctrl3", 1172 .label = "exynos5420-gpio-ctrl3",
1299 }, { 1173 }, {
1300 /* pin-controller instance 4 data */ 1174 /* pin-controller instance 4 data */
1301 .pin_banks = exynos5420_pin_banks4, 1175 .pin_banks = exynos5420_pin_banks4,
1302 .nr_banks = ARRAY_SIZE(exynos5420_pin_banks4), 1176 .nr_banks = ARRAY_SIZE(exynos5420_pin_banks4),
1303 .geint_con = EXYNOS_GPIO_ECON_OFFSET,
1304 .geint_mask = EXYNOS_GPIO_EMASK_OFFSET,
1305 .geint_pend = EXYNOS_GPIO_EPEND_OFFSET,
1306 .svc = EXYNOS_SVC_OFFSET,
1307 .eint_gpio_init = exynos_eint_gpio_init, 1177 .eint_gpio_init = exynos_eint_gpio_init,
1308 .label = "exynos5420-gpio-ctrl4", 1178 .label = "exynos5420-gpio-ctrl4",
1309 }, 1179 },
diff --git a/drivers/pinctrl/pinctrl-exynos.h b/drivers/pinctrl/samsung/pinctrl-exynos.h
index 3c91c357792f..3c91c357792f 100644
--- a/drivers/pinctrl/pinctrl-exynos.h
+++ b/drivers/pinctrl/samsung/pinctrl-exynos.h
diff --git a/drivers/pinctrl/pinctrl-exynos5440.c b/drivers/pinctrl/samsung/pinctrl-exynos5440.c
index 8fe2ab0a7698..88acfc0efd54 100644
--- a/drivers/pinctrl/pinctrl-exynos5440.c
+++ b/drivers/pinctrl/samsung/pinctrl-exynos5440.c
@@ -23,7 +23,7 @@
23#include <linux/interrupt.h> 23#include <linux/interrupt.h>
24#include <linux/irqdomain.h> 24#include <linux/irqdomain.h>
25#include <linux/of_irq.h> 25#include <linux/of_irq.h>
26#include "core.h" 26#include "../core.h"
27 27
28/* EXYNOS5440 GPIO and Pinctrl register offsets */ 28/* EXYNOS5440 GPIO and Pinctrl register offsets */
29#define GPIO_MUX 0x00 29#define GPIO_MUX 0x00
@@ -364,20 +364,14 @@ static void exynos5440_pinmux_setup(struct pinctrl_dev *pctldev, unsigned select
364} 364}
365 365
366/* enable a specified pinmux by writing to registers */ 366/* enable a specified pinmux by writing to registers */
367static int exynos5440_pinmux_enable(struct pinctrl_dev *pctldev, unsigned selector, 367static int exynos5440_pinmux_set_mux(struct pinctrl_dev *pctldev,
368 unsigned group) 368 unsigned selector,
369 unsigned group)
369{ 370{
370 exynos5440_pinmux_setup(pctldev, selector, group, true); 371 exynos5440_pinmux_setup(pctldev, selector, group, true);
371 return 0; 372 return 0;
372} 373}
373 374
374/* disable a specified pinmux by writing to registers */
375static void exynos5440_pinmux_disable(struct pinctrl_dev *pctldev,
376 unsigned selector, unsigned group)
377{
378 exynos5440_pinmux_setup(pctldev, selector, group, false);
379}
380
381/* 375/*
382 * The calls to gpio_direction_output() and gpio_direction_input() 376 * The calls to gpio_direction_output() and gpio_direction_input()
383 * leads to this function call (via the pinctrl_gpio_direction_{input|output}() 377 * leads to this function call (via the pinctrl_gpio_direction_{input|output}()
@@ -394,8 +388,7 @@ static const struct pinmux_ops exynos5440_pinmux_ops = {
394 .get_functions_count = exynos5440_get_functions_count, 388 .get_functions_count = exynos5440_get_functions_count,
395 .get_function_name = exynos5440_pinmux_get_fname, 389 .get_function_name = exynos5440_pinmux_get_fname,
396 .get_function_groups = exynos5440_pinmux_get_groups, 390 .get_function_groups = exynos5440_pinmux_get_groups,
397 .enable = exynos5440_pinmux_enable, 391 .set_mux = exynos5440_pinmux_set_mux,
398 .disable = exynos5440_pinmux_disable,
399 .gpio_set_direction = exynos5440_pinmux_gpio_set_direction, 392 .gpio_set_direction = exynos5440_pinmux_gpio_set_direction,
400}; 393};
401 394
@@ -881,11 +874,7 @@ static int exynos5440_gpiolib_register(struct platform_device *pdev,
881static int exynos5440_gpiolib_unregister(struct platform_device *pdev, 874static int exynos5440_gpiolib_unregister(struct platform_device *pdev,
882 struct exynos5440_pinctrl_priv_data *priv) 875 struct exynos5440_pinctrl_priv_data *priv)
883{ 876{
884 int ret = gpiochip_remove(priv->gc); 877 gpiochip_remove(priv->gc);
885 if (ret) {
886 dev_err(&pdev->dev, "gpio chip remove failed\n");
887 return ret;
888 }
889 return 0; 878 return 0;
890} 879}
891 880
diff --git a/drivers/pinctrl/pinctrl-s3c24xx.c b/drivers/pinctrl/samsung/pinctrl-s3c24xx.c
index ad3eaad17001..ad3eaad17001 100644
--- a/drivers/pinctrl/pinctrl-s3c24xx.c
+++ b/drivers/pinctrl/samsung/pinctrl-s3c24xx.c
diff --git a/drivers/pinctrl/pinctrl-s3c64xx.c b/drivers/pinctrl/samsung/pinctrl-s3c64xx.c
index 89143c903000..89143c903000 100644
--- a/drivers/pinctrl/pinctrl-s3c64xx.c
+++ b/drivers/pinctrl/samsung/pinctrl-s3c64xx.c
diff --git a/drivers/pinctrl/pinctrl-samsung.c b/drivers/pinctrl/samsung/pinctrl-samsung.c
index 3e61d0f8f146..2d37c8f49f3c 100644
--- a/drivers/pinctrl/pinctrl-samsung.c
+++ b/drivers/pinctrl/samsung/pinctrl-samsung.c
@@ -30,7 +30,7 @@
30#include <linux/spinlock.h> 30#include <linux/spinlock.h>
31#include <linux/syscore_ops.h> 31#include <linux/syscore_ops.h>
32 32
33#include "core.h" 33#include "../core.h"
34#include "pinctrl-samsung.h" 34#include "pinctrl-samsung.h"
35 35
36#define GROUP_SUFFIX "-grp" 36#define GROUP_SUFFIX "-grp"
@@ -40,13 +40,14 @@
40 40
41/* list of all possible config options supported */ 41/* list of all possible config options supported */
42static struct pin_config { 42static struct pin_config {
43 char *prop_cfg; 43 const char *property;
44 unsigned int cfg_type; 44 enum pincfg_type param;
45} pcfgs[] = { 45} cfg_params[] = {
46 { "samsung,pin-pud", PINCFG_TYPE_PUD }, 46 { "samsung,pin-pud", PINCFG_TYPE_PUD },
47 { "samsung,pin-drv", PINCFG_TYPE_DRV }, 47 { "samsung,pin-drv", PINCFG_TYPE_DRV },
48 { "samsung,pin-con-pdn", PINCFG_TYPE_CON_PDN }, 48 { "samsung,pin-con-pdn", PINCFG_TYPE_CON_PDN },
49 { "samsung,pin-pud-pdn", PINCFG_TYPE_PUD_PDN }, 49 { "samsung,pin-pud-pdn", PINCFG_TYPE_PUD_PDN },
50 { "samsung,pin-val", PINCFG_TYPE_DAT },
50}; 51};
51 52
52/* Global list of devices (struct samsung_pinctrl_drv_data) */ 53/* Global list of devices (struct samsung_pinctrl_drv_data) */
@@ -59,163 +60,242 @@ static inline struct samsung_pin_bank *gc_to_pin_bank(struct gpio_chip *gc)
59 return container_of(gc, struct samsung_pin_bank, gpio_chip); 60 return container_of(gc, struct samsung_pin_bank, gpio_chip);
60} 61}
61 62
62/* check if the selector is a valid pin group selector */
63static int samsung_get_group_count(struct pinctrl_dev *pctldev) 63static int samsung_get_group_count(struct pinctrl_dev *pctldev)
64{ 64{
65 struct samsung_pinctrl_drv_data *drvdata; 65 struct samsung_pinctrl_drv_data *pmx = pinctrl_dev_get_drvdata(pctldev);
66 66
67 drvdata = pinctrl_dev_get_drvdata(pctldev); 67 return pmx->nr_groups;
68 return drvdata->nr_groups;
69} 68}
70 69
71/* return the name of the group selected by the group selector */
72static const char *samsung_get_group_name(struct pinctrl_dev *pctldev, 70static const char *samsung_get_group_name(struct pinctrl_dev *pctldev,
73 unsigned selector) 71 unsigned group)
74{ 72{
75 struct samsung_pinctrl_drv_data *drvdata; 73 struct samsung_pinctrl_drv_data *pmx = pinctrl_dev_get_drvdata(pctldev);
76 74
77 drvdata = pinctrl_dev_get_drvdata(pctldev); 75 return pmx->pin_groups[group].name;
78 return drvdata->pin_groups[selector].name;
79} 76}
80 77
81/* return the pin numbers associated with the specified group */
82static int samsung_get_group_pins(struct pinctrl_dev *pctldev, 78static int samsung_get_group_pins(struct pinctrl_dev *pctldev,
83 unsigned selector, const unsigned **pins, unsigned *num_pins) 79 unsigned group,
80 const unsigned **pins,
81 unsigned *num_pins)
84{ 82{
85 struct samsung_pinctrl_drv_data *drvdata; 83 struct samsung_pinctrl_drv_data *pmx = pinctrl_dev_get_drvdata(pctldev);
84
85 *pins = pmx->pin_groups[group].pins;
86 *num_pins = pmx->pin_groups[group].num_pins;
86 87
87 drvdata = pinctrl_dev_get_drvdata(pctldev);
88 *pins = drvdata->pin_groups[selector].pins;
89 *num_pins = drvdata->pin_groups[selector].num_pins;
90 return 0; 88 return 0;
91} 89}
92 90
93/* create pinctrl_map entries by parsing device tree nodes */ 91static int reserve_map(struct device *dev, struct pinctrl_map **map,
94static int samsung_dt_node_to_map(struct pinctrl_dev *pctldev, 92 unsigned *reserved_maps, unsigned *num_maps,
95 struct device_node *np, struct pinctrl_map **maps, 93 unsigned reserve)
96 unsigned *nmaps)
97{ 94{
98 struct device *dev = pctldev->dev; 95 unsigned old_num = *reserved_maps;
99 struct pinctrl_map *map; 96 unsigned new_num = *num_maps + reserve;
100 unsigned long *cfg = NULL; 97 struct pinctrl_map *new_map;
101 char *gname, *fname;
102 int cfg_cnt = 0, map_cnt = 0, idx = 0;
103
104 /* count the number of config options specfied in the node */
105 for (idx = 0; idx < ARRAY_SIZE(pcfgs); idx++) {
106 if (of_find_property(np, pcfgs[idx].prop_cfg, NULL))
107 cfg_cnt++;
108 }
109 98
110 /* 99 if (old_num >= new_num)
111 * Find out the number of map entries to create. All the config options 100 return 0;
112 * can be accomadated into a single config map entry.
113 */
114 if (cfg_cnt)
115 map_cnt = 1;
116 if (of_find_property(np, "samsung,pin-function", NULL))
117 map_cnt++;
118 if (!map_cnt) {
119 dev_err(dev, "node %s does not have either config or function "
120 "configurations\n", np->name);
121 return -EINVAL;
122 }
123 101
124 /* Allocate memory for pin-map entries */ 102 new_map = krealloc(*map, sizeof(*new_map) * new_num, GFP_KERNEL);
125 map = kzalloc(sizeof(*map) * map_cnt, GFP_KERNEL); 103 if (!new_map) {
126 if (!map) { 104 dev_err(dev, "krealloc(map) failed\n");
127 dev_err(dev, "could not alloc memory for pin-maps\n");
128 return -ENOMEM; 105 return -ENOMEM;
129 } 106 }
130 *nmaps = 0;
131 107
132 /* 108 memset(new_map + old_num, 0, (new_num - old_num) * sizeof(*new_map));
133 * Allocate memory for pin group name. The pin group name is derived 109
134 * from the node name from which these map entries are be created. 110 *map = new_map;
135 */ 111 *reserved_maps = new_num;
136 gname = kzalloc(strlen(np->name) + GSUFFIX_LEN, GFP_KERNEL); 112
137 if (!gname) { 113 return 0;
138 dev_err(dev, "failed to alloc memory for group name\n"); 114}
139 goto free_map; 115
116static int add_map_mux(struct pinctrl_map **map, unsigned *reserved_maps,
117 unsigned *num_maps, const char *group,
118 const char *function)
119{
120 if (WARN_ON(*num_maps == *reserved_maps))
121 return -ENOSPC;
122
123 (*map)[*num_maps].type = PIN_MAP_TYPE_MUX_GROUP;
124 (*map)[*num_maps].data.mux.group = group;
125 (*map)[*num_maps].data.mux.function = function;
126 (*num_maps)++;
127
128 return 0;
129}
130
131static int add_map_configs(struct device *dev, struct pinctrl_map **map,
132 unsigned *reserved_maps, unsigned *num_maps,
133 const char *group, unsigned long *configs,
134 unsigned num_configs)
135{
136 unsigned long *dup_configs;
137
138 if (WARN_ON(*num_maps == *reserved_maps))
139 return -ENOSPC;
140
141 dup_configs = kmemdup(configs, num_configs * sizeof(*dup_configs),
142 GFP_KERNEL);
143 if (!dup_configs) {
144 dev_err(dev, "kmemdup(configs) failed\n");
145 return -ENOMEM;
140 } 146 }
141 sprintf(gname, "%s%s", np->name, GROUP_SUFFIX);
142 147
143 /* 148 (*map)[*num_maps].type = PIN_MAP_TYPE_CONFIGS_GROUP;
144 * don't have config options? then skip over to creating function 149 (*map)[*num_maps].data.configs.group_or_pin = group;
145 * map entries. 150 (*map)[*num_maps].data.configs.configs = dup_configs;
146 */ 151 (*map)[*num_maps].data.configs.num_configs = num_configs;
147 if (!cfg_cnt) 152 (*num_maps)++;
148 goto skip_cfgs; 153
149 154 return 0;
150 /* Allocate memory for config entries */ 155}
151 cfg = kzalloc(sizeof(*cfg) * cfg_cnt, GFP_KERNEL); 156
152 if (!cfg) { 157static int add_config(struct device *dev, unsigned long **configs,
153 dev_err(dev, "failed to alloc memory for configs\n"); 158 unsigned *num_configs, unsigned long config)
154 goto free_gname; 159{
160 unsigned old_num = *num_configs;
161 unsigned new_num = old_num + 1;
162 unsigned long *new_configs;
163
164 new_configs = krealloc(*configs, sizeof(*new_configs) * new_num,
165 GFP_KERNEL);
166 if (!new_configs) {
167 dev_err(dev, "krealloc(configs) failed\n");
168 return -ENOMEM;
155 } 169 }
156 170
157 /* Prepare a list of config settings */ 171 new_configs[old_num] = config;
158 for (idx = 0, cfg_cnt = 0; idx < ARRAY_SIZE(pcfgs); idx++) { 172
159 u32 value; 173 *configs = new_configs;
160 if (!of_property_read_u32(np, pcfgs[idx].prop_cfg, &value)) 174 *num_configs = new_num;
161 cfg[cfg_cnt++] = 175
162 PINCFG_PACK(pcfgs[idx].cfg_type, value); 176 return 0;
177}
178
179static void samsung_dt_free_map(struct pinctrl_dev *pctldev,
180 struct pinctrl_map *map,
181 unsigned num_maps)
182{
183 int i;
184
185 for (i = 0; i < num_maps; i++)
186 if (map[i].type == PIN_MAP_TYPE_CONFIGS_GROUP)
187 kfree(map[i].data.configs.configs);
188
189 kfree(map);
190}
191
192static int samsung_dt_subnode_to_map(struct samsung_pinctrl_drv_data *drvdata,
193 struct device *dev,
194 struct device_node *np,
195 struct pinctrl_map **map,
196 unsigned *reserved_maps,
197 unsigned *num_maps)
198{
199 int ret, i;
200 u32 val;
201 unsigned long config;
202 unsigned long *configs = NULL;
203 unsigned num_configs = 0;
204 unsigned reserve;
205 struct property *prop;
206 const char *group;
207 bool has_func = false;
208
209 ret = of_property_read_u32(np, "samsung,pin-function", &val);
210 if (!ret)
211 has_func = true;
212
213 for (i = 0; i < ARRAY_SIZE(cfg_params); i++) {
214 ret = of_property_read_u32(np, cfg_params[i].property, &val);
215 if (!ret) {
216 config = PINCFG_PACK(cfg_params[i].param, val);
217 ret = add_config(dev, &configs, &num_configs, config);
218 if (ret < 0)
219 goto exit;
220 /* EINVAL=missing, which is fine since it's optional */
221 } else if (ret != -EINVAL) {
222 dev_err(dev, "could not parse property %s\n",
223 cfg_params[i].property);
224 }
163 } 225 }
164 226
165 /* create the config map entry */ 227 reserve = 0;
166 map[*nmaps].data.configs.group_or_pin = gname; 228 if (has_func)
167 map[*nmaps].data.configs.configs = cfg; 229 reserve++;
168 map[*nmaps].data.configs.num_configs = cfg_cnt; 230 if (num_configs)
169 map[*nmaps].type = PIN_MAP_TYPE_CONFIGS_GROUP; 231 reserve++;
170 *nmaps += 1; 232 ret = of_property_count_strings(np, "samsung,pins");
171 233 if (ret < 0) {
172skip_cfgs: 234 dev_err(dev, "could not parse property samsung,pins\n");
173 /* create the function map entry */ 235 goto exit;
174 if (of_find_property(np, "samsung,pin-function", NULL)) { 236 }
175 fname = kzalloc(strlen(np->name) + FSUFFIX_LEN, GFP_KERNEL); 237 reserve *= ret;
176 if (!fname) { 238
177 dev_err(dev, "failed to alloc memory for func name\n"); 239 ret = reserve_map(dev, map, reserved_maps, num_maps, reserve);
178 goto free_cfg; 240 if (ret < 0)
241 goto exit;
242
243 of_property_for_each_string(np, "samsung,pins", prop, group) {
244 if (has_func) {
245 ret = add_map_mux(map, reserved_maps,
246 num_maps, group, np->full_name);
247 if (ret < 0)
248 goto exit;
179 } 249 }
180 sprintf(fname, "%s%s", np->name, FUNCTION_SUFFIX);
181 250
182 map[*nmaps].data.mux.group = gname; 251 if (num_configs) {
183 map[*nmaps].data.mux.function = fname; 252 ret = add_map_configs(dev, map, reserved_maps,
184 map[*nmaps].type = PIN_MAP_TYPE_MUX_GROUP; 253 num_maps, group, configs,
185 *nmaps += 1; 254 num_configs);
255 if (ret < 0)
256 goto exit;
257 }
186 } 258 }
187 259
188 *maps = map; 260 ret = 0;
189 return 0;
190 261
191free_cfg: 262exit:
192 kfree(cfg); 263 kfree(configs);
193free_gname: 264 return ret;
194 kfree(gname);
195free_map:
196 kfree(map);
197 return -ENOMEM;
198} 265}
199 266
200/* free the memory allocated to hold the pin-map table */ 267static int samsung_dt_node_to_map(struct pinctrl_dev *pctldev,
201static void samsung_dt_free_map(struct pinctrl_dev *pctldev, 268 struct device_node *np_config,
202 struct pinctrl_map *map, unsigned num_maps) 269 struct pinctrl_map **map,
270 unsigned *num_maps)
203{ 271{
204 int idx; 272 struct samsung_pinctrl_drv_data *drvdata;
205 273 unsigned reserved_maps;
206 for (idx = 0; idx < num_maps; idx++) { 274 struct device_node *np;
207 if (map[idx].type == PIN_MAP_TYPE_MUX_GROUP) { 275 int ret;
208 kfree(map[idx].data.mux.function); 276
209 if (!idx) 277 drvdata = pinctrl_dev_get_drvdata(pctldev);
210 kfree(map[idx].data.mux.group); 278
211 } else if (map->type == PIN_MAP_TYPE_CONFIGS_GROUP) { 279 reserved_maps = 0;
212 kfree(map[idx].data.configs.configs); 280 *map = NULL;
213 if (!idx) 281 *num_maps = 0;
214 kfree(map[idx].data.configs.group_or_pin); 282
283 if (!of_get_child_count(np_config))
284 return samsung_dt_subnode_to_map(drvdata, pctldev->dev,
285 np_config, map,
286 &reserved_maps,
287 num_maps);
288
289 for_each_child_of_node(np_config, np) {
290 ret = samsung_dt_subnode_to_map(drvdata, pctldev->dev, np, map,
291 &reserved_maps, num_maps);
292 if (ret < 0) {
293 samsung_dt_free_map(pctldev, *map, *num_maps);
294 return ret;
215 } 295 }
216 }; 296 }
217 297
218 kfree(map); 298 return 0;
219} 299}
220 300
221/* list of pinctrl callbacks for the pinctrl core */ 301/* list of pinctrl callbacks for the pinctrl core */
@@ -286,83 +366,21 @@ static void samsung_pinmux_setup(struct pinctrl_dev *pctldev, unsigned selector,
286 unsigned group, bool enable) 366 unsigned group, bool enable)
287{ 367{
288 struct samsung_pinctrl_drv_data *drvdata; 368 struct samsung_pinctrl_drv_data *drvdata;
289 const unsigned int *pins;
290 struct samsung_pin_bank *bank;
291 void __iomem *reg;
292 u32 mask, shift, data, pin_offset, cnt;
293 unsigned long flags;
294
295 drvdata = pinctrl_dev_get_drvdata(pctldev);
296 pins = drvdata->pin_groups[group].pins;
297
298 /*
299 * for each pin in the pin group selected, program the correspoding pin
300 * pin function number in the config register.
301 */
302 for (cnt = 0; cnt < drvdata->pin_groups[group].num_pins; cnt++) {
303 struct samsung_pin_bank_type *type;
304
305 pin_to_reg_bank(drvdata, pins[cnt] - drvdata->ctrl->base,
306 &reg, &pin_offset, &bank);
307 type = bank->type;
308 mask = (1 << type->fld_width[PINCFG_TYPE_FUNC]) - 1;
309 shift = pin_offset * type->fld_width[PINCFG_TYPE_FUNC];
310 if (shift >= 32) {
311 /* Some banks have two config registers */
312 shift -= 32;
313 reg += 4;
314 }
315
316 spin_lock_irqsave(&bank->slock, flags);
317
318 data = readl(reg + type->reg_offset[PINCFG_TYPE_FUNC]);
319 data &= ~(mask << shift);
320 if (enable)
321 data |= drvdata->pin_groups[group].func << shift;
322 writel(data, reg + type->reg_offset[PINCFG_TYPE_FUNC]);
323
324 spin_unlock_irqrestore(&bank->slock, flags);
325 }
326}
327
328/* enable a specified pinmux by writing to registers */
329static int samsung_pinmux_enable(struct pinctrl_dev *pctldev, unsigned selector,
330 unsigned group)
331{
332 samsung_pinmux_setup(pctldev, selector, group, true);
333 return 0;
334}
335
336/* disable a specified pinmux by writing to registers */
337static void samsung_pinmux_disable(struct pinctrl_dev *pctldev,
338 unsigned selector, unsigned group)
339{
340 samsung_pinmux_setup(pctldev, selector, group, false);
341}
342
343/*
344 * The calls to gpio_direction_output() and gpio_direction_input()
345 * leads to this function call (via the pinctrl_gpio_direction_{input|output}()
346 * function called from the gpiolib interface).
347 */
348static int samsung_pinmux_gpio_set_direction(struct pinctrl_dev *pctldev,
349 struct pinctrl_gpio_range *range, unsigned offset, bool input)
350{
351 struct samsung_pin_bank_type *type; 369 struct samsung_pin_bank_type *type;
352 struct samsung_pin_bank *bank; 370 struct samsung_pin_bank *bank;
353 struct samsung_pinctrl_drv_data *drvdata;
354 void __iomem *reg; 371 void __iomem *reg;
355 u32 data, pin_offset, mask, shift; 372 u32 mask, shift, data, pin_offset;
356 unsigned long flags; 373 unsigned long flags;
374 const struct samsung_pmx_func *func;
375 const struct samsung_pin_group *grp;
357 376
358 bank = gc_to_pin_bank(range->gc);
359 type = bank->type;
360 drvdata = pinctrl_dev_get_drvdata(pctldev); 377 drvdata = pinctrl_dev_get_drvdata(pctldev);
378 func = &drvdata->pmx_functions[selector];
379 grp = &drvdata->pin_groups[group];
361 380
362 pin_offset = offset - bank->pin_base; 381 pin_to_reg_bank(drvdata, grp->pins[0] - drvdata->ctrl->base,
363 reg = drvdata->virt_base + bank->pctl_offset + 382 &reg, &pin_offset, &bank);
364 type->reg_offset[PINCFG_TYPE_FUNC]; 383 type = bank->type;
365
366 mask = (1 << type->fld_width[PINCFG_TYPE_FUNC]) - 1; 384 mask = (1 << type->fld_width[PINCFG_TYPE_FUNC]) - 1;
367 shift = pin_offset * type->fld_width[PINCFG_TYPE_FUNC]; 385 shift = pin_offset * type->fld_width[PINCFG_TYPE_FUNC];
368 if (shift >= 32) { 386 if (shift >= 32) {
@@ -373,14 +391,21 @@ static int samsung_pinmux_gpio_set_direction(struct pinctrl_dev *pctldev,
373 391
374 spin_lock_irqsave(&bank->slock, flags); 392 spin_lock_irqsave(&bank->slock, flags);
375 393
376 data = readl(reg); 394 data = readl(reg + type->reg_offset[PINCFG_TYPE_FUNC]);
377 data &= ~(mask << shift); 395 data &= ~(mask << shift);
378 if (!input) 396 if (enable)
379 data |= FUNC_OUTPUT << shift; 397 data |= func->val << shift;
380 writel(data, reg); 398 writel(data, reg + type->reg_offset[PINCFG_TYPE_FUNC]);
381 399
382 spin_unlock_irqrestore(&bank->slock, flags); 400 spin_unlock_irqrestore(&bank->slock, flags);
401}
383 402
403/* enable a specified pinmux by writing to registers */
404static int samsung_pinmux_set_mux(struct pinctrl_dev *pctldev,
405 unsigned selector,
406 unsigned group)
407{
408 samsung_pinmux_setup(pctldev, selector, group, true);
384 return 0; 409 return 0;
385} 410}
386 411
@@ -389,9 +414,7 @@ static const struct pinmux_ops samsung_pinmux_ops = {
389 .get_functions_count = samsung_get_functions_count, 414 .get_functions_count = samsung_get_functions_count,
390 .get_function_name = samsung_pinmux_get_fname, 415 .get_function_name = samsung_pinmux_get_fname,
391 .get_function_groups = samsung_pinmux_get_groups, 416 .get_function_groups = samsung_pinmux_get_groups,
392 .enable = samsung_pinmux_enable, 417 .set_mux = samsung_pinmux_set_mux,
393 .disable = samsung_pinmux_disable,
394 .gpio_set_direction = samsung_pinmux_gpio_set_direction,
395}; 418};
396 419
397/* set or get the pin config settings for a specified pin */ 420/* set or get the pin config settings for a specified pin */
@@ -540,25 +563,59 @@ static int samsung_gpio_get(struct gpio_chip *gc, unsigned offset)
540} 563}
541 564
542/* 565/*
543 * gpiolib gpio_direction_input callback function. The setting of the pin 566 * The calls to gpio_direction_output() and gpio_direction_input()
544 * mux function as 'gpio input' will be handled by the pinctrl susbsystem 567 * leads to this function call.
545 * interface.
546 */ 568 */
569static int samsung_gpio_set_direction(struct gpio_chip *gc,
570 unsigned offset, bool input)
571{
572 struct samsung_pin_bank_type *type;
573 struct samsung_pin_bank *bank;
574 struct samsung_pinctrl_drv_data *drvdata;
575 void __iomem *reg;
576 u32 data, mask, shift;
577 unsigned long flags;
578
579 bank = gc_to_pin_bank(gc);
580 type = bank->type;
581 drvdata = bank->drvdata;
582
583 reg = drvdata->virt_base + bank->pctl_offset +
584 type->reg_offset[PINCFG_TYPE_FUNC];
585
586 mask = (1 << type->fld_width[PINCFG_TYPE_FUNC]) - 1;
587 shift = offset * type->fld_width[PINCFG_TYPE_FUNC];
588 if (shift >= 32) {
589 /* Some banks have two config registers */
590 shift -= 32;
591 reg += 4;
592 }
593
594 spin_lock_irqsave(&bank->slock, flags);
595
596 data = readl(reg);
597 data &= ~(mask << shift);
598 if (!input)
599 data |= FUNC_OUTPUT << shift;
600 writel(data, reg);
601
602 spin_unlock_irqrestore(&bank->slock, flags);
603
604 return 0;
605}
606
607/* gpiolib gpio_direction_input callback function. */
547static int samsung_gpio_direction_input(struct gpio_chip *gc, unsigned offset) 608static int samsung_gpio_direction_input(struct gpio_chip *gc, unsigned offset)
548{ 609{
549 return pinctrl_gpio_direction_input(gc->base + offset); 610 return samsung_gpio_set_direction(gc, offset, true);
550} 611}
551 612
552/* 613/* gpiolib gpio_direction_output callback function. */
553 * gpiolib gpio_direction_output callback function. The setting of the pin
554 * mux function as 'gpio output' will be handled by the pinctrl susbsystem
555 * interface.
556 */
557static int samsung_gpio_direction_output(struct gpio_chip *gc, unsigned offset, 614static int samsung_gpio_direction_output(struct gpio_chip *gc, unsigned offset,
558 int value) 615 int value)
559{ 616{
560 samsung_gpio_set(gc, offset, value); 617 samsung_gpio_set(gc, offset, value);
561 return pinctrl_gpio_direction_output(gc->base + offset); 618 return samsung_gpio_set_direction(gc, offset, false);
562} 619}
563 620
564/* 621/*
@@ -578,87 +635,115 @@ static int samsung_gpio_to_irq(struct gpio_chip *gc, unsigned offset)
578 return (virq) ? : -ENXIO; 635 return (virq) ? : -ENXIO;
579} 636}
580 637
581/* 638static struct samsung_pin_group *samsung_pinctrl_create_groups(
582 * Parse the pin names listed in the 'samsung,pins' property and convert it 639 struct device *dev,
583 * into a list of gpio numbers are create a pin group from it. 640 struct samsung_pinctrl_drv_data *drvdata,
584 */ 641 unsigned int *cnt)
585static int samsung_pinctrl_parse_dt_pins(struct platform_device *pdev,
586 struct device_node *cfg_np,
587 struct pinctrl_desc *pctl,
588 unsigned int **pin_list,
589 unsigned int *npins)
590{ 642{
591 struct device *dev = &pdev->dev; 643 struct pinctrl_desc *ctrldesc = &drvdata->pctl;
592 struct property *prop; 644 struct samsung_pin_group *groups, *grp;
593 struct pinctrl_pin_desc const *pdesc = pctl->pins; 645 const struct pinctrl_pin_desc *pdesc;
594 unsigned int idx = 0, cnt; 646 int i;
595 const char *pin_name; 647
648 groups = devm_kzalloc(dev, ctrldesc->npins * sizeof(*groups),
649 GFP_KERNEL);
650 if (!groups)
651 return ERR_PTR(-EINVAL);
652 grp = groups;
653
654 pdesc = ctrldesc->pins;
655 for (i = 0; i < ctrldesc->npins; ++i, ++pdesc, ++grp) {
656 grp->name = pdesc->name;
657 grp->pins = &pdesc->number;
658 grp->num_pins = 1;
659 }
660
661 *cnt = ctrldesc->npins;
662 return groups;
663}
664
665static int samsung_pinctrl_create_function(struct device *dev,
666 struct samsung_pinctrl_drv_data *drvdata,
667 struct device_node *func_np,
668 struct samsung_pmx_func *func)
669{
670 int npins;
671 int ret;
672 int i;
673
674 if (of_property_read_u32(func_np, "samsung,pin-function", &func->val))
675 return 0;
596 676
597 *npins = of_property_count_strings(cfg_np, "samsung,pins"); 677 npins = of_property_count_strings(func_np, "samsung,pins");
598 if (IS_ERR_VALUE(*npins)) { 678 if (npins < 1) {
599 dev_err(dev, "invalid pin list in %s node", cfg_np->name); 679 dev_err(dev, "invalid pin list in %s node", func_np->name);
600 return -EINVAL; 680 return -EINVAL;
601 } 681 }
602 682
603 *pin_list = devm_kzalloc(dev, *npins * sizeof(**pin_list), GFP_KERNEL); 683 func->name = func_np->full_name;
604 if (!*pin_list) { 684
605 dev_err(dev, "failed to allocate memory for pin list\n"); 685 func->groups = devm_kzalloc(dev, npins * sizeof(char *), GFP_KERNEL);
686 if (!func->groups)
606 return -ENOMEM; 687 return -ENOMEM;
607 }
608 688
609 of_property_for_each_string(cfg_np, "samsung,pins", prop, pin_name) { 689 for (i = 0; i < npins; ++i) {
610 for (cnt = 0; cnt < pctl->npins; cnt++) { 690 const char *gname;
611 if (pdesc[cnt].name) { 691
612 if (!strcmp(pin_name, pdesc[cnt].name)) { 692 ret = of_property_read_string_index(func_np, "samsung,pins",
613 (*pin_list)[idx++] = pdesc[cnt].number; 693 i, &gname);
614 break; 694 if (ret) {
615 } 695 dev_err(dev,
616 } 696 "failed to read pin name %d from %s node\n",
617 } 697 i, func_np->name);
618 if (cnt == pctl->npins) { 698 return ret;
619 dev_err(dev, "pin %s not valid in %s node\n",
620 pin_name, cfg_np->name);
621 devm_kfree(dev, *pin_list);
622 return -EINVAL;
623 } 699 }
700
701 func->groups[i] = gname;
624 } 702 }
625 703
626 return 0; 704 func->num_groups = npins;
705 return 1;
627} 706}
628 707
629/* 708static struct samsung_pmx_func *samsung_pinctrl_create_functions(
630 * Parse the information about all the available pin groups and pin functions 709 struct device *dev,
631 * from device node of the pin-controller. A pin group is formed with all 710 struct samsung_pinctrl_drv_data *drvdata,
632 * the pins listed in the "samsung,pins" property. 711 unsigned int *cnt)
633 */
634static int samsung_pinctrl_parse_dt(struct platform_device *pdev,
635 struct samsung_pinctrl_drv_data *drvdata)
636{ 712{
637 struct device *dev = &pdev->dev; 713 struct samsung_pmx_func *functions, *func;
638 struct device_node *dev_np = dev->of_node; 714 struct device_node *dev_np = dev->of_node;
639 struct device_node *cfg_np; 715 struct device_node *cfg_np;
640 struct samsung_pin_group *groups, *grp; 716 unsigned int func_cnt = 0;
641 struct samsung_pmx_func *functions, *func;
642 unsigned *pin_list;
643 unsigned int npins, grp_cnt, func_idx = 0;
644 char *gname, *fname;
645 int ret; 717 int ret;
646 718
647 grp_cnt = of_get_child_count(dev_np); 719 /*
648 if (!grp_cnt) 720 * Iterate over all the child nodes of the pin controller node
649 return -EINVAL; 721 * and create pin groups and pin function lists.
722 */
723 for_each_child_of_node(dev_np, cfg_np) {
724 struct device_node *func_np;
650 725
651 groups = devm_kzalloc(dev, grp_cnt * sizeof(*groups), GFP_KERNEL); 726 if (!of_get_child_count(cfg_np)) {
652 if (!groups) { 727 if (!of_find_property(cfg_np,
653 dev_err(dev, "failed allocate memory for ping group list\n"); 728 "samsung,pin-function", NULL))
654 return -EINVAL; 729 continue;
730 ++func_cnt;
731 continue;
732 }
733
734 for_each_child_of_node(cfg_np, func_np) {
735 if (!of_find_property(func_np,
736 "samsung,pin-function", NULL))
737 continue;
738 ++func_cnt;
739 }
655 } 740 }
656 grp = groups;
657 741
658 functions = devm_kzalloc(dev, grp_cnt * sizeof(*functions), GFP_KERNEL); 742 functions = devm_kzalloc(dev, func_cnt * sizeof(*functions),
743 GFP_KERNEL);
659 if (!functions) { 744 if (!functions) {
660 dev_err(dev, "failed to allocate memory for function list\n"); 745 dev_err(dev, "failed to allocate memory for function list\n");
661 return -EINVAL; 746 return ERR_PTR(-EINVAL);
662 } 747 }
663 func = functions; 748 func = functions;
664 749
@@ -666,61 +751,68 @@ static int samsung_pinctrl_parse_dt(struct platform_device *pdev,
666 * Iterate over all the child nodes of the pin controller node 751 * Iterate over all the child nodes of the pin controller node
667 * and create pin groups and pin function lists. 752 * and create pin groups and pin function lists.
668 */ 753 */
754 func_cnt = 0;
669 for_each_child_of_node(dev_np, cfg_np) { 755 for_each_child_of_node(dev_np, cfg_np) {
670 u32 function; 756 struct device_node *func_np;
671 if (!of_find_property(cfg_np, "samsung,pins", NULL)) 757
758 if (!of_get_child_count(cfg_np)) {
759 ret = samsung_pinctrl_create_function(dev, drvdata,
760 cfg_np, func);
761 if (ret < 0)
762 return ERR_PTR(ret);
763 if (ret > 0) {
764 ++func;
765 ++func_cnt;
766 }
672 continue; 767 continue;
768 }
673 769
674 ret = samsung_pinctrl_parse_dt_pins(pdev, cfg_np, 770 for_each_child_of_node(cfg_np, func_np) {
675 &drvdata->pctl, &pin_list, &npins); 771 ret = samsung_pinctrl_create_function(dev, drvdata,
676 if (ret) 772 func_np, func);
677 return ret; 773 if (ret < 0)
678 774 return ERR_PTR(ret);
679 /* derive pin group name from the node name */ 775 if (ret > 0) {
680 gname = devm_kzalloc(dev, strlen(cfg_np->name) + GSUFFIX_LEN, 776 ++func;
681 GFP_KERNEL); 777 ++func_cnt;
682 if (!gname) { 778 }
683 dev_err(dev, "failed to alloc memory for group name\n");
684 return -ENOMEM;
685 } 779 }
686 sprintf(gname, "%s%s", cfg_np->name, GROUP_SUFFIX); 780 }
687 781
688 grp->name = gname; 782 *cnt = func_cnt;
689 grp->pins = pin_list; 783 return functions;
690 grp->num_pins = npins; 784}
691 of_property_read_u32(cfg_np, "samsung,pin-function", &function);
692 grp->func = function;
693 grp++;
694 785
695 if (!of_find_property(cfg_np, "samsung,pin-function", NULL)) 786/*
696 continue; 787 * Parse the information about all the available pin groups and pin functions
788 * from device node of the pin-controller. A pin group is formed with all
789 * the pins listed in the "samsung,pins" property.
790 */
697 791
698 /* derive function name from the node name */ 792static int samsung_pinctrl_parse_dt(struct platform_device *pdev,
699 fname = devm_kzalloc(dev, strlen(cfg_np->name) + FSUFFIX_LEN, 793 struct samsung_pinctrl_drv_data *drvdata)
700 GFP_KERNEL); 794{
701 if (!fname) { 795 struct device *dev = &pdev->dev;
702 dev_err(dev, "failed to alloc memory for func name\n"); 796 struct samsung_pin_group *groups;
703 return -ENOMEM; 797 struct samsung_pmx_func *functions;
704 } 798 unsigned int grp_cnt = 0, func_cnt = 0;
705 sprintf(fname, "%s%s", cfg_np->name, FUNCTION_SUFFIX); 799
706 800 groups = samsung_pinctrl_create_groups(dev, drvdata, &grp_cnt);
707 func->name = fname; 801 if (IS_ERR(groups)) {
708 func->groups = devm_kzalloc(dev, sizeof(char *), GFP_KERNEL); 802 dev_err(dev, "failed to parse pin groups\n");
709 if (!func->groups) { 803 return PTR_ERR(groups);
710 dev_err(dev, "failed to alloc memory for group list " 804 }
711 "in pin function"); 805
712 return -ENOMEM; 806 functions = samsung_pinctrl_create_functions(dev, drvdata, &func_cnt);
713 } 807 if (IS_ERR(functions)) {
714 func->groups[0] = gname; 808 dev_err(dev, "failed to parse pin functions\n");
715 func->num_groups = 1; 809 return PTR_ERR(groups);
716 func++;
717 func_idx++;
718 } 810 }
719 811
720 drvdata->pin_groups = groups; 812 drvdata->pin_groups = groups;
721 drvdata->nr_groups = grp_cnt; 813 drvdata->nr_groups = grp_cnt;
722 drvdata->pmx_functions = functions; 814 drvdata->pmx_functions = functions;
723 drvdata->nr_functions = func_idx; 815 drvdata->nr_functions = func_cnt;
724 816
725 return 0; 817 return 0;
726} 818}
@@ -790,7 +882,8 @@ static int samsung_pinctrl_register(struct platform_device *pdev,
790 pin_bank = &drvdata->ctrl->pin_banks[bank]; 882 pin_bank = &drvdata->ctrl->pin_banks[bank];
791 pin_bank->grange.name = pin_bank->name; 883 pin_bank->grange.name = pin_bank->name;
792 pin_bank->grange.id = bank; 884 pin_bank->grange.id = bank;
793 pin_bank->grange.pin_base = pin_bank->pin_base; 885 pin_bank->grange.pin_base = drvdata->ctrl->base
886 + pin_bank->pin_base;
794 pin_bank->grange.base = pin_bank->gpio_chip.base; 887 pin_bank->grange.base = pin_bank->gpio_chip.base;
795 pin_bank->grange.npins = pin_bank->gpio_chip.ngpio; 888 pin_bank->grange.npins = pin_bank->gpio_chip.ngpio;
796 pin_bank->grange.gc = &pin_bank->gpio_chip; 889 pin_bank->grange.gc = &pin_bank->gpio_chip;
@@ -800,7 +893,19 @@ static int samsung_pinctrl_register(struct platform_device *pdev,
800 return 0; 893 return 0;
801} 894}
802 895
896static int samsung_gpio_request(struct gpio_chip *chip, unsigned offset)
897{
898 return pinctrl_request_gpio(chip->base + offset);
899}
900
901static void samsung_gpio_free(struct gpio_chip *chip, unsigned offset)
902{
903 pinctrl_free_gpio(chip->base + offset);
904}
905
803static const struct gpio_chip samsung_gpiolib_chip = { 906static const struct gpio_chip samsung_gpiolib_chip = {
907 .request = samsung_gpio_request,
908 .free = samsung_gpio_free,
804 .set = samsung_gpio_set, 909 .set = samsung_gpio_set,
805 .get = samsung_gpio_get, 910 .get = samsung_gpio_get,
806 .direction_input = samsung_gpio_direction_input, 911 .direction_input = samsung_gpio_direction_input,
@@ -841,9 +946,7 @@ static int samsung_gpiolib_register(struct platform_device *pdev,
841 946
842fail: 947fail:
843 for (--i, --bank; i >= 0; --i, --bank) 948 for (--i, --bank; i >= 0; --i, --bank)
844 if (gpiochip_remove(&bank->gpio_chip)) 949 gpiochip_remove(&bank->gpio_chip);
845 dev_err(&pdev->dev, "gpio chip %s remove failed\n",
846 bank->gpio_chip.label);
847 return ret; 950 return ret;
848} 951}
849 952
@@ -853,16 +956,11 @@ static int samsung_gpiolib_unregister(struct platform_device *pdev,
853{ 956{
854 struct samsung_pin_ctrl *ctrl = drvdata->ctrl; 957 struct samsung_pin_ctrl *ctrl = drvdata->ctrl;
855 struct samsung_pin_bank *bank = ctrl->pin_banks; 958 struct samsung_pin_bank *bank = ctrl->pin_banks;
856 int ret = 0;
857 int i; 959 int i;
858 960
859 for (i = 0; !ret && i < ctrl->nr_banks; ++i, ++bank) 961 for (i = 0; i < ctrl->nr_banks; ++i, ++bank)
860 ret = gpiochip_remove(&bank->gpio_chip); 962 gpiochip_remove(&bank->gpio_chip);
861 963 return 0;
862 if (ret)
863 dev_err(&pdev->dev, "gpio chip remove failed\n");
864
865 return ret;
866} 964}
867 965
868static const struct of_device_id samsung_pinctrl_dt_match[]; 966static const struct of_device_id samsung_pinctrl_dt_match[];
diff --git a/drivers/pinctrl/pinctrl-samsung.h b/drivers/pinctrl/samsung/pinctrl-samsung.h
index b3e41fa5798b..5cedc9d26390 100644
--- a/drivers/pinctrl/pinctrl-samsung.h
+++ b/drivers/pinctrl/samsung/pinctrl-samsung.h
@@ -26,6 +26,7 @@
26#include <linux/gpio.h> 26#include <linux/gpio.h>
27 27
28/* pinmux function number for pin as gpio output line */ 28/* pinmux function number for pin as gpio output line */
29#define FUNC_INPUT 0x0
29#define FUNC_OUTPUT 0x1 30#define FUNC_OUTPUT 0x1
30 31
31/** 32/**
@@ -156,13 +157,6 @@ struct samsung_pin_bank {
156 * @nr_banks: number of pin banks. 157 * @nr_banks: number of pin banks.
157 * @base: starting system wide pin number. 158 * @base: starting system wide pin number.
158 * @nr_pins: number of pins supported by the controller. 159 * @nr_pins: number of pins supported by the controller.
159 * @geint_con: offset of the ext-gpio controller registers.
160 * @geint_mask: offset of the ext-gpio interrupt mask registers.
161 * @geint_pend: offset of the ext-gpio interrupt pending registers.
162 * @weint_con: offset of the ext-wakeup controller registers.
163 * @weint_mask: offset of the ext-wakeup interrupt mask registers.
164 * @weint_pend: offset of the ext-wakeup interrupt pending registers.
165 * @svc: offset of the interrupt service register.
166 * @eint_gpio_init: platform specific callback to setup the external gpio 160 * @eint_gpio_init: platform specific callback to setup the external gpio
167 * interrupts for the controller. 161 * interrupts for the controller.
168 * @eint_wkup_init: platform specific callback to setup the external wakeup 162 * @eint_wkup_init: platform specific callback to setup the external wakeup
@@ -176,16 +170,6 @@ struct samsung_pin_ctrl {
176 u32 base; 170 u32 base;
177 u32 nr_pins; 171 u32 nr_pins;
178 172
179 u32 geint_con;
180 u32 geint_mask;
181 u32 geint_pend;
182
183 u32 weint_con;
184 u32 weint_mask;
185 u32 weint_pend;
186
187 u32 svc;
188
189 int (*eint_gpio_init)(struct samsung_pinctrl_drv_data *); 173 int (*eint_gpio_init)(struct samsung_pinctrl_drv_data *);
190 int (*eint_wkup_init)(struct samsung_pinctrl_drv_data *); 174 int (*eint_wkup_init)(struct samsung_pinctrl_drv_data *);
191 void (*suspend)(struct samsung_pinctrl_drv_data *); 175 void (*suspend)(struct samsung_pinctrl_drv_data *);
@@ -248,6 +232,7 @@ struct samsung_pmx_func {
248 const char *name; 232 const char *name;
249 const char **groups; 233 const char **groups;
250 u8 num_groups; 234 u8 num_groups;
235 u32 val;
251}; 236};
252 237
253/* list of all exported SoC specific data */ 238/* list of all exported SoC specific data */
diff --git a/drivers/pinctrl/sh-pfc/core.c b/drivers/pinctrl/sh-pfc/core.c
index b9b464d0578c..6572c233f73d 100644
--- a/drivers/pinctrl/sh-pfc/core.c
+++ b/drivers/pinctrl/sh-pfc/core.c
@@ -542,7 +542,7 @@ static int sh_pfc_probe(struct platform_device *pdev)
542 */ 542 */
543 ret = sh_pfc_register_pinctrl(pfc); 543 ret = sh_pfc_register_pinctrl(pfc);
544 if (unlikely(ret != 0)) 544 if (unlikely(ret != 0))
545 goto error; 545 return ret;
546 546
547#ifdef CONFIG_GPIO_SH_PFC 547#ifdef CONFIG_GPIO_SH_PFC
548 /* 548 /*
@@ -564,11 +564,6 @@ static int sh_pfc_probe(struct platform_device *pdev)
564 dev_info(pfc->dev, "%s support registered\n", info->name); 564 dev_info(pfc->dev, "%s support registered\n", info->name);
565 565
566 return 0; 566 return 0;
567
568error:
569 if (info->ops && info->ops->exit)
570 info->ops->exit(pfc);
571 return ret;
572} 567}
573 568
574static int sh_pfc_remove(struct platform_device *pdev) 569static int sh_pfc_remove(struct platform_device *pdev)
@@ -580,9 +575,6 @@ static int sh_pfc_remove(struct platform_device *pdev)
580#endif 575#endif
581 sh_pfc_unregister_pinctrl(pfc); 576 sh_pfc_unregister_pinctrl(pfc);
582 577
583 if (pfc->info->ops && pfc->info->ops->exit)
584 pfc->info->ops->exit(pfc);
585
586 return 0; 578 return 0;
587} 579}
588 580
diff --git a/drivers/pinctrl/sh-pfc/core.h b/drivers/pinctrl/sh-pfc/core.h
index b7b0e6ccf305..3daaa5241c47 100644
--- a/drivers/pinctrl/sh-pfc/core.h
+++ b/drivers/pinctrl/sh-pfc/core.h
@@ -33,7 +33,6 @@ struct sh_pfc_pin_range {
33struct sh_pfc { 33struct sh_pfc {
34 struct device *dev; 34 struct device *dev;
35 const struct sh_pfc_soc_info *info; 35 const struct sh_pfc_soc_info *info;
36 void *soc_data;
37 spinlock_t lock; 36 spinlock_t lock;
38 37
39 unsigned int num_windows; 38 unsigned int num_windows;
diff --git a/drivers/pinctrl/sh-pfc/gpio.c b/drivers/pinctrl/sh-pfc/gpio.c
index a9288ab01f7b..80f641ee4dea 100644
--- a/drivers/pinctrl/sh-pfc/gpio.c
+++ b/drivers/pinctrl/sh-pfc/gpio.c
@@ -409,11 +409,8 @@ int sh_pfc_register_gpiochip(struct sh_pfc *pfc)
409 409
410int sh_pfc_unregister_gpiochip(struct sh_pfc *pfc) 410int sh_pfc_unregister_gpiochip(struct sh_pfc *pfc)
411{ 411{
412 int err; 412 gpiochip_remove(&pfc->gpio->gpio_chip);
413 int ret; 413 gpiochip_remove(&pfc->func->gpio_chip);
414
415 ret = gpiochip_remove(&pfc->gpio->gpio_chip);
416 err = gpiochip_remove(&pfc->func->gpio_chip);
417 414
418 return ret < 0 ? ret : err; 415 return 0;
419} 416}
diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a73a4.c b/drivers/pinctrl/sh-pfc/pfc-r8a73a4.c
index ce9fb7aa8ba3..280a56f97786 100644
--- a/drivers/pinctrl/sh-pfc/pfc-r8a73a4.c
+++ b/drivers/pinctrl/sh-pfc/pfc-r8a73a4.c
@@ -2717,14 +2717,14 @@ static void r8a73a4_pinmux_set_bias(struct sh_pfc *pfc, unsigned int pin,
2717 iowrite8(value, addr); 2717 iowrite8(value, addr);
2718} 2718}
2719 2719
2720static const struct sh_pfc_soc_operations r8a73a4_pinmux_ops = { 2720static const struct sh_pfc_soc_operations r8a73a4_pfc_ops = {
2721 .get_bias = r8a73a4_pinmux_get_bias, 2721 .get_bias = r8a73a4_pinmux_get_bias,
2722 .set_bias = r8a73a4_pinmux_set_bias, 2722 .set_bias = r8a73a4_pinmux_set_bias,
2723}; 2723};
2724 2724
2725const struct sh_pfc_soc_info r8a73a4_pinmux_info = { 2725const struct sh_pfc_soc_info r8a73a4_pinmux_info = {
2726 .name = "r8a73a4_pfc", 2726 .name = "r8a73a4_pfc",
2727 .ops = &r8a73a4_pinmux_ops, 2727 .ops = &r8a73a4_pfc_ops,
2728 2728
2729 .input = { PINMUX_INPUT_BEGIN, PINMUX_INPUT_END }, 2729 .input = { PINMUX_INPUT_BEGIN, PINMUX_INPUT_END },
2730 .output = { PINMUX_OUTPUT_BEGIN, PINMUX_OUTPUT_END }, 2730 .output = { PINMUX_OUTPUT_BEGIN, PINMUX_OUTPUT_END },
diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7740.c b/drivers/pinctrl/sh-pfc/pfc-r8a7740.c
index e4c1ef477053..b486e9d20cc2 100644
--- a/drivers/pinctrl/sh-pfc/pfc-r8a7740.c
+++ b/drivers/pinctrl/sh-pfc/pfc-r8a7740.c
@@ -3752,14 +3752,14 @@ static void r8a7740_pinmux_set_bias(struct sh_pfc *pfc, unsigned int pin,
3752 iowrite8(value, addr); 3752 iowrite8(value, addr);
3753} 3753}
3754 3754
3755static const struct sh_pfc_soc_operations r8a7740_pinmux_ops = { 3755static const struct sh_pfc_soc_operations r8a7740_pfc_ops = {
3756 .get_bias = r8a7740_pinmux_get_bias, 3756 .get_bias = r8a7740_pinmux_get_bias,
3757 .set_bias = r8a7740_pinmux_set_bias, 3757 .set_bias = r8a7740_pinmux_set_bias,
3758}; 3758};
3759 3759
3760const struct sh_pfc_soc_info r8a7740_pinmux_info = { 3760const struct sh_pfc_soc_info r8a7740_pinmux_info = {
3761 .name = "r8a7740_pfc", 3761 .name = "r8a7740_pfc",
3762 .ops = &r8a7740_pinmux_ops, 3762 .ops = &r8a7740_pfc_ops,
3763 3763
3764 .input = { PINMUX_INPUT_BEGIN, 3764 .input = { PINMUX_INPUT_BEGIN,
3765 PINMUX_INPUT_END }, 3765 PINMUX_INPUT_END },
diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7791.c b/drivers/pinctrl/sh-pfc/pfc-r8a7791.c
index 2e688dc4a3c8..c6e5deba238e 100644
--- a/drivers/pinctrl/sh-pfc/pfc-r8a7791.c
+++ b/drivers/pinctrl/sh-pfc/pfc-r8a7791.c
@@ -1726,6 +1726,133 @@ static const unsigned int audio_clkout_mux[] = {
1726 AUDIO_CLKOUT_MARK, 1726 AUDIO_CLKOUT_MARK,
1727}; 1727};
1728 1728
1729/* - CAN -------------------------------------------------------------------- */
1730
1731static const unsigned int can0_data_pins[] = {
1732 /* TX, RX */
1733 RCAR_GP_PIN(3, 26), RCAR_GP_PIN(3, 29),
1734};
1735
1736static const unsigned int can0_data_mux[] = {
1737 CAN0_TX_MARK, CAN0_RX_MARK,
1738};
1739
1740static const unsigned int can0_data_b_pins[] = {
1741 /* TX, RX */
1742 RCAR_GP_PIN(7, 4), RCAR_GP_PIN(7, 3),
1743};
1744
1745static const unsigned int can0_data_b_mux[] = {
1746 CAN0_TX_B_MARK, CAN0_RX_B_MARK,
1747};
1748
1749static const unsigned int can0_data_c_pins[] = {
1750 /* TX, RX */
1751 RCAR_GP_PIN(5, 17), RCAR_GP_PIN(5, 18),
1752};
1753
1754static const unsigned int can0_data_c_mux[] = {
1755 CAN0_TX_C_MARK, CAN0_RX_C_MARK,
1756};
1757
1758static const unsigned int can0_data_d_pins[] = {
1759 /* TX, RX */
1760 RCAR_GP_PIN(2, 26), RCAR_GP_PIN(2, 27),
1761};
1762
1763static const unsigned int can0_data_d_mux[] = {
1764 CAN0_TX_D_MARK, CAN0_RX_D_MARK,
1765};
1766
1767static const unsigned int can0_data_e_pins[] = {
1768 /* TX, RX */
1769 RCAR_GP_PIN(4, 18), RCAR_GP_PIN(4, 28),
1770};
1771
1772static const unsigned int can0_data_e_mux[] = {
1773 CAN0_TX_E_MARK, CAN0_RX_E_MARK,
1774};
1775
1776static const unsigned int can0_data_f_pins[] = {
1777 /* TX, RX */
1778 RCAR_GP_PIN(6, 7), RCAR_GP_PIN(6, 6),
1779};
1780
1781static const unsigned int can0_data_f_mux[] = {
1782 CAN0_TX_F_MARK, CAN0_RX_F_MARK,
1783};
1784
1785static const unsigned int can1_data_pins[] = {
1786 /* TX, RX */
1787 RCAR_GP_PIN(3, 21), RCAR_GP_PIN(3, 20),
1788};
1789
1790static const unsigned int can1_data_mux[] = {
1791 CAN1_TX_MARK, CAN1_RX_MARK,
1792};
1793
1794static const unsigned int can1_data_b_pins[] = {
1795 /* TX, RX */
1796 RCAR_GP_PIN(7, 8), RCAR_GP_PIN(7, 9),
1797};
1798
1799static const unsigned int can1_data_b_mux[] = {
1800 CAN1_TX_B_MARK, CAN1_RX_B_MARK,
1801};
1802
1803static const unsigned int can1_data_c_pins[] = {
1804 /* TX, RX */
1805 RCAR_GP_PIN(5, 20), RCAR_GP_PIN(5, 19),
1806};
1807
1808static const unsigned int can1_data_c_mux[] = {
1809 CAN1_TX_C_MARK, CAN1_RX_C_MARK,
1810};
1811
1812static const unsigned int can1_data_d_pins[] = {
1813 /* TX, RX */
1814 RCAR_GP_PIN(4, 29), RCAR_GP_PIN(4, 31),
1815};
1816
1817static const unsigned int can1_data_d_mux[] = {
1818 CAN1_TX_D_MARK, CAN1_RX_D_MARK,
1819};
1820
1821static const unsigned int can_clk_pins[] = {
1822 /* CLK */
1823 RCAR_GP_PIN(7, 2),
1824};
1825
1826static const unsigned int can_clk_mux[] = {
1827 CAN_CLK_MARK,
1828};
1829
1830static const unsigned int can_clk_b_pins[] = {
1831 /* CLK */
1832 RCAR_GP_PIN(5, 21),
1833};
1834
1835static const unsigned int can_clk_b_mux[] = {
1836 CAN_CLK_B_MARK,
1837};
1838
1839static const unsigned int can_clk_c_pins[] = {
1840 /* CLK */
1841 RCAR_GP_PIN(4, 30),
1842};
1843
1844static const unsigned int can_clk_c_mux[] = {
1845 CAN_CLK_C_MARK,
1846};
1847
1848static const unsigned int can_clk_d_pins[] = {
1849 /* CLK */
1850 RCAR_GP_PIN(7, 19),
1851};
1852
1853static const unsigned int can_clk_d_mux[] = {
1854 CAN_CLK_D_MARK,
1855};
1729 1856
1730/* - DU --------------------------------------------------------------------- */ 1857/* - DU --------------------------------------------------------------------- */
1731static const unsigned int du_rgb666_pins[] = { 1858static const unsigned int du_rgb666_pins[] = {
@@ -1867,6 +1994,192 @@ static const unsigned int eth_rmii_mux[] = {
1867 ETH_RXD0_MARK, ETH_RXD1_MARK, ETH_RX_ER_MARK, ETH_CRS_DV_MARK, 1994 ETH_RXD0_MARK, ETH_RXD1_MARK, ETH_RX_ER_MARK, ETH_CRS_DV_MARK,
1868 ETH_TXD0_MARK, ETH_TXD1_MARK, ETH_TX_EN_MARK, ETH_REFCLK_MARK, 1995 ETH_TXD0_MARK, ETH_TXD1_MARK, ETH_TX_EN_MARK, ETH_REFCLK_MARK,
1869}; 1996};
1997
1998/* - HSCIF0 ----------------------------------------------------------------- */
1999static const unsigned int hscif0_data_pins[] = {
2000 /* RX, TX */
2001 RCAR_GP_PIN(7, 3), RCAR_GP_PIN(7, 4),
2002};
2003static const unsigned int hscif0_data_mux[] = {
2004 HRX0_MARK, HTX0_MARK,
2005};
2006static const unsigned int hscif0_clk_pins[] = {
2007 /* SCK */
2008 RCAR_GP_PIN(7, 2),
2009};
2010static const unsigned int hscif0_clk_mux[] = {
2011 HSCK0_MARK,
2012};
2013static const unsigned int hscif0_ctrl_pins[] = {
2014 /* RTS, CTS */
2015 RCAR_GP_PIN(7, 1), RCAR_GP_PIN(7, 0),
2016};
2017static const unsigned int hscif0_ctrl_mux[] = {
2018 HRTS0_N_MARK, HCTS0_N_MARK,
2019};
2020static const unsigned int hscif0_data_b_pins[] = {
2021 /* RX, TX */
2022 RCAR_GP_PIN(3, 12), RCAR_GP_PIN(3, 15),
2023};
2024static const unsigned int hscif0_data_b_mux[] = {
2025 HRX0_B_MARK, HTX0_B_MARK,
2026};
2027static const unsigned int hscif0_ctrl_b_pins[] = {
2028 /* RTS, CTS */
2029 RCAR_GP_PIN(3, 14), RCAR_GP_PIN(3, 13),
2030};
2031static const unsigned int hscif0_ctrl_b_mux[] = {
2032 HRTS0_N_B_MARK, HCTS0_N_B_MARK,
2033};
2034static const unsigned int hscif0_data_c_pins[] = {
2035 /* RX, TX */
2036 RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 1),
2037};
2038static const unsigned int hscif0_data_c_mux[] = {
2039 HRX0_C_MARK, HTX0_C_MARK,
2040};
2041static const unsigned int hscif0_clk_c_pins[] = {
2042 /* SCK */
2043 RCAR_GP_PIN(5, 31),
2044};
2045static const unsigned int hscif0_clk_c_mux[] = {
2046 HSCK0_C_MARK,
2047};
2048/* - HSCIF1 ----------------------------------------------------------------- */
2049static const unsigned int hscif1_data_pins[] = {
2050 /* RX, TX */
2051 RCAR_GP_PIN(7, 5), RCAR_GP_PIN(7, 6),
2052};
2053static const unsigned int hscif1_data_mux[] = {
2054 HRX1_MARK, HTX1_MARK,
2055};
2056static const unsigned int hscif1_clk_pins[] = {
2057 /* SCK */
2058 RCAR_GP_PIN(7, 7),
2059};
2060static const unsigned int hscif1_clk_mux[] = {
2061 HSCK1_MARK,
2062};
2063static const unsigned int hscif1_ctrl_pins[] = {
2064 /* RTS, CTS */
2065 RCAR_GP_PIN(7, 9), RCAR_GP_PIN(7, 8),
2066};
2067static const unsigned int hscif1_ctrl_mux[] = {
2068 HRTS1_N_MARK, HCTS1_N_MARK,
2069};
2070static const unsigned int hscif1_data_b_pins[] = {
2071 /* RX, TX */
2072 RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 18),
2073};
2074static const unsigned int hscif1_data_b_mux[] = {
2075 HRX1_B_MARK, HTX1_B_MARK,
2076};
2077static const unsigned int hscif1_data_c_pins[] = {
2078 /* RX, TX */
2079 RCAR_GP_PIN(7, 14), RCAR_GP_PIN(7, 15),
2080};
2081static const unsigned int hscif1_data_c_mux[] = {
2082 HRX1_C_MARK, HTX1_C_MARK,
2083};
2084static const unsigned int hscif1_clk_c_pins[] = {
2085 /* SCK */
2086 RCAR_GP_PIN(7, 16),
2087};
2088static const unsigned int hscif1_clk_c_mux[] = {
2089 HSCK1_C_MARK,
2090};
2091static const unsigned int hscif1_ctrl_c_pins[] = {
2092 /* RTS, CTS */
2093 RCAR_GP_PIN(7, 18), RCAR_GP_PIN(7, 17),
2094};
2095static const unsigned int hscif1_ctrl_c_mux[] = {
2096 HRTS1_N_C_MARK, HCTS1_N_C_MARK,
2097};
2098static const unsigned int hscif1_data_d_pins[] = {
2099 /* RX, TX */
2100 RCAR_GP_PIN(4, 28), RCAR_GP_PIN(4, 18),
2101};
2102static const unsigned int hscif1_data_d_mux[] = {
2103 HRX1_D_MARK, HTX1_D_MARK,
2104};
2105static const unsigned int hscif1_data_e_pins[] = {
2106 /* RX, TX */
2107 RCAR_GP_PIN(7, 14), RCAR_GP_PIN(7, 15),
2108};
2109static const unsigned int hscif1_data_e_mux[] = {
2110 HRX1_C_MARK, HTX1_C_MARK,
2111};
2112static const unsigned int hscif1_clk_e_pins[] = {
2113 /* SCK */
2114 RCAR_GP_PIN(2, 6),
2115};
2116static const unsigned int hscif1_clk_e_mux[] = {
2117 HSCK1_E_MARK,
2118};
2119static const unsigned int hscif1_ctrl_e_pins[] = {
2120 /* RTS, CTS */
2121 RCAR_GP_PIN(2, 8), RCAR_GP_PIN(2, 7),
2122};
2123static const unsigned int hscif1_ctrl_e_mux[] = {
2124 HRTS1_N_E_MARK, HCTS1_N_E_MARK,
2125};
2126/* - HSCIF2 ----------------------------------------------------------------- */
2127static const unsigned int hscif2_data_pins[] = {
2128 /* RX, TX */
2129 RCAR_GP_PIN(4, 16), RCAR_GP_PIN(4, 17),
2130};
2131static const unsigned int hscif2_data_mux[] = {
2132 HRX2_MARK, HTX2_MARK,
2133};
2134static const unsigned int hscif2_clk_pins[] = {
2135 /* SCK */
2136 RCAR_GP_PIN(4, 15),
2137};
2138static const unsigned int hscif2_clk_mux[] = {
2139 HSCK2_MARK,
2140};
2141static const unsigned int hscif2_ctrl_pins[] = {
2142 /* RTS, CTS */
2143 RCAR_GP_PIN(4, 14), RCAR_GP_PIN(4, 13),
2144};
2145static const unsigned int hscif2_ctrl_mux[] = {
2146 HRTS2_N_MARK, HCTS2_N_MARK,
2147};
2148static const unsigned int hscif2_data_b_pins[] = {
2149 /* RX, TX */
2150 RCAR_GP_PIN(1, 20), RCAR_GP_PIN(1, 22),
2151};
2152static const unsigned int hscif2_data_b_mux[] = {
2153 HRX2_B_MARK, HTX2_B_MARK,
2154};
2155static const unsigned int hscif2_ctrl_b_pins[] = {
2156 /* RTS, CTS */
2157 RCAR_GP_PIN(1, 23), RCAR_GP_PIN(1, 21),
2158};
2159static const unsigned int hscif2_ctrl_b_mux[] = {
2160 HRTS2_N_B_MARK, HCTS2_N_B_MARK,
2161};
2162static const unsigned int hscif2_data_c_pins[] = {
2163 /* RX, TX */
2164 RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 1),
2165};
2166static const unsigned int hscif2_data_c_mux[] = {
2167 HRX2_C_MARK, HTX2_C_MARK,
2168};
2169static const unsigned int hscif2_clk_c_pins[] = {
2170 /* SCK */
2171 RCAR_GP_PIN(5, 31),
2172};
2173static const unsigned int hscif2_clk_c_mux[] = {
2174 HSCK2_C_MARK,
2175};
2176static const unsigned int hscif2_data_d_pins[] = {
2177 /* RX, TX */
2178 RCAR_GP_PIN(1, 20), RCAR_GP_PIN(5, 31),
2179};
2180static const unsigned int hscif2_data_d_mux[] = {
2181 HRX2_B_MARK, HTX2_D_MARK,
2182};
1870/* - I2C0 ------------------------------------------------------------------- */ 2183/* - I2C0 ------------------------------------------------------------------- */
1871static const unsigned int i2c0_pins[] = { 2184static const unsigned int i2c0_pins[] = {
1872 /* SCL, SDA */ 2185 /* SCL, SDA */
@@ -3869,6 +4182,20 @@ static const struct sh_pfc_pin_group pinmux_groups[] = {
3869 SH_PFC_PIN_GROUP(audio_clk_b_b), 4182 SH_PFC_PIN_GROUP(audio_clk_b_b),
3870 SH_PFC_PIN_GROUP(audio_clk_c), 4183 SH_PFC_PIN_GROUP(audio_clk_c),
3871 SH_PFC_PIN_GROUP(audio_clkout), 4184 SH_PFC_PIN_GROUP(audio_clkout),
4185 SH_PFC_PIN_GROUP(can0_data),
4186 SH_PFC_PIN_GROUP(can0_data_b),
4187 SH_PFC_PIN_GROUP(can0_data_c),
4188 SH_PFC_PIN_GROUP(can0_data_d),
4189 SH_PFC_PIN_GROUP(can0_data_e),
4190 SH_PFC_PIN_GROUP(can0_data_f),
4191 SH_PFC_PIN_GROUP(can1_data),
4192 SH_PFC_PIN_GROUP(can1_data_b),
4193 SH_PFC_PIN_GROUP(can1_data_c),
4194 SH_PFC_PIN_GROUP(can1_data_d),
4195 SH_PFC_PIN_GROUP(can_clk),
4196 SH_PFC_PIN_GROUP(can_clk_b),
4197 SH_PFC_PIN_GROUP(can_clk_c),
4198 SH_PFC_PIN_GROUP(can_clk_d),
3872 SH_PFC_PIN_GROUP(du_rgb666), 4199 SH_PFC_PIN_GROUP(du_rgb666),
3873 SH_PFC_PIN_GROUP(du_rgb888), 4200 SH_PFC_PIN_GROUP(du_rgb888),
3874 SH_PFC_PIN_GROUP(du_clk_out_0), 4201 SH_PFC_PIN_GROUP(du_clk_out_0),
@@ -3885,6 +4212,32 @@ static const struct sh_pfc_pin_group pinmux_groups[] = {
3885 SH_PFC_PIN_GROUP(eth_magic), 4212 SH_PFC_PIN_GROUP(eth_magic),
3886 SH_PFC_PIN_GROUP(eth_mdio), 4213 SH_PFC_PIN_GROUP(eth_mdio),
3887 SH_PFC_PIN_GROUP(eth_rmii), 4214 SH_PFC_PIN_GROUP(eth_rmii),
4215 SH_PFC_PIN_GROUP(hscif0_data),
4216 SH_PFC_PIN_GROUP(hscif0_clk),
4217 SH_PFC_PIN_GROUP(hscif0_ctrl),
4218 SH_PFC_PIN_GROUP(hscif0_data_b),
4219 SH_PFC_PIN_GROUP(hscif0_ctrl_b),
4220 SH_PFC_PIN_GROUP(hscif0_data_c),
4221 SH_PFC_PIN_GROUP(hscif0_clk_c),
4222 SH_PFC_PIN_GROUP(hscif1_data),
4223 SH_PFC_PIN_GROUP(hscif1_clk),
4224 SH_PFC_PIN_GROUP(hscif1_ctrl),
4225 SH_PFC_PIN_GROUP(hscif1_data_b),
4226 SH_PFC_PIN_GROUP(hscif1_data_c),
4227 SH_PFC_PIN_GROUP(hscif1_clk_c),
4228 SH_PFC_PIN_GROUP(hscif1_ctrl_c),
4229 SH_PFC_PIN_GROUP(hscif1_data_d),
4230 SH_PFC_PIN_GROUP(hscif1_data_e),
4231 SH_PFC_PIN_GROUP(hscif1_clk_e),
4232 SH_PFC_PIN_GROUP(hscif1_ctrl_e),
4233 SH_PFC_PIN_GROUP(hscif2_data),
4234 SH_PFC_PIN_GROUP(hscif2_clk),
4235 SH_PFC_PIN_GROUP(hscif2_ctrl),
4236 SH_PFC_PIN_GROUP(hscif2_data_b),
4237 SH_PFC_PIN_GROUP(hscif2_ctrl_b),
4238 SH_PFC_PIN_GROUP(hscif2_data_c),
4239 SH_PFC_PIN_GROUP(hscif2_clk_c),
4240 SH_PFC_PIN_GROUP(hscif2_data_d),
3888 SH_PFC_PIN_GROUP(i2c0), 4241 SH_PFC_PIN_GROUP(i2c0),
3889 SH_PFC_PIN_GROUP(i2c0_b), 4242 SH_PFC_PIN_GROUP(i2c0_b),
3890 SH_PFC_PIN_GROUP(i2c0_c), 4243 SH_PFC_PIN_GROUP(i2c0_c),
@@ -4155,6 +4508,30 @@ static const char * const audio_clk_groups[] = {
4155 "audio_clkout", 4508 "audio_clkout",
4156}; 4509};
4157 4510
4511static const char * const can0_groups[] = {
4512 "can0_data",
4513 "can0_data_b",
4514 "can0_data_c",
4515 "can0_data_d",
4516 "can0_data_e",
4517 "can0_data_f",
4518 "can_clk",
4519 "can_clk_b",
4520 "can_clk_c",
4521 "can_clk_d",
4522};
4523
4524static const char * const can1_groups[] = {
4525 "can1_data",
4526 "can1_data_b",
4527 "can1_data_c",
4528 "can1_data_d",
4529 "can_clk",
4530 "can_clk_b",
4531 "can_clk_c",
4532 "can_clk_d",
4533};
4534
4158static const char * const du_groups[] = { 4535static const char * const du_groups[] = {
4159 "du_rgb666", 4536 "du_rgb666",
4160 "du_rgb888", 4537 "du_rgb888",
@@ -4183,6 +4560,41 @@ static const char * const eth_groups[] = {
4183 "eth_rmii", 4560 "eth_rmii",
4184}; 4561};
4185 4562
4563static const char * const hscif0_groups[] = {
4564 "hscif0_data",
4565 "hscif0_clk",
4566 "hscif0_ctrl",
4567 "hscif0_data_b",
4568 "hscif0_ctrl_b",
4569 "hscif0_data_c",
4570 "hscif0_clk_c",
4571};
4572
4573static const char * const hscif1_groups[] = {
4574 "hscif1_data",
4575 "hscif1_clk",
4576 "hscif1_ctrl",
4577 "hscif1_data_b",
4578 "hscif1_data_c",
4579 "hscif1_clk_c",
4580 "hscif1_ctrl_c",
4581 "hscif1_data_d",
4582 "hscif1_data_e",
4583 "hscif1_clk_e",
4584 "hscif1_ctrl_e",
4585};
4586
4587static const char * const hscif2_groups[] = {
4588 "hscif2_data",
4589 "hscif2_clk",
4590 "hscif2_ctrl",
4591 "hscif2_data_b",
4592 "hscif2_ctrl_b",
4593 "hscif2_data_c",
4594 "hscif2_clk_c",
4595 "hscif2_data_d",
4596};
4597
4186static const char * const i2c0_groups[] = { 4598static const char * const i2c0_groups[] = {
4187 "i2c0", 4599 "i2c0",
4188 "i2c0_b", 4600 "i2c0_b",
@@ -4543,10 +4955,15 @@ static const char * const vin2_groups[] = {
4543 4955
4544static const struct sh_pfc_function pinmux_functions[] = { 4956static const struct sh_pfc_function pinmux_functions[] = {
4545 SH_PFC_FUNCTION(audio_clk), 4957 SH_PFC_FUNCTION(audio_clk),
4958 SH_PFC_FUNCTION(can0),
4959 SH_PFC_FUNCTION(can1),
4546 SH_PFC_FUNCTION(du), 4960 SH_PFC_FUNCTION(du),
4547 SH_PFC_FUNCTION(du0), 4961 SH_PFC_FUNCTION(du0),
4548 SH_PFC_FUNCTION(du1), 4962 SH_PFC_FUNCTION(du1),
4549 SH_PFC_FUNCTION(eth), 4963 SH_PFC_FUNCTION(eth),
4964 SH_PFC_FUNCTION(hscif0),
4965 SH_PFC_FUNCTION(hscif1),
4966 SH_PFC_FUNCTION(hscif2),
4550 SH_PFC_FUNCTION(i2c0), 4967 SH_PFC_FUNCTION(i2c0),
4551 SH_PFC_FUNCTION(i2c1), 4968 SH_PFC_FUNCTION(i2c1),
4552 SH_PFC_FUNCTION(i2c2), 4969 SH_PFC_FUNCTION(i2c2),
diff --git a/drivers/pinctrl/sh-pfc/pfc-sh7372.c b/drivers/pinctrl/sh-pfc/pfc-sh7372.c
index d9158b3b2919..8211f66a2f68 100644
--- a/drivers/pinctrl/sh-pfc/pfc-sh7372.c
+++ b/drivers/pinctrl/sh-pfc/pfc-sh7372.c
@@ -2614,14 +2614,14 @@ static void sh7372_pinmux_set_bias(struct sh_pfc *pfc, unsigned int pin,
2614 iowrite8(value, addr); 2614 iowrite8(value, addr);
2615} 2615}
2616 2616
2617static const struct sh_pfc_soc_operations sh7372_pinmux_ops = { 2617static const struct sh_pfc_soc_operations sh7372_pfc_ops = {
2618 .get_bias = sh7372_pinmux_get_bias, 2618 .get_bias = sh7372_pinmux_get_bias,
2619 .set_bias = sh7372_pinmux_set_bias, 2619 .set_bias = sh7372_pinmux_set_bias,
2620}; 2620};
2621 2621
2622const struct sh_pfc_soc_info sh7372_pinmux_info = { 2622const struct sh_pfc_soc_info sh7372_pinmux_info = {
2623 .name = "sh7372_pfc", 2623 .name = "sh7372_pfc",
2624 .ops = &sh7372_pinmux_ops, 2624 .ops = &sh7372_pfc_ops,
2625 2625
2626 .input = { PINMUX_INPUT_BEGIN, PINMUX_INPUT_END }, 2626 .input = { PINMUX_INPUT_BEGIN, PINMUX_INPUT_END },
2627 .output = { PINMUX_OUTPUT_BEGIN, PINMUX_OUTPUT_END }, 2627 .output = { PINMUX_OUTPUT_BEGIN, PINMUX_OUTPUT_END },
diff --git a/drivers/pinctrl/sh-pfc/pfc-sh73a0.c b/drivers/pinctrl/sh-pfc/pfc-sh73a0.c
index ee370de4609a..d2efbfb776ac 100644
--- a/drivers/pinctrl/sh-pfc/pfc-sh73a0.c
+++ b/drivers/pinctrl/sh-pfc/pfc-sh73a0.c
@@ -3824,54 +3824,36 @@ static void sh73a0_pinmux_set_bias(struct sh_pfc *pfc, unsigned int pin,
3824 * SoC information 3824 * SoC information
3825 */ 3825 */
3826 3826
3827struct sh73a0_pinmux_data {
3828 struct regulator_dev *vccq_mc0;
3829};
3830
3831static int sh73a0_pinmux_soc_init(struct sh_pfc *pfc) 3827static int sh73a0_pinmux_soc_init(struct sh_pfc *pfc)
3832{ 3828{
3833 struct sh73a0_pinmux_data *data;
3834 struct regulator_config cfg = { }; 3829 struct regulator_config cfg = { };
3830 struct regulator_dev *vccq;
3835 int ret; 3831 int ret;
3836 3832
3837 data = devm_kzalloc(pfc->dev, sizeof(*data), GFP_KERNEL);
3838 if (data == NULL)
3839 return -ENOMEM;
3840
3841 cfg.dev = pfc->dev; 3833 cfg.dev = pfc->dev;
3842 cfg.init_data = &sh73a0_vccq_mc0_init_data; 3834 cfg.init_data = &sh73a0_vccq_mc0_init_data;
3843 cfg.driver_data = pfc; 3835 cfg.driver_data = pfc;
3844 3836
3845 data->vccq_mc0 = regulator_register(&sh73a0_vccq_mc0_desc, &cfg); 3837 vccq = devm_regulator_register(pfc->dev, &sh73a0_vccq_mc0_desc, &cfg);
3846 if (IS_ERR(data->vccq_mc0)) { 3838 if (IS_ERR(vccq)) {
3847 ret = PTR_ERR(data->vccq_mc0); 3839 ret = PTR_ERR(vccq);
3848 dev_err(pfc->dev, "Failed to register VCCQ MC0 regulator: %d\n", 3840 dev_err(pfc->dev, "Failed to register VCCQ MC0 regulator: %d\n",
3849 ret); 3841 ret);
3850 return ret; 3842 return ret;
3851 } 3843 }
3852 3844
3853 pfc->soc_data = data;
3854
3855 return 0; 3845 return 0;
3856} 3846}
3857 3847
3858static void sh73a0_pinmux_soc_exit(struct sh_pfc *pfc) 3848static const struct sh_pfc_soc_operations sh73a0_pfc_ops = {
3859{
3860 struct sh73a0_pinmux_data *data = pfc->soc_data;
3861
3862 regulator_unregister(data->vccq_mc0);
3863}
3864
3865static const struct sh_pfc_soc_operations sh73a0_pinmux_ops = {
3866 .init = sh73a0_pinmux_soc_init, 3849 .init = sh73a0_pinmux_soc_init,
3867 .exit = sh73a0_pinmux_soc_exit,
3868 .get_bias = sh73a0_pinmux_get_bias, 3850 .get_bias = sh73a0_pinmux_get_bias,
3869 .set_bias = sh73a0_pinmux_set_bias, 3851 .set_bias = sh73a0_pinmux_set_bias,
3870}; 3852};
3871 3853
3872const struct sh_pfc_soc_info sh73a0_pinmux_info = { 3854const struct sh_pfc_soc_info sh73a0_pinmux_info = {
3873 .name = "sh73a0_pfc", 3855 .name = "sh73a0_pfc",
3874 .ops = &sh73a0_pinmux_ops, 3856 .ops = &sh73a0_pfc_ops,
3875 3857
3876 .input = { PINMUX_INPUT_BEGIN, PINMUX_INPUT_END }, 3858 .input = { PINMUX_INPUT_BEGIN, PINMUX_INPUT_END },
3877 .output = { PINMUX_OUTPUT_BEGIN, PINMUX_OUTPUT_END }, 3859 .output = { PINMUX_OUTPUT_BEGIN, PINMUX_OUTPUT_END },
diff --git a/drivers/pinctrl/sh-pfc/pinctrl.c b/drivers/pinctrl/sh-pfc/pinctrl.c
index e758af95c209..910deaefa0ac 100644
--- a/drivers/pinctrl/sh-pfc/pinctrl.c
+++ b/drivers/pinctrl/sh-pfc/pinctrl.c
@@ -312,8 +312,8 @@ static int sh_pfc_get_function_groups(struct pinctrl_dev *pctldev,
312 return 0; 312 return 0;
313} 313}
314 314
315static int sh_pfc_func_enable(struct pinctrl_dev *pctldev, unsigned selector, 315static int sh_pfc_func_set_mux(struct pinctrl_dev *pctldev, unsigned selector,
316 unsigned group) 316 unsigned group)
317{ 317{
318 struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev); 318 struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev);
319 struct sh_pfc *pfc = pmx->pfc; 319 struct sh_pfc *pfc = pmx->pfc;
@@ -345,27 +345,6 @@ done:
345 return ret; 345 return ret;
346} 346}
347 347
348static void sh_pfc_func_disable(struct pinctrl_dev *pctldev, unsigned selector,
349 unsigned group)
350{
351 struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev);
352 struct sh_pfc *pfc = pmx->pfc;
353 const struct sh_pfc_pin_group *grp = &pfc->info->groups[group];
354 unsigned long flags;
355 unsigned int i;
356
357 spin_lock_irqsave(&pfc->lock, flags);
358
359 for (i = 0; i < grp->nr_pins; ++i) {
360 int idx = sh_pfc_get_pin_index(pfc, grp->pins[i]);
361 struct sh_pfc_pin_config *cfg = &pmx->configs[idx];
362
363 cfg->type = PINMUX_TYPE_NONE;
364 }
365
366 spin_unlock_irqrestore(&pfc->lock, flags);
367}
368
369static int sh_pfc_gpio_request_enable(struct pinctrl_dev *pctldev, 348static int sh_pfc_gpio_request_enable(struct pinctrl_dev *pctldev,
370 struct pinctrl_gpio_range *range, 349 struct pinctrl_gpio_range *range,
371 unsigned offset) 350 unsigned offset)
@@ -463,8 +442,7 @@ static const struct pinmux_ops sh_pfc_pinmux_ops = {
463 .get_functions_count = sh_pfc_get_functions_count, 442 .get_functions_count = sh_pfc_get_functions_count,
464 .get_function_name = sh_pfc_get_function_name, 443 .get_function_name = sh_pfc_get_function_name,
465 .get_function_groups = sh_pfc_get_function_groups, 444 .get_function_groups = sh_pfc_get_function_groups,
466 .enable = sh_pfc_func_enable, 445 .set_mux = sh_pfc_func_set_mux,
467 .disable = sh_pfc_func_disable,
468 .gpio_request_enable = sh_pfc_gpio_request_enable, 446 .gpio_request_enable = sh_pfc_gpio_request_enable,
469 .gpio_disable_free = sh_pfc_gpio_disable_free, 447 .gpio_disable_free = sh_pfc_gpio_disable_free,
470 .gpio_set_direction = sh_pfc_gpio_set_direction, 448 .gpio_set_direction = sh_pfc_gpio_set_direction,
diff --git a/drivers/pinctrl/sh-pfc/sh_pfc.h b/drivers/pinctrl/sh-pfc/sh_pfc.h
index d482c40b012a..5b7283182c1e 100644
--- a/drivers/pinctrl/sh-pfc/sh_pfc.h
+++ b/drivers/pinctrl/sh-pfc/sh_pfc.h
@@ -116,7 +116,6 @@ struct sh_pfc;
116 116
117struct sh_pfc_soc_operations { 117struct sh_pfc_soc_operations {
118 int (*init)(struct sh_pfc *pfc); 118 int (*init)(struct sh_pfc *pfc);
119 void (*exit)(struct sh_pfc *pfc);
120 unsigned int (*get_bias)(struct sh_pfc *pfc, unsigned int pin); 119 unsigned int (*get_bias)(struct sh_pfc *pfc, unsigned int pin);
121 void (*set_bias)(struct sh_pfc *pfc, unsigned int pin, 120 void (*set_bias)(struct sh_pfc *pfc, unsigned int pin,
122 unsigned int bias); 121 unsigned int bias);
diff --git a/drivers/pinctrl/sirf/pinctrl-atlas6.c b/drivers/pinctrl/sirf/pinctrl-atlas6.c
index c4dd3d5cf9c3..45f8391ddb34 100644
--- a/drivers/pinctrl/sirf/pinctrl-atlas6.c
+++ b/drivers/pinctrl/sirf/pinctrl-atlas6.c
@@ -134,8 +134,9 @@ static const struct sirfsoc_muxmask lcd_16bits_sirfsoc_muxmask[] = {
134 .mask = BIT(30) | BIT(31), 134 .mask = BIT(30) | BIT(31),
135 }, { 135 }, {
136 .group = 2, 136 .group = 2,
137 .mask = BIT(1) | BIT(6) | BIT(7) | BIT(8) | BIT(9) | BIT(10) | BIT(11) | 137 .mask = BIT(1) | BIT(6) | BIT(7) | BIT(8) | BIT(9) |
138 BIT(12) | BIT(13) | BIT(15) | BIT(16) | BIT(17) | BIT(18) | BIT(19) | 138 BIT(10) | BIT(11) | BIT(12) | BIT(13) | BIT(15) |
139 BIT(16) | BIT(17) | BIT(18) | BIT(19) |
139 BIT(20) | BIT(21) | BIT(22) | BIT(31), 140 BIT(20) | BIT(21) | BIT(22) | BIT(31),
140 }, 141 },
141}; 142};
@@ -148,14 +149,15 @@ static const struct sirfsoc_padmux lcd_16bits_padmux = {
148 .funcval = 0, 149 .funcval = 0,
149}; 150};
150 151
151static const unsigned lcd_16bits_pins[] = { 62, 63, 65, 70, 71, 72, 73, 74, 75, 76, 77, 79, 80, 81, 82, 83, 152static const unsigned lcd_16bits_pins[] = { 62, 63, 65, 70, 71, 72, 73, 74, 75,
152 84, 85, 86, 95 }; 153 76, 77, 79, 80, 81, 82, 83, 84, 85, 86, 95 };
153 154
154static const struct sirfsoc_muxmask lcd_18bits_muxmask[] = { 155static const struct sirfsoc_muxmask lcd_18bits_muxmask[] = {
155 { 156 {
156 .group = 2, 157 .group = 2,
157 .mask = BIT(1) | BIT(6) | BIT(7) | BIT(8) | BIT(9) | BIT(10) | BIT(11) | 158 .mask = BIT(1) | BIT(6) | BIT(7) | BIT(8) | BIT(9) |
158 BIT(12) | BIT(13) | BIT(15) | BIT(16) | BIT(17) | BIT(18) | BIT(19) | 159 BIT(10) | BIT(11) | BIT(12) | BIT(13) | BIT(15) |
160 BIT(16) | BIT(17) | BIT(18) | BIT(19) |
159 BIT(20) | BIT(21) | BIT(22) | BIT(31), 161 BIT(20) | BIT(21) | BIT(22) | BIT(31),
160 }, { 162 }, {
161 .group = 1, 163 .group = 1,
@@ -174,21 +176,23 @@ static const struct sirfsoc_padmux lcd_18bits_padmux = {
174 .funcval = 0, 176 .funcval = 0,
175}; 177};
176 178
177static const unsigned lcd_18bits_pins[] = { 16, 17, 62, 63, 65, 70, 71, 72, 73, 74, 75, 76, 77, 79, 80, 81, 82, 83, 179static const unsigned lcd_18bits_pins[] = { 16, 17, 62, 63, 65, 70, 71, 72, 73,
178 84, 85, 86, 95 }; 180 74, 75, 76, 77, 79, 80, 81, 82, 83, 84, 85, 86, 95 };
179 181
180static const struct sirfsoc_muxmask lcd_24bits_muxmask[] = { 182static const struct sirfsoc_muxmask lcd_24bits_muxmask[] = {
181 { 183 {
182 .group = 2, 184 .group = 2,
183 .mask = BIT(1) | BIT(6) | BIT(7) | BIT(8) | BIT(9) | BIT(10) | BIT(11) | 185 .mask = BIT(1) | BIT(6) | BIT(7) | BIT(8) | BIT(9) |
184 BIT(12) | BIT(13) | BIT(15) | BIT(16) | BIT(17) | BIT(18) | BIT(19) | 186 BIT(10) | BIT(11) | BIT(12) | BIT(13) | BIT(15) |
187 BIT(16) | BIT(17) | BIT(18) | BIT(19) |
185 BIT(20) | BIT(21) | BIT(22) | BIT(31), 188 BIT(20) | BIT(21) | BIT(22) | BIT(31),
186 }, { 189 }, {
187 .group = 1, 190 .group = 1,
188 .mask = BIT(30) | BIT(31), 191 .mask = BIT(30) | BIT(31),
189 }, { 192 }, {
190 .group = 0, 193 .group = 0,
191 .mask = BIT(16) | BIT(17) | BIT(18) | BIT(19) | BIT(20) | BIT(21) | BIT(22) | BIT(23), 194 .mask = BIT(16) | BIT(17) | BIT(18) | BIT(19) | BIT(20) |
195 BIT(21) | BIT(22) | BIT(23),
192 }, 196 },
193}; 197};
194 198
@@ -200,14 +204,16 @@ static const struct sirfsoc_padmux lcd_24bits_padmux = {
200 .funcval = 0, 204 .funcval = 0,
201}; 205};
202 206
203static const unsigned lcd_24bits_pins[] = { 16, 17, 18, 19, 20, 21, 22, 23, 62, 63, 65, 70, 71, 72, 73, 74, 75, 76, 77, 79, 207static const unsigned lcd_24bits_pins[] = { 16, 17, 18, 19, 20, 21, 22, 23, 62,
204 80, 81, 82, 83, 84, 85, 86, 95}; 208 63, 65, 70, 71, 72, 73, 74, 75, 76, 77, 79, 80, 81, 82, 83, 84,
209 85, 86, 95};
205 210
206static const struct sirfsoc_muxmask lcdrom_muxmask[] = { 211static const struct sirfsoc_muxmask lcdrom_muxmask[] = {
207 { 212 {
208 .group = 2, 213 .group = 2,
209 .mask = BIT(1) | BIT(6) | BIT(7) | BIT(8) | BIT(9) | BIT(10) | BIT(11) | 214 .mask = BIT(1) | BIT(6) | BIT(7) | BIT(8) | BIT(9) | BIT(10) |
210 BIT(12) | BIT(13) | BIT(15) | BIT(16) | BIT(17) | BIT(18) | BIT(19) | 215 BIT(11) | BIT(12) | BIT(13) | BIT(15) | BIT(16) |
216 BIT(17) | BIT(18) | BIT(19) |
211 BIT(20) | BIT(21) | BIT(22) | BIT(31), 217 BIT(20) | BIT(21) | BIT(22) | BIT(31),
212 }, { 218 }, {
213 .group = 1, 219 .group = 1,
@@ -226,8 +232,8 @@ static const struct sirfsoc_padmux lcdrom_padmux = {
226 .funcval = BIT(4), 232 .funcval = BIT(4),
227}; 233};
228 234
229static const unsigned lcdrom_pins[] = { 8, 62, 63, 65, 70, 71, 72, 73, 74, 75, 76, 77, 79, 80, 81, 82, 83, 235static const unsigned lcdrom_pins[] = { 8, 62, 63, 65, 70, 71, 72, 73, 74, 75,
230 84, 85, 86, 95}; 236 76, 77, 79, 80, 81, 82, 83, 84, 85, 86, 95};
231 237
232static const struct sirfsoc_muxmask uart0_muxmask[] = { 238static const struct sirfsoc_muxmask uart0_muxmask[] = {
233 { 239 {
@@ -371,11 +377,42 @@ static const struct sirfsoc_padmux cko1_padmux = {
371 377
372static const unsigned cko1_pins[] = { 42 }; 378static const unsigned cko1_pins[] = { 42 };
373 379
374static const struct sirfsoc_muxmask i2s_muxmask[] = { 380static const struct sirfsoc_muxmask i2s_mclk_muxmask[] = {
375 { 381 {
376 .group = 1, 382 .group = 1,
377 .mask = BIT(10), 383 .mask = BIT(10),
378 }, { 384 },
385};
386
387static const struct sirfsoc_padmux i2s_mclk_padmux = {
388 .muxmask_counts = ARRAY_SIZE(i2s_mclk_muxmask),
389 .muxmask = i2s_mclk_muxmask,
390 .ctrlreg = SIRFSOC_RSC_PIN_MUX,
391 .funcmask = BIT(3),
392 .funcval = BIT(3),
393};
394
395static const unsigned i2s_mclk_pins[] = { 42 };
396
397static const struct sirfsoc_muxmask i2s_ext_clk_input_muxmask[] = {
398 {
399 .group = 1,
400 .mask = BIT(19),
401 },
402};
403
404static const struct sirfsoc_padmux i2s_ext_clk_input_padmux = {
405 .muxmask_counts = ARRAY_SIZE(i2s_ext_clk_input_muxmask),
406 .muxmask = i2s_ext_clk_input_muxmask,
407 .ctrlreg = SIRFSOC_RSC_PIN_MUX,
408 .funcmask = BIT(2),
409 .funcval = BIT(2),
410};
411
412static const unsigned i2s_ext_clk_input_pins[] = { 51 };
413
414static const struct sirfsoc_muxmask i2s_muxmask[] = {
415 {
379 .group = 3, 416 .group = 3,
380 .mask = BIT(2) | BIT(3) | BIT(4) | BIT(5), 417 .mask = BIT(2) | BIT(3) | BIT(4) | BIT(5),
381 }, 418 },
@@ -385,17 +422,12 @@ static const struct sirfsoc_padmux i2s_padmux = {
385 .muxmask_counts = ARRAY_SIZE(i2s_muxmask), 422 .muxmask_counts = ARRAY_SIZE(i2s_muxmask),
386 .muxmask = i2s_muxmask, 423 .muxmask = i2s_muxmask,
387 .ctrlreg = SIRFSOC_RSC_PIN_MUX, 424 .ctrlreg = SIRFSOC_RSC_PIN_MUX,
388 .funcmask = BIT(3),
389 .funcval = BIT(3),
390}; 425};
391 426
392static const unsigned i2s_pins[] = { 42, 98, 99, 100, 101 }; 427static const unsigned i2s_pins[] = { 98, 99, 100, 101 };
393 428
394static const struct sirfsoc_muxmask i2s_no_din_muxmask[] = { 429static const struct sirfsoc_muxmask i2s_no_din_muxmask[] = {
395 { 430 {
396 .group = 1,
397 .mask = BIT(10),
398 }, {
399 .group = 3, 431 .group = 3,
400 .mask = BIT(2) | BIT(3) | BIT(4), 432 .mask = BIT(2) | BIT(3) | BIT(4),
401 }, 433 },
@@ -405,17 +437,12 @@ static const struct sirfsoc_padmux i2s_no_din_padmux = {
405 .muxmask_counts = ARRAY_SIZE(i2s_no_din_muxmask), 437 .muxmask_counts = ARRAY_SIZE(i2s_no_din_muxmask),
406 .muxmask = i2s_no_din_muxmask, 438 .muxmask = i2s_no_din_muxmask,
407 .ctrlreg = SIRFSOC_RSC_PIN_MUX, 439 .ctrlreg = SIRFSOC_RSC_PIN_MUX,
408 .funcmask = BIT(3),
409 .funcval = BIT(3),
410}; 440};
411 441
412static const unsigned i2s_no_din_pins[] = { 42, 98, 99, 100 }; 442static const unsigned i2s_no_din_pins[] = { 98, 99, 100 };
413 443
414static const struct sirfsoc_muxmask i2s_6chn_muxmask[] = { 444static const struct sirfsoc_muxmask i2s_6chn_muxmask[] = {
415 { 445 {
416 .group = 1,
417 .mask = BIT(10) | BIT(20) | BIT(23),
418 }, {
419 .group = 3, 446 .group = 3,
420 .mask = BIT(2) | BIT(3) | BIT(4) | BIT(5), 447 .mask = BIT(2) | BIT(3) | BIT(4) | BIT(5),
421 }, 448 },
@@ -425,11 +452,11 @@ static const struct sirfsoc_padmux i2s_6chn_padmux = {
425 .muxmask_counts = ARRAY_SIZE(i2s_6chn_muxmask), 452 .muxmask_counts = ARRAY_SIZE(i2s_6chn_muxmask),
426 .muxmask = i2s_6chn_muxmask, 453 .muxmask = i2s_6chn_muxmask,
427 .ctrlreg = SIRFSOC_RSC_PIN_MUX, 454 .ctrlreg = SIRFSOC_RSC_PIN_MUX,
428 .funcmask = BIT(1) | BIT(3) | BIT(9), 455 .funcmask = BIT(1) | BIT(9),
429 .funcval = BIT(1) | BIT(3) | BIT(9), 456 .funcval = BIT(1) | BIT(9),
430}; 457};
431 458
432static const unsigned i2s_6chn_pins[] = { 42, 52, 55, 98, 99, 100, 101 }; 459static const unsigned i2s_6chn_pins[] = { 52, 55, 98, 99, 100, 101 };
433 460
434static const struct sirfsoc_muxmask ac97_muxmask[] = { 461static const struct sirfsoc_muxmask ac97_muxmask[] = {
435 { 462 {
@@ -716,7 +743,8 @@ static const struct sirfsoc_padmux vip_padmux = {
716 .funcval = BIT(18), 743 .funcval = BIT(18),
717}; 744};
718 745
719static const unsigned vip_pins[] = { 36, 37, 38, 40, 41, 56, 57, 58, 59, 60, 61 }; 746static const unsigned vip_pins[] = { 36, 37, 38, 40, 41, 56, 57, 58, 59,
747 60, 61 };
720 748
721static const struct sirfsoc_muxmask vip_noupli_muxmask[] = { 749static const struct sirfsoc_muxmask vip_noupli_muxmask[] = {
722 { 750 {
@@ -737,7 +765,8 @@ static const struct sirfsoc_padmux vip_noupli_padmux = {
737 .funcval = BIT(15), 765 .funcval = BIT(15),
738}; 766};
739 767
740static const unsigned vip_noupli_pins[] = { 16, 17, 18, 19, 20, 21, 22, 23, 87, 88, 89 }; 768static const unsigned vip_noupli_pins[] = { 16, 17, 18, 19, 20, 21, 22, 23,
769 87, 88, 89 };
741 770
742static const struct sirfsoc_muxmask i2c0_muxmask[] = { 771static const struct sirfsoc_muxmask i2c0_muxmask[] = {
743 { 772 {
@@ -876,7 +905,8 @@ static const struct sirfsoc_padmux usb0_upli_drvbus_padmux = {
876 .funcval = 0, 905 .funcval = 0,
877}; 906};
878 907
879static const unsigned usb0_upli_drvbus_pins[] = { 36, 37, 38, 39, 40, 41, 56, 57, 58, 59, 60, 61 }; 908static const unsigned usb0_upli_drvbus_pins[] = { 36, 37, 38, 39, 40,
909 41, 56, 57, 58, 59, 60, 61 };
880 910
881static const struct sirfsoc_muxmask usb1_utmi_drvbus_muxmask[] = { 911static const struct sirfsoc_muxmask usb1_utmi_drvbus_muxmask[] = {
882 { 912 {
@@ -968,6 +998,8 @@ static const struct sirfsoc_pin_group sirfsoc_pin_groups[] = {
968 SIRFSOC_PIN_GROUP("usb1_dp_dngrp", usb1_dp_dn_pins), 998 SIRFSOC_PIN_GROUP("usb1_dp_dngrp", usb1_dp_dn_pins),
969 SIRFSOC_PIN_GROUP("uart1_route_io_usb1grp", uart1_route_io_usb1_pins), 999 SIRFSOC_PIN_GROUP("uart1_route_io_usb1grp", uart1_route_io_usb1_pins),
970 SIRFSOC_PIN_GROUP("pulse_countgrp", pulse_count_pins), 1000 SIRFSOC_PIN_GROUP("pulse_countgrp", pulse_count_pins),
1001 SIRFSOC_PIN_GROUP("i2smclkgrp", i2s_mclk_pins),
1002 SIRFSOC_PIN_GROUP("i2s_ext_clk_inputgrp", i2s_ext_clk_input_pins),
971 SIRFSOC_PIN_GROUP("i2sgrp", i2s_pins), 1003 SIRFSOC_PIN_GROUP("i2sgrp", i2s_pins),
972 SIRFSOC_PIN_GROUP("i2s_no_dingrp", i2s_no_din_pins), 1004 SIRFSOC_PIN_GROUP("i2s_no_dingrp", i2s_no_din_pins),
973 SIRFSOC_PIN_GROUP("i2s_6chngrp", i2s_6chn_pins), 1005 SIRFSOC_PIN_GROUP("i2s_6chngrp", i2s_6chn_pins),
@@ -1017,8 +1049,11 @@ static const char * const sdmmc2_nowpgrp[] = { "sdmmc2_nowpgrp" };
1017static const char * const usb0_upli_drvbusgrp[] = { "usb0_upli_drvbusgrp" }; 1049static const char * const usb0_upli_drvbusgrp[] = { "usb0_upli_drvbusgrp" };
1018static const char * const usb1_utmi_drvbusgrp[] = { "usb1_utmi_drvbusgrp" }; 1050static const char * const usb1_utmi_drvbusgrp[] = { "usb1_utmi_drvbusgrp" };
1019static const char * const usb1_dp_dngrp[] = { "usb1_dp_dngrp" }; 1051static const char * const usb1_dp_dngrp[] = { "usb1_dp_dngrp" };
1020static const char * const uart1_route_io_usb1grp[] = { "uart1_route_io_usb1grp" }; 1052static const char * const
1053 uart1_route_io_usb1grp[] = { "uart1_route_io_usb1grp" };
1021static const char * const pulse_countgrp[] = { "pulse_countgrp" }; 1054static const char * const pulse_countgrp[] = { "pulse_countgrp" };
1055static const char * const i2smclkgrp[] = { "i2smclkgrp" };
1056static const char * const i2s_ext_clk_inputgrp[] = { "i2s_ext_clk_inputgrp" };
1022static const char * const i2sgrp[] = { "i2sgrp" }; 1057static const char * const i2sgrp[] = { "i2sgrp" };
1023static const char * const i2s_no_dingrp[] = { "i2s_no_dingrp" }; 1058static const char * const i2s_no_dingrp[] = { "i2s_no_dingrp" };
1024static const char * const i2s_6chngrp[] = { "i2s_6chngrp" }; 1059static const char * const i2s_6chngrp[] = { "i2s_6chngrp" };
@@ -1038,7 +1073,8 @@ static const struct sirfsoc_pmx_func sirfsoc_pmx_functions[] = {
1038 uart0_nostreamctrl_padmux), 1073 uart0_nostreamctrl_padmux),
1039 SIRFSOC_PMX_FUNCTION("uart1", uart1grp, uart1_padmux), 1074 SIRFSOC_PMX_FUNCTION("uart1", uart1grp, uart1_padmux),
1040 SIRFSOC_PMX_FUNCTION("uart2", uart2grp, uart2_padmux), 1075 SIRFSOC_PMX_FUNCTION("uart2", uart2grp, uart2_padmux),
1041 SIRFSOC_PMX_FUNCTION("uart2_nostreamctrl", uart2_nostreamctrlgrp, uart2_nostreamctrl_padmux), 1076 SIRFSOC_PMX_FUNCTION("uart2_nostreamctrl",
1077 uart2_nostreamctrlgrp, uart2_nostreamctrl_padmux),
1042 SIRFSOC_PMX_FUNCTION("usp0", usp0grp, usp0_padmux), 1078 SIRFSOC_PMX_FUNCTION("usp0", usp0grp, usp0_padmux),
1043 SIRFSOC_PMX_FUNCTION("usp0_uart_nostreamctrl", 1079 SIRFSOC_PMX_FUNCTION("usp0_uart_nostreamctrl",
1044 usp0_uart_nostreamctrl_grp, 1080 usp0_uart_nostreamctrl_grp,
@@ -1068,12 +1104,19 @@ static const struct sirfsoc_pmx_func sirfsoc_pmx_functions[] = {
1068 SIRFSOC_PMX_FUNCTION("sdmmc2", sdmmc2grp, sdmmc2_padmux), 1104 SIRFSOC_PMX_FUNCTION("sdmmc2", sdmmc2grp, sdmmc2_padmux),
1069 SIRFSOC_PMX_FUNCTION("sdmmc3", sdmmc3grp, sdmmc3_padmux), 1105 SIRFSOC_PMX_FUNCTION("sdmmc3", sdmmc3grp, sdmmc3_padmux),
1070 SIRFSOC_PMX_FUNCTION("sdmmc5", sdmmc5grp, sdmmc5_padmux), 1106 SIRFSOC_PMX_FUNCTION("sdmmc5", sdmmc5grp, sdmmc5_padmux),
1071 SIRFSOC_PMX_FUNCTION("sdmmc2_nowp", sdmmc2_nowpgrp, sdmmc2_nowp_padmux), 1107 SIRFSOC_PMX_FUNCTION("sdmmc2_nowp",
1072 SIRFSOC_PMX_FUNCTION("usb0_upli_drvbus", usb0_upli_drvbusgrp, usb0_upli_drvbus_padmux), 1108 sdmmc2_nowpgrp, sdmmc2_nowp_padmux),
1073 SIRFSOC_PMX_FUNCTION("usb1_utmi_drvbus", usb1_utmi_drvbusgrp, usb1_utmi_drvbus_padmux), 1109 SIRFSOC_PMX_FUNCTION("usb0_upli_drvbus",
1110 usb0_upli_drvbusgrp, usb0_upli_drvbus_padmux),
1111 SIRFSOC_PMX_FUNCTION("usb1_utmi_drvbus",
1112 usb1_utmi_drvbusgrp, usb1_utmi_drvbus_padmux),
1074 SIRFSOC_PMX_FUNCTION("usb1_dp_dn", usb1_dp_dngrp, usb1_dp_dn_padmux), 1113 SIRFSOC_PMX_FUNCTION("usb1_dp_dn", usb1_dp_dngrp, usb1_dp_dn_padmux),
1075 SIRFSOC_PMX_FUNCTION("uart1_route_io_usb1", uart1_route_io_usb1grp, uart1_route_io_usb1_padmux), 1114 SIRFSOC_PMX_FUNCTION("uart1_route_io_usb1",
1115 uart1_route_io_usb1grp, uart1_route_io_usb1_padmux),
1076 SIRFSOC_PMX_FUNCTION("pulse_count", pulse_countgrp, pulse_count_padmux), 1116 SIRFSOC_PMX_FUNCTION("pulse_count", pulse_countgrp, pulse_count_padmux),
1117 SIRFSOC_PMX_FUNCTION("i2s_mclk", i2smclkgrp, i2s_mclk_padmux),
1118 SIRFSOC_PMX_FUNCTION("i2s_ext_clk_input", i2s_ext_clk_inputgrp,
1119 i2s_ext_clk_input_padmux),
1077 SIRFSOC_PMX_FUNCTION("i2s", i2sgrp, i2s_padmux), 1120 SIRFSOC_PMX_FUNCTION("i2s", i2sgrp, i2s_padmux),
1078 SIRFSOC_PMX_FUNCTION("i2s_no_din", i2s_no_dingrp, i2s_no_din_padmux), 1121 SIRFSOC_PMX_FUNCTION("i2s_no_din", i2s_no_dingrp, i2s_no_din_padmux),
1079 SIRFSOC_PMX_FUNCTION("i2s_6chn", i2s_6chngrp, i2s_6chn_padmux), 1122 SIRFSOC_PMX_FUNCTION("i2s_6chn", i2s_6chngrp, i2s_6chn_padmux),
diff --git a/drivers/pinctrl/sirf/pinctrl-prima2.c b/drivers/pinctrl/sirf/pinctrl-prima2.c
index 8aa76f0776d7..357678ee28e3 100644
--- a/drivers/pinctrl/sirf/pinctrl-prima2.c
+++ b/drivers/pinctrl/sirf/pinctrl-prima2.c
@@ -135,8 +135,9 @@ static const struct pinctrl_pin_desc sirfsoc_pads[] = {
135static const struct sirfsoc_muxmask lcd_16bits_sirfsoc_muxmask[] = { 135static const struct sirfsoc_muxmask lcd_16bits_sirfsoc_muxmask[] = {
136 { 136 {
137 .group = 3, 137 .group = 3,
138 .mask = BIT(0) | BIT(1) | BIT(2) | BIT(3) | BIT(4) | BIT(5) | BIT(6) | BIT(7) | BIT(8) | 138 .mask = BIT(0) | BIT(1) | BIT(2) | BIT(3) | BIT(4) | BIT(5) |
139 BIT(9) | BIT(10) | BIT(11) | BIT(12) | BIT(13) | BIT(14) | BIT(15) | BIT(16) | 139 BIT(6) | BIT(7) | BIT(8) | BIT(9) | BIT(10) | BIT(11) |
140 BIT(12) | BIT(13) | BIT(14) | BIT(15) | BIT(16) |
140 BIT(17) | BIT(18), 141 BIT(17) | BIT(18),
141 }, { 142 }, {
142 .group = 2, 143 .group = 2,
@@ -152,14 +153,15 @@ static const struct sirfsoc_padmux lcd_16bits_padmux = {
152 .funcval = 0, 153 .funcval = 0,
153}; 154};
154 155
155static const unsigned lcd_16bits_pins[] = { 95, 96, 97, 98, 99, 100, 101, 102, 103, 104, 156static const unsigned lcd_16bits_pins[] = { 95, 96, 97, 98, 99, 100, 101, 102,
156 105, 106, 107, 108, 109, 110, 111, 112, 113, 114 }; 157 103, 104, 105, 106, 107, 108, 109, 110, 111, 112, 113, 114 };
157 158
158static const struct sirfsoc_muxmask lcd_18bits_muxmask[] = { 159static const struct sirfsoc_muxmask lcd_18bits_muxmask[] = {
159 { 160 {
160 .group = 3, 161 .group = 3,
161 .mask = BIT(0) | BIT(1) | BIT(2) | BIT(3) | BIT(4) | BIT(5) | BIT(6) | BIT(7) | BIT(8) | 162 .mask = BIT(0) | BIT(1) | BIT(2) | BIT(3) | BIT(4) | BIT(5) |
162 BIT(9) | BIT(10) | BIT(11) | BIT(12) | BIT(13) | BIT(14) | BIT(15) | BIT(16) | 163 BIT(6) | BIT(7) | BIT(8) | BIT(9) | BIT(10) | BIT(11) |
164 BIT(12) | BIT(13) | BIT(14) | BIT(15) | BIT(16) |
163 BIT(17) | BIT(18), 165 BIT(17) | BIT(18),
164 }, { 166 }, {
165 .group = 2, 167 .group = 2,
@@ -178,21 +180,23 @@ static const struct sirfsoc_padmux lcd_18bits_padmux = {
178 .funcval = 0, 180 .funcval = 0,
179}; 181};
180 182
181static const unsigned lcd_18bits_pins[] = { 16, 17, 95, 96, 97, 98, 99, 100, 101, 102, 103, 104, 183static const unsigned lcd_18bits_pins[] = { 16, 17, 95, 96, 97, 98, 99, 100,
182 105, 106, 107, 108, 109, 110, 111, 112, 113, 114}; 184 101, 102, 103, 104, 105, 106, 107, 108, 109, 110, 111, 112, 113, 114};
183 185
184static const struct sirfsoc_muxmask lcd_24bits_muxmask[] = { 186static const struct sirfsoc_muxmask lcd_24bits_muxmask[] = {
185 { 187 {
186 .group = 3, 188 .group = 3,
187 .mask = BIT(0) | BIT(1) | BIT(2) | BIT(3) | BIT(4) | BIT(5) | BIT(6) | BIT(7) | BIT(8) | 189 .mask = BIT(0) | BIT(1) | BIT(2) | BIT(3) | BIT(4) | BIT(5) |
188 BIT(9) | BIT(10) | BIT(11) | BIT(12) | BIT(13) | BIT(14) | BIT(15) | BIT(16) | 190 BIT(6) | BIT(7) | BIT(8) | BIT(9) | BIT(10) | BIT(11) |
191 BIT(12) | BIT(13) | BIT(14) | BIT(15) | BIT(16) |
189 BIT(17) | BIT(18), 192 BIT(17) | BIT(18),
190 }, { 193 }, {
191 .group = 2, 194 .group = 2,
192 .mask = BIT(31), 195 .mask = BIT(31),
193 }, { 196 }, {
194 .group = 0, 197 .group = 0,
195 .mask = BIT(16) | BIT(17) | BIT(18) | BIT(19) | BIT(20) | BIT(21) | BIT(22) | BIT(23), 198 .mask = BIT(16) | BIT(17) | BIT(18) | BIT(19) | BIT(20) |
199 BIT(21) | BIT(22) | BIT(23),
196 }, 200 },
197}; 201};
198 202
@@ -204,14 +208,16 @@ static const struct sirfsoc_padmux lcd_24bits_padmux = {
204 .funcval = 0, 208 .funcval = 0,
205}; 209};
206 210
207static const unsigned lcd_24bits_pins[] = { 16, 17, 18, 19, 20, 21, 22, 23, 95, 96, 97, 98, 99, 100, 101, 102, 103, 104, 211static const unsigned lcd_24bits_pins[] = { 16, 17, 18, 19, 20, 21, 22, 23,
208 105, 106, 107, 108, 109, 110, 111, 112, 113, 114 }; 212 95, 96, 97, 98, 99, 100, 101, 102, 103, 104, 105, 106, 107, 108, 109,
213 110, 111, 112, 113, 114 };
209 214
210static const struct sirfsoc_muxmask lcdrom_muxmask[] = { 215static const struct sirfsoc_muxmask lcdrom_muxmask[] = {
211 { 216 {
212 .group = 3, 217 .group = 3,
213 .mask = BIT(0) | BIT(1) | BIT(2) | BIT(3) | BIT(4) | BIT(5) | BIT(6) | BIT(7) | BIT(8) | 218 .mask = BIT(0) | BIT(1) | BIT(2) | BIT(3) | BIT(4) | BIT(5) |
214 BIT(9) | BIT(10) | BIT(11) | BIT(12) | BIT(13) | BIT(14) | BIT(15) | BIT(16) | 219 BIT(6) | BIT(7) | BIT(8) | BIT(9) | BIT(10) | BIT(11) |
220 BIT(12) | BIT(13) | BIT(14) | BIT(15) | BIT(16) |
215 BIT(17) | BIT(18), 221 BIT(17) | BIT(18),
216 }, { 222 }, {
217 .group = 2, 223 .group = 2,
@@ -230,8 +236,8 @@ static const struct sirfsoc_padmux lcdrom_padmux = {
230 .funcval = BIT(4), 236 .funcval = BIT(4),
231}; 237};
232 238
233static const unsigned lcdrom_pins[] = { 23, 95, 96, 97, 98, 99, 100, 101, 102, 103, 104, 239static const unsigned lcdrom_pins[] = { 23, 95, 96, 97, 98, 99, 100, 101, 102,
234 105, 106, 107, 108, 109, 110, 111, 112, 113, 114 }; 240 103, 104, 105, 106, 107, 108, 109, 110, 111, 112, 113, 114 };
235 241
236static const struct sirfsoc_muxmask uart0_muxmask[] = { 242static const struct sirfsoc_muxmask uart0_muxmask[] = {
237 { 243 {
@@ -380,12 +386,44 @@ static const struct sirfsoc_padmux cko1_padmux = {
380 386
381static const unsigned cko1_pins[] = { 42 }; 387static const unsigned cko1_pins[] = { 42 };
382 388
389static const struct sirfsoc_muxmask i2s_mclk_muxmask[] = {
390 {
391 .group = 1,
392 .mask = BIT(10),
393 },
394};
395
396static const struct sirfsoc_padmux i2s_mclk_padmux = {
397 .muxmask_counts = ARRAY_SIZE(i2s_mclk_muxmask),
398 .muxmask = i2s_mclk_muxmask,
399 .ctrlreg = SIRFSOC_RSC_PIN_MUX,
400 .funcmask = BIT(3),
401 .funcval = BIT(3),
402};
403
404static const unsigned i2s_mclk_pins[] = { 42 };
405
406static const struct sirfsoc_muxmask i2s_ext_clk_input_muxmask[] = {
407 {
408 .group = 1,
409 .mask = BIT(19),
410 },
411};
412
413static const struct sirfsoc_padmux i2s_ext_clk_input_padmux = {
414 .muxmask_counts = ARRAY_SIZE(i2s_ext_clk_input_muxmask),
415 .muxmask = i2s_ext_clk_input_muxmask,
416 .ctrlreg = SIRFSOC_RSC_PIN_MUX,
417 .funcmask = BIT(2),
418 .funcval = BIT(2),
419};
420
421static const unsigned i2s_ext_clk_input_pins[] = { 51 };
422
383static const struct sirfsoc_muxmask i2s_muxmask[] = { 423static const struct sirfsoc_muxmask i2s_muxmask[] = {
384 { 424 {
385 .group = 1, 425 .group = 1,
386 .mask = 426 .mask = BIT(11) | BIT(12) | BIT(13) | BIT(14),
387 BIT(10) | BIT(11) | BIT(12) | BIT(13) | BIT(14) | BIT(19)
388 | BIT(23) | BIT(28),
389 }, 427 },
390}; 428};
391 429
@@ -393,11 +431,42 @@ static const struct sirfsoc_padmux i2s_padmux = {
393 .muxmask_counts = ARRAY_SIZE(i2s_muxmask), 431 .muxmask_counts = ARRAY_SIZE(i2s_muxmask),
394 .muxmask = i2s_muxmask, 432 .muxmask = i2s_muxmask,
395 .ctrlreg = SIRFSOC_RSC_PIN_MUX, 433 .ctrlreg = SIRFSOC_RSC_PIN_MUX,
396 .funcmask = BIT(3) | BIT(9),
397 .funcval = BIT(3),
398}; 434};
399 435
400static const unsigned i2s_pins[] = { 42, 43, 44, 45, 46, 51, 55, 60 }; 436static const unsigned i2s_pins[] = { 43, 44, 45, 46 };
437
438static const struct sirfsoc_muxmask i2s_no_din_muxmask[] = {
439 {
440 .group = 1,
441 .mask = BIT(11) | BIT(12) | BIT(14),
442 },
443};
444
445static const struct sirfsoc_padmux i2s_no_din_padmux = {
446 .muxmask_counts = ARRAY_SIZE(i2s_no_din_muxmask),
447 .muxmask = i2s_no_din_muxmask,
448 .ctrlreg = SIRFSOC_RSC_PIN_MUX,
449};
450
451static const unsigned i2s_no_din_pins[] = { 43, 44, 46 };
452
453static const struct sirfsoc_muxmask i2s_6chn_muxmask[] = {
454 {
455 .group = 1,
456 .mask = BIT(11) | BIT(12) | BIT(13) | BIT(14)
457 | BIT(23) | BIT(28),
458 },
459};
460
461static const struct sirfsoc_padmux i2s_6chn_padmux = {
462 .muxmask_counts = ARRAY_SIZE(i2s_6chn_muxmask),
463 .muxmask = i2s_6chn_muxmask,
464 .ctrlreg = SIRFSOC_RSC_PIN_MUX,
465 .funcmask = BIT(1) | BIT(9),
466 .funcval = BIT(1) | BIT(9),
467};
468
469static const unsigned i2s_6chn_pins[] = { 43, 44, 45, 46, 55, 60 };
401 470
402static const struct sirfsoc_muxmask ac97_muxmask[] = { 471static const struct sirfsoc_muxmask ac97_muxmask[] = {
403 { 472 {
@@ -685,7 +754,8 @@ static const struct sirfsoc_padmux vip_padmux = {
685 .funcval = 0, 754 .funcval = 0,
686}; 755};
687 756
688static const unsigned vip_pins[] = { 79, 80, 81, 82, 83, 84, 85, 86, 87, 88, 89 }; 757static const unsigned vip_pins[] = { 79, 80, 81, 82, 83, 84, 85, 86, 87,
758 88, 89 };
689 759
690static const struct sirfsoc_muxmask i2c0_muxmask[] = { 760static const struct sirfsoc_muxmask i2c0_muxmask[] = {
691 { 761 {
@@ -735,7 +805,8 @@ static const struct sirfsoc_padmux viprom_padmux = {
735 .funcval = BIT(0), 805 .funcval = BIT(0),
736}; 806};
737 807
738static const unsigned viprom_pins[] = { 12, 79, 80, 81, 82, 83, 84, 85, 86, 87, 88, 89 }; 808static const unsigned viprom_pins[] = { 12, 79, 80, 81, 82, 83, 84, 85, 86,
809 87, 88, 89 };
739 810
740static const struct sirfsoc_muxmask pwm0_muxmask[] = { 811static const struct sirfsoc_muxmask pwm0_muxmask[] = {
741 { 812 {
@@ -918,7 +989,11 @@ static const struct sirfsoc_pin_group sirfsoc_pin_groups[] = {
918 SIRFSOC_PIN_GROUP("usb1_dp_dngrp", usb1_dp_dn_pins), 989 SIRFSOC_PIN_GROUP("usb1_dp_dngrp", usb1_dp_dn_pins),
919 SIRFSOC_PIN_GROUP("uart1_route_io_usb1grp", uart1_route_io_usb1_pins), 990 SIRFSOC_PIN_GROUP("uart1_route_io_usb1grp", uart1_route_io_usb1_pins),
920 SIRFSOC_PIN_GROUP("pulse_countgrp", pulse_count_pins), 991 SIRFSOC_PIN_GROUP("pulse_countgrp", pulse_count_pins),
992 SIRFSOC_PIN_GROUP("i2smclkgrp", i2s_mclk_pins),
993 SIRFSOC_PIN_GROUP("i2s_ext_clk_inputgrp", i2s_ext_clk_input_pins),
921 SIRFSOC_PIN_GROUP("i2sgrp", i2s_pins), 994 SIRFSOC_PIN_GROUP("i2sgrp", i2s_pins),
995 SIRFSOC_PIN_GROUP("i2s_no_dingrp", i2s_no_din_pins),
996 SIRFSOC_PIN_GROUP("i2s_6chngrp", i2s_6chn_pins),
922 SIRFSOC_PIN_GROUP("ac97grp", ac97_pins), 997 SIRFSOC_PIN_GROUP("ac97grp", ac97_pins),
923 SIRFSOC_PIN_GROUP("nandgrp", nand_pins), 998 SIRFSOC_PIN_GROUP("nandgrp", nand_pins),
924 SIRFSOC_PIN_GROUP("spi0grp", spi0_pins), 999 SIRFSOC_PIN_GROUP("spi0grp", spi0_pins),
@@ -936,16 +1011,19 @@ static const char * const uart1grp[] = { "uart1grp" };
936static const char * const uart2grp[] = { "uart2grp" }; 1011static const char * const uart2grp[] = { "uart2grp" };
937static const char * const uart2_nostreamctrlgrp[] = { "uart2_nostreamctrlgrp" }; 1012static const char * const uart2_nostreamctrlgrp[] = { "uart2_nostreamctrlgrp" };
938static const char * const usp0grp[] = { "usp0grp" }; 1013static const char * const usp0grp[] = { "usp0grp" };
939static const char * const usp0_uart_nostreamctrl_grp[] = 1014static const char * const usp0_uart_nostreamctrl_grp[] = {
940 { "usp0_uart_nostreamctrl_grp" }; 1015 "usp0_uart_nostreamctrl_grp"
1016};
941static const char * const usp0_only_utfs_grp[] = { "usp0_only_utfs_grp" }; 1017static const char * const usp0_only_utfs_grp[] = { "usp0_only_utfs_grp" };
942static const char * const usp0_only_urfs_grp[] = { "usp0_only_urfs_grp" }; 1018static const char * const usp0_only_urfs_grp[] = { "usp0_only_urfs_grp" };
943static const char * const usp1grp[] = { "usp1grp" }; 1019static const char * const usp1grp[] = { "usp1grp" };
944static const char * const usp1_uart_nostreamctrl_grp[] = 1020static const char * const usp1_uart_nostreamctrl_grp[] = {
945 { "usp1_uart_nostreamctrl_grp" }; 1021 "usp1_uart_nostreamctrl_grp"
1022};
946static const char * const usp2grp[] = { "usp2grp" }; 1023static const char * const usp2grp[] = { "usp2grp" };
947static const char * const usp2_uart_nostreamctrl_grp[] = 1024static const char * const usp2_uart_nostreamctrl_grp[] = {
948 { "usp2_uart_nostreamctrl_grp" }; 1025 "usp2_uart_nostreamctrl_grp"
1026};
949static const char * const i2c0grp[] = { "i2c0grp" }; 1027static const char * const i2c0grp[] = { "i2c0grp" };
950static const char * const i2c1grp[] = { "i2c1grp" }; 1028static const char * const i2c1grp[] = { "i2c1grp" };
951static const char * const pwm0grp[] = { "pwm0grp" }; 1029static const char * const pwm0grp[] = { "pwm0grp" };
@@ -966,9 +1044,14 @@ static const char * const sdmmc5grp[] = { "sdmmc5grp" };
966static const char * const usb0_utmi_drvbusgrp[] = { "usb0_utmi_drvbusgrp" }; 1044static const char * const usb0_utmi_drvbusgrp[] = { "usb0_utmi_drvbusgrp" };
967static const char * const usb1_utmi_drvbusgrp[] = { "usb1_utmi_drvbusgrp" }; 1045static const char * const usb1_utmi_drvbusgrp[] = { "usb1_utmi_drvbusgrp" };
968static const char * const usb1_dp_dngrp[] = { "usb1_dp_dngrp" }; 1046static const char * const usb1_dp_dngrp[] = { "usb1_dp_dngrp" };
969static const char * const uart1_route_io_usb1grp[] = { "uart1_route_io_usb1grp" }; 1047static const char * const
1048 uart1_route_io_usb1grp[] = { "uart1_route_io_usb1grp" };
970static const char * const pulse_countgrp[] = { "pulse_countgrp" }; 1049static const char * const pulse_countgrp[] = { "pulse_countgrp" };
1050static const char * const i2smclkgrp[] = { "i2smclkgrp" };
1051static const char * const i2s_ext_clk_inputgrp[] = { "i2s_ext_clk_inputgrp" };
971static const char * const i2sgrp[] = { "i2sgrp" }; 1052static const char * const i2sgrp[] = { "i2sgrp" };
1053static const char * const i2s_no_dingrp[] = { "i2s_no_dingrp" };
1054static const char * const i2s_6chngrp[] = { "i2s_6chngrp" };
972static const char * const ac97grp[] = { "ac97grp" }; 1055static const char * const ac97grp[] = { "ac97grp" };
973static const char * const nandgrp[] = { "nandgrp" }; 1056static const char * const nandgrp[] = { "nandgrp" };
974static const char * const spi0grp[] = { "spi0grp" }; 1057static const char * const spi0grp[] = { "spi0grp" };
@@ -981,15 +1064,19 @@ static const struct sirfsoc_pmx_func sirfsoc_pmx_functions[] = {
981 SIRFSOC_PMX_FUNCTION("lcd_24bits", lcd_24bitsgrp, lcd_24bits_padmux), 1064 SIRFSOC_PMX_FUNCTION("lcd_24bits", lcd_24bitsgrp, lcd_24bits_padmux),
982 SIRFSOC_PMX_FUNCTION("lcdrom", lcdromgrp, lcdrom_padmux), 1065 SIRFSOC_PMX_FUNCTION("lcdrom", lcdromgrp, lcdrom_padmux),
983 SIRFSOC_PMX_FUNCTION("uart0", uart0grp, uart0_padmux), 1066 SIRFSOC_PMX_FUNCTION("uart0", uart0grp, uart0_padmux),
984 SIRFSOC_PMX_FUNCTION("uart0_nostreamctrl", uart0_nostreamctrlgrp, uart0_nostreamctrl_padmux), 1067 SIRFSOC_PMX_FUNCTION("uart0_nostreamctrl",
1068 uart0_nostreamctrlgrp, uart0_nostreamctrl_padmux),
985 SIRFSOC_PMX_FUNCTION("uart1", uart1grp, uart1_padmux), 1069 SIRFSOC_PMX_FUNCTION("uart1", uart1grp, uart1_padmux),
986 SIRFSOC_PMX_FUNCTION("uart2", uart2grp, uart2_padmux), 1070 SIRFSOC_PMX_FUNCTION("uart2", uart2grp, uart2_padmux),
987 SIRFSOC_PMX_FUNCTION("uart2_nostreamctrl", uart2_nostreamctrlgrp, uart2_nostreamctrl_padmux), 1071 SIRFSOC_PMX_FUNCTION("uart2_nostreamctrl",
1072 uart2_nostreamctrlgrp, uart2_nostreamctrl_padmux),
988 SIRFSOC_PMX_FUNCTION("usp0", usp0grp, usp0_padmux), 1073 SIRFSOC_PMX_FUNCTION("usp0", usp0grp, usp0_padmux),
989 SIRFSOC_PMX_FUNCTION("usp0_uart_nostreamctrl", 1074 SIRFSOC_PMX_FUNCTION("usp0_uart_nostreamctrl",
990 usp0_uart_nostreamctrl_grp, usp0_uart_nostreamctrl_padmux), 1075 usp0_uart_nostreamctrl_grp, usp0_uart_nostreamctrl_padmux),
991 SIRFSOC_PMX_FUNCTION("usp0_only_utfs", usp0_only_utfs_grp, usp0_only_utfs_padmux), 1076 SIRFSOC_PMX_FUNCTION("usp0_only_utfs",
992 SIRFSOC_PMX_FUNCTION("usp0_only_urfs", usp0_only_urfs_grp, usp0_only_urfs_padmux), 1077 usp0_only_utfs_grp, usp0_only_utfs_padmux),
1078 SIRFSOC_PMX_FUNCTION("usp0_only_urfs",
1079 usp0_only_urfs_grp, usp0_only_urfs_padmux),
993 SIRFSOC_PMX_FUNCTION("usp1", usp1grp, usp1_padmux), 1080 SIRFSOC_PMX_FUNCTION("usp1", usp1grp, usp1_padmux),
994 SIRFSOC_PMX_FUNCTION("usp1_uart_nostreamctrl", 1081 SIRFSOC_PMX_FUNCTION("usp1_uart_nostreamctrl",
995 usp1_uart_nostreamctrl_grp, usp1_uart_nostreamctrl_padmux), 1082 usp1_uart_nostreamctrl_grp, usp1_uart_nostreamctrl_padmux),
@@ -1013,12 +1100,20 @@ static const struct sirfsoc_pmx_func sirfsoc_pmx_functions[] = {
1013 SIRFSOC_PMX_FUNCTION("sdmmc3", sdmmc3grp, sdmmc3_padmux), 1100 SIRFSOC_PMX_FUNCTION("sdmmc3", sdmmc3grp, sdmmc3_padmux),
1014 SIRFSOC_PMX_FUNCTION("sdmmc4", sdmmc4grp, sdmmc4_padmux), 1101 SIRFSOC_PMX_FUNCTION("sdmmc4", sdmmc4grp, sdmmc4_padmux),
1015 SIRFSOC_PMX_FUNCTION("sdmmc5", sdmmc5grp, sdmmc5_padmux), 1102 SIRFSOC_PMX_FUNCTION("sdmmc5", sdmmc5grp, sdmmc5_padmux),
1016 SIRFSOC_PMX_FUNCTION("usb0_utmi_drvbus", usb0_utmi_drvbusgrp, usb0_utmi_drvbus_padmux), 1103 SIRFSOC_PMX_FUNCTION("usb0_utmi_drvbus",
1017 SIRFSOC_PMX_FUNCTION("usb1_utmi_drvbus", usb1_utmi_drvbusgrp, usb1_utmi_drvbus_padmux), 1104 usb0_utmi_drvbusgrp, usb0_utmi_drvbus_padmux),
1105 SIRFSOC_PMX_FUNCTION("usb1_utmi_drvbus",
1106 usb1_utmi_drvbusgrp, usb1_utmi_drvbus_padmux),
1018 SIRFSOC_PMX_FUNCTION("usb1_dp_dn", usb1_dp_dngrp, usb1_dp_dn_padmux), 1107 SIRFSOC_PMX_FUNCTION("usb1_dp_dn", usb1_dp_dngrp, usb1_dp_dn_padmux),
1019 SIRFSOC_PMX_FUNCTION("uart1_route_io_usb1", uart1_route_io_usb1grp, uart1_route_io_usb1_padmux), 1108 SIRFSOC_PMX_FUNCTION("uart1_route_io_usb1",
1109 uart1_route_io_usb1grp, uart1_route_io_usb1_padmux),
1020 SIRFSOC_PMX_FUNCTION("pulse_count", pulse_countgrp, pulse_count_padmux), 1110 SIRFSOC_PMX_FUNCTION("pulse_count", pulse_countgrp, pulse_count_padmux),
1111 SIRFSOC_PMX_FUNCTION("i2s_mclk", i2smclkgrp, i2s_mclk_padmux),
1112 SIRFSOC_PMX_FUNCTION("i2s_ext_clk_input", i2s_ext_clk_inputgrp,
1113 i2s_ext_clk_input_padmux),
1021 SIRFSOC_PMX_FUNCTION("i2s", i2sgrp, i2s_padmux), 1114 SIRFSOC_PMX_FUNCTION("i2s", i2sgrp, i2s_padmux),
1115 SIRFSOC_PMX_FUNCTION("i2s_no_din", i2s_no_dingrp, i2s_no_din_padmux),
1116 SIRFSOC_PMX_FUNCTION("i2s_6chn", i2s_6chngrp, i2s_6chn_padmux),
1022 SIRFSOC_PMX_FUNCTION("ac97", ac97grp, ac97_padmux), 1117 SIRFSOC_PMX_FUNCTION("ac97", ac97grp, ac97_padmux),
1023 SIRFSOC_PMX_FUNCTION("nand", nandgrp, nand_padmux), 1118 SIRFSOC_PMX_FUNCTION("nand", nandgrp, nand_padmux),
1024 SIRFSOC_PMX_FUNCTION("spi0", spi0grp, spi0_padmux), 1119 SIRFSOC_PMX_FUNCTION("spi0", spi0grp, spi0_padmux),
diff --git a/drivers/pinctrl/sirf/pinctrl-sirf.c b/drivers/pinctrl/sirf/pinctrl-sirf.c
index 014f5b1fee55..4c831fdfcc2f 100644
--- a/drivers/pinctrl/sirf/pinctrl-sirf.c
+++ b/drivers/pinctrl/sirf/pinctrl-sirf.c
@@ -58,17 +58,18 @@ static const char *sirfsoc_get_group_name(struct pinctrl_dev *pctldev,
58 return sirfsoc_pin_groups[selector].name; 58 return sirfsoc_pin_groups[selector].name;
59} 59}
60 60
61static int sirfsoc_get_group_pins(struct pinctrl_dev *pctldev, unsigned selector, 61static int sirfsoc_get_group_pins(struct pinctrl_dev *pctldev,
62 const unsigned **pins, 62 unsigned selector,
63 unsigned *num_pins) 63 const unsigned **pins,
64 unsigned *num_pins)
64{ 65{
65 *pins = sirfsoc_pin_groups[selector].pins; 66 *pins = sirfsoc_pin_groups[selector].pins;
66 *num_pins = sirfsoc_pin_groups[selector].num_pins; 67 *num_pins = sirfsoc_pin_groups[selector].num_pins;
67 return 0; 68 return 0;
68} 69}
69 70
70static void sirfsoc_pin_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s, 71static void sirfsoc_pin_dbg_show(struct pinctrl_dev *pctldev,
71 unsigned offset) 72 struct seq_file *s, unsigned offset)
72{ 73{
73 seq_printf(s, " " DRIVER_NAME); 74 seq_printf(s, " " DRIVER_NAME);
74} 75}
@@ -138,22 +139,25 @@ static struct pinctrl_ops sirfsoc_pctrl_ops = {
138static struct sirfsoc_pmx_func *sirfsoc_pmx_functions; 139static struct sirfsoc_pmx_func *sirfsoc_pmx_functions;
139static int sirfsoc_pmxfunc_cnt; 140static int sirfsoc_pmxfunc_cnt;
140 141
141static void sirfsoc_pinmux_endisable(struct sirfsoc_pmx *spmx, unsigned selector, 142static void sirfsoc_pinmux_endisable(struct sirfsoc_pmx *spmx,
142 bool enable) 143 unsigned selector, bool enable)
143{ 144{
144 int i; 145 int i;
145 const struct sirfsoc_padmux *mux = sirfsoc_pmx_functions[selector].padmux; 146 const struct sirfsoc_padmux *mux =
147 sirfsoc_pmx_functions[selector].padmux;
146 const struct sirfsoc_muxmask *mask = mux->muxmask; 148 const struct sirfsoc_muxmask *mask = mux->muxmask;
147 149
148 for (i = 0; i < mux->muxmask_counts; i++) { 150 for (i = 0; i < mux->muxmask_counts; i++) {
149 u32 muxval; 151 u32 muxval;
150 if (!spmx->is_marco) { 152 if (!spmx->is_marco) {
151 muxval = readl(spmx->gpio_virtbase + SIRFSOC_GPIO_PAD_EN(mask[i].group)); 153 muxval = readl(spmx->gpio_virtbase +
154 SIRFSOC_GPIO_PAD_EN(mask[i].group));
152 if (enable) 155 if (enable)
153 muxval = muxval & ~mask[i].mask; 156 muxval = muxval & ~mask[i].mask;
154 else 157 else
155 muxval = muxval | mask[i].mask; 158 muxval = muxval | mask[i].mask;
156 writel(muxval, spmx->gpio_virtbase + SIRFSOC_GPIO_PAD_EN(mask[i].group)); 159 writel(muxval, spmx->gpio_virtbase +
160 SIRFSOC_GPIO_PAD_EN(mask[i].group));
157 } else { 161 } else {
158 if (enable) 162 if (enable)
159 writel(mask[i].mask, spmx->gpio_virtbase + 163 writel(mask[i].mask, spmx->gpio_virtbase +
@@ -175,8 +179,9 @@ static void sirfsoc_pinmux_endisable(struct sirfsoc_pmx *spmx, unsigned selector
175 } 179 }
176} 180}
177 181
178static int sirfsoc_pinmux_enable(struct pinctrl_dev *pmxdev, unsigned selector, 182static int sirfsoc_pinmux_set_mux(struct pinctrl_dev *pmxdev,
179 unsigned group) 183 unsigned selector,
184 unsigned group)
180{ 185{
181 struct sirfsoc_pmx *spmx; 186 struct sirfsoc_pmx *spmx;
182 187
@@ -186,15 +191,6 @@ static int sirfsoc_pinmux_enable(struct pinctrl_dev *pmxdev, unsigned selector,
186 return 0; 191 return 0;
187} 192}
188 193
189static void sirfsoc_pinmux_disable(struct pinctrl_dev *pmxdev, unsigned selector,
190 unsigned group)
191{
192 struct sirfsoc_pmx *spmx;
193
194 spmx = pinctrl_dev_get_drvdata(pmxdev);
195 sirfsoc_pinmux_endisable(spmx, selector, false);
196}
197
198static int sirfsoc_pinmux_get_funcs_count(struct pinctrl_dev *pmxdev) 194static int sirfsoc_pinmux_get_funcs_count(struct pinctrl_dev *pmxdev)
199{ 195{
200 return sirfsoc_pmxfunc_cnt; 196 return sirfsoc_pmxfunc_cnt;
@@ -206,9 +202,10 @@ static const char *sirfsoc_pinmux_get_func_name(struct pinctrl_dev *pctldev,
206 return sirfsoc_pmx_functions[selector].name; 202 return sirfsoc_pmx_functions[selector].name;
207} 203}
208 204
209static int sirfsoc_pinmux_get_groups(struct pinctrl_dev *pctldev, unsigned selector, 205static int sirfsoc_pinmux_get_groups(struct pinctrl_dev *pctldev,
210 const char * const **groups, 206 unsigned selector,
211 unsigned * const num_groups) 207 const char * const **groups,
208 unsigned * const num_groups)
212{ 209{
213 *groups = sirfsoc_pmx_functions[selector].groups; 210 *groups = sirfsoc_pmx_functions[selector].groups;
214 *num_groups = sirfsoc_pmx_functions[selector].num_groups; 211 *num_groups = sirfsoc_pmx_functions[selector].num_groups;
@@ -227,9 +224,11 @@ static int sirfsoc_pinmux_request_gpio(struct pinctrl_dev *pmxdev,
227 spmx = pinctrl_dev_get_drvdata(pmxdev); 224 spmx = pinctrl_dev_get_drvdata(pmxdev);
228 225
229 if (!spmx->is_marco) { 226 if (!spmx->is_marco) {
230 muxval = readl(spmx->gpio_virtbase + SIRFSOC_GPIO_PAD_EN(group)); 227 muxval = readl(spmx->gpio_virtbase +
228 SIRFSOC_GPIO_PAD_EN(group));
231 muxval = muxval | (1 << (offset - range->pin_base)); 229 muxval = muxval | (1 << (offset - range->pin_base));
232 writel(muxval, spmx->gpio_virtbase + SIRFSOC_GPIO_PAD_EN(group)); 230 writel(muxval, spmx->gpio_virtbase +
231 SIRFSOC_GPIO_PAD_EN(group));
233 } else { 232 } else {
234 writel(1 << (offset - range->pin_base), spmx->gpio_virtbase + 233 writel(1 << (offset - range->pin_base), spmx->gpio_virtbase +
235 SIRFSOC_GPIO_PAD_EN(group)); 234 SIRFSOC_GPIO_PAD_EN(group));
@@ -239,8 +238,7 @@ static int sirfsoc_pinmux_request_gpio(struct pinctrl_dev *pmxdev,
239} 238}
240 239
241static struct pinmux_ops sirfsoc_pinmux_ops = { 240static struct pinmux_ops sirfsoc_pinmux_ops = {
242 .enable = sirfsoc_pinmux_enable, 241 .set_mux = sirfsoc_pinmux_set_mux,
243 .disable = sirfsoc_pinmux_disable,
244 .get_functions_count = sirfsoc_pinmux_get_funcs_count, 242 .get_functions_count = sirfsoc_pinmux_get_funcs_count,
245 .get_function_name = sirfsoc_pinmux_get_func_name, 243 .get_function_name = sirfsoc_pinmux_get_func_name,
246 .get_function_groups = sirfsoc_pinmux_get_groups, 244 .get_function_groups = sirfsoc_pinmux_get_groups,
@@ -528,24 +526,29 @@ static int sirfsoc_gpio_irq_type(struct irq_data *d, unsigned type)
528 case IRQ_TYPE_NONE: 526 case IRQ_TYPE_NONE:
529 break; 527 break;
530 case IRQ_TYPE_EDGE_RISING: 528 case IRQ_TYPE_EDGE_RISING:
531 val |= SIRFSOC_GPIO_CTL_INTR_HIGH_MASK | SIRFSOC_GPIO_CTL_INTR_TYPE_MASK; 529 val |= SIRFSOC_GPIO_CTL_INTR_HIGH_MASK |
530 SIRFSOC_GPIO_CTL_INTR_TYPE_MASK;
532 val &= ~SIRFSOC_GPIO_CTL_INTR_LOW_MASK; 531 val &= ~SIRFSOC_GPIO_CTL_INTR_LOW_MASK;
533 break; 532 break;
534 case IRQ_TYPE_EDGE_FALLING: 533 case IRQ_TYPE_EDGE_FALLING:
535 val &= ~SIRFSOC_GPIO_CTL_INTR_HIGH_MASK; 534 val &= ~SIRFSOC_GPIO_CTL_INTR_HIGH_MASK;
536 val |= SIRFSOC_GPIO_CTL_INTR_LOW_MASK | SIRFSOC_GPIO_CTL_INTR_TYPE_MASK; 535 val |= SIRFSOC_GPIO_CTL_INTR_LOW_MASK |
536 SIRFSOC_GPIO_CTL_INTR_TYPE_MASK;
537 break; 537 break;
538 case IRQ_TYPE_EDGE_BOTH: 538 case IRQ_TYPE_EDGE_BOTH:
539 val |= SIRFSOC_GPIO_CTL_INTR_HIGH_MASK | SIRFSOC_GPIO_CTL_INTR_LOW_MASK | 539 val |= SIRFSOC_GPIO_CTL_INTR_HIGH_MASK |
540 SIRFSOC_GPIO_CTL_INTR_TYPE_MASK; 540 SIRFSOC_GPIO_CTL_INTR_LOW_MASK |
541 SIRFSOC_GPIO_CTL_INTR_TYPE_MASK;
541 break; 542 break;
542 case IRQ_TYPE_LEVEL_LOW: 543 case IRQ_TYPE_LEVEL_LOW:
543 val &= ~(SIRFSOC_GPIO_CTL_INTR_HIGH_MASK | SIRFSOC_GPIO_CTL_INTR_TYPE_MASK); 544 val &= ~(SIRFSOC_GPIO_CTL_INTR_HIGH_MASK |
545 SIRFSOC_GPIO_CTL_INTR_TYPE_MASK);
544 val |= SIRFSOC_GPIO_CTL_INTR_LOW_MASK; 546 val |= SIRFSOC_GPIO_CTL_INTR_LOW_MASK;
545 break; 547 break;
546 case IRQ_TYPE_LEVEL_HIGH: 548 case IRQ_TYPE_LEVEL_HIGH:
547 val |= SIRFSOC_GPIO_CTL_INTR_HIGH_MASK; 549 val |= SIRFSOC_GPIO_CTL_INTR_HIGH_MASK;
548 val &= ~(SIRFSOC_GPIO_CTL_INTR_LOW_MASK | SIRFSOC_GPIO_CTL_INTR_TYPE_MASK); 550 val &= ~(SIRFSOC_GPIO_CTL_INTR_LOW_MASK |
551 SIRFSOC_GPIO_CTL_INTR_TYPE_MASK);
549 break; 552 break;
550 } 553 }
551 554
@@ -704,7 +707,8 @@ static inline void sirfsoc_gpio_set_output(struct sirfsoc_gpio_chip *sgpio,
704 spin_unlock_irqrestore(&bank->lock, flags); 707 spin_unlock_irqrestore(&bank->lock, flags);
705} 708}
706 709
707static int sirfsoc_gpio_direction_output(struct gpio_chip *chip, unsigned gpio, int value) 710static int sirfsoc_gpio_direction_output(struct gpio_chip *chip,
711 unsigned gpio, int value)
708{ 712{
709 struct sirfsoc_gpio_chip *sgpio = to_sirfsoc_gpio(chip); 713 struct sirfsoc_gpio_chip *sgpio = to_sirfsoc_gpio(chip);
710 struct sirfsoc_gpio_bank *bank = sirfsoc_gpio_to_bank(sgpio, gpio); 714 struct sirfsoc_gpio_bank *bank = sirfsoc_gpio_to_bank(sgpio, gpio);
@@ -849,7 +853,7 @@ static int sirfsoc_gpio_probe(struct device_node *np)
849 if (err) { 853 if (err) {
850 dev_err(&pdev->dev, 854 dev_err(&pdev->dev,
851 "could not connect irqchip to gpiochip\n"); 855 "could not connect irqchip to gpiochip\n");
852 goto out; 856 goto out_banks;
853 } 857 }
854 858
855 for (i = 0; i < SIRFSOC_GPIO_NO_OF_BANKS; i++) { 859 for (i = 0; i < SIRFSOC_GPIO_NO_OF_BANKS; i++) {
@@ -887,8 +891,7 @@ static int sirfsoc_gpio_probe(struct device_node *np)
887 891
888out_no_range: 892out_no_range:
889out_banks: 893out_banks:
890 if (gpiochip_remove(&sgpio->chip.gc)) 894 gpiochip_remove(&sgpio->chip.gc);
891 dev_err(&pdev->dev, "could not remove gpio chip\n");
892out: 895out:
893 iounmap(regs); 896 iounmap(regs);
894 return err; 897 return err;
@@ -908,8 +911,8 @@ static int __init sirfsoc_gpio_init(void)
908} 911}
909subsys_initcall(sirfsoc_gpio_init); 912subsys_initcall(sirfsoc_gpio_init);
910 913
911MODULE_AUTHOR("Rongjun Ying <rongjun.ying@csr.com>, " 914MODULE_AUTHOR("Rongjun Ying <rongjun.ying@csr.com>");
912 "Yuping Luo <yuping.luo@csr.com>, " 915MODULE_AUTHOR("Yuping Luo <yuping.luo@csr.com>");
913 "Barry Song <baohua.song@csr.com>"); 916MODULE_AUTHOR("Barry Song <baohua.song@csr.com>");
914MODULE_DESCRIPTION("SIRFSOC pin control driver"); 917MODULE_DESCRIPTION("SIRFSOC pin control driver");
915MODULE_LICENSE("GPL"); 918MODULE_LICENSE("GPL");
diff --git a/drivers/pinctrl/spear/Kconfig b/drivers/pinctrl/spear/Kconfig
index 04d93e602674..9ef18eb958e1 100644
--- a/drivers/pinctrl/spear/Kconfig
+++ b/drivers/pinctrl/spear/Kconfig
@@ -48,6 +48,7 @@ config PINCTRL_SPEAR1340
48config PINCTRL_SPEAR_PLGPIO 48config PINCTRL_SPEAR_PLGPIO
49 bool "SPEAr SoC PLGPIO Controller" 49 bool "SPEAr SoC PLGPIO Controller"
50 depends on GPIOLIB && PINCTRL_SPEAR 50 depends on GPIOLIB && PINCTRL_SPEAR
51 select GPIOLIB_IRQCHIP
51 help 52 help
52 Say yes here to support PLGPIO controller on ST Microelectronics SPEAr 53 Say yes here to support PLGPIO controller on ST Microelectronics SPEAr
53 SoCs. 54 SoCs.
diff --git a/drivers/pinctrl/spear/pinctrl-plgpio.c b/drivers/pinctrl/spear/pinctrl-plgpio.c
index ecfc6aacf270..ce5f22c4151d 100644
--- a/drivers/pinctrl/spear/pinctrl-plgpio.c
+++ b/drivers/pinctrl/spear/pinctrl-plgpio.c
@@ -11,12 +11,11 @@
11 11
12#include <linux/clk.h> 12#include <linux/clk.h>
13#include <linux/err.h> 13#include <linux/err.h>
14#include <linux/gpio.h> 14#include <linux/gpio/driver.h>
15#include <linux/io.h> 15#include <linux/io.h>
16#include <linux/irq.h>
17#include <linux/irqdomain.h>
18#include <linux/irqchip/chained_irq.h>
19#include <linux/module.h> 16#include <linux/module.h>
17#include <linux/of.h>
18#include <linux/of_platform.h>
20#include <linux/pinctrl/consumer.h> 19#include <linux/pinctrl/consumer.h>
21#include <linux/platform_device.h> 20#include <linux/platform_device.h>
22#include <linux/pm.h> 21#include <linux/pm.h>
@@ -54,7 +53,6 @@ struct plgpio_regs {
54 * 53 *
55 * lock: lock for guarding gpio registers 54 * lock: lock for guarding gpio registers
56 * base: base address of plgpio block 55 * base: base address of plgpio block
57 * irq_base: irq number of plgpio0
58 * chip: gpio framework specific chip information structure 56 * chip: gpio framework specific chip information structure
59 * p2o: function ptr for pin to offset conversion. This is required only for 57 * p2o: function ptr for pin to offset conversion. This is required only for
60 * machines where mapping b/w pin and offset is not 1-to-1. 58 * machines where mapping b/w pin and offset is not 1-to-1.
@@ -68,8 +66,6 @@ struct plgpio {
68 spinlock_t lock; 66 spinlock_t lock;
69 void __iomem *base; 67 void __iomem *base;
70 struct clk *clk; 68 struct clk *clk;
71 unsigned irq_base;
72 struct irq_domain *irq_domain;
73 struct gpio_chip chip; 69 struct gpio_chip chip;
74 int (*p2o)(int pin); /* pin_to_offset */ 70 int (*p2o)(int pin); /* pin_to_offset */
75 int (*o2p)(int offset); /* offset_to_pin */ 71 int (*o2p)(int offset); /* offset_to_pin */
@@ -280,21 +276,12 @@ disable_clk:
280 pinctrl_free_gpio(gpio); 276 pinctrl_free_gpio(gpio);
281} 277}
282 278
283static int plgpio_to_irq(struct gpio_chip *chip, unsigned offset)
284{
285 struct plgpio *plgpio = container_of(chip, struct plgpio, chip);
286
287 if (IS_ERR_VALUE(plgpio->irq_base))
288 return -EINVAL;
289
290 return irq_find_mapping(plgpio->irq_domain, offset);
291}
292
293/* PLGPIO IRQ */ 279/* PLGPIO IRQ */
294static void plgpio_irq_disable(struct irq_data *d) 280static void plgpio_irq_disable(struct irq_data *d)
295{ 281{
296 struct plgpio *plgpio = irq_data_get_irq_chip_data(d); 282 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
297 int offset = d->irq - plgpio->irq_base; 283 struct plgpio *plgpio = container_of(gc, struct plgpio, chip);
284 int offset = d->hwirq;
298 unsigned long flags; 285 unsigned long flags;
299 286
300 /* get correct offset for "offset" pin */ 287 /* get correct offset for "offset" pin */
@@ -311,8 +298,9 @@ static void plgpio_irq_disable(struct irq_data *d)
311 298
312static void plgpio_irq_enable(struct irq_data *d) 299static void plgpio_irq_enable(struct irq_data *d)
313{ 300{
314 struct plgpio *plgpio = irq_data_get_irq_chip_data(d); 301 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
315 int offset = d->irq - plgpio->irq_base; 302 struct plgpio *plgpio = container_of(gc, struct plgpio, chip);
303 int offset = d->hwirq;
316 unsigned long flags; 304 unsigned long flags;
317 305
318 /* get correct offset for "offset" pin */ 306 /* get correct offset for "offset" pin */
@@ -329,8 +317,9 @@ static void plgpio_irq_enable(struct irq_data *d)
329 317
330static int plgpio_irq_set_type(struct irq_data *d, unsigned trigger) 318static int plgpio_irq_set_type(struct irq_data *d, unsigned trigger)
331{ 319{
332 struct plgpio *plgpio = irq_data_get_irq_chip_data(d); 320 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
333 int offset = d->irq - plgpio->irq_base; 321 struct plgpio *plgpio = container_of(gc, struct plgpio, chip);
322 int offset = d->hwirq;
334 void __iomem *reg_off; 323 void __iomem *reg_off;
335 unsigned int supported_type = 0, val; 324 unsigned int supported_type = 0, val;
336 325
@@ -369,7 +358,8 @@ static struct irq_chip plgpio_irqchip = {
369 358
370static void plgpio_irq_handler(unsigned irq, struct irq_desc *desc) 359static void plgpio_irq_handler(unsigned irq, struct irq_desc *desc)
371{ 360{
372 struct plgpio *plgpio = irq_get_handler_data(irq); 361 struct gpio_chip *gc = irq_desc_get_handler_data(desc);
362 struct plgpio *plgpio = container_of(gc, struct plgpio, chip);
373 struct irq_chip *irqchip = irq_desc_get_chip(desc); 363 struct irq_chip *irqchip = irq_desc_get_chip(desc);
374 int regs_count, count, pin, offset, i = 0; 364 int regs_count, count, pin, offset, i = 0;
375 unsigned long pending; 365 unsigned long pending;
@@ -410,7 +400,8 @@ static void plgpio_irq_handler(unsigned irq, struct irq_desc *desc)
410 400
411 /* get correct irq line number */ 401 /* get correct irq line number */
412 pin = i * MAX_GPIO_PER_REG + pin; 402 pin = i * MAX_GPIO_PER_REG + pin;
413 generic_handle_irq(plgpio_to_irq(&plgpio->chip, pin)); 403 generic_handle_irq(
404 irq_find_mapping(gc->irqdomain, pin));
414 } 405 }
415 } 406 }
416 chained_irq_exit(irqchip, desc); 407 chained_irq_exit(irqchip, desc);
@@ -523,10 +514,9 @@ end:
523} 514}
524static int plgpio_probe(struct platform_device *pdev) 515static int plgpio_probe(struct platform_device *pdev)
525{ 516{
526 struct device_node *np = pdev->dev.of_node;
527 struct plgpio *plgpio; 517 struct plgpio *plgpio;
528 struct resource *res; 518 struct resource *res;
529 int ret, irq, i; 519 int ret, irq;
530 520
531 plgpio = devm_kzalloc(&pdev->dev, sizeof(*plgpio), GFP_KERNEL); 521 plgpio = devm_kzalloc(&pdev->dev, sizeof(*plgpio), GFP_KERNEL);
532 if (!plgpio) { 522 if (!plgpio) {
@@ -563,7 +553,6 @@ static int plgpio_probe(struct platform_device *pdev)
563 platform_set_drvdata(pdev, plgpio); 553 platform_set_drvdata(pdev, plgpio);
564 spin_lock_init(&plgpio->lock); 554 spin_lock_init(&plgpio->lock);
565 555
566 plgpio->irq_base = -1;
567 plgpio->chip.base = -1; 556 plgpio->chip.base = -1;
568 plgpio->chip.request = plgpio_request; 557 plgpio->chip.request = plgpio_request;
569 plgpio->chip.free = plgpio_free; 558 plgpio->chip.free = plgpio_free;
@@ -571,10 +560,10 @@ static int plgpio_probe(struct platform_device *pdev)
571 plgpio->chip.direction_output = plgpio_direction_output; 560 plgpio->chip.direction_output = plgpio_direction_output;
572 plgpio->chip.get = plgpio_get_value; 561 plgpio->chip.get = plgpio_get_value;
573 plgpio->chip.set = plgpio_set_value; 562 plgpio->chip.set = plgpio_set_value;
574 plgpio->chip.to_irq = plgpio_to_irq;
575 plgpio->chip.label = dev_name(&pdev->dev); 563 plgpio->chip.label = dev_name(&pdev->dev);
576 plgpio->chip.dev = &pdev->dev; 564 plgpio->chip.dev = &pdev->dev;
577 plgpio->chip.owner = THIS_MODULE; 565 plgpio->chip.owner = THIS_MODULE;
566 plgpio->chip.of_node = pdev->dev.of_node;
578 567
579 if (!IS_ERR(plgpio->clk)) { 568 if (!IS_ERR(plgpio->clk)) {
580 ret = clk_prepare(plgpio->clk); 569 ret = clk_prepare(plgpio->clk);
@@ -592,43 +581,32 @@ static int plgpio_probe(struct platform_device *pdev)
592 581
593 irq = platform_get_irq(pdev, 0); 582 irq = platform_get_irq(pdev, 0);
594 if (irq < 0) { 583 if (irq < 0) {
595 dev_info(&pdev->dev, "irqs not supported\n"); 584 dev_info(&pdev->dev, "PLGPIO registered without IRQs\n");
596 return 0;
597 }
598
599 plgpio->irq_base = irq_alloc_descs(-1, 0, plgpio->chip.ngpio, 0);
600 if (IS_ERR_VALUE(plgpio->irq_base)) {
601 /* we would not support irq for gpio */
602 dev_warn(&pdev->dev, "couldn't allocate irq base\n");
603 return 0; 585 return 0;
604 } 586 }
605 587
606 plgpio->irq_domain = irq_domain_add_legacy(np, plgpio->chip.ngpio, 588 ret = gpiochip_irqchip_add(&plgpio->chip,
607 plgpio->irq_base, 0, &irq_domain_simple_ops, NULL); 589 &plgpio_irqchip,
608 if (WARN_ON(!plgpio->irq_domain)) { 590 0,
609 dev_err(&pdev->dev, "irq domain init failed\n"); 591 handle_simple_irq,
610 irq_free_descs(plgpio->irq_base, plgpio->chip.ngpio); 592 IRQ_TYPE_NONE);
611 ret = -ENXIO; 593 if (ret) {
594 dev_err(&pdev->dev, "failed to add irqchip to gpiochip\n");
612 goto remove_gpiochip; 595 goto remove_gpiochip;
613 } 596 }
614 597
615 irq_set_chained_handler(irq, plgpio_irq_handler); 598 gpiochip_set_chained_irqchip(&plgpio->chip,
616 for (i = 0; i < plgpio->chip.ngpio; i++) { 599 &plgpio_irqchip,
617 irq_set_chip_and_handler(i + plgpio->irq_base, &plgpio_irqchip, 600 irq,
618 handle_simple_irq); 601 plgpio_irq_handler);
619 set_irq_flags(i + plgpio->irq_base, IRQF_VALID);
620 irq_set_chip_data(i + plgpio->irq_base, plgpio);
621 }
622 602
623 irq_set_handler_data(irq, plgpio);
624 dev_info(&pdev->dev, "PLGPIO registered with IRQs\n"); 603 dev_info(&pdev->dev, "PLGPIO registered with IRQs\n");
625 604
626 return 0; 605 return 0;
627 606
628remove_gpiochip: 607remove_gpiochip:
629 dev_info(&pdev->dev, "Remove gpiochip\n"); 608 dev_info(&pdev->dev, "Remove gpiochip\n");
630 if (gpiochip_remove(&plgpio->chip)) 609 gpiochip_remove(&plgpio->chip);
631 dev_err(&pdev->dev, "unable to remove gpiochip\n");
632unprepare_clk: 610unprepare_clk:
633 if (!IS_ERR(plgpio->clk)) 611 if (!IS_ERR(plgpio->clk))
634 clk_unprepare(plgpio->clk); 612 clk_unprepare(plgpio->clk);
diff --git a/drivers/pinctrl/spear/pinctrl-spear.c b/drivers/pinctrl/spear/pinctrl-spear.c
index 58bf6867aa17..abdb05ac43dc 100644
--- a/drivers/pinctrl/spear/pinctrl-spear.c
+++ b/drivers/pinctrl/spear/pinctrl-spear.c
@@ -268,18 +268,12 @@ static int spear_pinctrl_endisable(struct pinctrl_dev *pctldev,
268 return 0; 268 return 0;
269} 269}
270 270
271static int spear_pinctrl_enable(struct pinctrl_dev *pctldev, unsigned function, 271static int spear_pinctrl_set_mux(struct pinctrl_dev *pctldev, unsigned function,
272 unsigned group) 272 unsigned group)
273{ 273{
274 return spear_pinctrl_endisable(pctldev, function, group, true); 274 return spear_pinctrl_endisable(pctldev, function, group, true);
275} 275}
276 276
277static void spear_pinctrl_disable(struct pinctrl_dev *pctldev,
278 unsigned function, unsigned group)
279{
280 spear_pinctrl_endisable(pctldev, function, group, false);
281}
282
283/* gpio with pinmux */ 277/* gpio with pinmux */
284static struct spear_gpio_pingroup *get_gpio_pingroup(struct spear_pmx *pmx, 278static struct spear_gpio_pingroup *get_gpio_pingroup(struct spear_pmx *pmx,
285 unsigned pin) 279 unsigned pin)
@@ -344,8 +338,7 @@ static const struct pinmux_ops spear_pinmux_ops = {
344 .get_functions_count = spear_pinctrl_get_funcs_count, 338 .get_functions_count = spear_pinctrl_get_funcs_count,
345 .get_function_name = spear_pinctrl_get_func_name, 339 .get_function_name = spear_pinctrl_get_func_name,
346 .get_function_groups = spear_pinctrl_get_func_groups, 340 .get_function_groups = spear_pinctrl_get_func_groups,
347 .enable = spear_pinctrl_enable, 341 .set_mux = spear_pinctrl_set_mux,
348 .disable = spear_pinctrl_disable,
349 .gpio_request_enable = gpio_request_enable, 342 .gpio_request_enable = gpio_request_enable,
350 .gpio_disable_free = gpio_disable_free, 343 .gpio_disable_free = gpio_disable_free,
351}; 344};
diff --git a/drivers/pinctrl/spear/pinctrl-spear1310.c b/drivers/pinctrl/spear/pinctrl-spear1310.c
index 1a8bbfec60ca..6d57d43ab640 100644
--- a/drivers/pinctrl/spear/pinctrl-spear1310.c
+++ b/drivers/pinctrl/spear/pinctrl-spear1310.c
@@ -2692,7 +2692,7 @@ static struct spear_pinctrl_machdata spear1310_machdata = {
2692 .modes_supported = false, 2692 .modes_supported = false,
2693}; 2693};
2694 2694
2695static struct of_device_id spear1310_pinctrl_of_match[] = { 2695static const struct of_device_id spear1310_pinctrl_of_match[] = {
2696 { 2696 {
2697 .compatible = "st,spear1310-pinmux", 2697 .compatible = "st,spear1310-pinmux",
2698 }, 2698 },
diff --git a/drivers/pinctrl/spear/pinctrl-spear1340.c b/drivers/pinctrl/spear/pinctrl-spear1340.c
index 873966e2b99f..d243e43e7f6d 100644
--- a/drivers/pinctrl/spear/pinctrl-spear1340.c
+++ b/drivers/pinctrl/spear/pinctrl-spear1340.c
@@ -2008,7 +2008,7 @@ static struct spear_pinctrl_machdata spear1340_machdata = {
2008 .modes_supported = false, 2008 .modes_supported = false,
2009}; 2009};
2010 2010
2011static struct of_device_id spear1340_pinctrl_of_match[] = { 2011static const struct of_device_id spear1340_pinctrl_of_match[] = {
2012 { 2012 {
2013 .compatible = "st,spear1340-pinmux", 2013 .compatible = "st,spear1340-pinmux",
2014 }, 2014 },
diff --git a/drivers/pinctrl/spear/pinctrl-spear300.c b/drivers/pinctrl/spear/pinctrl-spear300.c
index 4777c0d0e730..9db83e9ee18c 100644
--- a/drivers/pinctrl/spear/pinctrl-spear300.c
+++ b/drivers/pinctrl/spear/pinctrl-spear300.c
@@ -646,7 +646,7 @@ static struct spear_function *spear300_functions[] = {
646 &gpio1_function, 646 &gpio1_function,
647}; 647};
648 648
649static struct of_device_id spear300_pinctrl_of_match[] = { 649static const struct of_device_id spear300_pinctrl_of_match[] = {
650 { 650 {
651 .compatible = "st,spear300-pinmux", 651 .compatible = "st,spear300-pinmux",
652 }, 652 },
diff --git a/drivers/pinctrl/spear/pinctrl-spear310.c b/drivers/pinctrl/spear/pinctrl-spear310.c
index ed1d3608f486..db775a414b7a 100644
--- a/drivers/pinctrl/spear/pinctrl-spear310.c
+++ b/drivers/pinctrl/spear/pinctrl-spear310.c
@@ -371,7 +371,7 @@ static struct spear_function *spear310_functions[] = {
371 &tdm_function, 371 &tdm_function,
372}; 372};
373 373
374static struct of_device_id spear310_pinctrl_of_match[] = { 374static const struct of_device_id spear310_pinctrl_of_match[] = {
375 { 375 {
376 .compatible = "st,spear310-pinmux", 376 .compatible = "st,spear310-pinmux",
377 }, 377 },
diff --git a/drivers/pinctrl/spear/pinctrl-spear320.c b/drivers/pinctrl/spear/pinctrl-spear320.c
index b8e290a8c8c9..80fbd68e17bc 100644
--- a/drivers/pinctrl/spear/pinctrl-spear320.c
+++ b/drivers/pinctrl/spear/pinctrl-spear320.c
@@ -3410,7 +3410,7 @@ static struct spear_function *spear320_functions[] = {
3410 &i2c2_function, 3410 &i2c2_function,
3411}; 3411};
3412 3412
3413static struct of_device_id spear320_pinctrl_of_match[] = { 3413static const struct of_device_id spear320_pinctrl_of_match[] = {
3414 { 3414 {
3415 .compatible = "st,spear320-pinmux", 3415 .compatible = "st,spear320-pinmux",
3416 }, 3416 },
diff --git a/drivers/pinctrl/sunxi/Kconfig b/drivers/pinctrl/sunxi/Kconfig
index 73e0a305ea13..a5e10f777ed2 100644
--- a/drivers/pinctrl/sunxi/Kconfig
+++ b/drivers/pinctrl/sunxi/Kconfig
@@ -1,36 +1,42 @@
1if ARCH_SUNXI 1if ARCH_SUNXI
2 2
3config PINCTRL_SUNXI
4 bool
5
6config PINCTRL_SUNXI_COMMON 3config PINCTRL_SUNXI_COMMON
7 bool 4 bool
8 select PINMUX 5 select PINMUX
9 select GENERIC_PINCONF 6 select GENERIC_PINCONF
10 7
11config PINCTRL_SUN4I_A10 8config PINCTRL_SUN4I_A10
12 def_bool PINCTRL_SUNXI || MACH_SUN4I 9 def_bool MACH_SUN4I
13 select PINCTRL_SUNXI_COMMON 10 select PINCTRL_SUNXI_COMMON
14 11
15config PINCTRL_SUN5I_A10S 12config PINCTRL_SUN5I_A10S
16 def_bool PINCTRL_SUNXI || MACH_SUN5I 13 def_bool MACH_SUN5I
17 select PINCTRL_SUNXI_COMMON 14 select PINCTRL_SUNXI_COMMON
18 15
19config PINCTRL_SUN5I_A13 16config PINCTRL_SUN5I_A13
20 def_bool PINCTRL_SUNXI || MACH_SUN5I 17 def_bool MACH_SUN5I
21 select PINCTRL_SUNXI_COMMON 18 select PINCTRL_SUNXI_COMMON
22 19
23config PINCTRL_SUN6I_A31 20config PINCTRL_SUN6I_A31
24 def_bool PINCTRL_SUNXI || MACH_SUN6I 21 def_bool MACH_SUN6I
25 select PINCTRL_SUNXI_COMMON 22 select PINCTRL_SUNXI_COMMON
26 23
27config PINCTRL_SUN6I_A31_R 24config PINCTRL_SUN6I_A31_R
28 def_bool PINCTRL_SUNXI || MACH_SUN6I 25 def_bool MACH_SUN6I
29 depends on RESET_CONTROLLER 26 depends on RESET_CONTROLLER
30 select PINCTRL_SUNXI_COMMON 27 select PINCTRL_SUNXI_COMMON
31 28
32config PINCTRL_SUN7I_A20 29config PINCTRL_SUN7I_A20
33 def_bool PINCTRL_SUNXI || MACH_SUN7I 30 def_bool MACH_SUN7I
31 select PINCTRL_SUNXI_COMMON
32
33config PINCTRL_SUN8I_A23
34 def_bool MACH_SUN8I
35 select PINCTRL_SUNXI_COMMON
36
37config PINCTRL_SUN8I_A23_R
38 def_bool MACH_SUN8I
39 depends on RESET_CONTROLLER
34 select PINCTRL_SUNXI_COMMON 40 select PINCTRL_SUNXI_COMMON
35 41
36endif 42endif
diff --git a/drivers/pinctrl/sunxi/Makefile b/drivers/pinctrl/sunxi/Makefile
index 0f4461cbe11d..e797efb02901 100644
--- a/drivers/pinctrl/sunxi/Makefile
+++ b/drivers/pinctrl/sunxi/Makefile
@@ -8,3 +8,5 @@ obj-$(CONFIG_PINCTRL_SUN5I_A13) += pinctrl-sun5i-a13.o
8obj-$(CONFIG_PINCTRL_SUN6I_A31) += pinctrl-sun6i-a31.o 8obj-$(CONFIG_PINCTRL_SUN6I_A31) += pinctrl-sun6i-a31.o
9obj-$(CONFIG_PINCTRL_SUN6I_A31_R) += pinctrl-sun6i-a31-r.o 9obj-$(CONFIG_PINCTRL_SUN6I_A31_R) += pinctrl-sun6i-a31-r.o
10obj-$(CONFIG_PINCTRL_SUN7I_A20) += pinctrl-sun7i-a20.o 10obj-$(CONFIG_PINCTRL_SUN7I_A20) += pinctrl-sun7i-a20.o
11obj-$(CONFIG_PINCTRL_SUN8I_A23) += pinctrl-sun8i-a23.o
12obj-$(CONFIG_PINCTRL_SUN8I_A23_R) += pinctrl-sun8i-a23-r.o
diff --git a/drivers/pinctrl/sunxi/pinctrl-sun4i-a10.c b/drivers/pinctrl/sunxi/pinctrl-sun4i-a10.c
index fa1ff7c7e357..86b608bedca6 100644
--- a/drivers/pinctrl/sunxi/pinctrl-sun4i-a10.c
+++ b/drivers/pinctrl/sunxi/pinctrl-sun4i-a10.c
@@ -1010,6 +1010,7 @@ static const struct sunxi_desc_pin sun4i_a10_pins[] = {
1010static const struct sunxi_pinctrl_desc sun4i_a10_pinctrl_data = { 1010static const struct sunxi_pinctrl_desc sun4i_a10_pinctrl_data = {
1011 .pins = sun4i_a10_pins, 1011 .pins = sun4i_a10_pins,
1012 .npins = ARRAY_SIZE(sun4i_a10_pins), 1012 .npins = ARRAY_SIZE(sun4i_a10_pins),
1013 .irq_banks = 1,
1013}; 1014};
1014 1015
1015static int sun4i_a10_pinctrl_probe(struct platform_device *pdev) 1016static int sun4i_a10_pinctrl_probe(struct platform_device *pdev)
diff --git a/drivers/pinctrl/sunxi/pinctrl-sun5i-a10s.c b/drivers/pinctrl/sunxi/pinctrl-sun5i-a10s.c
index 164d743f526c..2fa7430cabaf 100644
--- a/drivers/pinctrl/sunxi/pinctrl-sun5i-a10s.c
+++ b/drivers/pinctrl/sunxi/pinctrl-sun5i-a10s.c
@@ -661,6 +661,7 @@ static const struct sunxi_desc_pin sun5i_a10s_pins[] = {
661static const struct sunxi_pinctrl_desc sun5i_a10s_pinctrl_data = { 661static const struct sunxi_pinctrl_desc sun5i_a10s_pinctrl_data = {
662 .pins = sun5i_a10s_pins, 662 .pins = sun5i_a10s_pins,
663 .npins = ARRAY_SIZE(sun5i_a10s_pins), 663 .npins = ARRAY_SIZE(sun5i_a10s_pins),
664 .irq_banks = 1,
664}; 665};
665 666
666static int sun5i_a10s_pinctrl_probe(struct platform_device *pdev) 667static int sun5i_a10s_pinctrl_probe(struct platform_device *pdev)
diff --git a/drivers/pinctrl/sunxi/pinctrl-sun5i-a13.c b/drivers/pinctrl/sunxi/pinctrl-sun5i-a13.c
index 1188a2b7b988..e47c33dbae3a 100644
--- a/drivers/pinctrl/sunxi/pinctrl-sun5i-a13.c
+++ b/drivers/pinctrl/sunxi/pinctrl-sun5i-a13.c
@@ -330,15 +330,12 @@ static const struct sunxi_desc_pin sun5i_a13_pins[] = {
330 /* Hole */ 330 /* Hole */
331 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 0), 331 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 0),
332 SUNXI_FUNCTION(0x0, "gpio_in"), 332 SUNXI_FUNCTION(0x0, "gpio_in"),
333 SUNXI_FUNCTION(0x1, "gpio_out"),
334 SUNXI_FUNCTION_IRQ(0x6, 0)), /* EINT0 */ 333 SUNXI_FUNCTION_IRQ(0x6, 0)), /* EINT0 */
335 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 1), 334 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 1),
336 SUNXI_FUNCTION(0x0, "gpio_in"), 335 SUNXI_FUNCTION(0x0, "gpio_in"),
337 SUNXI_FUNCTION(0x1, "gpio_out"),
338 SUNXI_FUNCTION_IRQ(0x6, 1)), /* EINT1 */ 336 SUNXI_FUNCTION_IRQ(0x6, 1)), /* EINT1 */
339 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 2), 337 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 2),
340 SUNXI_FUNCTION(0x0, "gpio_in"), 338 SUNXI_FUNCTION(0x0, "gpio_in"),
341 SUNXI_FUNCTION(0x1, "gpio_out"),
342 SUNXI_FUNCTION_IRQ(0x6, 2)), /* EINT2 */ 339 SUNXI_FUNCTION_IRQ(0x6, 2)), /* EINT2 */
343 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 3), 340 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 3),
344 SUNXI_FUNCTION(0x0, "gpio_in"), 341 SUNXI_FUNCTION(0x0, "gpio_in"),
@@ -382,6 +379,7 @@ static const struct sunxi_desc_pin sun5i_a13_pins[] = {
382static const struct sunxi_pinctrl_desc sun5i_a13_pinctrl_data = { 379static const struct sunxi_pinctrl_desc sun5i_a13_pinctrl_data = {
383 .pins = sun5i_a13_pins, 380 .pins = sun5i_a13_pins,
384 .npins = ARRAY_SIZE(sun5i_a13_pins), 381 .npins = ARRAY_SIZE(sun5i_a13_pins),
382 .irq_banks = 1,
385}; 383};
386 384
387static int sun5i_a13_pinctrl_probe(struct platform_device *pdev) 385static int sun5i_a13_pinctrl_probe(struct platform_device *pdev)
diff --git a/drivers/pinctrl/sunxi/pinctrl-sun6i-a31-r.c b/drivers/pinctrl/sunxi/pinctrl-sun6i-a31-r.c
index 8fcba48e0a42..9a2517b65113 100644
--- a/drivers/pinctrl/sunxi/pinctrl-sun6i-a31-r.c
+++ b/drivers/pinctrl/sunxi/pinctrl-sun6i-a31-r.c
@@ -93,6 +93,7 @@ static const struct sunxi_pinctrl_desc sun6i_a31_r_pinctrl_data = {
93 .pins = sun6i_a31_r_pins, 93 .pins = sun6i_a31_r_pins,
94 .npins = ARRAY_SIZE(sun6i_a31_r_pins), 94 .npins = ARRAY_SIZE(sun6i_a31_r_pins),
95 .pin_base = PL_BASE, 95 .pin_base = PL_BASE,
96 .irq_banks = 2,
96}; 97};
97 98
98static int sun6i_a31_r_pinctrl_probe(struct platform_device *pdev) 99static int sun6i_a31_r_pinctrl_probe(struct platform_device *pdev)
diff --git a/drivers/pinctrl/sunxi/pinctrl-sun6i-a31.c b/drivers/pinctrl/sunxi/pinctrl-sun6i-a31.c
index 8dea5856458b..a2b4b85c5ad5 100644
--- a/drivers/pinctrl/sunxi/pinctrl-sun6i-a31.c
+++ b/drivers/pinctrl/sunxi/pinctrl-sun6i-a31.c
@@ -24,208 +24,244 @@ static const struct sunxi_desc_pin sun6i_a31_pins[] = {
24 SUNXI_FUNCTION(0x1, "gpio_out"), 24 SUNXI_FUNCTION(0x1, "gpio_out"),
25 SUNXI_FUNCTION(0x2, "gmac"), /* TXD0 */ 25 SUNXI_FUNCTION(0x2, "gmac"), /* TXD0 */
26 SUNXI_FUNCTION(0x3, "lcd1"), /* D0 */ 26 SUNXI_FUNCTION(0x3, "lcd1"), /* D0 */
27 SUNXI_FUNCTION(0x4, "uart1")), /* DTR */ 27 SUNXI_FUNCTION(0x4, "uart1"), /* DTR */
28 SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 0)), /* PA_EINT0 */
28 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 1), 29 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 1),
29 SUNXI_FUNCTION(0x0, "gpio_in"), 30 SUNXI_FUNCTION(0x0, "gpio_in"),
30 SUNXI_FUNCTION(0x1, "gpio_out"), 31 SUNXI_FUNCTION(0x1, "gpio_out"),
31 SUNXI_FUNCTION(0x2, "gmac"), /* TXD1 */ 32 SUNXI_FUNCTION(0x2, "gmac"), /* TXD1 */
32 SUNXI_FUNCTION(0x3, "lcd1"), /* D1 */ 33 SUNXI_FUNCTION(0x3, "lcd1"), /* D1 */
33 SUNXI_FUNCTION(0x4, "uart1")), /* DSR */ 34 SUNXI_FUNCTION(0x4, "uart1"), /* DSR */
35 SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 1)), /* PA_EINT1 */
34 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 2), 36 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 2),
35 SUNXI_FUNCTION(0x0, "gpio_in"), 37 SUNXI_FUNCTION(0x0, "gpio_in"),
36 SUNXI_FUNCTION(0x1, "gpio_out"), 38 SUNXI_FUNCTION(0x1, "gpio_out"),
37 SUNXI_FUNCTION(0x2, "gmac"), /* TXD2 */ 39 SUNXI_FUNCTION(0x2, "gmac"), /* TXD2 */
38 SUNXI_FUNCTION(0x3, "lcd1"), /* D2 */ 40 SUNXI_FUNCTION(0x3, "lcd1"), /* D2 */
39 SUNXI_FUNCTION(0x4, "uart1")), /* DCD */ 41 SUNXI_FUNCTION(0x4, "uart1"), /* DCD */
42 SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 2)), /* PA_EINT2 */
40 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 3), 43 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 3),
41 SUNXI_FUNCTION(0x0, "gpio_in"), 44 SUNXI_FUNCTION(0x0, "gpio_in"),
42 SUNXI_FUNCTION(0x1, "gpio_out"), 45 SUNXI_FUNCTION(0x1, "gpio_out"),
43 SUNXI_FUNCTION(0x2, "gmac"), /* TXD3 */ 46 SUNXI_FUNCTION(0x2, "gmac"), /* TXD3 */
44 SUNXI_FUNCTION(0x3, "lcd1"), /* D3 */ 47 SUNXI_FUNCTION(0x3, "lcd1"), /* D3 */
45 SUNXI_FUNCTION(0x4, "uart1")), /* RING */ 48 SUNXI_FUNCTION(0x4, "uart1"), /* RING */
49 SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 3)), /* PA_EINT3 */
46 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 4), 50 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 4),
47 SUNXI_FUNCTION(0x0, "gpio_in"), 51 SUNXI_FUNCTION(0x0, "gpio_in"),
48 SUNXI_FUNCTION(0x1, "gpio_out"), 52 SUNXI_FUNCTION(0x1, "gpio_out"),
49 SUNXI_FUNCTION(0x2, "gmac"), /* TXD4 */ 53 SUNXI_FUNCTION(0x2, "gmac"), /* TXD4 */
50 SUNXI_FUNCTION(0x3, "lcd1"), /* D4 */ 54 SUNXI_FUNCTION(0x3, "lcd1"), /* D4 */
51 SUNXI_FUNCTION(0x4, "uart1")), /* TX */ 55 SUNXI_FUNCTION(0x4, "uart1"), /* TX */
56 SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 4)), /* PA_EINT4 */
52 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 5), 57 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 5),
53 SUNXI_FUNCTION(0x0, "gpio_in"), 58 SUNXI_FUNCTION(0x0, "gpio_in"),
54 SUNXI_FUNCTION(0x1, "gpio_out"), 59 SUNXI_FUNCTION(0x1, "gpio_out"),
55 SUNXI_FUNCTION(0x2, "gmac"), /* TXD5 */ 60 SUNXI_FUNCTION(0x2, "gmac"), /* TXD5 */
56 SUNXI_FUNCTION(0x3, "lcd1"), /* D5 */ 61 SUNXI_FUNCTION(0x3, "lcd1"), /* D5 */
57 SUNXI_FUNCTION(0x4, "uart1")), /* RX */ 62 SUNXI_FUNCTION(0x4, "uart1"), /* RX */
63 SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 5)), /* PA_EINT5 */
58 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 6), 64 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 6),
59 SUNXI_FUNCTION(0x0, "gpio_in"), 65 SUNXI_FUNCTION(0x0, "gpio_in"),
60 SUNXI_FUNCTION(0x1, "gpio_out"), 66 SUNXI_FUNCTION(0x1, "gpio_out"),
61 SUNXI_FUNCTION(0x2, "gmac"), /* TXD6 */ 67 SUNXI_FUNCTION(0x2, "gmac"), /* TXD6 */
62 SUNXI_FUNCTION(0x3, "lcd1"), /* D6 */ 68 SUNXI_FUNCTION(0x3, "lcd1"), /* D6 */
63 SUNXI_FUNCTION(0x4, "uart1")), /* RTS */ 69 SUNXI_FUNCTION(0x4, "uart1"), /* RTS */
70 SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 6)), /* PA_EINT6 */
64 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 7), 71 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 7),
65 SUNXI_FUNCTION(0x0, "gpio_in"), 72 SUNXI_FUNCTION(0x0, "gpio_in"),
66 SUNXI_FUNCTION(0x1, "gpio_out"), 73 SUNXI_FUNCTION(0x1, "gpio_out"),
67 SUNXI_FUNCTION(0x2, "gmac"), /* TXD7 */ 74 SUNXI_FUNCTION(0x2, "gmac"), /* TXD7 */
68 SUNXI_FUNCTION(0x3, "lcd1"), /* D7 */ 75 SUNXI_FUNCTION(0x3, "lcd1"), /* D7 */
69 SUNXI_FUNCTION(0x4, "uart1")), /* CTS */ 76 SUNXI_FUNCTION(0x4, "uart1"), /* CTS */
77 SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 7)), /* PA_EINT7 */
70 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 8), 78 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 8),
71 SUNXI_FUNCTION(0x0, "gpio_in"), 79 SUNXI_FUNCTION(0x0, "gpio_in"),
72 SUNXI_FUNCTION(0x1, "gpio_out"), 80 SUNXI_FUNCTION(0x1, "gpio_out"),
73 SUNXI_FUNCTION(0x2, "gmac"), /* TXCLK */ 81 SUNXI_FUNCTION(0x2, "gmac"), /* TXCLK */
74 SUNXI_FUNCTION(0x3, "lcd1")), /* D8 */ 82 SUNXI_FUNCTION(0x3, "lcd1"), /* D8 */
83 SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 8)), /* PA_EINT8 */
75 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 9), 84 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 9),
76 SUNXI_FUNCTION(0x0, "gpio_in"), 85 SUNXI_FUNCTION(0x0, "gpio_in"),
77 SUNXI_FUNCTION(0x1, "gpio_out"), 86 SUNXI_FUNCTION(0x1, "gpio_out"),
78 SUNXI_FUNCTION(0x2, "gmac"), /* TXEN */ 87 SUNXI_FUNCTION(0x2, "gmac"), /* TXEN */
79 SUNXI_FUNCTION(0x3, "lcd1"), /* D9 */ 88 SUNXI_FUNCTION(0x3, "lcd1"), /* D9 */
80 SUNXI_FUNCTION(0x4, "mmc3"), /* CMD */ 89 SUNXI_FUNCTION(0x4, "mmc3"), /* CMD */
81 SUNXI_FUNCTION(0x5, "mmc2")), /* CMD */ 90 SUNXI_FUNCTION(0x5, "mmc2"), /* CMD */
91 SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 9)), /* PA_EINT9 */
82 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 10), 92 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 10),
83 SUNXI_FUNCTION(0x0, "gpio_in"), 93 SUNXI_FUNCTION(0x0, "gpio_in"),
84 SUNXI_FUNCTION(0x1, "gpio_out"), 94 SUNXI_FUNCTION(0x1, "gpio_out"),
85 SUNXI_FUNCTION(0x2, "gmac"), /* GTXCLK */ 95 SUNXI_FUNCTION(0x2, "gmac"), /* GTXCLK */
86 SUNXI_FUNCTION(0x3, "lcd1"), /* D10 */ 96 SUNXI_FUNCTION(0x3, "lcd1"), /* D10 */
87 SUNXI_FUNCTION(0x4, "mmc3"), /* CLK */ 97 SUNXI_FUNCTION(0x4, "mmc3"), /* CLK */
88 SUNXI_FUNCTION(0x5, "mmc2")), /* CLK */ 98 SUNXI_FUNCTION(0x5, "mmc2"), /* CLK */
99 SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 10)), /* PA_EINT10 */
89 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 11), 100 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 11),
90 SUNXI_FUNCTION(0x0, "gpio_in"), 101 SUNXI_FUNCTION(0x0, "gpio_in"),
91 SUNXI_FUNCTION(0x1, "gpio_out"), 102 SUNXI_FUNCTION(0x1, "gpio_out"),
92 SUNXI_FUNCTION(0x2, "gmac"), /* RXD0 */ 103 SUNXI_FUNCTION(0x2, "gmac"), /* RXD0 */
93 SUNXI_FUNCTION(0x3, "lcd1"), /* D11 */ 104 SUNXI_FUNCTION(0x3, "lcd1"), /* D11 */
94 SUNXI_FUNCTION(0x4, "mmc3"), /* D0 */ 105 SUNXI_FUNCTION(0x4, "mmc3"), /* D0 */
95 SUNXI_FUNCTION(0x5, "mmc2")), /* D0 */ 106 SUNXI_FUNCTION(0x5, "mmc2"), /* D0 */
107 SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 11)), /* PA_EINT11 */
96 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 12), 108 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 12),
97 SUNXI_FUNCTION(0x0, "gpio_in"), 109 SUNXI_FUNCTION(0x0, "gpio_in"),
98 SUNXI_FUNCTION(0x1, "gpio_out"), 110 SUNXI_FUNCTION(0x1, "gpio_out"),
99 SUNXI_FUNCTION(0x2, "gmac"), /* RXD1 */ 111 SUNXI_FUNCTION(0x2, "gmac"), /* RXD1 */
100 SUNXI_FUNCTION(0x3, "lcd1"), /* D12 */ 112 SUNXI_FUNCTION(0x3, "lcd1"), /* D12 */
101 SUNXI_FUNCTION(0x4, "mmc3"), /* D1 */ 113 SUNXI_FUNCTION(0x4, "mmc3"), /* D1 */
102 SUNXI_FUNCTION(0x5, "mmc2")), /* D1 */ 114 SUNXI_FUNCTION(0x5, "mmc2"), /* D1 */
115 SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 12)), /* PA_EINT12 */
103 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 13), 116 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 13),
104 SUNXI_FUNCTION(0x0, "gpio_in"), 117 SUNXI_FUNCTION(0x0, "gpio_in"),
105 SUNXI_FUNCTION(0x1, "gpio_out"), 118 SUNXI_FUNCTION(0x1, "gpio_out"),
106 SUNXI_FUNCTION(0x2, "gmac"), /* RXD2 */ 119 SUNXI_FUNCTION(0x2, "gmac"), /* RXD2 */
107 SUNXI_FUNCTION(0x3, "lcd1"), /* D13 */ 120 SUNXI_FUNCTION(0x3, "lcd1"), /* D13 */
108 SUNXI_FUNCTION(0x4, "mmc3"), /* D2 */ 121 SUNXI_FUNCTION(0x4, "mmc3"), /* D2 */
109 SUNXI_FUNCTION(0x5, "mmc2")), /* D2 */ 122 SUNXI_FUNCTION(0x5, "mmc2"), /* D2 */
123 SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 13)), /* PA_EINT13 */
110 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 14), 124 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 14),
111 SUNXI_FUNCTION(0x0, "gpio_in"), 125 SUNXI_FUNCTION(0x0, "gpio_in"),
112 SUNXI_FUNCTION(0x1, "gpio_out"), 126 SUNXI_FUNCTION(0x1, "gpio_out"),
113 SUNXI_FUNCTION(0x2, "gmac"), /* RXD3 */ 127 SUNXI_FUNCTION(0x2, "gmac"), /* RXD3 */
114 SUNXI_FUNCTION(0x3, "lcd1"), /* D14 */ 128 SUNXI_FUNCTION(0x3, "lcd1"), /* D14 */
115 SUNXI_FUNCTION(0x4, "mmc3"), /* D3 */ 129 SUNXI_FUNCTION(0x4, "mmc3"), /* D3 */
116 SUNXI_FUNCTION(0x5, "mmc2")), /* D3 */ 130 SUNXI_FUNCTION(0x5, "mmc2"), /* D3 */
131 SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 14)), /* PA_EINT14 */
117 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 15), 132 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 15),
118 SUNXI_FUNCTION(0x0, "gpio_in"), 133 SUNXI_FUNCTION(0x0, "gpio_in"),
119 SUNXI_FUNCTION(0x1, "gpio_out"), 134 SUNXI_FUNCTION(0x1, "gpio_out"),
120 SUNXI_FUNCTION(0x2, "gmac"), /* RXD4 */ 135 SUNXI_FUNCTION(0x2, "gmac"), /* RXD4 */
121 SUNXI_FUNCTION(0x3, "lcd1")), /* D15 */ 136 SUNXI_FUNCTION(0x3, "lcd1"), /* D15 */
137 SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 15)), /* PA_EINT15 */
122 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 16), 138 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 16),
123 SUNXI_FUNCTION(0x0, "gpio_in"), 139 SUNXI_FUNCTION(0x0, "gpio_in"),
124 SUNXI_FUNCTION(0x1, "gpio_out"), 140 SUNXI_FUNCTION(0x1, "gpio_out"),
125 SUNXI_FUNCTION(0x2, "gmac"), /* RXD5 */ 141 SUNXI_FUNCTION(0x2, "gmac"), /* RXD5 */
126 SUNXI_FUNCTION(0x3, "lcd1")), /* D16 */ 142 SUNXI_FUNCTION(0x3, "lcd1"), /* D16 */
143 SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 16)), /* PA_EINT16 */
127 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 17), 144 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 17),
128 SUNXI_FUNCTION(0x0, "gpio_in"), 145 SUNXI_FUNCTION(0x0, "gpio_in"),
129 SUNXI_FUNCTION(0x1, "gpio_out"), 146 SUNXI_FUNCTION(0x1, "gpio_out"),
130 SUNXI_FUNCTION(0x2, "gmac"), /* RXD6 */ 147 SUNXI_FUNCTION(0x2, "gmac"), /* RXD6 */
131 SUNXI_FUNCTION(0x3, "lcd1")), /* D17 */ 148 SUNXI_FUNCTION(0x3, "lcd1"), /* D17 */
149 SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 17)), /* PA_EINT17 */
132 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 18), 150 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 18),
133 SUNXI_FUNCTION(0x0, "gpio_in"), 151 SUNXI_FUNCTION(0x0, "gpio_in"),
134 SUNXI_FUNCTION(0x1, "gpio_out"), 152 SUNXI_FUNCTION(0x1, "gpio_out"),
135 SUNXI_FUNCTION(0x2, "gmac"), /* RXD7 */ 153 SUNXI_FUNCTION(0x2, "gmac"), /* RXD7 */
136 SUNXI_FUNCTION(0x3, "lcd1")), /* D18 */ 154 SUNXI_FUNCTION(0x3, "lcd1"), /* D18 */
155 SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 18)), /* PA_EINT18 */
137 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 19), 156 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 19),
138 SUNXI_FUNCTION(0x0, "gpio_in"), 157 SUNXI_FUNCTION(0x0, "gpio_in"),
139 SUNXI_FUNCTION(0x1, "gpio_out"), 158 SUNXI_FUNCTION(0x1, "gpio_out"),
140 SUNXI_FUNCTION(0x2, "gmac"), /* RXDV */ 159 SUNXI_FUNCTION(0x2, "gmac"), /* RXDV */
141 SUNXI_FUNCTION(0x3, "lcd1"), /* D19 */ 160 SUNXI_FUNCTION(0x3, "lcd1"), /* D19 */
142 SUNXI_FUNCTION(0x4, "pwm3")), /* Positive */ 161 SUNXI_FUNCTION(0x4, "pwm3"), /* Positive */
162 SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 19)), /* PA_EINT19 */
143 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 20), 163 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 20),
144 SUNXI_FUNCTION(0x0, "gpio_in"), 164 SUNXI_FUNCTION(0x0, "gpio_in"),
145 SUNXI_FUNCTION(0x1, "gpio_out"), 165 SUNXI_FUNCTION(0x1, "gpio_out"),
146 SUNXI_FUNCTION(0x2, "gmac"), /* RXCLK */ 166 SUNXI_FUNCTION(0x2, "gmac"), /* RXCLK */
147 SUNXI_FUNCTION(0x3, "lcd1"), /* D20 */ 167 SUNXI_FUNCTION(0x3, "lcd1"), /* D20 */
148 SUNXI_FUNCTION(0x4, "pwm3")), /* Negative */ 168 SUNXI_FUNCTION(0x4, "pwm3"), /* Negative */
169 SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 20)), /* PA_EINT20 */
149 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 21), 170 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 21),
150 SUNXI_FUNCTION(0x0, "gpio_in"), 171 SUNXI_FUNCTION(0x0, "gpio_in"),
151 SUNXI_FUNCTION(0x1, "gpio_out"), 172 SUNXI_FUNCTION(0x1, "gpio_out"),
152 SUNXI_FUNCTION(0x2, "gmac"), /* TXERR */ 173 SUNXI_FUNCTION(0x2, "gmac"), /* TXERR */
153 SUNXI_FUNCTION(0x3, "lcd1"), /* D21 */ 174 SUNXI_FUNCTION(0x3, "lcd1"), /* D21 */
154 SUNXI_FUNCTION(0x4, "spi3")), /* CS0 */ 175 SUNXI_FUNCTION(0x4, "spi3"), /* CS0 */
176 SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 21)), /* PA_EINT21 */
155 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 22), 177 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 22),
156 SUNXI_FUNCTION(0x0, "gpio_in"), 178 SUNXI_FUNCTION(0x0, "gpio_in"),
157 SUNXI_FUNCTION(0x1, "gpio_out"), 179 SUNXI_FUNCTION(0x1, "gpio_out"),
158 SUNXI_FUNCTION(0x2, "gmac"), /* RXERR */ 180 SUNXI_FUNCTION(0x2, "gmac"), /* RXERR */
159 SUNXI_FUNCTION(0x3, "lcd1"), /* D22 */ 181 SUNXI_FUNCTION(0x3, "lcd1"), /* D22 */
160 SUNXI_FUNCTION(0x4, "spi3")), /* CLK */ 182 SUNXI_FUNCTION(0x4, "spi3"), /* CLK */
183 SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 22)), /* PA_EINT22 */
161 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 23), 184 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 23),
162 SUNXI_FUNCTION(0x0, "gpio_in"), 185 SUNXI_FUNCTION(0x0, "gpio_in"),
163 SUNXI_FUNCTION(0x1, "gpio_out"), 186 SUNXI_FUNCTION(0x1, "gpio_out"),
164 SUNXI_FUNCTION(0x2, "gmac"), /* COL */ 187 SUNXI_FUNCTION(0x2, "gmac"), /* COL */
165 SUNXI_FUNCTION(0x3, "lcd1"), /* D23 */ 188 SUNXI_FUNCTION(0x3, "lcd1"), /* D23 */
166 SUNXI_FUNCTION(0x4, "spi3")), /* MOSI */ 189 SUNXI_FUNCTION(0x4, "spi3"), /* MOSI */
190 SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 23)), /* PA_EINT23 */
167 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 24), 191 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 24),
168 SUNXI_FUNCTION(0x0, "gpio_in"), 192 SUNXI_FUNCTION(0x0, "gpio_in"),
169 SUNXI_FUNCTION(0x1, "gpio_out"), 193 SUNXI_FUNCTION(0x1, "gpio_out"),
170 SUNXI_FUNCTION(0x2, "gmac"), /* CRS */ 194 SUNXI_FUNCTION(0x2, "gmac"), /* CRS */
171 SUNXI_FUNCTION(0x3, "lcd1"), /* CLK */ 195 SUNXI_FUNCTION(0x3, "lcd1"), /* CLK */
172 SUNXI_FUNCTION(0x4, "spi3")), /* MISO */ 196 SUNXI_FUNCTION(0x4, "spi3"), /* MISO */
197 SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 24)), /* PA_EINT24 */
173 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 25), 198 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 25),
174 SUNXI_FUNCTION(0x0, "gpio_in"), 199 SUNXI_FUNCTION(0x0, "gpio_in"),
175 SUNXI_FUNCTION(0x1, "gpio_out"), 200 SUNXI_FUNCTION(0x1, "gpio_out"),
176 SUNXI_FUNCTION(0x2, "gmac"), /* CLKIN */ 201 SUNXI_FUNCTION(0x2, "gmac"), /* CLKIN */
177 SUNXI_FUNCTION(0x3, "lcd1"), /* DE */ 202 SUNXI_FUNCTION(0x3, "lcd1"), /* DE */
178 SUNXI_FUNCTION(0x4, "spi3")), /* CS1 */ 203 SUNXI_FUNCTION(0x4, "spi3"), /* CS1 */
204 SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 25)), /* PA_EINT25 */
179 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 26), 205 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 26),
180 SUNXI_FUNCTION(0x0, "gpio_in"), 206 SUNXI_FUNCTION(0x0, "gpio_in"),
181 SUNXI_FUNCTION(0x1, "gpio_out"), 207 SUNXI_FUNCTION(0x1, "gpio_out"),
182 SUNXI_FUNCTION(0x2, "gmac"), /* MDC */ 208 SUNXI_FUNCTION(0x2, "gmac"), /* MDC */
183 SUNXI_FUNCTION(0x3, "lcd1")), /* HSYNC */ 209 SUNXI_FUNCTION(0x3, "lcd1"), /* HSYNC */
210 SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 26)), /* PA_EINT26 */
184 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 27), 211 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 27),
185 SUNXI_FUNCTION(0x0, "gpio_in"), 212 SUNXI_FUNCTION(0x0, "gpio_in"),
186 SUNXI_FUNCTION(0x1, "gpio_out"), 213 SUNXI_FUNCTION(0x1, "gpio_out"),
187 SUNXI_FUNCTION(0x2, "gmac"), /* MDIO */ 214 SUNXI_FUNCTION(0x2, "gmac"), /* MDIO */
188 SUNXI_FUNCTION(0x3, "lcd1")), /* VSYNC */ 215 SUNXI_FUNCTION(0x3, "lcd1"), /* VSYNC */
216 SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 27)), /* PA_EINT27 */
189 /* Hole */ 217 /* Hole */
190 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 0), 218 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 0),
191 SUNXI_FUNCTION(0x0, "gpio_in"), 219 SUNXI_FUNCTION(0x0, "gpio_in"),
192 SUNXI_FUNCTION(0x1, "gpio_out"), 220 SUNXI_FUNCTION(0x1, "gpio_out"),
193 SUNXI_FUNCTION(0x2, "i2s0"), /* MCLK */ 221 SUNXI_FUNCTION(0x2, "i2s0"), /* MCLK */
194 SUNXI_FUNCTION(0x3, "uart3"), /* CTS */ 222 SUNXI_FUNCTION(0x3, "uart3"), /* CTS */
195 SUNXI_FUNCTION(0x4, "csi")), /* MCLK1 */ 223 SUNXI_FUNCTION(0x4, "csi"), /* MCLK1 */
224 SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 0)), /* PB_EINT0 */
196 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 1), 225 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 1),
197 SUNXI_FUNCTION(0x0, "gpio_in"), 226 SUNXI_FUNCTION(0x0, "gpio_in"),
198 SUNXI_FUNCTION(0x1, "gpio_out"), 227 SUNXI_FUNCTION(0x1, "gpio_out"),
199 SUNXI_FUNCTION(0x2, "i2s0")), /* BCLK */ 228 SUNXI_FUNCTION(0x2, "i2s0"), /* BCLK */
229 SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 1)), /* PB_EINT1 */
200 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 2), 230 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 2),
201 SUNXI_FUNCTION(0x0, "gpio_in"), 231 SUNXI_FUNCTION(0x0, "gpio_in"),
202 SUNXI_FUNCTION(0x1, "gpio_out"), 232 SUNXI_FUNCTION(0x1, "gpio_out"),
203 SUNXI_FUNCTION(0x2, "i2s0")), /* LRCK */ 233 SUNXI_FUNCTION(0x2, "i2s0"), /* LRCK */
234 SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 2)), /* PB_EINT2 */
204 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 3), 235 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 3),
205 SUNXI_FUNCTION(0x0, "gpio_in"), 236 SUNXI_FUNCTION(0x0, "gpio_in"),
206 SUNXI_FUNCTION(0x1, "gpio_out"), 237 SUNXI_FUNCTION(0x1, "gpio_out"),
207 SUNXI_FUNCTION(0x2, "i2s0")), /* DO0 */ 238 SUNXI_FUNCTION(0x2, "i2s0"), /* DO0 */
239 SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 3)), /* PB_EINT3 */
208 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 4), 240 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 4),
209 SUNXI_FUNCTION(0x0, "gpio_in"), 241 SUNXI_FUNCTION(0x0, "gpio_in"),
210 SUNXI_FUNCTION(0x1, "gpio_out"), 242 SUNXI_FUNCTION(0x1, "gpio_out"),
211 SUNXI_FUNCTION(0x2, "i2s0"), /* DO1 */ 243 SUNXI_FUNCTION(0x2, "i2s0"), /* DO1 */
212 SUNXI_FUNCTION(0x3, "uart3")), /* RTS */ 244 SUNXI_FUNCTION(0x3, "uart3"), /* RTS */
245 SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 4)), /* PB_EINT4 */
213 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 5), 246 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 5),
214 SUNXI_FUNCTION(0x0, "gpio_in"), 247 SUNXI_FUNCTION(0x0, "gpio_in"),
215 SUNXI_FUNCTION(0x1, "gpio_out"), 248 SUNXI_FUNCTION(0x1, "gpio_out"),
216 SUNXI_FUNCTION(0x2, "i2s0"), /* DO2 */ 249 SUNXI_FUNCTION(0x2, "i2s0"), /* DO2 */
217 SUNXI_FUNCTION(0x3, "uart3"), /* TX */ 250 SUNXI_FUNCTION(0x3, "uart3"), /* TX */
218 SUNXI_FUNCTION(0x4, "i2c3")), /* SCK */ 251 SUNXI_FUNCTION(0x4, "i2c3"), /* SCK */
252 SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 5)), /* PB_EINT5 */
219 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 6), 253 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 6),
220 SUNXI_FUNCTION(0x0, "gpio_in"), 254 SUNXI_FUNCTION(0x0, "gpio_in"),
221 SUNXI_FUNCTION(0x1, "gpio_out"), 255 SUNXI_FUNCTION(0x1, "gpio_out"),
222 SUNXI_FUNCTION(0x2, "i2s0"), /* DO3 */ 256 SUNXI_FUNCTION(0x2, "i2s0"), /* DO3 */
223 SUNXI_FUNCTION(0x3, "uart3"), /* RX */ 257 SUNXI_FUNCTION(0x3, "uart3"), /* RX */
224 SUNXI_FUNCTION(0x4, "i2c3")), /* SDA */ 258 SUNXI_FUNCTION(0x4, "i2c3"), /* SDA */
259 SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 6)), /* PB_EINT6 */
225 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 7), 260 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 7),
226 SUNXI_FUNCTION(0x0, "gpio_in"), 261 SUNXI_FUNCTION(0x0, "gpio_in"),
227 SUNXI_FUNCTION(0x1, "gpio_out"), 262 SUNXI_FUNCTION(0x1, "gpio_out"),
228 SUNXI_FUNCTION(0x3, "i2s0")), /* DI */ 263 SUNXI_FUNCTION(0x3, "i2s0"), /* DI */
264 SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 7)), /* PB_EINT7 */
229 /* Hole */ 265 /* Hole */
230 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 0), 266 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 0),
231 SUNXI_FUNCTION(0x0, "gpio_in"), 267 SUNXI_FUNCTION(0x0, "gpio_in"),
@@ -510,86 +546,103 @@ static const struct sunxi_desc_pin sun6i_a31_pins[] = {
510 SUNXI_FUNCTION(0x0, "gpio_in"), 546 SUNXI_FUNCTION(0x0, "gpio_in"),
511 SUNXI_FUNCTION(0x1, "gpio_out"), 547 SUNXI_FUNCTION(0x1, "gpio_out"),
512 SUNXI_FUNCTION(0x2, "csi"), /* PCLK */ 548 SUNXI_FUNCTION(0x2, "csi"), /* PCLK */
513 SUNXI_FUNCTION(0x3, "ts")), /* CLK */ 549 SUNXI_FUNCTION(0x3, "ts"), /* CLK */
550 SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 0)), /* PE_EINT0 */
514 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 1), 551 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 1),
515 SUNXI_FUNCTION(0x0, "gpio_in"), 552 SUNXI_FUNCTION(0x0, "gpio_in"),
516 SUNXI_FUNCTION(0x1, "gpio_out"), 553 SUNXI_FUNCTION(0x1, "gpio_out"),
517 SUNXI_FUNCTION(0x2, "csi"), /* MCLK */ 554 SUNXI_FUNCTION(0x2, "csi"), /* MCLK */
518 SUNXI_FUNCTION(0x3, "ts")), /* ERR */ 555 SUNXI_FUNCTION(0x3, "ts"), /* ERR */
556 SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 1)), /* PE_EINT1 */
519 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 2), 557 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 2),
520 SUNXI_FUNCTION(0x0, "gpio_in"), 558 SUNXI_FUNCTION(0x0, "gpio_in"),
521 SUNXI_FUNCTION(0x1, "gpio_out"), 559 SUNXI_FUNCTION(0x1, "gpio_out"),
522 SUNXI_FUNCTION(0x2, "csi"), /* HSYNC */ 560 SUNXI_FUNCTION(0x2, "csi"), /* HSYNC */
523 SUNXI_FUNCTION(0x3, "ts")), /* SYNC */ 561 SUNXI_FUNCTION(0x3, "ts"), /* SYNC */
562 SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 2)), /* PE_EINT2 */
524 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 3), 563 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 3),
525 SUNXI_FUNCTION(0x0, "gpio_in"), 564 SUNXI_FUNCTION(0x0, "gpio_in"),
526 SUNXI_FUNCTION(0x1, "gpio_out"), 565 SUNXI_FUNCTION(0x1, "gpio_out"),
527 SUNXI_FUNCTION(0x2, "csi"), /* VSYNC */ 566 SUNXI_FUNCTION(0x2, "csi"), /* VSYNC */
528 SUNXI_FUNCTION(0x3, "ts")), /* DVLD */ 567 SUNXI_FUNCTION(0x3, "ts"), /* DVLD */
568 SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 3)), /* PE_EINT3 */
529 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 4), 569 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 4),
530 SUNXI_FUNCTION(0x0, "gpio_in"), 570 SUNXI_FUNCTION(0x0, "gpio_in"),
531 SUNXI_FUNCTION(0x1, "gpio_out"), 571 SUNXI_FUNCTION(0x1, "gpio_out"),
532 SUNXI_FUNCTION(0x2, "csi"), /* D0 */ 572 SUNXI_FUNCTION(0x2, "csi"), /* D0 */
533 SUNXI_FUNCTION(0x3, "uart5")), /* TX */ 573 SUNXI_FUNCTION(0x3, "uart5"), /* TX */
574 SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 4)), /* PE_EINT4 */
534 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 5), 575 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 5),
535 SUNXI_FUNCTION(0x0, "gpio_in"), 576 SUNXI_FUNCTION(0x0, "gpio_in"),
536 SUNXI_FUNCTION(0x1, "gpio_out"), 577 SUNXI_FUNCTION(0x1, "gpio_out"),
537 SUNXI_FUNCTION(0x2, "csi"), /* D1 */ 578 SUNXI_FUNCTION(0x2, "csi"), /* D1 */
538 SUNXI_FUNCTION(0x3, "uart5")), /* RX */ 579 SUNXI_FUNCTION(0x3, "uart5"), /* RX */
580 SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 5)), /* PE_EINT5 */
539 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 6), 581 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 6),
540 SUNXI_FUNCTION(0x0, "gpio_in"), 582 SUNXI_FUNCTION(0x0, "gpio_in"),
541 SUNXI_FUNCTION(0x1, "gpio_out"), 583 SUNXI_FUNCTION(0x1, "gpio_out"),
542 SUNXI_FUNCTION(0x2, "csi"), /* D2 */ 584 SUNXI_FUNCTION(0x2, "csi"), /* D2 */
543 SUNXI_FUNCTION(0x3, "uart5")), /* RTS */ 585 SUNXI_FUNCTION(0x3, "uart5"), /* RTS */
586 SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 6)), /* PE_EINT6 */
544 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 7), 587 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 7),
545 SUNXI_FUNCTION(0x0, "gpio_in"), 588 SUNXI_FUNCTION(0x0, "gpio_in"),
546 SUNXI_FUNCTION(0x1, "gpio_out"), 589 SUNXI_FUNCTION(0x1, "gpio_out"),
547 SUNXI_FUNCTION(0x2, "csi"), /* D3 */ 590 SUNXI_FUNCTION(0x2, "csi"), /* D3 */
548 SUNXI_FUNCTION(0x3, "uart5")), /* CTS */ 591 SUNXI_FUNCTION(0x3, "uart5"), /* CTS */
592 SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 7)), /* PE_EINT7 */
549 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 8), 593 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 8),
550 SUNXI_FUNCTION(0x0, "gpio_in"), 594 SUNXI_FUNCTION(0x0, "gpio_in"),
551 SUNXI_FUNCTION(0x1, "gpio_out"), 595 SUNXI_FUNCTION(0x1, "gpio_out"),
552 SUNXI_FUNCTION(0x2, "csi"), /* D4 */ 596 SUNXI_FUNCTION(0x2, "csi"), /* D4 */
553 SUNXI_FUNCTION(0x3, "ts")), /* D0 */ 597 SUNXI_FUNCTION(0x3, "ts"), /* D0 */
598 SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 8)), /* PE_EINT8 */
554 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 9), 599 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 9),
555 SUNXI_FUNCTION(0x0, "gpio_in"), 600 SUNXI_FUNCTION(0x0, "gpio_in"),
556 SUNXI_FUNCTION(0x1, "gpio_out"), 601 SUNXI_FUNCTION(0x1, "gpio_out"),
557 SUNXI_FUNCTION(0x2, "csi"), /* D5 */ 602 SUNXI_FUNCTION(0x2, "csi"), /* D5 */
558 SUNXI_FUNCTION(0x3, "ts")), /* D1 */ 603 SUNXI_FUNCTION(0x3, "ts"), /* D1 */
604 SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 9)), /* PE_EINT9 */
559 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 10), 605 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 10),
560 SUNXI_FUNCTION(0x0, "gpio_in"), 606 SUNXI_FUNCTION(0x0, "gpio_in"),
561 SUNXI_FUNCTION(0x1, "gpio_out"), 607 SUNXI_FUNCTION(0x1, "gpio_out"),
562 SUNXI_FUNCTION(0x2, "csi"), /* D6 */ 608 SUNXI_FUNCTION(0x2, "csi"), /* D6 */
563 SUNXI_FUNCTION(0x3, "ts")), /* D2 */ 609 SUNXI_FUNCTION(0x3, "ts"), /* D2 */
610 SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 10)), /* PE_EINT10 */
564 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 11), 611 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 11),
565 SUNXI_FUNCTION(0x0, "gpio_in"), 612 SUNXI_FUNCTION(0x0, "gpio_in"),
566 SUNXI_FUNCTION(0x1, "gpio_out"), 613 SUNXI_FUNCTION(0x1, "gpio_out"),
567 SUNXI_FUNCTION(0x2, "csi"), /* D7 */ 614 SUNXI_FUNCTION(0x2, "csi"), /* D7 */
568 SUNXI_FUNCTION(0x3, "ts")), /* D3 */ 615 SUNXI_FUNCTION(0x3, "ts"), /* D3 */
616 SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 11)), /* PE_EINT11 */
569 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 12), 617 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 12),
570 SUNXI_FUNCTION(0x0, "gpio_in"), 618 SUNXI_FUNCTION(0x0, "gpio_in"),
571 SUNXI_FUNCTION(0x1, "gpio_out"), 619 SUNXI_FUNCTION(0x1, "gpio_out"),
572 SUNXI_FUNCTION(0x2, "csi"), /* D8 */ 620 SUNXI_FUNCTION(0x2, "csi"), /* D8 */
573 SUNXI_FUNCTION(0x3, "ts")), /* D4 */ 621 SUNXI_FUNCTION(0x3, "ts"), /* D4 */
622 SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 12)), /* PE_EINT12 */
574 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 13), 623 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 13),
575 SUNXI_FUNCTION(0x0, "gpio_in"), 624 SUNXI_FUNCTION(0x0, "gpio_in"),
576 SUNXI_FUNCTION(0x1, "gpio_out"), 625 SUNXI_FUNCTION(0x1, "gpio_out"),
577 SUNXI_FUNCTION(0x2, "csi"), /* D9 */ 626 SUNXI_FUNCTION(0x2, "csi"), /* D9 */
578 SUNXI_FUNCTION(0x3, "ts")), /* D5 */ 627 SUNXI_FUNCTION(0x3, "ts"), /* D5 */
628 SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 13)), /* PE_EINT13 */
579 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 14), 629 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 14),
580 SUNXI_FUNCTION(0x0, "gpio_in"), 630 SUNXI_FUNCTION(0x0, "gpio_in"),
581 SUNXI_FUNCTION(0x1, "gpio_out"), 631 SUNXI_FUNCTION(0x1, "gpio_out"),
582 SUNXI_FUNCTION(0x2, "csi"), /* D10 */ 632 SUNXI_FUNCTION(0x2, "csi"), /* D10 */
583 SUNXI_FUNCTION(0x3, "ts")), /* D6 */ 633 SUNXI_FUNCTION(0x3, "ts"), /* D6 */
634 SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 14)), /* PE_EINT14 */
584 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 15), 635 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 15),
585 SUNXI_FUNCTION(0x0, "gpio_in"), 636 SUNXI_FUNCTION(0x0, "gpio_in"),
586 SUNXI_FUNCTION(0x1, "gpio_out"), 637 SUNXI_FUNCTION(0x1, "gpio_out"),
587 SUNXI_FUNCTION(0x2, "csi"), /* D11 */ 638 SUNXI_FUNCTION(0x2, "csi"), /* D11 */
588 SUNXI_FUNCTION(0x3, "ts")), /* D7 */ 639 SUNXI_FUNCTION(0x3, "ts"), /* D7 */
640 SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 15)), /* PE_EINT15 */
589 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 16), 641 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 16),
590 SUNXI_FUNCTION(0x0, "gpio_in"), 642 SUNXI_FUNCTION(0x0, "gpio_in"),
591 SUNXI_FUNCTION(0x1, "gpio_out"), 643 SUNXI_FUNCTION(0x1, "gpio_out"),
592 SUNXI_FUNCTION(0x2, "csi")), /* MIPI CSI MCLK */ 644 SUNXI_FUNCTION(0x2, "csi"), /* MIPI CSI MCLK */
645 SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 16)), /* PE_EINT16 */
593 /* Hole */ 646 /* Hole */
594 SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 0), 647 SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 0),
595 SUNXI_FUNCTION(0x0, "gpio_in"), 648 SUNXI_FUNCTION(0x0, "gpio_in"),
@@ -625,86 +678,105 @@ static const struct sunxi_desc_pin sun6i_a31_pins[] = {
625 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 0), 678 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 0),
626 SUNXI_FUNCTION(0x0, "gpio_in"), 679 SUNXI_FUNCTION(0x0, "gpio_in"),
627 SUNXI_FUNCTION(0x1, "gpio_out"), 680 SUNXI_FUNCTION(0x1, "gpio_out"),
628 SUNXI_FUNCTION(0x2, "mmc1")), /* CLK */ 681 SUNXI_FUNCTION(0x2, "mmc1"), /* CLK */
682 SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 0)), /* PG_EINT0 */
629 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 1), 683 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 1),
630 SUNXI_FUNCTION(0x0, "gpio_in"), 684 SUNXI_FUNCTION(0x0, "gpio_in"),
631 SUNXI_FUNCTION(0x1, "gpio_out"), 685 SUNXI_FUNCTION(0x1, "gpio_out"),
632 SUNXI_FUNCTION(0x2, "mmc1")), /* CMD */ 686 SUNXI_FUNCTION(0x2, "mmc1"), /* CMD */
687 SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 1)), /* PG_EINT1 */
633 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 2), 688 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 2),
634 SUNXI_FUNCTION(0x0, "gpio_in"), 689 SUNXI_FUNCTION(0x0, "gpio_in"),
635 SUNXI_FUNCTION(0x1, "gpio_out"), 690 SUNXI_FUNCTION(0x1, "gpio_out"),
636 SUNXI_FUNCTION(0x2, "mmc1")), /* D0 */ 691 SUNXI_FUNCTION(0x2, "mmc1"), /* D0 */
692 SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 2)), /* PG_EINT2 */
637 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 3), 693 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 3),
638 SUNXI_FUNCTION(0x0, "gpio_in"), 694 SUNXI_FUNCTION(0x0, "gpio_in"),
639 SUNXI_FUNCTION(0x1, "gpio_out"), 695 SUNXI_FUNCTION(0x1, "gpio_out"),
640 SUNXI_FUNCTION(0x2, "mmc1")), /* D1 */ 696 SUNXI_FUNCTION(0x2, "mmc1"), /* D1 */
697 SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 3)), /* PG_EINT3 */
641 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 4), 698 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 4),
642 SUNXI_FUNCTION(0x0, "gpio_in"), 699 SUNXI_FUNCTION(0x0, "gpio_in"),
643 SUNXI_FUNCTION(0x1, "gpio_out"), 700 SUNXI_FUNCTION(0x1, "gpio_out"),
644 SUNXI_FUNCTION(0x2, "mmc1")), /* D2 */ 701 SUNXI_FUNCTION(0x2, "mmc1"), /* D2 */
702 SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 4)), /* PG_EINT4 */
645 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 5), 703 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 5),
646 SUNXI_FUNCTION(0x0, "gpio_in"), 704 SUNXI_FUNCTION(0x0, "gpio_in"),
647 SUNXI_FUNCTION(0x1, "gpio_out"), 705 SUNXI_FUNCTION(0x1, "gpio_out"),
648 SUNXI_FUNCTION(0x2, "mmc1")), /* D3 */ 706 SUNXI_FUNCTION(0x2, "mmc1"), /* D3 */
707 SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 5)), /* PG_EINT5 */
649 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 6), 708 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 6),
650 SUNXI_FUNCTION(0x0, "gpio_in"), 709 SUNXI_FUNCTION(0x0, "gpio_in"),
651 SUNXI_FUNCTION(0x1, "gpio_out"), 710 SUNXI_FUNCTION(0x1, "gpio_out"),
652 SUNXI_FUNCTION(0x2, "uart2")), /* TX */ 711 SUNXI_FUNCTION(0x2, "uart2"), /* TX */
712 SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 6)), /* PG_EINT6 */
653 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 7), 713 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 7),
654 SUNXI_FUNCTION(0x0, "gpio_in"), 714 SUNXI_FUNCTION(0x0, "gpio_in"),
655 SUNXI_FUNCTION(0x1, "gpio_out"), 715 SUNXI_FUNCTION(0x1, "gpio_out"),
656 SUNXI_FUNCTION(0x2, "uart2")), /* RX */ 716 SUNXI_FUNCTION(0x2, "uart2"), /* RX */
717 SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 7)), /* PG_EINT7 */
657 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 8), 718 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 8),
658 SUNXI_FUNCTION(0x0, "gpio_in"), 719 SUNXI_FUNCTION(0x0, "gpio_in"),
659 SUNXI_FUNCTION(0x1, "gpio_out"), 720 SUNXI_FUNCTION(0x1, "gpio_out"),
660 SUNXI_FUNCTION(0x2, "uart2")), /* RTS */ 721 SUNXI_FUNCTION(0x2, "uart2"), /* RTS */
722 SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 8)), /* PG_EINT8 */
661 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 9), 723 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 9),
662 SUNXI_FUNCTION(0x0, "gpio_in"), 724 SUNXI_FUNCTION(0x0, "gpio_in"),
663 SUNXI_FUNCTION(0x1, "gpio_out"), 725 SUNXI_FUNCTION(0x1, "gpio_out"),
664 SUNXI_FUNCTION(0x2, "uart2")), /* CTS */ 726 SUNXI_FUNCTION(0x2, "uart2"), /* CTS */
727 SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 9)), /* PG_EINT9 */
665 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 10), 728 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 10),
666 SUNXI_FUNCTION(0x0, "gpio_in"), 729 SUNXI_FUNCTION(0x0, "gpio_in"),
667 SUNXI_FUNCTION(0x1, "gpio_out"), 730 SUNXI_FUNCTION(0x1, "gpio_out"),
668 SUNXI_FUNCTION(0x2, "i2c3"), /* SCK */ 731 SUNXI_FUNCTION(0x2, "i2c3"), /* SCK */
669 SUNXI_FUNCTION(0x3, "usb")), /* DP3 */ 732 SUNXI_FUNCTION(0x3, "usb"), /* DP3 */
733 SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 10)), /* PG_EINT10 */
670 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 11), 734 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 11),
671 SUNXI_FUNCTION(0x0, "gpio_in"), 735 SUNXI_FUNCTION(0x0, "gpio_in"),
672 SUNXI_FUNCTION(0x1, "gpio_out"), 736 SUNXI_FUNCTION(0x1, "gpio_out"),
673 SUNXI_FUNCTION(0x2, "i2c3"), /* SDA */ 737 SUNXI_FUNCTION(0x2, "i2c3"), /* SDA */
674 SUNXI_FUNCTION(0x3, "usb")), /* DM3 */ 738 SUNXI_FUNCTION(0x3, "usb"), /* DM3 */
739 SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 11)), /* PG_EINT11 */
675 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 12), 740 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 12),
676 SUNXI_FUNCTION(0x0, "gpio_in"), 741 SUNXI_FUNCTION(0x0, "gpio_in"),
677 SUNXI_FUNCTION(0x1, "gpio_out"), 742 SUNXI_FUNCTION(0x1, "gpio_out"),
678 SUNXI_FUNCTION(0x2, "spi1"), /* CS1 */ 743 SUNXI_FUNCTION(0x2, "spi1"), /* CS1 */
679 SUNXI_FUNCTION(0x3, "i2s1")), /* MCLK */ 744 SUNXI_FUNCTION(0x3, "i2s1"), /* MCLK */
745 SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 12)), /* PG_EINT12 */
680 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 13), 746 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 13),
681 SUNXI_FUNCTION(0x0, "gpio_in"), 747 SUNXI_FUNCTION(0x0, "gpio_in"),
682 SUNXI_FUNCTION(0x1, "gpio_out"), 748 SUNXI_FUNCTION(0x1, "gpio_out"),
683 SUNXI_FUNCTION(0x2, "spi1"), /* CS0 */ 749 SUNXI_FUNCTION(0x2, "spi1"), /* CS0 */
684 SUNXI_FUNCTION(0x3, "i2s1")), /* BCLK */ 750 SUNXI_FUNCTION(0x3, "i2s1"), /* BCLK */
751 SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 13)), /* PG_EINT13 */
685 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 14), 752 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 14),
686 SUNXI_FUNCTION(0x0, "gpio_in"), 753 SUNXI_FUNCTION(0x0, "gpio_in"),
687 SUNXI_FUNCTION(0x1, "gpio_out"), 754 SUNXI_FUNCTION(0x1, "gpio_out"),
688 SUNXI_FUNCTION(0x2, "spi1"), /* CLK */ 755 SUNXI_FUNCTION(0x2, "spi1"), /* CLK */
689 SUNXI_FUNCTION(0x3, "i2s1")), /* LRCK */ 756 SUNXI_FUNCTION(0x3, "i2s1"), /* LRCK */
757 SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 14)), /* PG_EINT14 */
690 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 15), 758 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 15),
691 SUNXI_FUNCTION(0x0, "gpio_in"), 759 SUNXI_FUNCTION(0x0, "gpio_in"),
692 SUNXI_FUNCTION(0x1, "gpio_out"), 760 SUNXI_FUNCTION(0x1, "gpio_out"),
693 SUNXI_FUNCTION(0x2, "spi1"), /* MOSI */ 761 SUNXI_FUNCTION(0x2, "spi1"), /* MOSI */
694 SUNXI_FUNCTION(0x3, "i2s1")), /* DIN */ 762 SUNXI_FUNCTION(0x3, "i2s1"), /* DIN */
763 SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 15)), /* PG_EINT15 */
695 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 16), 764 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 16),
696 SUNXI_FUNCTION(0x0, "gpio_in"), 765 SUNXI_FUNCTION(0x0, "gpio_in"),
697 SUNXI_FUNCTION(0x1, "gpio_out"), 766 SUNXI_FUNCTION(0x1, "gpio_out"),
698 SUNXI_FUNCTION(0x2, "spi1"), /* MISO */ 767 SUNXI_FUNCTION(0x2, "spi1"), /* MISO */
699 SUNXI_FUNCTION(0x3, "i2s1")), /* DOUT */ 768 SUNXI_FUNCTION(0x3, "i2s1"), /* DOUT */
769 SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 16)), /* PG_EINT16 */
700 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 17), 770 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 17),
701 SUNXI_FUNCTION(0x0, "gpio_in"), 771 SUNXI_FUNCTION(0x0, "gpio_in"),
702 SUNXI_FUNCTION(0x1, "gpio_out"), 772 SUNXI_FUNCTION(0x1, "gpio_out"),
703 SUNXI_FUNCTION(0x2, "uart4")), /* TX */ 773 SUNXI_FUNCTION(0x2, "uart4"), /* TX */
774 SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 17)), /* PG_EINT17 */
704 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 18), 775 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 18),
705 SUNXI_FUNCTION(0x0, "gpio_in"), 776 SUNXI_FUNCTION(0x0, "gpio_in"),
706 SUNXI_FUNCTION(0x1, "gpio_out"), 777 SUNXI_FUNCTION(0x1, "gpio_out"),
707 SUNXI_FUNCTION(0x2, "uart4")), /* RX */ 778 SUNXI_FUNCTION(0x2, "uart4"), /* RX */
779 SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 18)), /* PG_EINT18 */
708 /* Hole */ 780 /* Hole */
709 SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 0), 781 SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 0),
710 SUNXI_FUNCTION(0x0, "gpio_in"), 782 SUNXI_FUNCTION(0x0, "gpio_in"),
@@ -836,6 +908,7 @@ static const struct sunxi_desc_pin sun6i_a31_pins[] = {
836static const struct sunxi_pinctrl_desc sun6i_a31_pinctrl_data = { 908static const struct sunxi_pinctrl_desc sun6i_a31_pinctrl_data = {
837 .pins = sun6i_a31_pins, 909 .pins = sun6i_a31_pins,
838 .npins = ARRAY_SIZE(sun6i_a31_pins), 910 .npins = ARRAY_SIZE(sun6i_a31_pins),
911 .irq_banks = 4,
839}; 912};
840 913
841static int sun6i_a31_pinctrl_probe(struct platform_device *pdev) 914static int sun6i_a31_pinctrl_probe(struct platform_device *pdev)
diff --git a/drivers/pinctrl/sunxi/pinctrl-sun7i-a20.c b/drivers/pinctrl/sunxi/pinctrl-sun7i-a20.c
index d8577ce5f1a4..dac99e02bfdb 100644
--- a/drivers/pinctrl/sunxi/pinctrl-sun7i-a20.c
+++ b/drivers/pinctrl/sunxi/pinctrl-sun7i-a20.c
@@ -1036,6 +1036,7 @@ static const struct sunxi_desc_pin sun7i_a20_pins[] = {
1036static const struct sunxi_pinctrl_desc sun7i_a20_pinctrl_data = { 1036static const struct sunxi_pinctrl_desc sun7i_a20_pinctrl_data = {
1037 .pins = sun7i_a20_pins, 1037 .pins = sun7i_a20_pins,
1038 .npins = ARRAY_SIZE(sun7i_a20_pins), 1038 .npins = ARRAY_SIZE(sun7i_a20_pins),
1039 .irq_banks = 1,
1039}; 1040};
1040 1041
1041static int sun7i_a20_pinctrl_probe(struct platform_device *pdev) 1042static int sun7i_a20_pinctrl_probe(struct platform_device *pdev)
diff --git a/drivers/pinctrl/sunxi/pinctrl-sun8i-a23-r.c b/drivers/pinctrl/sunxi/pinctrl-sun8i-a23-r.c
new file mode 100644
index 000000000000..90f3b3a7c51e
--- /dev/null
+++ b/drivers/pinctrl/sunxi/pinctrl-sun8i-a23-r.c
@@ -0,0 +1,142 @@
1/*
2 * Allwinner A23 SoCs special pins pinctrl driver.
3 *
4 * Copyright (C) 2014 Chen-Yu Tsai
5 * Chen-Yu Tsai <wens@csie.org>
6 *
7 * Copyright (C) 2014 Boris Brezillon
8 * Boris Brezillon <boris.brezillon@free-electrons.com>
9 *
10 * Copyright (C) 2014 Maxime Ripard
11 * Maxime Ripard <maxime.ripard@free-electrons.com>
12 *
13 * This file is licensed under the terms of the GNU General Public
14 * License version 2. This program is licensed "as is" without any
15 * warranty of any kind, whether express or implied.
16 */
17
18#include <linux/module.h>
19#include <linux/platform_device.h>
20#include <linux/of.h>
21#include <linux/of_device.h>
22#include <linux/pinctrl/pinctrl.h>
23#include <linux/reset.h>
24
25#include "pinctrl-sunxi.h"
26
27static const struct sunxi_desc_pin sun8i_a23_r_pins[] = {
28 SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 0),
29 SUNXI_FUNCTION(0x0, "gpio_in"),
30 SUNXI_FUNCTION(0x1, "gpio_out"),
31 SUNXI_FUNCTION(0x2, "s_rsb"), /* SCK */
32 SUNXI_FUNCTION(0x3, "s_twi"), /* SCK */
33 SUNXI_FUNCTION_IRQ_BANK(0x4, 0, 0)), /* PL_EINT0 */
34 SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 1),
35 SUNXI_FUNCTION(0x0, "gpio_in"),
36 SUNXI_FUNCTION(0x1, "gpio_out"),
37 SUNXI_FUNCTION(0x2, "s_rsb"), /* SDA */
38 SUNXI_FUNCTION(0x3, "s_twi"), /* SDA */
39 SUNXI_FUNCTION_IRQ_BANK(0x4, 0, 1)), /* PL_EINT1 */
40 SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 2),
41 SUNXI_FUNCTION(0x0, "gpio_in"),
42 SUNXI_FUNCTION(0x1, "gpio_out"),
43 SUNXI_FUNCTION(0x2, "s_uart"), /* TX */
44 SUNXI_FUNCTION_IRQ_BANK(0x4, 0, 2)), /* PL_EINT2 */
45 SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 3),
46 SUNXI_FUNCTION(0x0, "gpio_in"),
47 SUNXI_FUNCTION(0x1, "gpio_out"),
48 SUNXI_FUNCTION(0x2, "s_uart"), /* RX */
49 SUNXI_FUNCTION_IRQ_BANK(0x4, 0, 3)), /* PL_EINT3 */
50 SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 4),
51 SUNXI_FUNCTION(0x0, "gpio_in"),
52 SUNXI_FUNCTION(0x1, "gpio_out"),
53 SUNXI_FUNCTION(0x3, "s_jtag"), /* MS */
54 SUNXI_FUNCTION_IRQ_BANK(0x4, 0, 4)), /* PL_EINT4 */
55 SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 5),
56 SUNXI_FUNCTION(0x0, "gpio_in"),
57 SUNXI_FUNCTION(0x1, "gpio_out"),
58 SUNXI_FUNCTION(0x3, "s_jtag"), /* CK */
59 SUNXI_FUNCTION_IRQ_BANK(0x4, 0, 5)), /* PL_EINT5 */
60 SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 6),
61 SUNXI_FUNCTION(0x0, "gpio_in"),
62 SUNXI_FUNCTION(0x1, "gpio_out"),
63 SUNXI_FUNCTION(0x3, "s_jtag"), /* DO */
64 SUNXI_FUNCTION_IRQ_BANK(0x4, 0, 6)), /* PL_EINT6 */
65 SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 7),
66 SUNXI_FUNCTION(0x0, "gpio_in"),
67 SUNXI_FUNCTION(0x1, "gpio_out"),
68 SUNXI_FUNCTION(0x3, "s_jtag"), /* DI */
69 SUNXI_FUNCTION_IRQ_BANK(0x4, 0, 7)), /* PL_EINT7 */
70 SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 8),
71 SUNXI_FUNCTION(0x0, "gpio_in"),
72 SUNXI_FUNCTION(0x1, "gpio_out"),
73 SUNXI_FUNCTION(0x2, "s_twi"), /* SCK */
74 SUNXI_FUNCTION_IRQ_BANK(0x4, 0, 8)), /* PL_EINT8 */
75 SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 9),
76 SUNXI_FUNCTION(0x0, "gpio_in"),
77 SUNXI_FUNCTION(0x1, "gpio_out"),
78 SUNXI_FUNCTION(0x2, "s_twi"), /* SDA */
79 SUNXI_FUNCTION_IRQ_BANK(0x4, 0, 9)), /* PL_EINT9 */
80 SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 10),
81 SUNXI_FUNCTION(0x0, "gpio_in"),
82 SUNXI_FUNCTION(0x1, "gpio_out"),
83 SUNXI_FUNCTION(0x2, "s_pwm"),
84 SUNXI_FUNCTION_IRQ_BANK(0x4, 0, 10)), /* PL_EINT10 */
85 SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 11),
86 SUNXI_FUNCTION(0x0, "gpio_in"),
87 SUNXI_FUNCTION(0x1, "gpio_out"),
88 SUNXI_FUNCTION_IRQ_BANK(0x4, 0, 11)), /* PL_EINT11 */
89};
90
91static const struct sunxi_pinctrl_desc sun8i_a23_r_pinctrl_data = {
92 .pins = sun8i_a23_r_pins,
93 .npins = ARRAY_SIZE(sun8i_a23_r_pins),
94 .pin_base = PL_BASE,
95 .irq_banks = 1,
96};
97
98static int sun8i_a23_r_pinctrl_probe(struct platform_device *pdev)
99{
100 struct reset_control *rstc;
101 int ret;
102
103 rstc = devm_reset_control_get(&pdev->dev, NULL);
104 if (IS_ERR(rstc)) {
105 dev_err(&pdev->dev, "Reset controller missing\n");
106 return PTR_ERR(rstc);
107 }
108
109 ret = reset_control_deassert(rstc);
110 if (ret)
111 return ret;
112
113 ret = sunxi_pinctrl_init(pdev,
114 &sun8i_a23_r_pinctrl_data);
115
116 if (ret)
117 reset_control_assert(rstc);
118
119 return ret;
120}
121
122static struct of_device_id sun8i_a23_r_pinctrl_match[] = {
123 { .compatible = "allwinner,sun8i-a23-r-pinctrl", },
124 {}
125};
126MODULE_DEVICE_TABLE(of, sun8i_a23_r_pinctrl_match);
127
128static struct platform_driver sun8i_a23_r_pinctrl_driver = {
129 .probe = sun8i_a23_r_pinctrl_probe,
130 .driver = {
131 .name = "sun8i-a23-r-pinctrl",
132 .owner = THIS_MODULE,
133 .of_match_table = sun8i_a23_r_pinctrl_match,
134 },
135};
136module_platform_driver(sun8i_a23_r_pinctrl_driver);
137
138MODULE_AUTHOR("Chen-Yu Tsai <wens@csie.org>");
139MODULE_AUTHOR("Boris Brezillon <boris.brezillon@free-electrons.com");
140MODULE_AUTHOR("Maxime Ripard <maxime.ripard@free-electrons.com");
141MODULE_DESCRIPTION("Allwinner A23 R_PIO pinctrl driver");
142MODULE_LICENSE("GPL");
diff --git a/drivers/pinctrl/sunxi/pinctrl-sun8i-a23.c b/drivers/pinctrl/sunxi/pinctrl-sun8i-a23.c
new file mode 100644
index 000000000000..ac71e8c5901b
--- /dev/null
+++ b/drivers/pinctrl/sunxi/pinctrl-sun8i-a23.c
@@ -0,0 +1,593 @@
1/*
2 * Allwinner A23 SoCs pinctrl driver.
3 *
4 * Copyright (C) 2014 Chen-Yu Tsai
5 *
6 * Chen-Yu Tsai <wens@csie.org>
7 *
8 * Copyright (C) 2014 Maxime Ripard
9 *
10 * Maxime Ripard <maxime.ripard@free-electrons.com>
11 *
12 * This file is licensed under the terms of the GNU General Public
13 * License version 2. This program is licensed "as is" without any
14 * warranty of any kind, whether express or implied.
15 */
16
17#include <linux/module.h>
18#include <linux/platform_device.h>
19#include <linux/of.h>
20#include <linux/of_device.h>
21#include <linux/pinctrl/pinctrl.h>
22
23#include "pinctrl-sunxi.h"
24
25static const struct sunxi_desc_pin sun8i_a23_pins[] = {
26 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 0),
27 SUNXI_FUNCTION(0x0, "gpio_in"),
28 SUNXI_FUNCTION(0x1, "gpio_out"),
29 SUNXI_FUNCTION(0x2, "spi1"), /* CS */
30 SUNXI_FUNCTION(0x3, "jtag"), /* MS0 */
31 SUNXI_FUNCTION_IRQ_BANK(0x4, 0, 0)), /* PA_EINT0 */
32 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 1),
33 SUNXI_FUNCTION(0x0, "gpio_in"),
34 SUNXI_FUNCTION(0x1, "gpio_out"),
35 SUNXI_FUNCTION(0x2, "spi1"), /* CLK */
36 SUNXI_FUNCTION(0x3, "jtag"), /* CKO */
37 SUNXI_FUNCTION_IRQ_BANK(0x4, 0, 1)), /* PA_EINT1 */
38 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 2),
39 SUNXI_FUNCTION(0x0, "gpio_in"),
40 SUNXI_FUNCTION(0x1, "gpio_out"),
41 SUNXI_FUNCTION(0x2, "spi1"), /* MOSI */
42 SUNXI_FUNCTION(0x3, "jtag"), /* DOO */
43 SUNXI_FUNCTION_IRQ_BANK(0x4, 0, 2)), /* PA_EINT2 */
44 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 3),
45 SUNXI_FUNCTION(0x0, "gpio_in"),
46 SUNXI_FUNCTION(0x1, "gpio_out"),
47 SUNXI_FUNCTION(0x2, "spi1"), /* MISO */
48 SUNXI_FUNCTION(0x3, "jtag"), /* DIO */
49 SUNXI_FUNCTION_IRQ_BANK(0x4, 0, 3)), /* PA_EINT3 */
50 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 4),
51 SUNXI_FUNCTION(0x0, "gpio_in"),
52 SUNXI_FUNCTION(0x1, "gpio_out"),
53 SUNXI_FUNCTION(0x2, "uart4"), /* TX */
54 SUNXI_FUNCTION_IRQ_BANK(0x4, 0, 4)), /* PA_EINT4 */
55 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 5),
56 SUNXI_FUNCTION(0x0, "gpio_in"),
57 SUNXI_FUNCTION(0x1, "gpio_out"),
58 SUNXI_FUNCTION(0x2, "uart4"), /* RX */
59 SUNXI_FUNCTION_IRQ_BANK(0x4, 0, 5)), /* PA_EINT5 */
60 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 6),
61 SUNXI_FUNCTION(0x0, "gpio_in"),
62 SUNXI_FUNCTION(0x1, "gpio_out"),
63 SUNXI_FUNCTION(0x2, "uart4"), /* RTS */
64 SUNXI_FUNCTION_IRQ_BANK(0x4, 0, 6)), /* PA_EINT6 */
65 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 7),
66 SUNXI_FUNCTION(0x0, "gpio_in"),
67 SUNXI_FUNCTION(0x1, "gpio_out"),
68 SUNXI_FUNCTION(0x2, "uart4"), /* CTS */
69 SUNXI_FUNCTION_IRQ_BANK(0x4, 0, 7)), /* PA_EINT7 */
70 /* Hole */
71 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 0),
72 SUNXI_FUNCTION(0x0, "gpio_in"),
73 SUNXI_FUNCTION(0x1, "gpio_out"),
74 SUNXI_FUNCTION(0x2, "uart2"), /* TX */
75 SUNXI_FUNCTION_IRQ_BANK(0x4, 1, 0)), /* PB_EINT0 */
76 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 1),
77 SUNXI_FUNCTION(0x0, "gpio_in"),
78 SUNXI_FUNCTION(0x1, "gpio_out"),
79 SUNXI_FUNCTION(0x2, "uart2"), /* RX */
80 SUNXI_FUNCTION_IRQ_BANK(0x4, 1, 1)), /* PB_EINT1 */
81 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 2),
82 SUNXI_FUNCTION(0x0, "gpio_in"),
83 SUNXI_FUNCTION(0x1, "gpio_out"),
84 SUNXI_FUNCTION(0x2, "uart2"), /* RTS */
85 SUNXI_FUNCTION_IRQ_BANK(0x4, 1, 2)), /* PB_EINT2 */
86 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 3),
87 SUNXI_FUNCTION(0x0, "gpio_in"),
88 SUNXI_FUNCTION(0x1, "gpio_out"),
89 SUNXI_FUNCTION(0x2, "uart2"), /* CTS */
90 SUNXI_FUNCTION_IRQ_BANK(0x4, 1, 3)), /* PB_EINT3 */
91 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 4),
92 SUNXI_FUNCTION(0x0, "gpio_in"),
93 SUNXI_FUNCTION(0x1, "gpio_out"),
94 SUNXI_FUNCTION(0x2, "i2s0"), /* SYNC */
95 SUNXI_FUNCTION_IRQ_BANK(0x4, 1, 4)), /* PB_EINT4 */
96 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 5),
97 SUNXI_FUNCTION(0x0, "gpio_in"),
98 SUNXI_FUNCTION(0x1, "gpio_out"),
99 SUNXI_FUNCTION(0x2, "i2s0"), /* DOUT */
100 SUNXI_FUNCTION_IRQ_BANK(0x4, 1, 5)), /* PB_EINT5 */
101 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 6),
102 SUNXI_FUNCTION(0x0, "gpio_in"),
103 SUNXI_FUNCTION(0x1, "gpio_out"),
104 SUNXI_FUNCTION(0x2, "i2s0"), /* DIN */
105 SUNXI_FUNCTION_IRQ_BANK(0x4, 1, 6)), /* PB_EINT6 */
106 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 7),
107 SUNXI_FUNCTION(0x0, "gpio_in"),
108 SUNXI_FUNCTION(0x1, "gpio_out"),
109 SUNXI_FUNCTION(0x3, "i2s0"), /* DI */
110 SUNXI_FUNCTION_IRQ_BANK(0x4, 1, 7)), /* PB_EINT7 */
111 /* Hole */
112 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 0),
113 SUNXI_FUNCTION(0x0, "gpio_in"),
114 SUNXI_FUNCTION(0x1, "gpio_out"),
115 SUNXI_FUNCTION(0x2, "nand0"), /* WE */
116 SUNXI_FUNCTION(0x3, "spi0")), /* MOSI */
117 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 1),
118 SUNXI_FUNCTION(0x0, "gpio_in"),
119 SUNXI_FUNCTION(0x1, "gpio_out"),
120 SUNXI_FUNCTION(0x2, "nand0"), /* ALE */
121 SUNXI_FUNCTION(0x3, "spi0")), /* MISO */
122 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 2),
123 SUNXI_FUNCTION(0x0, "gpio_in"),
124 SUNXI_FUNCTION(0x1, "gpio_out"),
125 SUNXI_FUNCTION(0x2, "nand0"), /* CLE */
126 SUNXI_FUNCTION(0x3, "spi0")), /* CLK */
127 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 3),
128 SUNXI_FUNCTION(0x0, "gpio_in"),
129 SUNXI_FUNCTION(0x1, "gpio_out"),
130 SUNXI_FUNCTION(0x2, "nand0"), /* CE1 */
131 SUNXI_FUNCTION(0x3, "spi0")), /* CS */
132 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 4),
133 SUNXI_FUNCTION(0x0, "gpio_in"),
134 SUNXI_FUNCTION(0x1, "gpio_out"),
135 SUNXI_FUNCTION(0x2, "nand0")), /* CE0 */
136 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 5),
137 SUNXI_FUNCTION(0x0, "gpio_in"),
138 SUNXI_FUNCTION(0x1, "gpio_out"),
139 SUNXI_FUNCTION(0x2, "nand0"), /* RE */
140 SUNXI_FUNCTION(0x3, "mmc2")), /* CLK */
141 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 6),
142 SUNXI_FUNCTION(0x0, "gpio_in"),
143 SUNXI_FUNCTION(0x1, "gpio_out"),
144 SUNXI_FUNCTION(0x2, "nand0"), /* RB0 */
145 SUNXI_FUNCTION(0x3, "mmc2")), /* CMD */
146 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 7),
147 SUNXI_FUNCTION(0x0, "gpio_in"),
148 SUNXI_FUNCTION(0x1, "gpio_out"),
149 SUNXI_FUNCTION(0x2, "nand0")), /* RB1 */
150 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 8),
151 SUNXI_FUNCTION(0x0, "gpio_in"),
152 SUNXI_FUNCTION(0x1, "gpio_out"),
153 SUNXI_FUNCTION(0x2, "nand0"), /* DQ0 */
154 SUNXI_FUNCTION(0x3, "mmc2")), /* D0 */
155 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 9),
156 SUNXI_FUNCTION(0x0, "gpio_in"),
157 SUNXI_FUNCTION(0x1, "gpio_out"),
158 SUNXI_FUNCTION(0x2, "nand0"), /* DQ1 */
159 SUNXI_FUNCTION(0x3, "mmc2")), /* D1 */
160 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 10),
161 SUNXI_FUNCTION(0x0, "gpio_in"),
162 SUNXI_FUNCTION(0x1, "gpio_out"),
163 SUNXI_FUNCTION(0x2, "nand0"), /* DQ2 */
164 SUNXI_FUNCTION(0x3, "mmc2")), /* D2 */
165 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 11),
166 SUNXI_FUNCTION(0x0, "gpio_in"),
167 SUNXI_FUNCTION(0x1, "gpio_out"),
168 SUNXI_FUNCTION(0x2, "nand0"), /* DQ3 */
169 SUNXI_FUNCTION(0x3, "mmc2")), /* D3 */
170 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 12),
171 SUNXI_FUNCTION(0x0, "gpio_in"),
172 SUNXI_FUNCTION(0x1, "gpio_out"),
173 SUNXI_FUNCTION(0x2, "nand0"), /* DQ4 */
174 SUNXI_FUNCTION(0x3, "mmc2")), /* D4 */
175 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 13),
176 SUNXI_FUNCTION(0x0, "gpio_in"),
177 SUNXI_FUNCTION(0x1, "gpio_out"),
178 SUNXI_FUNCTION(0x2, "nand0"), /* DQ5 */
179 SUNXI_FUNCTION(0x3, "mmc2")), /* D5 */
180 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 14),
181 SUNXI_FUNCTION(0x0, "gpio_in"),
182 SUNXI_FUNCTION(0x1, "gpio_out"),
183 SUNXI_FUNCTION(0x2, "nand"), /* DQ6 */
184 SUNXI_FUNCTION(0x3, "mmc2")), /* D6 */
185 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 15),
186 SUNXI_FUNCTION(0x0, "gpio_in"),
187 SUNXI_FUNCTION(0x1, "gpio_out"),
188 SUNXI_FUNCTION(0x2, "nand"), /* DQ7 */
189 SUNXI_FUNCTION(0x3, "mmc2")), /* D7 */
190 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 16),
191 SUNXI_FUNCTION(0x0, "gpio_in"),
192 SUNXI_FUNCTION(0x1, "gpio_out"),
193 SUNXI_FUNCTION(0x2, "nand"), /* DQS */
194 SUNXI_FUNCTION(0x3, "mmc2")), /* RST */
195 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 17),
196 SUNXI_FUNCTION(0x0, "gpio_in"),
197 SUNXI_FUNCTION(0x1, "gpio_out"),
198 SUNXI_FUNCTION(0x2, "nand0")), /* CE2 */
199 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 18),
200 SUNXI_FUNCTION(0x0, "gpio_in"),
201 SUNXI_FUNCTION(0x1, "gpio_out"),
202 SUNXI_FUNCTION(0x2, "nand0")), /* CE3 */
203 /* Hole */
204 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 0),
205 SUNXI_FUNCTION(0x0, "gpio_in"),
206 SUNXI_FUNCTION(0x1, "gpio_out"),
207 SUNXI_FUNCTION(0x2, "lcd0")), /* D0 */
208 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 1),
209 SUNXI_FUNCTION(0x0, "gpio_in"),
210 SUNXI_FUNCTION(0x1, "gpio_out"),
211 SUNXI_FUNCTION(0x2, "lcd0")), /* D1 */
212 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 2),
213 SUNXI_FUNCTION(0x0, "gpio_in"),
214 SUNXI_FUNCTION(0x1, "gpio_out"),
215 SUNXI_FUNCTION(0x2, "lcd0"), /* D2 */
216 SUNXI_FUNCTION(0x3, "mmc1")), /* CLK */
217 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 3),
218 SUNXI_FUNCTION(0x0, "gpio_in"),
219 SUNXI_FUNCTION(0x1, "gpio_out"),
220 SUNXI_FUNCTION(0x2, "lcd0"), /* D3 */
221 SUNXI_FUNCTION(0x3, "mmc1")), /* CMD */
222 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 4),
223 SUNXI_FUNCTION(0x0, "gpio_in"),
224 SUNXI_FUNCTION(0x1, "gpio_out"),
225 SUNXI_FUNCTION(0x2, "lcd0"), /* D4 */
226 SUNXI_FUNCTION(0x3, "mmc1")), /* D0 */
227 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 5),
228 SUNXI_FUNCTION(0x0, "gpio_in"),
229 SUNXI_FUNCTION(0x1, "gpio_out"),
230 SUNXI_FUNCTION(0x2, "lcd0"), /* D5 */
231 SUNXI_FUNCTION(0x3, "mmc1")), /* D1 */
232 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 6),
233 SUNXI_FUNCTION(0x0, "gpio_in"),
234 SUNXI_FUNCTION(0x1, "gpio_out"),
235 SUNXI_FUNCTION(0x2, "lcd0"), /* D6 */
236 SUNXI_FUNCTION(0x3, "mmc1")), /* D2 */
237 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 7),
238 SUNXI_FUNCTION(0x0, "gpio_in"),
239 SUNXI_FUNCTION(0x1, "gpio_out"),
240 SUNXI_FUNCTION(0x2, "lcd0"), /* D7 */
241 SUNXI_FUNCTION(0x3, "mmc1")), /* D3 */
242 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 8),
243 SUNXI_FUNCTION(0x0, "gpio_in"),
244 SUNXI_FUNCTION(0x1, "gpio_out"),
245 SUNXI_FUNCTION(0x2, "lcd0"), /* D8 */
246 SUNXI_FUNCTION(0x3, "uart3")), /* TX */
247 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 9),
248 SUNXI_FUNCTION(0x0, "gpio_in"),
249 SUNXI_FUNCTION(0x1, "gpio_out"),
250 SUNXI_FUNCTION(0x2, "lcd0"), /* D9 */
251 SUNXI_FUNCTION(0x3, "uart3")), /* RX */
252 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 10),
253 SUNXI_FUNCTION(0x0, "gpio_in"),
254 SUNXI_FUNCTION(0x1, "gpio_out"),
255 SUNXI_FUNCTION(0x2, "lcd0"), /* D10 */
256 SUNXI_FUNCTION(0x3, "uart1")), /* TX */
257 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 11),
258 SUNXI_FUNCTION(0x0, "gpio_in"),
259 SUNXI_FUNCTION(0x1, "gpio_out"),
260 SUNXI_FUNCTION(0x2, "lcd0"), /* D11 */
261 SUNXI_FUNCTION(0x3, "uart1")), /* RX */
262 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 12),
263 SUNXI_FUNCTION(0x0, "gpio_in"),
264 SUNXI_FUNCTION(0x1, "gpio_out"),
265 SUNXI_FUNCTION(0x2, "lcd0"), /* D12 */
266 SUNXI_FUNCTION(0x3, "uart1")), /* RTS */
267 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 13),
268 SUNXI_FUNCTION(0x0, "gpio_in"),
269 SUNXI_FUNCTION(0x1, "gpio_out"),
270 SUNXI_FUNCTION(0x2, "lcd0"), /* D13 */
271 SUNXI_FUNCTION(0x3, "uart1")), /* CTS */
272 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 14),
273 SUNXI_FUNCTION(0x0, "gpio_in"),
274 SUNXI_FUNCTION(0x1, "gpio_out"),
275 SUNXI_FUNCTION(0x2, "lcd0"), /* D14 */
276 SUNXI_FUNCTION(0x3, "i2s1")), /* SYNC */
277 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 15),
278 SUNXI_FUNCTION(0x0, "gpio_in"),
279 SUNXI_FUNCTION(0x1, "gpio_out"),
280 SUNXI_FUNCTION(0x2, "lcd0"), /* D15 */
281 SUNXI_FUNCTION(0x3, "i2s1")), /* CLK */
282 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 16),
283 SUNXI_FUNCTION(0x0, "gpio_in"),
284 SUNXI_FUNCTION(0x1, "gpio_out"),
285 SUNXI_FUNCTION(0x2, "lcd0"), /* D16 */
286 SUNXI_FUNCTION(0x3, "i2s1")), /* DOUT */
287 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 17),
288 SUNXI_FUNCTION(0x0, "gpio_in"),
289 SUNXI_FUNCTION(0x1, "gpio_out"),
290 SUNXI_FUNCTION(0x2, "lcd0"), /* D17 */
291 SUNXI_FUNCTION(0x3, "i2s1")), /* DIN */
292 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 18),
293 SUNXI_FUNCTION(0x0, "gpio_in"),
294 SUNXI_FUNCTION(0x1, "gpio_out"),
295 SUNXI_FUNCTION(0x2, "lcd0"), /* D18 */
296 SUNXI_FUNCTION(0x3, "lvds0")), /* VN0 */
297 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 19),
298 SUNXI_FUNCTION(0x0, "gpio_in"),
299 SUNXI_FUNCTION(0x1, "gpio_out"),
300 SUNXI_FUNCTION(0x2, "lcd0"), /* D19 */
301 SUNXI_FUNCTION(0x3, "lvds0")), /* VP0 */
302 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 20),
303 SUNXI_FUNCTION(0x0, "gpio_in"),
304 SUNXI_FUNCTION(0x1, "gpio_out"),
305 SUNXI_FUNCTION(0x2, "lcd0"), /* D20 */
306 SUNXI_FUNCTION(0x3, "lvds0")), /* VP1 */
307 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 21),
308 SUNXI_FUNCTION(0x0, "gpio_in"),
309 SUNXI_FUNCTION(0x1, "gpio_out"),
310 SUNXI_FUNCTION(0x2, "lcd0"), /* D21 */
311 SUNXI_FUNCTION(0x3, "lvds0")), /* VN1 */
312 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 22),
313 SUNXI_FUNCTION(0x0, "gpio_in"),
314 SUNXI_FUNCTION(0x1, "gpio_out"),
315 SUNXI_FUNCTION(0x2, "lcd0"), /* D22 */
316 SUNXI_FUNCTION(0x3, "lvds0")), /* VP2 */
317 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 23),
318 SUNXI_FUNCTION(0x0, "gpio_in"),
319 SUNXI_FUNCTION(0x1, "gpio_out"),
320 SUNXI_FUNCTION(0x2, "lcd0"), /* D23 */
321 SUNXI_FUNCTION(0x3, "lvds0")), /* VN2 */
322 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 24),
323 SUNXI_FUNCTION(0x0, "gpio_in"),
324 SUNXI_FUNCTION(0x1, "gpio_out"),
325 SUNXI_FUNCTION(0x2, "lcd0"), /* CLK */
326 SUNXI_FUNCTION(0x3, "lvds0")), /* VPC */
327 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 25),
328 SUNXI_FUNCTION(0x0, "gpio_in"),
329 SUNXI_FUNCTION(0x1, "gpio_out"),
330 SUNXI_FUNCTION(0x2, "lcd0"), /* DE */
331 SUNXI_FUNCTION(0x3, "lvds0")), /* VNC */
332 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 26),
333 SUNXI_FUNCTION(0x0, "gpio_in"),
334 SUNXI_FUNCTION(0x1, "gpio_out"),
335 SUNXI_FUNCTION(0x2, "lcd0"), /* HSYNC */
336 SUNXI_FUNCTION(0x3, "lvds0")), /* VP3 */
337 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 27),
338 SUNXI_FUNCTION(0x0, "gpio_in"),
339 SUNXI_FUNCTION(0x1, "gpio_out"),
340 SUNXI_FUNCTION(0x2, "lcd0"), /* VSYNC */
341 SUNXI_FUNCTION(0x3, "lvds0")), /* VN3 */
342 /* Hole */
343 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 0),
344 SUNXI_FUNCTION(0x0, "gpio_in"),
345 SUNXI_FUNCTION(0x1, "gpio_out"),
346 SUNXI_FUNCTION(0x2, "csi")), /* PCLK */
347 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 1),
348 SUNXI_FUNCTION(0x0, "gpio_in"),
349 SUNXI_FUNCTION(0x1, "gpio_out"),
350 SUNXI_FUNCTION(0x2, "csi")), /* MCLK */
351 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 2),
352 SUNXI_FUNCTION(0x0, "gpio_in"),
353 SUNXI_FUNCTION(0x1, "gpio_out"),
354 SUNXI_FUNCTION(0x2, "csi")), /* HSYNC */
355 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 3),
356 SUNXI_FUNCTION(0x0, "gpio_in"),
357 SUNXI_FUNCTION(0x1, "gpio_out"),
358 SUNXI_FUNCTION(0x2, "csi")), /* VSYNC */
359 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 4),
360 SUNXI_FUNCTION(0x0, "gpio_in"),
361 SUNXI_FUNCTION(0x1, "gpio_out"),
362 SUNXI_FUNCTION(0x2, "csi")), /* D0 */
363 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 5),
364 SUNXI_FUNCTION(0x0, "gpio_in"),
365 SUNXI_FUNCTION(0x1, "gpio_out"),
366 SUNXI_FUNCTION(0x2, "csi")), /* D1 */
367 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 6),
368 SUNXI_FUNCTION(0x0, "gpio_in"),
369 SUNXI_FUNCTION(0x1, "gpio_out"),
370 SUNXI_FUNCTION(0x2, "csi")), /* D2 */
371 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 7),
372 SUNXI_FUNCTION(0x0, "gpio_in"),
373 SUNXI_FUNCTION(0x1, "gpio_out"),
374 SUNXI_FUNCTION(0x2, "csi")), /* D3 */
375 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 8),
376 SUNXI_FUNCTION(0x0, "gpio_in"),
377 SUNXI_FUNCTION(0x1, "gpio_out"),
378 SUNXI_FUNCTION(0x2, "csi")), /* D4 */
379 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 9),
380 SUNXI_FUNCTION(0x0, "gpio_in"),
381 SUNXI_FUNCTION(0x1, "gpio_out"),
382 SUNXI_FUNCTION(0x2, "csi")), /* D5 */
383 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 10),
384 SUNXI_FUNCTION(0x0, "gpio_in"),
385 SUNXI_FUNCTION(0x1, "gpio_out"),
386 SUNXI_FUNCTION(0x2, "csi")), /* D6 */
387 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 11),
388 SUNXI_FUNCTION(0x0, "gpio_in"),
389 SUNXI_FUNCTION(0x1, "gpio_out"),
390 SUNXI_FUNCTION(0x2, "csi")), /* D7 */
391 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 12),
392 SUNXI_FUNCTION(0x0, "gpio_in"),
393 SUNXI_FUNCTION(0x1, "gpio_out"),
394 SUNXI_FUNCTION(0x2, "csi"), /* SCK */
395 SUNXI_FUNCTION(0x3, "i2c2")), /* SCK */
396 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 13),
397 SUNXI_FUNCTION(0x0, "gpio_in"),
398 SUNXI_FUNCTION(0x1, "gpio_out"),
399 SUNXI_FUNCTION(0x2, "csi"), /* SDA */
400 SUNXI_FUNCTION(0x3, "i2c2")), /* SDA */
401 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 14),
402 SUNXI_FUNCTION(0x0, "gpio_in"),
403 SUNXI_FUNCTION(0x1, "gpio_out")),
404 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 15),
405 SUNXI_FUNCTION(0x0, "gpio_in"),
406 SUNXI_FUNCTION(0x1, "gpio_out")),
407 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 16),
408 SUNXI_FUNCTION(0x0, "gpio_in"),
409 SUNXI_FUNCTION(0x1, "gpio_out")),
410 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 17),
411 SUNXI_FUNCTION(0x0, "gpio_in"),
412 SUNXI_FUNCTION(0x1, "gpio_out")),
413 /* Hole */
414 SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 0),
415 SUNXI_FUNCTION(0x0, "gpio_in"),
416 SUNXI_FUNCTION(0x1, "gpio_out"),
417 SUNXI_FUNCTION(0x2, "mmc0"), /* D1 */
418 SUNXI_FUNCTION(0x3, "jtag")), /* MS1 */
419 SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 1),
420 SUNXI_FUNCTION(0x0, "gpio_in"),
421 SUNXI_FUNCTION(0x1, "gpio_out"),
422 SUNXI_FUNCTION(0x2, "mmc0"), /* D0 */
423 SUNXI_FUNCTION(0x3, "jtag")), /* DI1 */
424 SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 2),
425 SUNXI_FUNCTION(0x0, "gpio_in"),
426 SUNXI_FUNCTION(0x1, "gpio_out"),
427 SUNXI_FUNCTION(0x2, "mmc0"), /* CLK */
428 SUNXI_FUNCTION(0x3, "uart0")), /* TX */
429 SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 3),
430 SUNXI_FUNCTION(0x0, "gpio_in"),
431 SUNXI_FUNCTION(0x1, "gpio_out"),
432 SUNXI_FUNCTION(0x2, "mmc0"), /* CMD */
433 SUNXI_FUNCTION(0x3, "jtag")), /* DO1 */
434 SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 4),
435 SUNXI_FUNCTION(0x0, "gpio_in"),
436 SUNXI_FUNCTION(0x1, "gpio_out"),
437 SUNXI_FUNCTION(0x2, "mmc0"), /* D3 */
438 SUNXI_FUNCTION(0x3, "uart0")), /* RX */
439 SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 5),
440 SUNXI_FUNCTION(0x0, "gpio_in"),
441 SUNXI_FUNCTION(0x1, "gpio_out"),
442 SUNXI_FUNCTION(0x2, "mmc0"), /* D2 */
443 SUNXI_FUNCTION(0x3, "jtag")), /* CK1 */
444 /* Hole */
445 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 0),
446 SUNXI_FUNCTION(0x0, "gpio_in"),
447 SUNXI_FUNCTION(0x1, "gpio_out"),
448 SUNXI_FUNCTION(0x2, "mmc1"), /* CLK */
449 SUNXI_FUNCTION_IRQ_BANK(0x4, 2, 0)), /* PG_EINT0 */
450 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 1),
451 SUNXI_FUNCTION(0x0, "gpio_in"),
452 SUNXI_FUNCTION(0x1, "gpio_out"),
453 SUNXI_FUNCTION(0x2, "mmc1"), /* CMD */
454 SUNXI_FUNCTION_IRQ_BANK(0x4, 2, 1)), /* PG_EINT1 */
455 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 2),
456 SUNXI_FUNCTION(0x0, "gpio_in"),
457 SUNXI_FUNCTION(0x1, "gpio_out"),
458 SUNXI_FUNCTION(0x2, "mmc1"), /* D0 */
459 SUNXI_FUNCTION_IRQ_BANK(0x4, 2, 2)), /* PG_EINT2 */
460 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 3),
461 SUNXI_FUNCTION(0x0, "gpio_in"),
462 SUNXI_FUNCTION(0x1, "gpio_out"),
463 SUNXI_FUNCTION(0x2, "mmc1"), /* D1 */
464 SUNXI_FUNCTION_IRQ_BANK(0x4, 2, 3)), /* PG_EINT3 */
465 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 4),
466 SUNXI_FUNCTION(0x0, "gpio_in"),
467 SUNXI_FUNCTION(0x1, "gpio_out"),
468 SUNXI_FUNCTION(0x2, "mmc1"), /* D2 */
469 SUNXI_FUNCTION_IRQ_BANK(0x4, 2, 4)), /* PG_EINT4 */
470 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 5),
471 SUNXI_FUNCTION(0x0, "gpio_in"),
472 SUNXI_FUNCTION(0x1, "gpio_out"),
473 SUNXI_FUNCTION(0x2, "mmc1"), /* D3 */
474 SUNXI_FUNCTION_IRQ_BANK(0x4, 2, 5)), /* PG_EINT5 */
475 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 6),
476 SUNXI_FUNCTION(0x0, "gpio_in"),
477 SUNXI_FUNCTION(0x1, "gpio_out"),
478 SUNXI_FUNCTION(0x2, "uart1"), /* TX */
479 SUNXI_FUNCTION_IRQ_BANK(0x4, 2, 6)), /* PG_EINT6 */
480 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 7),
481 SUNXI_FUNCTION(0x0, "gpio_in"),
482 SUNXI_FUNCTION(0x1, "gpio_out"),
483 SUNXI_FUNCTION(0x2, "uart1"), /* RX */
484 SUNXI_FUNCTION_IRQ_BANK(0x4, 2, 7)), /* PG_EINT7 */
485 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 8),
486 SUNXI_FUNCTION(0x0, "gpio_in"),
487 SUNXI_FUNCTION(0x1, "gpio_out"),
488 SUNXI_FUNCTION(0x2, "uart2"), /* RTS */
489 SUNXI_FUNCTION_IRQ_BANK(0x4, 2, 8)), /* PG_EINT8 */
490 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 9),
491 SUNXI_FUNCTION(0x0, "gpio_in"),
492 SUNXI_FUNCTION(0x1, "gpio_out"),
493 SUNXI_FUNCTION(0x2, "uart2"), /* CTS */
494 SUNXI_FUNCTION_IRQ_BANK(0x4, 2, 9)), /* PG_EINT9 */
495 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 10),
496 SUNXI_FUNCTION(0x0, "gpio_in"),
497 SUNXI_FUNCTION(0x1, "gpio_out"),
498 SUNXI_FUNCTION(0x2, "i2s1"), /* SYNC */
499 SUNXI_FUNCTION_IRQ_BANK(0x4, 2, 10)), /* PG_EINT10 */
500 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 11),
501 SUNXI_FUNCTION(0x0, "gpio_in"),
502 SUNXI_FUNCTION(0x1, "gpio_out"),
503 SUNXI_FUNCTION(0x2, "i2s1"), /* CLK */
504 SUNXI_FUNCTION_IRQ_BANK(0x4, 2, 11)), /* PG_EINT11 */
505 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 12),
506 SUNXI_FUNCTION(0x0, "gpio_in"),
507 SUNXI_FUNCTION(0x1, "gpio_out"),
508 SUNXI_FUNCTION(0x2, "i2s1"), /* DOUT */
509 SUNXI_FUNCTION_IRQ_BANK(0x4, 2, 12)), /* PG_EINT12 */
510 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 13),
511 SUNXI_FUNCTION(0x0, "gpio_in"),
512 SUNXI_FUNCTION(0x1, "gpio_out"),
513 SUNXI_FUNCTION(0x2, "i2s1"), /* DIN */
514 SUNXI_FUNCTION_IRQ_BANK(0x4, 2, 13)), /* PG_EINT13 */
515 /* Hole */
516 SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 0),
517 SUNXI_FUNCTION(0x0, "gpio_in"),
518 SUNXI_FUNCTION(0x1, "gpio_out"),
519 SUNXI_FUNCTION(0x2, "pwm0")),
520 SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 1),
521 SUNXI_FUNCTION(0x0, "gpio_in"),
522 SUNXI_FUNCTION(0x1, "gpio_out"),
523 SUNXI_FUNCTION(0x2, "pwm1")),
524 SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 2),
525 SUNXI_FUNCTION(0x0, "gpio_in"),
526 SUNXI_FUNCTION(0x1, "gpio_out"),
527 SUNXI_FUNCTION(0x2, "i2c0")), /* SCK */
528 SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 3),
529 SUNXI_FUNCTION(0x0, "gpio_in"),
530 SUNXI_FUNCTION(0x1, "gpio_out"),
531 SUNXI_FUNCTION(0x2, "i2c0")), /* SDA */
532 SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 4),
533 SUNXI_FUNCTION(0x0, "gpio_in"),
534 SUNXI_FUNCTION(0x1, "gpio_out"),
535 SUNXI_FUNCTION(0x2, "i2c1")), /* SCK */
536 SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 5),
537 SUNXI_FUNCTION(0x0, "gpio_in"),
538 SUNXI_FUNCTION(0x1, "gpio_out"),
539 SUNXI_FUNCTION(0x2, "i2c1")), /* SDA */
540 SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 6),
541 SUNXI_FUNCTION(0x0, "gpio_in"),
542 SUNXI_FUNCTION(0x1, "gpio_out"),
543 SUNXI_FUNCTION(0x2, "spi0"), /* CS */
544 SUNXI_FUNCTION(0x3, "uart3")), /* TX */
545 SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 7),
546 SUNXI_FUNCTION(0x0, "gpio_in"),
547 SUNXI_FUNCTION(0x1, "gpio_out"),
548 SUNXI_FUNCTION(0x2, "spi0"), /* CLK */
549 SUNXI_FUNCTION(0x3, "uart3")), /* RX */
550 SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 8),
551 SUNXI_FUNCTION(0x0, "gpio_in"),
552 SUNXI_FUNCTION(0x1, "gpio_out"),
553 SUNXI_FUNCTION(0x2, "spi0"), /* DOUT */
554 SUNXI_FUNCTION(0x3, "uart3")), /* RTS */
555 SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 9),
556 SUNXI_FUNCTION(0x0, "gpio_in"),
557 SUNXI_FUNCTION(0x1, "gpio_out"),
558 SUNXI_FUNCTION(0x2, "spi0"), /* DIN */
559 SUNXI_FUNCTION(0x3, "uart3")), /* CTS */
560};
561
562static const struct sunxi_pinctrl_desc sun8i_a23_pinctrl_data = {
563 .pins = sun8i_a23_pins,
564 .npins = ARRAY_SIZE(sun8i_a23_pins),
565 .irq_banks = 3,
566};
567
568static int sun8i_a23_pinctrl_probe(struct platform_device *pdev)
569{
570 return sunxi_pinctrl_init(pdev,
571 &sun8i_a23_pinctrl_data);
572}
573
574static struct of_device_id sun8i_a23_pinctrl_match[] = {
575 { .compatible = "allwinner,sun8i-a23-pinctrl", },
576 {}
577};
578MODULE_DEVICE_TABLE(of, sun8i_a23_pinctrl_match);
579
580static struct platform_driver sun8i_a23_pinctrl_driver = {
581 .probe = sun8i_a23_pinctrl_probe,
582 .driver = {
583 .name = "sun8i-a23-pinctrl",
584 .owner = THIS_MODULE,
585 .of_match_table = sun8i_a23_pinctrl_match,
586 },
587};
588module_platform_driver(sun8i_a23_pinctrl_driver);
589
590MODULE_AUTHOR("Chen-Yu Tsai <wens@csie.org>");
591MODULE_AUTHOR("Maxime Ripard <maxime.ripard@free-electrons.com");
592MODULE_DESCRIPTION("Allwinner A23 pinctrl driver");
593MODULE_LICENSE("GPL");
diff --git a/drivers/pinctrl/sunxi/pinctrl-sunxi.c b/drivers/pinctrl/sunxi/pinctrl-sunxi.c
index 5f38c7f67834..ef9d804e55de 100644
--- a/drivers/pinctrl/sunxi/pinctrl-sunxi.c
+++ b/drivers/pinctrl/sunxi/pinctrl-sunxi.c
@@ -31,6 +31,9 @@
31#include "../core.h" 31#include "../core.h"
32#include "pinctrl-sunxi.h" 32#include "pinctrl-sunxi.h"
33 33
34static struct irq_chip sunxi_pinctrl_edge_irq_chip;
35static struct irq_chip sunxi_pinctrl_level_irq_chip;
36
34static struct sunxi_pinctrl_group * 37static struct sunxi_pinctrl_group *
35sunxi_pinctrl_find_group_by_name(struct sunxi_pinctrl *pctl, const char *group) 38sunxi_pinctrl_find_group_by_name(struct sunxi_pinctrl *pctl, const char *group)
36{ 39{
@@ -390,9 +393,9 @@ static void sunxi_pmx_set(struct pinctrl_dev *pctldev,
390 spin_unlock_irqrestore(&pctl->lock, flags); 393 spin_unlock_irqrestore(&pctl->lock, flags);
391} 394}
392 395
393static int sunxi_pmx_enable(struct pinctrl_dev *pctldev, 396static int sunxi_pmx_set_mux(struct pinctrl_dev *pctldev,
394 unsigned function, 397 unsigned function,
395 unsigned group) 398 unsigned group)
396{ 399{
397 struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); 400 struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
398 struct sunxi_pinctrl_group *g = pctl->groups + group; 401 struct sunxi_pinctrl_group *g = pctl->groups + group;
@@ -438,7 +441,7 @@ static const struct pinmux_ops sunxi_pmx_ops = {
438 .get_functions_count = sunxi_pmx_get_funcs_cnt, 441 .get_functions_count = sunxi_pmx_get_funcs_cnt,
439 .get_function_name = sunxi_pmx_get_func_name, 442 .get_function_name = sunxi_pmx_get_func_name,
440 .get_function_groups = sunxi_pmx_get_func_groups, 443 .get_function_groups = sunxi_pmx_get_func_groups,
441 .enable = sunxi_pmx_enable, 444 .set_mux = sunxi_pmx_set_mux,
442 .gpio_set_direction = sunxi_pmx_gpio_set_direction, 445 .gpio_set_direction = sunxi_pmx_gpio_set_direction,
443}; 446};
444 447
@@ -508,7 +511,7 @@ static int sunxi_pinctrl_gpio_of_xlate(struct gpio_chip *gc,
508 base = PINS_PER_BANK * gpiospec->args[0]; 511 base = PINS_PER_BANK * gpiospec->args[0];
509 pin = base + gpiospec->args[1]; 512 pin = base + gpiospec->args[1];
510 513
511 if (pin > (gc->base + gc->ngpio)) 514 if (pin > gc->ngpio)
512 return -EINVAL; 515 return -EINVAL;
513 516
514 if (flags) 517 if (flags)
@@ -521,25 +524,61 @@ static int sunxi_pinctrl_gpio_to_irq(struct gpio_chip *chip, unsigned offset)
521{ 524{
522 struct sunxi_pinctrl *pctl = dev_get_drvdata(chip->dev); 525 struct sunxi_pinctrl *pctl = dev_get_drvdata(chip->dev);
523 struct sunxi_desc_function *desc; 526 struct sunxi_desc_function *desc;
527 unsigned pinnum = pctl->desc->pin_base + offset;
528 unsigned irqnum;
524 529
525 if (offset >= chip->ngpio) 530 if (offset >= chip->ngpio)
526 return -ENXIO; 531 return -ENXIO;
527 532
528 desc = sunxi_pinctrl_desc_find_function_by_pin(pctl, offset, "irq"); 533 desc = sunxi_pinctrl_desc_find_function_by_pin(pctl, pinnum, "irq");
529 if (!desc) 534 if (!desc)
530 return -EINVAL; 535 return -EINVAL;
531 536
537 irqnum = desc->irqbank * IRQ_PER_BANK + desc->irqnum;
538
532 dev_dbg(chip->dev, "%s: request IRQ for GPIO %d, return %d\n", 539 dev_dbg(chip->dev, "%s: request IRQ for GPIO %d, return %d\n",
533 chip->label, offset + chip->base, desc->irqnum); 540 chip->label, offset + chip->base, irqnum);
534 541
535 return irq_find_mapping(pctl->domain, desc->irqnum); 542 return irq_find_mapping(pctl->domain, irqnum);
536} 543}
537 544
545static int sunxi_pinctrl_irq_request_resources(struct irq_data *d)
546{
547 struct sunxi_pinctrl *pctl = irq_data_get_irq_chip_data(d);
548 struct sunxi_desc_function *func;
549 int ret;
550
551 func = sunxi_pinctrl_desc_find_function_by_pin(pctl,
552 pctl->irq_array[d->hwirq], "irq");
553 if (!func)
554 return -EINVAL;
555
556 ret = gpio_lock_as_irq(pctl->chip,
557 pctl->irq_array[d->hwirq] - pctl->desc->pin_base);
558 if (ret) {
559 dev_err(pctl->dev, "unable to lock HW IRQ %lu for IRQ\n",
560 irqd_to_hwirq(d));
561 return ret;
562 }
563
564 /* Change muxing to INT mode */
565 sunxi_pmx_set(pctl->pctl_dev, pctl->irq_array[d->hwirq], func->muxval);
538 566
539static int sunxi_pinctrl_irq_set_type(struct irq_data *d, 567 return 0;
540 unsigned int type) 568}
569
570static void sunxi_pinctrl_irq_release_resources(struct irq_data *d)
571{
572 struct sunxi_pinctrl *pctl = irq_data_get_irq_chip_data(d);
573
574 gpio_unlock_as_irq(pctl->chip,
575 pctl->irq_array[d->hwirq] - pctl->desc->pin_base);
576}
577
578static int sunxi_pinctrl_irq_set_type(struct irq_data *d, unsigned int type)
541{ 579{
542 struct sunxi_pinctrl *pctl = irq_data_get_irq_chip_data(d); 580 struct sunxi_pinctrl *pctl = irq_data_get_irq_chip_data(d);
581 struct irq_desc *desc = container_of(d, struct irq_desc, irq_data);
543 u32 reg = sunxi_irq_cfg_reg(d->hwirq); 582 u32 reg = sunxi_irq_cfg_reg(d->hwirq);
544 u8 index = sunxi_irq_cfg_offset(d->hwirq); 583 u8 index = sunxi_irq_cfg_offset(d->hwirq);
545 unsigned long flags; 584 unsigned long flags;
@@ -566,6 +605,14 @@ static int sunxi_pinctrl_irq_set_type(struct irq_data *d,
566 return -EINVAL; 605 return -EINVAL;
567 } 606 }
568 607
608 if (type & IRQ_TYPE_LEVEL_MASK) {
609 d->chip = &sunxi_pinctrl_level_irq_chip;
610 desc->handle_irq = handle_fasteoi_irq;
611 } else {
612 d->chip = &sunxi_pinctrl_edge_irq_chip;
613 desc->handle_irq = handle_edge_irq;
614 }
615
569 spin_lock_irqsave(&pctl->lock, flags); 616 spin_lock_irqsave(&pctl->lock, flags);
570 617
571 regval = readl(pctl->membase + reg); 618 regval = readl(pctl->membase + reg);
@@ -577,26 +624,14 @@ static int sunxi_pinctrl_irq_set_type(struct irq_data *d,
577 return 0; 624 return 0;
578} 625}
579 626
580static void sunxi_pinctrl_irq_mask_ack(struct irq_data *d) 627static void sunxi_pinctrl_irq_ack(struct irq_data *d)
581{ 628{
582 struct sunxi_pinctrl *pctl = irq_data_get_irq_chip_data(d); 629 struct sunxi_pinctrl *pctl = irq_data_get_irq_chip_data(d);
583 u32 ctrl_reg = sunxi_irq_ctrl_reg(d->hwirq);
584 u8 ctrl_idx = sunxi_irq_ctrl_offset(d->hwirq);
585 u32 status_reg = sunxi_irq_status_reg(d->hwirq); 630 u32 status_reg = sunxi_irq_status_reg(d->hwirq);
586 u8 status_idx = sunxi_irq_status_offset(d->hwirq); 631 u8 status_idx = sunxi_irq_status_offset(d->hwirq);
587 unsigned long flags;
588 u32 val;
589
590 spin_lock_irqsave(&pctl->lock, flags);
591
592 /* Mask the IRQ */
593 val = readl(pctl->membase + ctrl_reg);
594 writel(val & ~(1 << ctrl_idx), pctl->membase + ctrl_reg);
595 632
596 /* Clear the IRQ */ 633 /* Clear the IRQ */
597 writel(1 << status_idx, pctl->membase + status_reg); 634 writel(1 << status_idx, pctl->membase + status_reg);
598
599 spin_unlock_irqrestore(&pctl->lock, flags);
600} 635}
601 636
602static void sunxi_pinctrl_irq_mask(struct irq_data *d) 637static void sunxi_pinctrl_irq_mask(struct irq_data *d)
@@ -619,19 +654,11 @@ static void sunxi_pinctrl_irq_mask(struct irq_data *d)
619static void sunxi_pinctrl_irq_unmask(struct irq_data *d) 654static void sunxi_pinctrl_irq_unmask(struct irq_data *d)
620{ 655{
621 struct sunxi_pinctrl *pctl = irq_data_get_irq_chip_data(d); 656 struct sunxi_pinctrl *pctl = irq_data_get_irq_chip_data(d);
622 struct sunxi_desc_function *func;
623 u32 reg = sunxi_irq_ctrl_reg(d->hwirq); 657 u32 reg = sunxi_irq_ctrl_reg(d->hwirq);
624 u8 idx = sunxi_irq_ctrl_offset(d->hwirq); 658 u8 idx = sunxi_irq_ctrl_offset(d->hwirq);
625 unsigned long flags; 659 unsigned long flags;
626 u32 val; 660 u32 val;
627 661
628 func = sunxi_pinctrl_desc_find_function_by_pin(pctl,
629 pctl->irq_array[d->hwirq],
630 "irq");
631
632 /* Change muxing to INT mode */
633 sunxi_pmx_set(pctl->pctl_dev, pctl->irq_array[d->hwirq], func->muxval);
634
635 spin_lock_irqsave(&pctl->lock, flags); 662 spin_lock_irqsave(&pctl->lock, flags);
636 663
637 /* Unmask the IRQ */ 664 /* Unmask the IRQ */
@@ -641,28 +668,60 @@ static void sunxi_pinctrl_irq_unmask(struct irq_data *d)
641 spin_unlock_irqrestore(&pctl->lock, flags); 668 spin_unlock_irqrestore(&pctl->lock, flags);
642} 669}
643 670
644static struct irq_chip sunxi_pinctrl_irq_chip = { 671static void sunxi_pinctrl_irq_ack_unmask(struct irq_data *d)
672{
673 sunxi_pinctrl_irq_ack(d);
674 sunxi_pinctrl_irq_unmask(d);
675}
676
677static struct irq_chip sunxi_pinctrl_edge_irq_chip = {
678 .irq_ack = sunxi_pinctrl_irq_ack,
679 .irq_mask = sunxi_pinctrl_irq_mask,
680 .irq_unmask = sunxi_pinctrl_irq_unmask,
681 .irq_request_resources = sunxi_pinctrl_irq_request_resources,
682 .irq_release_resources = sunxi_pinctrl_irq_release_resources,
683 .irq_set_type = sunxi_pinctrl_irq_set_type,
684 .flags = IRQCHIP_SKIP_SET_WAKE,
685};
686
687static struct irq_chip sunxi_pinctrl_level_irq_chip = {
688 .irq_eoi = sunxi_pinctrl_irq_ack,
645 .irq_mask = sunxi_pinctrl_irq_mask, 689 .irq_mask = sunxi_pinctrl_irq_mask,
646 .irq_mask_ack = sunxi_pinctrl_irq_mask_ack,
647 .irq_unmask = sunxi_pinctrl_irq_unmask, 690 .irq_unmask = sunxi_pinctrl_irq_unmask,
691 /* Define irq_enable / disable to avoid spurious irqs for drivers
692 * using these to suppress irqs while they clear the irq source */
693 .irq_enable = sunxi_pinctrl_irq_ack_unmask,
694 .irq_disable = sunxi_pinctrl_irq_mask,
695 .irq_request_resources = sunxi_pinctrl_irq_request_resources,
696 .irq_release_resources = sunxi_pinctrl_irq_release_resources,
648 .irq_set_type = sunxi_pinctrl_irq_set_type, 697 .irq_set_type = sunxi_pinctrl_irq_set_type,
698 .flags = IRQCHIP_SKIP_SET_WAKE | IRQCHIP_EOI_THREADED |
699 IRQCHIP_EOI_IF_HANDLED,
649}; 700};
650 701
651static void sunxi_pinctrl_irq_handler(unsigned irq, struct irq_desc *desc) 702static void sunxi_pinctrl_irq_handler(unsigned irq, struct irq_desc *desc)
652{ 703{
653 struct irq_chip *chip = irq_get_chip(irq); 704 struct irq_chip *chip = irq_get_chip(irq);
654 struct sunxi_pinctrl *pctl = irq_get_handler_data(irq); 705 struct sunxi_pinctrl *pctl = irq_get_handler_data(irq);
655 const unsigned long reg = readl(pctl->membase + IRQ_STATUS_REG); 706 unsigned long bank, reg, val;
707
708 for (bank = 0; bank < pctl->desc->irq_banks; bank++)
709 if (irq == pctl->irq[bank])
710 break;
711
712 if (bank == pctl->desc->irq_banks)
713 return;
656 714
657 /* Clear all interrupts */ 715 reg = sunxi_irq_status_reg_from_bank(bank);
658 writel(reg, pctl->membase + IRQ_STATUS_REG); 716 val = readl(pctl->membase + reg);
659 717
660 if (reg) { 718 if (val) {
661 int irqoffset; 719 int irqoffset;
662 720
663 chained_irq_enter(chip, desc); 721 chained_irq_enter(chip, desc);
664 for_each_set_bit(irqoffset, &reg, SUNXI_IRQ_NUMBER) { 722 for_each_set_bit(irqoffset, &val, IRQ_PER_BANK) {
665 int pin_irq = irq_find_mapping(pctl->domain, irqoffset); 723 int pin_irq = irq_find_mapping(pctl->domain,
724 bank * IRQ_PER_BANK + irqoffset);
666 generic_handle_irq(pin_irq); 725 generic_handle_irq(pin_irq);
667 } 726 }
668 chained_irq_exit(chip, desc); 727 chained_irq_exit(chip, desc);
@@ -730,8 +789,11 @@ static int sunxi_pinctrl_build_state(struct platform_device *pdev)
730 789
731 while (func->name) { 790 while (func->name) {
732 /* Create interrupt mapping while we're at it */ 791 /* Create interrupt mapping while we're at it */
733 if (!strcmp(func->name, "irq")) 792 if (!strcmp(func->name, "irq")) {
734 pctl->irq_array[func->irqnum] = pin->pin.number; 793 int irqnum = func->irqnum + func->irqbank * IRQ_PER_BANK;
794 pctl->irq_array[irqnum] = pin->pin.number;
795 }
796
735 sunxi_pinctrl_add_function(pctl, func->name); 797 sunxi_pinctrl_add_function(pctl, func->name);
736 func++; 798 func++;
737 } 799 }
@@ -801,6 +863,13 @@ int sunxi_pinctrl_init(struct platform_device *pdev,
801 pctl->dev = &pdev->dev; 863 pctl->dev = &pdev->dev;
802 pctl->desc = desc; 864 pctl->desc = desc;
803 865
866 pctl->irq_array = devm_kcalloc(&pdev->dev,
867 IRQ_PER_BANK * pctl->desc->irq_banks,
868 sizeof(*pctl->irq_array),
869 GFP_KERNEL);
870 if (!pctl->irq_array)
871 return -ENOMEM;
872
804 ret = sunxi_pinctrl_build_state(pdev); 873 ret = sunxi_pinctrl_build_state(pdev);
805 if (ret) { 874 if (ret) {
806 dev_err(&pdev->dev, "dt probe failed: %d\n", ret); 875 dev_err(&pdev->dev, "dt probe failed: %d\n", ret);
@@ -869,7 +938,7 @@ int sunxi_pinctrl_init(struct platform_device *pdev,
869 const struct sunxi_desc_pin *pin = pctl->desc->pins + i; 938 const struct sunxi_desc_pin *pin = pctl->desc->pins + i;
870 939
871 ret = gpiochip_add_pin_range(pctl->chip, dev_name(&pdev->dev), 940 ret = gpiochip_add_pin_range(pctl->chip, dev_name(&pdev->dev),
872 pin->pin.number, 941 pin->pin.number - pctl->desc->pin_base,
873 pin->pin.number, 1); 942 pin->pin.number, 1);
874 if (ret) 943 if (ret)
875 goto gpiochip_error; 944 goto gpiochip_error;
@@ -885,30 +954,51 @@ int sunxi_pinctrl_init(struct platform_device *pdev,
885 if (ret) 954 if (ret)
886 goto gpiochip_error; 955 goto gpiochip_error;
887 956
888 pctl->irq = irq_of_parse_and_map(node, 0); 957 pctl->irq = devm_kcalloc(&pdev->dev,
958 pctl->desc->irq_banks,
959 sizeof(*pctl->irq),
960 GFP_KERNEL);
889 if (!pctl->irq) { 961 if (!pctl->irq) {
890 ret = -EINVAL; 962 ret = -ENOMEM;
891 goto clk_error; 963 goto clk_error;
892 } 964 }
893 965
894 pctl->domain = irq_domain_add_linear(node, SUNXI_IRQ_NUMBER, 966 for (i = 0; i < pctl->desc->irq_banks; i++) {
895 &irq_domain_simple_ops, NULL); 967 pctl->irq[i] = platform_get_irq(pdev, i);
968 if (pctl->irq[i] < 0) {
969 ret = pctl->irq[i];
970 goto clk_error;
971 }
972 }
973
974 pctl->domain = irq_domain_add_linear(node,
975 pctl->desc->irq_banks * IRQ_PER_BANK,
976 &irq_domain_simple_ops,
977 NULL);
896 if (!pctl->domain) { 978 if (!pctl->domain) {
897 dev_err(&pdev->dev, "Couldn't register IRQ domain\n"); 979 dev_err(&pdev->dev, "Couldn't register IRQ domain\n");
898 ret = -ENOMEM; 980 ret = -ENOMEM;
899 goto clk_error; 981 goto clk_error;
900 } 982 }
901 983
902 for (i = 0; i < SUNXI_IRQ_NUMBER; i++) { 984 for (i = 0; i < (pctl->desc->irq_banks * IRQ_PER_BANK); i++) {
903 int irqno = irq_create_mapping(pctl->domain, i); 985 int irqno = irq_create_mapping(pctl->domain, i);
904 986
905 irq_set_chip_and_handler(irqno, &sunxi_pinctrl_irq_chip, 987 irq_set_chip_and_handler(irqno, &sunxi_pinctrl_edge_irq_chip,
906 handle_simple_irq); 988 handle_edge_irq);
907 irq_set_chip_data(irqno, pctl); 989 irq_set_chip_data(irqno, pctl);
908 }; 990 };
909 991
910 irq_set_chained_handler(pctl->irq, sunxi_pinctrl_irq_handler); 992 for (i = 0; i < pctl->desc->irq_banks; i++) {
911 irq_set_handler_data(pctl->irq, pctl); 993 /* Mask and clear all IRQs before registering a handler */
994 writel(0, pctl->membase + sunxi_irq_ctrl_reg_from_bank(i));
995 writel(0xffffffff,
996 pctl->membase + sunxi_irq_status_reg_from_bank(i));
997
998 irq_set_chained_handler(pctl->irq[i],
999 sunxi_pinctrl_irq_handler);
1000 irq_set_handler_data(pctl->irq[i], pctl);
1001 }
912 1002
913 dev_info(&pdev->dev, "initialized sunXi PIO driver\n"); 1003 dev_info(&pdev->dev, "initialized sunXi PIO driver\n");
914 1004
@@ -917,8 +1007,7 @@ int sunxi_pinctrl_init(struct platform_device *pdev,
917clk_error: 1007clk_error:
918 clk_disable_unprepare(clk); 1008 clk_disable_unprepare(clk);
919gpiochip_error: 1009gpiochip_error:
920 if (gpiochip_remove(pctl->chip)) 1010 gpiochip_remove(pctl->chip);
921 dev_err(&pdev->dev, "failed to remove gpio chip\n");
922pinctrl_error: 1011pinctrl_error:
923 pinctrl_unregister(pctl->pctl_dev); 1012 pinctrl_unregister(pctl->pctl_dev);
924 return ret; 1013 return ret;
diff --git a/drivers/pinctrl/sunxi/pinctrl-sunxi.h b/drivers/pinctrl/sunxi/pinctrl-sunxi.h
index 8169ba598876..4245b96c7996 100644
--- a/drivers/pinctrl/sunxi/pinctrl-sunxi.h
+++ b/drivers/pinctrl/sunxi/pinctrl-sunxi.h
@@ -53,7 +53,7 @@
53#define PULL_PINS_BITS 2 53#define PULL_PINS_BITS 2
54#define PULL_PINS_MASK 0x03 54#define PULL_PINS_MASK 0x03
55 55
56#define SUNXI_IRQ_NUMBER 32 56#define IRQ_PER_BANK 32
57 57
58#define IRQ_CFG_REG 0x200 58#define IRQ_CFG_REG 0x200
59#define IRQ_CFG_IRQ_PER_REG 8 59#define IRQ_CFG_IRQ_PER_REG 8
@@ -68,6 +68,8 @@
68#define IRQ_STATUS_IRQ_BITS 1 68#define IRQ_STATUS_IRQ_BITS 1
69#define IRQ_STATUS_IRQ_MASK ((1 << IRQ_STATUS_IRQ_BITS) - 1) 69#define IRQ_STATUS_IRQ_MASK ((1 << IRQ_STATUS_IRQ_BITS) - 1)
70 70
71#define IRQ_MEM_SIZE 0x20
72
71#define IRQ_EDGE_RISING 0x00 73#define IRQ_EDGE_RISING 0x00
72#define IRQ_EDGE_FALLING 0x01 74#define IRQ_EDGE_FALLING 0x01
73#define IRQ_LEVEL_HIGH 0x02 75#define IRQ_LEVEL_HIGH 0x02
@@ -77,6 +79,7 @@
77struct sunxi_desc_function { 79struct sunxi_desc_function {
78 const char *name; 80 const char *name;
79 u8 muxval; 81 u8 muxval;
82 u8 irqbank;
80 u8 irqnum; 83 u8 irqnum;
81}; 84};
82 85
@@ -89,6 +92,7 @@ struct sunxi_pinctrl_desc {
89 const struct sunxi_desc_pin *pins; 92 const struct sunxi_desc_pin *pins;
90 int npins; 93 int npins;
91 unsigned pin_base; 94 unsigned pin_base;
95 unsigned irq_banks;
92}; 96};
93 97
94struct sunxi_pinctrl_function { 98struct sunxi_pinctrl_function {
@@ -113,8 +117,8 @@ struct sunxi_pinctrl {
113 unsigned nfunctions; 117 unsigned nfunctions;
114 struct sunxi_pinctrl_group *groups; 118 struct sunxi_pinctrl_group *groups;
115 unsigned ngroups; 119 unsigned ngroups;
116 int irq; 120 int *irq;
117 int irq_array[SUNXI_IRQ_NUMBER]; 121 unsigned *irq_array;
118 spinlock_t lock; 122 spinlock_t lock;
119 struct pinctrl_dev *pctl_dev; 123 struct pinctrl_dev *pctl_dev;
120}; 124};
@@ -139,6 +143,14 @@ struct sunxi_pinctrl {
139 .irqnum = _irq, \ 143 .irqnum = _irq, \
140 } 144 }
141 145
146#define SUNXI_FUNCTION_IRQ_BANK(_val, _bank, _irq) \
147 { \
148 .name = "irq", \
149 .muxval = _val, \
150 .irqbank = _bank, \
151 .irqnum = _irq, \
152 }
153
142/* 154/*
143 * The sunXi PIO registers are organized as is: 155 * The sunXi PIO registers are organized as is:
144 * 0x00 - 0x0c Muxing values. 156 * 0x00 - 0x0c Muxing values.
@@ -218,8 +230,10 @@ static inline u32 sunxi_pull_offset(u16 pin)
218 230
219static inline u32 sunxi_irq_cfg_reg(u16 irq) 231static inline u32 sunxi_irq_cfg_reg(u16 irq)
220{ 232{
221 u8 reg = irq / IRQ_CFG_IRQ_PER_REG * 0x04; 233 u8 bank = irq / IRQ_PER_BANK;
222 return reg + IRQ_CFG_REG; 234 u8 reg = (irq % IRQ_PER_BANK) / IRQ_CFG_IRQ_PER_REG * 0x04;
235
236 return IRQ_CFG_REG + bank * IRQ_MEM_SIZE + reg;
223} 237}
224 238
225static inline u32 sunxi_irq_cfg_offset(u16 irq) 239static inline u32 sunxi_irq_cfg_offset(u16 irq)
@@ -228,10 +242,16 @@ static inline u32 sunxi_irq_cfg_offset(u16 irq)
228 return irq_num * IRQ_CFG_IRQ_BITS; 242 return irq_num * IRQ_CFG_IRQ_BITS;
229} 243}
230 244
245static inline u32 sunxi_irq_ctrl_reg_from_bank(u8 bank)
246{
247 return IRQ_CTRL_REG + bank * IRQ_MEM_SIZE;
248}
249
231static inline u32 sunxi_irq_ctrl_reg(u16 irq) 250static inline u32 sunxi_irq_ctrl_reg(u16 irq)
232{ 251{
233 u8 reg = irq / IRQ_CTRL_IRQ_PER_REG * 0x04; 252 u8 bank = irq / IRQ_PER_BANK;
234 return reg + IRQ_CTRL_REG; 253
254 return sunxi_irq_ctrl_reg_from_bank(bank);
235} 255}
236 256
237static inline u32 sunxi_irq_ctrl_offset(u16 irq) 257static inline u32 sunxi_irq_ctrl_offset(u16 irq)
@@ -240,10 +260,16 @@ static inline u32 sunxi_irq_ctrl_offset(u16 irq)
240 return irq_num * IRQ_CTRL_IRQ_BITS; 260 return irq_num * IRQ_CTRL_IRQ_BITS;
241} 261}
242 262
263static inline u32 sunxi_irq_status_reg_from_bank(u8 bank)
264{
265 return IRQ_STATUS_REG + bank * IRQ_MEM_SIZE;
266}
267
243static inline u32 sunxi_irq_status_reg(u16 irq) 268static inline u32 sunxi_irq_status_reg(u16 irq)
244{ 269{
245 u8 reg = irq / IRQ_STATUS_IRQ_PER_REG * 0x04; 270 u8 bank = irq / IRQ_PER_BANK;
246 return reg + IRQ_STATUS_REG; 271
272 return sunxi_irq_status_reg_from_bank(bank);
247} 273}
248 274
249static inline u32 sunxi_irq_status_offset(u16 irq) 275static inline u32 sunxi_irq_status_offset(u16 irq)
diff --git a/drivers/pinctrl/vt8500/pinctrl-wmt.c b/drivers/pinctrl/vt8500/pinctrl-wmt.c
index 2c61281bebd7..d055d63309e4 100644
--- a/drivers/pinctrl/vt8500/pinctrl-wmt.c
+++ b/drivers/pinctrl/vt8500/pinctrl-wmt.c
@@ -131,9 +131,9 @@ static int wmt_set_pinmux(struct wmt_pinctrl_data *data, unsigned func,
131 return 0; 131 return 0;
132} 132}
133 133
134static int wmt_pmx_enable(struct pinctrl_dev *pctldev, 134static int wmt_pmx_set_mux(struct pinctrl_dev *pctldev,
135 unsigned func_selector, 135 unsigned func_selector,
136 unsigned group_selector) 136 unsigned group_selector)
137{ 137{
138 struct wmt_pinctrl_data *data = pinctrl_dev_get_drvdata(pctldev); 138 struct wmt_pinctrl_data *data = pinctrl_dev_get_drvdata(pctldev);
139 u32 pinnum = data->pins[group_selector].number; 139 u32 pinnum = data->pins[group_selector].number;
@@ -141,17 +141,6 @@ static int wmt_pmx_enable(struct pinctrl_dev *pctldev,
141 return wmt_set_pinmux(data, func_selector, pinnum); 141 return wmt_set_pinmux(data, func_selector, pinnum);
142} 142}
143 143
144static void wmt_pmx_disable(struct pinctrl_dev *pctldev,
145 unsigned func_selector,
146 unsigned group_selector)
147{
148 struct wmt_pinctrl_data *data = pinctrl_dev_get_drvdata(pctldev);
149 u32 pinnum = data->pins[group_selector].number;
150
151 /* disable by setting GPIO_IN */
152 wmt_set_pinmux(data, WMT_FSEL_GPIO_IN, pinnum);
153}
154
155static void wmt_pmx_gpio_disable_free(struct pinctrl_dev *pctldev, 144static void wmt_pmx_gpio_disable_free(struct pinctrl_dev *pctldev,
156 struct pinctrl_gpio_range *range, 145 struct pinctrl_gpio_range *range,
157 unsigned offset) 146 unsigned offset)
@@ -179,8 +168,7 @@ static struct pinmux_ops wmt_pinmux_ops = {
179 .get_functions_count = wmt_pmx_get_functions_count, 168 .get_functions_count = wmt_pmx_get_functions_count,
180 .get_function_name = wmt_pmx_get_function_name, 169 .get_function_name = wmt_pmx_get_function_name,
181 .get_function_groups = wmt_pmx_get_function_groups, 170 .get_function_groups = wmt_pmx_get_function_groups,
182 .enable = wmt_pmx_enable, 171 .set_mux = wmt_pmx_set_mux,
183 .disable = wmt_pmx_disable,
184 .gpio_disable_free = wmt_pmx_gpio_disable_free, 172 .gpio_disable_free = wmt_pmx_gpio_disable_free,
185 .gpio_set_direction = wmt_pmx_gpio_set_direction, 173 .gpio_set_direction = wmt_pmx_gpio_set_direction,
186}; 174};
@@ -627,8 +615,7 @@ int wmt_pinctrl_probe(struct platform_device *pdev,
627 return 0; 615 return 0;
628 616
629fail_range: 617fail_range:
630 if (gpiochip_remove(&data->gpio_chip)) 618 gpiochip_remove(&data->gpio_chip);
631 dev_err(&pdev->dev, "failed to remove gpio chip\n");
632fail_gpio: 619fail_gpio:
633 pinctrl_unregister(data->pctl_dev); 620 pinctrl_unregister(data->pctl_dev);
634 return err; 621 return err;
@@ -637,12 +624,8 @@ fail_gpio:
637int wmt_pinctrl_remove(struct platform_device *pdev) 624int wmt_pinctrl_remove(struct platform_device *pdev)
638{ 625{
639 struct wmt_pinctrl_data *data = platform_get_drvdata(pdev); 626 struct wmt_pinctrl_data *data = platform_get_drvdata(pdev);
640 int err;
641
642 err = gpiochip_remove(&data->gpio_chip);
643 if (err)
644 dev_err(&pdev->dev, "failed to remove gpio chip\n");
645 627
628 gpiochip_remove(&data->gpio_chip);
646 pinctrl_unregister(data->pctl_dev); 629 pinctrl_unregister(data->pctl_dev);
647 630
648 return 0; 631 return 0;
generated by cgit v1.2.2 (git 2.25.0) at 2026-02-23 01:16:12 -0500