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authorArnd Bergmann <arnd@arndb.de>2012-09-04 09:01:37 -0400
committerArnd Bergmann <arnd@arndb.de>2012-09-04 09:01:37 -0400
commit863e99a8c1ea2b0391491904297f57a0f6a1fdd6 (patch)
tree0e7789f83c0ba3a1bc3c19d3ccf5ea6f84f19db6 /drivers/pinctrl
parentdd9bf78040fa0da4cecc228e1682b9682b8cb180 (diff)
parenta849088aa1552b1a28eea3daff599ee22a734ae3 (diff)
Merge commit 'a849088aa1' from rmk/fixes into cleanup/io-pci
As Stephen Rothwell reports, a849088aa155 ("ARM: Fix ioremap() of address zero") from the arm-current tree and commit c2794437091a ("ARM: Add fixed PCI i/o mapping") from the arm-soc tree conflict in a nontrivial way in arch/arm/mm/mmu.c. Rob Herring explains: The PCI i/o reserved area has a dummy physical address of 0 and needs to be skipped by ioremap searches. So we don't set VM_ARM_STATIC_MAPPING to prevent matches by ioremap. The vm_struct settings don't really matter when we do the real mapping of the i/o space. Since commit a849088aa155 is at the start of the fixes branch in the arm tree, we can merge it into the branch that contains the other ioremap changes. Signed-off-by: Arnd Bergmann <arnd@arndb.de> Cc: Rob Herring <rob.herring@calxeda.com> Cc: Russell King <rmk+kernel@arm.linux.org.uk>
Diffstat (limited to 'drivers/pinctrl')
-rw-r--r--drivers/pinctrl/Kconfig10
-rw-r--r--drivers/pinctrl/Makefile1
-rw-r--r--drivers/pinctrl/core.c54
-rw-r--r--drivers/pinctrl/pinctrl-coh901.c6
-rw-r--r--drivers/pinctrl/pinctrl-imx.c15
-rw-r--r--drivers/pinctrl/pinctrl-imx23.c2
-rw-r--r--drivers/pinctrl/pinctrl-imx28.c2
-rw-r--r--drivers/pinctrl/pinctrl-imx51.c2
-rw-r--r--drivers/pinctrl/pinctrl-imx6q.c2
-rw-r--r--drivers/pinctrl/pinctrl-nomadik-db8500.c38
-rw-r--r--drivers/pinctrl/pinctrl-nomadik.c42
-rw-r--r--drivers/pinctrl/pinctrl-single.c987
-rw-r--r--drivers/pinctrl/pinctrl-sirf.c490
-rw-r--r--drivers/pinctrl/pinctrl-tegra.c5
-rw-r--r--drivers/pinctrl/pinctrl-u300.c14
-rw-r--r--drivers/pinctrl/spear/pinctrl-spear.c4
16 files changed, 1570 insertions, 104 deletions
diff --git a/drivers/pinctrl/Kconfig b/drivers/pinctrl/Kconfig
index c6e6ae0aa3b1..54e3588bef62 100644
--- a/drivers/pinctrl/Kconfig
+++ b/drivers/pinctrl/Kconfig
@@ -102,6 +102,14 @@ config PINCTRL_PXA910
102 select PINCTRL_PXA3xx 102 select PINCTRL_PXA3xx
103 select PINCONF 103 select PINCONF
104 104
105config PINCTRL_SINGLE
106 tristate "One-register-per-pin type device tree based pinctrl driver"
107 depends on OF
108 select PINMUX
109 select PINCONF
110 help
111 This selects the device tree based generic pinctrl driver.
112
105config PINCTRL_SIRF 113config PINCTRL_SIRF
106 bool "CSR SiRFprimaII pin controller driver" 114 bool "CSR SiRFprimaII pin controller driver"
107 depends on ARCH_PRIMA2 115 depends on ARCH_PRIMA2
@@ -130,7 +138,7 @@ config PINCTRL_U300
130 138
131config PINCTRL_COH901 139config PINCTRL_COH901
132 bool "ST-Ericsson U300 COH 901 335/571 GPIO" 140 bool "ST-Ericsson U300 COH 901 335/571 GPIO"
133 depends on GPIOLIB && ARCH_U300 && PINMUX_U300 141 depends on GPIOLIB && ARCH_U300 && PINCTRL_U300
134 help 142 help
135 Say yes here to support GPIO interface on ST-Ericsson U300. 143 Say yes here to support GPIO interface on ST-Ericsson U300.
136 The names of the two IP block variants supported are 144 The names of the two IP block variants supported are
diff --git a/drivers/pinctrl/Makefile b/drivers/pinctrl/Makefile
index 8c074376cdea..f40b1f81ff2c 100644
--- a/drivers/pinctrl/Makefile
+++ b/drivers/pinctrl/Makefile
@@ -22,6 +22,7 @@ obj-$(CONFIG_PINCTRL_NOMADIK) += pinctrl-nomadik.o
22obj-$(CONFIG_PINCTRL_DB8500) += pinctrl-nomadik-db8500.o 22obj-$(CONFIG_PINCTRL_DB8500) += pinctrl-nomadik-db8500.o
23obj-$(CONFIG_PINCTRL_PXA168) += pinctrl-pxa168.o 23obj-$(CONFIG_PINCTRL_PXA168) += pinctrl-pxa168.o
24obj-$(CONFIG_PINCTRL_PXA910) += pinctrl-pxa910.o 24obj-$(CONFIG_PINCTRL_PXA910) += pinctrl-pxa910.o
25obj-$(CONFIG_PINCTRL_SINGLE) += pinctrl-single.o
25obj-$(CONFIG_PINCTRL_SIRF) += pinctrl-sirf.o 26obj-$(CONFIG_PINCTRL_SIRF) += pinctrl-sirf.o
26obj-$(CONFIG_PINCTRL_TEGRA) += pinctrl-tegra.o 27obj-$(CONFIG_PINCTRL_TEGRA) += pinctrl-tegra.o
27obj-$(CONFIG_PINCTRL_TEGRA20) += pinctrl-tegra20.o 28obj-$(CONFIG_PINCTRL_TEGRA20) += pinctrl-tegra20.o
diff --git a/drivers/pinctrl/core.c b/drivers/pinctrl/core.c
index 0cc053af70bd..dc5c126e398a 100644
--- a/drivers/pinctrl/core.c
+++ b/drivers/pinctrl/core.c
@@ -332,19 +332,16 @@ void pinctrl_add_gpio_range(struct pinctrl_dev *pctldev,
332} 332}
333EXPORT_SYMBOL_GPL(pinctrl_add_gpio_range); 333EXPORT_SYMBOL_GPL(pinctrl_add_gpio_range);
334 334
335/** 335void pinctrl_add_gpio_ranges(struct pinctrl_dev *pctldev,
336 * pinctrl_remove_gpio_range() - remove a range of GPIOs fro a pin controller 336 struct pinctrl_gpio_range *ranges,
337 * @pctldev: pin controller device to remove the range from 337 unsigned nranges)
338 * @range: the GPIO range to remove
339 */
340void pinctrl_remove_gpio_range(struct pinctrl_dev *pctldev,
341 struct pinctrl_gpio_range *range)
342{ 338{
343 mutex_lock(&pinctrl_mutex); 339 int i;
344 list_del(&range->node); 340
345 mutex_unlock(&pinctrl_mutex); 341 for (i = 0; i < nranges; i++)
342 pinctrl_add_gpio_range(pctldev, &ranges[i]);
346} 343}
347EXPORT_SYMBOL_GPL(pinctrl_remove_gpio_range); 344EXPORT_SYMBOL_GPL(pinctrl_add_gpio_ranges);
348 345
349/** 346/**
350 * pinctrl_get_group_selector() - returns the group selector for a group 347 * pinctrl_get_group_selector() - returns the group selector for a group
@@ -660,11 +657,7 @@ static struct pinctrl *pinctrl_get_locked(struct device *dev)
660 if (p != NULL) 657 if (p != NULL)
661 return ERR_PTR(-EBUSY); 658 return ERR_PTR(-EBUSY);
662 659
663 p = create_pinctrl(dev); 660 return create_pinctrl(dev);
664 if (IS_ERR(p))
665 return p;
666
667 return p;
668} 661}
669 662
670/** 663/**
@@ -741,11 +734,8 @@ static struct pinctrl_state *pinctrl_lookup_state_locked(struct pinctrl *p,
741 dev_dbg(p->dev, "using pinctrl dummy state (%s)\n", 734 dev_dbg(p->dev, "using pinctrl dummy state (%s)\n",
742 name); 735 name);
743 state = create_state(p, name); 736 state = create_state(p, name);
744 if (IS_ERR(state)) 737 } else
745 return state; 738 state = ERR_PTR(-ENODEV);
746 } else {
747 return ERR_PTR(-ENODEV);
748 }
749 } 739 }
750 740
751 return state; 741 return state;
@@ -1395,9 +1385,9 @@ struct pinctrl_dev *pinctrl_register(struct pinctrl_desc *pctldesc,
1395 struct pinctrl_dev *pctldev; 1385 struct pinctrl_dev *pctldev;
1396 int ret; 1386 int ret;
1397 1387
1398 if (pctldesc == NULL) 1388 if (!pctldesc)
1399 return NULL; 1389 return NULL;
1400 if (pctldesc->name == NULL) 1390 if (!pctldesc->name)
1401 return NULL; 1391 return NULL;
1402 1392
1403 pctldev = kzalloc(sizeof(*pctldev), GFP_KERNEL); 1393 pctldev = kzalloc(sizeof(*pctldev), GFP_KERNEL);
@@ -1415,23 +1405,20 @@ struct pinctrl_dev *pinctrl_register(struct pinctrl_desc *pctldesc,
1415 pctldev->dev = dev; 1405 pctldev->dev = dev;
1416 1406
1417 /* check core ops for sanity */ 1407 /* check core ops for sanity */
1418 ret = pinctrl_check_ops(pctldev); 1408 if (pinctrl_check_ops(pctldev)) {
1419 if (ret) {
1420 dev_err(dev, "pinctrl ops lacks necessary functions\n"); 1409 dev_err(dev, "pinctrl ops lacks necessary functions\n");
1421 goto out_err; 1410 goto out_err;
1422 } 1411 }
1423 1412
1424 /* If we're implementing pinmuxing, check the ops for sanity */ 1413 /* If we're implementing pinmuxing, check the ops for sanity */
1425 if (pctldesc->pmxops) { 1414 if (pctldesc->pmxops) {
1426 ret = pinmux_check_ops(pctldev); 1415 if (pinmux_check_ops(pctldev))
1427 if (ret)
1428 goto out_err; 1416 goto out_err;
1429 } 1417 }
1430 1418
1431 /* If we're implementing pinconfig, check the ops for sanity */ 1419 /* If we're implementing pinconfig, check the ops for sanity */
1432 if (pctldesc->confops) { 1420 if (pctldesc->confops) {
1433 ret = pinconf_check_ops(pctldev); 1421 if (pinconf_check_ops(pctldev))
1434 if (ret)
1435 goto out_err; 1422 goto out_err;
1436 } 1423 }
1437 1424
@@ -1457,11 +1444,9 @@ struct pinctrl_dev *pinctrl_register(struct pinctrl_desc *pctldesc,
1457 if (IS_ERR(s)) { 1444 if (IS_ERR(s)) {
1458 dev_dbg(dev, "failed to lookup the default state\n"); 1445 dev_dbg(dev, "failed to lookup the default state\n");
1459 } else { 1446 } else {
1460 ret = pinctrl_select_state_locked(pctldev->p, s); 1447 if (pinctrl_select_state_locked(pctldev->p, s))
1461 if (ret) {
1462 dev_err(dev, 1448 dev_err(dev,
1463 "failed to select default state\n"); 1449 "failed to select default state\n");
1464 }
1465 } 1450 }
1466 } 1451 }
1467 1452
@@ -1485,6 +1470,7 @@ EXPORT_SYMBOL_GPL(pinctrl_register);
1485 */ 1470 */
1486void pinctrl_unregister(struct pinctrl_dev *pctldev) 1471void pinctrl_unregister(struct pinctrl_dev *pctldev)
1487{ 1472{
1473 struct pinctrl_gpio_range *range, *n;
1488 if (pctldev == NULL) 1474 if (pctldev == NULL)
1489 return; 1475 return;
1490 1476
@@ -1500,6 +1486,10 @@ void pinctrl_unregister(struct pinctrl_dev *pctldev)
1500 /* Destroy descriptor tree */ 1486 /* Destroy descriptor tree */
1501 pinctrl_free_pindescs(pctldev, pctldev->desc->pins, 1487 pinctrl_free_pindescs(pctldev, pctldev->desc->pins,
1502 pctldev->desc->npins); 1488 pctldev->desc->npins);
1489 /* remove gpio ranges map */
1490 list_for_each_entry_safe(range, n, &pctldev->gpio_ranges, node)
1491 list_del(&range->node);
1492
1503 kfree(pctldev); 1493 kfree(pctldev);
1504 1494
1505 mutex_unlock(&pinctrl_mutex); 1495 mutex_unlock(&pinctrl_mutex);
diff --git a/drivers/pinctrl/pinctrl-coh901.c b/drivers/pinctrl/pinctrl-coh901.c
index 55697a5d7482..cc0f00d73d15 100644
--- a/drivers/pinctrl/pinctrl-coh901.c
+++ b/drivers/pinctrl/pinctrl-coh901.c
@@ -770,7 +770,7 @@ static int __init u300_gpio_probe(struct platform_device *pdev)
770 dev_err(gpio->dev, "could not get GPIO clock\n"); 770 dev_err(gpio->dev, "could not get GPIO clock\n");
771 goto err_no_clk; 771 goto err_no_clk;
772 } 772 }
773 err = clk_enable(gpio->clk); 773 err = clk_prepare_enable(gpio->clk);
774 if (err) { 774 if (err) {
775 dev_err(gpio->dev, "could not enable GPIO clock\n"); 775 dev_err(gpio->dev, "could not enable GPIO clock\n");
776 goto err_no_clk_enable; 776 goto err_no_clk_enable;
@@ -912,7 +912,7 @@ err_no_ioremap:
912 release_mem_region(gpio->memres->start, resource_size(gpio->memres)); 912 release_mem_region(gpio->memres->start, resource_size(gpio->memres));
913err_no_ioregion: 913err_no_ioregion:
914err_no_resource: 914err_no_resource:
915 clk_disable(gpio->clk); 915 clk_disable_unprepare(gpio->clk);
916err_no_clk_enable: 916err_no_clk_enable:
917 clk_put(gpio->clk); 917 clk_put(gpio->clk);
918err_no_clk: 918err_no_clk:
@@ -943,7 +943,7 @@ static int __exit u300_gpio_remove(struct platform_device *pdev)
943 iounmap(gpio->base); 943 iounmap(gpio->base);
944 release_mem_region(gpio->memres->start, 944 release_mem_region(gpio->memres->start,
945 resource_size(gpio->memres)); 945 resource_size(gpio->memres));
946 clk_disable(gpio->clk); 946 clk_disable_unprepare(gpio->clk);
947 clk_put(gpio->clk); 947 clk_put(gpio->clk);
948 platform_set_drvdata(pdev, NULL); 948 platform_set_drvdata(pdev, NULL);
949 kfree(gpio); 949 kfree(gpio);
diff --git a/drivers/pinctrl/pinctrl-imx.c b/drivers/pinctrl/pinctrl-imx.c
index dd6d93aa5334..44e97265cd7d 100644
--- a/drivers/pinctrl/pinctrl-imx.c
+++ b/drivers/pinctrl/pinctrl-imx.c
@@ -146,7 +146,7 @@ static int imx_dt_node_to_map(struct pinctrl_dev *pctldev,
146 struct pinctrl_map *new_map; 146 struct pinctrl_map *new_map;
147 struct device_node *parent; 147 struct device_node *parent;
148 int map_num = 1; 148 int map_num = 1;
149 int i; 149 int i, j;
150 150
151 /* 151 /*
152 * first find the group of this node and check if we need create 152 * first find the group of this node and check if we need create
@@ -184,13 +184,14 @@ static int imx_dt_node_to_map(struct pinctrl_dev *pctldev,
184 184
185 /* create config map */ 185 /* create config map */
186 new_map++; 186 new_map++;
187 for (i = 0; i < grp->npins; i++) { 187 for (i = j = 0; i < grp->npins; i++) {
188 if (!(grp->configs[i] & IMX_NO_PAD_CTL)) { 188 if (!(grp->configs[i] & IMX_NO_PAD_CTL)) {
189 new_map[i].type = PIN_MAP_TYPE_CONFIGS_PIN; 189 new_map[j].type = PIN_MAP_TYPE_CONFIGS_PIN;
190 new_map[i].data.configs.group_or_pin = 190 new_map[j].data.configs.group_or_pin =
191 pin_get_name(pctldev, grp->pins[i]); 191 pin_get_name(pctldev, grp->pins[i]);
192 new_map[i].data.configs.configs = &grp->configs[i]; 192 new_map[j].data.configs.configs = &grp->configs[i];
193 new_map[i].data.configs.num_configs = 1; 193 new_map[j].data.configs.num_configs = 1;
194 j++;
194 } 195 }
195 } 196 }
196 197
@@ -474,7 +475,9 @@ static int __devinit imx_pinctrl_parse_groups(struct device_node *np,
474 grp->configs[j] = config & ~IMX_PAD_SION; 475 grp->configs[j] = config & ~IMX_PAD_SION;
475 } 476 }
476 477
478#ifdef DEBUG
477 IMX_PMX_DUMP(info, grp->pins, grp->mux_mode, grp->configs, grp->npins); 479 IMX_PMX_DUMP(info, grp->pins, grp->mux_mode, grp->configs, grp->npins);
480#endif
478 481
479 return 0; 482 return 0;
480} 483}
diff --git a/drivers/pinctrl/pinctrl-imx23.c b/drivers/pinctrl/pinctrl-imx23.c
index 75d3eff94296..3674d877ed7c 100644
--- a/drivers/pinctrl/pinctrl-imx23.c
+++ b/drivers/pinctrl/pinctrl-imx23.c
@@ -292,7 +292,7 @@ static int __init imx23_pinctrl_init(void)
292{ 292{
293 return platform_driver_register(&imx23_pinctrl_driver); 293 return platform_driver_register(&imx23_pinctrl_driver);
294} 294}
295arch_initcall(imx23_pinctrl_init); 295postcore_initcall(imx23_pinctrl_init);
296 296
297static void __exit imx23_pinctrl_exit(void) 297static void __exit imx23_pinctrl_exit(void)
298{ 298{
diff --git a/drivers/pinctrl/pinctrl-imx28.c b/drivers/pinctrl/pinctrl-imx28.c
index b973026811a2..0f5b2122b1ba 100644
--- a/drivers/pinctrl/pinctrl-imx28.c
+++ b/drivers/pinctrl/pinctrl-imx28.c
@@ -408,7 +408,7 @@ static int __init imx28_pinctrl_init(void)
408{ 408{
409 return platform_driver_register(&imx28_pinctrl_driver); 409 return platform_driver_register(&imx28_pinctrl_driver);
410} 410}
411arch_initcall(imx28_pinctrl_init); 411postcore_initcall(imx28_pinctrl_init);
412 412
413static void __exit imx28_pinctrl_exit(void) 413static void __exit imx28_pinctrl_exit(void)
414{ 414{
diff --git a/drivers/pinctrl/pinctrl-imx51.c b/drivers/pinctrl/pinctrl-imx51.c
index 689b3c88dd2e..9fd02162a3c2 100644
--- a/drivers/pinctrl/pinctrl-imx51.c
+++ b/drivers/pinctrl/pinctrl-imx51.c
@@ -974,7 +974,7 @@ static struct imx_pin_reg imx51_pin_regs[] = {
974 IMX_PIN_REG(MX51_PAD_EIM_DA13, NO_PAD, 0x050, 0, 0x000, 0), /* MX51_PAD_EIM_DA13__EIM_DA13 */ 974 IMX_PIN_REG(MX51_PAD_EIM_DA13, NO_PAD, 0x050, 0, 0x000, 0), /* MX51_PAD_EIM_DA13__EIM_DA13 */
975 IMX_PIN_REG(MX51_PAD_EIM_DA14, NO_PAD, 0x054, 0, 0x000, 0), /* MX51_PAD_EIM_DA14__EIM_DA14 */ 975 IMX_PIN_REG(MX51_PAD_EIM_DA14, NO_PAD, 0x054, 0, 0x000, 0), /* MX51_PAD_EIM_DA14__EIM_DA14 */
976 IMX_PIN_REG(MX51_PAD_EIM_DA15, NO_PAD, 0x058, 0, 0x000, 0), /* MX51_PAD_EIM_DA15__EIM_DA15 */ 976 IMX_PIN_REG(MX51_PAD_EIM_DA15, NO_PAD, 0x058, 0, 0x000, 0), /* MX51_PAD_EIM_DA15__EIM_DA15 */
977 IMX_PIN_REG(MX51_PAD_SD2_CMD, NO_PAD, 0x3b4, 2, 0x91c, 3), /* MX51_PAD_SD2_CMD__CSPI_MOSI */ 977 IMX_PIN_REG(MX51_PAD_SD2_CMD, 0x7bc, 0x3b4, 2, 0x91c, 3), /* MX51_PAD_SD2_CMD__CSPI_MOSI */
978 IMX_PIN_REG(MX51_PAD_SD2_CMD, 0x7bc, 0x3b4, 1, 0x9b0, 2), /* MX51_PAD_SD2_CMD__I2C1_SCL */ 978 IMX_PIN_REG(MX51_PAD_SD2_CMD, 0x7bc, 0x3b4, 1, 0x9b0, 2), /* MX51_PAD_SD2_CMD__I2C1_SCL */
979 IMX_PIN_REG(MX51_PAD_SD2_CMD, 0x7bc, 0x3b4, 0, 0x000, 0), /* MX51_PAD_SD2_CMD__SD2_CMD */ 979 IMX_PIN_REG(MX51_PAD_SD2_CMD, 0x7bc, 0x3b4, 0, 0x000, 0), /* MX51_PAD_SD2_CMD__SD2_CMD */
980 IMX_PIN_REG(MX51_PAD_SD2_CLK, 0x7c0, 0x3b8, 2, 0x914, 3), /* MX51_PAD_SD2_CLK__CSPI_SCLK */ 980 IMX_PIN_REG(MX51_PAD_SD2_CLK, 0x7c0, 0x3b8, 2, 0x914, 3), /* MX51_PAD_SD2_CLK__CSPI_SCLK */
diff --git a/drivers/pinctrl/pinctrl-imx6q.c b/drivers/pinctrl/pinctrl-imx6q.c
index 7737d4d71a3c..e9bf71fbedca 100644
--- a/drivers/pinctrl/pinctrl-imx6q.c
+++ b/drivers/pinctrl/pinctrl-imx6q.c
@@ -1950,6 +1950,8 @@ static struct imx_pin_reg imx6q_pin_regs[] = {
1950 IMX_PIN_REG(MX6Q_PAD_SD2_DAT3, 0x0744, 0x035C, 5, 0x0000, 0), /* MX6Q_PAD_SD2_DAT3__GPIO_1_12 */ 1950 IMX_PIN_REG(MX6Q_PAD_SD2_DAT3, 0x0744, 0x035C, 5, 0x0000, 0), /* MX6Q_PAD_SD2_DAT3__GPIO_1_12 */
1951 IMX_PIN_REG(MX6Q_PAD_SD2_DAT3, 0x0744, 0x035C, 6, 0x0000, 0), /* MX6Q_PAD_SD2_DAT3__SJC_DONE */ 1951 IMX_PIN_REG(MX6Q_PAD_SD2_DAT3, 0x0744, 0x035C, 6, 0x0000, 0), /* MX6Q_PAD_SD2_DAT3__SJC_DONE */
1952 IMX_PIN_REG(MX6Q_PAD_SD2_DAT3, 0x0744, 0x035C, 7, 0x0000, 0), /* MX6Q_PAD_SD2_DAT3__ANATOP_TESTO_3 */ 1952 IMX_PIN_REG(MX6Q_PAD_SD2_DAT3, 0x0744, 0x035C, 7, 0x0000, 0), /* MX6Q_PAD_SD2_DAT3__ANATOP_TESTO_3 */
1953 IMX_PIN_REG(MX6Q_PAD_ENET_RX_ER, 0x04EC, 0x01D8, 0, 0x0000, 0), /* MX6Q_PAD_ENET_RX_ER__ANATOP_USBOTG_ID */
1954 IMX_PIN_REG(MX6Q_PAD_GPIO_1, 0x05F4, 0x0224, 3, 0x0000, 0), /* MX6Q_PAD_GPIO_1__ANATOP_USBOTG_ID */
1953}; 1955};
1954 1956
1955/* Pad names for the pinmux subsystem */ 1957/* Pad names for the pinmux subsystem */
diff --git a/drivers/pinctrl/pinctrl-nomadik-db8500.c b/drivers/pinctrl/pinctrl-nomadik-db8500.c
index 8b2022276f71..a39fb7a6fc51 100644
--- a/drivers/pinctrl/pinctrl-nomadik-db8500.c
+++ b/drivers/pinctrl/pinctrl-nomadik-db8500.c
@@ -467,9 +467,12 @@ static const unsigned mc1_a_1_pins[] = { DB8500_PIN_AH16, DB8500_PIN_AG15,
467 DB8500_PIN_AH15 }; 467 DB8500_PIN_AH15 };
468static const unsigned mc1dir_a_1_pins[] = { DB8500_PIN_AH13, DB8500_PIN_AG12, 468static const unsigned mc1dir_a_1_pins[] = { DB8500_PIN_AH13, DB8500_PIN_AG12,
469 DB8500_PIN_AH12, DB8500_PIN_AH11 }; 469 DB8500_PIN_AH12, DB8500_PIN_AH11 };
470static const unsigned hsir_a_1_pins[] = { DB8500_PIN_AG10, DB8500_PIN_AH10 }; 470static const unsigned hsir_a_1_pins[] = { DB8500_PIN_AG10, DB8500_PIN_AH10,
471static const unsigned hsit_a_1_pins[] = { DB8500_PIN_AJ11, DB8500_PIN_AJ9, 471 DB8500_PIN_AJ11 };
472 DB8500_PIN_AH9, DB8500_PIN_AG9, DB8500_PIN_AG8, DB8500_PIN_AF8 }; 472static const unsigned hsit_a_1_pins[] = { DB8500_PIN_AJ9, DB8500_PIN_AH9,
473 DB8500_PIN_AG9, DB8500_PIN_AG8, DB8500_PIN_AF8 };
474static const unsigned hsit_a_2_pins[] = { DB8500_PIN_AJ9, DB8500_PIN_AH9,
475 DB8500_PIN_AG9, DB8500_PIN_AG8 };
473static const unsigned clkout_a_1_pins[] = { DB8500_PIN_AH7, DB8500_PIN_AJ6 }; 476static const unsigned clkout_a_1_pins[] = { DB8500_PIN_AH7, DB8500_PIN_AJ6 };
474static const unsigned clkout_a_2_pins[] = { DB8500_PIN_AG7, DB8500_PIN_AF7 }; 477static const unsigned clkout_a_2_pins[] = { DB8500_PIN_AG7, DB8500_PIN_AF7 };
475static const unsigned usb_a_1_pins[] = { DB8500_PIN_AF28, DB8500_PIN_AE29, 478static const unsigned usb_a_1_pins[] = { DB8500_PIN_AF28, DB8500_PIN_AE29,
@@ -502,15 +505,19 @@ static const unsigned kp_b_1_pins[] = { DB8500_PIN_F3, DB8500_PIN_F1,
502 DB8500_PIN_J3, DB8500_PIN_H2, DB8500_PIN_J2, DB8500_PIN_H1, 505 DB8500_PIN_J3, DB8500_PIN_H2, DB8500_PIN_J2, DB8500_PIN_H1,
503 DB8500_PIN_F4, DB8500_PIN_E3, DB8500_PIN_E4, DB8500_PIN_D2, 506 DB8500_PIN_F4, DB8500_PIN_E3, DB8500_PIN_E4, DB8500_PIN_D2,
504 DB8500_PIN_C1, DB8500_PIN_D3, DB8500_PIN_C2, DB8500_PIN_D5 }; 507 DB8500_PIN_C1, DB8500_PIN_D3, DB8500_PIN_C2, DB8500_PIN_D5 };
508static const unsigned kp_b_2_pins[] = { DB8500_PIN_F3, DB8500_PIN_F1,
509 DB8500_PIN_G3, DB8500_PIN_G2, DB8500_PIN_F4, DB8500_PIN_E3};
505static const unsigned sm_b_1_pins[] = { DB8500_PIN_C6, DB8500_PIN_B3, 510static const unsigned sm_b_1_pins[] = { DB8500_PIN_C6, DB8500_PIN_B3,
506 DB8500_PIN_C4, DB8500_PIN_E6, DB8500_PIN_A3, DB8500_PIN_B6, 511 DB8500_PIN_C4, DB8500_PIN_E6, DB8500_PIN_A3, DB8500_PIN_B6,
507 DB8500_PIN_D6, DB8500_PIN_B7, DB8500_PIN_D7, DB8500_PIN_D8, 512 DB8500_PIN_D6, DB8500_PIN_B7, DB8500_PIN_D7, DB8500_PIN_D8,
508 DB8500_PIN_D9, DB8500_PIN_A5, DB8500_PIN_B4, DB8500_PIN_C8, 513 DB8500_PIN_D9, DB8500_PIN_A5, DB8500_PIN_B4, DB8500_PIN_C8,
509 DB8500_PIN_A12, DB8500_PIN_C10, DB8500_PIN_B10, DB8500_PIN_B9, 514 DB8500_PIN_A12, DB8500_PIN_C10, DB8500_PIN_B10, DB8500_PIN_B9,
510 DB8500_PIN_A9, DB8500_PIN_C7, DB8500_PIN_A7, DB8500_PIN_C5, 515 DB8500_PIN_A9, DB8500_PIN_C7, DB8500_PIN_A7, DB8500_PIN_C5,
511 DB8500_PIN_C9, DB8500_PIN_B14 }; 516 DB8500_PIN_C9 };
512/* This chip select pin can be "ps0" in alt B so have it separately */ 517/* This chip select pin can be "ps0" in alt C so have it separately */
513static const unsigned smcs0_b_1_pins[] = { DB8500_PIN_E8 }; 518static const unsigned smcs0_b_1_pins[] = { DB8500_PIN_E8 };
519/* This chip select pin can be "ps1" in alt C so have it separately */
520static const unsigned smcs1_b_1_pins[] = { DB8500_PIN_B14 };
514static const unsigned ipgpio7_b_1_pins[] = { DB8500_PIN_B11 }; 521static const unsigned ipgpio7_b_1_pins[] = { DB8500_PIN_B11 };
515static const unsigned ipgpio2_b_1_pins[] = { DB8500_PIN_C12 }; 522static const unsigned ipgpio2_b_1_pins[] = { DB8500_PIN_C12 };
516static const unsigned ipgpio3_b_1_pins[] = { DB8500_PIN_C11 }; 523static const unsigned ipgpio3_b_1_pins[] = { DB8500_PIN_C11 };
@@ -572,6 +579,7 @@ static const unsigned mc2rstn_c_1_pins[] = { DB8500_PIN_C8 };
572static const unsigned kp_c_1_pins[] = { DB8500_PIN_C9, DB8500_PIN_B11, 579static const unsigned kp_c_1_pins[] = { DB8500_PIN_C9, DB8500_PIN_B11,
573 DB8500_PIN_C12, DB8500_PIN_C11, DB8500_PIN_D17, DB8500_PIN_D16, 580 DB8500_PIN_C12, DB8500_PIN_C11, DB8500_PIN_D17, DB8500_PIN_D16,
574 DB8500_PIN_C23, DB8500_PIN_D23 }; 581 DB8500_PIN_C23, DB8500_PIN_D23 };
582static const unsigned smps0_c_1_pins[] = { DB8500_PIN_E8 };
575static const unsigned smps1_c_1_pins[] = { DB8500_PIN_B14 }; 583static const unsigned smps1_c_1_pins[] = { DB8500_PIN_B14 };
576static const unsigned u2rxtx_c_3_pins[] = { DB8500_PIN_B17, DB8500_PIN_C16 }; 584static const unsigned u2rxtx_c_3_pins[] = { DB8500_PIN_B17, DB8500_PIN_C16 };
577static const unsigned stmape_c_2_pins[] = { DB8500_PIN_C19, DB8500_PIN_C17, 585static const unsigned stmape_c_2_pins[] = { DB8500_PIN_C19, DB8500_PIN_C17,
@@ -595,6 +603,8 @@ static const unsigned kp_oc1_1_pins[] = { DB8500_PIN_C6, DB8500_PIN_B3,
595 DB8500_PIN_D6, DB8500_PIN_B7 }; 603 DB8500_PIN_D6, DB8500_PIN_B7 };
596static const unsigned spi2_oc1_1_pins[] = { DB8500_PIN_AH13, DB8500_PIN_AG12, 604static const unsigned spi2_oc1_1_pins[] = { DB8500_PIN_AH13, DB8500_PIN_AG12,
597 DB8500_PIN_AH12, DB8500_PIN_AH11 }; 605 DB8500_PIN_AH12, DB8500_PIN_AH11 };
606static const unsigned spi2_oc1_2_pins[] = { DB8500_PIN_AH13, DB8500_PIN_AH12,
607 DB8500_PIN_AH11 };
598 608
599#define DB8500_PIN_GROUP(a,b) { .name = #a, .pins = a##_pins, \ 609#define DB8500_PIN_GROUP(a,b) { .name = #a, .pins = a##_pins, \
600 .npins = ARRAY_SIZE(a##_pins), .altsetting = b } 610 .npins = ARRAY_SIZE(a##_pins), .altsetting = b }
@@ -610,6 +620,8 @@ static const struct nmk_pingroup nmk_db8500_groups[] = {
610 DB8500_PIN_GROUP(msp0tfstck_a_1, NMK_GPIO_ALT_A), 620 DB8500_PIN_GROUP(msp0tfstck_a_1, NMK_GPIO_ALT_A),
611 DB8500_PIN_GROUP(msp0rfsrck_a_1, NMK_GPIO_ALT_A), 621 DB8500_PIN_GROUP(msp0rfsrck_a_1, NMK_GPIO_ALT_A),
612 DB8500_PIN_GROUP(mc0_a_1, NMK_GPIO_ALT_A), 622 DB8500_PIN_GROUP(mc0_a_1, NMK_GPIO_ALT_A),
623 DB8500_PIN_GROUP(mc0_dat47_a_1, NMK_GPIO_ALT_A),
624 DB8500_PIN_GROUP(mc0dat31dir_a_1, NMK_GPIO_ALT_A),
613 DB8500_PIN_GROUP(msp1txrx_a_1, NMK_GPIO_ALT_A), 625 DB8500_PIN_GROUP(msp1txrx_a_1, NMK_GPIO_ALT_A),
614 DB8500_PIN_GROUP(msp1_a_1, NMK_GPIO_ALT_A), 626 DB8500_PIN_GROUP(msp1_a_1, NMK_GPIO_ALT_A),
615 DB8500_PIN_GROUP(lcdb_a_1, NMK_GPIO_ALT_A), 627 DB8500_PIN_GROUP(lcdb_a_1, NMK_GPIO_ALT_A),
@@ -631,6 +643,7 @@ static const struct nmk_pingroup nmk_db8500_groups[] = {
631 DB8500_PIN_GROUP(mc1_a_1, NMK_GPIO_ALT_A), 643 DB8500_PIN_GROUP(mc1_a_1, NMK_GPIO_ALT_A),
632 DB8500_PIN_GROUP(hsir_a_1, NMK_GPIO_ALT_A), 644 DB8500_PIN_GROUP(hsir_a_1, NMK_GPIO_ALT_A),
633 DB8500_PIN_GROUP(hsit_a_1, NMK_GPIO_ALT_A), 645 DB8500_PIN_GROUP(hsit_a_1, NMK_GPIO_ALT_A),
646 DB8500_PIN_GROUP(hsit_a_2, NMK_GPIO_ALT_A),
634 DB8500_PIN_GROUP(clkout_a_1, NMK_GPIO_ALT_A), 647 DB8500_PIN_GROUP(clkout_a_1, NMK_GPIO_ALT_A),
635 DB8500_PIN_GROUP(clkout_a_2, NMK_GPIO_ALT_A), 648 DB8500_PIN_GROUP(clkout_a_2, NMK_GPIO_ALT_A),
636 DB8500_PIN_GROUP(usb_a_1, NMK_GPIO_ALT_A), 649 DB8500_PIN_GROUP(usb_a_1, NMK_GPIO_ALT_A),
@@ -651,8 +664,10 @@ static const struct nmk_pingroup nmk_db8500_groups[] = {
651 DB8500_PIN_GROUP(spi3_b_1, NMK_GPIO_ALT_B), 664 DB8500_PIN_GROUP(spi3_b_1, NMK_GPIO_ALT_B),
652 DB8500_PIN_GROUP(msp1txrx_b_1, NMK_GPIO_ALT_B), 665 DB8500_PIN_GROUP(msp1txrx_b_1, NMK_GPIO_ALT_B),
653 DB8500_PIN_GROUP(kp_b_1, NMK_GPIO_ALT_B), 666 DB8500_PIN_GROUP(kp_b_1, NMK_GPIO_ALT_B),
667 DB8500_PIN_GROUP(kp_b_2, NMK_GPIO_ALT_B),
654 DB8500_PIN_GROUP(sm_b_1, NMK_GPIO_ALT_B), 668 DB8500_PIN_GROUP(sm_b_1, NMK_GPIO_ALT_B),
655 DB8500_PIN_GROUP(smcs0_b_1, NMK_GPIO_ALT_B), 669 DB8500_PIN_GROUP(smcs0_b_1, NMK_GPIO_ALT_B),
670 DB8500_PIN_GROUP(smcs1_b_1, NMK_GPIO_ALT_B),
656 DB8500_PIN_GROUP(ipgpio7_b_1, NMK_GPIO_ALT_B), 671 DB8500_PIN_GROUP(ipgpio7_b_1, NMK_GPIO_ALT_B),
657 DB8500_PIN_GROUP(ipgpio2_b_1, NMK_GPIO_ALT_B), 672 DB8500_PIN_GROUP(ipgpio2_b_1, NMK_GPIO_ALT_B),
658 DB8500_PIN_GROUP(ipgpio3_b_1, NMK_GPIO_ALT_B), 673 DB8500_PIN_GROUP(ipgpio3_b_1, NMK_GPIO_ALT_B),
@@ -693,6 +708,7 @@ static const struct nmk_pingroup nmk_db8500_groups[] = {
693 DB8500_PIN_GROUP(mc5_c_1, NMK_GPIO_ALT_C), 708 DB8500_PIN_GROUP(mc5_c_1, NMK_GPIO_ALT_C),
694 DB8500_PIN_GROUP(mc2rstn_c_1, NMK_GPIO_ALT_C), 709 DB8500_PIN_GROUP(mc2rstn_c_1, NMK_GPIO_ALT_C),
695 DB8500_PIN_GROUP(kp_c_1, NMK_GPIO_ALT_C), 710 DB8500_PIN_GROUP(kp_c_1, NMK_GPIO_ALT_C),
711 DB8500_PIN_GROUP(smps0_c_1, NMK_GPIO_ALT_C),
696 DB8500_PIN_GROUP(smps1_c_1, NMK_GPIO_ALT_C), 712 DB8500_PIN_GROUP(smps1_c_1, NMK_GPIO_ALT_C),
697 DB8500_PIN_GROUP(u2rxtx_c_3, NMK_GPIO_ALT_C), 713 DB8500_PIN_GROUP(u2rxtx_c_3, NMK_GPIO_ALT_C),
698 DB8500_PIN_GROUP(stmape_c_2, NMK_GPIO_ALT_C), 714 DB8500_PIN_GROUP(stmape_c_2, NMK_GPIO_ALT_C),
@@ -709,6 +725,7 @@ static const struct nmk_pingroup nmk_db8500_groups[] = {
709 /* Other alt C1 column, these are still configured as alt C */ 725 /* Other alt C1 column, these are still configured as alt C */
710 DB8500_PIN_GROUP(kp_oc1_1, NMK_GPIO_ALT_C), 726 DB8500_PIN_GROUP(kp_oc1_1, NMK_GPIO_ALT_C),
711 DB8500_PIN_GROUP(spi2_oc1_1, NMK_GPIO_ALT_C), 727 DB8500_PIN_GROUP(spi2_oc1_1, NMK_GPIO_ALT_C),
728 DB8500_PIN_GROUP(spi2_oc1_2, NMK_GPIO_ALT_C),
712}; 729};
713 730
714/* We use this macro to define the groups applicable to a function */ 731/* We use this macro to define the groups applicable to a function */
@@ -731,13 +748,13 @@ DB8500_FUNC_GROUPS(ipi2c, "ipi2c_a_1", "ipi2c_a_2");
731 */ 748 */
732DB8500_FUNC_GROUPS(msp0, "msp0txrx_a_1", "msp0tfstck_a_1", "msp0rfstck_a_1", 749DB8500_FUNC_GROUPS(msp0, "msp0txrx_a_1", "msp0tfstck_a_1", "msp0rfstck_a_1",
733 "msp0txrx_b_1", "msp0sck_b_1"); 750 "msp0txrx_b_1", "msp0sck_b_1");
734DB8500_FUNC_GROUPS(mc0, "mc0_a_1"); 751DB8500_FUNC_GROUPS(mc0, "mc0_a_1", "mc0_dat47_a_1", "mc0dat31dir_a_1");
735/* MSP0 can swap RX/TX like MSP0 but has no SCK pin available */ 752/* MSP0 can swap RX/TX like MSP0 but has no SCK pin available */
736DB8500_FUNC_GROUPS(msp1, "msp1txrx_a_1", "msp1_a_1", "msp1txrx_b_1"); 753DB8500_FUNC_GROUPS(msp1, "msp1txrx_a_1", "msp1_a_1", "msp1txrx_b_1");
737DB8500_FUNC_GROUPS(lcdb, "lcdb_a_1"); 754DB8500_FUNC_GROUPS(lcdb, "lcdb_a_1");
738DB8500_FUNC_GROUPS(lcd, "lcdvsi0_a_1", "lcdvsi1_a_1", "lcd_d0_d7_a_1", 755DB8500_FUNC_GROUPS(lcd, "lcdvsi0_a_1", "lcdvsi1_a_1", "lcd_d0_d7_a_1",
739 "lcd_d8_d11_a_1", "lcd_d12_d23_a_1", "lcd_b_1"); 756 "lcd_d8_d11_a_1", "lcd_d12_d23_a_1", "lcd_b_1");
740DB8500_FUNC_GROUPS(kp, "kp_a_1", "kp_b_1", "kp_c_1", "kp_oc1_1"); 757DB8500_FUNC_GROUPS(kp, "kp_a_1", "kp_b_1", "kp_b_2", "kp_c_1", "kp_oc1_1");
741DB8500_FUNC_GROUPS(mc2, "mc2_a_1", "mc2rstn_c_1"); 758DB8500_FUNC_GROUPS(mc2, "mc2_a_1", "mc2rstn_c_1");
742DB8500_FUNC_GROUPS(ssp1, "ssp1_a_1"); 759DB8500_FUNC_GROUPS(ssp1, "ssp1_a_1");
743DB8500_FUNC_GROUPS(ssp0, "ssp0_a_1"); 760DB8500_FUNC_GROUPS(ssp0, "ssp0_a_1");
@@ -752,7 +769,7 @@ DB8500_FUNC_GROUPS(ipgpio, "ipgpio0_a_1", "ipgpio1_a_1", "ipgpio7_b_1",
752DB8500_FUNC_GROUPS(msp2, "msp2sck_a_1", "msp2_a_1"); 769DB8500_FUNC_GROUPS(msp2, "msp2sck_a_1", "msp2_a_1");
753DB8500_FUNC_GROUPS(mc4, "mc4_a_1", "mc4rstn_c_1"); 770DB8500_FUNC_GROUPS(mc4, "mc4_a_1", "mc4rstn_c_1");
754DB8500_FUNC_GROUPS(mc1, "mc1_a_1", "mc1dir_a_1"); 771DB8500_FUNC_GROUPS(mc1, "mc1_a_1", "mc1dir_a_1");
755DB8500_FUNC_GROUPS(hsi, "hsir1_a_1", "hsit1_a_1"); 772DB8500_FUNC_GROUPS(hsi, "hsir_a_1", "hsit_a_1", "hsit_a_2");
756DB8500_FUNC_GROUPS(clkout, "clkout_a_1", "clkout_a_2", "clkout_c_1"); 773DB8500_FUNC_GROUPS(clkout, "clkout_a_1", "clkout_a_2", "clkout_c_1");
757DB8500_FUNC_GROUPS(usb, "usb_a_1"); 774DB8500_FUNC_GROUPS(usb, "usb_a_1");
758DB8500_FUNC_GROUPS(trig, "trig_b_1"); 775DB8500_FUNC_GROUPS(trig, "trig_b_1");
@@ -768,7 +785,8 @@ DB8500_FUNC_GROUPS(uartmod, "uartmodtx_b_1", "uartmodrx_b_1", "uartmodrx_b_2",
768DB8500_FUNC_GROUPS(stmmod, "stmmod_b_1", "stmmod_c_1"); 785DB8500_FUNC_GROUPS(stmmod, "stmmod_b_1", "stmmod_c_1");
769DB8500_FUNC_GROUPS(spi3, "spi3_b_1"); 786DB8500_FUNC_GROUPS(spi3, "spi3_b_1");
770/* Select between CS0 on alt B or PS1 on alt C */ 787/* Select between CS0 on alt B or PS1 on alt C */
771DB8500_FUNC_GROUPS(sm, "sm_b_1", "smcs0_b_1", "smcleale_c_1", "smps1_c_1"); 788DB8500_FUNC_GROUPS(sm, "sm_b_1", "smcs0_b_1", "smcs1_b_1", "smcleale_c_1",
789 "smps0_c_1", "smps1_c_1");
772DB8500_FUNC_GROUPS(lcda, "lcdaclk_b_1", "lcda_b_1"); 790DB8500_FUNC_GROUPS(lcda, "lcdaclk_b_1", "lcda_b_1");
773DB8500_FUNC_GROUPS(ddrtrig, "ddrtrig_b_1"); 791DB8500_FUNC_GROUPS(ddrtrig, "ddrtrig_b_1");
774DB8500_FUNC_GROUPS(pwl, "pwl_b_1", "pwl_b_2", "pwl_b_3", "pwl_b_4"); 792DB8500_FUNC_GROUPS(pwl, "pwl_b_1", "pwl_b_2", "pwl_b_3", "pwl_b_4");
@@ -783,7 +801,7 @@ DB8500_FUNC_GROUPS(mc5, "mc5_c_1");
783DB8500_FUNC_GROUPS(usbsim, "usbsim_c_1", "usbsim_c_2"); 801DB8500_FUNC_GROUPS(usbsim, "usbsim_c_1", "usbsim_c_2");
784DB8500_FUNC_GROUPS(i2c3, "i2c3_c_1", "i2c3_c_2"); 802DB8500_FUNC_GROUPS(i2c3, "i2c3_c_1", "i2c3_c_2");
785DB8500_FUNC_GROUPS(spi0, "spi0_c_1"); 803DB8500_FUNC_GROUPS(spi0, "spi0_c_1");
786DB8500_FUNC_GROUPS(spi2, "spi2_oc1_1"); 804DB8500_FUNC_GROUPS(spi2, "spi2_oc1_1", "spi2_oc1_2");
787 805
788#define FUNCTION(fname) \ 806#define FUNCTION(fname) \
789 { \ 807 { \
diff --git a/drivers/pinctrl/pinctrl-nomadik.c b/drivers/pinctrl/pinctrl-nomadik.c
index 3e7e47d6b385..3dde6537adb8 100644
--- a/drivers/pinctrl/pinctrl-nomadik.c
+++ b/drivers/pinctrl/pinctrl-nomadik.c
@@ -434,7 +434,7 @@ static int __nmk_config_pins(pin_cfg_t *cfgs, int num, bool sleep)
434/** 434/**
435 * nmk_config_pin - configure a pin's mux attributes 435 * nmk_config_pin - configure a pin's mux attributes
436 * @cfg: pin confguration 436 * @cfg: pin confguration
437 * 437 * @sleep: Non-zero to apply the sleep mode configuration
438 * Configures a pin's mode (alternate function or GPIO), its pull up status, 438 * Configures a pin's mode (alternate function or GPIO), its pull up status,
439 * and its sleep mode based on the specified configuration. The @cfg is 439 * and its sleep mode based on the specified configuration. The @cfg is
440 * usually one of the SoC specific macros defined in mach/<soc>-pins.h. These 440 * usually one of the SoC specific macros defined in mach/<soc>-pins.h. These
@@ -1194,11 +1194,11 @@ static int __devinit nmk_gpio_probe(struct platform_device *dev)
1194 } 1194 }
1195 1195
1196 if (np) { 1196 if (np) {
1197 pdata = kzalloc(sizeof(*pdata), GFP_KERNEL); 1197 pdata = devm_kzalloc(&dev->dev, sizeof(*pdata), GFP_KERNEL);
1198 if (!pdata) 1198 if (!pdata)
1199 return -ENOMEM; 1199 return -ENOMEM;
1200 1200
1201 if (of_get_property(np, "supports-sleepmode", NULL)) 1201 if (of_get_property(np, "st,supports-sleepmode", NULL))
1202 pdata->supports_sleepmode = true; 1202 pdata->supports_sleepmode = true;
1203 1203
1204 if (of_property_read_u32(np, "gpio-bank", &dev->id)) { 1204 if (of_property_read_u32(np, "gpio-bank", &dev->id)) {
@@ -1229,29 +1229,23 @@ static int __devinit nmk_gpio_probe(struct platform_device *dev)
1229 goto out; 1229 goto out;
1230 } 1230 }
1231 1231
1232 if (request_mem_region(res->start, resource_size(res), 1232 base = devm_request_and_ioremap(&dev->dev, res);
1233 dev_name(&dev->dev)) == NULL) {
1234 ret = -EBUSY;
1235 goto out;
1236 }
1237
1238 base = ioremap(res->start, resource_size(res));
1239 if (!base) { 1233 if (!base) {
1240 ret = -ENOMEM; 1234 ret = -ENOMEM;
1241 goto out_release; 1235 goto out;
1242 } 1236 }
1243 1237
1244 clk = clk_get(&dev->dev, NULL); 1238 clk = devm_clk_get(&dev->dev, NULL);
1245 if (IS_ERR(clk)) { 1239 if (IS_ERR(clk)) {
1246 ret = PTR_ERR(clk); 1240 ret = PTR_ERR(clk);
1247 goto out_unmap; 1241 goto out;
1248 } 1242 }
1249 clk_prepare(clk); 1243 clk_prepare(clk);
1250 1244
1251 nmk_chip = kzalloc(sizeof(*nmk_chip), GFP_KERNEL); 1245 nmk_chip = devm_kzalloc(&dev->dev, sizeof(*nmk_chip), GFP_KERNEL);
1252 if (!nmk_chip) { 1246 if (!nmk_chip) {
1253 ret = -ENOMEM; 1247 ret = -ENOMEM;
1254 goto out_clk; 1248 goto out;
1255 } 1249 }
1256 1250
1257 /* 1251 /*
@@ -1286,7 +1280,7 @@ static int __devinit nmk_gpio_probe(struct platform_device *dev)
1286 1280
1287 ret = gpiochip_add(&nmk_chip->chip); 1281 ret = gpiochip_add(&nmk_chip->chip);
1288 if (ret) 1282 if (ret)
1289 goto out_free; 1283 goto out;
1290 1284
1291 BUG_ON(nmk_chip->bank >= ARRAY_SIZE(nmk_gpio_chips)); 1285 BUG_ON(nmk_chip->bank >= ARRAY_SIZE(nmk_gpio_chips));
1292 1286
@@ -1298,9 +1292,9 @@ static int __devinit nmk_gpio_probe(struct platform_device *dev)
1298 NOMADIK_GPIO_TO_IRQ(pdata->first_gpio), 1292 NOMADIK_GPIO_TO_IRQ(pdata->first_gpio),
1299 0, &nmk_gpio_irq_simple_ops, nmk_chip); 1293 0, &nmk_gpio_irq_simple_ops, nmk_chip);
1300 if (!nmk_chip->domain) { 1294 if (!nmk_chip->domain) {
1301 pr_err("%s: Failed to create irqdomain\n", np->full_name); 1295 dev_err(&dev->dev, "failed to create irqdomain\n");
1302 ret = -ENOSYS; 1296 ret = -ENOSYS;
1303 goto out_free; 1297 goto out;
1304 } 1298 }
1305 1299
1306 nmk_gpio_init_irq(nmk_chip); 1300 nmk_gpio_init_irq(nmk_chip);
@@ -1309,20 +1303,9 @@ static int __devinit nmk_gpio_probe(struct platform_device *dev)
1309 1303
1310 return 0; 1304 return 0;
1311 1305
1312out_free:
1313 kfree(nmk_chip);
1314out_clk:
1315 clk_disable(clk);
1316 clk_put(clk);
1317out_unmap:
1318 iounmap(base);
1319out_release:
1320 release_mem_region(res->start, resource_size(res));
1321out: 1306out:
1322 dev_err(&dev->dev, "Failure %i for GPIO %i-%i\n", ret, 1307 dev_err(&dev->dev, "Failure %i for GPIO %i-%i\n", ret,
1323 pdata->first_gpio, pdata->first_gpio+31); 1308 pdata->first_gpio, pdata->first_gpio+31);
1324 if (np)
1325 kfree(pdata);
1326 1309
1327 return ret; 1310 return ret;
1328} 1311}
@@ -1748,7 +1731,6 @@ static int __devinit nmk_pinctrl_probe(struct platform_device *pdev)
1748 for (i = 0; i < npct->soc->gpio_num_ranges; i++) { 1731 for (i = 0; i < npct->soc->gpio_num_ranges; i++) {
1749 if (!nmk_gpio_chips[i]) { 1732 if (!nmk_gpio_chips[i]) {
1750 dev_warn(&pdev->dev, "GPIO chip %d not registered yet\n", i); 1733 dev_warn(&pdev->dev, "GPIO chip %d not registered yet\n", i);
1751 devm_kfree(&pdev->dev, npct);
1752 return -EPROBE_DEFER; 1734 return -EPROBE_DEFER;
1753 } 1735 }
1754 npct->soc->gpio_ranges[i].gc = &nmk_gpio_chips[i]->chip; 1736 npct->soc->gpio_ranges[i].gc = &nmk_gpio_chips[i]->chip;
diff --git a/drivers/pinctrl/pinctrl-single.c b/drivers/pinctrl/pinctrl-single.c
new file mode 100644
index 000000000000..76a4260f20f3
--- /dev/null
+++ b/drivers/pinctrl/pinctrl-single.c
@@ -0,0 +1,987 @@
1/*
2 * Generic device tree based pinctrl driver for one register per pin
3 * type pinmux controllers
4 *
5 * Copyright (C) 2012 Texas Instruments, Inc.
6 *
7 * This file is licensed under the terms of the GNU General Public
8 * License version 2. This program is licensed "as is" without any
9 * warranty of any kind, whether express or implied.
10 */
11
12#include <linux/init.h>
13#include <linux/module.h>
14#include <linux/io.h>
15#include <linux/slab.h>
16#include <linux/err.h>
17#include <linux/list.h>
18
19#include <linux/of.h>
20#include <linux/of_device.h>
21#include <linux/of_address.h>
22
23#include <linux/pinctrl/pinctrl.h>
24#include <linux/pinctrl/pinmux.h>
25
26#include "core.h"
27
28#define DRIVER_NAME "pinctrl-single"
29#define PCS_MUX_NAME "pinctrl-single,pins"
30#define PCS_REG_NAME_LEN ((sizeof(unsigned long) * 2) + 1)
31#define PCS_OFF_DISABLED ~0U
32
33/**
34 * struct pcs_pingroup - pingroups for a function
35 * @np: pingroup device node pointer
36 * @name: pingroup name
37 * @gpins: array of the pins in the group
38 * @ngpins: number of pins in the group
39 * @node: list node
40 */
41struct pcs_pingroup {
42 struct device_node *np;
43 const char *name;
44 int *gpins;
45 int ngpins;
46 struct list_head node;
47};
48
49/**
50 * struct pcs_func_vals - mux function register offset and value pair
51 * @reg: register virtual address
52 * @val: register value
53 */
54struct pcs_func_vals {
55 void __iomem *reg;
56 unsigned val;
57};
58
59/**
60 * struct pcs_function - pinctrl function
61 * @name: pinctrl function name
62 * @vals: register and vals array
63 * @nvals: number of entries in vals array
64 * @pgnames: array of pingroup names the function uses
65 * @npgnames: number of pingroup names the function uses
66 * @node: list node
67 */
68struct pcs_function {
69 const char *name;
70 struct pcs_func_vals *vals;
71 unsigned nvals;
72 const char **pgnames;
73 int npgnames;
74 struct list_head node;
75};
76
77/**
78 * struct pcs_data - wrapper for data needed by pinctrl framework
79 * @pa: pindesc array
80 * @cur: index to current element
81 *
82 * REVISIT: We should be able to drop this eventually by adding
83 * support for registering pins individually in the pinctrl
84 * framework for those drivers that don't need a static array.
85 */
86struct pcs_data {
87 struct pinctrl_pin_desc *pa;
88 int cur;
89};
90
91/**
92 * struct pcs_name - register name for a pin
93 * @name: name of the pinctrl register
94 *
95 * REVISIT: We may want to make names optional in the pinctrl
96 * framework as some drivers may not care about pin names to
97 * avoid kernel bloat. The pin names can be deciphered by user
98 * space tools using debugfs based on the register address and
99 * SoC packaging information.
100 */
101struct pcs_name {
102 char name[PCS_REG_NAME_LEN];
103};
104
105/**
106 * struct pcs_device - pinctrl device instance
107 * @res: resources
108 * @base: virtual address of the controller
109 * @size: size of the ioremapped area
110 * @dev: device entry
111 * @pctl: pin controller device
112 * @mutex: mutex protecting the lists
113 * @width: bits per mux register
114 * @fmask: function register mask
115 * @fshift: function register shift
116 * @foff: value to turn mux off
117 * @fmax: max number of functions in fmask
118 * @names: array of register names for pins
119 * @pins: physical pins on the SoC
120 * @pgtree: pingroup index radix tree
121 * @ftree: function index radix tree
122 * @pingroups: list of pingroups
123 * @functions: list of functions
124 * @ngroups: number of pingroups
125 * @nfuncs: number of functions
126 * @desc: pin controller descriptor
127 * @read: register read function to use
128 * @write: register write function to use
129 */
130struct pcs_device {
131 struct resource *res;
132 void __iomem *base;
133 unsigned size;
134 struct device *dev;
135 struct pinctrl_dev *pctl;
136 struct mutex mutex;
137 unsigned width;
138 unsigned fmask;
139 unsigned fshift;
140 unsigned foff;
141 unsigned fmax;
142 struct pcs_name *names;
143 struct pcs_data pins;
144 struct radix_tree_root pgtree;
145 struct radix_tree_root ftree;
146 struct list_head pingroups;
147 struct list_head functions;
148 unsigned ngroups;
149 unsigned nfuncs;
150 struct pinctrl_desc desc;
151 unsigned (*read)(void __iomem *reg);
152 void (*write)(unsigned val, void __iomem *reg);
153};
154
155/*
156 * REVISIT: Reads and writes could eventually use regmap or something
157 * generic. But at least on omaps, some mux registers are performance
158 * critical as they may need to be remuxed every time before and after
159 * idle. Adding tests for register access width for every read and
160 * write like regmap is doing is not desired, and caching the registers
161 * does not help in this case.
162 */
163
164static unsigned __maybe_unused pcs_readb(void __iomem *reg)
165{
166 return readb(reg);
167}
168
169static unsigned __maybe_unused pcs_readw(void __iomem *reg)
170{
171 return readw(reg);
172}
173
174static unsigned __maybe_unused pcs_readl(void __iomem *reg)
175{
176 return readl(reg);
177}
178
179static void __maybe_unused pcs_writeb(unsigned val, void __iomem *reg)
180{
181 writeb(val, reg);
182}
183
184static void __maybe_unused pcs_writew(unsigned val, void __iomem *reg)
185{
186 writew(val, reg);
187}
188
189static void __maybe_unused pcs_writel(unsigned val, void __iomem *reg)
190{
191 writel(val, reg);
192}
193
194static int pcs_get_groups_count(struct pinctrl_dev *pctldev)
195{
196 struct pcs_device *pcs;
197
198 pcs = pinctrl_dev_get_drvdata(pctldev);
199
200 return pcs->ngroups;
201}
202
203static const char *pcs_get_group_name(struct pinctrl_dev *pctldev,
204 unsigned gselector)
205{
206 struct pcs_device *pcs;
207 struct pcs_pingroup *group;
208
209 pcs = pinctrl_dev_get_drvdata(pctldev);
210 group = radix_tree_lookup(&pcs->pgtree, gselector);
211 if (!group) {
212 dev_err(pcs->dev, "%s could not find pingroup%i\n",
213 __func__, gselector);
214 return NULL;
215 }
216
217 return group->name;
218}
219
220static int pcs_get_group_pins(struct pinctrl_dev *pctldev,
221 unsigned gselector,
222 const unsigned **pins,
223 unsigned *npins)
224{
225 struct pcs_device *pcs;
226 struct pcs_pingroup *group;
227
228 pcs = pinctrl_dev_get_drvdata(pctldev);
229 group = radix_tree_lookup(&pcs->pgtree, gselector);
230 if (!group) {
231 dev_err(pcs->dev, "%s could not find pingroup%i\n",
232 __func__, gselector);
233 return -EINVAL;
234 }
235
236 *pins = group->gpins;
237 *npins = group->ngpins;
238
239 return 0;
240}
241
242static void pcs_pin_dbg_show(struct pinctrl_dev *pctldev,
243 struct seq_file *s,
244 unsigned offset)
245{
246 seq_printf(s, " " DRIVER_NAME);
247}
248
249static void pcs_dt_free_map(struct pinctrl_dev *pctldev,
250 struct pinctrl_map *map, unsigned num_maps)
251{
252 struct pcs_device *pcs;
253
254 pcs = pinctrl_dev_get_drvdata(pctldev);
255 devm_kfree(pcs->dev, map);
256}
257
258static int pcs_dt_node_to_map(struct pinctrl_dev *pctldev,
259 struct device_node *np_config,
260 struct pinctrl_map **map, unsigned *num_maps);
261
262static struct pinctrl_ops pcs_pinctrl_ops = {
263 .get_groups_count = pcs_get_groups_count,
264 .get_group_name = pcs_get_group_name,
265 .get_group_pins = pcs_get_group_pins,
266 .pin_dbg_show = pcs_pin_dbg_show,
267 .dt_node_to_map = pcs_dt_node_to_map,
268 .dt_free_map = pcs_dt_free_map,
269};
270
271static int pcs_get_functions_count(struct pinctrl_dev *pctldev)
272{
273 struct pcs_device *pcs;
274
275 pcs = pinctrl_dev_get_drvdata(pctldev);
276
277 return pcs->nfuncs;
278}
279
280static const char *pcs_get_function_name(struct pinctrl_dev *pctldev,
281 unsigned fselector)
282{
283 struct pcs_device *pcs;
284 struct pcs_function *func;
285
286 pcs = pinctrl_dev_get_drvdata(pctldev);
287 func = radix_tree_lookup(&pcs->ftree, fselector);
288 if (!func) {
289 dev_err(pcs->dev, "%s could not find function%i\n",
290 __func__, fselector);
291 return NULL;
292 }
293
294 return func->name;
295}
296
297static int pcs_get_function_groups(struct pinctrl_dev *pctldev,
298 unsigned fselector,
299 const char * const **groups,
300 unsigned * const ngroups)
301{
302 struct pcs_device *pcs;
303 struct pcs_function *func;
304
305 pcs = pinctrl_dev_get_drvdata(pctldev);
306 func = radix_tree_lookup(&pcs->ftree, fselector);
307 if (!func) {
308 dev_err(pcs->dev, "%s could not find function%i\n",
309 __func__, fselector);
310 return -EINVAL;
311 }
312 *groups = func->pgnames;
313 *ngroups = func->npgnames;
314
315 return 0;
316}
317
318static int pcs_enable(struct pinctrl_dev *pctldev, unsigned fselector,
319 unsigned group)
320{
321 struct pcs_device *pcs;
322 struct pcs_function *func;
323 int i;
324
325 pcs = pinctrl_dev_get_drvdata(pctldev);
326 func = radix_tree_lookup(&pcs->ftree, fselector);
327 if (!func)
328 return -EINVAL;
329
330 dev_dbg(pcs->dev, "enabling %s function%i\n",
331 func->name, fselector);
332
333 for (i = 0; i < func->nvals; i++) {
334 struct pcs_func_vals *vals;
335 unsigned val;
336
337 vals = &func->vals[i];
338 val = pcs->read(vals->reg);
339 val &= ~pcs->fmask;
340 val |= vals->val;
341 pcs->write(val, vals->reg);
342 }
343
344 return 0;
345}
346
347static void pcs_disable(struct pinctrl_dev *pctldev, unsigned fselector,
348 unsigned group)
349{
350 struct pcs_device *pcs;
351 struct pcs_function *func;
352 int i;
353
354 pcs = pinctrl_dev_get_drvdata(pctldev);
355 func = radix_tree_lookup(&pcs->ftree, fselector);
356 if (!func) {
357 dev_err(pcs->dev, "%s could not find function%i\n",
358 __func__, fselector);
359 return;
360 }
361
362 /*
363 * Ignore disable if function-off is not specified. Some hardware
364 * does not have clearly defined disable function. For pin specific
365 * off modes, you can use alternate named states as described in
366 * pinctrl-bindings.txt.
367 */
368 if (pcs->foff == PCS_OFF_DISABLED) {
369 dev_dbg(pcs->dev, "ignoring disable for %s function%i\n",
370 func->name, fselector);
371 return;
372 }
373
374 dev_dbg(pcs->dev, "disabling function%i %s\n",
375 fselector, func->name);
376
377 for (i = 0; i < func->nvals; i++) {
378 struct pcs_func_vals *vals;
379 unsigned val;
380
381 vals = &func->vals[i];
382 val = pcs->read(vals->reg);
383 val &= ~pcs->fmask;
384 val |= pcs->foff << pcs->fshift;
385 pcs->write(val, vals->reg);
386 }
387}
388
389static int pcs_request_gpio(struct pinctrl_dev *pctldev,
390 struct pinctrl_gpio_range *range, unsigned offset)
391{
392 return -ENOTSUPP;
393}
394
395static struct pinmux_ops pcs_pinmux_ops = {
396 .get_functions_count = pcs_get_functions_count,
397 .get_function_name = pcs_get_function_name,
398 .get_function_groups = pcs_get_function_groups,
399 .enable = pcs_enable,
400 .disable = pcs_disable,
401 .gpio_request_enable = pcs_request_gpio,
402};
403
404static int pcs_pinconf_get(struct pinctrl_dev *pctldev,
405 unsigned pin, unsigned long *config)
406{
407 return -ENOTSUPP;
408}
409
410static int pcs_pinconf_set(struct pinctrl_dev *pctldev,
411 unsigned pin, unsigned long config)
412{
413 return -ENOTSUPP;
414}
415
416static int pcs_pinconf_group_get(struct pinctrl_dev *pctldev,
417 unsigned group, unsigned long *config)
418{
419 return -ENOTSUPP;
420}
421
422static int pcs_pinconf_group_set(struct pinctrl_dev *pctldev,
423 unsigned group, unsigned long config)
424{
425 return -ENOTSUPP;
426}
427
428static void pcs_pinconf_dbg_show(struct pinctrl_dev *pctldev,
429 struct seq_file *s, unsigned offset)
430{
431}
432
433static void pcs_pinconf_group_dbg_show(struct pinctrl_dev *pctldev,
434 struct seq_file *s, unsigned selector)
435{
436}
437
438static struct pinconf_ops pcs_pinconf_ops = {
439 .pin_config_get = pcs_pinconf_get,
440 .pin_config_set = pcs_pinconf_set,
441 .pin_config_group_get = pcs_pinconf_group_get,
442 .pin_config_group_set = pcs_pinconf_group_set,
443 .pin_config_dbg_show = pcs_pinconf_dbg_show,
444 .pin_config_group_dbg_show = pcs_pinconf_group_dbg_show,
445};
446
447/**
448 * pcs_add_pin() - add a pin to the static per controller pin array
449 * @pcs: pcs driver instance
450 * @offset: register offset from base
451 */
452static int __devinit pcs_add_pin(struct pcs_device *pcs, unsigned offset)
453{
454 struct pinctrl_pin_desc *pin;
455 struct pcs_name *pn;
456 int i;
457
458 i = pcs->pins.cur;
459 if (i >= pcs->desc.npins) {
460 dev_err(pcs->dev, "too many pins, max %i\n",
461 pcs->desc.npins);
462 return -ENOMEM;
463 }
464
465 pin = &pcs->pins.pa[i];
466 pn = &pcs->names[i];
467 sprintf(pn->name, "%lx",
468 (unsigned long)pcs->res->start + offset);
469 pin->name = pn->name;
470 pin->number = i;
471 pcs->pins.cur++;
472
473 return i;
474}
475
476/**
477 * pcs_allocate_pin_table() - adds all the pins for the pinctrl driver
478 * @pcs: pcs driver instance
479 *
480 * In case of errors, resources are freed in pcs_free_resources.
481 *
482 * If your hardware needs holes in the address space, then just set
483 * up multiple driver instances.
484 */
485static int __devinit pcs_allocate_pin_table(struct pcs_device *pcs)
486{
487 int mux_bytes, nr_pins, i;
488
489 mux_bytes = pcs->width / BITS_PER_BYTE;
490 nr_pins = pcs->size / mux_bytes;
491
492 dev_dbg(pcs->dev, "allocating %i pins\n", nr_pins);
493 pcs->pins.pa = devm_kzalloc(pcs->dev,
494 sizeof(*pcs->pins.pa) * nr_pins,
495 GFP_KERNEL);
496 if (!pcs->pins.pa)
497 return -ENOMEM;
498
499 pcs->names = devm_kzalloc(pcs->dev,
500 sizeof(struct pcs_name) * nr_pins,
501 GFP_KERNEL);
502 if (!pcs->names)
503 return -ENOMEM;
504
505 pcs->desc.pins = pcs->pins.pa;
506 pcs->desc.npins = nr_pins;
507
508 for (i = 0; i < pcs->desc.npins; i++) {
509 unsigned offset;
510 int res;
511
512 offset = i * mux_bytes;
513 res = pcs_add_pin(pcs, offset);
514 if (res < 0) {
515 dev_err(pcs->dev, "error adding pins: %i\n", res);
516 return res;
517 }
518 }
519
520 return 0;
521}
522
523/**
524 * pcs_add_function() - adds a new function to the function list
525 * @pcs: pcs driver instance
526 * @np: device node of the mux entry
527 * @name: name of the function
528 * @vals: array of mux register value pairs used by the function
529 * @nvals: number of mux register value pairs
530 * @pgnames: array of pingroup names for the function
531 * @npgnames: number of pingroup names
532 */
533static struct pcs_function *pcs_add_function(struct pcs_device *pcs,
534 struct device_node *np,
535 const char *name,
536 struct pcs_func_vals *vals,
537 unsigned nvals,
538 const char **pgnames,
539 unsigned npgnames)
540{
541 struct pcs_function *function;
542
543 function = devm_kzalloc(pcs->dev, sizeof(*function), GFP_KERNEL);
544 if (!function)
545 return NULL;
546
547 function->name = name;
548 function->vals = vals;
549 function->nvals = nvals;
550 function->pgnames = pgnames;
551 function->npgnames = npgnames;
552
553 mutex_lock(&pcs->mutex);
554 list_add_tail(&function->node, &pcs->functions);
555 radix_tree_insert(&pcs->ftree, pcs->nfuncs, function);
556 pcs->nfuncs++;
557 mutex_unlock(&pcs->mutex);
558
559 return function;
560}
561
562static void pcs_remove_function(struct pcs_device *pcs,
563 struct pcs_function *function)
564{
565 int i;
566
567 mutex_lock(&pcs->mutex);
568 for (i = 0; i < pcs->nfuncs; i++) {
569 struct pcs_function *found;
570
571 found = radix_tree_lookup(&pcs->ftree, i);
572 if (found == function)
573 radix_tree_delete(&pcs->ftree, i);
574 }
575 list_del(&function->node);
576 mutex_unlock(&pcs->mutex);
577}
578
579/**
580 * pcs_add_pingroup() - add a pingroup to the pingroup list
581 * @pcs: pcs driver instance
582 * @np: device node of the mux entry
583 * @name: name of the pingroup
584 * @gpins: array of the pins that belong to the group
585 * @ngpins: number of pins in the group
586 */
587static int pcs_add_pingroup(struct pcs_device *pcs,
588 struct device_node *np,
589 const char *name,
590 int *gpins,
591 int ngpins)
592{
593 struct pcs_pingroup *pingroup;
594
595 pingroup = devm_kzalloc(pcs->dev, sizeof(*pingroup), GFP_KERNEL);
596 if (!pingroup)
597 return -ENOMEM;
598
599 pingroup->name = name;
600 pingroup->np = np;
601 pingroup->gpins = gpins;
602 pingroup->ngpins = ngpins;
603
604 mutex_lock(&pcs->mutex);
605 list_add_tail(&pingroup->node, &pcs->pingroups);
606 radix_tree_insert(&pcs->pgtree, pcs->ngroups, pingroup);
607 pcs->ngroups++;
608 mutex_unlock(&pcs->mutex);
609
610 return 0;
611}
612
613/**
614 * pcs_get_pin_by_offset() - get a pin index based on the register offset
615 * @pcs: pcs driver instance
616 * @offset: register offset from the base
617 *
618 * Note that this is OK as long as the pins are in a static array.
619 */
620static int pcs_get_pin_by_offset(struct pcs_device *pcs, unsigned offset)
621{
622 unsigned index;
623
624 if (offset >= pcs->size) {
625 dev_err(pcs->dev, "mux offset out of range: 0x%x (0x%x)\n",
626 offset, pcs->size);
627 return -EINVAL;
628 }
629
630 index = offset / (pcs->width / BITS_PER_BYTE);
631
632 return index;
633}
634
635/**
636 * smux_parse_one_pinctrl_entry() - parses a device tree mux entry
637 * @pcs: pinctrl driver instance
638 * @np: device node of the mux entry
639 * @map: map entry
640 * @pgnames: pingroup names
641 *
642 * Note that this binding currently supports only sets of one register + value.
643 *
644 * Also note that this driver tries to avoid understanding pin and function
645 * names because of the extra bloat they would cause especially in the case of
646 * a large number of pins. This driver just sets what is specified for the board
647 * in the .dts file. Further user space debugging tools can be developed to
648 * decipher the pin and function names using debugfs.
649 *
650 * If you are concerned about the boot time, set up the static pins in
651 * the bootloader, and only set up selected pins as device tree entries.
652 */
653static int pcs_parse_one_pinctrl_entry(struct pcs_device *pcs,
654 struct device_node *np,
655 struct pinctrl_map **map,
656 const char **pgnames)
657{
658 struct pcs_func_vals *vals;
659 const __be32 *mux;
660 int size, rows, *pins, index = 0, found = 0, res = -ENOMEM;
661 struct pcs_function *function;
662
663 mux = of_get_property(np, PCS_MUX_NAME, &size);
664 if ((!mux) || (size < sizeof(*mux) * 2)) {
665 dev_err(pcs->dev, "bad data for mux %s\n",
666 np->name);
667 return -EINVAL;
668 }
669
670 size /= sizeof(*mux); /* Number of elements in array */
671 rows = size / 2; /* Each row is a key value pair */
672
673 vals = devm_kzalloc(pcs->dev, sizeof(*vals) * rows, GFP_KERNEL);
674 if (!vals)
675 return -ENOMEM;
676
677 pins = devm_kzalloc(pcs->dev, sizeof(*pins) * rows, GFP_KERNEL);
678 if (!pins)
679 goto free_vals;
680
681 while (index < size) {
682 unsigned offset, val;
683 int pin;
684
685 offset = be32_to_cpup(mux + index++);
686 val = be32_to_cpup(mux + index++);
687 vals[found].reg = pcs->base + offset;
688 vals[found].val = val;
689
690 pin = pcs_get_pin_by_offset(pcs, offset);
691 if (pin < 0) {
692 dev_err(pcs->dev,
693 "could not add functions for %s %ux\n",
694 np->name, offset);
695 break;
696 }
697 pins[found++] = pin;
698 }
699
700 pgnames[0] = np->name;
701 function = pcs_add_function(pcs, np, np->name, vals, found, pgnames, 1);
702 if (!function)
703 goto free_pins;
704
705 res = pcs_add_pingroup(pcs, np, np->name, pins, found);
706 if (res < 0)
707 goto free_function;
708
709 (*map)->type = PIN_MAP_TYPE_MUX_GROUP;
710 (*map)->data.mux.group = np->name;
711 (*map)->data.mux.function = np->name;
712
713 return 0;
714
715free_function:
716 pcs_remove_function(pcs, function);
717
718free_pins:
719 devm_kfree(pcs->dev, pins);
720
721free_vals:
722 devm_kfree(pcs->dev, vals);
723
724 return res;
725}
726/**
727 * pcs_dt_node_to_map() - allocates and parses pinctrl maps
728 * @pctldev: pinctrl instance
729 * @np_config: device tree pinmux entry
730 * @map: array of map entries
731 * @num_maps: number of maps
732 */
733static int pcs_dt_node_to_map(struct pinctrl_dev *pctldev,
734 struct device_node *np_config,
735 struct pinctrl_map **map, unsigned *num_maps)
736{
737 struct pcs_device *pcs;
738 const char **pgnames;
739 int ret;
740
741 pcs = pinctrl_dev_get_drvdata(pctldev);
742
743 *map = devm_kzalloc(pcs->dev, sizeof(**map), GFP_KERNEL);
744 if (!map)
745 return -ENOMEM;
746
747 *num_maps = 0;
748
749 pgnames = devm_kzalloc(pcs->dev, sizeof(*pgnames), GFP_KERNEL);
750 if (!pgnames) {
751 ret = -ENOMEM;
752 goto free_map;
753 }
754
755 ret = pcs_parse_one_pinctrl_entry(pcs, np_config, map, pgnames);
756 if (ret < 0) {
757 dev_err(pcs->dev, "no pins entries for %s\n",
758 np_config->name);
759 goto free_pgnames;
760 }
761 *num_maps = 1;
762
763 return 0;
764
765free_pgnames:
766 devm_kfree(pcs->dev, pgnames);
767free_map:
768 devm_kfree(pcs->dev, *map);
769
770 return ret;
771}
772
773/**
774 * pcs_free_funcs() - free memory used by functions
775 * @pcs: pcs driver instance
776 */
777static void pcs_free_funcs(struct pcs_device *pcs)
778{
779 struct list_head *pos, *tmp;
780 int i;
781
782 mutex_lock(&pcs->mutex);
783 for (i = 0; i < pcs->nfuncs; i++) {
784 struct pcs_function *func;
785
786 func = radix_tree_lookup(&pcs->ftree, i);
787 if (!func)
788 continue;
789 radix_tree_delete(&pcs->ftree, i);
790 }
791 list_for_each_safe(pos, tmp, &pcs->functions) {
792 struct pcs_function *function;
793
794 function = list_entry(pos, struct pcs_function, node);
795 list_del(&function->node);
796 }
797 mutex_unlock(&pcs->mutex);
798}
799
800/**
801 * pcs_free_pingroups() - free memory used by pingroups
802 * @pcs: pcs driver instance
803 */
804static void pcs_free_pingroups(struct pcs_device *pcs)
805{
806 struct list_head *pos, *tmp;
807 int i;
808
809 mutex_lock(&pcs->mutex);
810 for (i = 0; i < pcs->ngroups; i++) {
811 struct pcs_pingroup *pingroup;
812
813 pingroup = radix_tree_lookup(&pcs->pgtree, i);
814 if (!pingroup)
815 continue;
816 radix_tree_delete(&pcs->pgtree, i);
817 }
818 list_for_each_safe(pos, tmp, &pcs->pingroups) {
819 struct pcs_pingroup *pingroup;
820
821 pingroup = list_entry(pos, struct pcs_pingroup, node);
822 list_del(&pingroup->node);
823 }
824 mutex_unlock(&pcs->mutex);
825}
826
827/**
828 * pcs_free_resources() - free memory used by this driver
829 * @pcs: pcs driver instance
830 */
831static void pcs_free_resources(struct pcs_device *pcs)
832{
833 if (pcs->pctl)
834 pinctrl_unregister(pcs->pctl);
835
836 pcs_free_funcs(pcs);
837 pcs_free_pingroups(pcs);
838}
839
840#define PCS_GET_PROP_U32(name, reg, err) \
841 do { \
842 ret = of_property_read_u32(np, name, reg); \
843 if (ret) { \
844 dev_err(pcs->dev, err); \
845 return ret; \
846 } \
847 } while (0);
848
849static struct of_device_id pcs_of_match[];
850
851static int __devinit pcs_probe(struct platform_device *pdev)
852{
853 struct device_node *np = pdev->dev.of_node;
854 const struct of_device_id *match;
855 struct resource *res;
856 struct pcs_device *pcs;
857 int ret;
858
859 match = of_match_device(pcs_of_match, &pdev->dev);
860 if (!match)
861 return -EINVAL;
862
863 pcs = devm_kzalloc(&pdev->dev, sizeof(*pcs), GFP_KERNEL);
864 if (!pcs) {
865 dev_err(&pdev->dev, "could not allocate\n");
866 return -ENOMEM;
867 }
868 pcs->dev = &pdev->dev;
869 mutex_init(&pcs->mutex);
870 INIT_LIST_HEAD(&pcs->pingroups);
871 INIT_LIST_HEAD(&pcs->functions);
872
873 PCS_GET_PROP_U32("pinctrl-single,register-width", &pcs->width,
874 "register width not specified\n");
875
876 PCS_GET_PROP_U32("pinctrl-single,function-mask", &pcs->fmask,
877 "function register mask not specified\n");
878 pcs->fshift = ffs(pcs->fmask) - 1;
879 pcs->fmax = pcs->fmask >> pcs->fshift;
880
881 ret = of_property_read_u32(np, "pinctrl-single,function-off",
882 &pcs->foff);
883 if (ret)
884 pcs->foff = PCS_OFF_DISABLED;
885
886 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
887 if (!res) {
888 dev_err(pcs->dev, "could not get resource\n");
889 return -ENODEV;
890 }
891
892 pcs->res = devm_request_mem_region(pcs->dev, res->start,
893 resource_size(res), DRIVER_NAME);
894 if (!pcs->res) {
895 dev_err(pcs->dev, "could not get mem_region\n");
896 return -EBUSY;
897 }
898
899 pcs->size = resource_size(pcs->res);
900 pcs->base = devm_ioremap(pcs->dev, pcs->res->start, pcs->size);
901 if (!pcs->base) {
902 dev_err(pcs->dev, "could not ioremap\n");
903 return -ENODEV;
904 }
905
906 INIT_RADIX_TREE(&pcs->pgtree, GFP_KERNEL);
907 INIT_RADIX_TREE(&pcs->ftree, GFP_KERNEL);
908 platform_set_drvdata(pdev, pcs);
909
910 switch (pcs->width) {
911 case 8:
912 pcs->read = pcs_readb;
913 pcs->write = pcs_writeb;
914 break;
915 case 16:
916 pcs->read = pcs_readw;
917 pcs->write = pcs_writew;
918 break;
919 case 32:
920 pcs->read = pcs_readl;
921 pcs->write = pcs_writel;
922 break;
923 default:
924 break;
925 }
926
927 pcs->desc.name = DRIVER_NAME;
928 pcs->desc.pctlops = &pcs_pinctrl_ops;
929 pcs->desc.pmxops = &pcs_pinmux_ops;
930 pcs->desc.confops = &pcs_pinconf_ops;
931 pcs->desc.owner = THIS_MODULE;
932
933 ret = pcs_allocate_pin_table(pcs);
934 if (ret < 0)
935 goto free;
936
937 pcs->pctl = pinctrl_register(&pcs->desc, pcs->dev, pcs);
938 if (!pcs->pctl) {
939 dev_err(pcs->dev, "could not register single pinctrl driver\n");
940 ret = -EINVAL;
941 goto free;
942 }
943
944 dev_info(pcs->dev, "%i pins at pa %p size %u\n",
945 pcs->desc.npins, pcs->base, pcs->size);
946
947 return 0;
948
949free:
950 pcs_free_resources(pcs);
951
952 return ret;
953}
954
955static int __devexit pcs_remove(struct platform_device *pdev)
956{
957 struct pcs_device *pcs = platform_get_drvdata(pdev);
958
959 if (!pcs)
960 return 0;
961
962 pcs_free_resources(pcs);
963
964 return 0;
965}
966
967static struct of_device_id pcs_of_match[] __devinitdata = {
968 { .compatible = DRIVER_NAME, },
969 { },
970};
971MODULE_DEVICE_TABLE(of, pcs_of_match);
972
973static struct platform_driver pcs_driver = {
974 .probe = pcs_probe,
975 .remove = __devexit_p(pcs_remove),
976 .driver = {
977 .owner = THIS_MODULE,
978 .name = DRIVER_NAME,
979 .of_match_table = pcs_of_match,
980 },
981};
982
983module_platform_driver(pcs_driver);
984
985MODULE_AUTHOR("Tony Lindgren <tony@atomide.com>");
986MODULE_DESCRIPTION("One-register-per-pin type device tree based pinctrl driver");
987MODULE_LICENSE("GPL v2");
diff --git a/drivers/pinctrl/pinctrl-sirf.c b/drivers/pinctrl/pinctrl-sirf.c
index e9f8e7d11001..7fca6ce5952b 100644
--- a/drivers/pinctrl/pinctrl-sirf.c
+++ b/drivers/pinctrl/pinctrl-sirf.c
@@ -8,24 +8,61 @@
8 8
9#include <linux/init.h> 9#include <linux/init.h>
10#include <linux/module.h> 10#include <linux/module.h>
11#include <linux/irq.h>
11#include <linux/platform_device.h> 12#include <linux/platform_device.h>
12#include <linux/io.h> 13#include <linux/io.h>
13#include <linux/slab.h> 14#include <linux/slab.h>
14#include <linux/err.h> 15#include <linux/err.h>
16#include <linux/irqdomain.h>
15#include <linux/pinctrl/pinctrl.h> 17#include <linux/pinctrl/pinctrl.h>
16#include <linux/pinctrl/pinmux.h> 18#include <linux/pinctrl/pinmux.h>
19#include <linux/pinctrl/consumer.h>
17#include <linux/of.h> 20#include <linux/of.h>
18#include <linux/of_address.h> 21#include <linux/of_address.h>
19#include <linux/of_device.h> 22#include <linux/of_device.h>
20#include <linux/of_platform.h> 23#include <linux/of_platform.h>
21#include <linux/bitops.h> 24#include <linux/bitops.h>
25#include <linux/gpio.h>
26#include <linux/of_gpio.h>
22 27
23#define DRIVER_NAME "pinmux-sirf" 28#define DRIVER_NAME "pinmux-sirf"
24 29
25#define SIRFSOC_NUM_PADS 622 30#define SIRFSOC_NUM_PADS 622
26#define SIRFSOC_GPIO_PAD_EN(g) ((g)*0x100 + 0x84)
27#define SIRFSOC_RSC_PIN_MUX 0x4 31#define SIRFSOC_RSC_PIN_MUX 0x4
28 32
33#define SIRFSOC_GPIO_PAD_EN(g) ((g)*0x100 + 0x84)
34#define SIRFSOC_GPIO_CTRL(g, i) ((g)*0x100 + (i)*4)
35#define SIRFSOC_GPIO_DSP_EN0 (0x80)
36#define SIRFSOC_GPIO_PAD_EN(g) ((g)*0x100 + 0x84)
37#define SIRFSOC_GPIO_INT_STATUS(g) ((g)*0x100 + 0x8C)
38
39#define SIRFSOC_GPIO_CTL_INTR_LOW_MASK 0x1
40#define SIRFSOC_GPIO_CTL_INTR_HIGH_MASK 0x2
41#define SIRFSOC_GPIO_CTL_INTR_TYPE_MASK 0x4
42#define SIRFSOC_GPIO_CTL_INTR_EN_MASK 0x8
43#define SIRFSOC_GPIO_CTL_INTR_STS_MASK 0x10
44#define SIRFSOC_GPIO_CTL_OUT_EN_MASK 0x20
45#define SIRFSOC_GPIO_CTL_DATAOUT_MASK 0x40
46#define SIRFSOC_GPIO_CTL_DATAIN_MASK 0x80
47#define SIRFSOC_GPIO_CTL_PULL_MASK 0x100
48#define SIRFSOC_GPIO_CTL_PULL_HIGH 0x200
49#define SIRFSOC_GPIO_CTL_DSP_INT 0x400
50
51#define SIRFSOC_GPIO_NO_OF_BANKS 5
52#define SIRFSOC_GPIO_BANK_SIZE 32
53#define SIRFSOC_GPIO_NUM(bank, index) (((bank)*(32)) + (index))
54
55struct sirfsoc_gpio_bank {
56 struct of_mm_gpio_chip chip;
57 struct irq_domain *domain;
58 int id;
59 int parent_irq;
60 spinlock_t lock;
61};
62
63static struct sirfsoc_gpio_bank sgpio_bank[SIRFSOC_GPIO_NO_OF_BANKS];
64static DEFINE_SPINLOCK(sgpio_lock);
65
29/* 66/*
30 * pad list for the pinmux subsystem 67 * pad list for the pinmux subsystem
31 * refer to CS-131858-DC-6A.xls 68 * refer to CS-131858-DC-6A.xls
@@ -1180,7 +1217,6 @@ out_no_rsc_remap:
1180 iounmap(spmx->gpio_virtbase); 1217 iounmap(spmx->gpio_virtbase);
1181out_no_gpio_remap: 1218out_no_gpio_remap:
1182 platform_set_drvdata(pdev, NULL); 1219 platform_set_drvdata(pdev, NULL);
1183 devm_kfree(&pdev->dev, spmx);
1184 return ret; 1220 return ret;
1185} 1221}
1186 1222
@@ -1204,7 +1240,457 @@ static int __init sirfsoc_pinmux_init(void)
1204} 1240}
1205arch_initcall(sirfsoc_pinmux_init); 1241arch_initcall(sirfsoc_pinmux_init);
1206 1242
1243static inline int sirfsoc_gpio_to_irq(struct gpio_chip *chip, unsigned offset)
1244{
1245 struct sirfsoc_gpio_bank *bank = container_of(to_of_mm_gpio_chip(chip),
1246 struct sirfsoc_gpio_bank, chip);
1247
1248 return irq_find_mapping(bank->domain, offset);
1249}
1250
1251static inline int sirfsoc_gpio_to_offset(unsigned int gpio)
1252{
1253 return gpio % SIRFSOC_GPIO_BANK_SIZE;
1254}
1255
1256static inline struct sirfsoc_gpio_bank *sirfsoc_gpio_to_bank(unsigned int gpio)
1257{
1258 return &sgpio_bank[gpio / SIRFSOC_GPIO_BANK_SIZE];
1259}
1260
1261void sirfsoc_gpio_set_pull(unsigned gpio, unsigned mode)
1262{
1263 struct sirfsoc_gpio_bank *bank = sirfsoc_gpio_to_bank(gpio);
1264 int idx = sirfsoc_gpio_to_offset(gpio);
1265 u32 val, offset;
1266 unsigned long flags;
1267
1268 offset = SIRFSOC_GPIO_CTRL(bank->id, idx);
1269
1270 spin_lock_irqsave(&sgpio_lock, flags);
1271
1272 val = readl(bank->chip.regs + offset);
1273
1274 switch (mode) {
1275 case SIRFSOC_GPIO_PULL_NONE:
1276 val &= ~SIRFSOC_GPIO_CTL_PULL_MASK;
1277 break;
1278 case SIRFSOC_GPIO_PULL_UP:
1279 val |= SIRFSOC_GPIO_CTL_PULL_MASK;
1280 val |= SIRFSOC_GPIO_CTL_PULL_HIGH;
1281 break;
1282 case SIRFSOC_GPIO_PULL_DOWN:
1283 val |= SIRFSOC_GPIO_CTL_PULL_MASK;
1284 val &= ~SIRFSOC_GPIO_CTL_PULL_HIGH;
1285 break;
1286 default:
1287 break;
1288 }
1289
1290 writel(val, bank->chip.regs + offset);
1291
1292 spin_unlock_irqrestore(&sgpio_lock, flags);
1293}
1294EXPORT_SYMBOL(sirfsoc_gpio_set_pull);
1295
1296static inline struct sirfsoc_gpio_bank *sirfsoc_irqchip_to_bank(struct gpio_chip *chip)
1297{
1298 return container_of(to_of_mm_gpio_chip(chip), struct sirfsoc_gpio_bank, chip);
1299}
1300
1301static void sirfsoc_gpio_irq_ack(struct irq_data *d)
1302{
1303 struct sirfsoc_gpio_bank *bank = irq_data_get_irq_chip_data(d);
1304 int idx = d->hwirq % SIRFSOC_GPIO_BANK_SIZE;
1305 u32 val, offset;
1306 unsigned long flags;
1307
1308 offset = SIRFSOC_GPIO_CTRL(bank->id, idx);
1309
1310 spin_lock_irqsave(&sgpio_lock, flags);
1311
1312 val = readl(bank->chip.regs + offset);
1313
1314 writel(val, bank->chip.regs + offset);
1315
1316 spin_unlock_irqrestore(&sgpio_lock, flags);
1317}
1318
1319static void __sirfsoc_gpio_irq_mask(struct sirfsoc_gpio_bank *bank, int idx)
1320{
1321 u32 val, offset;
1322 unsigned long flags;
1323
1324 offset = SIRFSOC_GPIO_CTRL(bank->id, idx);
1325
1326 spin_lock_irqsave(&sgpio_lock, flags);
1327
1328 val = readl(bank->chip.regs + offset);
1329 val &= ~SIRFSOC_GPIO_CTL_INTR_EN_MASK;
1330 val &= ~SIRFSOC_GPIO_CTL_INTR_STS_MASK;
1331 writel(val, bank->chip.regs + offset);
1332
1333 spin_unlock_irqrestore(&sgpio_lock, flags);
1334}
1335
1336static void sirfsoc_gpio_irq_mask(struct irq_data *d)
1337{
1338 struct sirfsoc_gpio_bank *bank = irq_data_get_irq_chip_data(d);
1339
1340 __sirfsoc_gpio_irq_mask(bank, d->hwirq % SIRFSOC_GPIO_BANK_SIZE);
1341}
1342
1343static void sirfsoc_gpio_irq_unmask(struct irq_data *d)
1344{
1345 struct sirfsoc_gpio_bank *bank = irq_data_get_irq_chip_data(d);
1346 int idx = d->hwirq % SIRFSOC_GPIO_BANK_SIZE;
1347 u32 val, offset;
1348 unsigned long flags;
1349
1350 offset = SIRFSOC_GPIO_CTRL(bank->id, idx);
1351
1352 spin_lock_irqsave(&sgpio_lock, flags);
1353
1354 val = readl(bank->chip.regs + offset);
1355 val &= ~SIRFSOC_GPIO_CTL_INTR_STS_MASK;
1356 val |= SIRFSOC_GPIO_CTL_INTR_EN_MASK;
1357 writel(val, bank->chip.regs + offset);
1358
1359 spin_unlock_irqrestore(&sgpio_lock, flags);
1360}
1361
1362static int sirfsoc_gpio_irq_type(struct irq_data *d, unsigned type)
1363{
1364 struct sirfsoc_gpio_bank *bank = irq_data_get_irq_chip_data(d);
1365 int idx = d->hwirq % SIRFSOC_GPIO_BANK_SIZE;
1366 u32 val, offset;
1367 unsigned long flags;
1368
1369 offset = SIRFSOC_GPIO_CTRL(bank->id, idx);
1370
1371 spin_lock_irqsave(&sgpio_lock, flags);
1372
1373 val = readl(bank->chip.regs + offset);
1374 val &= ~SIRFSOC_GPIO_CTL_INTR_STS_MASK;
1375
1376 switch (type) {
1377 case IRQ_TYPE_NONE:
1378 break;
1379 case IRQ_TYPE_EDGE_RISING:
1380 val |= SIRFSOC_GPIO_CTL_INTR_HIGH_MASK | SIRFSOC_GPIO_CTL_INTR_TYPE_MASK;
1381 val &= ~SIRFSOC_GPIO_CTL_INTR_LOW_MASK;
1382 break;
1383 case IRQ_TYPE_EDGE_FALLING:
1384 val &= ~SIRFSOC_GPIO_CTL_INTR_HIGH_MASK;
1385 val |= SIRFSOC_GPIO_CTL_INTR_LOW_MASK | SIRFSOC_GPIO_CTL_INTR_TYPE_MASK;
1386 break;
1387 case IRQ_TYPE_EDGE_BOTH:
1388 val |= SIRFSOC_GPIO_CTL_INTR_HIGH_MASK | SIRFSOC_GPIO_CTL_INTR_LOW_MASK |
1389 SIRFSOC_GPIO_CTL_INTR_TYPE_MASK;
1390 break;
1391 case IRQ_TYPE_LEVEL_LOW:
1392 val &= ~(SIRFSOC_GPIO_CTL_INTR_HIGH_MASK | SIRFSOC_GPIO_CTL_INTR_TYPE_MASK);
1393 val |= SIRFSOC_GPIO_CTL_INTR_LOW_MASK;
1394 break;
1395 case IRQ_TYPE_LEVEL_HIGH:
1396 val |= SIRFSOC_GPIO_CTL_INTR_HIGH_MASK;
1397 val &= ~(SIRFSOC_GPIO_CTL_INTR_LOW_MASK | SIRFSOC_GPIO_CTL_INTR_TYPE_MASK);
1398 break;
1399 }
1400
1401 writel(val, bank->chip.regs + offset);
1402
1403 spin_unlock_irqrestore(&sgpio_lock, flags);
1404
1405 return 0;
1406}
1407
1408static struct irq_chip sirfsoc_irq_chip = {
1409 .name = "sirf-gpio-irq",
1410 .irq_ack = sirfsoc_gpio_irq_ack,
1411 .irq_mask = sirfsoc_gpio_irq_mask,
1412 .irq_unmask = sirfsoc_gpio_irq_unmask,
1413 .irq_set_type = sirfsoc_gpio_irq_type,
1414};
1415
1416static void sirfsoc_gpio_handle_irq(unsigned int irq, struct irq_desc *desc)
1417{
1418 struct sirfsoc_gpio_bank *bank = irq_get_handler_data(irq);
1419 u32 status, ctrl;
1420 int idx = 0;
1421 unsigned int first_irq;
1422
1423 status = readl(bank->chip.regs + SIRFSOC_GPIO_INT_STATUS(bank->id));
1424 if (!status) {
1425 printk(KERN_WARNING
1426 "%s: gpio id %d status %#x no interrupt is flaged\n",
1427 __func__, bank->id, status);
1428 handle_bad_irq(irq, desc);
1429 return;
1430 }
1431
1432 first_irq = bank->domain->revmap_data.legacy.first_irq;
1433
1434 while (status) {
1435 ctrl = readl(bank->chip.regs + SIRFSOC_GPIO_CTRL(bank->id, idx));
1436
1437 /*
1438 * Here we must check whether the corresponding GPIO's interrupt
1439 * has been enabled, otherwise just skip it
1440 */
1441 if ((status & 0x1) && (ctrl & SIRFSOC_GPIO_CTL_INTR_EN_MASK)) {
1442 pr_debug("%s: gpio id %d idx %d happens\n",
1443 __func__, bank->id, idx);
1444 generic_handle_irq(first_irq + idx);
1445 }
1446
1447 idx++;
1448 status = status >> 1;
1449 }
1450}
1451
1452static inline void sirfsoc_gpio_set_input(struct sirfsoc_gpio_bank *bank, unsigned ctrl_offset)
1453{
1454 u32 val;
1455 unsigned long flags;
1456
1457 spin_lock_irqsave(&bank->lock, flags);
1458
1459 val = readl(bank->chip.regs + ctrl_offset);
1460 val &= ~SIRFSOC_GPIO_CTL_OUT_EN_MASK;
1461 writel(val, bank->chip.regs + ctrl_offset);
1462
1463 spin_unlock_irqrestore(&bank->lock, flags);
1464}
1465
1466static int sirfsoc_gpio_request(struct gpio_chip *chip, unsigned offset)
1467{
1468 struct sirfsoc_gpio_bank *bank = sirfsoc_irqchip_to_bank(chip);
1469 unsigned long flags;
1470
1471 if (pinctrl_request_gpio(chip->base + offset))
1472 return -ENODEV;
1473
1474 spin_lock_irqsave(&bank->lock, flags);
1475
1476 /*
1477 * default status:
1478 * set direction as input and mask irq
1479 */
1480 sirfsoc_gpio_set_input(bank, SIRFSOC_GPIO_CTRL(bank->id, offset));
1481 __sirfsoc_gpio_irq_mask(bank, offset);
1482
1483 spin_unlock_irqrestore(&bank->lock, flags);
1484
1485 return 0;
1486}
1487
1488static void sirfsoc_gpio_free(struct gpio_chip *chip, unsigned offset)
1489{
1490 struct sirfsoc_gpio_bank *bank = sirfsoc_irqchip_to_bank(chip);
1491 unsigned long flags;
1492
1493 spin_lock_irqsave(&bank->lock, flags);
1494
1495 __sirfsoc_gpio_irq_mask(bank, offset);
1496 sirfsoc_gpio_set_input(bank, SIRFSOC_GPIO_CTRL(bank->id, offset));
1497
1498 spin_unlock_irqrestore(&bank->lock, flags);
1499
1500 pinctrl_free_gpio(chip->base + offset);
1501}
1502
1503static int sirfsoc_gpio_direction_input(struct gpio_chip *chip, unsigned gpio)
1504{
1505 struct sirfsoc_gpio_bank *bank = sirfsoc_irqchip_to_bank(chip);
1506 int idx = sirfsoc_gpio_to_offset(gpio);
1507 unsigned long flags;
1508 unsigned offset;
1509
1510 offset = SIRFSOC_GPIO_CTRL(bank->id, idx);
1511
1512 spin_lock_irqsave(&bank->lock, flags);
1513
1514 sirfsoc_gpio_set_input(bank, offset);
1515
1516 spin_unlock_irqrestore(&bank->lock, flags);
1517
1518 return 0;
1519}
1520
1521static inline void sirfsoc_gpio_set_output(struct sirfsoc_gpio_bank *bank, unsigned offset,
1522 int value)
1523{
1524 u32 out_ctrl;
1525 unsigned long flags;
1526
1527 spin_lock_irqsave(&bank->lock, flags);
1528
1529 out_ctrl = readl(bank->chip.regs + offset);
1530 if (value)
1531 out_ctrl |= SIRFSOC_GPIO_CTL_DATAOUT_MASK;
1532 else
1533 out_ctrl &= ~SIRFSOC_GPIO_CTL_DATAOUT_MASK;
1534
1535 out_ctrl &= ~SIRFSOC_GPIO_CTL_INTR_EN_MASK;
1536 out_ctrl |= SIRFSOC_GPIO_CTL_OUT_EN_MASK;
1537 writel(out_ctrl, bank->chip.regs + offset);
1538
1539 spin_unlock_irqrestore(&bank->lock, flags);
1540}
1541
1542static int sirfsoc_gpio_direction_output(struct gpio_chip *chip, unsigned gpio, int value)
1543{
1544 struct sirfsoc_gpio_bank *bank = sirfsoc_irqchip_to_bank(chip);
1545 int idx = sirfsoc_gpio_to_offset(gpio);
1546 u32 offset;
1547 unsigned long flags;
1548
1549 offset = SIRFSOC_GPIO_CTRL(bank->id, idx);
1550
1551 spin_lock_irqsave(&sgpio_lock, flags);
1552
1553 sirfsoc_gpio_set_output(bank, offset, value);
1554
1555 spin_unlock_irqrestore(&sgpio_lock, flags);
1556
1557 return 0;
1558}
1559
1560static int sirfsoc_gpio_get_value(struct gpio_chip *chip, unsigned offset)
1561{
1562 struct sirfsoc_gpio_bank *bank = sirfsoc_irqchip_to_bank(chip);
1563 u32 val;
1564 unsigned long flags;
1565
1566 spin_lock_irqsave(&bank->lock, flags);
1567
1568 val = readl(bank->chip.regs + SIRFSOC_GPIO_CTRL(bank->id, offset));
1569
1570 spin_unlock_irqrestore(&bank->lock, flags);
1571
1572 return !!(val & SIRFSOC_GPIO_CTL_DATAIN_MASK);
1573}
1574
1575static void sirfsoc_gpio_set_value(struct gpio_chip *chip, unsigned offset,
1576 int value)
1577{
1578 struct sirfsoc_gpio_bank *bank = sirfsoc_irqchip_to_bank(chip);
1579 u32 ctrl;
1580 unsigned long flags;
1581
1582 spin_lock_irqsave(&bank->lock, flags);
1583
1584 ctrl = readl(bank->chip.regs + SIRFSOC_GPIO_CTRL(bank->id, offset));
1585 if (value)
1586 ctrl |= SIRFSOC_GPIO_CTL_DATAOUT_MASK;
1587 else
1588 ctrl &= ~SIRFSOC_GPIO_CTL_DATAOUT_MASK;
1589 writel(ctrl, bank->chip.regs + SIRFSOC_GPIO_CTRL(bank->id, offset));
1590
1591 spin_unlock_irqrestore(&bank->lock, flags);
1592}
1593
1594int sirfsoc_gpio_irq_map(struct irq_domain *d, unsigned int irq,
1595 irq_hw_number_t hwirq)
1596{
1597 struct sirfsoc_gpio_bank *bank = d->host_data;
1598
1599 if (!bank)
1600 return -EINVAL;
1601
1602 irq_set_chip(irq, &sirfsoc_irq_chip);
1603 irq_set_handler(irq, handle_level_irq);
1604 irq_set_chip_data(irq, bank);
1605 set_irq_flags(irq, IRQF_VALID);
1606
1607 return 0;
1608}
1609
1610const struct irq_domain_ops sirfsoc_gpio_irq_simple_ops = {
1611 .map = sirfsoc_gpio_irq_map,
1612 .xlate = irq_domain_xlate_twocell,
1613};
1614
1615static int __devinit sirfsoc_gpio_probe(struct device_node *np)
1616{
1617 int i, err = 0;
1618 struct sirfsoc_gpio_bank *bank;
1619 void *regs;
1620 struct platform_device *pdev;
1621
1622 pdev = of_find_device_by_node(np);
1623 if (!pdev)
1624 return -ENODEV;
1625
1626 regs = of_iomap(np, 0);
1627 if (!regs)
1628 return -ENOMEM;
1629
1630 for (i = 0; i < SIRFSOC_GPIO_NO_OF_BANKS; i++) {
1631 bank = &sgpio_bank[i];
1632 spin_lock_init(&bank->lock);
1633 bank->chip.gc.request = sirfsoc_gpio_request;
1634 bank->chip.gc.free = sirfsoc_gpio_free;
1635 bank->chip.gc.direction_input = sirfsoc_gpio_direction_input;
1636 bank->chip.gc.get = sirfsoc_gpio_get_value;
1637 bank->chip.gc.direction_output = sirfsoc_gpio_direction_output;
1638 bank->chip.gc.set = sirfsoc_gpio_set_value;
1639 bank->chip.gc.to_irq = sirfsoc_gpio_to_irq;
1640 bank->chip.gc.base = i * SIRFSOC_GPIO_BANK_SIZE;
1641 bank->chip.gc.ngpio = SIRFSOC_GPIO_BANK_SIZE;
1642 bank->chip.gc.label = kstrdup(np->full_name, GFP_KERNEL);
1643 bank->chip.gc.of_node = np;
1644 bank->chip.regs = regs;
1645 bank->id = i;
1646 bank->parent_irq = platform_get_irq(pdev, i);
1647 if (bank->parent_irq < 0) {
1648 err = bank->parent_irq;
1649 goto out;
1650 }
1651
1652 err = gpiochip_add(&bank->chip.gc);
1653 if (err) {
1654 pr_err("%s: error in probe function with status %d\n",
1655 np->full_name, err);
1656 goto out;
1657 }
1658
1659 bank->domain = irq_domain_add_legacy(np, SIRFSOC_GPIO_BANK_SIZE,
1660 SIRFSOC_GPIO_IRQ_START + i * SIRFSOC_GPIO_BANK_SIZE, 0,
1661 &sirfsoc_gpio_irq_simple_ops, bank);
1662
1663 if (!bank->domain) {
1664 pr_err("%s: Failed to create irqdomain\n", np->full_name);
1665 err = -ENOSYS;
1666 goto out;
1667 }
1668
1669 irq_set_chained_handler(bank->parent_irq, sirfsoc_gpio_handle_irq);
1670 irq_set_handler_data(bank->parent_irq, bank);
1671 }
1672
1673out:
1674 iounmap(regs);
1675 return err;
1676}
1677
1678static int __init sirfsoc_gpio_init(void)
1679{
1680
1681 struct device_node *np;
1682
1683 np = of_find_matching_node(NULL, pinmux_ids);
1684
1685 if (!np)
1686 return -ENODEV;
1687
1688 return sirfsoc_gpio_probe(np);
1689}
1690subsys_initcall(sirfsoc_gpio_init);
1691
1207MODULE_AUTHOR("Rongjun Ying <rongjun.ying@csr.com>, " 1692MODULE_AUTHOR("Rongjun Ying <rongjun.ying@csr.com>, "
1693 "Yuping Luo <yuping.luo@csr.com>, "
1208 "Barry Song <baohua.song@csr.com>"); 1694 "Barry Song <baohua.song@csr.com>");
1209MODULE_DESCRIPTION("SIRFSOC pin control driver"); 1695MODULE_DESCRIPTION("SIRFSOC pin control driver");
1210MODULE_LICENSE("GPL"); 1696MODULE_LICENSE("GPL");
diff --git a/drivers/pinctrl/pinctrl-tegra.c b/drivers/pinctrl/pinctrl-tegra.c
index b6934867d8d3..ae52e4e5d098 100644
--- a/drivers/pinctrl/pinctrl-tegra.c
+++ b/drivers/pinctrl/pinctrl-tegra.c
@@ -745,9 +745,9 @@ int __devinit tegra_pinctrl_probe(struct platform_device *pdev,
745 } 745 }
746 746
747 pmx->pctl = pinctrl_register(&tegra_pinctrl_desc, &pdev->dev, pmx); 747 pmx->pctl = pinctrl_register(&tegra_pinctrl_desc, &pdev->dev, pmx);
748 if (IS_ERR(pmx->pctl)) { 748 if (!pmx->pctl) {
749 dev_err(&pdev->dev, "Couldn't register pinctrl driver\n"); 749 dev_err(&pdev->dev, "Couldn't register pinctrl driver\n");
750 return PTR_ERR(pmx->pctl); 750 return -ENODEV;
751 } 751 }
752 752
753 pinctrl_add_gpio_range(pmx->pctl, &tegra_pinctrl_gpio_range); 753 pinctrl_add_gpio_range(pmx->pctl, &tegra_pinctrl_gpio_range);
@@ -764,7 +764,6 @@ int __devexit tegra_pinctrl_remove(struct platform_device *pdev)
764{ 764{
765 struct tegra_pmx *pmx = platform_get_drvdata(pdev); 765 struct tegra_pmx *pmx = platform_get_drvdata(pdev);
766 766
767 pinctrl_remove_gpio_range(pmx->pctl, &tegra_pinctrl_gpio_range);
768 pinctrl_unregister(pmx->pctl); 767 pinctrl_unregister(pmx->pctl);
769 768
770 return 0; 769 return 0;
diff --git a/drivers/pinctrl/pinctrl-u300.c b/drivers/pinctrl/pinctrl-u300.c
index 05d029911be6..309f5b9a70ec 100644
--- a/drivers/pinctrl/pinctrl-u300.c
+++ b/drivers/pinctrl/pinctrl-u300.c
@@ -1113,8 +1113,6 @@ static int __devinit u300_pmx_probe(struct platform_device *pdev)
1113 int ret; 1113 int ret;
1114 int i; 1114 int i;
1115 1115
1116 pr_err("U300 PMX PROBE\n");
1117
1118 /* Create state holders etc for this driver */ 1116 /* Create state holders etc for this driver */
1119 upmx = devm_kzalloc(&pdev->dev, sizeof(*upmx), GFP_KERNEL); 1117 upmx = devm_kzalloc(&pdev->dev, sizeof(*upmx), GFP_KERNEL);
1120 if (!upmx) 1118 if (!upmx)
@@ -1123,10 +1121,8 @@ static int __devinit u300_pmx_probe(struct platform_device *pdev)
1123 upmx->dev = &pdev->dev; 1121 upmx->dev = &pdev->dev;
1124 1122
1125 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1123 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1126 if (!res) { 1124 if (!res)
1127 ret = -ENOENT; 1125 return -ENOENT;
1128 goto out_no_resource;
1129 }
1130 upmx->phybase = res->start; 1126 upmx->phybase = res->start;
1131 upmx->physize = resource_size(res); 1127 upmx->physize = resource_size(res);
1132 1128
@@ -1167,23 +1163,17 @@ out_no_remap:
1167 platform_set_drvdata(pdev, NULL); 1163 platform_set_drvdata(pdev, NULL);
1168out_no_memregion: 1164out_no_memregion:
1169 release_mem_region(upmx->phybase, upmx->physize); 1165 release_mem_region(upmx->phybase, upmx->physize);
1170out_no_resource:
1171 devm_kfree(&pdev->dev, upmx);
1172 return ret; 1166 return ret;
1173} 1167}
1174 1168
1175static int __devexit u300_pmx_remove(struct platform_device *pdev) 1169static int __devexit u300_pmx_remove(struct platform_device *pdev)
1176{ 1170{
1177 struct u300_pmx *upmx = platform_get_drvdata(pdev); 1171 struct u300_pmx *upmx = platform_get_drvdata(pdev);
1178 int i;
1179 1172
1180 for (i = 0; i < ARRAY_SIZE(u300_gpio_ranges); i++)
1181 pinctrl_remove_gpio_range(upmx->pctl, &u300_gpio_ranges[i]);
1182 pinctrl_unregister(upmx->pctl); 1173 pinctrl_unregister(upmx->pctl);
1183 iounmap(upmx->virtbase); 1174 iounmap(upmx->virtbase);
1184 release_mem_region(upmx->phybase, upmx->physize); 1175 release_mem_region(upmx->phybase, upmx->physize);
1185 platform_set_drvdata(pdev, NULL); 1176 platform_set_drvdata(pdev, NULL);
1186 devm_kfree(&pdev->dev, upmx);
1187 1177
1188 return 0; 1178 return 0;
1189} 1179}
diff --git a/drivers/pinctrl/spear/pinctrl-spear.c b/drivers/pinctrl/spear/pinctrl-spear.c
index b3f6b2873fdd..5d4f44f462f0 100644
--- a/drivers/pinctrl/spear/pinctrl-spear.c
+++ b/drivers/pinctrl/spear/pinctrl-spear.c
@@ -336,9 +336,9 @@ int __devinit spear_pinctrl_probe(struct platform_device *pdev,
336 spear_pinctrl_desc.npins = machdata->npins; 336 spear_pinctrl_desc.npins = machdata->npins;
337 337
338 pmx->pctl = pinctrl_register(&spear_pinctrl_desc, &pdev->dev, pmx); 338 pmx->pctl = pinctrl_register(&spear_pinctrl_desc, &pdev->dev, pmx);
339 if (IS_ERR(pmx->pctl)) { 339 if (!pmx->pctl) {
340 dev_err(&pdev->dev, "Couldn't register pinctrl driver\n"); 340 dev_err(&pdev->dev, "Couldn't register pinctrl driver\n");
341 return PTR_ERR(pmx->pctl); 341 return -ENODEV;
342 } 342 }
343 343
344 return 0; 344 return 0;
generated by cgit v1.2.2 (git 2.25.0) at 2025-01-29 03:50:09 -0500